diff options
| author | Daniel Hellstrom <daniel@gaisler.com> | 2014-12-03 11:35:52 +0100 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-12-04 12:51:11 +0100 |
| commit | dff1803cfbec3775fff1b9c34cc707c05494dc3b (patch) | |
| tree | dbb8850d94b30f8388f9e3df9a68fc6c99855f74 /cpukit/score/cpu/sparc | |
| parent | pc386 bsp fix for default mode (diff) | |
| download | rtems-dff1803cfbec3775fff1b9c34cc707c05494dc3b.tar.bz2 | |
SPARC: optimize IRQ enable & disable
* Coding style cleanups.
* Use OS reserved trap 0x89 for IRQ Disable
* Use OS reserved trap 0x8A for IRQ Enable
* Add to SPARC CPU supplement documentation
This will result in faster Disable/Enable code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.
It was also possible to reduce the interrupt trap handler by
five instructions due to this.
Diffstat (limited to 'cpukit/score/cpu/sparc')
| -rw-r--r-- | cpukit/score/cpu/sparc/rtems/score/sparc.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h b/cpukit/score/cpu/sparc/rtems/score/sparc.h index abd0f8b987..ac8c510e46 100644 --- a/cpukit/score/cpu/sparc/rtems/score/sparc.h +++ b/cpukit/score/cpu/sparc/rtems/score/sparc.h @@ -149,6 +149,11 @@ extern "C" { #define LEON3_ASR17_PROCESSOR_INDEX_SHIFT 28 +/* SPARC Software Trap number definitions */ +#define SPARC_SWTRAP_SYSCALL 0 +#define SPARC_SWTRAP_IRQDIS 9 +#define SPARC_SWTRAP_IRQEN 10 + #ifndef ASM /** @@ -298,7 +303,12 @@ void _SPARC_Set_TBR( uint32_t new_tbr ); * * @return This method returns the entire PSR contents. */ -uint32_t sparc_disable_interrupts(void); +static inline uint32_t sparc_disable_interrupts(void) +{ + register uint32_t psr __asm__("g1"); /* return value of trap handler */ + __asm__ volatile ( "ta %1\n\t" : "=r" (psr) : "i" (SPARC_SWTRAP_IRQDIS)); + return psr; +} /** * @brief SPARC enable processor interrupts. @@ -307,7 +317,11 @@ uint32_t sparc_disable_interrupts(void); * * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts. */ -void sparc_enable_interrupts(uint32_t psr); +static inline void sparc_enable_interrupts(uint32_t psr) +{ + register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */ + __asm__ volatile ( "ta %0\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr)); +} /** * @brief SPARC exit through system call 1 |