diff options
| author | Daniel Cederman <cederman@gaisler.com> | 2015-11-16 14:13:28 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-11-16 14:48:54 +0100 |
| commit | 78cac9b092db0fa380ae7f7206d6c00e513ef9b9 (patch) | |
| tree | 68bc4fc09a948d0015c937d886d3358db3e3fa3a /cpukit/score/cpu/sparc | |
| parent | Update config.guess and config.sub (diff) | |
| download | rtems-78cac9b092db0fa380ae7f7206d6c00e513ef9b9.tar.bz2 | |
sparc: Fix context switch on SMP
We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
Diffstat (limited to 'cpukit/score/cpu/sparc')
| -rw-r--r-- | cpukit/score/cpu/sparc/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index 569b6f8ec8..5434355618 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -356,6 +356,9 @@ void _CPU_Context_Initialize( tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ + /* _CPU_Context_restore_heir() relies on this */ + _Assert( ( tmp_psr & SPARC_PSR_ET_MASK ) != 0 ); + #if (SPARC_HAS_FPU == 1) /* * If this bit is not set, then a task gets a fault when it accesses |