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* build: Remove old build systemSebastian Huber2021-09-211-14/+0
| | | | | Close #3250. Close #4081.
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-283-15/+20
| | | | | | | | Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it is a proper declaration of a function which does not return. Fix the type of the error code. If necessary, add the implementation to cpu.c. Implementing _CPU_Fatal_halt() as a function makes it possible to wrap this function for example to fully test _Terminate().
* score: Remove processor event broadcast/receiveSebastian Huber2021-07-281-12/+0
| | | | | | Remove _CPU_SMP_Processor_event_broadcast() and _CPU_SMP_Processor_event_receive(). These functions are hard to use since they are subject to the lost wake up problem.
* arm: For AArch32 use non-shareable memorySebastian Huber2021-06-291-2/+2
| | | | | | | | The Cortex-R52 does not support cache coherency and the shareable memory attribute. If a region is configured to be shareable, then it falls back to use non-cacheable memory. Update #4202.
* arm: Fix AARCH32_PMSA_ATTR_XN valueSebastian Huber2021-06-291-1/+1
| | | | Update #4202.
* arm: Fix AArch32 memory attribute definesSebastian Huber2021-06-291-4/+4
| | | | Update #4202.
* arm: Disable alignment check in PMSA initSebastian Huber2021-06-291-1/+1
| | | | | | | Disable the alignment check through SCTLR[A] in _AArch32_PMSA_Initialize(). Update #4202.
* cpu/armv7m: Fix initialization of MPU regionsChristian Mauderer2021-06-211-1/+1
| | | | | | | | | | | The write to RBAR didn't have the valid flag set. Therefore the write to RASR had an influence on the previously set region. That means for example that if Region 0 had been enabled but 1 should be disabled due to a size of 0, the previous code would have disabled region 0 instead. This patch fixes that behaviour. Close #4450
* cpu/armv7m: Avoid regions with negative sizeChristian Mauderer2021-06-211-1/+1
| | | | | | | Don't initialze regions that have a negative size (for example due to a wrong calculation). Update #4450
* arm: Fix parameter use in AARCH32_PMSA_MEM_ATTR()Sebastian Huber2021-06-161-1/+1
| | | | Update #4202.
* score: Add _CPU_Context_switch_no_return()Sebastian Huber2021-05-182-0/+8
| | | | | | | | | | | The __builtin_unreachable() cannot be used with current GCC versions to tell the compiler that a function does not return to the caller, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99151 Add a no return variant of _CPU_Context_switch() to avoid generation of dead code in _Thread_Start_multitasking() if RTEMS was built with SMP support enabled.
* Update header.amSebastian Huber2020-12-231-0/+2
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* arm: Add support for Arm PMSAv8-32Sebastian Huber2020-12-223-0/+568
| | | | Update #4202.
* arm: Add header file for AArch32 System RegistersSebastian Huber2020-12-221-0/+14657
| | | | Update #4202.
* arm: Optimize arm_interrupt_disable()Sebastian Huber2020-12-161-2/+11
| | | | Update #4202.
* cpu/armv7m: Fix table based init for ARMV7M_MPUChristian Mauderer2020-12-141-1/+7
| | | | | | | | Somehow the table index has been missing in the latest patch version. With that, the configuration for the first region has been applied multiple times. Update #4180
* arm: Support Armv8 in <rtems/score/arm.h>Sebastian Huber2020-12-101-11/+10
| | | | Update #4202.
* cpu/armv7m: Add table based init for ARMV7M_MPUChristian Mauderer2020-11-201-0/+103
| | | | | | | Modify the MPU functions of the stm32h7 BSP to be table based and available for all ARMV7M BSPs. Update #4180
* bsps/arm: Workaround for Errata 845369Sebastian Huber2020-10-161-0/+32
| | | | | | | Add a workaround for Cortex-A9 Errata 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption. Update #4115.
* rtems: Improve RTEMS_NO_RETURN attributeSebastian Huber2020-10-101-4/+2
| | | | | | | | | | | Provide RTEMS_NO_RETURN also in case RTEMS_DEBUG is defined to prevent errors like this: error: no return statement in function returning non-void [-Werror=return-type] Use C11 and C++11 standard means to declare a no-return function. Close #4122.
* arm: Fix arm_cp15_set_translation_table_entries()Sebastian Huber2020-09-171-0/+16
| | | | | | | | In a multi-processor system we must broadcast the TLB maintenance operation to the Inner Shareable domain to ensure that the other processors update their TLB caches accordingly. Close #4068.
* score: Add CPU_USE_LIBC_INIT_FINI_ARRAYKinsey Moore2020-06-301-0/+2
| | | | | | | | This introduces the CPU_USE_LIBC_INIT_FINI_ARRAY define for use by CPU ports to determine which global constructor and destructor methods are used instead of placing architecture defines where they shouldn't be. Close #4018
* arm: Fix ARMv7-M exception handlerSebastian Huber2020-05-271-8/+15
| | | | | | Store the stack pointer of the exception context to the exception frame. Close #3987.
* Canonicalize config.h includeSebastian Huber2020-04-1623-23/+23
| | | | | | | | Use the following variant which was already used by most source files: #ifdef HAVE_CONFIG_H #include "config.h" #endif
* arm: ARMv7-M statically initialized vector tableSebastian Huber2020-04-032-16/+30
| | | | | | | Statically initialize the ARMv7-M vector table to allow a placement in ROM with read-only MPU settings. Change licence to BSD-2-Clause in some files.
* score: Remove superfluous FP types/definesSebastian Huber2020-02-121-6/+0
| | | | Update #3835.
* arm: Add defines for small pages MMUSebastian Huber2019-10-311-0/+57
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* arm: Fix default exception handlerSebastian Huber2019-09-031-2/+2
| | | | Keep the stack pointer properly 8-byte aligned.
* arm: Return the current handler from arm_cp15_set_exception_handlerChris Johns2019-06-281-1/+6
| | | | Closes #3762
* doxygen: score: Put ARM Co-Processor 15 group in ARMAndreas Dachsberger2019-04-021-3/+3
| | | | Update #3706.
* score: Add ARM CPU architecture groupSebastian Huber2019-03-2610-52/+32
| | | | Update #3706.
* score: Rename ScoreCPU Doxygen groupSebastian Huber2019-03-268-10/+10
| | | | Update #3706.
* Remove superfluous <rtems/system.h> includesSebastian Huber2019-03-142-2/+0
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* cpukit/arm: Correct register definitionJonathan Brandmeyer2019-03-081-2/+2
| | | | | | | | | | | | | | The register definition for the CP15 PMCR (performance monitor control register) has the bits for X (export enable) and D (clock divider enable) backwards. Correct them according to ARMv7-A/R Architecture Reference Manual, Rev C, Section B4.1.117. Consequences: On an implementation that starts off with D set at reset, the clock divider will not be disabled by using RTEMS' definition of the D bit. Tested by using the counter on Xilinx Zynq 7020 to measure some atomic accesses and cache flushing operations.
* bsps/arm: Fix system register for virtual timerKinsey Moore2019-02-221-1/+1
| | | | | | | | | The system register in use for retrieval of the virtual timer value was mistakenly copied from the physical timer value retrieval function. Virtual timer value retrieval should use the same system register as the virtual timer value setter. Close #3699.
* libdl: Fix the support for constructors and desctructors.Chris Johns2019-02-091-20/+52
| | | | | | | - Fix the handling of pending objects. - Add a constructor flags in objects to track then being called. Closes #2921
* arm: Remove use of proc_ptrSebastian Huber2018-11-123-14/+16
| | | | Update #3585.
* build: Include header.am in cpukit/Makefile.amSebastian Huber2018-10-102-24/+11
| | | | | Include all cpukit/*/header.am files in cpukit/Makefile.am. This gets rid of all subtree Makefile.am and the sudirs hack.
* build: Merge score/cpu/*/Makefile.amSebastian Huber2018-10-101-34/+0
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* build: Remove specialized CPPFLAGSSebastian Huber2018-10-091-1/+0
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* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-052-12/+4
| | | | | | | Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-3/+0
| | | | | | | | | | | | | | Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
| | | | | | | | On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
| | | | | This helps to reduce the use of architecture-specific defines throughout the code base.
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
| | | | | | | The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
* Rework initialization and interrupt stack supportSebastian Huber2018-06-271-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
* score: Add CPU_INTERRUPT_STACK_ALIGNMENTSebastian Huber2018-06-271-0/+2
| | | | | | | Add CPU port define for the interrupt stack alignment. The alignment should take the stack ABI and the cache line size into account. Update #3459.
* arm: Simplify CPU counter supportSebastian Huber2018-06-151-2/+5
| | | | | | | | | | Use the standard ARMv7-M systick module for the ARMv7-M CPU counter instead of DWT counter since the DWT counter is affected by power saving states. Use an inline function for _CPU_Counter_difference() for all ARM BSPs. Update #3456.
* Add _CPU_Counter_frequency()Sebastian Huber2018-06-151-0/+2
| | | | | | | | | | Add rtems_counter_frequency() API function. Use it to initialize the counter value converter via the new system initialization step (RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation and the counter converter. It avoids an unnecessary pull in of the 64-bit integer division from libgcc. Update #3456.
* Drop executable permissions on .[ch] filesJoel Sherrill2018-04-301-0/+0
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