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authorSebastian Huber <sebastian.huber@embedded-brains.de>2019-10-28 09:15:58 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2019-10-31 09:45:46 +0100
commit3fb72b0f1ea00eb29320416ed3c74943e033db30 (patch)
treece6e1c36aff2446982dd55f37f951febd466451d /cpukit/score/cpu/arm
parentbsps/riscv: UART - Read reg-shift from DTB to properly set/get registers (diff)
downloadrtems-3fb72b0f1ea00eb29320416ed3c74943e033db30.tar.bz2
arm: Add defines for small pages MMU
Diffstat (limited to 'cpukit/score/cpu/arm')
-rw-r--r--cpukit/score/cpu/arm/include/libcpu/arm-cp15.h57
1 files changed, 57 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
index 6e66b15b07..8d43ca0ac2 100644
--- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
+++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
@@ -92,9 +92,66 @@ extern "C" {
((1U << ARM_MMU_SECT_BASE_SHIFT) \
+ ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U)))
+#define ARM_MMU_PAGE_TABLE_BASE_SHIFT 10
+#define ARM_MMU_PAGE_TABLE_BASE_MASK (0x3fffffU << ARM_MMU_PAGE_TABLE_BASE_SHIFT)
+#define ARM_MMU_PAGE_TABLE_DOMAIN_SHIFT 5
+#define ARM_MMU_PAGE_TABLE_DOMAIN_MASK (0xfU << ARM_MMU_PAGE_TABLE_DOMAIN_SHIFT)
+#define ARM_MMU_PAGE_TABLE_NS (1U << 3)
+#define ARM_MMU_PAGE_TABLE_PXN (1U << 2)
+#define ARM_MMU_PAGE_TABLE_DEFAULT 0x1U
+
+#define ARM_MMU_SMALL_PAGE_BASE_SHIFT 12
+#define ARM_MMU_SMALL_PAGE_BASE_MASK (0xfffffU << ARM_MMU_SMALL_PAGE_BASE_SHIFT)
+#define ARM_MMU_SMALL_PAGE_NG (1U << 11)
+#define ARM_MMU_SMALL_PAGE_S (1U << 10)
+#define ARM_MMU_SMALL_PAGE_AP_2 (1U << 9)
+#define ARM_MMU_SMALL_PAGE_TEX_2 (1U << 8)
+#define ARM_MMU_SMALL_PAGE_TEX_1 (1U << 7)
+#define ARM_MMU_SMALL_PAGE_TEX_0 (1U << 6)
+#define ARM_MMU_SMALL_PAGE_TEX_SHIFT 6
+#define ARM_MMU_SMALL_PAGE_TEX_MASK (0x3U << ARM_MMU_SMALL_PAGE_TEX_SHIFT)
+#define ARM_MMU_SMALL_PAGE_AP_1 (1U << 5)
+#define ARM_MMU_SMALL_PAGE_AP_0 (1U << 4)
+#define ARM_MMU_SMALL_PAGE_AP_SHIFT 4
+#define ARM_MMU_SMALL_PAGE_AP_MASK (0x23U << ARM_MMU_SMALL_PAGE_AP_SHIFT)
+#define ARM_MMU_SMALL_PAGE_C (1U << 3)
+#define ARM_MMU_SMALL_PAGE_B (1U << 2)
+#define ARM_MMU_SMALL_PAGE_XN (1U << 0)
+#define ARM_MMU_SMALL_PAGE_DEFAULT 0x2U
+#define ARM_MMU_SMALL_PAGE_GET_INDEX(mva) \
+ (((uint32_t) (mva)) >> ARM_MMU_SMALL_PAGE_BASE_SHIFT)
+#define ARM_MMU_SMALL_PAGE_MVA_ALIGN_UP(mva) \
+ ((1U << ARM_MMU_SMALL_PAGE_BASE_SHIFT) \
+ + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SMALL_PAGE_BASE_SHIFT) - 1U)))
+
+#define ARM_MMU_SECT_FLAGS_TO_PAGE_TABLE(flags) \
+ (ARM_MMU_PAGE_TABLE_DEFAULT \
+ | ((flags) & ARM_MMU_SECT_DOMAIN_MASK) \
+ | (((flags) & ARM_MMU_SECT_NS) >> 16) \
+ | (((flags) & ARM_MMU_SECT_PXN) << 2))
+
+#define ARM_MMU_PAGE_TABLE_FLAGS_TO_SECT(flags) \
+ (ARM_MMU_SECT_DEFAULT \
+ | ((flags) & ARM_MMU_PAGE_TABLE_DOMAIN_MASK) \
+ | (((flags) & ARM_MMU_PAGE_TABLE_NS) << 16) \
+ | (((flags) & ARM_MMU_PAGE_TABLE_PXN) >> 2))
+
+#define ARM_MMU_SECT_FLAGS_TO_SMALL_PAGE(flags) \
+ ((((flags) & 0x3fc00) >> 6) \
+ | ((flags) & (ARM_MMU_SECT_C | ARM_MMU_SECT_B | 0x2)) \
+ | (((flags) & ARM_MMU_SECT_XN) >> 4))
+
+#define ARM_MMU_SMALL_PAGE_FLAGS_TO_SECT(flags) \
+ ((((flags) & 0xff0) << 6) \
+ | ((flags) & (ARM_MMU_SMALL_PAGE_C | ARM_MMU_SMALL_PAGE_B | 0x2)) \
+ | (((flags) & ARM_MMU_SMALL_PAGE_XN) << 4))
+
#define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U
#define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U
+#define ARM_MMU_SMALL_PAGE_TABLE_ENTRY_SIZE 4U
+#define ARM_MMU_SMALL_PAGE_TABLE_ENTRY_COUNT 256U
+
#define ARM_MMU_DEFAULT_CLIENT_DOMAIN 15U
#define ARMV7_MMU_READ_ONLY \