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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-09-04 20:10:57 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-09-17 08:20:35 +0200 |
| commit | 20d82377a679e5207328943ff5d1b3ad253d1feb (patch) | |
| tree | 469e746e617aebf76f9e38bf5702caffe00b0a65 /cpukit/score/cpu/arm | |
| parent | build: Fix multiple defintion error for i386/pc386 (diff) | |
| download | rtems-20d82377a679e5207328943ff5d1b3ad253d1feb.tar.bz2 | |
arm: Fix arm_cp15_set_translation_table_entries()
In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close #4068.
Diffstat (limited to 'cpukit/score/cpu/arm')
| -rw-r--r-- | cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h index 8d43ca0ac2..6097d60ba6 100644 --- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h +++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h @@ -647,6 +647,22 @@ arm_cp15_tlb_invalidate_entry_all_asids(const void *mva) } ARM_CP15_TEXT_SECTION static inline void +arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(const void *mva) +{ + ARM_SWITCH_REGISTERS; + + mva = ARM_CP15_TLB_PREPARE_MVA(mva); + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 0, %[mva], c8, c3, 3\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [mva] "r" (mva) + ); +} + +ARM_CP15_TEXT_SECTION static inline void arm_cp15_tlb_instruction_invalidate(void) { ARM_SWITCH_REGISTERS; |