summaryrefslogtreecommitdiffstats
path: root/c/src/lib/libcpu/i386/cpu.h (follow)
Commit message (Collapse)AuthorAgeFilesLines
* i386: refactor libcpu/cpu.h into rtems/score/i386.hJoel Sherrill2016-03-031-475/+0
| | | | Fixes #2515.
* basdefs.h: Add and use RTEMS_PACKEDSebastian Huber2015-10-261-1/+1
|
* i386: doxygen and comments related to VESA real mode framebufferJan Dolezal2014-12-041-28/+37
|
* i386: global descriptor table manipulation functionsJan Dolezal2014-11-201-4/+87
|
* i386: GDTR manipulation functions parameters changed to use explicit width typesJan Dolezal2014-11-201-2/+4
|
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
|
* Remove All CVS Id Strings Possible Using a ScriptJoel Sherrill2012-05-111-2/+0
| | | | | | | | | | | | Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
* 2011-03-14 Joel Sherrill <joel.sherrill@oarcorp.com>Joel Sherrill2011-03-141-8/+8
| | | | * cpu.h: Remove warnings.
* 2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>Ralf Corsepius2011-02-111-18/+18
| | | | | * cache.c, cpu.h, cpuModel.h: Use "__asm__" instead of "asm" for improved c99-compliance.
* 2011-01-28 Joel Sherrill <joel.sherrilL@OARcorp.com>Joel Sherrill2011-01-281-1/+1
| | | | | * byteorder.h, cpu.h, page.c: Fix typo where license said found in found in.
* Whitespace removal.Ralf Corsepius2009-12-041-10/+10
|
* Remove stray white spaces.Ralf Corsepius2004-04-151-1/+0
|
* 2003-09-04 Joel Sherrill <joel@OARcorp.com>Joel Sherrill2003-09-041-1/+1
| | | | | * cpu.c, cpu.h, cpuModel.S, cpuModel.h, displayCpu.c, idtr.S, page.c: URL for license changed.
* 2002-03-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>Joel Sherrill2002-04-121-82/+3
| | | | | | | * cache.c: Include <rtems/score/registers.h> instead of <libcpu/registers.h>. * cpu.h: Ditto. Remove parts moved to score/cpu/i386. * registers.h: Add BIG-FAT warning.
* Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine GauthierJoel Sherrill2000-06-121-47/+0
| | | | | | | | | | | | | | | <charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart <Darlene.Stewart@nrc.ca> to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860
* *** empty log message ***Joel Sherrill1999-11-231-27/+21
|
* Patch from Erik Ivanenko <erik.ivanenko@utoronto.ca> to eliminate aJoel Sherrill1999-04-191-1/+2
| | | | warning.
* Fixed some spacing issues.Joel Sherrill1999-04-191-4/+5
|
* Patch from "Tony R. Ambardar" <tonya@ece.ubc.ca> and blessed byJoel Sherrill1999-03-301-2/+2
| | | | | Ian Lance Taylor <ian@airs.com> to note that condition codes are modified.
* Patch from Ian Lance Taylor <ian@airs.com> to correct previous interruptJoel Sherrill1999-03-081-3/+2
| | | | patch.
* Patch from Ian Lance Taylor <ian@airs.com>:Joel Sherrill1999-02-181-6/+6
| | | | | | | | | Here is a patch which slightly improves the i386 interrupt handling macros. These macros were written to use both input and output parameters, which is not necessary. This patch changes them to use only an input or output parameter, as appropriate. It also changes the constraints to permit the interrupt level to be loaded directly in and out of memory, rather than always requiring a register.
* Patch from Emmanuel Raguet <raguet@crf.canon.fr>:Joel Sherrill1999-02-181-0/+147
| | | | | | | You will find enclosed a patch which contains, for Intel PC386 target : - an Ethernet driver for DEC21140 device based boards. - a simple cache management with paging mechanism.
* Automatic CPU type detection code from Eric Valette <valette@crf.canon.fr>.Joel Sherrill1998-08-051-3/+6
| | | | Enabled on the pc386.
* Patch from Eric VALETTE <valette@crf.canon.fr>:Joel Sherrill1998-07-231-0/+365
Here is a enhanced version of my previous patch. This patch enables to potentially share the new interrupt management code for all Intel targets (pc386, go32 and force386) bsp. Note : this patch is complete only for pc386. It still needs to be completed for go32 and force386. I carrefully checked that anything needed is in for force386 (only some function name changes for IDT manipulation and GDT segment manipulation). But anyway I will not be able to test any of theses targets...