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* build: Remove old build systemSebastian Huber2021-09-211-96/+0
| | | | | Close #3250. Close #4081.
* riscv: Address differences in the linkerscript between GNU LD and LLVM/LLDHesham Almatary2019-10-271-0/+13
| | | | | | | | | | LLVM/LLD does not support STARTUP and ALIGN_WITH_INPUT directives that GNU LD support. INPUT and ALIGN(8) are supported by LLVM/LLD and can replace the unsupported STARTUP/ALIGN_WITH_INPUT directives. The commit conditionally adds the supported directive that linkers can understand depending on the toolchain used to compile RTEMS i.e., clang or gcc. Clang is assumed to use LLD by default.
* riscv: Generate linkcmds.base from the shared linkcmds.base.inHesham Almatary2019-10-271-0/+1
| | | | | This commit moves the existing linkcmds.base to linkcmds.base.in in order to make it configurable by autotools.
* riscv: add freedom E310 Arty A7 bspPragnesh Patel2019-10-231-1/+15
| | | | | | | Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board. Update #3785. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
* bsp/riscv: Disable HTIF support by defaultSebastian Huber2018-07-251-2/+2
| | | | | | The HTIF is a legacy machinery. Update #3433.
* riscv: Rework exception handlingSebastian Huber2018-07-251-0/+3
| | | | | | | | | | | Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() functions. Applications can install an exception handler via the fatal error handler to handle synchronous exceptions. Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must be provided by the BSP. Update #3433.
* bsp/riscv: Add console support for NS16550 devicesSebastian Huber2018-07-061-0/+6
| | | | Update #3433.
* bsp/riscv: Add device tree support for consoleSebastian Huber2018-06-281-0/+3
| | | | Update #3433.
* bsp/riscv: Add device tree supportSebastian Huber2018-06-281-0/+12
| | | | Update #3433.
* bsp/riscv: Add BSP options to define RAM regionSebastian Huber2018-06-271-2/+24
| | | | Update #3433.
* bsp/riscv: Remove unused BSP optionsSebastian Huber2018-06-271-10/+0
| | | | Update #3433.
* bsp/riscv_generic: Rename to "riscv"Sebastian Huber2018-06-271-0/+32
Update #3433.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-22 09:19:27 +0000