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path: root/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c (follow)
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* bsps: Move arm-cp15-set-ttb-entries.c to bspsSebastian Huber2018-04-241-89/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa2016-09-071-9/+1
| | | | | | | | | | | Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level.
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-07-201-8/+42
| | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED }
* Change all references of rtems.com to rtems.org.Chris Johns2014-03-211-1/+1
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* bsps/arm: Fix for top of the address spaceRic Claus2013-07-171-2/+3
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* bsps/arm: Add arm_cp15_set_trans*_table_entries()Sebastian Huber2013-05-031-0/+62