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* bsps/arm: Remove unused filesSebastian Huber2018-04-2512-17989/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-cp15-set-ttb-entries.c to bspsSebastian Huber2018-04-241-89/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-cp15-set-exception-handler.c to bspsSebastian Huber2018-04-241-56/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-a9mpcore-smp.c to bspsSebastian Huber2018-04-241-70/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-pl050.c to bspsSebastian Huber2018-04-241-116/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-pl011.c to bspsSebastian Huber2018-04-241-91/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-pl111-fb.c to bspsSebastian Huber2018-04-241-276/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-generic-timer-clock-config.c to bspsSebastian Huber2018-04-241-202/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move arm-a9mpcore-clock-config.c to bspsSebastian Huber2018-04-241-212/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move armv7m-cpucounter.c to bspsSebastian Huber2018-04-241-53/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move bspreset.c to bspsSebastian Huber2018-04-241-38/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps/arm: Remove unused shared/comm/uart.cSebastian Huber2018-04-241-565/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps/arm: Move bsp_memory_management_initialize()Sebastian Huber2018-04-241-29/+0
| | | | | | | | This function is only used by the raspberrypi BSP. This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move legacy network drivers to bspsSebastian Huber2018-04-231-1839/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move interrupt controller support to bspsSebastian Huber2018-04-233-279/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move startup files to bspsSebastian Huber2018-04-206-868/+0
| | | | | | | | Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move start files to bspsSebastian Huber2018-04-201-462/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move clock drivers to bspsSebastian Huber2018-04-204-299/+4
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Move doxygen.h files to bspsSebastian Huber2018-04-201-15/+0
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* bsps: Rework cache manager implementationSebastian Huber2018-01-314-2088/+0
| | | | | | | | | | | | | | | | | | The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
* bsps: Move network define to source filesSebastian Huber2018-01-311-2/+1
| | | | | Define __INSIDE_RTEMS_BSD_TCPIP_STACK__ in the network interface driver source files to avoid some build system magic.
* Remove make preinstallChris Johns2018-01-2532-7570/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
* ARM BSPs: Simplify bsp_specsJoel Sherrill2017-12-191-0/+1
| | | | Updates #3520.
* bsps/arm: Disable all interrupts in GIC initSebastian Huber2017-12-141-0/+4
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* bsps/arm: Remove DWT based clock.Christian Mauderer2017-10-181-30/+7
| | | | | | | | | | | It seems that the DWT CYCCNT does not advance when the CPU waits on a WFI instruction. That leads to the effect that for example on the atsamv BSP a sleep(1) needs something in the range of a few minutes (depending on the configured systick). A debugger might disables some deep sleep modes so that the problem only appears if the application is executed without a debugger.
* bsps/arm: Copy FDT only on boot processorSebastian Huber2017-09-221-7/+14
| | | | Update #3090.
* bsps: Clock_driver_support_install_isr()Sebastian Huber2017-09-184-20/+8
| | | | | | | Remove old ISR parameter since is not used by the clock driver shell. Make an implementation optional. Update #3139.
* Simplify and unify BSP_output_charSebastian Huber2017-09-121-1/+0
| | | | | | | | The BSP_output_char should output a char and not mingle with high level processing, e.g. '\n' to '\r\n' translation. Move this translation to rtems_putc(). Remove it from all the BSP_output_char implementations. Close #3122.
* Include missing <string.h>Sebastian Huber2017-08-252-0/+3
| | | | Update #2133.
* bsps/arm: Add ARMv7-AR Generic Timer clock driverSebastian Huber2017-08-041-0/+205
| | | | Update #3090.
* bsps: Include missing header fileSebastian Huber2017-07-121-0/+1
| | | | Update #3071.
* bsp/beagle: Add FDT support for Beaglebone BlackSichen Zhao2017-07-121-0/+5
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* Add interrupt vector set/get affinitySebastian Huber2017-07-122-12/+21
| | | | Close #3071.
* bsps: Improve interrupt vector enable/disable APISebastian Huber2017-06-202-32/+14
| | | | | | Change bsp_interrupt_vector_enable() and bsp_interrupt_vector_disable() to not return a status code. Add bsp_interrupt_assert() and use it to validate the vector number in the vector enable/disable implementations.
* Remove excessive locking from cache operations.Alexei Pososin2017-06-141-35/+9
| | | | | | | | According to manual, the used operations (Clean Line by PA, Clean and Invalidate Line by PA, Cache Sync) are atomic and do not require locking. Update #3007.
* bsps/arm: Fix ARMv7-M interrupt suppportChristian Mauderer2017-06-071-2/+6
| | | | | | Enable/disable vector routines now check for a valid vector. Without these guards, the enable/disable vector routines will not work with the interrupt server.
* bsps/arm: Fix bit field offset in GIC supportSebastian Huber2017-05-111-1/+1
| | | | Update #3002.
* arm: Remove legacy execption supportSebastian Huber2017-03-083-343/+0
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* bsps/arm: Fix Cortex-M DWT CPU counter.Christian Mauderer2017-01-302-10/+6
| | | | | | | | | It is necessary to enable the DWT using a special initialization sequence before the CYCCNT can be enabled. See for example the RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h. Note that this problem only occurs if no debugger is connected. A debugger most likely already enables the necessary module.
* Adding ARM VFP V2 supportKevin Kirspel2017-01-241-0/+4
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* powerpc/shared/linkcmds.base: Add .rela.rtemsroset and .rela.rtemsrwsetJoel Sherrill2017-01-161-0/+2
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* bsps/arm: Add Cortex-M DWT CPU counterSebastian Huber2016-11-241-0/+55
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* arm: Use TPIDRPRW for current per-CPU controlSebastian Huber2016-11-181-5/+13
| | | | | | Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
* bsps/arm: Export bsp_start_hook_0_done symbol from ARM start.S.Pavel Pisa2016-09-221-0/+1
| | | | | | | | The symbol can be used by bsp_start_hook_0 when complete RAM memory is initialization and overwritten during BSP self-test. The test overwrites even memory used to store return address / link register and regular resturn from bsp_start_hook_0 is not possible then.
* bsps/arm: remove lock in arm_cp15_set_translation_table_entries().Pavel Pisa2016-09-071-9/+1
| | | | | | | | | | | Protection by rtems_interrupt_disable() is incompatible with SMP build. Actual page table entries manipulation function does not need locking and disabling cache and can be run concurrently even on multiple CPUs as long as changes do not modify same region. If the function is called from more threads/CPUs to modify same region with different mapping options concurrently then there is problem at another level of virtual address space management and has to be solved by mutex or other locking at that level.
* libbsp/arm: Add the TTB table to the default MMU set up as read/write.Chris Johns2016-08-151-0/+4
| | | | | | | This lets the table be changed at runtime for dynamic loading and debugger support. Closes #2775.
* bsps/arm: Clear pending exceptions for ARMv7-MAlexander Krutwig2016-07-261-0/+2
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* arm/bsps: CP15 and basic cache support entire cache clean for more ↵Pavel Pisa2016-07-202-4/+24
| | | | | | | | | | | | | | | | | architecture variants now. Next cache operations should work on most of cores now rtems_cache_flush_entire_data() rtems_cache_invalidate_entire_data() rtems_cache_invalidate_entire_instruction() Instruction cache invalidate works on the first level for now only. Data cacache operations are extended to ensure flush/invalidate on all cache levels. The CP15 arm_cp15_data_cache_clean_all_levels() function extended to continue through unified levels too (ctype = 4).
* bsps/arm: do not disable MMU during translation table management operations.Pavel Pisa2016-07-201-8/+42
| | | | | | | | | | | | | | | | | | | | Disabling MMU requires complex cache flushing and invalidation operations. There is almost no way how to do that right on SMP system without stopping all other CPUs. On the other hand, there is documented sequence of operations which should be used according to ARM manual and it guarantees even distribution of maintenance operations to other cores for last generation of Cortex-A cores with multiprocessor extension. This change could require addition of appropriate entry to arm_cp15_start_mmu_config_table for some BSPs to ensure that MMU table stays accessible after MMU is enabled { .begin = (uint32_t) bsp_translation_table_base, .end = (uint32_t) bsp_translation_table_base + 0x4000, .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED }
* Misc: Spell length correctlyJoel Sherrill2016-07-122-2/+2
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