| Commit message (Collapse) | Author | Age | Files | Lines |
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Since the trap table is now statically initialized, there is no need to
invalidate the instruction cache.
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Using rtems_interrupt_entry_install() instead of
rtems_interrupt_handler_install() avoids a dependency on the dynamic memory
allocation.
Use Interrupt Manager directives instead of a BSP-specific API. Use inline
functions. In SMP configurations, set an affinity to all online processors and
raise the interrupt on the current processor.
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Using rtems_interrupt_entry_install() instead of
rtems_interrupt_handler_install() avoids a dependency on the dynamic memory
allocation.
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Using rtems_interrupt_entry_install() instead of
rtems_interrupt_handler_install() avoids a dependency on the dynamic memory
allocation.
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The AArch64 cache implementation does not define
rtems_cache_disable_data(), but declares that it does via
CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of
_CPU_cache_disable_data() is sufficient to enable this functionality
without the erroneous cache feature flag.
Closes #4569
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The BSPs provide memory for the separate C Program Heap initialization
via _Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the separate C Program Heap and let the
BSP select one of the implementations based on the number of provided
memory areas. This gets rid of a dependency on _Heap_Extend(). It
also avoids dead code sections for most BSPs.
Change licence to BSD-2-Clause according to file history.
Update #3053.
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The BSPs provide memory for the workspace initialization via
_Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the workspace handler and let the BSP
select one of the implementations based on the number of provided memory
areas. This gets rid of a dependency on _Heap_Extend(). It also avoids
dead code sections for most BSPs.
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Updates #3937.
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Fixing the debug mask flag broke nested interrupts. This restores that
functionality.
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This adds support for libdebugger under AArch64 using software
breakpoints and the single-step execution mode present in all AArch64
CPUs.
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Debug events should be masked at least until after the first context
switch and should usually be masked until a debugger is attached for
application debugging.
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The existing code is functional but inccorrect and blindly modifies the
other masking bits. It is important to preserve those other bits since
they control masking of important system events.
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Certain input parameters for MMU mapping operations could cause an
infinite recursion if block end boundaries didn't align to 4k. This
ensures that recursion descent does not exceed 2 levels and instead
rounds up to the nearest 4k block if necessary.
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This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
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This reworks the existing MicroBlaze architecture port and BSP to
achieve basic functionality using the latest RTEMS APIs.
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This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
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ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
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GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only
configured for 192 interrupts.
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This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on BSP configuration.
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Close #3250.
Close #4081.
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- Trigger on a single character entering the RX FIFO
- Disable the RX timeout
- Send up to a FIFO full of data
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Added I2C drivers for ZynqMP and updated build system accordingly.
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Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
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This simplifies the implementation a bit. Declare _TOD_Days_to_date[] in
<rtems/score/todimpl.h>. Make _TOD_Days_per_month[] and
_TOD_Days_since_last_leap_year[] static.
Update #4338.
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Rename LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR in
LEON3_FATAL_INVALID_CACHE_CONFIG_BOOT_PROCESSOR since the term
"boot processor" is used elsewhere in the code base.
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It wasn't possible to keep the CS line low between multiple message
descriptors in one transfer. This patch reworks the driver so that it is
possible.
Update #4180
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- Wait for the tx holding register to empty in a tx flush
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The Pi firmware added a wfe(wait for event), the cores 1-3 wait
for the start address being written to the mailbox register, followed
by a SEV poke to the mailbox that acts as a wfe wake-up event.
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Take the interrupt force register into account in all configurations.
Update #3269.
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Do not continue execution on processors which are not configured to prevent the
use of arbitrary memory for the initialization stack.
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Directly call the handler on the executing processor instead of doing this
indirectly via a per-CPU job.
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Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
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Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
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Add default implementations for bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() which are required to link all tests in SMP
configurations.
Update #3269.
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Add rtems_interrupt_entry_remove(). Split up irq-generic.c into several files.
In particular, place all functions which use dynamic memory into their own
file.
Add optional macros to let the BSP customize the vector installation after
installing the first entry and the vector removal before removing the last
entry:
* bsp_interrupt_vector_install()
* bsp_interrupt_vector_remove()
Use these new customization options in the m68k/genmcf548x BSP so re-use the
generic interrupt controller support.
Update #3269.
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This function is only used by one BSP.
Update #3269.
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Return RTEMS_INCORRECT_STATE instead of RTEMS_INTERNAL_ERROR in case the
interrupt support is not initialized. This is similar to
rtems_timer_server_fire_after() for example.
Update #3269.
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Update #3269.
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Update #3269.
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Update #3269.
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Return a status code for bsp_interrupt_set_affinity().
Update #3269.
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Return a status code for bsp_interrupt_get_affinity().
Update #3269.
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Return a status code for bsp_interrupt_vector_disable().
Update #3269.
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Return a status code for bsp_interrupt_vector_enable().
Update #3269.
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Add a default implementation which just returns RTEMS_UNSATISFIED.
Update #3269.
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Add a default implementation which clears the attributes to zero and
just returns RTEMS_SUCCESSFUL for valid parameters.
Update #3269.
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Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
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