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* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-208-4/+132
* bsps/riscv: Add device tree blobPadmarao Begari2022-09-202-0/+967
* bsps/riscv/riscv: Fix fe310_uart_readAlan Cudmore2022-09-191-2/+5
* bsp/riscv: Add NOEL-V BSPMartin Aberg2022-09-068-0/+469
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+144
* riscv: Use zicsr architecture extensionSebastian Huber2022-02-252-1/+8
* bsps/riscv: Add missing includeSebastian Huber2022-02-251-0/+1
* bsp_specs: Delete last remnants of these.Joel Sherrill2021-11-292-0/+0
* build: Remove old build systemSebastian Huber2021-09-216-534/+0
* score: Canonicalize _CPU_Fatal_halt()Sebastian Huber2021-07-282-2/+4
* bsps/irq: bsp_interrupt_facility_initialize()Sebastian Huber2021-07-272-6/+2
* bsps/irq: bsp_interrupt_set_affinity()Sebastian Huber2021-07-264-6/+10
* bsps/irq: bsp_interrupt_get_affinity()Sebastian Huber2021-07-264-4/+8
* bsps/irq: bsp_interrupt_vector_disable()Sebastian Huber2021-07-262-2/+5
* bsps/irq: bsp_interrupt_vector_enable()Sebastian Huber2021-07-262-2/+5
* bsps/irq: Add rtems_interrupt_is_pending()Sebastian Huber2021-07-262-0/+22
* bsps/irq: Add rtems_interrupt_get_attributes()Sebastian Huber2021-07-262-0/+16
* bsps/irq: Add rtems_interrupt_raise()Sebastian Huber2021-07-262-0/+46
* bsps/irq: Add rtems_interrupt_vector_is_enabled()Sebastian Huber2021-07-262-0/+22
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MAXSebastian Huber2021-06-242-2/+0
* bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNTSebastian Huber2021-06-242-0/+2
* bsps/irq: Remove BSP_INTERRUPT_VECTOR_MINSebastian Huber2021-06-242-4/+0
* grlib: Add apbuart_outbyte_wait()Sebastian Huber2021-06-171-1/+2
* grlib: Remove NL -> CR in apbuart_outbyte_polled()Sebastian Huber2021-06-171-1/+1
* grlib: Add ambapp_plb()Sebastian Huber2021-06-175-16/+25
* bsps: Support RTEMS_NOINIT in linkcmdsSebastian Huber2021-05-022-0/+11
* bsps: Remove networking driversVijay Kumar Banerjee2021-04-071-59/+0
* bsps/riscv: Add per cpu clock interruptJan Sommer2021-03-231-10/+49
* bsp/riscv: Re-license to BSD-2-ClauseSebastian Huber2021-02-091-10/+37
* bsps: Replace bsp_specs with an empty fileSebastian Huber2021-01-282-18/+0
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-20/+30
* Add networking support for griscv bspJiri Gaisler2020-11-093-1/+74
* grlib: Add and use irqmp_has_timestamp()Sebastian Huber2020-10-101-1/+1
* bsps/riscv: Add bsp_fdt_map_intr()Sebastian Huber2020-09-231-0/+6
* riscv: Make sifive_test finisher 4 bytesHesham Almatary2020-09-171-1/+1
* bsps/riscv: Use far jump to boot_card()Sebastian Huber2020-09-151-1/+1
* htif_console_handler is defined in htif.cHesham Almatary2020-09-061-1/+1
* bsps: Always install IPI in SMP configsSebastian Huber2020-08-311-12/+9
* bsps/riscv: Fix multiple definitionSebastian Huber2020-04-101-2/+0
* imfs: Replace devfs with an IMFS specializationSebastian Huber2020-03-091-3/+0
* Use RTEMS_SYSINIT_ORDER_LAST_BUT_5Sebastian Huber2020-02-041-1/+1
* bsps: Add RamEnd to linker command filesSebastian Huber2020-02-041-0/+1
* Regenerate headers.amSebastian Huber2019-11-291-0/+1
* bsp/riscv: Fix format and warningsSebastian Huber2019-11-142-45/+27
* bsp/riscv: Fix use of uninitialized integerSebastian Huber2019-11-141-6/+1
* bsp/riscv: riscv_get_core_frequency()Sebastian Huber2019-11-142-43/+23
* bsps/riscv: UART - Read reg-shift from DTB to properly set/get registersHesham Almatary2019-10-301-2/+13
* riscv: Add new BSP cfg variants to be built with llvm/clangHesham Almatary2019-10-278-0/+112
* riscv: Add new offending input sections to the linker scriptHesham Almatary2019-10-271-0/+5
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