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* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* bsps/riscv: Make SMP start more robustSebastian Huber2023-03-171-2/+14
| | | | | | | In SMP configurations, check that we run on a configured processor. If not, then there is not much that can be done since we do not have a stack available for this processor. Just loop forever in this case. Do this in assemlby to ensure that no stack memory is used.
* doxygen: Add Doxygen files to a groupSebastian Huber2023-02-161-0/+8
| | | | Update #3707.
* bsps/riscv: Use start data for objectSebastian Huber2022-11-041-0/+6
| | | | | | Maybe this helps to ensure that the object is properly aligned. Update #4658.
* bsps/riscv: Workaround for sporadic linker issuesSebastian Huber2022-10-281-0/+1
| | | | | | | | | | | Disable the linker relaxation in start.S to work around an issue described here: https://mail.gnu.org/archive/html/bug-binutils/2021-03/msg00164.html The real issue is probably in the linker command file or the linker itself. Update #4658.
* bsps/riscv: Add Microchip PolarFire SoC BSP variantPadmarao Begari2022-09-201-0/+2
| | | | | | | | The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
* bsp/riscv: Work area size based on /memory node in fdtDaniel Cederman2022-09-061-0/+144
| | | | | Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node.
* riscv: Use zicsr architecture extensionSebastian Huber2022-02-251-0/+1
| | | | | | | | | | This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
* build: Remove old build systemSebastian Huber2021-09-211-410/+0
| | | | | Close #3250. Close #4081.
* bsps: Support RTEMS_NOINIT in linkcmdsSebastian Huber2021-05-021-0/+7
| | | | Update #3866.
* bsps: Add missing DWARF 5 sectionsSebastian Huber2021-01-261-3/+5
| | | | Sort alphabetically.
* bsps: Support DWARF 5 sectionsSebastian Huber2021-01-251-20/+30
| | | | GCC 11 uses DWARF 5 by default.
* bsps/riscv: Use far jump to boot_card()Sebastian Huber2020-09-151-1/+1
| | | | | | Use a far jump to avoid errors like this: relocation truncated to fit: R_RISCV_JAL against symbol `boot_card'
* bsps: Add RamEnd to linker command filesSebastian Huber2020-02-041-0/+1
| | | | Update #3838.
* riscv: Add new offending input sections to the linker scriptHesham Almatary2019-10-271-0/+5
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* riscv: Add NOLOAD directive to the .work sectionHesham Almatary2019-10-271-1/+1
| | | | ld.lld defaults .work to PROGBITS otherwise
* riscv: Address differences in the linkerscript between GNU LD and LLVM/LLDHesham Almatary2019-10-271-51/+51
| | | | | | | | | | LLVM/LLD does not support STARTUP and ALIGN_WITH_INPUT directives that GNU LD support. INPUT and ALIGN(8) are supported by LLVM/LLD and can replace the unsupported STARTUP/ALIGN_WITH_INPUT directives. The commit conditionally adds the supported directive that linkers can understand depending on the toolchain used to compile RTEMS i.e., clang or gcc. Clang is assumed to use LLD by default.
* riscv: Generate linkcmds.base from the shared linkcmds.base.inHesham Almatary2019-10-271-0/+0
| | | | | This commit moves the existing linkcmds.base to linkcmds.base.in in order to make it configurable by autotools.
* bsps: Adjust shared Doxygen groupsSebastian Huber2019-03-081-0/+8
| | | | Update #3706.
* bsps: Adjust architecture Doxygen groupsSebastian Huber2019-03-041-0/+7
| | | | | | | | | | - Use CamelCase as it is not used in our C code. Enables simple search and replace. - Prefix with "RTEMS" to aid deployment and integration. It aids searching and sorting. Update #3706.
* riscv: add griscv bspJiri Gaisler2019-01-222-0/+532
Update #3678.
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