diff options
Diffstat (limited to 'c/src/lib/libbsp/powerpc/mbx8xx')
17 files changed, 515 insertions, 515 deletions
diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c b/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c index 4a79f81864..b4bf7ca93e 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/clock/p_clock.c @@ -28,7 +28,7 @@ static rtems_irq_connect_data clockIrqData = {BSP_PERIODIC_TIMER, (rtems_irq_enable)clockOn, (rtems_irq_disable)clockOff, (rtems_irq_is_enabled)clockIsOn}; - + int BSP_get_clock_irq_level() { /* @@ -65,6 +65,6 @@ int BSP_connect_clock_handler (rtems_irq_hdl hdl) clockIrqData.on = (rtems_irq_enable)clockOn; clockIrqData.off = (rtems_irq_enable)clockOff; clockIrqData.isOn = (rtems_irq_is_enabled)clockIsOn; - + return BSP_install_rtems_irq_handler (&clockIrqData); } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c index 7716cf3a85..efb7c6853b 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/console/console.c @@ -45,7 +45,7 @@ * Interrupt-driven I/O requires termios. * * TESTS: - * + * * TO RUN THE TESTS, USE POLLED I/O WITHOUT TERMIOS SUPPORT. Some tests * play with the interrupt masks and turn off I/O. Those tests will hang * when interrupt-driven I/O is used. Other tests, such as cdtest, do I/O @@ -55,16 +55,16 @@ * should all be fixed to work with interrupt-driven I/O and to * produce output in the expected sequence. Obviously, the termios test * requires termios support in the driver. - * + * * Set CONSOLE_MINOR to the appropriate device minor number in the * config file. This allows the RTEMS application console to be different * from the EPPBug debug console or the GDB port. - * + * * This driver handles all five available serial ports: it distinguishes * the sub-devices using minor device numbers. It is not possible to have * other protocols running on the other ports when this driver is used as * currently written. - * + * * Based on code (alloc860.c in eth_comm port) by * Jay Monkman (jmonkman@frasca.com), * Copyright (C) 1998 by Frasca International, Inc. @@ -118,7 +118,7 @@ static int _EPPCBug_pollRead( volatile int simask; /* We must read and write m8xx.simask */ int retval; ISR_Level level; - + struct { int clun; int dlun; @@ -126,7 +126,7 @@ static int _EPPCBug_pollRead( int nbytes_requested; int reserved; } volatile input_params; - + struct { int status; union { @@ -145,30 +145,30 @@ static int _EPPCBug_pollRead( retval = -1; input_params.clun = 0; - + switch( minor ) { - case SMC1_MINOR: + case SMC1_MINOR: input_params.dlun = 0; /* Should be 4, but doesn't work with EPPCBug 1.1 */ break; - case SMC2_MINOR: + case SMC2_MINOR: input_params.dlun = 5; break; - case SCC2_MINOR: + case SCC2_MINOR: input_params.dlun = 1; break; #ifdef mpc860 - case SCC3_MINOR: + case SCC3_MINOR: input_params.dlun = 2; break; - case SCC4_MINOR: + case SCC4_MINOR: input_params.dlun = 3; break; #endif - default: + default: input_params.dlun = 0; break; } - + _ISR_Disable( level ); simask = m8xx.simask; @@ -180,21 +180,21 @@ static int _EPPCBug_pollRead( :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if ( (output_params.status == 0) && output_params.u.stat.input_char_available) { - + /* Read the char and return it */ input_params.inbuf = &c; input_params.nbytes_requested = 1; - + asm volatile( "li 10,0x200 /* Code for .CIO_READ */\n\ mr 3, %0 /* Address of input_params */\n\ mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ + sc" /* Call EPPCBUG */ :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if ( (output_params.status == 0) && output_params.u.read.nbytes_received) retval = (int)c; } - + m8xx.simask = simask; _ISR_Enable( level ); return retval; @@ -227,7 +227,7 @@ static int _EPPCBug_pollWrite( volatile int simask; int i, retval; ISR_Level level; - + struct { int clun; int dlun; @@ -235,7 +235,7 @@ static int _EPPCBug_pollWrite( int nbytes_to_output; int reserved; } volatile input_params; - + struct { int status; union { @@ -255,26 +255,26 @@ static int _EPPCBug_pollWrite( input_params.clun = 0; input_params.reserved = 0; - + switch( minor ) { - case SMC1_MINOR: + case SMC1_MINOR: input_params.dlun = 0; /* Should be 4, but doesn't work with EPPCBug 1.1 */ break; - case SMC2_MINOR: + case SMC2_MINOR: input_params.dlun = 5; break; - case SCC2_MINOR: + case SCC2_MINOR: input_params.dlun = 1; break; #ifdef mpc860 - case SCC3_MINOR: + case SCC3_MINOR: input_params.dlun = 2; break; - case SCC4_MINOR: + case SCC4_MINOR: input_params.dlun = 3; break; #endif - default: + default: input_params.dlun = 0; break; } @@ -291,7 +291,7 @@ static int _EPPCBug_pollWrite( asm volatile( "li 10,0x202 /* Code for .CIO_STAT */\n\ mr 3, %0 /* Address of input_params */\n\ mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ + sc" /* Call EPPCBUG */ :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if (output_params.status) @@ -301,11 +301,11 @@ static int _EPPCBug_pollWrite( /* Output the characters until done */ input_params.outbuf = &buf[i]; input_params.nbytes_to_output = len - i; - + asm volatile( "li 10,0x201 /* Code for .CIO_WRITE */\n\ mr 3, %0 /* Address of input_params */\n\ mr 4, %1 /* Address of output_params */\n\ - sc" /* Call EPPCBUG */ + sc" /* Call EPPCBUG */ :: "g" (&input_params), "g" (&output_params) : "3", "4", "10" ); if (output_params.status) @@ -313,7 +313,7 @@ static int _EPPCBug_pollWrite( i += output_params.u.write.nbytes_sent; } - + /* Return something */ m8xx.simask = simask; _ISR_Enable( level ); @@ -361,7 +361,7 @@ static rtems_status_code do_poll_read( #if NVRAM_CONFIGURE == 1 int (*pollRead)( int minor ); - + if ( (nvram->console_mode & 0x06) == 0x04 ) pollRead = _EPPCBug_pollRead; else @@ -399,7 +399,7 @@ static rtems_status_code do_poll_read( * Output characters through polled I/O. Returns only once every character has * been sent. * - * CR is transmitted AFTER a LF on output. + * CR is transmitted AFTER a LF on output. * * Input parameters: * major - ignored. Should be the major number for this driver. @@ -427,7 +427,7 @@ static rtems_status_code do_poll_write( #if NVRAM_CONFIGURE == 1 int (*pollWrite)(int minor, const char *buf, int len); - + if ( (nvram->console_mode & 0x06) == 0x04 ) pollWrite = _EPPCBug_pollWrite; else @@ -468,8 +468,8 @@ static rtems_status_code do_poll_write( static void _BSP_output_char( char c ) { char cr = '\r'; - - /* + + /* * Can't rely on console_initialize having been called before this function * is used, so it may fail unless output is done through EPPC-Bug. */ @@ -489,8 +489,8 @@ static void _BSP_output_char( char c ) if( c == '\n' ) m8xx_uart_pollWrite( PRINTK_MINOR, &cr, 1 ); } - -#else + +#else #if PRINTK_IO_MODE == 2 #define PRINTK_WRITE _EPPCBug_pollWrite @@ -501,7 +501,7 @@ static void _BSP_output_char( char c ) PRINTK_WRITE( PRINTK_MINOR, &c, 1 ); if( c == '\n' ) PRINTK_WRITE( PRINTK_MINOR, &cr, 1 ); - + #endif } @@ -543,7 +543,7 @@ serial_init() bd_t *bd; bd = eppcbugInfo; - + cp = cpmp; sp = (smc_t*)&(cp->cp_smc[SMC_INDEX]); up = (smc_uart_t *)&cp->cp_dparam[PROFF_CONS]; @@ -723,14 +723,14 @@ rtems_device_driver console_initialize( { rtems_status_code status; rtems_device_minor_number console_minor; - + /* * Set up TERMIOS if needed */ #if NVRAM_CONFIGURE == 1 /* Use NVRAM info for configuration */ console_minor = nvram->console_printk_port & 0x07; - + if ( nvram->console_mode & 0x01 ) /* termios */ rtems_termios_initialize (); @@ -739,7 +739,7 @@ rtems_device_driver console_initialize( * Do common initialization. */ m8xx_uart_initialize(); - + /* * Do device-specific initialization */ @@ -750,12 +750,12 @@ rtems_device_driver console_initialize( if ( ((nvram->console_mode & 0x30) != 0x20) || (((nvram->console_printk_port & 0x30) >> 4) != SMC2_MINOR) ) - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ + m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ if ( ((nvram->console_mode & 0x30) != 0x20) || (((nvram->console_printk_port & 0x30) >> 4) != SCC2_MINOR) ) m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ - + #ifdef mpc860 if ( ((nvram->console_mode & 0x30) != 0x20) || @@ -771,18 +771,18 @@ rtems_device_driver console_initialize( #else /* NVRAM_CONFIGURE != 1 */ console_minor = CONSOLE_MINOR; - + #if UARTS_USE_TERMIOS == 1 rtems_termios_initialize (); - + #endif /* UARTS_USE_TERMIOS */ - + /* * Do common initialization. */ m8xx_uart_initialize(); - + /* * Do device-specific initialization */ @@ -791,13 +791,13 @@ rtems_device_driver console_initialize( #endif #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SMC2_MINOR - m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ + m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */ #endif #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC2_MINOR m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2 */ #endif - + #ifdef mpc860 #if PRINTK_IO_MODE != 2 || PRINTK_MINOR != SCC3_MINOR @@ -818,31 +818,31 @@ rtems_device_driver console_initialize( status = rtems_io_register_name ("/dev/tty0", major, SMC1_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty1", major, SMC2_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty2", major, SCC2_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + #ifdef mpc860 status = rtems_io_register_name ("/dev/tty3", major, SCC3_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + status = rtems_io_register_name ("/dev/tty4", major, SCC4_MINOR); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + #endif /* mpc860 */ - + /* Now register the RTEMS console */ status = rtems_io_register_name ("/dev/console", major, console_minor); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred (status); - + return RTEMS_SUCCESSFUL; } @@ -881,12 +881,12 @@ rtems_device_driver console_open( 0 /* outputUsesInterrupts */ }; rtems_status_code sc; - - + + #if (NVRAM_CONFIGURE == 1) || \ ((NVRAM_CONFIGURE != 1) && (UARTS_USE_TERMIOS == 1) && \ (UARTS_IO_MODE == 1)) - + static const rtems_termios_callbacks intrCallbacks = { NULL, /* firstOpen */ NULL, /* lastClose */ @@ -898,13 +898,13 @@ rtems_device_driver console_open( 1 /* outputUsesInterrupts */ }; #endif - - if ( minor > NUM_PORTS-1 ) + + if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) { /* Use termios */ if ( (nvram->console_mode & 0x06) == 0x02 ) { @@ -923,7 +923,7 @@ rtems_device_driver console_open( else /* no termios -- default to polled I/O */ return RTEMS_SUCCESSFUL; - + #else /* NVRAM_CONFIGURE != 1 */ #if UARTS_USE_TERMIOS == 1 @@ -943,7 +943,7 @@ rtems_device_driver console_open( #endif /* UARTS_USE_TERMIOS != 1 */ return sc; - + #endif /* NVRAM_CONFIGURE != 1 */ } @@ -962,7 +962,7 @@ rtems_device_driver console_close( #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* use termios */ return rtems_termios_close( arg ); @@ -996,7 +996,7 @@ rtems_device_driver console_read( #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* use termios */ return rtems_termios_read( arg ); @@ -1030,7 +1030,7 @@ rtems_device_driver console_write( #if NVRAM_CONFIGURE == 1 - /* Use NVRAM info for configuration */ + /* Use NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* use termios */ return rtems_termios_write( arg ); @@ -1059,13 +1059,13 @@ rtems_device_driver console_control( rtems_device_minor_number minor, void *arg ) -{ +{ if ( minor > NUM_PORTS-1 ) return RTEMS_INVALID_NUMBER; #if NVRAM_CONFIGURE == 1 - /* Uuse NVRAM info for configuration */ + /* Uuse NVRAM info for configuration */ if ( nvram->console_mode & 0x01 ) /* termios */ return rtems_termios_ioctl( arg ); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c b/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c index eb9f6c135b..6dee967b54 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/ide/idecfg.c @@ -45,5 +45,5 @@ ide_controller_bsp_table_t IDE_Controller_Table[] = { }; /* Number of rows in IDE_Controller_Table */ -unsigned long IDE_Controller_Count = +unsigned long IDE_Controller_Count = sizeof(IDE_Controller_Table)/sizeof(IDE_Controller_Table[0]); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c b/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c index 6c6d2d368d..9e9d3069fc 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/ide/pcmcia_ide.c @@ -33,8 +33,8 @@ /* #define DATAREG_16BIT */ /* 16 bit mode not yet working */ /* #define DEBUG_OUT */ -/* - * support functions for PCMCIA IDE IF +/* + * support functions for PCMCIA IDE IF */ /*=========================================================================*\ | Function: | @@ -55,11 +55,11 @@ boolean mbx8xx_pcmciaide_probe \*=========================================================================*/ { boolean ide_card_plugged = TRUE; /* assume: we have a card plugged in */ - + /* * check, that the CD# pins are low -> a PCMCIA card is plugged in */ - if ((m8xx.pipr + if ((m8xx.pipr & (M8xx_PCMCIA_PIPR_CACD1 | M8xx_PCMCIA_PIPR_CACD2)) != 0x00) { ide_card_plugged = FALSE; } @@ -79,7 +79,7 @@ boolean mbx8xx_pcmciaide_probe int cis_pos = 0; boolean fixed_disk_tuple_found = FALSE; boolean ata_disk_tuple_found = FALSE; - + while ((cis_pos < 256) && (CIS_BYTE(cis_pos) != 0xff) && (!fixed_disk_tuple_found || !ata_disk_tuple_found)) { @@ -95,10 +95,10 @@ boolean mbx8xx_pcmciaide_probe (CIS_BYTE(cis_pos+3) == 0x01)) { ata_disk_tuple_found = TRUE; } - /* - * advance using the length field + /* + * advance using the length field */ - cis_pos += CIS_BYTE(cis_pos+1)+2; + cis_pos += CIS_BYTE(cis_pos+1)+2; } ide_card_plugged = fixed_disk_tuple_found && ata_disk_tuple_found; } @@ -127,7 +127,7 @@ void mbx8xx_pcmciaide_initialize * FIXME: enable interrupts, if needed */ /* - * FIXME: set programming voltage as requested + * FIXME: set programming voltage as requested */ } @@ -155,14 +155,14 @@ void mbx8xx_pcmciaide_read_reg if (reg == IDE_REGISTER_DATA_WORD) { #ifdef DATAREG_16BIT - *value = *(volatile uint16_t*)(port+reg); + *value = *(volatile uint16_t*)(port+reg); #else - *value = ((*(volatile uint8_t*)(port+reg) << 8) + - (*(volatile uint8_t*)(port+reg+1) )); + *value = ((*(volatile uint8_t*)(port+reg) << 8) + + (*(volatile uint8_t*)(port+reg+1) )); #endif } else { - *value = *(volatile uint8_t*)(port+reg); + *value = *(volatile uint8_t*)(port+reg); } #ifdef DEBUG_OUT printk("mbx8xx_pcmciaide_read_reg(0x%x)=0x%x\r\n",reg,*value & 0xff); @@ -196,14 +196,14 @@ void mbx8xx_pcmciaide_write_reg #endif if (reg == IDE_REGISTER_DATA_WORD) { #ifdef DATAREG_16BIT - *(volatile uint16_t*)(port+reg) = value; + *(volatile uint16_t*)(port+reg) = value; #else - *(volatile uint8_t*)(port+reg) = value >> 8; - *(volatile uint8_t*)(port+reg+1) = value; + *(volatile uint8_t*)(port+reg) = value >> 8; + *(volatile uint8_t*)(port+reg+1) = value; #endif } else { - *(volatile uint8_t*)(port+reg)= value; + *(volatile uint8_t*)(port+reg)= value; } } @@ -218,9 +218,9 @@ void mbx8xx_pcmciaide_read_block +---------------------------------------------------------------------------+ | Input Parameters: | \*-------------------------------------------------------------------------*/ - int minor, - uint16_t block_size, - blkdev_sg_buffer *bufs, + int minor, + uint16_t block_size, + blkdev_sg_buffer *bufs, uint32_t *cbuf, uint32_t *pos ) @@ -242,17 +242,17 @@ void mbx8xx_pcmciaide_read_block ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); #endif uint32_t llength = bufs[(*cbuf)].length; - - while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) - & IDE_REGISTER_STATUS_DRQ) && + + while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) + & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) { #ifdef DATAREG_16BIT *lbuf++ = *(volatile uint16_t*)(port+8); /* 16 bit data port */ - cnt += 2; + cnt += 2; (*pos) += 2; #else *lbuf++ = *(volatile uint8_t*)(port+IDE_REGISTER_DATA); - cnt += 1; + cnt += 1; (*pos) += 1; #endif if ((*pos) == llength) { @@ -261,7 +261,7 @@ void mbx8xx_pcmciaide_read_block lbuf = bufs[(*cbuf)].buffer; llength = bufs[(*cbuf)].length; } - } + } } /*=========================================================================*\ @@ -275,9 +275,9 @@ void mbx8xx_pcmciaide_write_block +---------------------------------------------------------------------------+ | Input Parameters: | \*-------------------------------------------------------------------------*/ - int minor, - uint16_t block_size, - blkdev_sg_buffer *bufs, + int minor, + uint16_t block_size, + blkdev_sg_buffer *bufs, uint32_t *cbuf, uint32_t *pos ) @@ -300,17 +300,17 @@ void mbx8xx_pcmciaide_write_block ((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos)); #endif uint32_t llength = bufs[(*cbuf)].length; - - while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) - & IDE_REGISTER_STATUS_DRQ) && + + while (((*(volatile uint8_t*)(port+IDE_REGISTER_STATUS)) + & IDE_REGISTER_STATUS_DRQ) && (cnt < block_size)) { #ifdef DATAREG_16BIT *(volatile uint16_t*)(port+8) = *lbuf++; /* 16 bit data port */ - cnt += 2; + cnt += 2; (*pos) += 2; #else *(volatile uint8_t*)(port+IDE_REGISTER_DATA) = *lbuf++; - cnt += 1; + cnt += 1; (*pos) += 1; #endif if ((*pos) == llength) { @@ -319,7 +319,7 @@ void mbx8xx_pcmciaide_write_block lbuf = bufs[(*cbuf)].buffer; llength = bufs[(*cbuf)].length; } - } + } } /*=========================================================================*\ @@ -368,7 +368,7 @@ rtems_status_code mbx8xx_pcmciaide_config_io_speed } /* - * The following table configures the functions used for IDE drivers + * The following table configures the functions used for IDE drivers * in this BSP. */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h index b86bbd8e31..9beb406672 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h @@ -107,7 +107,7 @@ extern rtems_configuration_table BSP_Configuration; /* * NOTE: Use the standard Console driver entry */ - + /* * NOTE: Use the standard Clock driver entry */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c index 1b8f8c2da1..2a5afa4569 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c @@ -10,7 +10,7 @@ * * $Id$ */ - + #include <rtems/system.h> #include <bsp.h> #include <bsp/irq.h> @@ -66,9 +66,9 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) /* - * masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. + * masks used to mask off the interrupts. For exmaple, for ILVL2, the + * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 + * and ILVL7. * */ const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = @@ -132,10 +132,10 @@ int BSP_irq_enable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 1; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); @@ -145,10 +145,10 @@ int BSP_irq_disable_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) { int cpm_irq_index; - + if (!is_cpm_irq(irqLine)) return 0; - + cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); } @@ -156,7 +156,7 @@ int BSP_irq_enabled_at_cpm(const rtems_irq_symbolic_name irqLine) int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine) { int siu_irq_index; - + if (!is_siu_irq(irqLine)) return 1; @@ -173,7 +173,7 @@ int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine) if (!is_siu_irq(irqLine)) return 1; - + siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; @@ -199,7 +199,7 @@ int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine) int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -220,14 +220,14 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_cpm_irq(irq->name)) { /* * Enable interrupt at PIC level */ BSP_irq_enable_at_cpm (irq->name); } - + if (is_siu_irq(irq->name)) { /* * Enable interrupt at SIU level @@ -245,7 +245,7 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * Enable interrupt on device */ irq->on(irq); - + _CPU_ISR_Enable(level); return 1; @@ -264,7 +264,7 @@ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { unsigned int level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -296,7 +296,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * Disable interrupt on device @@ -412,7 +412,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[BSP_DECREMENTER].hdl(); _CPU_MSR_SET(msr); @@ -423,12 +423,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) */ #ifdef DISPATCH_HANDLER_STAT loopCounter = 0; -#endif +#endif while (1) { if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { #ifdef DISPATCH_HANDLER_STAT if (loopCounter > maxLoop) maxLoop = loopCounter; -#endif +#endif break; } irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); @@ -443,12 +443,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) * Acknowledge current interrupt. This has no effect on internal level interrupt. */ ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); - + if (cpmIntr) { /* * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. * We must before acknowledege the current irq at CPM level to avoid trigerring - * the interrupt again. + * the interrupt again. */ /* * Acknowledge and get the vector. @@ -468,7 +468,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[irq].hdl(); _CPU_MSR_SET(msr); @@ -481,12 +481,12 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; #ifdef DISPATCH_HANDLER_STAT ++ loopCounter; -#endif +#endif } } - - + + void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) { /* diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h index a3b2f71f0c..49e720a6b5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h @@ -69,7 +69,7 @@ typedef enum { * Some SIU IRQ symbolic name definition. Please note that * INT IRQ are defined but a single one will be used to * redirect all CPM interrupt. - */ + */ BSP_SIU_EXT_IRQ_0 = 0, BSP_SIU_INT_IRQ_0 = 1, @@ -78,19 +78,19 @@ typedef enum { BSP_SIU_EXT_IRQ_2 = 4, BSP_SIU_INT_IRQ_2 = 5, - + BSP_SIU_EXT_IRQ_3 = 6, BSP_SIU_INT_IRQ_3 = 7, - + BSP_SIU_EXT_IRQ_4 = 8, BSP_SIU_INT_IRQ_4 = 9, BSP_SIU_EXT_IRQ_5 = 10, BSP_SIU_INT_IRQ_5 = 11, - + BSP_SIU_EXT_IRQ_6 = 12, BSP_SIU_INT_IRQ_6 = 13, - + BSP_SIU_EXT_IRQ_7 = 14, BSP_SIU_INT_IRQ_7 = 15, /* @@ -110,18 +110,18 @@ typedef enum { BSP_CPM_IRQ_SPI = BSP_CPM_IRQ_LOWEST_OFFSET + 5, BSP_CPM_IRQ_PARALLEL_IO_PC6 = BSP_CPM_IRQ_LOWEST_OFFSET + 6, BSP_CPM_IRQ_TIMER_4 = BSP_CPM_IRQ_LOWEST_OFFSET + 7, - + BSP_CPM_IRQ_PARALLEL_IO_PC7 = BSP_CPM_IRQ_LOWEST_OFFSET + 9, BSP_CPM_IRQ_PARALLEL_IO_PC8 = BSP_CPM_IRQ_LOWEST_OFFSET + 10, BSP_CPM_IRQ_PARALLEL_IO_PC9 = BSP_CPM_IRQ_LOWEST_OFFSET + 11, BSP_CPM_IRQ_TIMER_3 = BSP_CPM_IRQ_LOWEST_OFFSET + 12, - + BSP_CPM_IRQ_PARALLEL_IO_PC10 = BSP_CPM_IRQ_LOWEST_OFFSET + 14, BSP_CPM_IRQ_PARALLEL_IO_PC11 = BSP_CPM_IRQ_LOWEST_OFFSET + 15, BSP_CPM_I2C = BSP_CPM_IRQ_LOWEST_OFFSET + 16, BSP_CPM_RISC_TIMER_TABLE = BSP_CPM_IRQ_LOWEST_OFFSET + 17, BSP_CPM_IRQ_TIMER_2 = BSP_CPM_IRQ_LOWEST_OFFSET + 18, - + BSP_CPM_IDMA2 = BSP_CPM_IRQ_LOWEST_OFFSET + 20, BSP_CPM_IDMA1 = BSP_CPM_IRQ_LOWEST_OFFSET + 21, BSP_CPM_SDMA_CHANNEL_BUS_ERR = BSP_CPM_IRQ_LOWEST_OFFSET + 22, @@ -138,10 +138,10 @@ typedef enum { * Some Processor exception handled as rtems IRQ symbolic name definition */ BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET - + }rtems_irq_symbolic_name; -#define CPM_INTERRUPT +#define CPM_INTERRUPT /* @@ -171,9 +171,9 @@ typedef struct __rtems_irq_connect_data__ { * It is usually called immediately AFTER connecting the interrupt handler. * RTEMS may well need such a function when restoring normal interrupt * processing after a debug session. - * + * */ - rtems_irq_enable on; + rtems_irq_enable on; /* * function for disabling interrupts at device level (ONLY!). * The code will disable it at SIU and CPM level. RATIONALE : anyway @@ -209,7 +209,7 @@ typedef struct { rtems_irq_symbolic_name irqBase; /* * software priorities associated with interrupts. - * if irqPrio [i] > intrPrio [j] it means that + * if irqPrio [i] > intrPrio [j] it means that * interrupt handler hdl connected for interrupt name i * will not be interrupted by the handler connected for interrupt j * The interrupt source will be physically masked at i8259 level. @@ -285,7 +285,7 @@ int BSP_irq_enabled_at_siu (const rtems_irq_symbolic_name irqLine); * 4) perform rescheduling when necessary, * 5) restore the C scratch registers... * 6) restore initial execution flow - * + * */ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*); /* @@ -328,7 +328,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config); * (Re) get info on current RTEMS interrupt management. */ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**); - + extern void BSP_rtems_irq_mng_init(unsigned cpuId); #ifdef __cplusplus diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S index 1d3e1d2fcf..fa877aafaf 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S @@ -1,5 +1,5 @@ /* - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -15,22 +15,22 @@ * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> #include <libcpu/raw_exception.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(decrementer_exception_vector_prolog_code) - + SYM (decrementer_exception_vector_prolog_code): /* * let room for exception frame @@ -38,32 +38,32 @@ SYM (decrementer_exception_vector_prolog_code): stwu r1, - (EXCEPTION_FRAME_END)(r1) stw r4, GPR4_OFFSET(r1) #ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE - /* + /* * save link register */ mflr r4 stw r4, EXC_LR_OFFSET(r1) - /* + /* * make link register contain shared_raw_irq_code_entry * address */ lis r4,shared_raw_irq_code_entry@h ori r4,r4,shared_raw_irq_code_entry@l mtlr r4 - + li r4, ASM_DEC_VECTOR blr #else li r4, ASM_DEC_VECTOR ba shared_raw_irq_code_entry -#endif +#endif PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) - + decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code PUBLIC_VAR(external_exception_vector_prolog_code) - + SYM (external_exception_vector_prolog_code): /* * let room for exception frame @@ -71,12 +71,12 @@ SYM (external_exception_vector_prolog_code): stwu r1, - (EXCEPTION_FRAME_END)(r1) stw r4, GPR4_OFFSET(r1) #ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE - /* + /* * save link register */ mflr r4 stw r4, EXC_LR_OFFSET(r1) - /* + /* * make link register contain shared_raw_irq_code_entry * address */ @@ -90,14 +90,14 @@ SYM (external_exception_vector_prolog_code): li r4, ASM_EXT_VECTOR ba shared_raw_irq_code_entry #endif - + PUBLIC_VAR (external_exception_vector_prolog_code_size) - + external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code PUBLIC_VAR(shared_raw_irq_code_entry) PUBLIC_VAR(C_dispatch_irq_handler) - + .p2align 5 SYM (shared_raw_irq_code_entry): /* @@ -108,17 +108,17 @@ SYM (shared_raw_irq_code_entry): * R4 : vector number */ /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to reenable exception processing */ stw r0, GPR0_OFFSET(r1) stw r2, GPR2_OFFSET(r1) stw r3, GPR3_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r2 mfmsr r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r2, SRR1_FRAME_OFFSET(r1) /* @@ -157,14 +157,14 @@ SYM (shared_raw_irq_code_entry): #ifndef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE mflr r8 #endif - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) -#ifndef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE +#ifndef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE stw r8, EXC_LR_OFFSET(r1) #endif - + /* * Add some non volatile registers to store information * that will be used when returning from C handler @@ -197,9 +197,9 @@ SYM (shared_raw_irq_code_entry): cmpwi r2,0 bne nested mfspr r1, SPRG1 - -nested: - /* + +nested: + /* * Start Incrementing nesting level in R2 */ addi r2,r2,1 @@ -216,7 +216,7 @@ nested: /* store new nesting level in _ISR_Nest_level */ stw r2, _ISR_Nest_level@l(r7) #endif - + addi r6, r6, 1 mfmsr r5 /* @@ -226,7 +226,7 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* * Call C exception handler for decrementer Interrupt frame is passed just @@ -235,7 +235,7 @@ nested: addi r3, r14, 0x8 bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -259,7 +259,7 @@ nested: stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -267,14 +267,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lwz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lwz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -306,12 +306,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -326,21 +326,21 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -348,7 +348,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 @@ -377,7 +377,7 @@ easy_exit: /* * Restore rfi related settings */ - + lwz r4, SRR1_FRAME_OFFSET(r1) lwz r2, SRR0_FRAME_OFFSET(r1) lwz r3, GPR3_OFFSET(r1) diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c index 01d2d14cd4..98406a91b5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_init.c @@ -80,7 +80,7 @@ void BSP_SIU_irq_init() ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel; } -/* +/* * Initialize CPM interrupt management */ void @@ -94,7 +94,7 @@ BSP_CPM_irq_init(void) (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | #else (CICR_SCB_SCC2 | CICR_SCA_SCC1) | -#endif +#endif ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; @@ -105,7 +105,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + BSP_SIU_irq_init(); BSP_CPM_irq_init(); /* @@ -133,7 +133,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. @@ -155,7 +155,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId) if (!mpc8xx_set_exception (&vectorDesc)) { BSP_panic("Unable to initialize RTEMS external raw exception\n"); } -#ifdef TRACE_IRQ_INIT +#ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c index 1c2d20ec70..32c08798f5 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c @@ -7,7 +7,7 @@ * Right now, we only do 10 Mbps, even with the FEC. The function * rtems_enet_driver_attach determines which one to use. Currently, * only one may be used at a time. - * + * * Based on the MC68360 network driver by * W. Eric Norum * Saskatchewan Accelerator Laboratory @@ -180,7 +180,7 @@ static void m860_fec_interrupt_handler () enet_driver[0].rxInterrupts++; rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT); } - + /* * Buffer transmitted or transmitter error? */ @@ -208,7 +208,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) { int i; unsigned char *hwaddr; - + /* * Configure port A * PA15 is enet RxD. Set PAPAR(15) to 1, PADIR(15) to 0. @@ -219,7 +219,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.papar |= 0x303; m8xx.padir &= ~0x303; m8xx.paodr &= ~0x2; - + /* * Configure port C * PC11 is CTS1*. Set PCPAR(11) to 0, PCDIR(11) to 0, and PCSO(11) to 1. @@ -228,7 +228,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.pcpar &= ~0x30; m8xx.pcdir &= ~0x30; m8xx.pcso |= 0x30; - + /* * Connect CLK1 and CLK2 to SCC1 in the SICR. * CLK1 is TxClk, CLK2 is RxClk. No grant mechanism, SCC1 is directly @@ -237,22 +237,22 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) * T1CS = 0b100 (CLK1) */ m8xx.sicr |= 0x2C; - + /* * Initialize SDMA configuration register */ m8xx.sdcr = 1; - + /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers"); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -260,46 +260,46 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx; m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx; - + /* * Send "Init parameters" command */ m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1); - + /* * Set receive and transmit function codes */ m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0); m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0); - + /* * Set maximum receive buffer length */ m8xx.scc1p.mrblr = RBUF_SIZE; - + /* * Set CRC parameters */ m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF; m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3; - + /* * Clear diagnostic counters */ m8xx.scc1p.un.ethernet.crcec = 0; m8xx.scc1p.un.ethernet.alec = 0; m8xx.scc1p.un.ethernet.disfc = 0; - + /* * Set pad value */ m8xx.scc1p.un.ethernet.pads = 0x8888; - + /* * Set retry limit */ m8xx.scc1p.un.ethernet.ret_lim = 15; - + /* * Set maximum and minimum frame length */ @@ -307,7 +307,7 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.scc1p.un.ethernet.minflr = 64; m8xx.scc1p.un.ethernet.maxd1 = MAX_MTU_SIZE; m8xx.scc1p.un.ethernet.maxd2 = MAX_MTU_SIZE; - + /* * Clear group address hash table */ @@ -315,21 +315,21 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.scc1p.un.ethernet.gaddr2 = 0; m8xx.scc1p.un.ethernet.gaddr3 = 0; m8xx.scc1p.un.ethernet.gaddr4 = 0; - + /* * Set our physical address */ hwaddr = sc->arpcom.ac_enaddr; - + m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4]; m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2]; m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0]; - + /* * Aggressive retry */ m8xx.scc1p.un.ethernet.p_per = 0; - + /* * Clear individual address hash table */ @@ -337,14 +337,14 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) m8xx.scc1p.un.ethernet.iaddr2 = 0; m8xx.scc1p.un.ethernet.iaddr3 = 0; m8xx.scc1p.un.ethernet.iaddr4 = 0; - + /* * Clear temp address */ m8xx.scc1p.un.ethernet.taddr_l = 0; m8xx.scc1p.un.ethernet.taddr_m = 0; m8xx.scc1p.un.ethernet.taddr_h = 0; - + /* * Set up receive buffer descriptors */ @@ -361,12 +361,12 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) } sc->txBdHead = sc->txBdTail = 0; sc->txBdActiveCount = 0; - + /* * Clear any outstanding events */ m8xx.scc1.scce = 0xFFFF; - + /* * Set up interrupts */ @@ -374,20 +374,20 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) rtems_panic ("Can't attach M8xx SCC1 interrupt handler\n"); } m8xx.scc1.sccm = 0; /* No interrupts unmasked till necessary */ - + /* * Set up General SCC Mode Register * Ethernet configuration */ m8xx.scc1.gsmr_h = 0x0; m8xx.scc1.gsmr_l = 0x1088000c; - + /* * Set up data synchronization register * Ethernet synchronization pattern */ m8xx.scc1.dsr = 0xd555; - + /* * Set up protocol-specific mode register * No Heartbeat check @@ -405,13 +405,13 @@ m8xx_enet_initialize (struct m8xx_enet_struct *sc) * Disable full-duplex operation */ m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100); - + /* * Enable the TENA (RTS1*) pin */ m8xx.pcpar |= 0x1; m8xx.pcdir &= ~0x1; - + /* * Enable receiver and transmitter */ @@ -452,7 +452,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) */ m8xx.fec.ecntrl=0x1; - /* + /* * Put ethernet transciever in reset */ m8xx.pgcra |= 0x80; @@ -471,10 +471,10 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) /* * Set SIU interrupt level to LVL2 - * + * */ m8xx.fec.ivec = ((((unsigned) BSP_FAST_ETHERNET_CTRL)/2) << 29); - + /* * Set the TX and RX fifo sizes. For now, we'll split it evenly */ @@ -487,7 +487,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) * Set our physical address */ hwaddr = sc->arpcom.ac_enaddr; - + m8xx.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) | (hwaddr[2] << 8) | (hwaddr[3] << 0); m8xx.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16); @@ -506,13 +506,13 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) /* * Allocate mbuf pointers */ - sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, + sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); - sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, + sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); if (!sc->rxMbuf || !sc->txMbuf) rtems_panic ("No memory for mbuf pointers"); - + /* * Set receiver and transmitter buffer descriptor bases */ @@ -520,7 +520,7 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) sc->txBdBase = m8xx_bd_allocate(sc->txBdCount); m8xx.fec.r_des_start = (int)sc->rxBdBase; m8xx.fec.x_des_start = (int)sc->txBdBase; - + /* * Set up Receive Control Register: * Not promiscuous mode @@ -554,17 +554,17 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) m8xx.sdcr = 1; /* - * Set MII speed to 2.5 MHz for 25 Mhz system clock + * Set MII speed to 2.5 MHz for 25 Mhz system clock */ m8xx.fec.mii_speed = 0x0a; m8xx.fec.mii_data = 0x58021000; - + /* * Set up receive buffer descriptors */ for (i = 0 ; i < sc->rxBdCount ; i++) (sc->rxBdBase + i)->status = 0; - + /* * Set up transmit buffer descriptors */ @@ -574,13 +574,13 @@ m860_fec_initialize_hardware (struct m860_enet_struct *sc) } sc->txBdHead = sc->txBdTail = 0; sc->txBdActiveCount = 0; - - + + /* * Mask all FEC interrupts and clear events */ - m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | + m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT | M8xx_FEC_IEVENT_RFINT; m8xx.fec.ievent = ~0; @@ -610,7 +610,7 @@ m8xx_Enet_retire_tx_bd (struct m8xx_enet_struct *sc) int i; int nRetired; struct mbuf *m, *n; - + i = sc->txBdTail; nRetired = 0; while ((sc->txBdActiveCount != 0) @@ -636,7 +636,7 @@ m8xx_Enet_retire_tx_bd (struct m8xx_enet_struct *sc) enet_driver[0].txRetryLimit++; if (status & M8xx_BD_UNDERRUN) enet_driver[0].txUnderrun++; - + /* * Restart the transmitter */ @@ -682,7 +682,7 @@ scc_rxDaemon (void *arg) uint16_t status; m8xxBufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -699,14 +699,14 @@ scc_rxDaemon (void *arg) break; } } - + /* * Input packet handling loop */ rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -715,7 +715,7 @@ scc_rxDaemon (void *arg) * Clear old events */ m8xx.scc1.scce = 0x8; - + /* * Wait for packet * Note that the buffer descriptor is checked @@ -725,19 +725,19 @@ scc_rxDaemon (void *arg) */ while ((status = rxBd->status) & M8xx_BD_EMPTY) { rtems_event_set events; - + /* * Unmask RXF (Full frame received) event */ m8xx.scc1.sccm |= 0x8; - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); } } - + /* * Check that packet is valid */ @@ -756,12 +756,12 @@ scc_rxDaemon (void *arg) * FIXME: Packet filtering hook could be done here. */ struct ether_header *eh; - + /* * Invalidate the buffer for this descriptor */ rtems_cache_invalidate_multiple_data_lines((const void *)rxBd->buffer, rxBd->length); - + m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint32_t) - @@ -769,7 +769,7 @@ scc_rxDaemon (void *arg) eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - + /* * Allocate a new mbuf */ @@ -800,13 +800,13 @@ scc_rxDaemon (void *arg) if (status & M8xx_BD_COLLISION) sc->rxCollision++; } - + /* * Reenable the buffer descriptor */ rxBd->status = (status & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) | M8xx_BD_EMPTY; - + /* * Move to next buffer descriptor */ @@ -826,7 +826,7 @@ fec_rxDaemon (void *arg) uint16_t status; m8xxBufferDescriptor_t *rxBd; int rxBdIndex; - + /* * Allocate space for incoming packets and start reception */ @@ -844,14 +844,14 @@ fec_rxDaemon (void *arg) break; } } - + /* * Input packet handling loop */ rxBdIndex = 0; for (;;) { rxBd = sc->rxBdBase + rxBdIndex; - + /* * Wait for packet if there's not one ready */ @@ -860,7 +860,7 @@ fec_rxDaemon (void *arg) * Clear old events */ m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT; - + /* * Wait for packet * Note that the buffer descriptor is checked @@ -870,19 +870,19 @@ fec_rxDaemon (void *arg) */ while ((status = rxBd->status) & M8xx_BD_EMPTY) { rtems_event_set events; - + /* * Unmask RXF (Full frame received) event */ m8xx.fec.ievent |= M8xx_FEC_IEVENT_RFINT; - + rtems_bsdnet_event_receive (INTERRUPT_EVENT, RTEMS_WAIT|RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &events); } } - + /* * Check that packet is valid */ @@ -892,12 +892,12 @@ fec_rxDaemon (void *arg) * FIXME: Packet filtering hook could be done here. */ struct ether_header *eh; - + /* * Invalidate the buffer for this descriptor */ rtems_cache_invalidate_multiple_data_lines((const void *)rxBd->buffer, rxBd->length); - + m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - sizeof(uint32_t) - @@ -905,7 +905,7 @@ fec_rxDaemon (void *arg) eh = mtod (m, struct ether_header *); m->m_data += sizeof(struct ether_header); ether_input (ifp, eh, m); - + /* * Allocate a new mbuf */ @@ -958,12 +958,12 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) struct mbuf *l = NULL; uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m8xx_Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -982,7 +982,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8xx.scc1.scce = 0x12; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -998,7 +998,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TXB (buffer transmitted) and * TXE (transmitter error) events. @@ -1011,13 +1011,13 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8xx_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -1037,7 +1037,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) * Flush the buffer for this descriptor */ rtems_cache_flush_multiple_data_lines((const void *)txBd->buffer, txBd->length); - + sc->txMbuf[sc->txBdHead] = m; nAdded++; if (++sc->txBdHead == sc->txBdCount) { @@ -1057,7 +1057,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) if (l != NULL) l->m_next = m; } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -1086,12 +1086,12 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) /* struct mbuf *l = NULL; */ uint16_t status; int nAdded; - + /* * Free up buffer descriptors */ m8xx_Enet_retire_tx_bd (sc); - + /* * Set up the transmit buffer descriptors. * No need to pad out short packets since the @@ -1110,7 +1110,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) * Clear old events */ m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT; - + /* * Wait for buffer descriptor to become available. * Note that the buffer descriptors are checked @@ -1126,7 +1126,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { rtems_event_set events; - + /* * Unmask TXB (buffer transmitted) and * TXE (transmitter error) events. @@ -1139,13 +1139,13 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) m8xx_Enet_retire_tx_bd (sc); } } - + /* * Don't set the READY flag till the * whole packet has been readied. */ status = nAdded ? M8xx_BD_READY : 0; - + /* * FIXME: Why not deal with empty mbufs at at higher level? * The IP fragmentation routine in ip_output @@ -1160,12 +1160,12 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) */ txBd->buffer = mtod (m, void *); txBd->length = m->m_len; - + /* * Flush the buffer for this descriptor */ rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length); - + sc->txMbuf[sc->txBdHead] = m; nAdded++; if (++sc->txBdHead == sc->txBdCount) { @@ -1187,7 +1187,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) l->m_next = m; */ } - + /* * Set the transmit buffer status. * Break out of the loop if this mbuf is the last in the frame. @@ -1219,13 +1219,13 @@ scc_txDaemon (void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -1251,16 +1251,16 @@ fec_txDaemon (void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; struct mbuf *m; rtems_event_set events; - + for (;;) { /* * Wait for packet */ - rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, - RTEMS_EVENT_ANY | RTEMS_WAIT, - RTEMS_NO_TIMEOUT, + rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, + RTEMS_EVENT_ANY | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, &events); - + /* * Send packets till queue is empty */ @@ -1286,7 +1286,7 @@ static void m8xx_enet_start (struct ifnet *ifp) { struct m8xx_enet_struct *sc = ifp->if_softc; - + rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); ifp->if_flags |= IFF_OACTIVE; } @@ -1300,22 +1300,22 @@ scc_init (void *arg) { struct m8xx_enet_struct *sc = arg; struct ifnet *ifp = &sc->arpcom.ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m8xx_enet_initialize (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, scc_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, scc_rxDaemon, sc); - + } - + /* * Set flags appropriately */ @@ -1323,12 +1323,12 @@ scc_init (void *arg) m8xx.scc1.psmr |= 0x200; else m8xx.scc1.psmr &= ~0x200; - + /* * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -1342,22 +1342,22 @@ fec_init (void *arg) { struct m8xx_enet_struct *sc = arg; struct ifnet *ifp = &sc->arpcom.ac_if; - + if (sc->txDaemonTid == 0) { - + /* * Set up SCC hardware */ m8xx_fec_initialize_hardware (sc); - + /* * Start driver tasks */ sc->txDaemonTid = rtems_bsdnet_newproc ("SCtx", 4096, fec_txDaemon, sc); sc->rxDaemonTid = rtems_bsdnet_newproc ("SCrx", 4096, fec_rxDaemon, sc); - + } - + /* * Set flags appropriately */ @@ -1366,12 +1366,12 @@ fec_init (void *arg) else m8xx.fec.r_cntrl &= ~0x8; - + /* * Tell the world that we're running. */ ifp->if_flags |= IFF_RUNNING; - + /* * Enable receiver and transmitter */ @@ -1387,9 +1387,9 @@ static void scc_stop (struct m8xx_enet_struct *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -1402,9 +1402,9 @@ static void fec_stop (struct m8xx_enet_struct *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; - + ifp->if_flags &= ~IFF_RUNNING; - + /* * Shut down receiver and transmitter */ @@ -1429,7 +1429,7 @@ enet_stats (struct m8xx_enet_struct *sc) printf (" Overrun:%-8lu", sc->rxOverrun); printf (" Collision:%-8lu\n", sc->rxCollision); printf (" Discarded:%-8lu\n", (unsigned long)m8xx.scc1p.un.ethernet.disfc); - + printf (" Tx Interrupts:%-8lu", sc->txInterrupts); printf (" Deferred:%-8lu", sc->txDeferred); printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); @@ -1449,37 +1449,37 @@ scc_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m8xx_enet_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: ether_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: scc_stop (sc); break; - + case IFF_UP: scc_init (sc); break; - + case IFF_UP | IFF_RUNNING: scc_stop (sc); scc_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: enet_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -1497,37 +1497,37 @@ fec_ioctl (struct ifnet *ifp, int command, caddr_t data) { struct m8xx_enet_struct *sc = ifp->if_softc; int error = 0; - + switch (command) { case SIOCGIFADDR: case SIOCSIFADDR: ether_ioctl (ifp, command, data); break; - + case SIOCSIFFLAGS: switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { case IFF_RUNNING: fec_stop (sc); break; - + case IFF_UP: fec_init (sc); break; - + case IFF_UP | IFF_RUNNING: fec_stop (sc); fec_init (sc); break; - + default: break; } break; - + case SIO_RTEMS_SHOW_STATS: enet_stats (sc); break; - + /* * FIXME: All sorts of multicast commands need to be added here! */ @@ -1575,12 +1575,12 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) printf ("Driver already in use.\n"); return 0; } - + /* * Process options */ #if NVRAM_CONFIGURE == 1 - + /* Configure from NVRAM */ if ( (addr = nvram->ipaddr) ) { /* We have a non-zero entry, copy the value */ @@ -1589,7 +1589,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) else rtems_panic("Can't allocate ip_address buffer!\n"); } - + if ( (addr = nvram->netmask) ) { /* We have a non-zero entry, copy the value */ if ( (pAddr = malloc ( INET_ADDR_MAX_BUF_SIZE, 0, M_NOWAIT )) ) @@ -1601,7 +1601,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) /* Ethernet address requires special handling -- it must be copied into * the arpcom struct. The following if construct serves only to give the * User Area NVRAM parameter the highest priority. - * + * * If the ethernet address is specified in NVRAM, go ahead and copy it. * (ETHER_ADDR_LEN = 6 bytes). */ @@ -1619,9 +1619,9 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) */ rtems_panic("No Ethernet address specified!\n"); } - + #else /* NVRAM_CONFIGURE != 1 */ - + if (config->hardware_address) { memcpy (sc->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); } @@ -1631,7 +1631,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) */ rtems_panic("No Ethernet address specified!\n"); } - + #endif /* NVRAM_CONFIGURE != 1 */ if (config->mtu) @@ -1647,7 +1647,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -1662,7 +1662,7 @@ rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ @@ -1701,7 +1701,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) printf ("Driver already in use.\n"); return 0; } - + /* * Process options */ @@ -1724,7 +1724,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) else sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; sc->acceptBroadcast = !config->ignore_broadcast; - + /* * Set up network interface values */ @@ -1739,7 +1739,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; if (ifp->if_snd.ifq_maxlen == 0) ifp->if_snd.ifq_maxlen = ifqmaxlen; - + /* * Attach the interface */ @@ -1753,7 +1753,7 @@ rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config) int rtems_enet_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) { - + #ifdef MPC860T if ((m8xx.fec.mii_data & 0xffff) == 0x2000) { /* rtems_scc1_driver_attach(config);*/ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c index 0c853fabaf..2fc1a2f194 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c @@ -57,13 +57,13 @@ void bsp_libc_init( void *, uint32_t, int ); void BSP_panic(char *s) { printk("%s PANIC %s\n",_RTEMS_version, s); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } void _BSP_Fatal_error(unsigned int v) { printk("%s PANIC ERROR %x\n",_RTEMS_version, v); - __asm__ __volatile ("sc"); + __asm__ __volatile ("sc"); } /* @@ -75,7 +75,7 @@ void _BSP_Fatal_error(unsigned int v) * Must not use libc (to do io) from here, since drivers are not yet * initialized. * - * Installed in the rtems_cpu_table defined in + * Installed in the rtems_cpu_table defined in * rtems/c/src/exec/score/cpu/m68k/cpu.h in main() below. Called from * rtems_initialize_executive() defined in rtems/c/src/exec/sapi/src/init.c * @@ -87,7 +87,7 @@ void _BSP_Fatal_error(unsigned int v) */ void bsp_pretasking_hook(void) { - /* + /* * These are assigned addresses in the linkcmds file for the BSP. This * approach is better than having these defined as manifest constants and * compiled into the kernel, but it is still not ideal when dealing with @@ -101,7 +101,7 @@ void bsp_pretasking_hook(void) extern unsigned char _HeapEnd; bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 ); - + #ifdef RTEMS_DEBUG rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); #endif @@ -135,11 +135,11 @@ void bsp_pretasking_hook(void) void bsp_start(void) { extern void *_WorkspaceBase; - + ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; register unsigned char* intrStack; - + /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... @@ -148,7 +148,7 @@ void bsp_start(void) myCpuRevision = get_ppc_cpu_revision(); mmu_init(); - + /* * Enable instruction and data caches. Do not force writethrough mode. */ @@ -168,7 +168,7 @@ void bsp_start(void) /* * Initialize some SPRG registers related to irq handling */ - + intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); _write_SPRG1((unsigned int)intrStack); /* signal them that we have fixed PR288 - eventually, this should go away */ @@ -217,7 +217,7 @@ void bsp_start(void) Cpu_table.timer_least_valid = 3; #endif - /* + /* * Call this in case we use TERMIOS for console I/O */ m8xx_uart_reserve_resources( &BSP_Configuration ); @@ -232,6 +232,6 @@ void bsp_start(void) BSP_rtems_irq_mng_init(0); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); -#endif +#endif } diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c index 676d473051..19d8c59b77 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @@ -18,7 +18,7 @@ * in the SIU when it takes control, but does not restore it before * returning control to the program. We thus keep a copy of the * register, and restore it from gdb using the hook facilities. - * + * * We arrange for simask_copy to be initialized to zero so that * it resides in the .data section. This avoids having gdb set * the mask to crud before we get to initialize explicitly. Of @@ -35,11 +35,11 @@ uint32_t simask_copy = 0; * number MBXA/PG1. We are assuming that the values in MBXA/PG1 * are for the older MBX boards whose part number does not have * the "B" suffix, but we have discovered that the values from - * MBXA/PG2 work better, even for the older boards. - * + * MBXA/PG2 work better, even for the older boards. + * * THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and * MBX860-002. USE WITH CARE! - * + * * NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B * as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz. * We think the MBX821_001B is an entry level board and thus is 50 MHz, @@ -58,7 +58,7 @@ static uint32_t upmaTable[64] = { * initialized by EPPCBug 1.1. In particular, the original * burst-write values do not work! Also, the following values * facilitate higher performance. - */ + */ /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, @@ -83,7 +83,7 @@ static uint32_t upmaTable[64] = { 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - + /* Exception. (offset 0x3c in UPM RAM) */ 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 @@ -109,14 +109,14 @@ static uint32_t upmaTable[64] = { /* 40 MHz MBX */ /* - * Note: For the older MBX models (i.e. without the "b" + * Note: For the older MBX models (i.e. without the "b" * suffix, e.g. mbx860_001), the following values (from the * MBXA/PG2 manual) work better than, but are different * from those published in the original MBXA/PG1 manual and * initialized by EPPCBug 1.1. In particular, the following * burst-read and burst-write values facilitate higher * performance. - */ + */ /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, @@ -141,7 +141,7 @@ static uint32_t upmaTable[64] = { 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - + /* Exception. (offset 0x3c in UPM RAM) */ 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 #else @@ -157,14 +157,14 @@ void _InitMBX8xx (void) register uint32_t r1, i; extern uint32_t simask_copy; - /* + /* * Initialize the Debug Enable Register (DER) to an appropriate - * value for EPPCBug debugging. + * value for EPPCBug debugging. * (This value should also work for BDM debugging.) */ r1 = 0x70C67C07; /* All except EXTIE, ALIE, DECIE */ _mtspr( M8xx_DER, r1 ); - + /* * Initialize the Instruction Support Control Register (ICTRL) to a * an appropriate value for normal operation. A different value, @@ -172,7 +172,7 @@ void _InitMBX8xx (void) */ r1 = 0x00000007; _mtspr( M8xx_ICTRL, r1 ); - + /* * Disable and invalidate the instruction and data caches. */ @@ -185,7 +185,7 @@ void _InitMBX8xx (void) r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ _mtspr( M8xx_IC_CST, r1 ); _isync; - + r1 = M8xx_CACHE_CMD_DISABLE; _mtspr( M8xx_DC_CST, r1 ); _isync; @@ -214,14 +214,14 @@ void _InitMBX8xx (void) * imd: accessing m8xx.* should not occure before setting up the immr ! */ simask_copy = m8xx.simask; - - /* - * Initialize the SIU Module Configuration Register (SIUMCR) + + /* + * Initialize the SIU Module Configuration Register (SIUMCR) * m8xx.siumcr = 0x00602900, the default MBX and firmware value. */ - m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | + m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME; - + /* * Initialize the System Protection Control Register (SYPCR). * The SYPCR can only be written once after Reset. @@ -229,39 +229,39 @@ void _InitMBX8xx (void) * - Disable software watchdog timer * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value. */ - m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | + m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | M8xx_SYPCR_BME | M8xx_SYPCR_SWF; /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */ m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */ - + /* Initialize the Transfer Error Status Register (TESR) */ m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */ - + /* Initialize the SDMA Configuration Register (SDCR) */ m8xx.sdcr = 0x00000001; /* Default firmware value. */ - + /* * Initialize the Timebase Status and Control Register (TBSCR) * m8xx.tbscr = 0x00C3, default MBX and firmware value. */ m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */ - m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | + m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | M8xx_TBSCR_TBF | M8xx_TBSCR_TBE; - + /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */ m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */ m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */ - + /* Unlock other Real-Time Clock registers */ m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */ m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */ m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */ - + /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */ m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */ m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ - + /* Initialize the System Clock and Reset Control Register (SCCR) * Set the clock sources and division factors: * Timebase Source is GCLK2 / 16 @@ -299,18 +299,18 @@ void _InitMBX8xx (void) defined(mbx821_005)) m8xx.plprcr = 0x4C400000; #else -#error "MBX board not defined" +#error "MBX board not defined" #endif /* Unlock the timebase and decrementer registers. */ m8xx.tbk = M8xx_UNLOCK_KEY; - /* + /* * Initialize decrementer register to a large value to * guarantee that a decrementer interrupt will not be * generated before the kernel is fully initialized. */ r1 = 0x7FFFFFFF; _mtspr( M8xx_DEC, r1 ); - + /* Initialize the timebase register (TB is 64 bits) */ r1 = 0x00000000; _mtspr( M8xx_TBU_WR, r1 ); @@ -322,24 +322,24 @@ void _InitMBX8xx (void) /* * User Programmable Machine A (UPMA) Initialization - * + * * If this initialization code is running from DRAM, it is very * dangerous to change the value of any UPMA Ram array word from * what the firmware (EPPCBug) initialized it to. Thus we don't * initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug * has done the appropriate initialization. - * + * * An exception to our rule, is that, for the older MBX boards * (those without the "B" suffix, e.g. MBX821-001 and MBX860-002), * we do re-initialize the burst-read and burst-write values with * values that are more efficient. Also, in the MBX821 case, - * the burst-write original values set by EPPCBug do not work! + * the burst-write original values set by EPPCBug do not work! * This change can be done safely because the caches have not yet * been activated. * * The RAM array of UPMA is initialized by writing to each of * its 64 32-bit RAM locations. - * Note: UPM register initialization should occur before + * Note: UPM register initialization should occur before * initialization of the corresponding BRx and ORx registers. */ #if ( !defined(EPPCBUG_VECTORS) ) @@ -373,27 +373,27 @@ void _InitMBX8xx (void) #if ( !defined(EPPCBUG_VECTORS) ) /* * Initialize the memory periodic timer. - * Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) + * Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) * m8xx.mptpr = 0x0200; */ m8xx.mptpr = M8xx_MPTPR_PTP(0x2); - + /* * Initialize the Machine A Mode Register (MAMR) - * + * * ASSUMES THAT DIMMs ARE NOT INSTALLED! - * + * * Without DIMMs: * m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz). - * + * * With DIMMs: * m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz). */ #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) - m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | + m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; #else - m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | + m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; #endif #endif /* ! defined(EPPCBUG_VECTORS) */ @@ -416,31 +416,31 @@ void _InitMBX8xx (void) * FC000000 FC7FFFFF 7 8 N N GPCM Y Y Socketed FLASH Memory * * z = 3 for 4MB installed on the motherboard, z = F for 16M - * + * * NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4. * This table assumes that the 32-bit soldered flash device is the boot ROM. */ /* * CS0 : Soldered (32-bit) Flash Memory at 0xFE000000 - * + * * CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING! * (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to * access whatever flash device is not selected during hard reset.) - * + * * MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that * "EPPCBUG configures the reset flash device at the lower address, and the * nonreset flash device at the higher address." If we take reset flash device * to mean the boot flash memory, then the statement must mean that BR0 must * point to the device at the lower address, i.e. 0xFC000000, while BR7 must * point to the device at the highest address, i.e. 0xFE000000. - * + * * THIS IS NOT THE CASE! - * + * * The boot flash is always configured to start at 0xFE000000, and the other * one to start at 0xFC000000. Changing jumper J4 only changes the width of * the memory ports into these two region. - * + * * BR0 = 0xFE000001 * Base addr [0-16] 0b11111110000000000 = 0xFE000000 * Address type [17-19] 0b000 @@ -464,7 +464,7 @@ void _InitMBX8xx (void) * * m8xx.memc[0]._or = 0xFF800930 (40 MHz) * m8xx.memc[0]._or = 0xFF800940 (50 MHz) - * m8xx.memc[0]._br = 0xFE000001 + * m8xx.memc[0]._br = 0xFE000001 */ #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | @@ -476,13 +476,13 @@ void _InitMBX8xx (void) m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - /* + /* * CS1 : Local DRAM Memory at 0x00000000 * m8xx.memc[1]._or = 0xFFC00400; * m8xx.memc[1]._br = 0x00000081; */ #if ( defined(mbx860_001b) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | + m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); #elif ( defined(mbx860_002b) || \ defined(mbx860_003b) || \ @@ -495,7 +495,7 @@ void _InitMBX8xx (void) defined(mbx821_001) || \ defined(mbx821_002) || \ defined(mbx821_003) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | + m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); #elif ( defined(mbx860_004) || \ defined(mbx860_005) || \ @@ -507,7 +507,7 @@ void _InitMBX8xx (void) defined(mbx821_004b) || \ defined(mbx821_005b) || \ defined(mbx821_006b) ) - m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | + m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); #else #error "MBX board not defined" @@ -515,28 +515,28 @@ void _InitMBX8xx (void) m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V; - /* - * CS2 : DIMM Memory - Bank #0, not present + /* + * CS2 : DIMM Memory - Bank #0, not present * m8xx.memc[2]._or = 0x00000400; * m8xx.memc[2]._br = 0x00000080; */ - m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | + m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); m8xx.memc[2]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ - /* - * CS3 : DIMM Memory - Bank #1, not present + /* + * CS3 : DIMM Memory - Bank #1, not present * m8xx.memc[3]._or = 0x00000400; * m8xx.memc[3]._br = 0x00000080; */ - m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | + m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); m8xx.memc[3]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ /* - * CS4 : Battery-Backed SRAM at 0xFA000000 + * CS4 : Battery-Backed SRAM at 0xFA000000 * m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz * m8xx.memc[4]._br = 0xFA000401; */ @@ -551,7 +551,7 @@ void _InitMBX8xx (void) M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; /* - * CS5 : PCI I/O and Memory at 0x80000000 + * CS5 : PCI I/O and Memory at 0x80000000 * m8xx.memc[5]._or = 0xA0000108; * m8xx.memc[5]._br = 0x80000001; */ @@ -560,8 +560,8 @@ void _InitMBX8xx (void) m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - /* - * CS6 : QSPAN Registers at 0xFA210000 + /* + * CS6 : QSPAN Registers at 0xFA210000 * m8xx.memc[6]._or = 0xFFFF0108; * m8xx.memc[6]._br = 0xFA210001; */ @@ -570,8 +570,8 @@ void _InitMBX8xx (void) m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; - /* - * CS7 : Socketed (8-bit) Flash at 0xFC000000 + /* + * CS7 : Socketed (8-bit) Flash at 0xFC000000 * m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz * m8xx.memc[7]._br = 0xFC000401; */ @@ -591,36 +591,36 @@ void _InitMBX8xx (void) * PCMCIA region 0: common memory */ m8xx.pbr0 = PCMCIA_MEM_ADDR; - m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_MEM + m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) + | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_MEM |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); /* * PCMCIA region 1: dma memory */ m8xx.pbr1 = PCMCIA_DMA_ADDR; - m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) - | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_DMA + m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) + | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_DMA |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); /* * PCMCIA region 2: attribute memory */ m8xx.pbr2 = PCMCIA_ATTRB_ADDR; - m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) + m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_ATT |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); /* * PCMCIA region 3: I/O access */ m8xx.pbr3 = PCMCIA_IO_ADDR; - m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB - | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) - | M8xx_PCMCIA_POR_PSL(32) + m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB + | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) + | M8xx_PCMCIA_POR_PSL(32) | M8xx_PCMCIA_POR_PPS_16 | M8xx_PCMCIA_POR_PRS_IO |M8xx_PCMCIA_POR_PSLOT_A | M8xx_PCMCIA_POR_VALID); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c index a252f7d1ac..47b34f3e12 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/mmutlbtab.c @@ -1,7 +1,7 @@ -/* +/* * mmutlbtab.c - * - * This file defines the MMU_TLB_table for the MBX8xx. + * + * This file defines the MMU_TLB_table for the MBX8xx. * * Copyright (c) 1999, National Research Council of Canada * @@ -27,14 +27,14 @@ * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must * not have more than 32 lines in it! * - * We set up the virtual memory map so that virtual address of a + * We set up the virtual memory map so that virtual address of a * location is equal to its real address. */ MMU_TLB_table_t MMU_TLB_table[] = { #if ( defined(mbx860_001b) ) /* - * DRAM: CS1, Start address 0x00000000, 2M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 2M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. * EPN TWC RPN @@ -55,8 +55,8 @@ MMU_TLB_table_t MMU_TLB_table[] = { defined(mbx821_002) || \ defined(mbx821_003) ) /* - * DRAM: CS1, Start address 0x00000000, 4M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 4M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. * EPN TWC RPN @@ -78,10 +78,10 @@ MMU_TLB_table_t MMU_TLB_table[] = { defined(mbx821_005) || \ defined(mbx821_004b) || \ defined(mbx821_005b) || \ - defined(mbx821_006b) ) + defined(mbx821_006b) ) /* - * DRAM: CS1, Start address 0x00000000, 16M, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * DRAM: CS1, Start address 0x00000000, 16M, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ @@ -93,9 +93,9 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * NVRAM: CS4, Start address 0xFA000000, 32K, - * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, + * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, * R/W,X for all, no ASID comparison, cache-inhibited. - * + * * EPN TWC RPN */ { 0xFA000200, 0x01, 0xFA0009FF }, /* NVRAM - PS=16K */ @@ -103,7 +103,7 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * Board Control/Status Register #1/#2: CS4, Start address 0xFA100000, (4 x 8 bits?) - * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, + * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, * R/W,X for all, no ASID comparison, cache-inhibited. * EPN TWC RPN */ @@ -111,10 +111,10 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K, - * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, + * ASID=0x0, APG=0x0, guarded memory, write-through data cache policy, * R/W,X for all, no ASID comparison, cache-inhibited. - * - * Note: We use the value in MBXA/PG2, which is also the value that + * + * Note: We use the value in MBXA/PG2, which is also the value that * EPPC-Bug programmed into our boards. The alternative is the value * in MBXA/PG1: 0xFFA00000. This value might well depend on the revision * of the firmware. @@ -124,7 +124,7 @@ MMU_TLB_table_t MMU_TLB_table[] = { /* * * Flash: CS0, Start address 0xFE000000, 4M, (BootROM-EPPCBug) - * ASID=0x0, APG=0x0, not guarded memory, + * ASID=0x0, APG=0x0, not guarded memory, * R/O,X for all, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ @@ -138,7 +138,7 @@ MMU_TLB_table_t MMU_TLB_table[] = { { 0xFE380200, 0x05, 0xFE380CFD }, /* Flash - PS=512K */ /* * BootROM: CS7, Start address 0xFC000000, 4M?, (socketed FLASH) - * ASID=0x0, APG=0x0, not guarded memory, + * ASID=0x0, APG=0x0, not guarded memory, * R/O,X for all, no ASID comparison, not cache-inhibited. * EPN TWC RPN */ @@ -173,23 +173,23 @@ MMU_TLB_table_t MMU_TLB_table[] = { * For each space (MEM/DMA/ATTRIB/IO) only the first 8MB are mapped * ASID=0x0, APG=0x0, guarded memory, * R/W,X for all, no ASID comparison, cache-inhibited. - * EPN TWC + * EPN TWC * RPN */ - { (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_MEM_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_MEM_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA Memory - PS=8M */ - { (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_DMA_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_DMA_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA DMA - PS=8M */ - { (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_ATTRB_ADDR & 0xfffff000) | 0x9F7 },/* PCMCIA ATTRIB-PS=8M*/ - { (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D, + { (PCMCIA_IO_ADDR & 0xfffff000) | 0x200, 0x1D, (PCMCIA_IO_ADDR & 0xfffff000) | 0x9F7 } /* PCMCIA I/O - PS=8M */ }; -/* +/* * MMU_N_TLB_Table_Entries is defined here because the size of the * MMU_TLB_table is only known in this file. */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S index ebd60be5ab..ed44cfd41c 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S @@ -6,28 +6,28 @@ * all remaining initialization. * * This file is based on several others: - * - * (1) start360.s from the gen68360 BSP by + * + * (1) start360.s from the gen68360 BSP by * W. Eric Norum (eric@skatter.usask.ca) * with the following copyright and license: * * COPYRIGHT (c) 1989-1998. * On-Line Applications Research Corporation (OAR). - * + * * The license and distribution terms for this file may in * the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. * * (2) start.s for the eth_comm port by * Jay Monkman (jmonkman@fracsa.com), - * which itself is based on the - * + * which itself is based on the + * * (3) dlentry.s for the Papyrus BSP, written by: * Andrew Bray <andy@i-cubed.co.uk> * with the following copyright and license: * * COPYRIGHT (c) 1995 by i-cubed ltd. - * + * * (4) start860.S for the MBX821/MBX860, written by: * Darlene A. Stewart <darlene.stewart@iit.nrc.ca> * Copyright (c) 1999, National Research Council of Canada @@ -179,7 +179,7 @@ .L_D4_e: .L_D2: .previous - + /* * Tell C's eabi-ctor's that we have an atexit function, * and that it is to register __do_global_dtors. @@ -188,7 +188,7 @@ PUBLIC_VAR(__atexit) .section ".sdata","aw" .align 2 -SYM(__atexit): +SYM(__atexit): EXT_PROC_REF(atexit)@fixup .previous @@ -198,7 +198,7 @@ SYM(__atexit): .previous /* That should do it */ - + /* * Put the entry point in its own section. That way, we can guarantee * to put it first in the .text section in the linker script. @@ -208,16 +208,16 @@ SYM(__atexit): PUBLIC_VAR (start) SYM(start): bl .startup /* or bl .spin */ -base_addr: +base_addr: /* * Parameters from linker */ -toc_pointer: +toc_pointer: .long __GOT_START__ -bss_length: +bss_length: .long bss.size -bss_addr: +bss_addr: .long bss.start PUBLIC_VAR (text_addr) @@ -230,7 +230,7 @@ text_length: /* * Spin, if necessary, to acquire control from debugger (CodeWarrior). - */ + */ spin: .long 0x0001 .spin: @@ -238,22 +238,22 @@ spin: lwz r3, spin@l(r3) cmpwi r3, 0x1 beq .spin -/* +/* * #define LOADED_BY_EPPCBUG */ #define LOADED_BY_EPPCBUG -#define EARLY_CONSOLE +#define EARLY_CONSOLE /* - * Initialization code + * Initialization code */ -.startup: +.startup: /* Get the start address. */ mflr r1 -#ifdef LOADED_BY_EPPCBUG +#ifdef LOADED_BY_EPPCBUG /* Save pointer to residual/board data */ lis r9,eppcbugInfo@ha stw r3,eppcbugInfo@l(r9) -#endif +#endif /* Initialize essential registers. */ bl initregs nop @@ -272,24 +272,24 @@ spin: EXTERN_PROC (_InitMBX8xx) bl PROC (_InitMBX8xx) nop - + /* Clear the bss section. */ bl bssclr nop #if defined(EARLY_CONSOLE) && defined(LOADED_BY_EPPCBUG) EXTERN_PROC (serial_init) bl PROC (serial_init) -#endif +#endif lis r5,environ@ha la r5,environ@l(r5) /* environp */ /* clear argc and argv */ xor r3, r3, r3 xor r4, r4, r4 - + EXTERN_PROC (boot_card) bl PROC (boot_card) /* call the first C routine */ nop - + /* we should never return from boot_card, but in case we do ... */ /* The next instructions are dependent on your runtime environment */ @@ -297,14 +297,14 @@ spin: lis r10, 0x0400 /* Data cache disable */ mtspr 568, r10 isync - + mtspr 560, r10 /* Instruction cache disable */ isync - + stop_here: li r10, 0x0F00 /* .RETURN */ sc - + b stop_here nop @@ -320,13 +320,13 @@ bssclr: rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */ beqlr /* no bss - return */ mtctr r5 /* set ctr reg */ - + li r5,0x0000 /* r5 = 0 */ clear_bss: stw r5,0(r4) /* store r6 */ addi r4,r4,0x4 /* update r4 */ bdnz clear_bss /* dec counter and loop */ - + blr /* return */ /* @@ -337,24 +337,24 @@ clear_bss: * r0 - scratch */ initregs: - /* + /* * Disable address translation. We should already be running in real space, * so this should be a no-op, i.e. no need to switch instruction stream * addresses from virtual space to real space. Other bits set the processor * for big-endian mode, exceptions vectored to 0x000n_nnnn (vectors are * already in low memory!), no execution tracing, machine check exceptions - * enabled, floating-point not available (MPC8xx has none), supervisor + * enabled, floating-point not available (MPC8xx has none), supervisor * priviledge level, external interrupts disabled, power management * disabled (normal operation mode). */ li r0, 0x1000 /* MSR_ME */ mtmsr r0 /* Context-synchronizing */ isync - + /* * Clear the exception handling registers. * Note SPRG3 is reserved for use by EPPCBug on the MBX8xx. - */ + */ li r0, 0x0000 mtdar r0 mtspr sprg0, r0 @@ -362,13 +362,13 @@ initregs: mtspr sprg2, r0 mtspr srr0, r0 mtspr srr1, r0 - + mr r6, r0 mr r7, r0 mr r8, r0 mr r9, r0 mr r10, r0 - mr r11, r0 + mr r11, r0 mr r12, r0 mr r13, r0 mr r14, r0 @@ -389,9 +389,9 @@ initregs: mr r29, r0 mr r30, r0 mr r31, r0 - + blr /* return */ - + .L_text_e: .comm environ,4,4 diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S index d634cc8b88..14720aee38 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S +++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.S @@ -2,26 +2,26 @@ * (c) 1999, Eric Valette valette@crf.canon.fr * * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * exception veneers for RTEMS. * * $Id$ */ - + #include <rtems/asm.h> #include <rtems/score/cpu.h> #include <bsp/vectors.h> - + #define SYNC \ sync; \ isync - + .text - .p2align 5 - + .p2align 5 + PUBLIC_VAR(default_exception_vector_code_prolog) SYM (default_exception_vector_code_prolog): /* @@ -34,7 +34,7 @@ SYM (default_exception_vector_code_prolog): stw r2, EXC_LR_OFFSET(r1) bl 0f 0: /* - * r3 = exception vector entry point + * r3 = exception vector entry point * (256 * vector number) + few instructions */ mflr r3 @@ -42,21 +42,21 @@ SYM (default_exception_vector_code_prolog): * r3 = r3 >> 8 = vector */ srwi r3,r3,8 -#ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE +#ifdef THIS_CODE_LINKED_USING_FLASH_ADDR_RANGE lis r2,push_normalized_frame@h ori r2,r2,push_normalized_frame@l mtlr r2 blr #else ba push_normalized_frame -#endif - +#endif + PUBLIC_VAR (default_exception_vector_code_prolog_size) - + default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog - + .p2align 5 -PUBLIC_VAR (push_normalized_frame) +PUBLIC_VAR (push_normalized_frame) SYM (push_normalized_frame): stw r3, EXCEPTION_NUMBER_OFFSET(r1) stw r0, GPR0_OFFSET(r1) @@ -70,7 +70,7 @@ SYM (push_normalized_frame): * Saved a few line above : R0 * * Manual says that "stmw" instruction may be slower than - * series of individual "stw" but who cares about performance + * series of individual "stw" but who cares about performance * for the DEFAULT exception handler? */ stmw r4, GPR4_OFFSET(r1) /* save R4->R31 */ @@ -96,7 +96,7 @@ SYM (push_normalized_frame): ori r3,r3, MSR_RI | MSR_IR | MSR_DR mtmsr r3 SYNC - + /* * Call C exception handler */ @@ -137,12 +137,12 @@ SYM (push_normalized_frame): /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h index fc841f0fa2..43fb7ecedf 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h +++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -16,10 +16,10 @@ #define LIBBSP_POWERPC_MBX8XX_VECTORS_H /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -81,7 +81,7 @@ extern int default_exception_vector_code_prolog_size; * zero, it performs more or less like memmove. No copy is performed if * source and destination addresses are equal. However the caches * are synchronized. Note that the size is always rounded up to the - * next mutiple of 4. + * next mutiple of 4. */ extern void * codemove(void *, const void *, unsigned int, unsigned long); extern void initialize_exceptions(); diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c index 1aaae35f5e..5c97bb892e 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -25,7 +25,7 @@ exception_handler_t globalExceptHdl; void C_exception_handler(BSP_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -69,7 +69,7 @@ void C_exception_handler(BSP_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; |