summaryrefslogtreecommitdiffstats
path: root/bsps/shared/dev/irq/arm-gicv3.c
diff options
context:
space:
mode:
Diffstat (limited to 'bsps/shared/dev/irq/arm-gicv3.c')
-rw-r--r--bsps/shared/dev/irq/arm-gicv3.c35
1 files changed, 27 insertions, 8 deletions
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 4772ff5db4..958b1061bd 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -1,6 +1,15 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup DevIRQGIC
*
+ * @brief This source file contains the implementation of the generic GICv3
+ * support.
+ */
+
+/*
* Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
*
* Redistribution and use in source and binary forms, with or without
@@ -27,18 +36,24 @@
#include <dev/irq/arm-gicv3.h>
-#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/start.h>
+#include <rtems/score/processormaskimpl.h>
void bsp_interrupt_dispatch(void)
{
- uint32_t icciar = READ_SR(ICC_IAR1);
- rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
- rtems_vector_number spurious = 1023;
+ while (true) {
+ uint32_t icciar = READ_SR(ICC_IAR1);
+ rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+ uint32_t status;
- if (vector != spurious) {
- arm_interrupt_handler_dispatch(vector);
+ if (!bsp_interrupt_is_valid_vector(vector)) {
+ break;
+ }
+
+ status = arm_interrupt_enable_interrupts();
+ bsp_interrupt_handler_dispatch_unchecked(vector);
+ arm_interrupt_restore_interrupts(status);
WRITE_SR(ICC_EOIR1, icciar);
}
@@ -242,6 +257,7 @@ rtems_status_code arm_gic_irq_get_priority(
return sc;
}
+#ifdef RTEMS_SMP
rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
@@ -274,12 +290,14 @@ rtems_status_code bsp_interrupt_get_affinity(
_Processor_mask_From_uint32_t(affinity, targets, 0);
return RTEMS_SUCCESSFUL;
}
+#endif
void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
{
gicv3_trigger_sgi(vector, targets);
}
+#ifdef RTEMS_SMP
uint32_t arm_gic_irq_processor_count(void)
{
volatile gic_dist *dist = ARM_GIC_DIST;
@@ -306,3 +324,4 @@ uint32_t arm_gic_irq_processor_count(void)
return cpu_count;
}
+#endif