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-rw-r--r--bsps/shared/dev/clock/arm-generic-timer.c19
-rw-r--r--bsps/shared/dev/clock/bcm2835-system-timer.c94
-rw-r--r--bsps/shared/dev/clock/clockimpl.h54
-rw-r--r--bsps/shared/dev/clock/xil-ttc.c214
-rw-r--r--bsps/shared/dev/i2c/cadence-i2c.c1
-rw-r--r--bsps/shared/dev/irq/arm-gicv2-get-attributes.c5
-rw-r--r--bsps/shared/dev/irq/arm-gicv2-zynqmp.c6
-rw-r--r--bsps/shared/dev/irq/arm-gicv2.c36
-rw-r--r--bsps/shared/dev/irq/arm-gicv3.c35
-rw-r--r--bsps/shared/dev/nand/xnandpsu.c103
-rw-r--r--bsps/shared/dev/nand/xnandpsu_bbm.c89
-rw-r--r--bsps/shared/dev/rtc/mcp7940m.c361
-rw-r--r--bsps/shared/dev/serial/console-polled.c2
-rw-r--r--bsps/shared/dev/serial/legacy-console.c6
-rw-r--r--bsps/shared/dev/serial/zynq-uart-kernel-io.c88
-rw-r--r--bsps/shared/dev/serial/zynq-uart-polled.c28
-rw-r--r--bsps/shared/dev/serial/zynq-uart.c19
-rw-r--r--bsps/shared/dev/spi/xqspipsu-flash-helper.c177
-rw-r--r--bsps/shared/dev/spi/xqspipsu.c38
19 files changed, 1265 insertions, 110 deletions
diff --git a/bsps/shared/dev/clock/arm-generic-timer.c b/bsps/shared/dev/clock/arm-generic-timer.c
index 1188800170..ba159f6833 100644
--- a/bsps/shared/dev/clock/arm-generic-timer.c
+++ b/bsps/shared/dev/clock/arm-generic-timer.c
@@ -54,15 +54,12 @@ typedef struct {
static arm_gt_clock_context arm_gt_clock_instance;
-/* This is defined in dev/clock/clockimpl.h */
-void Clock_isr(rtems_irq_hdl_param arg);
-
-static void arm_gt_clock_at_tick(void)
+static void arm_gt_clock_at_tick(arm_gt_clock_context *ctx)
{
uint64_t cval;
uint32_t interval;
- interval = arm_gt_clock_instance.interval;
+ interval = ctx->interval;
cval = arm_gt_clock_get_compare_value();
cval += interval;
arm_gt_clock_set_compare_value(cval);
@@ -71,7 +68,7 @@ static void arm_gt_clock_at_tick(void)
#endif /* ARM_GENERIC_TIMER_UNMASK_AT_TICK */
}
-static void arm_gt_clock_handler_install(void)
+static void arm_gt_clock_handler_install(rtems_interrupt_handler handler)
{
rtems_status_code sc;
@@ -79,8 +76,8 @@ static void arm_gt_clock_handler_install(void)
arm_gt_clock_instance.irq,
"Clock",
RTEMS_INTERRUPT_UNIQUE,
- (rtems_interrupt_handler) Clock_isr,
- NULL
+ handler,
+ &arm_gt_clock_instance
);
if (sc != RTEMS_SUCCESSFUL) {
bsp_fatal(BSP_ARM_FATAL_GENERIC_TIMER_CLOCK_IRQ_INSTALL);
@@ -185,14 +182,14 @@ RTEMS_SYSINIT_ITEM(
RTEMS_SYSINIT_ORDER_FIRST
);
-#define Clock_driver_support_at_tick() \
- arm_gt_clock_at_tick()
+#define Clock_driver_support_at_tick(arg) \
+ arm_gt_clock_at_tick(arg)
#define Clock_driver_support_initialize_hardware() \
arm_gt_clock_initialize()
#define Clock_driver_support_install_isr(isr) \
- arm_gt_clock_handler_install()
+ arm_gt_clock_handler_install(isr)
/* Include shared source clock driver code */
#include "../../shared/dev/clock/clockimpl.h"
diff --git a/bsps/shared/dev/clock/bcm2835-system-timer.c b/bsps/shared/dev/clock/bcm2835-system-timer.c
new file mode 100644
index 0000000000..bb8490d03a
--- /dev/null
+++ b/bsps/shared/dev/clock/bcm2835-system-timer.c
@@ -0,0 +1,94 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockImpl
+ *
+ * @brief This source file contains the implementation of the BCM2835 Clock
+ * Driver.
+ */
+
+/*
+ * Copyright (c) 2013 Alan Cudmore
+ * Copyright (c) 2016 Pavel Pisa
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE
+ *
+*/
+
+#include <rtems.h>
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <bsp/raspberrypi.h>
+#include <rtems/timecounter.h>
+
+static struct timecounter raspberrypi_tc;
+
+static uint32_t raspberrypi_clock_get_timecount(struct timecounter *tc)
+{
+ return BCM2835_REG(BCM2835_GPU_TIMER_CLO);
+}
+
+static void raspberrypi_clock_at_tick(void)
+{
+ uint32_t act_val;
+ uint32_t next_cmp = BCM2835_REG(BCM2835_GPU_TIMER_C3);
+ next_cmp += rtems_configuration_get_microseconds_per_tick();
+ BCM2835_REG(BCM2835_GPU_TIMER_C3) = next_cmp;
+ act_val = BCM2835_REG(BCM2835_GPU_TIMER_CLO);
+
+ /*
+ * Clear interrupt only if there is time left to the next tick.
+ * If time of the next tick has already passed then interrupt
+ * request stays active and fires immediately after current tick
+ * processing is finished.
+ */
+ if ((int32_t)(next_cmp - act_val) > 0)
+ BCM2835_REG(BCM2835_GPU_TIMER_CS) = BCM2835_GPU_TIMER_CS_M3;
+}
+
+static void raspberrypi_clock_handler_install_isr(
+ rtems_interrupt_handler clock_isr
+)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+ sc = rtems_interrupt_handler_install(
+ BCM2835_IRQ_ID_GPU_TIMER_M3,
+ "Clock",
+ RTEMS_INTERRUPT_UNIQUE,
+ clock_isr,
+ NULL
+ );
+ if ( sc != RTEMS_SUCCESSFUL ) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+}
+
+static void raspberrypi_clock_initialize_hardware(void)
+{
+ uint32_t next_cmp = BCM2835_REG(BCM2835_GPU_TIMER_CLO);
+ next_cmp += rtems_configuration_get_microseconds_per_tick();
+ BCM2835_REG(BCM2835_GPU_TIMER_C3) = next_cmp;
+ BCM2835_REG(BCM2835_GPU_TIMER_CS) = BCM2835_GPU_TIMER_CS_M3;
+
+ raspberrypi_tc.tc_get_timecount = raspberrypi_clock_get_timecount;
+ raspberrypi_tc.tc_counter_mask = 0xffffffff;
+ raspberrypi_tc.tc_frequency = 1000000; /* 1 MHz */
+ raspberrypi_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
+ rtems_timecounter_install(&raspberrypi_tc);
+}
+
+#define Clock_driver_support_at_tick(arg) raspberrypi_clock_at_tick()
+
+#define Clock_driver_support_initialize_hardware() raspberrypi_clock_initialize_hardware()
+
+#define Clock_driver_support_install_isr(clock_isr) \
+ raspberrypi_clock_handler_install_isr(clock_isr)
+
+#define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR 1
+
+#include "../../../shared/dev/clock/clockimpl.h"
diff --git a/bsps/shared/dev/clock/clockimpl.h b/bsps/shared/dev/clock/clockimpl.h
index e922c0b320..b27f7c15bc 100644
--- a/bsps/shared/dev/clock/clockimpl.h
+++ b/bsps/shared/dev/clock/clockimpl.h
@@ -42,6 +42,7 @@
#include <bsp.h>
#include <rtems/clockdrv.h>
#include <rtems/score/percpu.h>
+#include <rtems/score/processormaskimpl.h>
#include <rtems/score/smpimpl.h>
#include <rtems/score/timecounter.h>
#include <rtems/score/thread.h>
@@ -63,6 +64,13 @@
#error "Fast Idle PLUS n ISRs per tick is not supported"
#endif
+#if defined(BSP_FEATURE_IRQ_EXTENSION) || \
+ (CPU_SIMPLE_VECTORED_INTERRUPTS != TRUE)
+typedef void * Clock_isr_argument;
+#else
+typedef rtems_vector_number Clock_isr_argument;
+#endif
+
/**
* @brief Do nothing by default.
*/
@@ -81,7 +89,7 @@
* @brief Do nothing by default.
*/
#ifndef Clock_driver_support_at_tick
- #define Clock_driver_support_at_tick()
+ #define Clock_driver_support_at_tick( arg ) do { (void) arg; } while (0)
#endif
/**
@@ -96,8 +104,9 @@
* instead of the default.
*/
#ifndef Clock_driver_timecounter_tick
-static void Clock_driver_timecounter_tick( void )
+static void Clock_driver_timecounter_tick( Clock_isr_argument arg )
{
+ (void) arg;
#if defined(CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER)
rtems_clock_tick();
#elif defined(RTEMS_SMP) && defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
@@ -139,25 +148,31 @@ volatile uint32_t Clock_driver_ticks;
#error "Clock_driver_support_shutdown_hardware() is no longer supported"
#endif
+#if CLOCK_DRIVER_USE_FAST_IDLE
+static bool _Clock_Has_watchdogs(const Per_CPU_Control *cpu)
+{
+ size_t i;
+
+ for (i = 0; i < RTEMS_ARRAY_SIZE(cpu->Watchdog.Header); ++i) {
+ if (_Watchdog_Header_first(&cpu->Watchdog.Header[i]) != NULL) {
+ return true;
+ }
+ }
+
+ return false;
+}
+#endif
+
/**
* @brief Clock_isr
*
* This is the clock tick interrupt handler.
*
- * @param vector Vector number.
+ * @param arg is the clock interrupt handler argument.
*/
-#if defined(BSP_FEATURE_IRQ_EXTENSION) || \
- (CPU_SIMPLE_VECTORED_INTERRUPTS != TRUE)
-void Clock_isr(void *arg);
-void Clock_isr(void *arg)
-{
-#else
-rtems_isr Clock_isr(rtems_vector_number vector);
-rtems_isr Clock_isr(
- rtems_vector_number vector
-)
+void Clock_isr( Clock_isr_argument arg );
+void Clock_isr( Clock_isr_argument arg )
{
-#endif
/*
* Accurate count of ISRs
*/
@@ -165,7 +180,7 @@ rtems_isr Clock_isr(
#if CLOCK_DRIVER_USE_FAST_IDLE
{
- Clock_driver_timecounter_tick();
+ Clock_driver_timecounter_tick( arg );
if (_SMP_Get_processor_maximum() == 1) {
struct timecounter *tc;
@@ -182,6 +197,7 @@ rtems_isr Clock_isr(
cpu_self->thread_dispatch_disable_level == cpu_self->isr_nest_level
&& cpu_self->heir == cpu_self->executing
&& cpu_self->executing->is_idle
+ && _Clock_Has_watchdogs(cpu_self)
) {
ISR_lock_Context lock_context;
@@ -194,7 +210,7 @@ rtems_isr Clock_isr(
}
}
- Clock_driver_support_at_tick();
+ Clock_driver_support_at_tick( arg );
}
#else
/*
@@ -202,14 +218,14 @@ rtems_isr Clock_isr(
*
* The counter/timer may or may not be set to automatically reload.
*/
- Clock_driver_support_at_tick();
+ Clock_driver_support_at_tick( arg );
#if CLOCK_DRIVER_ISRS_PER_TICK
/*
* The driver is multiple ISRs per clock tick.
*/
if ( !Clock_driver_isrs ) {
- Clock_driver_timecounter_tick();
+ Clock_driver_timecounter_tick( arg );
Clock_driver_isrs = CLOCK_DRIVER_ISRS_PER_TICK_VALUE;
}
@@ -218,7 +234,7 @@ rtems_isr Clock_isr(
/*
* The driver is one ISR per clock tick.
*/
- Clock_driver_timecounter_tick();
+ Clock_driver_timecounter_tick( arg );
#endif
#endif
}
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
new file mode 100644
index 0000000000..624845d71c
--- /dev/null
+++ b/bsps/shared/dev/clock/xil-ttc.c
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockXilTTC
+ *
+ * @brief This source file contains a Clock Driver implementation using the
+ * Xilinx Triple Timer Counter (TTC).
+ */
+
+/*
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2023 Reflex Aerospace GmbH
+ *
+ * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/fatal.h>
+#include <dev/clock/xttcps_hw.h>
+#include <rtems/sysinit.h>
+#include <rtems/timecounter.h>
+
+#if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX
+#error "unexpected XTTCPS_COUNT_VALUE_MASK value"
+#endif
+
+/**
+ * @defgroup RTEMSDriverClockXilTTC \
+ * Xilinx Triple Timer Counter (TTC) Clock Driver
+ *
+ * @ingroup RTEMSDriverClockImpl
+ *
+ * @brief This group contains the Xilinx Triple Timer Counter (TTC) Clock
+ * Driver implementation.
+ *
+ * @{
+ */
+
+uint32_t _CPU_Counter_frequency( void )
+{
+ return XIL_CLOCK_TTC_REFERENCE_CLOCK;
+}
+
+CPU_Counter_ticks _CPU_Counter_read(void)
+{
+ return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
+}
+
+static void xil_ttc_initialize(void)
+{
+ /* Do not use a prescaler to get a high resolution time source */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CLK_CNTRL_OFFSET, 0);
+
+ /* Disable interupts */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, 0);
+
+ /*
+ * Enable the timer, do not enable waveform output, increment up, use
+ * overflow mode, enable match mode.
+ */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CNT_CNTRL_OFFSET,
+ XTTCPS_CNT_CNTRL_EN_WAVE_MASK | XTTCPS_CNT_CNTRL_MATCH_MASK);
+}
+
+RTEMS_SYSINIT_ITEM(
+ xil_ttc_initialize,
+ RTEMS_SYSINIT_CPU_COUNTER,
+ RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+typedef struct {
+ struct timecounter base;
+ uint32_t irq_match_interval;
+} xil_ttc_timecounter;
+
+static xil_ttc_timecounter xil_ttc_clock_instance;
+
+static uint32_t xil_ttc_get_timecount(struct timecounter *tc)
+{
+ (void) tc;
+ return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
+}
+
+static void xil_ttc_clock_driver_support_initialize_hardware(void)
+{
+ xil_ttc_timecounter *tc;
+ uint64_t frequency;
+ uint32_t irq_match_interval;
+ uint32_t count;
+
+ tc = &xil_ttc_clock_instance;
+ frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK;
+ irq_match_interval = (uint32_t)
+ ((frequency * rtems_configuration_get_microseconds_per_tick()) / 1000000);
+
+ /* Setup match register to generate clock interrupts */
+ count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET,
+ count + irq_match_interval);
+
+ /* Clear interupts (clear on read) */
+ (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
+
+ /* Enable interupt for match register */
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET,
+ XTTCPS_IXR_MATCH_0_MASK);
+
+ /* Install timecounter */
+ tc->irq_match_interval = irq_match_interval;
+ tc->base.tc_counter_mask = UINT32_MAX;
+ tc->base.tc_frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK;
+ tc->base.tc_get_timecount = xil_ttc_get_timecount;
+ tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
+ rtems_timecounter_install(&tc->base);
+}
+
+static void xil_ttc_clock_driver_support_at_tick(xil_ttc_timecounter *tc)
+{
+ uint32_t irq_match_interval;
+ uint32_t count;
+ uint32_t match;
+
+ irq_match_interval = tc->irq_match_interval;
+
+ /* Update match register */
+ match = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET);
+ match += irq_match_interval;
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match);
+
+ /* Clear interupts (clear on read) */
+ (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
+
+ /* Check that the new match value is in the future */
+ count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
+
+ while (RTEMS_PREDICT_FALSE(match - count > irq_match_interval)) {
+ /*
+ * Tick misses may happen if interrupts are disabled for an extremly long
+ * period or while debugging.
+ */
+ rtems_timecounter_tick();
+
+ /* Update match register */
+ match += irq_match_interval;
+ XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match);
+
+ /* Clear interupts (clear on read) */
+ (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET);
+
+ /* Maybe the new match value is now in the future */
+ count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET);
+ }
+}
+
+static rtems_interrupt_entry xil_ttc_interrupt_entry;
+
+static void xil_ttc_clock_driver_support_install_isr(
+ rtems_interrupt_handler handler
+)
+{
+ rtems_status_code sc;
+
+ rtems_interrupt_entry_initialize(
+ &xil_ttc_interrupt_entry,
+ handler,
+ &xil_ttc_clock_instance,
+ "Clock"
+ );
+ sc = rtems_interrupt_entry_install(
+ XIL_CLOCK_TTC_IRQ,
+ RTEMS_INTERRUPT_UNIQUE,
+ &xil_ttc_interrupt_entry
+ );
+ if ( sc != RTEMS_SUCCESSFUL ) {
+ bsp_fatal(XIL_FATAL_TTC_IRQ_INSTALL);
+ }
+}
+
+#define Clock_driver_support_at_tick(arg) \
+ xil_ttc_clock_driver_support_at_tick(arg)
+
+#define Clock_driver_support_initialize_hardware \
+ xil_ttc_clock_driver_support_initialize_hardware
+
+#define Clock_driver_support_install_isr(isr) \
+ xil_ttc_clock_driver_support_install_isr(isr)
+
+/** @} */
+
+#include "../../../shared/dev/clock/clockimpl.h"
diff --git a/bsps/shared/dev/i2c/cadence-i2c.c b/bsps/shared/dev/i2c/cadence-i2c.c
index 6704288a79..67dec0da46 100644
--- a/bsps/shared/dev/i2c/cadence-i2c.c
+++ b/bsps/shared/dev/i2c/cadence-i2c.c
@@ -28,7 +28,6 @@
#include <dev/i2c/cadence-i2c.h>
#include <dev/i2c/cadence-i2c-regs.h>
-#include <rtems/irq-extension.h>
#include <rtems/score/assert.h>
#include <dev/i2c/i2c.h>
diff --git a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
index 3280671ab6..613174bb3a 100644
--- a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
+++ b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
@@ -3,9 +3,10 @@
/**
* @file
*
- * @ingroup RTEMSBSPsShared
+ * @ingroup DevIRQGIC
*
- * @brief This source file contains the interrupt get attribute implementation.
+ * @brief This source file contains the implementation of
+ * bsp_interrupt_get_attributes() for the GICv2.
*/
/*
diff --git a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
index ee4479155a..bb9bfafb48 100644
--- a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
+++ b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
@@ -3,9 +3,11 @@
/**
* @file
*
- * @ingroup RTEMSBSPsShared
+ * @ingroup DevIRQGIC
*
- * @brief This source file contains the interrupt get attribute implementation.
+ * @brief This source file contains the implementation of
+ * bsp_interrupt_get_attributes() for the GICv2 of Xilinx Zynq UltraScale+
+ * MPSoC and RFSoC devices.
*/
/*
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index fcc3d0dfc8..263278148b 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -3,9 +3,10 @@
/**
* @file
*
- * @ingroup RTEMSBSPsARMShared
+ * @ingroup DevIRQGIC
*
- * @brief This source file contains the implementation of ARM GICv2 support.
+ * @brief This source file contains the implementation of the generic GICv2
+ * support.
*/
/*
@@ -36,9 +37,17 @@
#include <dev/irq/arm-gic.h>
#include <dev/irq/arm-gic-arch.h>
-#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/start.h>
+#include <rtems/score/processormaskimpl.h>
+
+/*
+ * The GIC architecture reserves interrupt ID numbers 1020 to 1023 for special
+ * purposes.
+ */
+#if BSP_INTERRUPT_VECTOR_COUNT >= 1020
+#error "BSP_INTERRUPT_VECTOR_COUNT is too large"
+#endif
#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
@@ -74,12 +83,19 @@
void bsp_interrupt_dispatch(void)
{
volatile gic_cpuif *cpuif = GIC_CPUIF;
- uint32_t icciar = cpuif->icciar;
- rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
- rtems_vector_number spurious = 1023;
- if (vector != spurious) {
- arm_interrupt_handler_dispatch(vector);
+ while (true) {
+ uint32_t icciar = cpuif->icciar;
+ rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+ uint32_t status;
+
+ if (!bsp_interrupt_is_valid_vector(vector)) {
+ break;
+ }
+
+ status = arm_interrupt_enable_interrupts();
+ bsp_interrupt_handler_dispatch_unchecked(vector);
+ arm_interrupt_restore_interrupts(status);
cpuif->icceoir = icciar;
}
@@ -328,6 +344,7 @@ rtems_status_code arm_gic_irq_get_group(
return sc;
}
+#ifdef RTEMS_SMP
rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
@@ -387,6 +404,7 @@ rtems_status_code bsp_interrupt_get_affinity(
_Processor_mask_From_uint32_t(affinity, targets, 0);
return RTEMS_SUCCESSFUL;
}
+#endif
void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
{
@@ -400,9 +418,11 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
| GIC_DIST_ICDSGIR_SGIINTID(vector);
}
+#ifdef RTEMS_SMP
uint32_t arm_gic_irq_processor_count(void)
{
volatile gic_dist *dist = ARM_GIC_DIST;
return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
}
+#endif
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 4772ff5db4..958b1061bd 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -1,6 +1,15 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup DevIRQGIC
*
+ * @brief This source file contains the implementation of the generic GICv3
+ * support.
+ */
+
+/*
* Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
*
* Redistribution and use in source and binary forms, with or without
@@ -27,18 +36,24 @@
#include <dev/irq/arm-gicv3.h>
-#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/start.h>
+#include <rtems/score/processormaskimpl.h>
void bsp_interrupt_dispatch(void)
{
- uint32_t icciar = READ_SR(ICC_IAR1);
- rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
- rtems_vector_number spurious = 1023;
+ while (true) {
+ uint32_t icciar = READ_SR(ICC_IAR1);
+ rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+ uint32_t status;
- if (vector != spurious) {
- arm_interrupt_handler_dispatch(vector);
+ if (!bsp_interrupt_is_valid_vector(vector)) {
+ break;
+ }
+
+ status = arm_interrupt_enable_interrupts();
+ bsp_interrupt_handler_dispatch_unchecked(vector);
+ arm_interrupt_restore_interrupts(status);
WRITE_SR(ICC_EOIR1, icciar);
}
@@ -242,6 +257,7 @@ rtems_status_code arm_gic_irq_get_priority(
return sc;
}
+#ifdef RTEMS_SMP
rtems_status_code bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
@@ -274,12 +290,14 @@ rtems_status_code bsp_interrupt_get_affinity(
_Processor_mask_From_uint32_t(affinity, targets, 0);
return RTEMS_SUCCESSFUL;
}
+#endif
void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
{
gicv3_trigger_sgi(vector, targets);
}
+#ifdef RTEMS_SMP
uint32_t arm_gic_irq_processor_count(void)
{
volatile gic_dist *dist = ARM_GIC_DIST;
@@ -306,3 +324,4 @@ uint32_t arm_gic_irq_processor_count(void)
return cpu_count;
}
+#endif
diff --git a/bsps/shared/dev/nand/xnandpsu.c b/bsps/shared/dev/nand/xnandpsu.c
index 89451d19f8..79025f3c04 100644
--- a/bsps/shared/dev/nand/xnandpsu.c
+++ b/bsps/shared/dev/nand/xnandpsu.c
@@ -244,6 +244,11 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
InstancePtr->DmaMode = XNANDPSU_MDMA;
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+#ifdef __rtems__
+ /* Set page cache to unavailable */
+ InstancePtr->PartialDataPageIndex = XNANDPSU_PAGE_CACHE_UNAVAILABLE;
+#endif
+
/* Initialize the NAND flash targets */
Status = XNandPsu_FlashInit(InstancePtr);
if (Status != XST_SUCCESS) {
@@ -278,6 +283,11 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
#endif
goto Out;
}
+
+#ifdef __rtems__
+ /* Set page cache to none */
+ InstancePtr->PartialDataPageIndex = XNANDPSU_PAGE_CACHE_NONE;
+#endif
Out:
return Status;
}
@@ -814,6 +824,21 @@ void XNandPsu_DisableEccMode(XNandPsu *InstancePtr)
InstancePtr->EccMode = XNANDPSU_NONE;
}
+#ifdef __rtems__
+#include <rtems/rtems/clock.h>
+static void udelay( void )
+{
+ uint64_t time = rtems_clock_get_uptime_nanoseconds() + 1000;
+ while (1) {
+ uint64_t newtime = rtems_clock_get_uptime_nanoseconds();
+ if (newtime > time) {
+ break;
+ }
+ }
+}
+#define usleep(x) udelay()
+#endif
+
/*****************************************************************************/
/**
*
@@ -1439,6 +1464,12 @@ s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
goto Out;
}
+#ifdef __rtems__
+ if (InstancePtr->PartialDataPageIndex != XNANDPSU_PAGE_CACHE_UNAVAILABLE) {
+ /* All writes invalidate the page cache */
+ InstancePtr->PartialDataPageIndex = XNANDPSU_PAGE_CACHE_NONE;
+ }
+#endif
while (LengthVar > 0U) {
Block = (u32) (OffsetVar/InstancePtr->Geometry.BlockSize);
/*
@@ -1467,7 +1498,11 @@ s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
}
Target = (u32) (OffsetVar/InstancePtr->Geometry.TargetSize);
+#ifdef __rtems__
+ {
+#else
if (Page > InstancePtr->Geometry.NumTargetPages) {
+#endif
Page %= InstancePtr->Geometry.NumTargetPages;
}
@@ -1582,7 +1617,11 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
}
Target = (u32) (OffsetVar/InstancePtr->Geometry.TargetSize);
+#ifdef __rtems__
+ {
+#else
if (Page > InstancePtr->Geometry.NumTargetPages) {
+#endif
Page %= InstancePtr->Geometry.NumTargetPages;
}
/* Check if partial read */
@@ -1596,14 +1635,45 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
InstancePtr->Geometry.BytesPerPage :
(u32)LengthVar;
}
+#ifdef __rtems__
+ if (Page == InstancePtr->PartialDataPageIndex) {
+ /*
+ * This is a whole page read for the currently cached
+ * page. It will not be taken care of below, so perform
+ * the copy here.
+ */
+ if (PartialBytes == 0U) {
+ (void)Xil_MemCpy(DestBufPtr,
+ &InstancePtr->PartialDataBuf[0],
+ NumBytes);
+ }
+ } else {
+#endif
/* Read page */
Status = XNandPsu_ReadPage(InstancePtr, Target, Page, 0U,
BufPtr);
+#ifdef __rtems__
+ if (PartialBytes > 0U &&
+ InstancePtr->PartialDataPageIndex != XNANDPSU_PAGE_CACHE_UNAVAILABLE) {
+ /*
+ * Partial read into page cache. Update the
+ * cached page index.
+ */
+ InstancePtr->PartialDataPageIndex = Page;
+ }
+ }
+#endif
if (Status != XST_SUCCESS) {
goto Out;
}
if (PartialBytes > 0U) {
(void)Xil_MemCpy(DestBufPtr, BufPtr + Col, NumBytes);
+#ifdef __rtems__
+ /* The destination buffer is touched by hardware, synchronize */
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)(void *)DestBufPtr, NumBytes);
+ }
+#endif
}
DestBufPtr += NumBytes;
OffsetVar += NumBytes;
@@ -1693,13 +1763,21 @@ s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length)
for (Block = StartBlock; Block < (StartBlock + NumBlocks); Block++) {
Target = Block/InstancePtr->Geometry.NumTargetBlocks;
+#ifdef __rtems__
+ u32 ModBlock = Block % InstancePtr->Geometry.NumTargetBlocks;
+#else
Block %= InstancePtr->Geometry.NumTargetBlocks;
+#endif
/* Don't erase bad block */
if (XNandPsu_IsBlockBad(InstancePtr, Block) ==
XST_SUCCESS)
continue;
/* Block Erase */
+#ifdef __rtems__
+ Status = XNandPsu_EraseBlock(InstancePtr, Target, ModBlock);
+#else
Status = XNandPsu_EraseBlock(InstancePtr, Target, Block);
+#endif
if (Status != XST_SUCCESS)
goto Out;
@@ -2002,6 +2080,14 @@ static s32 XNandPsu_ReadPage(XNandPsu *InstancePtr, u32 Target, u32 Page,
Status = XNandPsu_Data_ReadWrite(InstancePtr, Buf, PktCount, PktSize, 0, 1);
+#ifdef __rtems__
+ if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)(void *)Buf, (PktSize * PktCount));
+ }
+ }
+#endif
+
/* Check ECC Errors */
if (InstancePtr->EccMode == XNANDPSU_HWECC) {
/* Hamming Multi Bit Errors */
@@ -2115,6 +2201,14 @@ s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
Status = XNandPsu_Data_ReadWrite(InstancePtr, Buf, PktCount, PktSize, 0, 1);
+#ifdef __rtems__
+ if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheInvalidateRange((INTPTR)(void *)Buf, (PktSize * PktCount));
+ }
+ }
+#endif
+
return Status;
}
@@ -2140,7 +2234,11 @@ s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Target < XNANDPSU_MAX_TARGETS);
+#ifdef __rtems__
+ Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumTargetBlocks);
+#else
Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
+#endif
s32 Status = XST_FAILURE;
u32 Page;
@@ -2557,6 +2655,11 @@ static s32 XNandPsu_ChangeWriteColumn(XNandPsu *InstancePtr, u32 Target,
if (InstancePtr->DmaMode == XNANDPSU_MDMA) {
RegVal = XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK |
XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK;
+#ifdef __rtems__
+ if (InstancePtr->Config.IsCacheCoherent == 0) {
+ Xil_DCacheFlushRange((INTPTR)(void *)Buf, (PktSize * PktCount));
+ }
+#endif
XNandPsu_Update_DmaAddr(InstancePtr, Buf);
} else {
RegVal = XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK;
diff --git a/bsps/shared/dev/nand/xnandpsu_bbm.c b/bsps/shared/dev/nand/xnandpsu_bbm.c
index dd59148536..40cf798965 100644
--- a/bsps/shared/dev/nand/xnandpsu_bbm.c
+++ b/bsps/shared/dev/nand/xnandpsu_bbm.c
@@ -62,7 +62,9 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
u32 Target);
+#ifndef __rtems__
static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target);
+#endif
/************************** Variable Definitions *****************************/
@@ -321,13 +323,23 @@ Out:
******************************************************************************/
static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target)
{
+#ifndef __rtems__
u32 BlockOffset;
u8 BlockShift;
u32 Data;
u8 BlockType;
u32 BlockIndex;
+#endif
u32 BbtLen = InstancePtr->Geometry.NumTargetBlocks >>
XNANDPSU_BBT_BLOCK_SHIFT;
+#ifdef __rtems__
+ u32 BbtOffset = Target * InstancePtr->Geometry.NumTargetBlocks / XNANDPSU_BBT_ENTRY_NUM_BLOCKS;
+
+ for(u32 BbtIndex = 0; BbtIndex < BbtLen; BbtIndex++) {
+ /* Invert the byte to convert from in-flash BBT to in-memory BBT */
+ InstancePtr->Bbt[BbtIndex + BbtOffset] = ~Buf[BbtIndex];
+ }
+#else
u32 StartBlock = Target * InstancePtr->Geometry.NumTargetBlocks;
for(BlockOffset = StartBlock; BlockOffset < (StartBlock + BbtLen);
@@ -370,6 +382,7 @@ static void XNandPsu_ConvertBbt(XNandPsu *InstancePtr, u8 *Buf, u32 Target)
}
}
}
+#endif
}
/*****************************************************************************/
@@ -400,7 +413,11 @@ static s32 XNandPsu_ReadBbt(XNandPsu *InstancePtr, u32 Target)
XNandPsu_BbtDesc *Desc = &InstancePtr->BbtDesc;
XNandPsu_BbtDesc *MirrorDesc = &InstancePtr->BbtMirrorDesc;
+#ifdef __rtems__
+ BufLen = InstancePtr->Geometry.NumTargetBlocks >>
+#else
BufLen = InstancePtr->Geometry.NumBlocks >>
+#endif
XNANDPSU_BBT_BLOCK_SHIFT;
/* Search the Bad Block Table(BBT) in flash */
Status1 = XNandPsu_SearchBbt(InstancePtr, Desc, Target);
@@ -548,6 +565,9 @@ static s32 XNandPsu_SearchBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
VerOffset = Desc->VerOffset;
MaxBlocks = Desc->MaxBlocks;
SigLength = Desc->SigLength;
+#ifdef __rtems__
+ Desc->Valid = 0;
+#endif
/* Read the last 4 blocks for Bad Block Table(BBT) signature */
for(Block = 0U; Block < MaxBlocks; Block++) {
@@ -612,6 +632,7 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
u8 SpareBuf[XNANDPSU_MAX_SPARE_SIZE] __attribute__ ((aligned(64))) = {0U};
#endif
+#ifndef __rtems__
u8 Mask[4] = {0x00U, 0x01U, 0x02U, 0x03U};
u8 Data;
u32 BlockOffset;
@@ -621,11 +642,21 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
u32 Index;
u8 BlockType;
u32 BbtLen = InstancePtr->Geometry.NumBlocks >>
+#else
+ s32 Status;
+ u32 Index;
+ u32 BbtLen = InstancePtr->Geometry.NumTargetBlocks >>
+#endif
XNANDPSU_BBT_BLOCK_SHIFT;
/* Find a valid block to write the Bad Block Table(BBT) */
if ((!Desc->Valid) != 0U) {
for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
Block = (EndBlock - Index);
+#ifdef __rtems__
+ if (XNandPsu_IsBlockBad(InstancePtr, Block) != XST_FAILURE) {
+ continue;
+ }
+#else
BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
BlockShift = XNandPsu_BbtBlockShift(Block);
BlockType = (InstancePtr->Bbt[BlockOffset] >>
@@ -639,6 +670,7 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
/* Good Block */
break;
}
+#endif
Desc->PageOffset[Target] = Block *
InstancePtr->Geometry.PagesPerBlock;
if (Desc->PageOffset[Target] !=
@@ -666,6 +698,14 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
/* Convert the memory based BBT to flash based table */
(void)memset(Buf, 0xff, BbtLen);
+#ifdef __rtems__
+ u32 BbtTargetOffset = BbtLen * Target;
+ /* Loop through the BBT entries */
+ for(u32 BbtIndex = 0U; BbtIndex < BbtLen; BbtIndex++) {
+ /* Invert byte to convert from in-memory BBT to in-flash BBT */
+ Buf[BbtIndex] = ~InstancePtr->Bbt[BbtIndex + BbtTargetOffset];
+ }
+#else
/* Loop through the number of blocks */
for(BlockOffset = 0U; BlockOffset < BbtLen; BlockOffset++) {
Data = InstancePtr->Bbt[BlockOffset];
@@ -679,8 +719,14 @@ static s32 XNandPsu_WriteBbt(XNandPsu *InstancePtr, XNandPsu_BbtDesc *Desc,
Data >>= XNANDPSU_BBT_BLOCK_SHIFT;
}
}
+#endif
/* Write the Bad Block Table(BBT) to flash */
+#ifdef __rtems__
+ Status = XNandPsu_EraseBlock(InstancePtr, Target,
+ Block % InstancePtr->Geometry.NumTargetBlocks);
+#else
Status = XNandPsu_EraseBlock(InstancePtr, 0U, Block);
+#endif
if (Status != XST_SUCCESS) {
goto Out;
}
@@ -726,7 +772,11 @@ Out:
* - XST_FAILURE if fail.
*
******************************************************************************/
+#ifdef __rtems__
+s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
+#else
static s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target)
+#endif
{
s32 Status;
u8 Version;
@@ -786,7 +836,11 @@ static s32 XNandPsu_MarkBbt(XNandPsu* InstancePtr, XNandPsu_BbtDesc *Desc,
/* Mark the last four blocks as Reserved */
BlockIndex = ((Target + (u32)1) * InstancePtr->Geometry.NumTargetBlocks) -
+#ifdef __rtems__
+ Desc->MaxBlocks;
+#else
Desc->MaxBlocks - (u32)1;
+#endif
for(Index = 0U; Index < Desc->MaxBlocks; Index++) {
@@ -871,11 +925,22 @@ s32 XNandPsu_IsBlockBad(XNandPsu *InstancePtr, u32 Block)
*
******************************************************************************/
s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
+#ifdef __rtems__
+{
+ return XNandPsu_MarkBlock(InstancePtr, Block, XNANDPSU_BLOCK_BAD );
+}
+
+s32 XNandPsu_MarkBlock(XNandPsu *InstancePtr, u32 Block, u8 BlockMark)
+#endif
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY)
Xil_AssertNonvoid(Block < InstancePtr->Geometry.NumBlocks);
+#ifdef __rtems__
+ BlockMark &= XNANDPSU_BLOCK_TYPE_MASK;
+#endif
+
u8 Data;
u8 BlockShift;
u32 BlockOffset;
@@ -893,7 +958,11 @@ s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
/* Mark the block as bad in the RAM based Bad Block Table */
OldVal = Data;
Data &= ~(XNANDPSU_BLOCK_TYPE_MASK << BlockShift);
+#ifdef __rtems__
+ Data |= (BlockMark << BlockShift);
+#else
Data |= (XNANDPSU_BLOCK_BAD << BlockShift);
+#endif
NewVal = Data;
InstancePtr->Bbt[BlockOffset] = Data;
@@ -909,4 +978,24 @@ s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
Out:
return Status;
}
+
+#ifdef __rtems__
+bool XNandPsu_StageBlockMark(XNandPsu *InstancePtr, u32 Block, u8 BlockMark)
+{
+ u8 BlockShift;
+ u32 BlockOffset;
+ u8 OldVal;
+
+ BlockMark &= XNANDPSU_BLOCK_TYPE_MASK;
+
+ BlockOffset = Block >> XNANDPSU_BBT_BLOCK_SHIFT;
+ BlockShift = XNandPsu_BbtBlockShift(Block);
+ OldVal = InstancePtr->Bbt[BlockOffset] >> BlockShift;
+ OldVal &= XNANDPSU_BLOCK_TYPE_MASK;
+ InstancePtr->Bbt[BlockOffset] &= ~(XNANDPSU_BLOCK_TYPE_MASK << BlockShift);
+ InstancePtr->Bbt[BlockOffset] |= (BlockMark << BlockShift);
+ return BlockMark != OldVal;
+}
+#endif
+
/** @} */
diff --git a/bsps/shared/dev/rtc/mcp7940m.c b/bsps/shared/dev/rtc/mcp7940m.c
new file mode 100644
index 0000000000..1abc5faaad
--- /dev/null
+++ b/bsps/shared/dev/rtc/mcp7940m.c
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2023 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Note: This driver implements only the basic RTC functionality of the
+ * MCP7940M. It tries not to touch any register fields except for the basic
+ * date/time fields in the get/set time functions. That way it should be
+ * possible to re-use the driver for similar RTCs by just replacing the
+ * initialization function. Suggested method for that: Add a field to the struct
+ * mcp7940m_rtc with a function pointer that points to the initialization
+ * function.
+ *
+ * All flags that are considered MCP7940M specific have a MCP7940M in the name.
+ *
+ * Only 24 hour format is supported. If this driver is the only ones who write
+ * the RTC, that shouldn't be a problem.
+ *
+ * The weekday register is not used. It has a user-defined representation anyway
+ * and therefore doesn't really matter.
+ */
+
+#include <dev/i2c/i2c.h>
+#include <libchip/mcp7940m-rtc.h>
+#include <rtems/score/sysstate.h>
+#include <rtems/score/todimpl.h>
+
+#include <fcntl.h>
+#include <stdint.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <unistd.h>
+
+#define REG_RTCSEC 0x00u
+
+#define RTCSEC_SECBCD_SHIFT 0u
+#define RTCSEC_SECBCD_MASK (0x7fu << RTCSEC_SECBCD_SHIFT)
+#define RTCSEC_SECBCD(x) (((x) << RTCSEC_SECBCD_SHIFT) & RTCSEC_SECBCD_MASK)
+#define RTCSEC_SECBCD_GET(x) (((x) & RTCSEC_SECBCD_MASK) >> RTCSEC_SECBCD_SHIFT)
+
+#define MCP7940M_RTCSEC_ST (0x01u << 7)
+
+#define REG_RTCMIN 0x01
+
+#define RTCMIN_MINBCD_SHIFT 0u
+#define RTCMIN_MINBCD_MASK (0x7fu << RTCMIN_MINBCD_SHIFT)
+#define RTCMIN_MINBCD(x) (((x) << RTCMIN_MINBCD_SHIFT) & RTCMIN_MINBCD_MASK)
+#define RTCMIN_MINBCD_GET(x) (((x) & RTCMIN_MINBCD_MASK) >> RTCMIN_MINBCD_SHIFT)
+
+#define REG_RTCHOUR 0x02
+
+#define RTCHOUR_HRBCD12_SHIFT 0u
+#define RTCHOUR_HRBCD12_MASK (0x1fu << RTCHOUR_HRBCD12_SHIFT)
+#define RTCHOUR_HRBCD12(x) (((x) << RTCHOUR_HRBCD12_SHIFT) & RTCHOUR_HRBCD12_MASK)
+#define RTCHOUR_HRBCD12_GET(x) (((x) & RTCHOUR_HRBCD12_MASK) >> RTCHOUR_HRBCD12_SHIFT)
+
+#define RTCHOUR_HRBCD24_SHIFT 0u
+#define RTCHOUR_HRBCD24_MASK (0x3fu << RTCHOUR_HRBCD24_SHIFT)
+#define RTCHOUR_HRBCD24(x) (((x) << RTCHOUR_HRBCD24_SHIFT) & RTCHOUR_HRBCD24_MASK)
+#define RTCHOUR_HRBCD24_GET(x) (((x) & RTCHOUR_HRBCD24_MASK) >> RTCHOUR_HRBCD24_SHIFT)
+
+#define RTCHOUR_AMPM (0x01u << 5)
+#define RTCHOUR_1224 (0x01u << 6)
+
+#define REG_RTCWKDAY 0x03
+
+#define RTCWKDAY_WKDAY_SHIFT 0u
+#define RTCWKDAY_WKDAY_MASK (0x7u << RTCWKDAY_WKDAY_SHIFT)
+#define RTCWKDAY_WKDAY(x) (((x) << RTCWKDAY_WKDAY_SHIFT) & RTCWKDAY_WKDAY_MASK)
+#define RTCWKDAY_WKDAY_GET(x) (((x) & RTCWKDAY_WKDAY_MASK) >> RTCWKDAY_WKDAY_SHIFT)
+
+#define REG_RTCDATE 0x04
+
+#define RTCDATE_DATEBCD_SHIFT 0u
+#define RTCDATE_DATEBCD_MASK (0x3fu << RTCDATE_DATEBCD_SHIFT)
+#define RTCDATE_DATEBCD(x) (((x) << RTCDATE_DATEBCD_SHIFT) & RTCDATE_DATEBCD_MASK)
+#define RTCDATE_DATEBCD_GET(x) (((x) & RTCDATE_DATEBCD_MASK) >> RTCDATE_DATEBCD_SHIFT)
+
+#define REG_RTCMTH 0x05
+
+#define RTCMTH_MTHBCD_SHIFT 0u
+#define RTCMTH_MTHBCD_MASK (0x1fu << RTCMTH_MTHBCD_SHIFT)
+#define RTCMTH_MTHBCD(x) (((x) << RTCMTH_MTHBCD_SHIFT) & RTCMTH_MTHBCD_MASK)
+#define RTCMTH_MTHBCD_GET(x) (((x) & RTCMTH_MTHBCD_MASK) >> RTCMTH_MTHBCD_SHIFT)
+
+#define MCP7940M_RTCMTH_LPYR (0x01u << 5)
+
+#define REG_RTCYEAR 0x06
+
+#define RTCYEAR_YRBCD_SHIFT 0u
+#define RTCYEAR_YRBCD_MASK (0xffu << RTCYEAR_YRBCD_SHIFT)
+#define RTCYEAR_YRBCD(x) (((x) << RTCYEAR_YRBCD_SHIFT) & RTCYEAR_YRBCD_MASK)
+#define RTCYEAR_YRBCD_GET(x) (((x) & RTCYEAR_YRBCD_MASK) >> RTCYEAR_YRBCD_SHIFT)
+
+#define REG_MCP7940M_CONTROL 0x07
+
+#define MCP7940M_CONTROL_OUT (0x1u << 7)
+#define MCP7940M_CONTROL_SQWEN (0x1u << 6)
+#define MCP7940M_CONTROL_ALM1EN (0x1u << 5)
+#define MCP7940M_CONTROL_ALM0EN (0x1u << 4)
+#define MCP7940M_CONTROL_EXTOSC (0x1u << 3)
+#define MCP7940M_CONTROL_CRSTRIM (0x1u << 2)
+#define MCP7940M_CONTROL_SQWFS1 (0x1u << 1)
+#define MCP7940M_CONTROL_SQWFS0 (0x1u << 0)
+
+static inline uint8_t bcd_to_bin(uint8_t bcd)
+{
+ uint8_t bin;
+ bin = bcd & 0x0f;
+ bin += ((bcd >> 4) & 0x0f) * 10;
+ return bin;
+}
+
+static inline uint8_t bin_to_bcd(uint8_t bin)
+{
+ uint8_t bcd;
+ bcd = bin % 10;
+ bcd |= (bin / 10) << 4;
+ return bcd;
+}
+
+static struct mcp7940m_rtc *mcp7940m_get_context(int minor)
+{
+ return (struct mcp7940m_rtc *) RTC_Table[minor].pDeviceParams;
+}
+
+static int mcp7940m_i2c_read(
+ struct mcp7940m_rtc *ctx,
+ uint8_t addr,
+ uint8_t *buf,
+ size_t len
+)
+{
+ int fd;
+ int rv;
+ struct i2c_msg msgs[] = {{
+ .addr = ctx->i2c_addr,
+ .flags = 0,
+ .buf = &addr,
+ .len = 1,
+ }, {
+ .addr = ctx->i2c_addr,
+ .flags = I2C_M_RD,
+ .buf = buf,
+ .len = len,
+ }};
+ struct i2c_rdwr_ioctl_data payload = {
+ .msgs = msgs,
+ .nmsgs = sizeof(msgs)/sizeof(msgs[0]),
+ };
+
+ fd = open(ctx->i2c_bus_path, O_RDWR);
+ if (fd < 0) {
+ return fd;
+ }
+
+ rv = ioctl(fd, I2C_RDWR, &payload);
+
+ close(fd);
+
+ return rv;
+}
+
+static int mcp7940m_i2c_write(
+ struct mcp7940m_rtc *ctx,
+ uint8_t addr,
+ const uint8_t *buf,
+ size_t len
+)
+{
+ int fd;
+ int rv;
+ uint8_t writebuf[len + 1];
+ struct i2c_msg msgs[] = {{
+ .addr = ctx->i2c_addr,
+ .flags = 0,
+ .buf = writebuf,
+ .len = len + 1,
+ }};
+ struct i2c_rdwr_ioctl_data payload = {
+ .msgs = msgs,
+ .nmsgs = sizeof(msgs)/sizeof(msgs[0]),
+ };
+
+ writebuf[0] = addr;
+ memcpy(&writebuf[1], buf, len);
+
+ fd = open(ctx->i2c_bus_path, O_RDWR);
+ if (fd < 0) {
+ return fd;
+ }
+
+ rv = ioctl(fd, I2C_RDWR, &payload);
+
+ close(fd);
+
+ return rv;
+}
+
+static int mcp7940m_initialize_once(struct mcp7940m_rtc *ctx)
+{
+ uint8_t reg;
+ ssize_t rv;
+
+ if (ctx->initialized) {
+ return 0;
+ }
+
+ /*
+ * Make sure that all alarms and outputs are disabled. Enable or disable
+ * oscillator.
+ *
+ * This makes sure that we can start with an uninitialized device that has a
+ * random value in the control register.
+ */
+ reg = 0;
+ if (!ctx->crystal) {
+ reg |= MCP7940M_CONTROL_EXTOSC;
+ }
+ rv = mcp7940m_i2c_write(ctx, REG_MCP7940M_CONTROL, &reg, 1);
+
+ if (rv == 0 && ctx->crystal) {
+ rv = mcp7940m_i2c_read(ctx, REG_RTCSEC, &reg, 1);
+ if (rv == 0 && (reg & MCP7940M_RTCSEC_ST) == 0) {
+ reg |= MCP7940M_RTCSEC_ST;
+ rv = mcp7940m_i2c_write(ctx, REG_RTCSEC, &reg, 1);
+ }
+ }
+
+ ctx->initialized = true;
+
+ return rv;
+}
+
+static int mcp7940m_get_time(int minor, rtems_time_of_day *time)
+{
+ int rv = 0;
+ uint8_t buf[REG_RTCYEAR + 1];
+ struct mcp7940m_rtc *ctx = mcp7940m_get_context(minor);
+
+ if (!_System_state_Is_up(_System_state_Get())) {
+ return -1;
+ }
+
+ rtems_mutex_lock(&ctx->mutex);
+
+ rv = mcp7940m_initialize_once(ctx);
+
+ if (rv == 0) {
+ rv = mcp7940m_i2c_read(ctx, REG_RTCSEC, buf, sizeof(buf));
+ }
+
+ if (rv == 0) {
+ unsigned year = bcd_to_bin(RTCYEAR_YRBCD_GET(buf[REG_RTCYEAR])) +
+ (TOD_BASE_YEAR / 100 * 100);
+ if (year < TOD_BASE_YEAR) {
+ year += 100;
+ }
+ time->year = year;
+ time->month = bcd_to_bin(RTCMTH_MTHBCD_GET(buf[REG_RTCMTH]));
+ time->day = bcd_to_bin(RTCDATE_DATEBCD_GET(buf[REG_RTCDATE]));
+ time->hour = bcd_to_bin(RTCHOUR_HRBCD24_GET(buf[REG_RTCHOUR]));
+ time->minute = bcd_to_bin(RTCMIN_MINBCD_GET(buf[REG_RTCMIN]));
+ time->second = bcd_to_bin(RTCSEC_SECBCD_GET(buf[REG_RTCSEC]));
+ time->ticks = 0;
+ }
+
+ rtems_mutex_unlock(&ctx->mutex);
+
+ return rv;
+}
+
+static int mcp7940m_set_time(int minor, const rtems_time_of_day *time)
+{
+ int rv = 0;
+ uint8_t buf[REG_RTCYEAR + 1];
+ struct mcp7940m_rtc *ctx = mcp7940m_get_context(minor);
+
+ if (!_System_state_Is_up(_System_state_Get())) {
+ return -1;
+ }
+
+ rtems_mutex_lock(&ctx->mutex);
+
+ rv = mcp7940m_initialize_once(ctx);
+
+ if (rv == 0) {
+ rv = mcp7940m_i2c_read(ctx, REG_RTCSEC, buf, sizeof(buf));
+ }
+
+ if (rv == 0) {
+ /* Make sure weekday is not 0 (out of range). Otherwise it's not used. */
+ if (RTCWKDAY_WKDAY_GET(buf[REG_RTCWKDAY]) < 1) {
+ buf[REG_RTCWKDAY] &= ~RTCWKDAY_WKDAY_MASK;
+ buf[REG_RTCWKDAY] |= RTCWKDAY_WKDAY(1);
+ }
+
+ buf[REG_RTCYEAR] &= ~RTCYEAR_YRBCD_MASK;
+ buf[REG_RTCYEAR] |= RTCYEAR_YRBCD(bin_to_bcd(time->year % 100));
+
+ buf[REG_RTCMTH] &= ~RTCMTH_MTHBCD_MASK;
+ buf[REG_RTCMTH] |= RTCMTH_MTHBCD(bin_to_bcd(time->month));
+
+ buf[REG_RTCDATE] &= ~RTCDATE_DATEBCD_MASK;
+ buf[REG_RTCDATE] |= RTCDATE_DATEBCD(bin_to_bcd(time->day));
+
+ buf[REG_RTCHOUR] &= ~(RTCHOUR_HRBCD24_MASK | RTCHOUR_1224);
+ buf[REG_RTCHOUR] |= RTCHOUR_HRBCD24(bin_to_bcd(time->hour));
+
+ buf[REG_RTCMIN] &= ~RTCMIN_MINBCD_MASK;
+ buf[REG_RTCMIN] |= RTCMIN_MINBCD(bin_to_bcd(time->minute));
+
+ buf[REG_RTCSEC] &= ~RTCSEC_SECBCD_MASK;
+ buf[REG_RTCSEC] |= RTCSEC_SECBCD(bin_to_bcd(time->second));
+
+ rv = mcp7940m_i2c_write(ctx, REG_RTCSEC, buf, sizeof(buf));
+ }
+
+ rtems_mutex_unlock(&ctx->mutex);
+
+ return rv;
+}
+
+static void mcp7940m_init(int minor)
+{
+ (void) minor;
+}
+
+bool rtc_mcp7940m_probe(int minor)
+{
+ return true;
+}
+
+const rtc_fns rtc_mcp7940m_fns = {
+ .deviceInitialize = mcp7940m_init,
+ .deviceGetTime = mcp7940m_get_time,
+ .deviceSetTime = mcp7940m_set_time,
+};
diff --git a/bsps/shared/dev/serial/console-polled.c b/bsps/shared/dev/serial/console-polled.c
index 0fc765cb64..37ad5b8f18 100644
--- a/bsps/shared/dev/serial/console-polled.c
+++ b/bsps/shared/dev/serial/console-polled.c
@@ -113,7 +113,7 @@ rtems_device_driver console_open(
NULL, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
- 0 /* outputUsesInterrupts */
+ TERMIOS_POLLED /* outputUsesInterrupts */
};
assert( minor == 0 );
diff --git a/bsps/shared/dev/serial/legacy-console.c b/bsps/shared/dev/serial/legacy-console.c
index 7da87276b0..698439b247 100644
--- a/bsps/shared/dev/serial/legacy-console.c
+++ b/bsps/shared/dev/serial/legacy-console.c
@@ -234,7 +234,11 @@ rtems_device_driver console_open(
Callbacks.stopRemoteTx = NULL;
Callbacks.startRemoteTx = NULL;
}
- Callbacks.outputUsesInterrupts = cptr->pDeviceFns->deviceOutputUsesInterrupts;
+ if (cptr->pDeviceFns->deviceOutputUsesInterrupts) {
+ Callbacks.outputUsesInterrupts = TERMIOS_IRQ_DRIVEN;
+ } else {
+ Callbacks.outputUsesInterrupts = TERMIOS_POLLED;
+ }
/* XXX what about
* Console_Port_Tbl[minor].ulMargin,
diff --git a/bsps/shared/dev/serial/zynq-uart-kernel-io.c b/bsps/shared/dev/serial/zynq-uart-kernel-io.c
new file mode 100644
index 0000000000..61b1043cd2
--- /dev/null
+++ b/bsps/shared/dev/serial/zynq-uart-kernel-io.c
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup zynq_uart
+ *
+ * @brief This source file contains the definition of ::BSP_output_char and
+ * ::BSP_poll_char.
+ */
+
+/*
+ * Copyright (C) 2013, 2024 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/bspIo.h>
+
+#include <bsp.h>
+#include <dev/serial/zynq-uart-regs.h>
+#include <rtems/sysinit.h>
+
+static void zynq_uart_kernel_output_char(char c)
+{
+ volatile zynq_uart *regs =
+ (volatile zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR;
+
+ zynq_uart_write_char_polled(regs, c);
+}
+
+static int zynq_uart_kernel_poll_char(void)
+{
+ volatile zynq_uart *regs =
+ (volatile zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR;
+
+ return zynq_uart_read_char_polled(regs);
+}
+
+static void zynq_uart_kernel_early_init(char c);
+
+static void zynq_uart_kernel_init(void)
+{
+ volatile zynq_uart *regs =
+ (volatile zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR;
+
+ if (BSP_output_char != zynq_uart_kernel_early_init) {
+ return;
+ }
+
+ zynq_uart_initialize(regs);
+ BSP_output_char = zynq_uart_kernel_output_char;
+}
+
+static void zynq_uart_kernel_early_init(char c)
+{
+ zynq_uart_kernel_init();
+ zynq_uart_kernel_output_char(c);
+}
+
+BSP_output_char_function_type BSP_output_char = zynq_uart_kernel_early_init;
+
+BSP_polling_getchar_function_type BSP_poll_char = zynq_uart_kernel_poll_char;
+
+RTEMS_SYSINIT_ITEM(
+ zynq_uart_kernel_init,
+ RTEMS_SYSINIT_BSP_START,
+ RTEMS_SYSINIT_ORDER_LAST_BUT_5
+);
diff --git a/bsps/shared/dev/serial/zynq-uart-polled.c b/bsps/shared/dev/serial/zynq-uart-polled.c
index 7d5dd8ff1a..dbf75539f6 100644
--- a/bsps/shared/dev/serial/zynq-uart-polled.c
+++ b/bsps/shared/dev/serial/zynq-uart-polled.c
@@ -124,10 +124,8 @@ int zynq_cal_baud_rate(uint32_t baudrate,
return 0;
}
-void zynq_uart_initialize(rtems_termios_device_context *base)
+void zynq_uart_initialize(volatile zynq_uart *regs)
{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
uint32_t brgr = 0x3e;
uint32_t bauddiv = 0x6;
uint32_t mode_clks = regs->mode & ZYNQ_UART_MODE_CLKS;
@@ -154,18 +152,15 @@ void zynq_uart_initialize(rtems_termios_device_context *base)
| ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8)
| mode_clks;
- while (zynq_uart_read_polled(base) >= 0) {
+ while (zynq_uart_read_char_polled(regs) >= 0) {
/* Drop */
}
- zynq_uart_reset_tx_flush(ctx);
+ zynq_uart_reset_tx_flush(regs);
}
-int zynq_uart_read_polled(rtems_termios_device_context *base)
+int zynq_uart_read_char_polled(volatile zynq_uart *regs)
{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
-
if ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_REMPTY) != 0) {
return -1;
} else {
@@ -173,14 +168,8 @@ int zynq_uart_read_polled(rtems_termios_device_context *base)
}
}
-void zynq_uart_write_polled(
- rtems_termios_device_context *base,
- char c
-)
+void zynq_uart_write_char_polled(volatile zynq_uart *regs, char c)
{
- zynq_uart_context *ctx = (zynq_uart_context *) base;
- volatile zynq_uart *regs = ctx->regs;
-
while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TNFUL) != 0) {
/* Wait */
}
@@ -188,13 +177,12 @@ void zynq_uart_write_polled(
regs->tx_rx_fifo = ZYNQ_UART_TX_RX_FIFO_FIFO(c);
}
-void zynq_uart_reset_tx_flush(zynq_uart_context *ctx)
+void zynq_uart_reset_tx_flush(volatile zynq_uart *regs)
{
- volatile zynq_uart *regs = ctx->regs;
- int c = 4;
+ int c = 4;
while (c-- > 0)
- zynq_uart_write_polled(&ctx->base, '\r');
+ zynq_uart_write_char_polled(regs, '\r');
while ((regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TEMPTY) == 0 ||
(regs->channel_sts & ZYNQ_UART_CHANNEL_STS_TACTIVE) != 0) {
diff --git a/bsps/shared/dev/serial/zynq-uart.c b/bsps/shared/dev/serial/zynq-uart.c
index 10e5d2acff..0489288271 100644
--- a/bsps/shared/dev/serial/zynq-uart.c
+++ b/bsps/shared/dev/serial/zynq-uart.c
@@ -28,6 +28,7 @@
#include <dev/serial/zynq-uart.h>
#include <dev/serial/zynq-uart-regs.h>
#include <bsp/irq.h>
+#include <rtems/termiostypes.h>
#include <bspopts.h>
@@ -66,14 +67,14 @@ static bool zynq_uart_first_open(
rtems_libio_open_close_args_t *args
)
{
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
zynq_uart_context *ctx = (zynq_uart_context *) base;
volatile zynq_uart *regs = ctx->regs;
+#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
rtems_status_code sc;
#endif
rtems_termios_set_initial_baud(tty, ZYNQ_UART_DEFAULT_BAUD);
- zynq_uart_initialize(base);
+ zynq_uart_initialize(regs);
#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
regs->rx_fifo_trg_lvl = 1;
@@ -108,15 +109,23 @@ static void zynq_uart_last_close(
}
#endif
+#ifndef ZYNQ_CONSOLE_USE_INTERRUPTS
+static int zynq_uart_read_polled(rtems_termios_device_context *base)
+{
+ zynq_uart_context *ctx = (zynq_uart_context *) base;
+ return zynq_uart_read_char_polled(ctx->regs);
+}
+#endif
+
static void zynq_uart_write_support(
rtems_termios_device_context *base,
const char *buf,
size_t len
)
{
-#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
zynq_uart_context *ctx = (zynq_uart_context *) base;
volatile zynq_uart *regs = ctx->regs;
+#ifdef ZYNQ_CONSOLE_USE_INTERRUPTS
regs->irq_dis = ZYNQ_UART_TEMPTY;
@@ -134,9 +143,9 @@ static void zynq_uart_write_support(
regs->irq_en = ZYNQ_UART_TEMPTY;
}
#else
- ssize_t i;
+ size_t i;
for (i = 0; i < len; ++i) {
- zynq_uart_write_polled(base, buf[i]);
+ zynq_uart_write_char_polled(regs, buf[i]);
}
#endif
}
diff --git a/bsps/shared/dev/spi/xqspipsu-flash-helper.c b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
index 43dc700507..10e1066173 100644
--- a/bsps/shared/dev/spi/xqspipsu-flash-helper.c
+++ b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
@@ -274,22 +274,57 @@ static void QspiPsuHandler(
}
}
-/*****************************************************************************/
-/**
- *
- * Reads the flash ID and identifies the flash in FCT table.
- *
- * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
- *
- * @return XST_SUCCESS if successful, else XST_FAILURE.
- *
- * @note None.
- *
- *****************************************************************************/
-static int FlashReadID(XQspiPsu *QspiPsuPtr)
+int QspiPsu_NOR_RDSFDP(
+ XQspiPsu *QspiPsuPtr,
+ u32 Address,
+ u32 ByteCount,
+ u8 **ReadBfrPtr
+)
+{
+ int Status;
+
+ *ReadBfrPtr = ReadBuffer;
+
+ CmdBfr[COMMAND_OFFSET] = READ_SFDP;
+ CmdBfr[ADDRESS_1_OFFSET] =
+ (u8)((Address & 0xFF0000) >> 16);
+ CmdBfr[ADDRESS_2_OFFSET] =
+ (u8)((Address & 0xFF00) >> 8);
+ CmdBfr[ADDRESS_3_OFFSET] =
+ (u8)(Address & 0xFF);
+
+ FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+ FlashMsg[0].TxBfrPtr = CmdBfr;
+ FlashMsg[0].RxBfrPtr = NULL;
+ FlashMsg[0].ByteCount = 4;
+ FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
+
+ FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+ FlashMsg[1].TxBfrPtr = NULL;
+ FlashMsg[1].RxBfrPtr = NULL;
+ FlashMsg[1].ByteCount = DUMMY_CLOCKS;
+ FlashMsg[1].Flags = 0;
+
+ FlashMsg[2].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+ FlashMsg[2].TxBfrPtr = NULL;
+ FlashMsg[2].RxBfrPtr = *ReadBfrPtr;
+ FlashMsg[2].ByteCount = ByteCount;
+ FlashMsg[2].Flags = XQSPIPSU_MSG_FLAG_RX;
+
+ TransferInProgress = TRUE;
+ Status = XQspiPsu_InterruptTransfer(QspiPsuPtr, FlashMsg, 3);
+ if (Status != XST_SUCCESS)
+ return XST_FAILURE;
+
+ while (TransferInProgress);
+
+ rtems_cache_invalidate_multiple_data_lines(ReadBuffer, ByteCount);
+ return 0;
+}
+
+int QspiPsu_NOR_RDID(XQspiPsu *QspiPsuPtr, u8 *ReadBfrPtr, u32 ReadLen)
{
int Status;
- u32 ReadId = 0;
/*
* Read ID
@@ -303,7 +338,7 @@ static int FlashReadID(XQspiPsu *QspiPsuPtr)
FlashMsg[1].TxBfrPtr = NULL;
FlashMsg[1].RxBfrPtr = ReadBfrPtr;
- FlashMsg[1].ByteCount = 3;
+ FlashMsg[1].ByteCount = ReadLen;
FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
FlashMsg[1].Flags = XQSPIPSU_MSG_FLAG_RX;
@@ -314,6 +349,33 @@ static int FlashReadID(XQspiPsu *QspiPsuPtr)
}
while (TransferInProgress);
+ rtems_cache_invalidate_multiple_data_lines(ReadBfrPtr, ReadLen);
+ return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * Reads the flash ID and identifies the flash in FCT table.
+ *
+ * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
+ *
+ * @return XST_SUCCESS if successful, else XST_FAILURE.
+ *
+ * @note None.
+ *
+ *****************************************************************************/
+static int FlashReadID(XQspiPsu *QspiPsuPtr)
+{
+ u32 ReadId = 0;
+ u32 ReadLen = 3;
+ int Status;
+
+ Status = QspiPsu_NOR_RDID(QspiPsuPtr, ReadBfrPtr, ReadLen);
+ if (Status != XST_SUCCESS) {
+ return XST_FAILURE;
+ }
+
/* In case of dual, read both and ensure they are same make/size */
/*
@@ -333,7 +395,7 @@ static int FlashReadID(XQspiPsu *QspiPsuPtr)
return XST_SUCCESS;
}
-int QspiPsu_NOR_Write(
+int QspiPsu_NOR_Write_Page(
XQspiPsu *QspiPsuPtr,
u32 Address,
u32 ByteCount,
@@ -475,6 +537,51 @@ int QspiPsu_NOR_Write(
return 0;
}
+int QspiPsu_NOR_Write(
+ XQspiPsu *QspiPsuPtr,
+ u32 Address,
+ u32 ByteCount,
+ u8 *WriteBfrPtr
+)
+{
+ int Status;
+ size_t ByteCountRemaining = ByteCount;
+ unsigned char *WriteBfrPartial = WriteBfrPtr;
+ uint32_t AddressPartial = Address;
+ uint32_t PageSize = Flash_Config_Table[FCTIndex].PageSize;
+ if(QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL) {
+ PageSize *= 2;
+ }
+
+ while (ByteCountRemaining > 0) {
+ /* Get write boundary */
+ size_t WriteChunkLen = RTEMS_ALIGN_UP(AddressPartial + 1, PageSize);
+
+ /* Get offset to write boundary */
+ WriteChunkLen -= (size_t)AddressPartial;
+
+ /* Cap short writes */
+ if (WriteChunkLen > ByteCountRemaining) {
+ WriteChunkLen = ByteCountRemaining;
+ }
+
+ Status = QspiPsu_NOR_Write_Page(
+ QspiPsuPtr,
+ AddressPartial,
+ WriteChunkLen,
+ WriteBfrPartial
+ );
+ if ( Status != XST_SUCCESS ) {
+ return Status;
+ }
+
+ ByteCountRemaining -= WriteChunkLen;
+ AddressPartial += WriteChunkLen;
+ WriteBfrPartial += WriteChunkLen;
+ }
+ return Status;
+}
+
int QspiPsu_NOR_Erase(
XQspiPsu *QspiPsuPtr,
u32 Address,
@@ -489,22 +596,18 @@ int QspiPsu_NOR_Erase(
u32 NumSect;
int Status;
u32 SectSize;
- u32 SectMask;
WriteEnableCmd = WRITE_ENABLE_CMD;
if(QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL) {
- SectMask = (Flash_Config_Table[FCTIndex]).SectMask - (Flash_Config_Table[FCTIndex]).SectSize;
SectSize = (Flash_Config_Table[FCTIndex]).SectSize * 2;
NumSect = (Flash_Config_Table[FCTIndex]).NumSect;
} else if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_STACKED) {
NumSect = (Flash_Config_Table[FCTIndex]).NumSect * 2;
- SectMask = (Flash_Config_Table[FCTIndex]).SectMask;
SectSize = (Flash_Config_Table[FCTIndex]).SectSize;
} else {
SectSize = (Flash_Config_Table[FCTIndex]).SectSize;
NumSect = (Flash_Config_Table[FCTIndex]).NumSect;
- SectMask = (Flash_Config_Table[FCTIndex]).SectMask;
}
/*
@@ -569,18 +672,9 @@ int QspiPsu_NOR_Erase(
/*
* Calculate no. of sectors to erase based on byte count
*/
- NumSect = (ByteCount / SectSize) + 1;
-
- /*
- * If ByteCount to k sectors,
- * but the address range spans from N to N+k+1 sectors, then
- * increment no. of sectors to be erased
- */
-
- if (((Address + ByteCount) & SectMask) ==
- ((Address + (NumSect * SectSize)) & SectMask)) {
- NumSect++;
- }
+ u32 SectorStartBase = RTEMS_ALIGN_DOWN(Address, SectSize);
+ u32 SectorEndTop = RTEMS_ALIGN_UP(Address + ByteCount, SectSize);
+ NumSect = (SectorEndTop - SectorStartBase)/SectSize;
for (Sector = 0; Sector < NumSect; Sector++) {
@@ -828,6 +922,7 @@ int QspiPsu_NOR_Read(
while (TransferInProgress);
}
+ rtems_cache_invalidate_multiple_data_lines(ReadBuffer, ByteCount);
return 0;
}
@@ -1015,6 +1110,7 @@ static int MultiDieRead(
Address += data_len;
remain_len -= data_len;
}
+ rtems_cache_invalidate_multiple_data_lines(ReadBfrPtr, ByteCount);
return 0;
}
@@ -2226,3 +2322,20 @@ static int MultiDieReadEcc(
}
return 0;
}
+
+u32 QspiPsu_NOR_Get_Sector_Size(XQspiPsu *QspiPsuPtr)
+{
+ if(QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL) {
+ return Flash_Config_Table[FCTIndex].SectSize * 2;
+ }
+ return Flash_Config_Table[FCTIndex].SectSize;
+}
+
+u32 QspiPsu_NOR_Get_Device_Size(XQspiPsu *QspiPsuPtr)
+{
+ if(QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_STACKED
+ || QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL) {
+ return Flash_Config_Table[FCTIndex].FlashDeviceSize * 2;
+ }
+ return Flash_Config_Table[FCTIndex].FlashDeviceSize;
+}
diff --git a/bsps/shared/dev/spi/xqspipsu.c b/bsps/shared/dev/spi/xqspipsu.c
index 1286efd359..93d3fa4c98 100644
--- a/bsps/shared/dev/spi/xqspipsu.c
+++ b/bsps/shared/dev/spi/xqspipsu.c
@@ -84,6 +84,9 @@
#include "xqspipsu.h"
#include "xqspipsu_control.h"
#include "sleep.h"
+#ifdef __rtems__
+#include <rtems/rtems/cache.h>
+#endif
/************************** Constant Definitions *****************************/
#define MAX_DELAY_CNT 10000000U /**< Max delay count */
@@ -275,6 +278,12 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
u32 IntrStatus, ConfigReg, FifoStatus;
u32 DelayCount = 0U;
+#ifdef __rtems__
+ u32 FifoStatusMask = XQSPIPSU_ISR_RXEMPTY_MASK;
+ FifoStatusMask |= XQSPIPSU_ISR_TXEMPTY_MASK;
+ FifoStatusMask |= XQSPIPSU_ISR_GENFIFOEMPTY_MASK;
+#endif
+
Xil_AssertVoid(InstancePtr != NULL);
#ifdef DEBUG
xil_printf("\nXQspiPsu_Abort\r\n");
@@ -326,8 +335,13 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
*/
FifoStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+#ifdef __rtems__
+ XQSPIPSU_ISR_OFFSET) & FifoStatusMask;
+ while(FifoStatus != FifoStatusMask) {
+#else
XQSPIPSU_FIFO_CTRL_OFFSET);
while(FifoStatus != 0U) {
+#endif
if (DelayCount == MAX_DELAY_CNT) {
#ifdef DEBUG
xil_printf("Timeout error, FIFO reset failed.\r\n");
@@ -337,7 +351,11 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
usleep(1);
DelayCount++;
FifoStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+#ifdef __rtems__
+ XQSPIPSU_ISR_OFFSET) & FifoStatusMask;
+#else
XQSPIPSU_FIFO_CTRL_OFFSET);
+#endif
}
}
@@ -442,7 +460,16 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
for (Index = 0; Index < (s32)NumMsg; Index++) {
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+#ifdef __rtems__
+ if (Msg[Index].TxBfrPtr != NULL) {
+ rtems_cache_flush_multiple_data_lines(Msg[Index].TxBfrPtr, Msg[Index].ByteCount);
+ }
+#endif
}
+#ifdef __rtems__
+ rtems_cache_flush_multiple_data_lines(Msg, NumMsg * sizeof(*Msg));
+#endif
+
/*
* Check whether there is another transfer in progress.
* Not thread-safe
@@ -582,7 +609,18 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
for (Index = 0; Index < (s32)NumMsg; Index++)
+#ifdef __rtems__
+ {
+#endif
Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+#ifdef __rtems__
+ if (Msg[Index].TxBfrPtr != NULL) {
+ rtems_cache_flush_multiple_data_lines(Msg[Index].TxBfrPtr, Msg[Index].ByteCount);
+ }
+ }
+ rtems_cache_flush_multiple_data_lines(Msg, NumMsg * sizeof(*Msg));
+#endif
+
/*
* Check whether there is another transfer in progress.
* Not thread-safe
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-19 07:59:26 +0000