4 files changed, 62 insertions, 20 deletions
diff --git a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
index 3280671ab6..613174bb3a 100644
--- a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
+++ b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
@@ -3,9 +3,10 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsShared
+ * @ingroup DevIRQGIC
  *
- * @brief This source file contains the interrupt get attribute implementation.
+ * @brief This source file contains the implementation of
+ *   bsp_interrupt_get_attributes() for the GICv2.
  */
 
 /*
diff --git a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
index ee4479155a..bb9bfafb48 100644
--- a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
+++ b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
@@ -3,9 +3,11 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsShared
+ * @ingroup DevIRQGIC
  *
- * @brief This source file contains the interrupt get attribute implementation.
+ * @brief This source file contains the implementation of
+ *   bsp_interrupt_get_attributes() for the GICv2 of Xilinx Zynq UltraScale+
+ *   MPSoC and RFSoC devices.
  */
 
 /*
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index fcc3d0dfc8..263278148b 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -3,9 +3,10 @@
 /**
  * @file
  *
- * @ingroup RTEMSBSPsARMShared
+ * @ingroup DevIRQGIC
  *
- * @brief This source file contains the implementation of ARM GICv2 support.
+ * @brief This source file contains the implementation of the generic GICv2
+ *   support.
  */
 
 /*
@@ -36,9 +37,17 @@
 #include <dev/irq/arm-gic.h>
 #include <dev/irq/arm-gic-arch.h>
 
-#include <bsp/irq.h>
 #include <bsp/irq-generic.h>
 #include <bsp/start.h>
+#include <rtems/score/processormaskimpl.h>
+
+/*
+ * The GIC architecture reserves interrupt ID numbers 1020 to 1023 for special
+ * purposes.
+ */
+#if BSP_INTERRUPT_VECTOR_COUNT >= 1020
+#error "BSP_INTERRUPT_VECTOR_COUNT is too large"
+#endif
 
 #define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
 
@@ -74,12 +83,19 @@
 void bsp_interrupt_dispatch(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
-  uint32_t icciar = cpuif->icciar;
-  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
-  rtems_vector_number spurious = 1023;
 
-  if (vector != spurious) {
-    arm_interrupt_handler_dispatch(vector);
+  while (true) {
+    uint32_t icciar = cpuif->icciar;
+    rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+    uint32_t status;
+
+    if (!bsp_interrupt_is_valid_vector(vector)) {
+      break;
+    }
+
+    status = arm_interrupt_enable_interrupts();
+    bsp_interrupt_handler_dispatch_unchecked(vector);
+    arm_interrupt_restore_interrupts(status);
 
     cpuif->icceoir = icciar;
   }
@@ -328,6 +344,7 @@ rtems_status_code arm_gic_irq_get_group(
   return sc;
 }
 
+#ifdef RTEMS_SMP
 rtems_status_code bsp_interrupt_set_affinity(
   rtems_vector_number vector,
   const Processor_mask *affinity
@@ -387,6 +404,7 @@ rtems_status_code bsp_interrupt_get_affinity(
   _Processor_mask_From_uint32_t(affinity, targets, 0);
   return RTEMS_SUCCESSFUL;
 }
+#endif
 
 void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
 {
@@ -400,9 +418,11 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
     | GIC_DIST_ICDSGIR_SGIINTID(vector);
 }
 
+#ifdef RTEMS_SMP
 uint32_t arm_gic_irq_processor_count(void)
 {
   volatile gic_dist *dist = ARM_GIC_DIST;
 
   return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
 }
+#endif
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 4772ff5db4..958b1061bd 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -1,6 +1,15 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup DevIRQGIC
  *
+ * @brief This source file contains the implementation of the generic GICv3
+ *   support.
+ */
+
+/*
  * Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,18 +36,24 @@
 
 #include <dev/irq/arm-gicv3.h>
 
-#include <bsp/irq.h>
 #include <bsp/irq-generic.h>
 #include <bsp/start.h>
+#include <rtems/score/processormaskimpl.h>
 
 void bsp_interrupt_dispatch(void)
 {
-  uint32_t icciar = READ_SR(ICC_IAR1);
-  rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
-  rtems_vector_number spurious = 1023;
+  while (true) {
+    uint32_t icciar = READ_SR(ICC_IAR1);
+    rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
+    uint32_t status;
 
-  if (vector != spurious) {
-    arm_interrupt_handler_dispatch(vector);
+    if (!bsp_interrupt_is_valid_vector(vector)) {
+      break;
+    }
+
+    status = arm_interrupt_enable_interrupts();
+    bsp_interrupt_handler_dispatch_unchecked(vector);
+    arm_interrupt_restore_interrupts(status);
 
     WRITE_SR(ICC_EOIR1, icciar);
   }
@@ -242,6 +257,7 @@ rtems_status_code arm_gic_irq_get_priority(
   return sc;
 }
 
+#ifdef RTEMS_SMP
 rtems_status_code bsp_interrupt_set_affinity(
   rtems_vector_number vector,
   const Processor_mask *affinity
@@ -274,12 +290,14 @@ rtems_status_code bsp_interrupt_get_affinity(
   _Processor_mask_From_uint32_t(affinity, targets, 0);
   return RTEMS_SUCCESSFUL;
 }
+#endif
 
 void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
 {
   gicv3_trigger_sgi(vector, targets);
 }
 
+#ifdef RTEMS_SMP
 uint32_t arm_gic_irq_processor_count(void)
 {
   volatile gic_dist *dist = ARM_GIC_DIST;
@@ -306,3 +324,4 @@ uint32_t arm_gic_irq_processor_count(void)
 
   return cpu_count;
 }
+#endif