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| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /spec/build/bsps/riscv/optextirqmax.yml | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'spec/build/bsps/riscv/optextirqmax.yml')
| -rw-r--r-- | spec/build/bsps/riscv/optextirqmax.yml | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/spec/build/bsps/riscv/optextirqmax.yml b/spec/build/bsps/riscv/optextirqmax.yml index ffa84748b6..84dbbb7705 100644 --- a/spec/build/bsps/riscv/optextirqmax.yml +++ b/spec/build/bsps/riscv/optextirqmax.yml @@ -6,7 +6,10 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 64 -default-by-variant: [] +default-by-variant: +- value: 187 + variants: + - riscv/mpfs64.* description: | maximum number of external interrupts supported by the BSP (default 64) enabled-by: true |