From 6b0d3c987349d188b65e9fc8229daeba247928c5 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 19 Sep 2022 18:30:26 +0530 Subject: bsps/riscv: Add Microchip PolarFire SoC BSP variant The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART. --- spec/build/bsps/riscv/optextirqmax.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'spec/build/bsps/riscv/optextirqmax.yml') diff --git a/spec/build/bsps/riscv/optextirqmax.yml b/spec/build/bsps/riscv/optextirqmax.yml index ffa84748b6..84dbbb7705 100644 --- a/spec/build/bsps/riscv/optextirqmax.yml +++ b/spec/build/bsps/riscv/optextirqmax.yml @@ -6,7 +6,10 @@ build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) default: 64 -default-by-variant: [] +default-by-variant: +- value: 187 + variants: + - riscv/mpfs64.* description: | maximum number of external interrupts supported by the BSP (default 64) enabled-by: true -- cgit v1.2.3