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authorPadmarao Begari <padmarao.begari@microchip.com>2022-09-19 18:30:26 +0530
committerJoel Sherrill <joel@rtems.org>2022-09-20 12:00:51 -0500
commit6b0d3c987349d188b65e9fc8229daeba247928c5 (patch)
tree4f6f37aaab9be619b82612eb4f000a42549488ca /spec
parentspec/build/bsps: Add dtb support (diff)
downloadrtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
Diffstat (limited to 'spec')
-rw-r--r--spec/build/bsps/riscv/optextirqmax.yml5
-rw-r--r--spec/build/bsps/riscv/optrambegin.yml5
-rw-r--r--spec/build/bsps/riscv/optramsize.yml5
-rw-r--r--spec/build/bsps/riscv/riscv/abi.yml6
-rw-r--r--spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml19
-rw-r--r--spec/build/bsps/riscv/riscv/grp.yml6
-rw-r--r--spec/build/bsps/riscv/riscv/optmpfs.yml18
-rw-r--r--spec/build/bsps/riscv/riscv/optns16550max.yml3
-rw-r--r--spec/build/cpukit/cpuopts.yml2
-rw-r--r--spec/build/cpukit/optarchbits.yml1
-rw-r--r--spec/build/cpukit/optboothartid.yml19
-rw-r--r--spec/build/cpukit/optsmp.yml1
12 files changed, 87 insertions, 3 deletions
diff --git a/spec/build/bsps/riscv/optextirqmax.yml b/spec/build/bsps/riscv/optextirqmax.yml
index ffa84748b6..84dbbb7705 100644
--- a/spec/build/bsps/riscv/optextirqmax.yml
+++ b/spec/build/bsps/riscv/optextirqmax.yml
@@ -6,7 +6,10 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default: 64
-default-by-variant: []
+default-by-variant:
+- value: 187
+ variants:
+ - riscv/mpfs64.*
description: |
maximum number of external interrupts supported by the BSP (default 64)
enabled-by: true
diff --git a/spec/build/bsps/riscv/optrambegin.yml b/spec/build/bsps/riscv/optrambegin.yml
index 4a867a1921..90133411cf 100644
--- a/spec/build/bsps/riscv/optrambegin.yml
+++ b/spec/build/bsps/riscv/optrambegin.yml
@@ -1,7 +1,7 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-integer: null
-- assert-uint32: null
+- assert-uint64: null
- assert-aligned: 1048576
- env-assign: null
- format-and-define: null
@@ -22,6 +22,9 @@ default-by-variant:
- value: 1073741824
variants:
- riscv/griscv
+- value: 68719476736
+ variants:
+ - riscv/mpfs64.*
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/riscv/optramsize.yml b/spec/build/bsps/riscv/optramsize.yml
index cd58dbd504..316cc906de 100644
--- a/spec/build/bsps/riscv/optramsize.yml
+++ b/spec/build/bsps/riscv/optramsize.yml
@@ -1,7 +1,7 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
actions:
- get-integer: null
-- assert-uint32: null
+- assert-uint64: null
- assert-aligned: 1048576
- env-assign: null
- format-and-define: null
@@ -16,6 +16,9 @@ default-by-variant:
- value: 16777216
variants:
- riscv/griscv
+- value: 268435456
+ variants:
+ - riscv/mpfs64.*
description: ''
enabled-by: true
format: '{:#010x}'
diff --git a/spec/build/bsps/riscv/riscv/abi.yml b/spec/build/bsps/riscv/riscv/abi.yml
index e975b87c4c..3ef8b0681d 100644
--- a/spec/build/bsps/riscv/riscv/abi.yml
+++ b/spec/build/bsps/riscv/riscv/abi.yml
@@ -15,6 +15,12 @@ default-by-variant:
- -mabi=lp64d
- -mcmodel=medany
variants:
+ - riscv/mpfs64imafdc
+- value:
+ - -march=rv64imafdc
+ - -mabi=lp64d
+ - -mcmodel=medany
+ variants:
- riscv/rv64imafdc_medany
- value:
- -march=rv64imafdc
diff --git a/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
new file mode 100644
index 0000000000..c12703d79b
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: mpfs64imafdc
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: ../../opto2
+- role: build-dependency
+ uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/riscv/grp.yml b/spec/build/bsps/riscv/riscv/grp.yml
index 7f773d91ee..713c15509a 100644
--- a/spec/build/bsps/riscv/riscv/grp.yml
+++ b/spec/build/bsps/riscv/riscv/grp.yml
@@ -45,10 +45,16 @@ links:
- role: build-dependency
uid: ../../optfdtuboot
- role: build-dependency
+ uid: ../../optdtb
+- role: build-dependency
+ uid: ../../optdtbheaderpath
+- role: build-dependency
uid: optfrdme310arty
- role: build-dependency
uid: opthtif
- role: build-dependency
+ uid: optmpfs
+- role: build-dependency
uid: optns16550max
- role: build-dependency
uid: ../linkcmds
diff --git a/spec/build/bsps/riscv/riscv/optmpfs.yml b/spec/build/bsps/riscv/riscv/optmpfs.yml
new file mode 100644
index 0000000000..17614567e3
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/optmpfs.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: false
+default-by-variant:
+- value: true
+ variants:
+ - riscv/mpfs64.*
+description: |
+ enables support Microchip PolarFire SoC if defined to a non-zero value,otherwise it is disabled (disabled by default)
+enabled-by: true
+links: []
+name: RISCV_ENABLE_MPFS_SUPPORT
+type: build
diff --git a/spec/build/bsps/riscv/riscv/optns16550max.yml b/spec/build/bsps/riscv/riscv/optns16550max.yml
index 7e385a57b7..66189cfdfd 100644
--- a/spec/build/bsps/riscv/riscv/optns16550max.yml
+++ b/spec/build/bsps/riscv/riscv/optns16550max.yml
@@ -10,6 +10,9 @@ default-by-variant:
- value: null
variants:
- riscv/frdme310arty.*
+- value: 1
+ variants:
+ - riscv/mpfs64.*
description: |
maximum number of NS16550 devices supported by the console driver (2 by default)
enabled-by: true
diff --git a/spec/build/cpukit/cpuopts.yml b/spec/build/cpukit/cpuopts.yml
index 86cc7f676a..dcfca62d05 100644
--- a/spec/build/cpukit/cpuopts.yml
+++ b/spec/build/cpukit/cpuopts.yml
@@ -34,6 +34,8 @@ links:
- role: build-dependency
uid: optada
- role: build-dependency
+ uid: optboothartid
+- role: build-dependency
uid: optbuildlabel
- role: build-dependency
uid: optdebug
diff --git a/spec/build/cpukit/optarchbits.yml b/spec/build/cpukit/optarchbits.yml
index f7b652cc60..0ec4a9fe7e 100644
--- a/spec/build/cpukit/optarchbits.yml
+++ b/spec/build/cpukit/optarchbits.yml
@@ -11,6 +11,7 @@ default-by-variant:
- value:
- '64'
variants:
+ - riscv/mpfs64.*
- riscv/noel64.*
- riscv/rv64.*
- value:
diff --git a/spec/build/cpukit/optboothartid.yml b/spec/build/cpukit/optboothartid.yml
new file mode 100644
index 0000000000..ede4e5ead8
--- /dev/null
+++ b/spec/build/cpukit/optboothartid.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 0
+default-by-variant:
+- value: 1
+ variants:
+ - riscv/mpfs64.*
+description: |
+ boot hartid (processor number) of risc-v cpu (default 0)
+enabled-by: true
+format: '{}'
+links: []
+name: RISCV_BOOT_HARTID
+type: build
diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml
index a9e62bf8b9..b218364194 100644
--- a/spec/build/cpukit/optsmp.yml
+++ b/spec/build/cpukit/optsmp.yml
@@ -31,6 +31,7 @@ enabled-by:
- riscv/griscv
- riscv/grv32imac
- riscv/grv32imafdc
+- riscv/mpfs64imafdc
- riscv/noel32imafd
- riscv/noel64imac
- riscv/noel64imafdc