build: Use enabled by for defaults

Merge the "default" and "default-by-variant" attributes.  Use an
"enabled-by" expression to select the default value based on the enabled
set.  This makes it possible to select default values depending on other
options.  For example you could choose memory settings based on whether
RTEMS_SMP is enabled or disabled.

The change was tested by comparing the output of

  ./waf bspdefaults

before and after the change.

13 files changed, 45 insertions, 32 deletions

diff --git a/spec/build/bsps/arm/altera-cyclone-v/abi.yml b/spec/build/bsps/arm/altera-cyclone-v/abi.yml
index a3a710c97d..d3161d624d 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/abi.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/abi.yml
@@ -7,12 +7,13 @@ build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
 default:
-- -march=armv7-a
-- -mthumb
-- -mfpu=neon
-- -mfloat-abi=hard
-- -mtune=cortex-a9
-default-by-variant: []
+- enabled-by: true
+  value:
+  - -march=armv7-a
+  - -mthumb
+  - -mfpu=neon
+  - -mfloat-abi=hard
+  - -mtune=cortex-a9
 description: |
   ABI flags
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml
index e67ddc129b..717ab3987e 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/opta9periphclk.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: false
-default-by-variant: []
+default:
+- enabled-by: true
+  value: false
 description: |
   define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml
index 77dac09116..9a0fcab10c 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optcachedata.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   enable data cache
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml
index a59db43f31..d1528a778a 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optcacheinst.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   enable instruction cache
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml
index 61333a11f1..e303a8bf9f 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml
@@ -5,13 +5,14 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: false
-default-by-variant:
-- value: true
-  variants:
+default:
+- enabled-by:
   - arm/lm3s6965_qemu
   - arm/realview_pbx_a9_qemu
   - arm/xilinx_zynq_a9_qemu
+  value: true
+- enabled-by: true
+  value: false
 description: |
   This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing.  This can significantly reduce simulation times.
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml
index 635697cc8a..7c0a838c59 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optconcfg.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   configuration for console (UART 0)
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml
index f5c588a330..23a7228b33 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optconuart1.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   configuration for UART 1
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml
index f2fc473967..acaa870ecd 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optfdten.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   define if FDT is supported
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml
index ee8097aa3b..55e4d45d30 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/opti2cspeed.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 100000
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 100000
 description: |
   speed for I2C0 in HZ
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml
index 2d36d5f930..c5aad3d6f0 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optnoi2c.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   Number of configured I2C buses. Note that each bus has to be configured in an apropriate i2cdrv_config array.
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml
index efd1ea2b2a..bac5c79627 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optresetvec.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: false
-default-by-variant: []
+default:
+- enabled-by: true
+  value: false
 description: |
   reset vector address for BSP start
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml
index b5f577ffc3..e4a99ded5f 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optuartbaud.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: 115200
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 115200
 description: |
   baud for UARTs
 enabled-by: true
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml
index 152668b2d9..a9fa750357 100644
--- a/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml
+++ b/spec/build/bsps/arm/altera-cyclone-v/optuartirq.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-default: true
-default-by-variant: []
+default:
+- enabled-by: true
+  value: true
 description: |
   enable usage of interrupts for the UART modules
 enabled-by: true