diff options
Diffstat (limited to 'spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml')
-rw-r--r-- | spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml index 61333a11f1..e303a8bf9f 100644 --- a/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml +++ b/spec/build/bsps/arm/altera-cyclone-v/optclkfastidle.yml @@ -5,13 +5,14 @@ actions: build-type: option copyrights: - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) -default: false -default-by-variant: -- value: true - variants: +default: +- enabled-by: - arm/lm3s6965_qemu - arm/realview_pbx_a9_qemu - arm/xilinx_zynq_a9_qemu + value: true +- enabled-by: true + value: false description: | This sets a mode where the time runs as fast as possible when a clock ISR occurs while the IDLE thread is executing. This can significantly reduce simulation times. enabled-by: true |