Whitespace removal.

4 files changed, 37 insertions, 37 deletions

diff --git a/cpukit/score/cpu/lm32/cpu.c b/cpukit/score/cpu/lm32/cpu.c
index 825a70f96b..b796b6a1e6 100644
--- a/cpukit/score/cpu/lm32/cpu.c
+++ b/cpukit/score/cpu/lm32/cpu.c
@@ -50,7 +50,7 @@ void _CPU_Initialize(void)
  *
  *  XXX document implementation including references if appropriate
  */
- 
+
 uint32_t   _CPU_ISR_Get_level( void )
 {
   /*
@@ -68,7 +68,7 @@ uint32_t   _CPU_ISR_Get_level( void )
  *
  *  XXX document implementation including references if appropriate
  */
- 
+
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
   proc_ptr    new_handler,
diff --git a/cpukit/score/cpu/lm32/cpu_asm.S b/cpukit/score/cpu/lm32/cpu_asm.S
index 02e1f6928a..bfed8cb1af 100644
--- a/cpukit/score/cpu/lm32/cpu_asm.S
+++ b/cpukit/score/cpu/lm32/cpu_asm.S
@@ -108,7 +108,7 @@ _CPU_Context_switch_restore:
 _CPU_Context_restore:
     mv      r2, r1
     bi      _CPU_Context_switch_restore
-    
+
 /*  void _ISR_Handler()
  *
  *  This routine provides the RTEMS interrupt management.
@@ -125,7 +125,7 @@ _CPU_Context_restore:
  *  handles interrupt nesting, software interrupt stack setup etc and
  *  finally calls the user ISR.
  *  At the end the saved registers are restored.
- *  
+ *
  */
 
     .globl  _ISR_Handler
@@ -180,18 +180,18 @@ found_irq:
     mvhi    r3, hi(__ISR_Handler)
     ori     r3, r3, lo(__ISR_Handler)
     call    r3
-    
+
 exit_isr:
     /* Restore the saved registers */
     lw      r1, (sp+4)
-    lw      r2, (sp+8) 
-    lw      r3, (sp+12) 
-    lw      r4, (sp+16) 
-    lw      r5, (sp+20) 
-    lw      r6, (sp+24) 
-    lw      r7, (sp+28) 
-    lw      r8, (sp+32) 
-    lw      r9, (sp+36) 
+    lw      r2, (sp+8)
+    lw      r3, (sp+12)
+    lw      r4, (sp+16)
+    lw      r5, (sp+20)
+    lw      r6, (sp+24)
+    lw      r7, (sp+28)
+    lw      r8, (sp+32)
+    lw      r9, (sp+36)
     lw      r10, (sp+40)
     lw      ra, (sp+44)
     lw      ea, (sp+48)
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index f6b6a9210c..41c30ca099 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h
@@ -13,7 +13,7 @@
  *
  *  + Anywhere there is an XXX, it should be replaced
  *    with information about the CPU family being ported to.
- *  
+ *
  *  + At the end of each comment section, there is a heading which
  *    says "Port Specific Information:".  When porting to RTEMS,
  *    add CPU family specific information in this section
@@ -168,7 +168,7 @@ extern "C" {
 
 /**
  *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  a pointer to the saved interrupt frame (1) or just the vector
  *  number (0)?
  *
  *  Port Specific Information:
@@ -195,7 +195,7 @@ extern "C" {
  *  an i387 and wish to leave floating point support out of RTEMS.
  */
 
-/** 
+/**
  *  @def CPU_SOFTWARE_FP
  *
  *  Does the CPU have no hardware floating point and GCC provides a
@@ -203,7 +203,7 @@ extern "C" {
  *  switched?
  *
  *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context 
+ *  is software implemented floating point that must be context
  *  switched.  The determination of whether or not this applies
  *  is very tool specific and the state saved/restored is also
  *  compiler specific.
@@ -491,7 +491,7 @@ typedef struct {
  *  This macro returns the stack pointer associated with @a _context.
  *
  *  @param[in] _context is the thread context area to access
- *  
+ *
  *  @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
@@ -562,14 +562,14 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
 /**
  *  @ingroup CPUInterrupt
- *  This variable points to the lowest physical address of the interrupt 
+ *  This variable points to the lowest physical address of the interrupt
  *  stack.
  */
 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
 
 /**
  *  @ingroup CPUInterrupt
- *  This variable points to the lowest physical address of the interrupt 
+ *  This variable points to the lowest physical address of the interrupt
  *  stack.
  */
 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
@@ -663,7 +663,7 @@ SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
  *
  *  @note  This does not have to be a power of 2 although it should be
  *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least 
+ *         to be a multiple of 2 is because the heap uses the least
  *         significant field of the front and back flags to indicate
  *         that a block is in use or free.  So you do not want any odd
  *         length blocks really putting length data in that bit.
@@ -945,7 +945,7 @@ uint32_t   _CPU_ISR_Get_level( void );
 /**
  *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for 
+ *  This set of routines are used to implement fast searches for
  *  the most important ready task.
  */
 
@@ -970,7 +970,7 @@ uint32_t   _CPU_ISR_Get_level( void );
 /**
  *  @ingroup CPUBitfield
  *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type 
+ *  set in @a _value.  @a _value is of CPU dependent type
  *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
  *  wide although only the 16 least significant bits will be used.
  *
@@ -1013,14 +1013,14 @@ uint32_t   _CPU_ISR_Get_level( void );
         if _value > 0x00ff
           _value >>=8
           _number = 8;
-  
+
         if _value > 0x0000f
           _value >=8
           _number += 4
-  
+
         _number += bit_set_table[ _value ]
 @endverbatim
-  
+
  *    where bit_set_table[ 16 ] has values which indicate the first
  *      bit set
  *
@@ -1092,7 +1092,7 @@ void _CPU_Initialize(void);
 
 /**
  *  @ingroup CPUInterrupt
- *  This routine installs a "raw" interrupt handler directly into the 
+ *  This routine installs a "raw" interrupt handler directly into the
  *  processor's vector table.
  *
  *  @param[in] vector is the vector number
@@ -1254,12 +1254,12 @@ static inline uint32_t CPU_swap_u32(
 )
 {
   uint32_t byte1, byte2, byte3, byte4, swapped;
- 
+
   byte4 = (value >> 24) & 0xff;
   byte3 = (value >> 16) & 0xff;
   byte2 = (value >> 8)  & 0xff;
   byte1 =  value        & 0xff;
- 
+
   swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
   return swapped;
 }
diff --git a/cpukit/score/cpu/lm32/rtems/score/lm32.h b/cpukit/score/cpu/lm32/rtems/score/lm32.h
index c8327f47a9..06ad7eb398 100644
--- a/cpukit/score/cpu/lm32/rtems/score/lm32.h
+++ b/cpukit/score/cpu/lm32/rtems/score/lm32.h
@@ -1,6 +1,6 @@
 /*  lm32.h
  *
- *  This file sets up basic CPU dependency settings based on 
+ *  This file sets up basic CPU dependency settings based on
  *  compiler settings.  For example, it can determine if
  *  floating point is available.  This particular implementation
  *  is specified to the NO CPU port.
@@ -37,25 +37,25 @@ extern "C" {
  *  that this port supports and which RTEMS CPU model they correspond
  *  to.
  */
- 
+
 #if defined(rtems_multilib)
 /*
- *  Figure out all CPU Model Feature Flags based upon compiler 
- *  predefines. 
+ *  Figure out all CPU Model Feature Flags based upon compiler
+ *  predefines.
  */
 
 #define CPU_MODEL_NAME  "rtems_multilib"
 #define LM32_HAS_FPU     0
 
 #elif defined(__lm32__)
- 
+
 #define CPU_MODEL_NAME  "lm32"
 #define LM32_HAS_FPU     0
- 
+
 #else
- 
+
 #error "Unsupported CPU Model"
- 
+
 #endif
 
 /*