diff options
59 files changed, 794 insertions, 794 deletions
diff --git a/c/src/lib/libcpu/i386/cpu.h b/c/src/lib/libcpu/i386/cpu.h index ba524ab941..ec15f952da 100644 --- a/c/src/lib/libcpu/i386/cpu.h +++ b/c/src/lib/libcpu/i386/cpu.h @@ -1,5 +1,5 @@ /* - * cpu.h - This file contains definitions for data structure related + * cpu.h - This file contains definitions for data structure related * to Intel system programming. More information can be found * on Intel site and more precisely in the following book : * @@ -147,7 +147,7 @@ do { register unsigned short __port = _port; \ } while (0) /* - * Type definition for raw interrupts. + * Type definition for raw interrupts. */ typedef unsigned char rtems_vector_offset; @@ -167,16 +167,16 @@ typedef struct __rtems_raw_irq_connect_data__{ * libcpu library, this library should have no knowledge of * board specific hardware to manage interrupts and thus the * "on" routine must enable the irq both at device and PIC level. - * + * */ - rtems_raw_irq_enable on; + rtems_raw_irq_enable on; /* * function for disabling raw interrupts. In order to be consistent * with the fact that the raw connexion can defined in the * libcpu library, this library should have no knowledge of * board specific hardware to manage interrupts and thus the * "on" routine must disable the irq both at device and PIC level. - * + * */ rtems_raw_irq_disable off; /* @@ -204,7 +204,7 @@ typedef struct { /* * C callable function enabling to get handler currently connected to a vector - * + * */ rtems_raw_irq_hdl get_hdl_from_vector(rtems_vector_offset); @@ -335,7 +335,7 @@ typedef union { page_table_bits bits; unsigned int table_entry; } page_table_entry; - + /* * definitions related to page table entry */ @@ -371,12 +371,12 @@ extern void _CPU_disable_cache(); extern void _CPU_enable_cache(); extern int _CPU_map_phys_address (void **mappedAddress, void *physAddress, - int size, int flag); -extern int _CPU_unmap_virt_address (void *mappedAddress, int size); + int size, int flag); +extern int _CPU_unmap_virt_address (void *mappedAddress, int size); extern int _CPU_change_memory_mapping_attribute (void **newAddress, void *mappedAddress, unsigned int size, unsigned int flag); -extern int _CPU_display_memory_attribute(); +extern int _CPU_display_memory_attribute(); # endif /* ASM */ diff --git a/c/src/lib/libcpu/i386/cpuModel.S b/c/src/lib/libcpu/i386/cpuModel.S index 74fffd31d2..263f824004 100644 --- a/c/src/lib/libcpu/i386/cpuModel.S +++ b/c/src/lib/libcpu/i386/cpuModel.S @@ -5,15 +5,15 @@ * * Intel also provides public similar code in the book * called : - * + * * Pentium Processor Family * Developer Family * Volume 3 : Architecture and Programming Manual * * At the following place : - * + * * Chapter 5 : Feature determination - * Chapter 25: CPUID instruction + * Chapter 25: CPUID instruction * * COPYRIGHT (c) 1998 valette@crf.canon.fr * @@ -28,100 +28,100 @@ #include <rtems/score/registers.h> BEGIN_CODE - PUBLIC(checkCPUtypeSetCr0); -/* - * check Processor type: 386, 486, 6x86(L) or CPUID capable processor + PUBLIC(checkCPUtypeSetCr0); +/* + * check Processor type: 386, 486, 6x86(L) or CPUID capable processor */ SYM (checkCPUtypeSetCr0): /* - * Assume 386 for now + * Assume 386 for now */ - movl $3, SYM (x86) + movl $3, SYM (x86) /* * Start using the EFLAGS AC bit determination method described in * the book mentioned above page 5.1. If this bit can be set we * have a 486 or above. */ pushfl /* save EFLAGS */ - + pushfl /* Get EFLAGS in EAX */ popl eax - + movl eax,ecx /* save original EFLAGS in ECX */ xorl $EFLAGS_ALIGN_CHECK,eax /* flip AC bit in EAX */ pushl eax /* set EAX as EFLAGS */ - popfl + popfl pushfl /* Get new EFLAGS in EAX */ popl eax - + xorl ecx,eax /* check if AC bit changed */ - andl $EFLAGS_ALIGN_CHECK,eax + andl $EFLAGS_ALIGN_CHECK,eax je is386 /* If not : we have a 386 */ /* - * Assume 486 for now + * Assume 486 for now */ movl $4,SYM (x86) movl ecx,eax /* Restore orig EFLAGS in EAX */ xorl $EFLAGS_ID,eax /* flip ID flag */ pushl eax /* set EAX as EFLAGS */ - popfl + popfl pushfl /* Get new EFLAGS in EAX */ - popl eax - + popl eax + xorl ecx,eax /* check if ID bit changed */ andl $EFLAGS_ID,eax - /* + /* * if we are on a straight 486DX, * SX, or 487SX we can't change it - * OTOH 6x86MXs and MIIs check OK + * OTOH 6x86MXs and MIIs check OK * Also if we are on a Cyrix 6x86(L) */ je is486x -isnew: +isnew: /* * restore original EFLAGS */ popfl incl SYM(have_cpuid) /* we have CPUID instruction */ - /* use it to get : + /* use it to get : * processor type, * processor model, * processor mask, * by using it with EAX = 1 */ - movl $1, eax - cpuid + movl $1, eax + cpuid movl ecx,SYM(x86_capability_x) /* store ecx feature flags */ movb al, cl /* save reg for future use */ - + andb $0x0f,ah /* mask processor family */ movb ah,SYM (x86) /* put result in x86 var */ - + andb $0xf0, al /* get model */ shrb $4, al movb al,SYM (x86_model) /* store it in x86_model */ - + andb $0x0f, cl /* get mask revision */ movb cl,SYM (x86_mask) /* store it in x86_mask */ - + movl edx,SYM(x86_capability) /* store feature flags in x86_capability */ - + /* get vendor info by using CPUID with EXA = 0 */ - xorl eax, eax + xorl eax, eax cpuid /* * store results contained in ebx, edx, ecx in * x86_vendor_id variable. */ - movl ebx,SYM(x86_vendor_id) - movl edx,SYM(x86_vendor_id)+4 - movl ecx,SYM(x86_vendor_id)+8 + movl ebx,SYM(x86_vendor_id) + movl edx,SYM(x86_vendor_id)+4 + movl ecx,SYM(x86_vendor_id)+8 movl cr0,eax /* 486+ */ andl $(CR0_PAGING | CR0_PROTECTION_ENABLE | CR0_EXTENSION_TYPE), eax @@ -180,7 +180,7 @@ is486x: xor ax,ax getCx86($0xfe) /* DIR0 : let's check this is a 6x86(L) */ andb $0xf0,al /* should be 3xh */ - cmpb $0x30,al + cmpb $0x30,al jne n6x86 getCx86($0xe9) /* CCR5 : we reset the SLOP bit */ andb $0xfd,al /* so that udelay calculation */ @@ -206,7 +206,7 @@ is386: /* restore original EFLAGS */ 2: movl eax,cr0 call check_x87 ret - + /* * We depend on ET to be correct. This checks for 287/387. @@ -228,7 +228,7 @@ check_x87: ret END_CODE - + BEGIN_DATA PUBLIC(x86) PUBLIC(have_cpuid) @@ -239,20 +239,20 @@ BEGIN_DATA PUBLIC(x86_vendor_id) PUBLIC(hard_math) -SYM(x86): +SYM(x86): .byte 0 -SYM(have_cpuid): +SYM(have_cpuid): .long 0 -SYM(x86_model): +SYM(x86_model): .byte 0 -SYM(x86_mask): +SYM(x86_mask): .byte 0 -SYM(x86_capability): - .long 0 -SYM(x86_capability_x): - .long 0 -SYM(x86_vendor_id): +SYM(x86_capability): + .long 0 +SYM(x86_capability_x): + .long 0 +SYM(x86_vendor_id): .zero 13 -SYM(hard_math): +SYM(hard_math): .byte 0 END_DATA diff --git a/c/src/lib/libcpu/i386/cpuModel.h b/c/src/lib/libcpu/i386/cpuModel.h index cb4a4daea4..f11062a341 100644 --- a/c/src/lib/libcpu/i386/cpuModel.h +++ b/c/src/lib/libcpu/i386/cpuModel.h @@ -27,7 +27,7 @@ extern char x86_mask; extern int x86_capability; /* cpuid:EDX */ extern int x86_capability_x; /* cpuid:ECX */ extern char x86_vendor_id[13]; -extern int have_cpuid; +extern int have_cpuid; extern unsigned char Cx86_step; /* cyrix processor identification */ extern void printCpuInfo(); /* Display this information on console in ascii form */ diff --git a/c/src/lib/libcpu/i386/displayCpu.c b/c/src/lib/libcpu/i386/displayCpu.c index 97ca5ddb8b..b0f88c9312 100644 --- a/c/src/lib/libcpu/i386/displayCpu.c +++ b/c/src/lib/libcpu/i386/displayCpu.c @@ -134,7 +134,7 @@ static const char * AMDmodel(void) { const char *p=NULL; int i; - + if (x86_model < 16) for (i=0; i<sizeof(amd_models)/sizeof(struct cpu_model_info); i++) if (amd_models[i].x86 == x86) { @@ -187,14 +187,14 @@ void printCpuInfo(void) "16", "17", "18", "19", "20", "21", "22", "23" "24", "25", "26", "27", "28", "29", "30", "31" }; - - printk("cpu : %c86\n", x86+'0'); + + printk("cpu : %c86\n", x86+'0'); printk("model : %s\n", have_cpuid ? getmodel(x86, x86_model) : "unknown"); if (x86_vendor_id [0] == '\0') strcpy(x86_vendor_id, "unknown"); printk("vendor_id : %s\n", x86_vendor_id); - + if (x86_mask) if (strncmp(x86_vendor_id, "Cyrix", 5) != 0) { printk("stepping : %d\n", x86_mask); @@ -204,7 +204,7 @@ void printCpuInfo(void) } else printk("stepping : unknown\n"); - + printk("fpu : %s\n", (hard_math ? "yes" : "no")); printk("cpuid : %s\n", (have_cpuid ? "yes" : "no")); printk("flags :"); diff --git a/c/src/lib/libcpu/i386/idtr.S b/c/src/lib/libcpu/i386/idtr.S index 09a1121765..125b545b96 100644 --- a/c/src/lib/libcpu/i386/idtr.S +++ b/c/src/lib/libcpu/i386/idtr.S @@ -26,7 +26,7 @@ PUBLIC (i386_get_info_from_IDTR) PUBLIC (i386_set_IDTR) PUBLIC (i386_get_info_from_GDTR) PUBLIC (i386_set_GDTR) - + SYM (i386_get_info_from_IDTR): movl 4(esp), ecx /* get location where table address */ /* must be stored */ @@ -52,7 +52,7 @@ SYM (i386_get_info_from_IDTR): extern void i386_set_IDTR (interrupt_gate_descriptor* table, unsigned limit); */ -SYM (i386_set_IDTR): +SYM (i386_set_IDTR): leal 4(esp), edx /* load in edx address of input */ /* parameter "table" */ @@ -73,8 +73,8 @@ SYM (i386_set_IDTR): extern void i386_get_info_from_GDTR (segment_descriptors** table, unsigned* limit); */ - -SYM (i386_get_info_from_GDTR): + +SYM (i386_get_info_from_GDTR): movl 4(esp), ecx /* get location where table address */ /* must be stored */ movl 8(esp), edx /* get location table size must be stored */ @@ -97,7 +97,7 @@ SYM (i386_get_info_from_GDTR): * Must be called with interrupts masked at processor level!!!. * extern void i386_set_GDTR (segment_descriptors*, unsigned limit); */ -SYM (i386_set_GDTR): +SYM (i386_set_GDTR): leal 4(esp), edx /* load in edx address of input */ /* parameter "table" */ @@ -111,7 +111,7 @@ SYM (i386_set_GDTR): lgdt (edx) ret - + END_CODE END diff --git a/c/src/lib/libcpu/i386/page.c b/c/src/lib/libcpu/i386/page.c index b27dc2b920..45d9aaadd2 100644 --- a/c/src/lib/libcpu/i386/page.c +++ b/c/src/lib/libcpu/i386/page.c @@ -80,22 +80,22 @@ int init_paging(void) page_table *pageTable; unsigned int physPage; int nbTables=0; - + /* * rtemsFreeMemStart is the last valid 32-bits address * so the size is rtemsFreeMemStart + 4 */ memorySize = rtemsFreeMemStart + 4; - + nbPages = ( (memorySize - 1) / PG_SIZE ) + 1; nbTables = ( (memorySize - 1) / FOUR_MB ) + 2; /* allocate 1 page more to page alignement */ - Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) ); + Tables = (char *)malloc( (nbTables + 1)*sizeof(page_table) ); if ( Tables == NULL ){ return -1; /*unable to allocate memory */ } - + /* 4K-page alignement */ Tables += (PG_SIZE - (int)Tables) & 0xFFF; @@ -139,7 +139,7 @@ int init_paging(void) directoryEntry ++; pageTable ++; } - + nbInitPages++; } @@ -149,8 +149,8 @@ int init_paging(void) i386_set_cr3( regCr3.i ); - _CPU_enable_cache(); - _CPU_enable_paging(); + _CPU_enable_cache(); + _CPU_enable_paging(); return 0; } @@ -189,13 +189,13 @@ int _CPU_map_phys_address( int size, int flag ) -{ +{ page_table *localPageTable; unsigned int lastAddress, countAddress; char *Tables; linear_address virtualAddress; unsigned char pagingWasEnabled; - + pagingWasEnabled = 0; if (_CPU_is_paging_enabled()){ @@ -215,7 +215,7 @@ int _CPU_map_phys_address( /* Need to allocate a new page table */ if (pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address == 0){ /* We allocate 2 pages to perform 4k-page alignement */ - Tables = (char *)malloc(2*sizeof(page_table)); + Tables = (char *)malloc(2*sizeof(page_table)); if ( Tables == NULL ){ if (pagingWasEnabled) _CPU_enable_paging(); @@ -225,7 +225,7 @@ int _CPU_map_phys_address( Tables += (PG_SIZE - (int)Tables) & 0xFFF; /* Reset Table */ - memset( Tables, 0, sizeof(page_table) ); + memset( Tables, 0, sizeof(page_table) ); pageDirectory->pageDirEntry[directoryEntry].bits.page_frame_address = (unsigned int)Tables >> 12; pageDirectory->pageDirEntry[directoryEntry].bits.available = 0; @@ -237,7 +237,7 @@ int _CPU_map_phys_address( pageDirectory->pageDirEntry[directoryEntry].bits.writable = 1; pageDirectory->pageDirEntry[directoryEntry].bits.present = 1; } - + localPageTable = (page_table *)(pageDirectory-> pageDirEntry[directoryEntry].bits. @@ -264,7 +264,7 @@ int _CPU_map_phys_address( countAddress += PG_SIZE; tableEntry++; - if (tableEntry >= MAX_ENTRY){ + if (tableEntry >= MAX_ENTRY){ tableEntry = 0; directoryEntry++; } @@ -285,7 +285,7 @@ static void Paging_Table_Compress(void) { unsigned int dirCount, pageCount; page_table *localPageTable; - + if (tableEntry == 0){ dirCount = directoryEntry - 1; pageCount = MAX_ENTRY - 1; @@ -294,7 +294,7 @@ static void Paging_Table_Compress(void) dirCount = directoryEntry; pageCount = tableEntry - 1; } - + while (1){ localPageTable = (page_table *)(pageDirectory-> @@ -303,7 +303,7 @@ static void Paging_Table_Compress(void) if (localPageTable->pageTableEntry[pageCount].bits.present == 1){ pageCount++; - if (pageCount >= MAX_ENTRY){ + if (pageCount >= MAX_ENTRY){ pageCount = 0; dirCount++; } @@ -312,13 +312,13 @@ static void Paging_Table_Compress(void) if (pageCount == 0) { - if (dirCount == 0){ + if (dirCount == 0){ break; } else { pageCount = MAX_ENTRY - 1; dirCount-- ; - } + } } else pageCount-- ; @@ -327,8 +327,8 @@ static void Paging_Table_Compress(void) directoryEntry = dirCount; tableEntry = pageCount; } - - + + /* * Unmap the virtual address from the tables * (we do not deallocate the table already allocated) @@ -338,14 +338,14 @@ int _CPU_unmap_virt_address( void *mappedAddress, int size ) -{ +{ linear_address linearAddr; page_table *localPageTable; unsigned int lastAddr ; unsigned int dirCount ; unsigned char pagingWasEnabled; - + pagingWasEnabled = 0; if (_CPU_is_paging_enabled()){ @@ -371,15 +371,15 @@ int _CPU_unmap_virt_address( localPageTable = (page_table *)(pageDirectory-> pageDirEntry[linearAddr.bits.directory].bits. page_frame_address << 12); - + if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){ if (pagingWasEnabled) _CPU_enable_paging(); return -1; } - - localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0; - + + localPageTable->pageTableEntry[linearAddr.bits.page].bits.present = 0; + linearAddr.address += PG_SIZE ; } Paging_Table_Compress(); @@ -390,7 +390,7 @@ int _CPU_unmap_virt_address( } /* - * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE + * Modify the flags PRESENT, WRITABLE, USER, WRITE_TROUGH, CACHE_DISABLE * of the page's descriptor. */ @@ -400,20 +400,20 @@ int _CPU_change_memory_mapping_attribute( unsigned int size, unsigned int flag ) -{ +{ linear_address linearAddr; page_table *localPageTable; unsigned int lastAddr ; unsigned char pagingWasEnabled; - + pagingWasEnabled = 0; if (_CPU_is_paging_enabled()){ pagingWasEnabled = 1; _CPU_disable_paging(); } - + linearAddr.address = (unsigned int)mappedAddress; lastAddr = (unsigned int)mappedAddress + (size - 1); @@ -430,18 +430,18 @@ int _CPU_change_memory_mapping_attribute( localPageTable = (page_table *)(pageDirectory-> pageDirEntry[linearAddr.bits.directory].bits. page_frame_address << 12); - + if (localPageTable->pageTableEntry[linearAddr.bits.page].bits.present == 0){ if (pagingWasEnabled) _CPU_enable_paging(); return -1; } - + localPageTable->pageTableEntry[linearAddr.bits.page].table_entry &= ~MASK_FLAGS ; localPageTable->pageTableEntry[linearAddr.bits.page].table_entry |= flag ; - + linearAddr.address += PG_SIZE ; - } + } if (newAddress != NULL) *newAddress = mappedAddress ; @@ -460,7 +460,7 @@ int _CPU_change_memory_mapping_attribute( #include <rtems/bspIo.h> int _CPU_display_memory_attribute(void) -{ +{ unsigned int dirCount, pageCount; cr0 regCr0; page_table *localPageTable; @@ -468,9 +468,9 @@ int _CPU_display_memory_attribute(void) unsigned int prevPresent; unsigned int maxPage; unsigned char pagingWasEnabled; - + regCr0.i = i386_get_cr0(); - + printk("\n\n********* MEMORY CACHE CONFIGURATION *****\n"); printk("CR0 -> paging : %s\n",(regCr0.cr0.paging ? "ENABLE ":"DISABLE")); @@ -478,10 +478,10 @@ int _CPU_display_memory_attribute(void) if (regCr0.cr0.paging == 0) return 0; - + prevPresent = 0; prevCache = 1; - + pagingWasEnabled = 0; if (_CPU_is_paging_enabled()){ diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/bindec.S b/c/src/lib/libcpu/m68k/m68040/fpsp/bindec.S index 576f066388..0cdc10e34e 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/bindec.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/bindec.S @@ -21,7 +21,7 @@ // // Algorithm: // -// A1. Set RM and size ext; Set SIGMA = sign of input. +// A1. Set RM and size ext; Set SIGMA = sign of input. // The k-factor is saved for use in d7. Clear the // BINDEC_FLG for separating normalized/denormalized // input. If input is unnormalized or denormalized, @@ -31,15 +31,15 @@ // // A3. Compute ILOG. // ILOG is the log base 10 of the input value. It is -// approximated by adding e + 0.f when the original -// value is viewed as 2^^e * 1.f in extended precision. +// approximated by adding e + 0.f when the original +// value is viewed as 2^^e * 1.f in extended precision. // This value is stored in d6. // // A4. Clr INEX bit. -// The operation in A3 above may have set INEX2. +// The operation in A3 above may have set INEX2. // // A5. Set ICTR = 0; -// ICTR is a flag used in A13. It must be set before the +// ICTR is a flag used in A13. It must be set before the // loop entry A6. // // A6. Calculate LEN. @@ -61,9 +61,9 @@ // of ISCALE and X. A table is given in the code. // // A8. Clr INEX; Force RZ. -// The operation in A3 above may have set INEX2. +// The operation in A3 above may have set INEX2. // RZ mode is forced for the scaling operation to insure -// only one rounding error. The grs bits are collected in +// only one rounding error. The grs bits are collected in // the INEX flag for use in A10. // // A9. Scale X -> Y. @@ -92,11 +92,11 @@ // the mantissa by 10. // // A14. Convert the mantissa to bcd. -// The binstr routine is used to convert the LEN digit +// The binstr routine is used to convert the LEN digit // mantissa to bcd in memory. The input to binstr is // to be a fraction; i.e. (mantissa)/10^LEN and adjusted // such that the decimal point is to the left of bit 63. -// The bcd digits are stored in the correct position in +// The bcd digits are stored in the correct position in // the final string area in memory. // // A15. Convert the exponent to bcd. @@ -133,8 +133,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //BINDEC idnt 2,1 | Motorola 040 Floating Point Software Package @@ -173,7 +173,7 @@ bindec: // separating normalized/denormalized input. If the input // is a denormalized number, set the BINDEC_FLG memory word // to signal denorm. If the input is unnormalized, normalize -// the input and test for denormalized result. +// the input and test for denormalized result. // fmovel #rm_mode,%FPCR //set RM and ext movel (%a0),L_SCR2(%a6) //save exponent for sign check @@ -253,7 +253,7 @@ A3_cont: subw #0x3fff,%d0 //strip off bias faddw %d0,%fp0 //add in exp fsubs FONE,%fp0 //subtract off 1.0 - fbge pos_res //if pos, branch + fbge pos_res //if pos, branch fmulx LOG2UP1,%fp0 //if neg, mul by LOG2UP1 fmovel %fp0,%d6 //put ILOG in d6 as a lword bras A4_str //go move out ILOG @@ -263,14 +263,14 @@ pos_res: // A4. Clr INEX bit. -// The operation in A3 above may have set INEX2. +// The operation in A3 above may have set INEX2. -A4_str: +A4_str: fmovel #0,%FPSR //zero all of fpsr - nothing needed // A5. Set ICTR = 0; -// ICTR is a flag used in A13. It must be set before the +// ICTR is a flag used in A13. It must be set before the // loop entry A6. The lower word of d5 is used for ICTR. clrw %d5 //clear ICTR @@ -305,7 +305,7 @@ A4_str: // L_SCR1:x/x // L_SCR2:first word of X packed/Unchanged -A6_str: +A6_str: tstl %d7 //branch on sign of k bles k_neg //if k <= 0, LEN = ILOG + 1 - k movel %d7,%d4 //if k > 0, LEN = k @@ -377,13 +377,13 @@ LEN_ng: // L_SCR1:x/x // L_SCR2:first word of X packed/Unchanged -A7_str: +A7_str: tstl %d7 //test sign of k bgts k_pos //if pos and > 0, skip this cmpl %d6,%d7 //test k - ILOG blts k_pos //if ILOG >= k, skip this movel %d7,%d6 //if ((k<0) & (ILOG < k)) ILOG = k -k_pos: +k_pos: movel %d6,%d0 //calc ILOG + 1 - LEN in d0 addql #1,%d0 //add the 1 subl %d4,%d0 //sub off LEN @@ -397,9 +397,9 @@ k_pos: bgts no_inf //if false, skip rest addil #24,%d0 //add in 24 to iscale movel #24,%d2 //put 24 in d2 for A9 -no_inf: +no_inf: negl %d0 //and take abs of ISCALE -iscale: +iscale: fmoves FONE,%fp1 //init fp1 to 1 bfextu USER_FPCR(%a6){#26:#2},%d1 //get initial rmode bits lslw #1,%d1 //put them in bits 2:1 @@ -427,33 +427,33 @@ not_rp: leal PTENRM,%a1 //load a1 with RM table base rmode: clrl %d3 //clr table index -e_loop: +e_loop: lsrl #1,%d0 //shift next bit into carry bccs e_next //if zero, skip the mul fmulx (%a1,%d3),%fp1 //mul by 10**(d3_bit_no) -e_next: +e_next: addl #12,%d3 //inc d3 to next pwrten table entry tstl %d0 //test if ISCALE is zero bnes e_loop //if not, loop // A8. Clr INEX; Force RZ. -// The operation in A3 above may have set INEX2. +// The operation in A3 above may have set INEX2. // RZ mode is forced for the scaling operation to insure -// only one rounding error. The grs bits are collected in +// only one rounding error. The grs bits are collected in // the INEX flag for use in A10. // // Register usage: // Input/Output - fmovel #0,%FPSR //clr INEX + fmovel #0,%FPSR //clr INEX fmovel #rz_mode,%FPCR //set RZ rounding mode // A9. Scale X -> Y. // The mantissa is scaled to the desired number of significant // digits. The excess digits are collected in INEX2. If mul, -// Check d2 for excess 10 exponential value. If not zero, +// Check d2 for excess 10 exponential value. If not zero, // the iscale value would have caused the pwrten calculation // to overflow. Only a negative iscale can cause this, so // multiply by 10^(d2), which is now only allowed to be 24, @@ -482,7 +482,7 @@ e_next: // L_SCR1:x/x // L_SCR2:first word of X packed/Unchanged -A9_str: +A9_str: fmovex (%a0),%fp0 //load X from memory fabsx %fp0 //use abs(X) tstw %d5 //LAMBDA is in lower word of d5 @@ -500,9 +500,9 @@ sc_mul: movel #18,%d3 //load count for busy stack A9_loop: clrl -(%a7) //clear lword on stack - dbf %d3,A9_loop + dbf %d3,A9_loop moveb VER_TMP(%a6),(%a7) //write current version number - moveb #BUSY_SIZE-4,1(%a7) //write current busy size + moveb #BUSY_SIZE-4,1(%a7) //write current busy size moveb #0x10,0x44(%a7) //set fcefpte[15] bit movew #0x0023,0x40(%a7) //load cmdreg1b with mul command moveb #0xfe,0x8(%a7) //load all 1s to cu savepc @@ -539,7 +539,7 @@ A9_con: // fp1: 10^ISCALE/Unchanged // fp2: x/x -A10_st: +A10_st: fmovel %FPSR,%d0 //get FPSR fmovex %fp0,FP_SCR2(%a6) //move Y to memory leal FP_SCR2(%a6),%a2 //load a2 with ptr to FP_SCR2 @@ -555,9 +555,9 @@ A10_st: // routine expects the FPCR value to be in USER_FPCR for // mode and precision. The original FPCR is saved in L_SCR1. -A11_st: +A11_st: movel USER_FPCR(%a6),L_SCR1(%a6) //save it for later - andil #0x00000030,USER_FPCR(%a6) //set size to ext, + andil #0x00000030,USER_FPCR(%a6) //set size to ext, // ;block exceptions @@ -586,13 +586,13 @@ A11_st: // L_SCR2:first word of X packed/Unchanged A12_st: - moveml %d0-%d1/%a0-%a1,-(%a7) //save regs used by sintd0 + moveml %d0-%d1/%a0-%a1,-(%a7) //save regs used by sintd0 movel L_SCR1(%a6),-(%a7) movel L_SCR2(%a6),-(%a7) leal FP_SCR2(%a6),%a0 //a0 is ptr to F_SCR2(a6) fmovex %fp0,(%a0) //move Y to memory at FP_SCR2(a6) tstl L_SCR2(%a6) //test sign of original operand - bges do_fint //if pos, use Y + bges do_fint //if pos, use Y orl #0x80000000,(%a0) //if neg, use -Y do_fint: movel USER_FPSR(%a6),-(%a7) @@ -601,7 +601,7 @@ do_fint: addl #4,%a7 movel (%a7)+,L_SCR2(%a6) movel (%a7)+,L_SCR1(%a6) - moveml (%a7)+,%d0-%d1/%a0-%a1 //restore regs used by sint + moveml (%a7)+,%d0-%d1/%a0-%a1 //restore regs used by sint movel L_SCR2(%a6),FP_SCR2(%a6) //restore original exponent movel L_SCR1(%a6),USER_FPCR(%a6) //restore user's FPCR @@ -637,7 +637,7 @@ do_fint: // L_SCR1:original USER_FPCR/Unchanged // L_SCR2:first word of X packed/Unchanged -A13_st: +A13_st: swap %d5 //put ICTR in lower word of d5 tstw %d5 //check if ICTR = 0 bne not_zr //if non-zero, go to second test @@ -648,7 +648,7 @@ A13_st: movel %d4,%d0 //put LEN in d0 subql #1,%d0 //d0 = LEN -1 clrl %d3 //clr table index -l_loop: +l_loop: lsrl #1,%d0 //shift next bit into carry bccs l_next //if zero, skip the mul fmulx (%a1,%d3),%fp2 //mul by 10**(d3_bit_no) @@ -674,7 +674,7 @@ A13_con: subql #1,%d6 //subtract 1 from ILOG movew #1,%d5 //set ICTR fmovel #rm_mode,%FPCR //set rmode to RM - fmuls FTEN,%fp2 //compute 10^LEN + fmuls FTEN,%fp2 //compute 10^LEN bra A6_str //return to A6 and recompute YINT test_2: fmuls FTEN,%fp2 //compute 10^LEN @@ -690,7 +690,7 @@ fix_ex: fmovel #rm_mode,%FPCR //set rmode to RM bra A6_str //return to A6 and recompute YINT // -// Since ICTR <> 0, we have already been through one adjustment, +// Since ICTR <> 0, we have already been through one adjustment, // and shouldn't have another; this is to check if abs(YINT) = 10^LEN // 10^LEN is again computed using whatever table is in a1 since the // value calculated cannot be inexact. @@ -717,11 +717,11 @@ z_next: // A14. Convert the mantissa to bcd. -// The binstr routine is used to convert the LEN digit +// The binstr routine is used to convert the LEN digit // mantissa to bcd in memory. The input to binstr is // to be a fraction; i.e. (mantissa)/10^LEN and adjusted // such that the decimal point is to the left of bit 63. -// The bcd digits are stored in the correct position in +// The bcd digits are stored in the correct position in // the final string area in memory. // // @@ -747,7 +747,7 @@ z_next: // L_SCR1:original USER_FPCR/Unchanged // L_SCR2:first word of X packed/Unchanged -A14_st: +A14_st: fmovel #rz_mode,%FPCR //force rz for conversion fdivx %fp2,%fp0 //divide abs(YINT) by 10^LEN leal FP_SCR1(%a6),%a0 @@ -764,7 +764,7 @@ A14_st: bgts no_sft //if so, don't shift negl %d0 //make exp positive m_loop: - lsrl #1,%d2 //shift d2:d3 right, add 0s + lsrl #1,%d2 //shift d2:d3 right, add 0s roxrl #1,%d3 //the number of places dbf %d0,m_loop //given in d0 no_sft: @@ -819,7 +819,7 @@ zer_m: // L_SCR1:original USER_FPCR/Exponent digits on return from binstr // L_SCR2:first word of X packed/Unchanged -A15_st: +A15_st: tstb BINDEC_FLG(%a6) //check for denorm beqs not_denorm ftstx %fp0 //test for zero @@ -841,7 +841,7 @@ not_denorm: fbne not_zero //if zero, force exponent fmoves FONE,%fp0 //force exponent to 1 bras convrt //do it -not_zero: +not_zero: fmovel %d6,%fp0 //float ILOG fabsx %fp0 //get abs of ILOG convrt: @@ -854,7 +854,7 @@ convrt: subiw #0x3ffd,%d0 //subtract off bias negw %d0 //make exp positive x_loop: - lsrl #1,%d2 //shift d2:d3 right + lsrl #1,%d2 //shift d2:d3 right roxrl #1,%d3 //the number of places dbf %d0,x_loop //given in d0 x_loop_fin: @@ -865,12 +865,12 @@ x_loop_fin: movel #4,%d0 //put 4 in d0 for binstr call leal L_SCR1(%a6),%a0 //a0 is ptr to L_SCR1 for exp digits bsr binstr //call binstr to convert exp - movel L_SCR1(%a6),%d0 //load L_SCR1 lword to d0 + movel L_SCR1(%a6),%d0 //load L_SCR1 lword to d0 movel #12,%d1 //use d1 for shift count lsrl %d1,%d0 //shift d0 right by 12 bfins %d0,FP_SCR1(%a6){#4:#12} //put e3:e2:e1 in FP_SCR1 lsrl %d1,%d0 //shift d0 right by 12 - bfins %d0,FP_SCR1(%a6){#16:#4} //put e4 in FP_SCR1 + bfins %d0,FP_SCR1(%a6){#16:#4} //put e4 in FP_SCR1 tstb %d0 //check if e4 is zero beqs A16_st //if zero, skip rest orl #opaop_mask,USER_FPSR(%a6) //set OPERR & AIOP in USER_FPSR @@ -901,14 +901,14 @@ x_loop_fin: A16_st: clrl %d0 //clr d0 for collection of signs - andib #0x0f,FP_SCR1(%a6) //clear first nibble of FP_SCR1 + andib #0x0f,FP_SCR1(%a6) //clear first nibble of FP_SCR1 tstl L_SCR2(%a6) //check sign of original mantissa bges mant_p //if pos, don't set SM moveql #2,%d0 //move 2 in to d0 for SM mant_p: tstl %d6 //check sign of ILOG bges wr_sgn //if pos, don't set SE - addql #1,%d0 //set bit 0 in d0 for SE + addql #1,%d0 //set bit 0 in d0 for SE wr_sgn: bfins %d0,FP_SCR1(%a6){#0:#2} //insert SM and SE into FP_SCR1 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/binstr.S b/c/src/lib/libcpu/m68k/m68040/fpsp/binstr.S index 96f2592995..0c4b6e606f 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/binstr.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/binstr.S @@ -61,8 +61,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //BINSTR idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/bugfix.S b/c/src/lib/libcpu/m68k/m68040/fpsp/bugfix.S index 6c615934a3..17de21b1df 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/bugfix.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/bugfix.S @@ -8,7 +8,7 @@ // // Fixes for bugs: 1238 // -// Bug: 1238 +// Bug: 1238 // // // /* The following dirty_bit clear should be left in @@ -153,8 +153,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package @@ -168,8 +168,8 @@ .global b1238_fix b1238_fix: // -// This code is entered only on completion of the handling of an -// nu-generated ovfl, unfl, or inex exception. If the version +// This code is entered only on completion of the handling of an +// nu-generated ovfl, unfl, or inex exception. If the version // number of the fsave is not $40, this handler is not necessary. // Simply branch to fix_done and exit normally. // @@ -185,7 +185,7 @@ b1238_fix: // // Test the register conflict aspect. If opclass0, check for -// cu src equal to xu dest or equal to nu dest. If so, go to +// cu src equal to xu dest or equal to nu dest. If so, go to // op0. Else, or if opclass2, check for cu dest equal to // xu dest or equal to nu dest. If so, go to tst_opcl. Else, // exit, it is not the bug case. @@ -197,17 +197,17 @@ b1238_fix: bne op2sgl //not opclass 0, check op2 // // Check for cu and nu register conflict. If one exists, this takes -// priority over a cu and xu conflict. +// priority over a cu and xu conflict. // - bfextu CMDREG1B(%a6){#3:#3},%d0 //get 1st src + bfextu CMDREG1B(%a6){#3:#3},%d0 //get 1st src bfextu CMDREG3B(%a6){#6:#3},%d1 //get 3rd dest cmpb %d0,%d1 beqs op0 //if equal, continue bugfix // -// Check for cu dest equal to nu dest. If so, go and fix the +// Check for cu dest equal to nu dest. If so, go and fix the // bug condition. Otherwise, exit. // - bfextu CMDREG1B(%a6){#6:#3},%d0 //get 1st dest + bfextu CMDREG1B(%a6){#6:#3},%d0 //get 1st dest cmpb %d0,%d1 //cmp 1st dest with 3rd dest beqs op0 //if equal, continue bugfix // @@ -216,7 +216,7 @@ b1238_fix: bfextu CMDREG2B(%a6){#6:#3},%d1 //get 2nd dest cmpb %d0,%d1 //cmp 1st dest with 2nd dest beqs op0_xu //if equal, continue bugfix - bfextu CMDREG1B(%a6){#3:#3},%d0 //get 1st src + bfextu CMDREG1B(%a6){#3:#3},%d0 //get 1st src cmpb %d0,%d1 //cmp 1st src with 2nd dest beq op0_xu bne fix_done //if the reg checks fail, exit @@ -246,7 +246,7 @@ setete15: // // We have the case in which a conflict exists between the cu src or -// dest and the dest of the xu. We must clear the instruction in +// dest and the dest of the xu. We must clear the instruction in // the cu and restore the state, allowing the instruction in the // xu to complete. Remember, the instruction in the nu // was exceptional, and was completed by the appropriate handler. @@ -256,7 +256,7 @@ setete15: // exceptional, we choose to kill the process. // // Items saved from the stack: -// +// // $3c stag - L_SCR1 // $40 cmdreg1b - L_SCR2 // $44 dtag - L_SCR3 @@ -265,8 +265,8 @@ setete15: // fpu. // op0_xu: - movel STAG(%a6),L_SCR1(%a6) - movel CMDREG1B(%a6),L_SCR2(%a6) + movel STAG(%a6),L_SCR1(%a6) + movel CMDREG1B(%a6),L_SCR2(%a6) movel DTAG(%a6),L_SCR3(%a6) andil #0xe0000000,L_SCR3(%a6) moveb #0,CU_SAVEPC(%a6) @@ -275,13 +275,13 @@ op0_xu: fsave -(%a7) // // Check if the instruction which just completed was exceptional. -// +// cmpw #0x4060,(%a7) beq op0_xb -// +// // It is necessary to isolate the result of the instruction in the // xu if it is to fp0 - fp3 and write that value to the USER_FPn -// locations on the stack. The correct destination register is in +// locations on the stack. The correct destination register is in // cmdreg2b. // bfextu CMDREG2B(%a6){#6:#3},%d0 //get dest register no @@ -340,7 +340,7 @@ op0_sete15: // // The frame returned is busy. It is not possible to reconstruct -// the code sequence to allow completion. We will jump to +// the code sequence to allow completion. We will jump to // fpsp_fmt_error and allow the kernel to kill the process. // op0_xb: @@ -355,20 +355,20 @@ op2sgl: cmpiw #0x4400,%d0 //test for opclass 2 and size=sgl bne fix_done //if not, it is not bug 1238 // -// Check for cu dest equal to nu dest or equal to xu dest, with +// Check for cu dest equal to nu dest or equal to xu dest, with // a cu and nu conflict taking priority an nu conflict. If either, // go and fix the bug condition. Otherwise, exit. // - bfextu CMDREG1B(%a6){#6:#3},%d0 //get 1st dest + bfextu CMDREG1B(%a6){#6:#3},%d0 //get 1st dest bfextu CMDREG3B(%a6){#6:#3},%d1 //get 3rd dest cmpb %d0,%d1 //cmp 1st dest with 3rd dest beq op2_com //if equal, continue bugfix - bfextu CMDREG2B(%a6){#6:#3},%d1 //get 2nd dest + bfextu CMDREG2B(%a6){#6:#3},%d1 //get 2nd dest cmpb %d0,%d1 //cmp 1st dest with 2nd dest bne fix_done //if the reg checks fail, exit // // We have the case in which a conflict exists between the cu src or -// dest and the dest of the xu. We must clear the instruction in +// dest and the dest of the xu. We must clear the instruction in // the cu and restore the state, allowing the instruction in the // xu to complete. Remember, the instruction in the nu // was exceptional, and was completed by the appropriate handler. @@ -378,7 +378,7 @@ op2sgl: // exceptional, we choose to kill the process. // // Items saved from the stack: -// +// // $3c stag - L_SCR1 // $40 cmdreg1b - L_SCR2 // $44 dtag - L_SCR3 @@ -388,9 +388,9 @@ op2sgl: // fpu. // op2_xu: - movel STAG(%a6),L_SCR1(%a6) - movel CMDREG1B(%a6),L_SCR2(%a6) - movel DTAG(%a6),L_SCR3(%a6) + movel STAG(%a6),L_SCR1(%a6) + movel CMDREG1B(%a6),L_SCR2(%a6) + movel DTAG(%a6),L_SCR3(%a6) andil #0xe0000000,L_SCR3(%a6) moveb #0,CU_SAVEPC(%a6) movel ETEMP(%a6),FP_SCR2(%a6) @@ -401,13 +401,13 @@ op2_xu: fsave -(%a7) // // Check if the instruction which just completed was exceptional. -// +// cmpw #0x4060,(%a7) beq op2_xb -// +// // It is necessary to isolate the result of the instruction in the // xu if it is to fp0 - fp3 and write that value to the USER_FPn -// locations on the stack. The correct destination register is in +// locations on the stack. The correct destination register is in // cmdreg2b. // bfextu CMDREG2B(%a6){#6:#3},%d0 //get dest register no @@ -460,12 +460,12 @@ op2_com: bnes case2 movew #0x43FF,ETEMP_EX(%a6) //to double +max bra finish -case2: +case2: cmpw #0xC07F,ETEMP_EX(%a6) //single -max bnes case3 movew #0xC3FF,ETEMP_EX(%a6) //to double -max bra finish -case3: +case3: cmpw #0x3F80,ETEMP_EX(%a6) //single +min bnes case4 movew #0x3C00,ETEMP_EX(%a6) //to double +min @@ -481,7 +481,7 @@ case4: // an fline illegal instruction to be executed. // // You should replace the jump to fpsp_fmt_error with a jump -// to the entry point used to kill a process. +// to the entry point used to kill a process. // op2_xb: jmp fpsp_fmt_error diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/decbin.S b/c/src/lib/libcpu/m68k/m68040/fpsp/decbin.S index 03f0b084a0..5f39738d0e 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/decbin.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/decbin.S @@ -62,17 +62,17 @@ // it is negative. // // Clean up and return. Check if the final mul or div resulted -// in an inex2 exception. If so, set inex1 in the fpsr and +// in an inex2 exception. If so, set inex1 in the fpsr and // check if the inex1 exception is enabled. If so, set d7 upper // word to $0100. This will signal unimp.sa that an enabled inex1 // exception occurred. Unimp will fix the stack. -// +// // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //DECBIN idnt 2,1 | Motorola 040 Floating Point Software Package @@ -109,7 +109,7 @@ RTABLE: .byte 0,0,0,0 .set FSTRT,0 // .set ESTRT,4 - .set EDIGITS,2 // + .set EDIGITS,2 // // // Constants in single precision FZERO: .long 0x00000000 @@ -226,7 +226,7 @@ nextlw: addql #1,%d1 //inc lw pointer in mantissa cmpl #2,%d1 //test for last lw ble loadlw //if not, get last one - + // // Check the sign of the mant and make the value in fp0 the same sign. // @@ -234,7 +234,7 @@ m_sign: btst #31,(%a0) //test sign of the mantissa beq ap_st_z //if clear, go to append/strip zeros fnegx %fp0 //if set, negate fp0 - + // // Append/strip zeros: // @@ -409,7 +409,7 @@ ap_n_en: // // Pwrten calculates the exponent factor in the selected rounding mode // according to the following table: -// +// // Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode // // ANY ANY RN RN @@ -497,7 +497,7 @@ mul: // it will be inex2, but will be reported as inex1 by get_op. // end_dec: - fmovel %FPSR,%d0 //get status register + fmovel %FPSR,%d0 //get status register bclrl #inex2_bit+8,%d0 //test for inex2 and clear it fmovel %d0,%FPSR //return status reg w/o inex2 beqs no_exc //skip this if no exc diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S b/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S index 425faac9ab..7fde4078b3 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/do_func.S @@ -6,11 +6,11 @@ // Do_func performs the unimplemented operation. The operation // to be performed is determined from the lower 7 bits of the // extension word (except in the case of fmovecr and fsincos). -// The opcode and tag bits form an index into a jump table in -// tbldo.sa. Cases of zero, infinity and NaN are handled in +// The opcode and tag bits form an index into a jump table in +// tbldo.sa. Cases of zero, infinity and NaN are handled in // do_func by forcing the default result. Normalized and // denormalized (there are no unnormalized numbers at this -// point) are passed onto the emulation code. +// point) are passed onto the emulation code. // // CMDREG1B and STAG are extracted from the fsave frame // and combined to form the table index. The function called @@ -24,8 +24,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. DO_FUNC: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -70,7 +70,7 @@ do_func: // directly. // bfextu CMDREG1B(%a6){#0:#6},%d0 //get opclass and src fields - cmpil #0x17,%d0 //if op class and size fields are $17, + cmpil #0x17,%d0 //if op class and size fields are $17, // ;it is FMOVECR; if not, continue bnes not_fmovecr jmp smovcr //fmovecr; jmp directly to emulation @@ -78,7 +78,7 @@ do_func: not_fmovecr: movew CMDREG1B(%a6),%d0 andl #0x7F,%d0 - cmpil #0x38,%d0 //if the extension is >= $38, + cmpil #0x38,%d0 //if the extension is >= $38, bge serror //it is illegal bfextu STAG(%a6){#0:#3},%d1 lsll #3,%d0 //make room for STAG @@ -113,7 +113,7 @@ ld_mzinx: bsr ld_mzero //if neg, load neg zero, return here bra t_inx2 //now, set the inx for the next inst // -// Load a signed zero to fp0; do not set inex2/ainex +// Load a signed zero to fp0; do not set inex2/ainex // .global szero szero: @@ -121,7 +121,7 @@ szero: bne ld_mzero //if neg, load neg zero bra ld_pzero //load positive zero // -// Load a signed infinity to fp0; do not set inex2/ainex +// Load a signed infinity to fp0; do not set inex2/ainex // .global sinf sinf: @@ -129,7 +129,7 @@ sinf: bne ld_minf //if negative branch bra ld_pinf // -// Load a signed one to fp0; do not set inex2/ainex +// Load a signed one to fp0; do not set inex2/ainex // .global sone sone: @@ -137,7 +137,7 @@ sone: bne ld_mone bra ld_pone // -// Load a signed pi/2 to fp0; do not set inex2/ainex +// Load a signed pi/2 to fp0; do not set inex2/ainex // .global spi_2 spi_2: @@ -162,13 +162,13 @@ sopr_inf: bne t_operr bra ld_pinf // -// FLOGNP1 +// FLOGNP1 // .global sslognp1 sslognp1: fmovemx (%a0),%fp0-%fp0 fcmpb #-1,%fp0 - fbgt slognp1 + fbgt slognp1 fbeq t_dz2 //if = -1, divide by zero exception fmovel #0,%FPSR //clr N flag bra t_operr //take care of operands < -1 @@ -188,7 +188,7 @@ setoxm1i: // .global sslogn sslogn: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) bne t_operr //take care of operands < 0 cmpiw #0x3fff,LOCAL_EX(%a0) //test for 1.0 input bne slogn @@ -201,7 +201,7 @@ sslogn: .global sslognd sslognd: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) beq slognd bra t_operr //take care of operands < 0 @@ -223,7 +223,7 @@ sslog10: .global sslog10d sslog10d: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) beq slog10d bra t_operr //take care of operands < 0 @@ -245,7 +245,7 @@ sslog2: .global sslog2d sslog2d: - btstb #sign_bit,LOCAL_EX(%a0) + btstb #sign_bit,LOCAL_EX(%a0) beq slog2d bra t_operr //take care of operands < 0 @@ -312,7 +312,7 @@ smod_zsn: btstl #7,%d0 //test if + or - beq ld_pzero //if pos then load +0 bra ld_mzero //else neg load -0 - + smod_fpn: moveb ETEMP(%a6),%d1 //get sign of src op moveb FPTEMP(%a6),%d0 //get sign of dst op @@ -329,7 +329,7 @@ smod_nrm: fmovel USER_FPCR(%a6),%fpcr //use user's rmode and precision fmovex FPTEMP(%a6),%fp0 //return dest to fp0 rts - + // // FREM // @@ -374,7 +374,7 @@ prem: lea premt,%a1 movel (%a1,%d1.w*4),%a1 jmp (%a1) - + srem_snan: bra src_nan srem_dnan: @@ -392,7 +392,7 @@ srem_zsn: btstl #7,%d0 //test if + or - beq ld_pzero //if pos then load +0 bra ld_mzero //else neg load -0 - + srem_fpn: moveb ETEMP(%a6),%d1 //get sign of src op moveb FPTEMP(%a6),%d0 //get sign of dst op @@ -500,7 +500,7 @@ ssincosnan: bsr sto_cos bra src_nan // -// This code forces default values for the zero, inf, and nan cases +// This code forces default values for the zero, inf, and nan cases // in the transcendentals code. The CC bits must be set in the // stacked FPSR to be correctly reported. // diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/gen_except.S b/c/src/lib/libcpu/m68k/m68040/fpsp/gen_except.S index 7bb073d657..fa50b40c59 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/gen_except.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/gen_except.S @@ -4,10 +4,10 @@ // gen_except.sa 3.7 1/16/92 // // gen_except --- FPSP routine to detect reportable exceptions -// +// // This routine compares the exception enable byte of the // user_fpcr on the stack with the exception status byte -// of the user_fpsr. +// of the user_fpsr. // // Any routine which may report an exceptions must load // the stack frame in memory with the exceptional operand(s). @@ -25,14 +25,14 @@ // // Note: The IEEE standard specifies that inex2 is to be // reported if ovfl occurs and the ovfl enable bit is not -// set but the inex2 enable bit is. +// set but the inex2 enable bit is. // // // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. GEN_EXCEPT: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -72,12 +72,12 @@ gen_except: // movel ETEMP_EX(%a6),ETEMP_EX(%a1) //copy etemp from unimp movel ETEMP_HI(%a6),ETEMP_HI(%a1) //frame to busy frame - movel ETEMP_LO(%a6),ETEMP_LO(%a1) + movel ETEMP_LO(%a6),ETEMP_LO(%a1) movel CMDREG1B(%a6),CMDREG1B(%a1) //set inst in frame to unimp movel CMDREG1B(%a6),%d0 //fix cmd1b to make it andl #0x03c30000,%d0 //work for cmd3b bfextu CMDREG1B(%a6){#13:#1},%d1 //extract bit 2 - lsll #5,%d1 + lsll #5,%d1 swap %d1 orl %d1,%d0 //put it in the right place bfextu CMDREG1B(%a6){#10:#3},%d1 //extract bit 3,4,5 @@ -88,7 +88,7 @@ gen_except: // // Or in the FPSR from the emulation with the USER_FPSR on the stack. // - fmovel %FPSR,%d0 + fmovel %FPSR,%d0 orl %d0,USER_FPSR(%a6) movel USER_FPSR(%a6),FPSR_SHADOW(%a1) //set exc bits orl #sx_mask,E_BYTE(%a1) @@ -110,7 +110,7 @@ test_rev: cmpib #UNIMP_41_SIZE-4,1(%a7) //test for rev unimp frame bnel fpsp_fmt_error //if not $28 or $30 leal UNIMP_41_SIZE+LOCAL_SIZE(%a7),%a1 - + unimp_con: // // Fix up the new unimp frame with entries from the old unimp frame @@ -119,23 +119,23 @@ unimp_con: // // Or in the FPSR from the emulation with the USER_FPSR on the stack. // - fmovel %FPSR,%d0 + fmovel %FPSR,%d0 orl %d0,USER_FPSR(%a6) bra do_clean // // Frame is idle, so check for exceptions reported through -// USER_FPSR and set the unimp frame accordingly. +// USER_FPSR and set the unimp frame accordingly. // A7 must be incremented to the point before the // idle fsave vector to the unimp vector. // - + do_check: addl #4,%a7 //point A7 back to unimp frame // // Or in the FPSR from the emulation with the USER_FPSR on the stack. // - fmovel %FPSR,%d0 + fmovel %FPSR,%d0 orl %d0,USER_FPSR(%a6) // // On a busy frame, we must clear the nmnexc bits. @@ -167,10 +167,10 @@ frame_com: bsun_exc: bra do_clean // -// The typical work to be done to the unimp frame to report an +// The typical work to be done to the unimp frame to report an // exception is to set the E1/E3 byte and clr the U flag. -// commonE1 does this for E1 exceptions, which are snan, -// operr, and dz. commonE3 does this for E3 exceptions, which +// commonE1 does this for E1 exceptions, which are snan, +// operr, and dz. commonE3 does this for E3 exceptions, which // are inex2 and inex1, and also clears the E1 exception bit // left over from the unimp exception. // @@ -188,7 +188,7 @@ uniE3: unsE3: tstb RES_FLG(%a6) - bnes unsE3_0 + bnes unsE3_0 unsE3_1: bsetb #E3,E_BYTE(%a6) //set E3 flag unsE3_0: @@ -196,7 +196,7 @@ unsE3_0: movel CMDREG1B(%a6),%d0 andl #0x03c30000,%d0 //work for cmd3b bfextu CMDREG1B(%a6){#13:#1},%d1 //extract bit 2 - lsll #5,%d1 + lsll #5,%d1 swap %d1 orl %d1,%d0 //put it in the right place bfextu CMDREG1B(%a6){#10:#3},%d1 //extract bit 3,4,5 @@ -220,8 +220,8 @@ no_match: beqs no_exc //if clear, exit bras ovfl_unfl //go to unfl_ovfl to determine if // ;it is an unsupp or unimp exc - -// No exceptions are to be reported. If the instruction was + +// No exceptions are to be reported. If the instruction was // unimplemented, no FPU restore is necessary. If it was // unsupported, we must perform the restore. no_exc: @@ -245,13 +245,13 @@ uni_no_exc: // // Unimplemented Instruction Handler: // Ovfl: -// Only scosh, setox, ssinh, stwotox, and scale can set overflow in +// Only scosh, setox, ssinh, stwotox, and scale can set overflow in // this manner. // Unfl: // Stwotox, setox, and scale can set underflow in this manner. // Any of the other Library Routines such that f(x)=x in which -// x is an extended denorm can report an underflow exception. -// It is the responsibility of the exception-causing exception +// x is an extended denorm can report an underflow exception. +// It is the responsibility of the exception-causing exception // to make sure that WBTEMP is correct. // // The exceptional operand is in FP_SCR1. @@ -308,7 +308,7 @@ busy_fr: movel CMDREG1B(%a6),%d0 //fix cmd1b to make it andl #0x03c30000,%d0 //work for cmd3b bfextu CMDREG1B(%a6){#13:#1},%d1 //extract bit 2 - lsll #5,%d1 + lsll #5,%d1 swap %d1 orl %d1,%d0 //put it in the right place bfextu CMDREG1B(%a6){#10:#3},%d1 //extract bit 3,4,5 @@ -320,10 +320,10 @@ busy_fr: // // Check if the frame to be restored is busy or unimp. //** NOTE *** Bug fix for errata (0d43b #3) -// If the frame is unimp, we must create a busy frame to +// If the frame is unimp, we must create a busy frame to // fix the bug with the nmnexc bits in cases in which they // are set by a previous instruction and not cleared by -// the save. The frame will be unimp only if the final +// the save. The frame will be unimp only if the final // instruction in an emulation routine caused the exception // by doing an fmove <ea>,fp0. The exception operand, in // internal format, is in fptemp. @@ -364,7 +364,7 @@ loop2: bfins %d0,NMCEXC(%a1){#4:#4} //and insert them in nmcexc movel USER_FPSR(%a6),FPSR_SHADOW(%a1) //set exc bits orl #sx_mask,E_BYTE(%a1) - + do_restore: moveml USER_DA(%a6),%d0-%d1/%a0-%a1 fmovemx USER_FP0(%a6),%fp0-%fp3 @@ -376,10 +376,10 @@ do_restore: cont: unlk %a6 // -// If trace mode enabled, then go to trace handler. This handler -// cannot have any fp instructions. If there are fp inst's and an -// exception has been restored into the machine then the exception -// will occur upon execution of the fp inst. This is not desirable +// If trace mode enabled, then go to trace handler. This handler +// cannot have any fp instructions. If there are fp inst's and an +// exception has been restored into the machine then the exception +// will occur upon execution of the fp inst. This is not desirable // in the kernel (supervisor mode). See MC68040 manual Section 9.3.8. // finish_up: @@ -438,12 +438,12 @@ loop40: clrl -(%sp) movel USER_D1(%a6),%d1 // restore d1 movel #0x40280000,-(%sp) frestore (%sp)+ - unlk %a5 + unlk %a5 rts frame_41: tstb 1(%sp) // check to see if idle - bne notidle + bne notidle idle41: clrl (%sp) // get rid of old fsave frame movel %d1,USER_D1(%a6) // save d1 @@ -453,18 +453,18 @@ loop41: clrl -(%sp) movel USER_D1(%a6),%d1 // restore d1 movel #0x41300000,-(%sp) frestore (%sp)+ - unlk %a5 + unlk %a5 rts notidle: - bclrb #etemp15_bit,-40(%a5) + bclrb #etemp15_bit,-40(%a5) frestore (%sp)+ - unlk %a5 + unlk %a5 rts nofix: frestore (%sp)+ - unlk %a5 + unlk %a5 rts |end diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/get_op.S b/c/src/lib/libcpu/m68k/m68040/fpsp/get_op.S index 5f4921cf4b..85d742b13a 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/get_op.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/get_op.S @@ -18,7 +18,7 @@ // // - For unnormalized numbers (opclass 0, 2, or 3) the // number(s) is normalized and the operand type tag is updated. -// +// // - For a packed number (opclass 2) the number is unpacked and the // operand type tag is updated. // @@ -43,7 +43,7 @@ // the '040. The '040 then re-executes the fadd.x fpm,fpn with // a normalized number in the source and the instruction is // successful. -// +// // Next consider if in the process of normalizing the un- // normalized number it becomes a denormalized number. The // routine which converts the unnorm to a norm (called mk_norm) @@ -56,8 +56,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. GET_OP: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -196,7 +196,7 @@ uns_notpacked: uni_getop: bfextu CMDREG1B(%a6){#0:#6},%d0 //get opclass and src fields - cmpil #0x17,%d0 //if op class and size fields are $17, + cmpil #0x17,%d0 //if op class and size fields are $17, // ;it is FMOVECR; if not, continue // // If the instruction is fmovecr, exit get_op. It is handled @@ -228,21 +228,21 @@ dst_ex_dnrm: movew FPTEMP_EX(%a6),%d0 //get destination exponent andiw #0x7fff,%d0 //mask sign, check if exp = 0000 beqs src_op_ck //if denorm then check source op. -// ;denorms are taken care of in res_func +// ;denorms are taken care of in res_func // ;(unsupp) or do_func (unimp) // ;else unnorm fall through leal FPTEMP(%a6),%a0 //point a0 to dop - used in mk_norm bsr mk_norm //go normalize - mk_norm returns: -// ;L_SCR1{7:5} = operand tag +// ;L_SCR1{7:5} = operand tag // ; (000 = norm, 100 = denorm) -// ;L_SCR1{4} = fpte15 or ete15 +// ;L_SCR1{4} = fpte15 or ete15 // ; 0 = exp > $3fff // ; 1 = exp <= $3fff -// ;and puts the normalized num back +// ;and puts the normalized num back // ;on the fsave stack // - moveb L_SCR1(%a6),DTAG(%a6) //write the new tag & fpte15 -// ;to the fsave stack and fall + moveb L_SCR1(%a6),DTAG(%a6) //write the new tag & fpte15 +// ;to the fsave stack and fall // ;through to check source operand // src_op_ck: @@ -257,19 +257,19 @@ src_op_ck: src_ex_dnrm: movew ETEMP_EX(%a6),%d0 //get source exponent andiw #0x7fff,%d0 //mask sign, check if exp = 0000 - beq end_getop //if denorm then exit, denorms are + beq end_getop //if denorm then exit, denorms are // ;handled in do_func leal ETEMP(%a6),%a0 //point a0 to sop - used in mk_norm bsr mk_norm //go normalize - mk_norm returns: -// ;L_SCR1{7:5} = operand tag +// ;L_SCR1{7:5} = operand tag // ; (000 = norm, 100 = denorm) -// ;L_SCR1{4} = fpte15 or ete15 +// ;L_SCR1{4} = fpte15 or ete15 // ; 0 = exp > $3fff // ; 1 = exp <= $3fff -// ;and puts the normalized num back +// ;and puts the normalized num back // ;on the fsave stack // - moveb L_SCR1(%a6),STAG(%a6) //write the new tag & ete15 + moveb L_SCR1(%a6),STAG(%a6) //write the new tag & ete15 rts //end_getop // @@ -287,7 +287,7 @@ is_double: movew #0x3c01,%d1 //write the bias for a dbl denorm common: btstb #sign_bit,ETEMP_EX(%a6) //grab sign bit of mantissa - beqs pos + beqs pos bset #15,%d1 //set sign bit because it is negative pos: movew %d1,ETEMP_EX(%a6) @@ -299,7 +299,7 @@ pos: movew %d1,CMDREG1B(%a6) //write back to the command word in stack // ;this is needed to fix unsupp data stack leal ETEMP(%a6),%a0 //point a0 to sop - + bsr mk_norm //convert sgl/dbl denorm to norm moveb L_SCR1(%a6),STAG(%a6) //put tag into source tag reg - d0 rts //end_getop @@ -308,7 +308,7 @@ pos: // instruction is dyadic or monadic is still unknown // pack_source: - movel FPTEMP_LO(%a6),ETEMP(%a6) //write ms part of packed + movel FPTEMP_LO(%a6),ETEMP(%a6) //write ms part of packed // ;number to etemp slot bsr chk_dy_mo //set dyadic/monadic flag bsr unpack @@ -327,7 +327,7 @@ pack_dya: btstb #7,DTAG(%a6) //check dest tag for unnorm or denorm bne dst_ex_dnrm //else, handle the unnorm or ext denorm // -// Dest is not denormalized. Check for norm, and set fpte15 +// Dest is not denormalized. Check for norm, and set fpte15 // accordingly. // moveb DTAG(%a6),%d0 @@ -359,7 +359,7 @@ end_getop: // unsupported data type exception. Set if dyadic. // chk_dy_mo: - movew CMDREG1B(%a6),%d0 + movew CMDREG1B(%a6),%d0 btstl #5,%d0 //testing extension command word beqs set_mon //if bit 5 = 0 then monadic btstl #4,%d0 //know that bit 5 = 1 @@ -408,7 +408,7 @@ set_mon: // L_SCR1{7:5} = operand tag (000 = norm, 100 = denorm) // L_SCR1{4} = fpte15 or ete15 (0 = exp > $3fff, 1 = exp <=$3fff) // the normalized operand is placed back on the fsave stack -mk_norm: +mk_norm: clrl L_SCR1(%a6) bclrb #sign_bit,LOCAL_EX(%a0) sne LOCAL_SGN(%a0) //transform into internal extended format @@ -428,11 +428,11 @@ reload: cmpw #0x3fff,LOCAL_EX(%a0) //if exp > $3fff bgts end_mk // fpte15/ete15 already set to 0 bsetb #4,L_SCR1(%a6) //else set fpte15/ete15 to 1 -// ;calling routine actually sets the -// ;value on the stack (along with the -// ;tag), since this routine doesn't +// ;calling routine actually sets the +// ;value on the stack (along with the +// ;tag), since this routine doesn't // ;know if it should set ete15 or fpte15 -// ;ie, it doesn't know if this is the +// ;ie, it doesn't know if this is the // ;src op or dest op. end_mk: bfclr LOCAL_SGN(%a0){#0:#8} @@ -457,7 +457,7 @@ no_unfl: // uns_opx: bsr nrm_zero //normalize the number - btstb #7,LOCAL_HI(%a0) //check if integer bit (j-bit) is set + btstb #7,LOCAL_HI(%a0) //check if integer bit (j-bit) is set beqs uns_den //if clear then now have a denorm uns_nrm: orb #norm_tag,L_SCR1(%a6) //set tag to norm @@ -470,7 +470,7 @@ uns_den: // uni_inst: bsr nrm_zero - btstb #7,LOCAL_HI(%a0) //check if integer bit (j-bit) is set + btstb #7,LOCAL_HI(%a0) //check if integer bit (j-bit) is set beqs uni_den //if clear then now have a denorm uni_nrm: orb #norm_tag,L_SCR1(%a6) //set tag to norm @@ -482,9 +482,9 @@ uni_den: // // Decimal to binary conversion // -// Special cases of inf and NaNs are completed outside of decbin. +// Special cases of inf and NaNs are completed outside of decbin. // If the input is an snan, the snan bit is not set. -// +// // input: // ETEMP(a6) - points to packed decimal string in memory // output: @@ -612,16 +612,16 @@ mnot_spec: finish: movew CMDREG1B(%a6),%d0 //get the command word - andw #0xfbff,%d0 //change the source specifier field to + andw #0xfbff,%d0 //change the source specifier field to // ;extended (was packed). movew %d0,CMDREG1B(%a6) //write command word back to fsave stack -// ;we need to do this so the 040 will -// ;re-execute the inst. without taking +// ;we need to do this so the 040 will +// ;re-execute the inst. without taking // ;another packed trap. fix_stag: -//Converted result is now in etemp on fsave stack, now set the source -//tag (stag) +//Converted result is now in etemp on fsave stack, now set the source +//tag (stag) // if (ete =$7fff) then INF or NAN // if (etemp = $x.0----0) then // stag = INF @@ -634,7 +634,7 @@ fix_stag: // stag = NORM // // Note also that the etemp_15 bit (just right of the stag) must -// be set accordingly. +// be set accordingly. // movew ETEMP_EX(%a6),%d1 andiw #0x7fff,%d1 //strip sign @@ -653,7 +653,7 @@ is_nan: movel #0x60,%d0 rts z_or_nrm: - tstw %d1 + tstw %d1 bnes is_nrm is_zro: // For a zero, set etemp_15 @@ -672,7 +672,7 @@ end_is_nrm: movel #0,%d0 end_fix: rts - + end_get: rts |end diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/kernel_ex.S b/c/src/lib/libcpu/m68k/m68040/fpsp/kernel_ex.S index c4fd6812af..8497bc0b1e 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/kernel_ex.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/kernel_ex.S @@ -1,21 +1,21 @@ // // $Id$ // -// kernel_ex.sa 3.3 12/19/90 +// kernel_ex.sa 3.3 12/19/90 // -// This file contains routines to force exception status in the +// This file contains routines to force exception status in the // fpu for exceptional cases detected or reported within the // transcendental functions. Typically, the t_xx routine will // set the appropriate bits in the USER_FPSR word on the stack. // The bits are tested in gen_except.sa to determine if an exceptional -// situation needs to be created on return from the FPSP. +// situation needs to be created on return from the FPSP. // // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. KERNEL_EX: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -51,7 +51,7 @@ huge: .long 0x7ffe0000,0xffffffff,0xffffffff // // if dz trap disabled // store properly signed inf (use sign of etemp) into fp0 -// set FPSR exception status dz bit, condition code +// set FPSR exception status dz bit, condition code // inf bit, and accrued dz bit // return // frestore the frame into the machine (done by unimp_hd) @@ -63,7 +63,7 @@ huge: .long 0x7ffe0000,0xffffffff,0xffffffff // frestore the frame into the machine (done by unimp_hd) // // t_dz2 is used by monadic functions such as flogn (from do_func). -// t_dz is used by monadic functions such as satanh (from the +// t_dz is used by monadic functions such as satanh (from the // transcendental function). // t_dz2: @@ -106,10 +106,10 @@ dz_ena_end: // OPERR exception // // if (operr trap disabled) -// set FPSR exception status operr bit, condition code +// set FPSR exception status operr bit, condition code // nan bit; Store default NAN into fp0 // frestore the frame into the machine (done by unimp_hd) -// +// // else (operr trap enabled) // set FPSR exception status operr bit, accrued operr bit // set flag to disable sto_res from corrupting fp register @@ -161,13 +161,13 @@ unfl_ena: unfl_dis: bfextu FPCR_MODE(%a6){#0:#2},%d0 //get round precision - + bclrb #sign_bit,LOCAL_EX(%a0) sne LOCAL_SGN(%a0) //convert to internal ext format bsr unf_sub //returns IEEE result at a0 // ;and sets FPSR_CC accordingly - + bfclr LOCAL_SGN(%a0){#0:#8} //convert back to IEEE ext format beqs unfl_fin @@ -177,7 +177,7 @@ unfl_dis: unfl_fin: fmovemx (%a0),%fp0-%fp0 //store result in fp0 rts - + // // t_ovfl2 --- OVFL exception (without inex2 returned) @@ -282,7 +282,7 @@ no_uacc1: // DST_NAN // // Determine if the destination nan is signalling or non-signalling, -// and set the FPSR bits accordingly. See the MC68040 User's Manual +// and set the FPSR bits accordingly. See the MC68040 User's Manual // section 3.2.2.5 NOT-A-NUMBERS. // dst_nan: @@ -290,7 +290,7 @@ dst_nan: beqs dst_pos //if clr, it was positive bsetb #neg_bit,FPSR_CC(%a6) //set N bit dst_pos: - btstb #signan_bit,FPTEMP_HI(%a6) //check if signalling + btstb #signan_bit,FPTEMP_HI(%a6) //check if signalling beqs dst_snan //branch if signalling fmovel %d1,%fpcr //restore user's rmode/prec @@ -302,14 +302,14 @@ dst_pos: andib #0xe0,%d0 cmpib #0x60,%d0 bnes no_snan - btstb #signan_bit,ETEMP_HI(%a6) //check if signalling + btstb #signan_bit,ETEMP_HI(%a6) //check if signalling bnes no_snan orl #snaniop_mask,USER_FPSR(%a6) //set NAN, SNAN, AIOP no_snan: - rts + rts dst_snan: - btstb #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled + btstb #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled beqs dst_dis //branch if disabled orb #nan_tag,DTAG(%a6) //set up dtag for nan @@ -318,9 +318,9 @@ dst_snan: rts dst_dis: - bsetb #signan_bit,FPTEMP_HI(%a6) //set SNAN bit in sop + bsetb #signan_bit,FPTEMP_HI(%a6) //set SNAN bit in sop fmovel %d1,%fpcr //restore user's rmode/prec - fmovex FPTEMP(%a6),%fp0 //load non-sign. nan + fmovex FPTEMP(%a6),%fp0 //load non-sign. nan orl #snaniop_mask,USER_FPSR(%a6) //set NAN, SNAN, AIOP rts @@ -328,7 +328,7 @@ dst_dis: // SRC_NAN // // Determine if the source nan is signalling or non-signalling, -// and set the FPSR bits accordingly. See the MC68040 User's Manual +// and set the FPSR bits accordingly. See the MC68040 User's Manual // section 3.2.2.5 NOT-A-NUMBERS. // src_nan: @@ -336,16 +336,16 @@ src_nan: beqs src_pos //if clr, it was positive bsetb #neg_bit,FPSR_CC(%a6) //set N bit src_pos: - btstb #signan_bit,ETEMP_HI(%a6) //check if signalling + btstb #signan_bit,ETEMP_HI(%a6) //check if signalling beqs src_snan //branch if signalling fmovel %d1,%fpcr //restore user's rmode/prec fmovex ETEMP(%a6),%fp0 //return the non-signalling nan - rts + rts src_snan: - btstb #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled + btstb #snan_bit,FPCR_ENABLE(%a6) //check if trap enabled beqs src_dis //branch if disabled - bsetb #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop + bsetb #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop orb #norm_tag,DTAG(%a6) //set up dtag for norm orb #nan_tag,STAG(%a6) //set up stag for nan st STORE_FLG(%a6) //do not store a result @@ -353,9 +353,9 @@ src_snan: rts src_dis: - bsetb #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop + bsetb #signan_bit,ETEMP_HI(%a6) //set SNAN bit in sop fmovel %d1,%fpcr //restore user's rmode/prec - fmovex ETEMP(%a6),%fp0 //load non-sign. nan + fmovex ETEMP(%a6),%fp0 //load non-sign. nan orl #snaniop_mask,USER_FPSR(%a6) //set NAN, SNAN, AIOP rts @@ -369,7 +369,7 @@ t_extdnrm: bras xdnrm_con // // Entry point for scale with extended denorm. The function does -// not set inex2, aunfl, or ainex. +// not set inex2, aunfl, or ainex. // t_resdnrm: orl #unfl_mask,USER_FPSR(%a6) @@ -404,7 +404,7 @@ xdnrm_dn: bfclr LOCAL_SGN(%a0){#0:#8} //change back to IEEE ext format beqs xdep bsetb #sign_bit,LOCAL_EX(%a0) -xdep: +xdep: bfclr STAG(%a6){#5:#3} //clear wbtm66,wbtm1,wbtm0 bsetb #wbtemp15_bit,WB_BYTE(%a6) //set wbtemp15 bclrb #sticky_bit,STICKY(%a6) //clear sticky bit @@ -441,7 +441,7 @@ xdnrm_store: // .global t_avoid_unsupp t_avoid_unsupp: - link %a2,#-LOCAL_SIZE //so that a2 fpsp.h negative + link %a2,#-LOCAL_SIZE //so that a2 fpsp.h negative // ;offsets may be used fsave -(%a7) tstb 1(%a7) //check if idle, exit if so diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/res_func.S b/c/src/lib/libcpu/m68k/m68040/fpsp/res_func.S index 2f6b22870a..690315eeca 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/res_func.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/res_func.S @@ -10,7 +10,7 @@ // (Exception vector 55). // // For packed move out (fmove.p fpm,<ea>) the operation is -// completed here; data is packed and moved to user memory. +// completed here; data is packed and moved to user memory. // The stack is restored to the 040 only in the case of a // reportable exception in the conversion. // @@ -18,8 +18,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. RES_FUNC: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -102,7 +102,7 @@ monadic: movew CMDREG1B(%a6),%d0 //get command register andil #0x7f,%d0 //strip to only command word // -// At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and +// At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and // fdsqrt are possible. // For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize) // For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize) @@ -145,7 +145,7 @@ cu_ntpo: rts cu_ntn: orl #nan_mask,USER_FPSR(%a6) - movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for // ;snan handler rts @@ -208,7 +208,7 @@ cu_nmnr: cu_nmrd: movel #2,%d0 //set up the size for denorm movew LOCAL_EX(%a0),%d1 //compare exponent to double threshold - andw #0x7fff,%d1 + andw #0x7fff,%d1 cmpw #0x3c01,%d1 bls cu_nunfl bfextu FPCR_MODE(%a6){#2:#2},%d1 //get rmode @@ -361,7 +361,7 @@ cu_wreon: // ;write the new tag & ete15 to the fstack mon_dnrm: // -// At this point, check for the cases in which normalizing the +// At this point, check for the cases in which normalizing the // denorm produces incorrect results. // tstb DY_MO_FLG(%a6) //all cases of dyadic instructions would @@ -376,7 +376,7 @@ mon_dnrm: movew CMDREG1B(%a6),%d0 //get command register andil #0x7f,%d0 //strip to only command word // -// At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and +// At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and // fdsqrt are possible. // For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize) // For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize) @@ -384,12 +384,12 @@ mon_dnrm: btstl #0,%d0 bnes nrm_src //weed out fsqrt instructions st CU_ONLY(%a6) //set cu-only inst flag - bra cu_dnrm //fmove, fabs, fneg, ftst + bra cu_dnrm //fmove, fabs, fneg, ftst // ;cases go to cu_dnrm nrm_src: bclrb #sign_bit,LOCAL_EX(%a0) sne LOCAL_SGN(%a0) - bsr nrm_set //normalize number (exponent will go + bsr nrm_set //normalize number (exponent will go // ; negative) bclrb #sign_bit,LOCAL_EX(%a0) //get rid of false sign @@ -415,7 +415,7 @@ fix_stk: // // cu_dnrm handles all cu-only instructions (fmove, fabs, fneg, and -// ftst) completely in software without an frestore to the 040. +// ftst) completely in software without an frestore to the 040. // cu_dnrm: st CU_ONLY(%a6) @@ -448,7 +448,7 @@ cu_dtpo: rts cu_dtn: orl #nan_mask,USER_FPSR(%a6) - movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for // ;snan handler rts cu_dtcz: @@ -527,7 +527,7 @@ cu_dmsn: bra cu_sndr //load single neg zero w/lsb // // The precision is extended, so the result in etemp is correct. -// Simply set unfl (not inex2 or aunfl) and write the result to +// Simply set unfl (not inex2 or aunfl) and write the result to // the correct fp register. cu_wrexd: orl #unfl_mask,USER_FPSR(%a6) @@ -599,7 +599,7 @@ cu_sndr: orl #neg_mask,USER_FPSR(%a6) orl #unfinx_mask,USER_FPSR(%a6) bra wr_etemp - + // // This code checks for 16-bit overflow conditions on dyadic // operations which are not restorable into the floating-point @@ -615,7 +615,7 @@ cu_sndr: // $ff for both ops denormalized // // The wrap-around condition occurs for add, sub, div, and cmp -// when +// when // // abs(dest_exp - src_exp) >= $8000 // @@ -629,7 +629,7 @@ cu_sndr: // for this condition. The restore flag (RES_FLG) is left clear. // No frestore is done unless an exception is to be reported. // -// For fadd: +// For fadd: // if(sign_of(dest) != sign_of(src)) // replace exponent of src with $3fff (keep sign) // use fpu to perform dest+new_src (user's rmode and X) @@ -691,10 +691,10 @@ ck_wrap: cmpiw #cmpcode,%d0 beq wrap_cmp // -// Inst is fdiv. +// Inst is fdiv. // wrap_div: - cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, + cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, beq fix_stk //restore to fpu // // One of the ops is denormalized. Test for wrap condition @@ -724,7 +724,7 @@ ckinf_ns: bra ck_in_com ckinf_nd: moveb DTAG(%a6),%d0 //check destination tag for inf or nan -ck_in_com: +ck_in_com: andib #0x60,%d0 //isolate tag bits cmpb #0x40,%d0 //is it inf? beq nan_or_inf //not wrap case @@ -757,7 +757,7 @@ div_srcd: beqs force_ovf st WBTEMP_SGN(%a6) // -// This code handles the case of the instruction resulting in +// This code handles the case of the instruction resulting in // an overflow condition. // force_ovf: @@ -779,7 +779,7 @@ frcovf_fpcr: bfextu FPCR_MODE(%a6){#0:#2},%d0 //inst not forced - use fpcr prec frcovf_rnd: -// The 881/882 does not set inex2 for the following case, so the +// The 881/882 does not set inex2 for the following case, so the // line is commented out to be compatible with 881/882 // tst.b %d0 // beq.b frcovf_x @@ -787,7 +787,7 @@ frcovf_rnd: //frcovf_x: bsrl ovf_res //get correct result based on -// ;round precision/mode. This +// ;round precision/mode. This // ;sets FPSR_CC correctly // ;returns in external format bfclr WBTEMP_SGN(%a6){#0:#8} @@ -798,7 +798,7 @@ frcovf_rnd: // Inst is fadd. // wrap_add: - cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, + cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, beq fix_stk //restore to fpu // // One of the ops is denormalized. Test for wrap condition @@ -966,14 +966,14 @@ add_ckovf: // and aovfl, and clr the mantissa (incorrectly set by the // round routine.) // - orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) + orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) clrl 4(%a0) bra frcfpnr // // Inst is fsub. // wrap_sub: - cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, + cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, beq fix_stk //restore to fpu // // One of the ops is denormalized. Test for wrap condition @@ -1147,14 +1147,14 @@ sub_ckovf: // and aovfl, and clr the mantissa (incorrectly set by the // round routine.) // - orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) + orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6) clrl 4(%a0) bra frcfpnr // // Inst is fcmp. // wrap_cmp: - cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, + cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, beq fix_stk //restore to fpu // // One of the ops is denormalized. Test for wrap condition @@ -1192,7 +1192,7 @@ cmp_setn: // Inst is fmul. // wrap_mul: - cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, + cmpb #0xff,DNRM_FLG(%a6) //if both ops denorm, beq force_unf //force an underflow (really!) // // One of the ops is denormalized. Test for wrap condition @@ -1215,9 +1215,9 @@ mul_srcd: bfexts ETEMP_EX(%a6){#1:#15},%d1 //get src exp (always neg) addl %d1,%d0 //subtract src from dest bgt fix_stk - + // -// This code handles the case of the instruction resulting in +// This code handles the case of the instruction resulting in // an underflow condition. // force_unf: @@ -1247,7 +1247,7 @@ frcunf_fpcr: bfextu FPCR_MODE(%a6){#0:#2},%d0 //inst not forced - use fpcr prec frcunf_rnd: bsrl unf_sub //get correct result based on -// ;round precision/mode. This +// ;round precision/mode. This // ;sets FPSR_CC correctly bfclr WBTEMP_SGN(%a6){#0:#8} //convert back to IEEE ext format beqs frcfpn @@ -1279,14 +1279,14 @@ frcfpn_rnd: bclrb #sign_bit,WBTEMP_EX(%a6) sne WBTEMP_SGN(%a6) bsrl ovf_res //get correct result based on -// ;round precision/mode. This +// ;round precision/mode. This // ;sets FPSR_CC correctly bfclr WBTEMP_SGN(%a6){#0:#8} //convert back to IEEE ext format beqs frcfpn_clr bsetb #sign_bit,WBTEMP_EX(%a6) frcfpn_clr: orl #ovfinx_mask,USER_FPSR(%a6) -// +// // Perform the write. // frcfpn: @@ -1303,9 +1303,9 @@ frc0123: cmpib #0,%d0 beqs frc0_dst cmpib #1,%d0 - beqs frc1_dst + beqs frc1_dst cmpib #2,%d0 - beqs frc2_dst + beqs frc2_dst frc3_dst: movel WBTEMP_EX(%a6),USER_FP3(%a6) movel WBTEMP_HI(%a6),USER_FP3+4(%a6) @@ -1339,7 +1339,7 @@ wr_etemp: beqs fmoveinc //enabled, force restore btstb #snan_bit,FPCR_ENABLE(%a6) //and don't overwrite beqs fmoveinc //the dest - movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for // ;snan handler tstb ETEMP(%a6) //check for negative blts snan_neg @@ -1363,7 +1363,7 @@ fminc_cnan: cmpib #0x60,%d0 //check if stag is NaN bnes fminc_czero orl #nan_mask,USER_FPSR(%a6) //if nan, nothing yet has set NaN - movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for + movel ETEMP_EX(%a6),FPTEMP_EX(%a6) //set up fptemp sign for // ;snan handler tstw LOCAL_EX(%a0) //check sign bges fminc_con @@ -1391,9 +1391,9 @@ fp0123: cmpib #0,%d0 beqs fp0_dst cmpib #1,%d0 - beqs fp1_dst + beqs fp1_dst cmpib #2,%d0 - beqs fp2_dst + beqs fp2_dst fp3_dst: movel ETEMP_EX(%a6),USER_FP3(%a6) movel ETEMP_HI(%a6),USER_FP3+4(%a6) @@ -1423,7 +1423,7 @@ opclass3: beq pack_out //else it is norm or denorm bra mv_out - + // // MOVE OUT // @@ -1444,7 +1444,7 @@ mv_out: jmp (%a0) // -// This exit is for move-out to memory. The aunfl bit is +// This exit is for move-out to memory. The aunfl bit is // set if the result is inex and unfl is signalled. // mvout_end: @@ -1468,7 +1468,7 @@ no_aufl: mvout_con: rts // -// This exit is for move-out to int register. The aunfl bit is +// This exit is for move-out to int register. The aunfl bit is // not set in any case for this move. // mvouti_end: @@ -1498,7 +1498,7 @@ li: fmovemx ETEMP(%a6),%fp0-%fp0 fcmpd #0x41dfffffffc00000,%fp0 // 41dfffffffc00000 in dbl prec = 401d0000fffffffe00000000 in ext prec - fbge lo_plrg + fbge lo_plrg fcmpd #0xc1e0000000000000,%fp0 // c1e0000000000000 in dbl prec = c01e00008000000000000000 in ext prec fble lo_nlrg @@ -1543,7 +1543,7 @@ wi: fmovemx ETEMP(%a6),%fp0-%fp0 fcmps #0x46fffe00,%fp0 // 46fffe00 in sgl prec = 400d0000fffe000000000000 in ext prec - fbge wo_plrg + fbge wo_plrg fcmps #0xc7000000,%fp0 // c7000000 in sgl prec = c00e00008000000000000000 in ext prec fble wo_nlrg @@ -1588,7 +1588,7 @@ bi: fmovemx ETEMP(%a6),%fp0-%fp0 fcmps #0x42fe0000,%fp0 // 42fe0000 in sgl prec = 40050000fe00000000000000 in ext prec - fbge by_plrg + fbge by_plrg fcmps #0xc3000000,%fp0 // c3000000 in sgl prec = c00600008000000000000000 in ext prec fble by_nlrg @@ -1631,7 +1631,7 @@ by_nlrg: int_dnrm: movel #0,L_SCR1(%a6) // initialize result to 0 bfextu FPCR_MODE(%a6){#2:#2},%d1 // d1 is the rounding mode - cmpb #2,%d1 + cmpb #2,%d1 bmis int_inx // if RN or RZ, done bnes int_rp // if RP, continue below tstw ETEMP(%a6) // RM: store -1 in L_SCR1 if src is negative @@ -1644,7 +1644,7 @@ int_rp: bmis int_inx // otherwise, result is 0 lea L_SCR1(%a6),%a1 // a1 is address of L_SCR1 addal %d0,%a1 // offset by destination width -1 - subal #1,%a1 + subal #1,%a1 bsetb #0,(%a1) // set low bit at a1 address int_inx: oril #inx2a_mask,USER_FPSR(%a6) @@ -1658,10 +1658,10 @@ int_operr: oril #opaop_mask,USER_FPSR(%a6) // ;fall through to perform int_wrt -int_wrt: +int_wrt: movel EXC_EA(%a6),%a1 //load destination address tstl %a1 //check to see if it is a dest register - beqs wrt_dn //write data register + beqs wrt_dn //write data register lea L_SCR1(%a6),%a0 //point to supervisor source address bsrl mem_write bra mvouti_end @@ -1682,7 +1682,7 @@ sz_long: sz_con: movel %d0,%d1 //reg_dest expects size:reg in d1 bsrl reg_dest //load proper data register - bra mvouti_end + bra mvouti_end xp: lea ETEMP(%a6),%a0 bclrb #sign_bit,LOCAL_EX(%a0) @@ -1720,7 +1720,7 @@ dp: blt dp_under cmpw 2(%a1),%d0 bgt dp_over - + movel #2,%d0 //set destination format to double // ;fall through to do_fp // @@ -1728,10 +1728,10 @@ do_fp: bfextu FPCR_MODE(%a6){#2:#2},%d1 //rnd mode in d1 swap %d0 //rnd prec in upper word addl %d0,%d1 //d1 has PREC/MODE info - - clrl %d0 //clear g,r,s - bsrl round //round + clrl %d0 //clear g,r,s + + bsrl round //round movel %a0,%a1 movel EXC_EA(%a6),%a0 @@ -1766,12 +1766,12 @@ xdnrm: bsrl dest_ext //store to memory bsetb #unfl_bit,FPSR_EXCEPT(%a6) bra mvout_end - + sp_under: bsetb #etemp15_bit,STAG(%a6) cmpw 4(%a1),%d0 - blts sp_catas //catastrophic underflow case + blts sp_catas //catastrophic underflow case movel #1,%d0 //load in round precision movel #sgl_thresh,%d1 //load in single denorm threshold @@ -1786,9 +1786,9 @@ dp_under: cmpw 4(%a1),%d0 blts dp_catas //catastrophic underflow case - + movel #dbl_thresh,%d1 //load in double precision threshold - movel #2,%d0 + movel #2,%d0 bsrl dpspdnrm //expects d1 to have proper // ;denorm threshold // ;expects d0 to have round precision @@ -1815,11 +1815,11 @@ sp_catas: movel %a0,%a1 //a1 has the operand input movel EXC_EA(%a6),%a0 //a0 has the destination pointer - + bsrl dest_sgl //store the result oril #unfinx_mask,USER_FPSR(%a6) bra mvout_end - + dp_catas: // Temp fix for z bit set in unf_sub movel USER_FPSR(%a6),-(%a7) @@ -1830,12 +1830,12 @@ dp_catas: movel (%a7)+,USER_FPSR(%a6) movel #1,%d0 - subw %d0,LOCAL_EX(%a0) //account for difference between + subw %d0,LOCAL_EX(%a0) //account for difference between // ;denorm/norm bias movel %a0,%a1 //a1 has the operand input movel EXC_EA(%a6),%a0 //a0 has the destination pointer - + bsrl dest_dbl //store the result oril #unfinx_mask,USER_FPSR(%a6) bra mvout_end @@ -1907,7 +1907,7 @@ dpspdnrm: bfextu FPCR_MODE(%a6){#2:#2},%d1 //get rounding mode swap %d1 - movew 2(%a7),%d1 //set rounding precision + movew 2(%a7),%d1 //set rounding precision swap %d1 //at this point d1 has PREC/MODE info bsrl round //round result, sets the inex bit in // ;USER_FPSR if needed @@ -1967,7 +1967,7 @@ p_write: moveb #0,CU_SAVEPC(%a6) //set the cu save pc to all 0's // -// Also note that the dtag must be set to norm here - this is because +// Also note that the dtag must be set to norm here - this is because // the 040 uses the dtag to execute the correct microcode. // bfclr DTAG(%a6){#0:#3} //set dtag to norm diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/round.S b/c/src/lib/libcpu/m68k/m68040/fpsp/round.S index 3acce6e285..00dbb6ba62 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/round.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/round.S @@ -10,8 +10,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //ROUND idnt 2,1 | Motorola 040 Floating Point Software Package @@ -23,7 +23,7 @@ // // round --- round result according to precision/mode // -// a0 points to the input operand in the internal extended format +// a0 points to the input operand in the internal extended format // d1(high word) contains rounding precision: // ext = $0000xxxx // sgl = $0001xxxx @@ -46,15 +46,15 @@ .global round round: -// If g=r=s=0 then result is exact and round is done, else set -// the inex flag in status reg and continue. +// If g=r=s=0 then result is exact and round is done, else set +// the inex flag in status reg and continue. // - bsrs ext_grs //this subroutine looks at the -// :rounding precision and sets + bsrs ext_grs //this subroutine looks at the +// :rounding precision and sets // ;the appropriate g-r-s bits. tstl %d0 //if grs are zero, go force bne rnd_cont //lower bits to zero for size - + swap %d1 //set up d1.w for round prec. bra truncate @@ -95,7 +95,7 @@ rnd_plus: // rnd_mnus: swap %d1 //set up d1 for round prec. - tstb LOCAL_SGN(%a0) //check for sign + tstb LOCAL_SGN(%a0) //check for sign bpl truncate //if negative then truncate movel #0xffffffff,%d0 //force g,r,s to be all f's lea add_to_l,%a1 @@ -131,7 +131,7 @@ rnd_near: // // The ext_grs extract the guard/round/sticky bits according to the // selected rounding precision. It is called by the round subroutine -// only. All registers except d0 are kept intact. d0 becomes an +// only. All registers except d0 are kept intact. d0 becomes an // updated guard,round,sticky in d0{31:29} // // Notes: the ext_grs uses the round PREC, and therefore has to swap d1 @@ -142,7 +142,7 @@ ext_grs: cmpiw #0,%d1 bnes sgl_or_dbl bras end_ext_grs - + sgl_or_dbl: moveml %d2/%d3,-(%a7) //make some temp registers cmpiw #1,%d1 @@ -152,19 +152,19 @@ grs_sgl: movel #30,%d2 //of the sgl prec. limits lsll %d2,%d3 //shift g-r bits to MSB of d3 movel LOCAL_HI(%a0),%d2 //get word 2 for s-bit test - andil #0x0000003f,%d2 //s bit is the or of all other + andil #0x0000003f,%d2 //s bit is the or of all other bnes st_stky //bits to the right of g-r tstl LOCAL_LO(%a0) //test lower mantissa bnes st_stky //if any are set, set sticky tstl %d0 //test original g,r,s bnes st_stky //if any are set, set sticky bras end_sd //if words 3 and 4 are clr, exit -grs_dbl: +grs_dbl: bfextu LOCAL_LO(%a0){#21:#2},%d3 //dbl-prec. g-r are 2 bits right movel #30,%d2 //of the dbl prec. limits lsll %d2,%d3 //shift g-r bits to the MSB of d3 movel LOCAL_LO(%a0),%d2 //get lower mantissa for s-bit test - andil #0x000001ff,%d2 //s bit is the or-ing of all + andil #0x000001ff,%d2 //s bit is the or-ing of all bnes st_stky //other bits to the right of g-r tstl %d0 //test word original g,r,s bnes st_stky //if any are set, set sticky @@ -271,20 +271,20 @@ end_rnd: // // NORMALIZE // -// These routines (nrm_zero & nrm_set) normalize the unnorm. This -// is done by shifting the mantissa left while decrementing the +// These routines (nrm_zero & nrm_set) normalize the unnorm. This +// is done by shifting the mantissa left while decrementing the // exponent. // -// NRM_SET shifts and decrements until there is a 1 set in the integer +// NRM_SET shifts and decrements until there is a 1 set in the integer // bit of the mantissa (msb in d1). // -// NRM_ZERO shifts and decrements until there is a 1 set in the integer -// bit of the mantissa (msb in d1) unless this would mean the exponent -// would go less than 0. In that case the number becomes a denorm - the -// exponent (d0) is set to 0 and the mantissa (d1 & d2) is not +// NRM_ZERO shifts and decrements until there is a 1 set in the integer +// bit of the mantissa (msb in d1) unless this would mean the exponent +// would go less than 0. In that case the number becomes a denorm - the +// exponent (d0) is set to 0 and the mantissa (d1 & d2) is not // normalized. // -// Note that both routines have been optimized (for the worst case) and +// Note that both routines have been optimized (for the worst case) and // therefore do not have the easy to follow decrement/shift loop. // // NRM_ZERO @@ -306,34 +306,34 @@ end_rnd: .global nrm_zero nrm_zero: movew LOCAL_EX(%a0),%d0 - cmpw #64,%d0 //see if exp > 64 + cmpw #64,%d0 //see if exp > 64 bmis d0_less - bsr nrm_set //exp > 64 so exp won't exceed 0 + bsr nrm_set //exp > 64 so exp won't exceed 0 rts d0_less: moveml %d2/%d3/%d5/%d6,-(%a7) movel LOCAL_HI(%a0),%d1 movel LOCAL_LO(%a0),%d2 - bfffo %d1{#0:#32},%d3 //get the distance to the first 1 + bfffo %d1{#0:#32},%d3 //get the distance to the first 1 // ;in ms mant beqs ms_clr //branch if no bits were set cmpw %d3,%d0 //of X>Y - bmis greater //then exp will go past 0 (neg) if + bmis greater //then exp will go past 0 (neg) if // ;it is just shifted bsr nrm_set //else exp won't go past 0 moveml (%a7)+,%d2/%d3/%d5/%d6 - rts + rts greater: movel %d2,%d6 //save ls mant in d6 lsll %d0,%d2 //shift ls mant by count lsll %d0,%d1 //shift ms mant by count movel #32,%d5 - subl %d0,%d5 //make op a denorm by shifting bits - lsrl %d5,%d6 //by the number in the exp, then + subl %d0,%d5 //make op a denorm by shifting bits + lsrl %d5,%d6 //by the number in the exp, then // ;set exp = 0. orl %d6,%d1 //shift the ls mant bits into the ms mant - movel #0,%d0 //same as if decremented exp to 0 + movel #0,%d0 //same as if decremented exp to 0 // ;while shifting movew %d0,LOCAL_EX(%a0) movel %d1,LOCAL_HI(%a0) @@ -382,7 +382,7 @@ nrm_set: rts // -// We get here if ms mant was = 0, and we assume ls mant has bits +// We get here if ms mant was = 0, and we assume ls mant has bits // set (otherwise this would have been tagged a zero not a denorm). // lower: @@ -402,10 +402,10 @@ lower: // // Used by underflow. // -// Input: +// Input: // a0 points to the operand to be denormalized // (in the internal extended format) -// +// // d0: rounding precision // Output: // a0 points to the denormalized result @@ -413,15 +413,15 @@ lower: // // d0 is guard,round,sticky // -// d0 comes into this routine with the rounding precision. It -// is then loaded with the denormalized exponent threshold for the +// d0 comes into this routine with the rounding precision. It +// is then loaded with the denormalized exponent threshold for the // rounding precision. // .global denorm denorm: btstb #6,LOCAL_EX(%a0) //check for exponents between $7fff-$4000 - beqs no_sgn_ext + beqs no_sgn_ext bsetb #7,LOCAL_EX(%a0) //sign extend if it is so no_sgn_ext: @@ -444,7 +444,7 @@ load_dbl: movel %d1,%d0 //copy d1 into d0 subw LOCAL_EX(%a0),%d0 //diff = threshold - exp cmpw #67,%d0 //if diff > 67 (mant + grs bits) - bpls chk_stky //then branch (all bits would be + bpls chk_stky //then branch (all bits would be // ; shifted off in denorm routine) clrl %d0 //else clear the sticky flag bsr dnrm_lp //denormalize the number @@ -457,7 +457,7 @@ load_sgl: movel %d1,%d0 //copy d1 into d0 subw LOCAL_EX(%a0),%d0 //diff = threshold - exp cmpw #67,%d0 //if diff > 67 (mant + grs bits) - bpls chk_stky //then branch (all bits would be + bpls chk_stky //then branch (all bits would be // ; shifted off in denorm routine) clrl %d0 //else clear the sticky flag bsr dnrm_lp //denormalize the number @@ -498,7 +498,7 @@ no_inex: // // The LOCAL_LO and LOCAL_GRS parts of the value are copied to FP_SCR2 // so that bfext can be used to extract the new low part of the mantissa. -// Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there +// Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there // is no LOCAL_GRS scratch word following it on the fsave frame. // .global dnrm_lp @@ -517,8 +517,8 @@ not_E3: movel %d1,%d0 //copy the denorm threshold subw LOCAL_EX(%a0),%d1 //d1 = threshold - uns exponent bles no_lp //d1 <= 0 - cmpw #32,%d1 - blts case_1 //0 = d1 < 32 + cmpw #32,%d1 + blts case_1 //0 = d1 < 32 cmpw #64,%d1 blts case_2 //32 <= d1 < 64 bra case_3 //d1 >= 64 @@ -544,7 +544,7 @@ case_1: movel %d2,LOCAL_HI(%a0) //store new LOCAL_HI movel %d1,LOCAL_LO(%a0) //store new LOCAL_LO clrb %d1 - bftst %d0{#2:#30} + bftst %d0{#2:#30} beqs c1nstky bsetl #rnd_stky_bit,%d0 st %d1 @@ -587,7 +587,7 @@ end_c2: movel FP_SCR2+LOCAL_GRS(%a6),%d2 //restore original g,r,s andil #0xe0000000,%d2 //clear all but G,R,S tstl %d2 //test if original G,R,S are clear - beqs clear_grs + beqs clear_grs orl #0x20000000,%d0 //set sticky bit in d0 clear_grs: andil #0xe0000000,%d0 //get rid of all but G,R,S @@ -623,7 +623,7 @@ sixty_four: bfextu %d0{#2:#30},%d1 andil #0xc0000000,%d0 bras c3com - + sixty_five: movel LOCAL_HI(%a0),%d0 bfextu %d0{#1:#31},%d1 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/rtems_skel.S b/c/src/lib/libcpu/m68k/m68040/fpsp/rtems_skel.S index b047b62f36..e80f544dd4 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/rtems_skel.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/rtems_skel.S @@ -20,20 +20,20 @@ // to handle the exception. // // If the exception was completely handled by the package, then -// the return will be via a 'jmp fpsp_done'. Unless there is +// the return will be via a 'jmp fpsp_done'. Unless there is // OS specific work to be done (such as handling a context switch or // interrupt) the user program can be resumed via 'rte'. // // In the following skeleton code, some typical 'real_xxxx' handling // code is shown. This code may need to be moved to an appropriate // place in the target system, or rewritten. -// +// // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. // $Id$ @@ -68,7 +68,7 @@ SYM(_fpspEntry_dz): // // All inexact exceptions are real, but the 'real' handler // will probably want to clear the pending exception. -// The provided code will clear the E3 exception (if pending), +// The provided code will clear the E3 exception (if pending), // otherwise clear the E1 exception. The frestore is not really // necessary for E1 exceptions. // @@ -82,7 +82,7 @@ SYM(_fpspEntry_dz): // to the appropriate handler for the exception in the fpsr. Note // that this fix is only for d43b parts, and is skipped if the // version number is not $40. -// +// // .global SYM(_fpspEntry_inex) .global real_inex @@ -102,7 +102,7 @@ SYM(_fpspEntry_inex): bra snan inex_ckofl: btstb #ovfl_bit,2(sp) //test for ovfl - beq inex_ckufl + beq inex_ckufl addl #4,sp frestore (sp)+ unlk a6 @@ -146,7 +146,7 @@ inex_done: frestore (sp)+ unlk a6 jmp ([SYM(M68040FPSPUserExceptionHandlers)+2*4],%za0) - + // // Overflow exception // @@ -164,7 +164,7 @@ ovfl_done: frestore (sp)+ unlk a6 jmp ([SYM(M68040FPSPUserExceptionHandlers)+6*4],%za0) - + // // Underflow exception // @@ -182,7 +182,7 @@ unfl_done: frestore (sp)+ unlk a6 jmp ([SYM(M68040FPSPUserExceptionHandlers)+4*4],%za0) - + // // Signalling NAN exception // @@ -213,7 +213,7 @@ real_operr: frestore (sp)+ unlk a6 jmp ([SYM(M68040FPSPUserExceptionHandlers)+5*4],%za0) - + // // BSUN exception // @@ -237,7 +237,7 @@ real_bsun: // // F-line exception // -// A 'real' F-line exception is one that the FPSP is not supposed to +// A 'real' F-line exception is one that the FPSP is not supposed to // handle. E.g. an instruction with a co-processor ID that is not 1. // .global SYM(_fpspEntry_fline) @@ -341,7 +341,7 @@ user_write: // a1 - supervisor destination address // d0 - number of bytes to read (maximum count is 12) // -// Like mem_write, mem_read always reads with a supervisor +// Like mem_write, mem_read always reads with a supervisor // destination address on the supervisor stack. Also like mem_write, // the EXC_SR is checked and a simple memory copy is done if reading // from supervisor space is indicated. diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/sacos.S b/c/src/lib/libcpu/m68k/m68040/fpsp/sacos.S index f4f2c10252..361f76fc2a 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/sacos.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/sacos.S @@ -14,7 +14,7 @@ // // Accuracy and Monotonicity: The returned result is within 3 ulps in // 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the -// result is subsequently rounded to double precision. The +// result is subsequently rounded to double precision. The // result is provably monotonic in double precision. // // Speed: The program sCOS takes approximately 310 cycles. @@ -40,8 +40,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SACOS idnt 2,1 | Motorola 040 Floating Point Software Package @@ -112,6 +112,6 @@ ACOSBIG: ACOSP1: fmovel %d1,%FPCR fmoves #0x00000000,%fp0 - rts //Facos ; of +1 is exact + rts //Facos ; of +1 is exact |end diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/sasin.S b/c/src/lib/libcpu/m68k/m68040/fpsp/sasin.S index 44de0ae440..9d4d34c653 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/sasin.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/sasin.S @@ -14,7 +14,7 @@ // // Accuracy and Monotonicity: The returned result is within 3 ulps in // 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the -// result is subsequently rounded to double precision. The +// result is subsequently rounded to double precision. The // result is provably monotonic in double precision. // // Speed: The program sASIN takes approximately 310 cycles. @@ -40,8 +40,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SASIN idnt 2,1 | Motorola 040 Floating Point Software Package @@ -99,7 +99,7 @@ asinbig: andil #0x80000000,%d0 // ...SIGN BIT OF X oril #0x3F800000,%d0 // ...+-1 IN SGL FORMAT movel %d0,-(%sp) // ...push SIGN(X) IN SGL-FMT - fmovel %d1,%FPCR + fmovel %d1,%FPCR fmuls (%sp)+,%fp0 bra t_frcinx diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/satan.S b/c/src/lib/libcpu/m68k/m68040/fpsp/satan.S index 68733dc482..504954740a 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/satan.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/satan.S @@ -45,8 +45,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //satan idnt 2,1 | Motorola 040 Floating Point Software Package @@ -54,7 +54,7 @@ |section 8 #include "fpsp.defs" - + BOUNDS1: .long 0x3FFB8000,0x4002FFFF ONE: .long 0x3F800000 @@ -324,7 +324,7 @@ ATANMAIN: //--THE REASON FOR THIS REARRANGEMENT IS TO MAKE THE INDEPENDENT //--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED - + fmovex %fp0,%fp1 fmulx %fp1,%fp1 fmoved ATANA3,%fp2 @@ -334,7 +334,7 @@ ATANMAIN: faddd ATANA2,%fp2 // ...A2+V*(A3+V) fmuld ATANA1,%fp1 // ...A1*U*V fmulx %fp2,%fp1 // ...A1*U*V*(A2+V*(A3+V)) - + faddx %fp1,%fp0 // ...ATAN(U), FP1 RELEASED fmovel %d1,%FPCR //restore users exceptions faddx ATANF(%a6),%fp0 // ...ATAN(X) @@ -358,7 +358,7 @@ ATANSM: //--COMPUTE POLYNOMIAL fmulx %fp0,%fp0 // ...FP0 IS Y = X*X - + movew #0x0000,XDCARE(%a6) fmovex %fp0,%fp1 @@ -383,7 +383,7 @@ ATANSM: fmulx X(%a6),%fp0 // ...X*Y faddx %fp2,%fp1 // ...[B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))] - + fmulx %fp1,%fp0 // ...X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]) @@ -415,7 +415,7 @@ ATANBIG: fmoves #0xBF800000,%fp1 // ...LOAD -1 fdivx %fp0,%fp1 // ...FP1 IS -1/X - + //--DIVIDE IS STILL CRANKING fmovex %fp1,%fp0 // ...FP0 IS X' @@ -441,14 +441,14 @@ ATANBIG: fmulx X(%a6),%fp0 // ...X'*Y faddx %fp2,%fp1 // ...[Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)] - + fmulx %fp1,%fp0 // ...X'*Y*([B1+Z*(B3+Z*B5)] // ... +[Y*(B2+Z*(B4+Z*B6))]) faddx X(%a6),%fp0 fmovel %d1,%FPCR //restore users exceptions - + btstb #7,(%a0) beqs pos_big @@ -476,5 +476,5 @@ pos_huge: fmovel %d1,%fpcr fsubx PTINY,%fp0 bra t_frcinx - + |end diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/satanh.S b/c/src/lib/libcpu/m68k/m68040/fpsp/satanh.S index 592dfe7d1d..e0ebd1ed96 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/satanh.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/satanh.S @@ -15,7 +15,7 @@ // // Accuracy and Monotonicity: The returned result is within 3 ulps in // 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the -// result is subsequently rounded to double precision. The +// result is subsequently rounded to double precision. The // result is provably monotonic in double precision. // // Speed: The program satanh takes approximately 270 cycles. @@ -35,7 +35,7 @@ // 3. If |X| > 1, go to 5. // // 4. (|X| = 1) Generate infinity with an appropriate sign and -// divide-by-zero by +// divide-by-zero by // sgn := sign(X) // atan(X) := sgn / (+0). // Exit. @@ -47,8 +47,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //satanh idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/scale.S b/c/src/lib/libcpu/m68k/m68040/fpsp/scale.S index 4a5129d19c..43cb7256a3 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/scale.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/scale.S @@ -11,7 +11,7 @@ // The entry point sscale is called from do_func to emulate // the fscale unimplemented instruction. // -// Input: Double-extended destination operand in FPTEMP, +// Input: Double-extended destination operand in FPTEMP, // double-extended source operand in ETEMP. // // Output: The function returns scale(X,Y) to fp0. @@ -19,12 +19,12 @@ // Modifies: fp0. // // Algorithm: -// +// // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SCALE idnt 2,1 | Motorola 040 Floating Point Software Package @@ -149,7 +149,7 @@ nden_exit: src_neg: addl %d0,%d1 //add src to dest beqs denorm //if zero, result is denorm - blts fix_dnrm //if negative, result is + blts fix_dnrm //if negative, result is // ;needing denormalization tstb L_SCR1(%a6) beqs sneg_pos @@ -163,7 +163,7 @@ sneg_pos: // // The result exponent is below denorm value. Test for catastrophic -// underflow and force zero if true. If not, try to shift the +// underflow and force zero if true. If not, try to shift the // mantissa right until a zero exponent exists. // fix_dnrm: @@ -231,7 +231,7 @@ no_dir: rts // -// The rounding mode changed the zero to a smallest denorm. Call +// The rounding mode changed the zero to a smallest denorm. Call // t_resdnrm with exceptional operand in ETEMP. // sm_dnrm: @@ -252,7 +252,7 @@ not_zero: fix_exit: bras sm_dnrm - + // // The result has underflowed to zero. Return zero and set // unfl, aunfl, and ainex. @@ -286,7 +286,7 @@ neg_zero: clrl FP_SCR1(%a6) //clear the exceptional operand clrl FP_SCR1+4(%a6) //for gen_except. clrl FP_SCR1+8(%a6) - fmoves #0x80000000,%fp0 + fmoves #0x80000000,%fp0 rts pos_zero: clrl FP_SCR1(%a6) //clear the exceptional operand @@ -301,7 +301,7 @@ pos_zero: // then adding the remainder of the source to the exponent. // dst_dnrm: - moveml %d2/%d3,-(%a7) + moveml %d2/%d3,-(%a7) movew FPTEMP_EX(%a6),%d1 movel FPTEMP_HI(%a6),%d2 movel FPTEMP_LO(%a6),%d3 @@ -315,7 +315,7 @@ dst_loop: roxll #1,%d2 bras dst_loop // -// Destination became normalized. Simply add the remaining +// Destination became normalized. Simply add the remaining // portion of the src to the exponent. // dst_norm: diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/scosh.S b/c/src/lib/libcpu/m68k/m68040/fpsp/scosh.S index 92e53918c0..7226615936 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/scosh.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/scosh.S @@ -51,8 +51,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SCOSH idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/setox.S b/c/src/lib/libcpu/m68k/m68040/fpsp/setox.S index 43e01bc25a..a11186a32c 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/setox.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/setox.S @@ -333,8 +333,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //setox idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/sgetem.S b/c/src/lib/libcpu/m68k/m68040/fpsp/sgetem.S index d1e8a49c41..514a433bb9 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/sgetem.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/sgetem.S @@ -3,14 +3,14 @@ // // sgetem.sa 3.1 12/10/90 // -// The entry point sGETEXP returns the exponent portion +// The entry point sGETEXP returns the exponent portion // of the input argument. The exponent bias is removed -// and the exponent value is returned as an extended +// and the exponent value is returned as an extended // precision number in fp0. sGETEXPD handles denormalized // numbers. // -// The entry point sGETMAN extracts the mantissa of the -// input argument. The mantissa is converted to an +// The entry point sGETMAN extracts the mantissa of the +// input argument. The mantissa is converted to an // extended precision number and returned in fp0. The // range of the result is [1.0 - 2.0). // @@ -26,8 +26,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SGETEM idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/sint.S b/c/src/lib/libcpu/m68k/m68040/fpsp/sint.S index a9ddacb98a..6f1dfd1af1 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/sint.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/sint.S @@ -3,8 +3,8 @@ // // sint.sa 3.1 12/10/90 // -// The entry point sINT computes the rounded integer -// equivalent of the input argument, sINTRZ computes +// The entry point sINT computes the rounded integer +// equivalent of the input argument, sINTRZ computes // the integer rounded to zero of the input argument. // // Entry points sint and sintrz are called from do_func @@ -26,10 +26,10 @@ // // Algorithm: (sint and sintrz) // -// 1. If exp(X) >= 63, return X. +// 1. If exp(X) >= 63, return X. // If exp(X) < 0, return +/- 0 or +/- 1, according to // the rounding mode. -// +// // 2. (X is in range) set rsc = 63 - exp(X). Unnormalize the // result to the exponent $403e. // @@ -53,8 +53,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SINT idnt 2,1 | Motorola 040 Floating Point Software Package @@ -80,9 +80,9 @@ sint: bfextu FPCR_MODE(%a6){#2:#2},%d1 //use user's mode for rounding // ;implicitly has extend precision -// ;in upper word. +// ;in upper word. movel %d1,L_SCR1(%a6) //save mode bits - bras sintexc + bras sintexc // // FINT with extended denorm inputs. @@ -117,13 +117,13 @@ sintmz: sintrz: movel #1,L_SCR1(%a6) //use rz mode for rounding // ;implicitly has extend precision -// ;in upper word. - bras sintexc +// ;in upper word. + bras sintexc // // SINTDO // // Input: a0 points to an IEEE extended format operand -// Output: fp0 has the result +// Output: fp0 has the result // // Exceptions: // @@ -135,7 +135,7 @@ sintrz: sintdo: bfextu FPCR_MODE(%a6){#2:#2},%d1 //use user's mode for rounding // ;implicitly has ext precision -// ;in upper word. +// ;in upper word. movel %d1,L_SCR1(%a6) //save mode bits // // Real work of sint is in sintexc @@ -143,7 +143,7 @@ sintdo: sintexc: bclrb #sign_bit,LOCAL_EX(%a0) //convert to internal extended // ;format - sne LOCAL_SGN(%a0) + sne LOCAL_SGN(%a0) cmpw #0x403e,LOCAL_EX(%a0) //check if (unbiased) exp > 63 bgts out_rnge //branch if exp < 63 cmpw #0x3ffd,LOCAL_EX(%a0) //check if (unbiased) exp < 0 @@ -189,7 +189,7 @@ un_rnrz: un_rnrz_neg: bsr ld_mzero bra t_inx2 - + // // Input is greater than 2^63. All bits are significant. Return // the input. diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/slog2.S b/c/src/lib/libcpu/m68k/m68040/fpsp/slog2.S index 42c70092fa..610d6be18f 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/slog2.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/slog2.S @@ -3,28 +3,28 @@ // // slog2.sa 3.1 12/10/90 // -// The entry point slog10 computes the base-10 +// The entry point slog10 computes the base-10 // logarithm of an input argument X. -// slog10d does the same except the input value is a -// denormalized number. +// slog10d does the same except the input value is a +// denormalized number. // sLog2 and sLog2d are the base-2 analogues. // -// INPUT: Double-extended value in memory location pointed to +// INPUT: Double-extended value in memory location pointed to // by address register a0. // -// OUTPUT: log_10(X) or log_2(X) returned in floating-point +// OUTPUT: log_10(X) or log_2(X) returned in floating-point // register fp0. // -// ACCURACY and MONOTONICITY: The returned result is within 1.7 -// ulps in 64 significant bit, i.e. within 0.5003 ulp -// to 53 bits if the result is subsequently rounded -// to double precision. The result is provably monotonic +// ACCURACY and MONOTONICITY: The returned result is within 1.7 +// ulps in 64 significant bit, i.e. within 0.5003 ulp +// to 53 bits if the result is subsequently rounded +// to double precision. The result is provably monotonic // in double precision. // -// SPEED: Two timings are measured, both in the copy-back mode. -// The first one is measured when the function is invoked -// the first time (so the instructions and data are not -// in cache), and the second one is measured when the +// SPEED: Two timings are measured, both in the copy-back mode. +// The first one is measured when the function is invoked +// the first time (so the instructions and data are not +// in cache), and the second one is measured when the // function is reinvoked at the same input argument. // // ALGORITHM and IMPLEMENTATION NOTES: @@ -44,7 +44,7 @@ // 2.2 Return ans := Y * INV_L10. // // -// slog10: +// slog10: // // Step 0. If X < 0, create a NaN and raise the invalid operation // flag. Otherwise, save FPCR in D1; set FpCR to default. @@ -98,15 +98,15 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SLOG2 idnt 2,1 | Motorola 040 Floating Point Software Package |section 8 - |xref t_frcinx + |xref t_frcinx |xref t_operr |xref slogn |xref slognd diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/slogn.S b/c/src/lib/libcpu/m68k/m68040/fpsp/slogn.S index b208a603b7..8f61565996 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/slogn.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/slogn.S @@ -15,11 +15,11 @@ // // Accuracy and Monotonicity: The returned result is within 2 ulps in // 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the -// result is subsequently rounded to double precision. The +// result is subsequently rounded to double precision. The // result is provably monotonic in double precision. // -// Speed: The program slogn takes approximately 190 cycles for input -// argument X such that |X-1| >= 1/16, which is the the usual +// Speed: The program slogn takes approximately 190 cycles for input +// argument X such that |X-1| >= 1/16, which is the the usual // situation. For those arguments, slognp1 takes approximately // 210 cycles. For the less common arguments, the program will // run no worse than 10% slower. @@ -47,26 +47,26 @@ // Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done in Step 2 // of the algorithm for LOGN and compute log(1+X) as // k*log(2) + log(F) + poly where poly approximates log(1+u), -// u = (Y-F)/F. +// u = (Y-F)/F. // // Implementation Notes: // Note 1. There are 64 different possible values for F, thus 64 log(F)'s -// need to be tabulated. Moreover, the values of 1/F are also +// need to be tabulated. Moreover, the values of 1/F are also // tabulated so that the division in (Y-F)/F can be performed by a // multiplication. // // Note 2. In Step 2 of lognp1, in order to preserved accuracy, the value -// Y-F has to be calculated carefully when 1/2 <= X < 3/2. +// Y-F has to be calculated carefully when 1/2 <= X < 3/2. // // Note 3. To fully exploit the pipeline, polynomials are usually separated // into two parts evaluated independently before being added up. -// +// // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //slogn idnt 2,1 | Motorola 040 Floating Point Software Package @@ -264,7 +264,7 @@ slognd: //----the value TWOTO100 is no longer needed. //----Note that this code assumes the denormalized input is NON-ZERO. - moveml %d2-%d7,-(%a7) // ...save some registers + moveml %d2-%d7,-(%a7) // ...save some registers movel #0x00000000,%d3 // ...D3 is exponent of smallest norm. # movel 4(%a0),%d4 movel 8(%a0),%d5 // ...(D4,D5) is (Hi_X,Lo_X) @@ -349,7 +349,7 @@ LOGMAIN: //--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING //--LOG(1+U) CAN BE VERY EFFICIENT. //--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO -//--DIVISION IS NEEDED TO CALCULATE (Y-F)/F. +//--DIVISION IS NEEDED TO CALCULATE (Y-F)/F. //--GET K, Y, F, AND ADDRESS OF 1/F. asrl #8,%d0 @@ -365,7 +365,7 @@ LOGMAIN: andil #0xFE000000,FFRAC(%a6) // ...FIRST 7 BITS OF Y oril #0x01000000,FFRAC(%a6) // ...GET F: ATTACH A 1 AT THE EIGHTH BIT movel FFRAC(%a6),%d0 // ...READY TO GET ADDRESS OF 1/F - andil #0x7E000000,%d0 + andil #0x7E000000,%d0 asrl #8,%d0 asrl #8,%d0 asrl #4,%d0 // ...SHIFTED 20, D0 IS THE DISPLACEMENT @@ -392,7 +392,7 @@ LP1CONT1: //--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))] fmovex %fp2,%fp3 - fmovex %fp2,%fp1 + fmovex %fp2,%fp1 fmuld LOGA6,%fp1 // ...V*A6 fmuld LOGA5,%fp2 // ...V*A5 @@ -442,7 +442,7 @@ LP1CONT2: fmovex %fp1,%fp0 fmulx %fp0,%fp0 // ...FP0 IS V fmovex %fp1,SAVEU(%a6) // ...STORE U IN MEMORY, FREE FP1 - fmovex %fp0,%fp1 + fmovex %fp0,%fp1 fmulx %fp1,%fp1 // ...FP1 IS W fmoved LOGB5,%fp3 @@ -467,7 +467,7 @@ LP1CONT2: fmulx %fp1,%fp0 // ...U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] ) fmovel %d1,%fpcr - faddx SAVEU(%a6),%fp0 + faddx SAVEU(%a6),%fp0 bra t_frcinx rts @@ -551,7 +551,7 @@ KISNEG1: asrl #8,%d0 asrl #4,%d0 // ...D0 CONTAINS DISPLACEMENT FOR 1/F faddx %fp1,%fp1 // ...GET 2Z - fmovemx %fp2-%fp2/%fp3,-(%sp) // ...SAVE FP2 + fmovemx %fp2-%fp2/%fp3,-(%sp) // ...SAVE FP2 faddx %fp1,%fp0 // ...FP0 IS Y-F = (2-F)+2Z lea LOGTBL,%a0 // ...A0 IS ADDRESS OF 1/F addal %d0,%a0 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/smovecr.S b/c/src/lib/libcpu/m68k/m68040/fpsp/smovecr.S index e2caae764e..000adcf8cd 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/smovecr.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/smovecr.S @@ -17,8 +17,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SMOVECR idnt 2,1 | Motorola 040 Floating Point Software Package @@ -41,7 +41,7 @@ FZERO: .long 00000000 // -// FMOVECR +// FMOVECR // .global smovcr smovcr: @@ -57,7 +57,7 @@ smovcr: cmpib #0x0e,%d0 //check range $0b - $0e bles SM_TBL //valid constants in this range cmpib #0x2f,%d0 //check range $10 - $2f - bles Z_VAL //if in this range, return zero + bles Z_VAL //if in this range, return zero cmpib #0x3f,%d0 //check range $30 - $3f ble BG_TBL //valid constants in this range Z_VAL: @@ -151,7 +151,7 @@ not_ext: lea FP_SCR1(%a6),%a0 btstb #sign_bit,LOCAL_EX(%a0) sne LOCAL_SGN(%a0) //convert to internal ext. format - + bsr round //go round the mantissa bfclr LOCAL_SGN(%a0){#0:#8} //convert back to IEEE ext format diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/srem_mod.S b/c/src/lib/libcpu/m68k/m68040/fpsp/srem_mod.S index 8bbcb8a3de..1a148f90d8 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/srem_mod.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/srem_mod.S @@ -23,7 +23,7 @@ // --------- // // Step 1. Save and strip signs of X and Y: signX := sign(X), -// signY := sign(Y), X := |X|, Y := |Y|, +// signY := sign(Y), X := |X|, Y := |Y|, // signQ := signX EOR signY. Record whether MOD or REM // is requested. // @@ -43,7 +43,7 @@ // // Step 4. At this point, R = X - QY = MOD(X,Y). Set // Last_Subtract := false (used in Step 7 below). If -// MOD is requested, go to Step 6. +// MOD is requested, go to Step 6. // // Step 5. R = MOD(X,Y), but REM(X,Y) is requested. // 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to @@ -63,13 +63,13 @@ // X = 2^(j)*(Q+1)Y. set Q := 2^(j)*(Q+1), // R := 0. Return signQ, last 7 bits of Q, and R. // -// - +// + // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. SREM_MOD: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -364,10 +364,10 @@ Fix_Sign: //..Get Q // Get_Q: - clrl %d6 + clrl %d6 movew SignQ(%a6),%d6 // ...D6 is sign(Q) movel #8,%d7 - lsrl %d7,%d6 + lsrl %d7,%d6 andil #0x0000007F,%d3 // ...7 bits of Q orl %d6,%d3 // ...sign and bits of Q swap %d3 @@ -393,7 +393,7 @@ Finish: Rem_is_0: //..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1) addql #1,%d3 - cmpil #8,%d0 // ...D0 is j + cmpil #8,%d0 // ...D0 is j bges Q_Big lsll %d0,%d3 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/ssin.S b/c/src/lib/libcpu/m68k/m68040/fpsp/ssin.S index 9c93c95940..f4e76aba36 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/ssin.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/ssin.S @@ -85,8 +85,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SSIN idnt 2,1 | Motorola 040 Floating Point Software Package @@ -206,7 +206,7 @@ SINMAIN: //--HIDE THE NEXT THREE INSTRUCTIONS lea PITBL+0x200,%a1 // ...TABLE OF N*PI/2, N = -32,...,32 - + //--FP1 IS NOW READY fmovel %fp1,N(%a6) // ...CONVERT TO INTEGER @@ -275,7 +275,7 @@ SINPOLY: faddx %fp2,%fp1 // ...[A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))] //--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING //--FP2 RELEASED, RESTORE NOW AND TAKE FULL ADVANTAGE OF HIDING - + fmulx %fp1,%fp0 // ...SIN(R')-R' //--FP1 RELEASED. @@ -337,7 +337,7 @@ COSPOLY: fmulx %fp2,%fp0 // ...S(B2+T(B4+T(B6+TB8))) //--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING //--FP2 RELEASED. - + faddx %fp1,%fp0 //--FP1 RELEASED @@ -354,7 +354,7 @@ SINBORS: //--IF |X| < 2**(-40), RETURN X OR 1. cmpil #0x3FFF8000,%d0 bgts REDUCEX - + SINSM: movel ADJN(%a6),%d0 @@ -468,7 +468,7 @@ WORK: movew %d2,FP_SCR2(%a6) clrw FP_SCR2+2(%a6) movel #0xC90FDAA2,FP_SCR2+4(%a6) - clrl FP_SCR2+8(%a6) // ...FP_SCR2 is 2**(L) * Piby2_1 + clrl FP_SCR2+8(%a6) // ...FP_SCR2 is 2**(L) * Piby2_1 //--FP2 IS READY fsubs TWOTO63(%a6),%fp2 // ...FP2 is N @@ -516,7 +516,7 @@ RESTORE: movel (%a7)+,%d2 fmovemx (%a7)+,%fp2-%fp5 - + movel ADJN(%a6),%d0 cmpil #4,%d0 @@ -561,7 +561,7 @@ SCMAIN: //--HIDE THE NEXT THREE INSTRUCTIONS lea PITBL+0x200,%a1 // ...TABLE OF N*PI/2, N = -32,...,32 - + //--FP1 IS NOW READY fmovel %fp1,N(%a6) // ...CONVERT TO INTEGER @@ -579,7 +579,7 @@ SCCONT: //--HIDE THE NEXT TWO movel N(%a6),%d0 rorl #1,%d0 - + cmpil #0,%d0 // ...D0 < 0 IFF N IS ODD bge NEVEN @@ -643,7 +643,7 @@ NODD: fmulx %fp0,%fp1 // ...S(A1+...) fmulx %fp2,%fp0 // ...S(B2+...) - + fmulx RPRIME(%a6),%fp1 // ...R'S(A1+...) fadds COSB1,%fp0 // ...B1+S(B2...) @@ -711,7 +711,7 @@ NEVEN: fmulx %fp0,%fp1 // ...S(B2+...) fmulx %fp2,%fp0 // ...s(a1+...) - + fadds COSB1,%fp1 // ...B1+S(B2...) fmulx RPRIME(%a6),%fp0 // ...R'S(A1+...) @@ -730,7 +730,7 @@ NEVEN: SCBORS: cmpil #0x3FFF8000,%d0 bgt REDUCEX - + SCSM: movew #0x0000,XDCARE(%a6) diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/ssinh.S b/c/src/lib/libcpu/m68k/m68040/fpsp/ssinh.S index 52af339319..41c813f0d6 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/ssinh.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/ssinh.S @@ -7,7 +7,7 @@ // an input argument; sSinhd does the same except for denormalized // input. // -// Input: Double-extended number X in location pointed to +// Input: Double-extended number X in location pointed to // by address register a0. // // Output: The value sinh(X) returned in floating-point register Fp0. @@ -51,8 +51,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //SSINH idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/stan.S b/c/src/lib/libcpu/m68k/m68040/fpsp/stan.S index 6f698e63d9..dcfb7a66c7 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/stan.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/stan.S @@ -52,8 +52,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //STAN idnt 2,1 | Motorola 040 Floating Point Software Package @@ -239,10 +239,10 @@ TANCONT: fmulx %fp0,%fp2 // ...RS(P1+S(P2+SP3)) fmulx %fp3,%fp1 // ...S(Q1+S(Q2+S(Q3+SQ4))) - + faddx %fp2,%fp0 // ...R+RS(P1+S(P2+SP3)) - + fadds #0x3F800000,%fp1 // ...1+S(Q1+...) @@ -277,11 +277,11 @@ NODD: fmulx %fp1,%fp2 // ...RS(P1+S(P2+SP3)) fmulx %fp3,%fp0 // ...S(Q1+S(Q2+S(Q3+SQ4))) - + faddx %fp2,%fp1 // ...R+RS(P1+S(P2+SP3)) fadds #0x3F800000,%fp0 // ...1+S(Q1+...) - + fmovex %fp1,-(%sp) eoril #0x80000000,(%sp) @@ -399,7 +399,7 @@ WORK: movew %d2,FP_SCR2(%a6) clrw FP_SCR2+2(%a6) movel #0xC90FDAA2,FP_SCR2+4(%a6) - clrl FP_SCR2+8(%a6) // ...FP_SCR2 is 2**(L) * Piby2_1 + clrl FP_SCR2+8(%a6) // ...FP_SCR2 is 2**(L) * Piby2_1 //--FP2 IS READY fsubs TWOTO63(%a6),%fp2 // ...FP2 is N @@ -447,7 +447,7 @@ RESTORE: movel (%a7)+,%d2 fmovemx (%a7)+,%fp2-%fp5 - + movel N(%a6),%d0 rorl #1,%d0 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/stanh.S b/c/src/lib/libcpu/m68k/m68040/fpsp/stanh.S index b3c591ac96..f71b987063 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/stanh.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/stanh.S @@ -51,14 +51,14 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //STANH idnt 2,1 | Motorola 040 Floating Point Software Package |section 8 - + #include "fpsp.defs" .set X,FP_SCR5 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/sto_res.S b/c/src/lib/libcpu/m68k/m68040/fpsp/sto_res.S index a5b6543914..67bd145e41 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/sto_res.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/sto_res.S @@ -7,9 +7,9 @@ // Library functions return result in fp0. If fp0 is not the // users destination register then fp0 is moved to the the // correct floating-point destination register. fp0 and fp1 -// are then restored to the original contents. +// are then restored to the original contents. // -// Input: result in fp0,fp1 +// Input: result in fp0,fp1 // // d2 & a0 should be kept unmodified // @@ -21,8 +21,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. STO_RES: //idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/stwotox.S b/c/src/lib/libcpu/m68k/m68040/fpsp/stwotox.S index 45f2ad52f7..45833e0801 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/stwotox.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/stwotox.S @@ -78,8 +78,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //STWOTOX idnt 2,1 | Motorola 040 Floating Point Software Package @@ -224,14 +224,14 @@ TWOOK1: cmpil #0x400D80C0,%d0 // ...|X| > 16480? bles TWOMAIN bra EXPBORS - + TWOMAIN: //--USUAL CASE, 2^(-70) <= |X| <= 16480 fmovex %fp0,%fp1 fmuls #0x42800000,%fp1 // ...64 * X - + fmovel %fp1,N(%a6) // ...N = ROUND-TO-INT(64 X) movel %d2,-(%sp) lea EXPTBL,%a1 // ...LOAD ADDRESS OF TABLE OF 2^(J/64) @@ -266,7 +266,7 @@ TWOMAIN: clrw FACT2HI+2(%a6) clrl FACT2LOW(%a6) addw %d0,FACT1(%a6) - + fmulx LOG2,%fp0 // ...FP0 IS R addw %d0,FACT2(%a6) @@ -334,7 +334,7 @@ TENMAIN: fmovex %fp0,%fp1 fmuld L2TEN64,%fp1 // ...X*64*LOG10/LOG2 - + fmovel %fp1,N(%a6) // ...N=INT(X*64*LOG10/LOG2) movel %d2,-(%sp) lea EXPTBL,%a1 // ...LOAD ADDRESS OF TABLE OF 2^(J/64) @@ -377,7 +377,7 @@ TENMAIN: clrl FACT2LOW(%a6) fmulx LOG10,%fp0 // ...FP0 IS R - + addw %d0,FACT1(%a6) addw %d0,FACT2(%a6) @@ -407,9 +407,9 @@ expr: fmulx %fp1,%fp2 // ...FP2 IS S*(A1+S*(A3+S*A5)) faddx %fp3,%fp0 // ...FP0 IS R+R*S*(A2+S*A4) - + faddx %fp2,%fp0 // ...FP0 IS EXP(R) - 1 - + //--FINAL RECONSTRUCTION PROCESS //--EXP(X) = 2^M*2^(J/64) + 2^M*2^(J/64)*(EXP(R)-1) - (1 OR 0) diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/tbldo.S b/c/src/lib/libcpu/m68k/m68040/fpsp/tbldo.S index df3caba0e5..b3caf1e9d7 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/tbldo.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/tbldo.S @@ -8,19 +8,19 @@ // of indirection in do_func for monadic // functions. Dyadic functions require two // levels, and the tables are still contained -// in do_func. The table is arranged for +// in do_func. The table is arranged for // index with a 10-bit index, with the first // 7 bits the opcode, and the remaining 3 // the stag. For dyadic functions, all // valid addresses are to the generic entry -// point. +// point. // // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //TBLDO idnt 2,1 | Motorola 040 Floating Point Software Package @@ -59,7 +59,7 @@ tblpre: .long smovcr //$00-7 fmovecr all .long sint //$01-0 fint norm - .long szero //$01-1 fint zero + .long szero //$01-1 fint zero .long sinf //$01-2 fint inf .long src_nan //$01-3 fint nan .long sintd //$01-4 fint denorm inx diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/util.S b/c/src/lib/libcpu/m68k/m68040/fpsp/util.S index f73f15be25..c0090d6a58 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/util.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/util.S @@ -6,20 +6,20 @@ // This file contains routines used by other programs. // // ovf_res: used by overflow to force the correct -// result. ovf_r_k, ovf_r_x2, ovf_r_x3 are +// result. ovf_r_k, ovf_r_x2, ovf_r_x3 are // derivatives of this routine. // get_fline: get user's opcode word // g_dfmtou: returns the destination format. // g_opcls: returns the opclass of the float instruction. -// g_rndpr: returns the rounding precision. +// g_rndpr: returns the rounding precision. // reg_dest: write byte, word, or long data to Dn // // // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. //UTIL idnt 2,1 | Motorola 040 Floating Point Software Package @@ -41,13 +41,13 @@ // are unnecessary as ovf_res always returns the sign separately from // the exponent. // ;+inf -EXT_PINF: .long 0x7fff0000,0x00000000,0x00000000,0x00000000 +EXT_PINF: .long 0x7fff0000,0x00000000,0x00000000,0x00000000 // ;largest +ext -EXT_PLRG: .long 0x7ffe0000,0xffffffff,0xffffffff,0x00000000 +EXT_PLRG: .long 0x7ffe0000,0xffffffff,0xffffffff,0x00000000 // ;largest magnitude +sgl in ext -SGL_PLRG: .long 0x407e0000,0xffffff00,0x00000000,0x00000000 +SGL_PLRG: .long 0x407e0000,0xffffff00,0x00000000,0x00000000 // ;largest magnitude +dbl in ext -DBL_PLRG: .long 0x43fe0000,0xffffffff,0xfffff800,0x00000000 +DBL_PLRG: .long 0x43fe0000,0xffffffff,0xfffff800,0x00000000 // ;largest -ext tblovfl: @@ -72,7 +72,7 @@ tblovfl: // // ovf_r_k --- overflow result calculation // -// This entry point is used by kernel_ex. +// This entry point is used by kernel_ex. // // This forces the destination precision to be extended // @@ -81,7 +81,7 @@ tblovfl: // .global ovf_r_k ovf_r_k: - lea ETEMP(%a6),%a0 //a0 points to source operand + lea ETEMP(%a6),%a0 //a0 points to source operand bclrb #sign_bit,ETEMP_EX(%a6) sne ETEMP_SGN(%a6) //convert to internal IEEE format @@ -114,10 +114,10 @@ ovf_e3_exc: beql ovff_dbl //force precision is double movew CMDREG3B(%a6),%d0 //get the command word again andil #0x7f,%d0 //clear all except operation - cmpil #0x33,%d0 + cmpil #0x33,%d0 beql ovf_fsgl //fsglmul or fsgldiv cmpil #0x30,%d0 - beql ovf_fsgl + beql ovf_fsgl bra ovf_fpcr //instruction is none of the above // ;use FPCR ovf_e1_exc: @@ -134,7 +134,7 @@ ovf_e1_exc: cmpil #0x00000024,%d0 beql ovf_fsgl //fsgldiv bra ovf_fpcr //none of the above, use FPCR -// +// // // Inst is either fsgldiv or fsglmul. Force extended precision. // @@ -154,7 +154,7 @@ ovff_dbl: ovf_fpcr: bfextu FPCR_MODE(%a6){#0:#2},%d0 //set round precision bra ovf_res - + // // // ovf_r_x3 --- overflow result calculation @@ -194,7 +194,7 @@ ovf_res: EXT_RN: leal EXT_PINF,%a1 //answer is +/- infinity bsetb #inf_bit,FPSR_CC(%a6) - bra set_sign //now go set the sign + bra set_sign //now go set the sign EXT_RZ: leal EXT_PLRG,%a1 //answer is +/- large number bra set_sign //now go set the sign @@ -315,9 +315,9 @@ get_fline: rts // // g_rndpr --- put rounding precision in d0{1:0} -// +// // valid return codes are: -// 00 - extended +// 00 - extended // 01 - single // 10 - double // @@ -352,7 +352,7 @@ g_rndpr: // For move out instructions (opclass 011) the destination format // is the same as the rounding precision. Pass results from g_dfmtou. // - bsr g_dfmtou + bsr g_dfmtou rts op_0x0: btstb #E3,E_BYTE(%a6) @@ -366,7 +366,7 @@ unf_e3_exc: beql unff_dbl movew CMDREG3B(%a6),%d0 //get the command word again andil #0x7f,%d0 //clear all except operation - cmpil #0x33,%d0 + cmpil #0x33,%d0 beql unf_fsgl //fsglmul or fsgldiv cmpil #0x30,%d0 beql unf_fsgl //fsgldiv or fsglmul @@ -410,7 +410,7 @@ unff_dbl: // Force extended // unf_fsgl: - movel #0,%d0 + movel #0,%d0 rts // // Get rounding precision set in FPCR{7:6}. @@ -438,7 +438,7 @@ opc_1b: // If E1, the format is from cmdreg1b{12:10} // If E3, the format is extended. // -// Dest. Fmt. +// Dest. Fmt. // extended 010 -> 00 // single 001 -> 01 // double 101 -> 10 @@ -470,17 +470,17 @@ not_dbl: // are unnecessary as unf_sub always returns the sign separately from // the exponent. // ;+zero -EXT_PZRO: .long 0x00000000,0x00000000,0x00000000,0x00000000 +EXT_PZRO: .long 0x00000000,0x00000000,0x00000000,0x00000000 // ;+zero -SGL_PZRO: .long 0x3f810000,0x00000000,0x00000000,0x00000000 +SGL_PZRO: .long 0x3f810000,0x00000000,0x00000000,0x00000000 // ;+zero -DBL_PZRO: .long 0x3c010000,0x00000000,0x00000000,0x00000000 +DBL_PZRO: .long 0x3c010000,0x00000000,0x00000000,0x00000000 // ;smallest +ext denorm -EXT_PSML: .long 0x00000000,0x00000000,0x00000001,0x00000000 +EXT_PSML: .long 0x00000000,0x00000000,0x00000001,0x00000000 // ;smallest +sgl denorm -SGL_PSML: .long 0x3f810000,0x00000100,0x00000000,0x00000000 +SGL_PSML: .long 0x3f810000,0x00000100,0x00000000,0x00000000 // ;smallest +dbl denorm -DBL_PSML: .long 0x3c010000,0x00000000,0x00000800,0x00000000 +DBL_PSML: .long 0x3c010000,0x00000000,0x00000800,0x00000000 // // UNF_SUB --- underflow result calculation // @@ -524,7 +524,7 @@ unf_sub: uEXT_RN: leal EXT_PZRO,%a1 //answer is +/- zero bsetb #z_bit,FPSR_CC(%a6) - bra uset_sign //now go set the sign + bra uset_sign //now go set the sign uEXT_RZ: leal EXT_PZRO,%a1 //answer is +/- zero bsetb #z_bit,FPSR_CC(%a6) @@ -631,7 +631,7 @@ end_unfr: // // // Input: -// L_SCR1: Data +// L_SCR1: Data // d1: data size and dest register number formatted as: // // 32 5 4 3 2 1 0 diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_bsun.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_bsun.S index 51a6d74d19..1ff35457fd 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_bsun.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_bsun.S @@ -15,8 +15,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_BSUN: //idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_fline.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_fline.S index 3dfbd08c52..b176419160 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_fline.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_fline.S @@ -15,8 +15,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_FLINE: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -54,7 +54,7 @@ fpsp_fline: leal L_SCR1(%a6),%a1 //use L_SCR1 as scratch movel #4,%d0 addl #4,%a6 //to offset the sub.l #4,a7 above so that -// ;a6 can point correctly to the stack frame +// ;a6 can point correctly to the stack frame // ;before branching to mem_read bsrl mem_read subl #4,%a6 @@ -64,7 +64,7 @@ fpsp_fline: bne not_mvcr //exit if not bfextu %d0{#16:#6},%d1 cmpib #0x17,%d1 //check if it is an FMOVECR encoding - bne not_mvcr + bne not_mvcr // ;if an FMOVECR instruction, fix stack // ;and go to FPSP_UNIMP fix_stack: diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_operr.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_operr.S index 9fd9c99cf0..589f21fb75 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_operr.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_operr.S @@ -15,8 +15,8 @@ // the dest format is integer (b, w, l) and the operr is caused by // integer overflow, or the source op is inf, then the result stored is // garbage. -// There are three cases in which operr is incorrectly signaled on the -// 040. This occurs for move_out of format b, w, or l for the largest +// There are three cases in which operr is incorrectly signaled on the +// 040. This occurs for move_out of format b, w, or l for the largest // negative integer (-2^7 for b, -2^15 for w, -2^31 for l). // // On opclass = 011 fmove.(b,w,l) that causes a conversion @@ -38,15 +38,15 @@ // Note 2: For trap enabled 040 does the following: // If the inst is move_out, then same as Note 1. // If the inst is not move_out, the dest is not modified. -// The exceptional operand is not defined for integer overflow +// The exceptional operand is not defined for integer overflow // during a move_out. // // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_OPERR: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -79,7 +79,7 @@ fpsp_operr: beqs operr_end // -// If the destination size is B,W,or L, the operr must be +// If the destination size is B,W,or L, the operr must be // handled here. // movel CMDREG1B(%a6),%d0 @@ -92,9 +92,9 @@ fpsp_operr: beq operr_byte // -// The size is not B,W,or L, so the operr is handled by the +// The size is not B,W,or L, so the operr is handled by the // kernel handler. Set the operr bits and clean up, leaving -// only the integer exception frame on the stack, and the +// only the integer exception frame on the stack, and the // fpu in the original exceptional state. // operr_end: @@ -113,7 +113,7 @@ operr_long: moveb STAG(%a6),%d0 //test stag for nan andib #0xe0,%d0 //clr all but tag cmpib #0x60,%d0 //check for nan - beq operr_nan + beq operr_nan cmpil #0x80000000,FPTEMP_LO(%a6) //test if ls lword is special bnes chklerr //if not equal, check for incorrect operr bsr check_upper //check if exp and ms mant are special @@ -160,7 +160,7 @@ operr_word: moveb STAG(%a6),%d0 //test stag for nan andib #0xe0,%d0 //clr all but tag cmpib #0x60,%d0 //check for nan - beq operr_nan + beq operr_nan cmpil #0xffff8000,FPTEMP_LO(%a6) //test if ls lword is special bnes chkwerr //if not equal, check for incorrect operr bsr check_upper //check if exp and ms mant are special @@ -187,7 +187,7 @@ operr_byte: moveb STAG(%a6),%d0 //test stag for nan andib #0xe0,%d0 //clr all but tag cmpib #0x60,%d0 //check for nan - beqs operr_nan + beqs operr_nan cmpil #0xffffff80,FPTEMP_LO(%a6) //test if ls lword is special bnes chkberr //if not equal, check for incorrect operr bsr check_upper //check if exp and ms mant are special @@ -231,7 +231,7 @@ store_max: bclrb #inex2_bit,FPSR_EXCEPT(%a6) bclrb #ainex_bit,FPSR_AEXCEPT(%a6) fmovel #0,%FPSR - + tstw FPTEMP_EX(%a6) //check sign blts load_neg movel #0x7fffffff,%d0 @@ -282,7 +282,7 @@ dest_mem: bsrl mem_write rts // -// Check the exponent for $c000 and the upper 32 bits of the +// Check the exponent for $c000 and the upper 32 bits of the // mantissa for $ffffffff. If both are true, return d0 clr // and store the lower n bits of the least lword of FPTEMP // to d0 for write out. If not, it is a real operr, and set d0. diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_ovfl.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_ovfl.S index e56f2b88c5..3e282ef8de 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_ovfl.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_ovfl.S @@ -10,7 +10,7 @@ // or when storing to memory, the contents of a floating-point // data register are too large to be represented in the // destination format. -// +// // Trap disabled results // // If the instruction is move_out, then garbage is stored in the @@ -37,8 +37,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_OVFL: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -75,7 +75,7 @@ fpsp_ovfl: // if overflow traps not enabled check for inexact exception // btstb #ovfl_bit,FPCR_ENABLE(%a6) - beqs ck_inex + beqs ck_inex // btstb #E3,E_BYTE(%a6) beqs no_e3_1 @@ -122,7 +122,7 @@ no_e3_2: frestore (%a7)+ unlk %a6 bral real_inex - + ovfl_exit: bclrb #E3,E_BYTE(%a6) //test and clear E3 bit beqs e1_set @@ -154,7 +154,7 @@ e1_set: // ovf_adj: // -// Have a0 point to the correct operand. +// Have a0 point to the correct operand. // btstb #E3,E_BYTE(%a6) //test E3 bit beqs ovf_e1 @@ -180,7 +180,7 @@ ovf_com: bsrl ovf_r_x3 //returns a0 pointing to result moveb L_SCR1(%a6),FPSR_CC(%a6) bral store //stores to memory or register - + not_opc011: bsrl ovf_r_x2 //returns a0 pointing to result bral store //stores to memory or register diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_snan.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_snan.S index 473630f7b7..dd3b6eb565 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_snan.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_snan.S @@ -16,7 +16,7 @@ // of the mantissa are sent to the integer unit). // // For trap enabled the 040 does the following: -// If the inst is move_out, then the results are the same as for trap +// If the inst is move_out, then the results are the same as for trap // disabled with the exception posted. If the instruction is not move_ // out, the dest. is not modified, and the exception is posted. // @@ -24,8 +24,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_SNAN: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -141,7 +141,7 @@ loop2: bral fpsp_done // -// Move_out +// Move_out // move_out: movel EXC_EA(%a6),%a0 //get <ea> from exc frame @@ -149,18 +149,18 @@ move_out: bfextu CMDREG1B(%a6){#3:#3},%d0 //move rx field to d0{2:0} cmpil #0,%d0 //check for long beqs sto_long //branch if move_out long - + cmpil #4,%d0 //check for word beqs sto_word //branch if move_out word - + cmpil #6,%d0 //check for byte beqs sto_byte //branch if move_out byte - + // // Not byte, word or long // rts -// +// // Get the 32 most significant bits of etemp mantissa // sto_long: @@ -169,13 +169,13 @@ sto_long: // // Set signalling nan bit // - bsetl #30,%d1 + bsetl #30,%d1 // // Store to the users destination address // tstl %a0 //check if <ea> is 0 beqs wrt_dn //destination is a data register - + movel %d1,-(%a7) //move the snan onto the stack movel %a0,%a1 //load dest addr into a1 movel %a7,%a0 //load src addr of snan into a0 @@ -191,7 +191,7 @@ sto_word: // // Set signalling nan bit // - bsetl #30,%d1 + bsetl #30,%d1 // // Store to the users destination address // @@ -213,7 +213,7 @@ sto_byte: // // Set signalling nan bit // - bsetl #30,%d1 + bsetl #30,%d1 // // Store to the users destination address // @@ -255,7 +255,7 @@ wrt_byte: // Check if it is a src nan or dst nan // not_out: - movel DTAG(%a6),%d0 + movel DTAG(%a6),%d0 bfextu %d0{#0:#3},%d0 //isolate dtag in lsbs cmpib #3,%d0 //check for nan in destination diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_store.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_store.S index f22dd71b8b..77a67af270 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_store.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_store.S @@ -13,8 +13,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_STORE: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -56,7 +56,7 @@ is_pos: // in the USER_FPn variable on the stack because all exception // handlers restore fp0-fp3 from there. // - cmpb #0x80,%d0 + cmpb #0x80,%d0 bnes not_fp0 fmovemx %fp0-%fp0,USER_FP0(%a6) rts @@ -139,7 +139,7 @@ dest_dbl: addw #0x3ff,%d0 //add double precision bias swap %d0 //d0 now in upper word lsll #4,%d0 //d0 now in proper place for dbl prec exp - tstb LOCAL_SGN(%a1) + tstb LOCAL_SGN(%a1) beqs get_mant //if positive, go process mantissa bsetl #31,%d0 //if negative, put in sign information // ; before continuing @@ -210,7 +210,7 @@ dest_sgl: addw #0x7f,%d0 //add single precision bias swap %d0 //put exp in upper word of d0 lsll #7,%d0 //shift it into single exp bits - tstb LOCAL_SGN(%a1) + tstb LOCAL_SGN(%a1) beqs get_sman //if positive, continue bsetl #31,%d0 //if negative, put in sign first bras get_sman //get mantissa @@ -242,7 +242,7 @@ sgl_Dn: orl #0x10,%d1 //reg_dest wants size added to reg# bral reg_dest //size is X, rts in reg_dest will // ;return to caller of dest_sgl - + dest_ext: tstb LOCAL_SGN(%a1) //put back sign into exponent word beqs dstx_cont diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_unfl.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_unfl.S index 3a8d481dd7..fa13a46ce8 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_unfl.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_unfl.S @@ -6,25 +6,25 @@ // fpsp_unfl --- FPSP handler for underflow exception // // Trap disabled results -// For 881/2 compatibility, sw must denormalize the intermediate -// result, then store the result. Denormalization is accomplished -// by taking the intermediate result (which is always normalized) and -// shifting the mantissa right while incrementing the exponent until -// it is equal to the denormalized exponent for the destination -// format. After denormalization, the result is rounded to the +// For 881/2 compatibility, sw must denormalize the intermediate +// result, then store the result. Denormalization is accomplished +// by taking the intermediate result (which is always normalized) and +// shifting the mantissa right while incrementing the exponent until +// it is equal to the denormalized exponent for the destination +// format. After denormalization, the result is rounded to the // destination format. -// +// // Trap enabled results -// All trap disabled code applies. In addition the exceptional -// operand needs to made available to the user with a bias of $6000 +// All trap disabled code applies. In addition the exceptional +// operand needs to made available to the user with a bias of $6000 // added to the exponent. // // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_UNFL: //idnt 2,1 | Motorola 040 Floating Point Software Package @@ -93,7 +93,7 @@ ck_inex: // // Inexact enabled and reported, and we must take an inexact exception -// +// take_inex: btstb #E3,E_BYTE(%a6) beqs no_e3_2 @@ -147,7 +147,7 @@ unf_res: // ;1=sgl, 2=dbl // ;we need the RND_PREC in the // ;upper word for round - movew #0,-(%a7) + movew #0,-(%a7) movew %d0,-(%a7) //copy RND_PREC to stack // // @@ -201,7 +201,7 @@ unf_cont: // must not corrupt a0 and d0. // // -// Perform Round +// Perform Round // Input: a0 points to input operand // d0{31:29} has guard, round, sticky // d1{01:00} has rounding mode @@ -224,7 +224,7 @@ opc011: bsrl g_dfmtou tstb %d0 beqs ext_opc011 //If extended, do not subtract -// ;If destination format is sgl/dbl, +// ;If destination format is sgl/dbl, tstb LOCAL_HI(%a0) //If rounded result is normal,don't // ;subtract bmis ext_opc011 @@ -259,7 +259,7 @@ ck_sgn: bsetb #neg_bit,FPSR_CC(%a6) // -// Finish. +// Finish. // unf_done: btstb #inex2_bit,FPSR_EXCEPT(%a6) diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_unimp.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_unimp.S index 9bbca88c67..5673f97c16 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_unimp.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_unimp.S @@ -3,14 +3,14 @@ // // x_unimp.sa 3.3 7/1/91 // -// fpsp_unimp --- FPSP handler for unimplemented instruction +// fpsp_unimp --- FPSP handler for unimplemented instruction // exception. // // Invoked when the user program encounters a floating-point // op-code that hardware does not support. Trap vector# 11 // (See table 8-1 MC68030 User's Manual). // -// +// // Note: An fsave for an unimplemented inst. will create a short // fsave stack. // @@ -24,8 +24,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_UNIMP: //idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/c/src/lib/libcpu/m68k/m68040/fpsp/x_unsupp.S b/c/src/lib/libcpu/m68k/m68040/fpsp/x_unsupp.S index d1371d05f3..222872c653 100644 --- a/c/src/lib/libcpu/m68k/m68040/fpsp/x_unsupp.S +++ b/c/src/lib/libcpu/m68k/m68040/fpsp/x_unsupp.S @@ -5,12 +5,12 @@ // // fpsp_unsupp --- FPSP handler for unsupported data type exception // -// Trap vector #55 (See table 8-1 Mc68030 User's manual). +// Trap vector #55 (See table 8-1 Mc68030 User's manual). // Invoked when the user program encounters a data format (packed) that // hardware does not support or a data type (denormalized numbers or un- // normalized numbers). -// Normalizes denorms and unnorms, unpacks packed numbers then stores -// them back into the machine to let the 040 finish the operation. +// Normalizes denorms and unnorms, unpacks packed numbers then stores +// them back into the machine to let the 040 finish the operation. // // Unsupp calls two routines: // 1. get_op - gets the operand(s) @@ -25,8 +25,8 @@ // Copyright (C) Motorola, Inc. 1990 // All Rights Reserved // -// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA -// The copyright notice above does not evidence any +// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA +// The copyright notice above does not evidence any // actual or intended publication of such source code. X_UNSUPP: //idnt 2,1 | Motorola 040 Floating Point Software Package diff --git a/cpukit/score/cpu/bfin/irq.c b/cpukit/score/cpu/bfin/irq.c index d43f39ffa0..eccb03d3d5 100644 --- a/cpukit/score/cpu/bfin/irq.c +++ b/cpukit/score/cpu/bfin/irq.c @@ -10,10 +10,10 @@ * * $Id$ */ - + #if 0 /* this file no longer used */ - + #include <rtems/system.h> #include <rtems/score/cpu.h> #include <rtems/score/isr.h> diff --git a/cpukit/score/cpu/bfin/rtems/score/bfin.h b/cpukit/score/cpu/bfin/rtems/score/bfin.h index 252e5a6cf5..7568205ae7 100644 --- a/cpukit/score/cpu/bfin/rtems/score/bfin.h +++ b/cpukit/score/cpu/bfin/rtems/score/bfin.h @@ -1,6 +1,6 @@ /* bfin.h * - * This file sets up basic CPU dependency settings based on + * This file sets up basic CPU dependency settings based on * compiler settings. For example, it can determine if * floating point is available. This particular implementation * is specified to the Blackfin port. @@ -38,24 +38,24 @@ extern "C" { * that this port supports and which RTEMS CPU model they correspond * to. */ - + /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. */ #if defined(__BFIN__) #define CPU_MODEL_NAME "BF533" #define BF_HAS_FPU 0 #else - + #error "Unsupported CPU Model" - + #endif /* * Define the name of the CPU family. */ - + #define CPU_NAME "BFIN" #ifdef __cplusplus diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h index 3f9df06b16..8cb689db3e 100644 --- a/cpukit/score/cpu/bfin/rtems/score/cpu.h +++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h @@ -5,7 +5,7 @@ /* * This include file contains information pertaining to the Blackfin * processor. - * + * * COPYRIGHT (c) 1989-2006. * On-Line Applications Research Corporation (OAR). * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch> @@ -169,7 +169,7 @@ extern "C" { /** * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? * * Port Specific Information: @@ -196,7 +196,7 @@ extern "C" { * an i387 and wish to leave floating point support out of RTEMS. */ -/** +/** * @def CPU_SOFTWARE_FP * * Does the CPU have no hardware floating point and GCC provides a @@ -204,7 +204,7 @@ extern "C" { * switched? * * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context + * is software implemented floating point that must be context * switched. The determination of whether or not this applies * is very tool specific and the state saved/restored is also * compiler specific. @@ -356,7 +356,7 @@ extern "C" { * * XXX document implementation including references if appropriate */ -#define CPU_STRUCTURE_ALIGNMENT +#define CPU_STRUCTURE_ALIGNMENT /** * @defgroup CPUEndian Processor Dependent Endianness Support @@ -477,18 +477,18 @@ typedef struct { uint32_t register_p3; uint32_t register_p4; - uint32_t register_p5; + uint32_t register_p5; uint32_t register_fp; uint32_t register_sp; - + uint32_t register_l0; uint32_t register_l1; uint32_t register_l2; - uint32_t register_l3; - + uint32_t register_l3; + uint32_t register_rets; - uint32_t imask; + uint32_t imask; } Context_Control; #define _CPU_Context_Get_SP( _context ) \ @@ -511,7 +511,7 @@ typedef struct { * in @ref Context_Control. */ typedef struct { - /** This field is a hint that a port will have a number of integer + /** This field is a hint that a port will have a number of integer * registers that need to be saved when an interrupt occurs or * when a context switch occurs at the end of an ISR. */ @@ -551,14 +551,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_high; @@ -652,7 +652,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * * @note This does not have to be a power of 2 although it should be * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least + * to be a multiple of 2 is because the heap uses the least * significant field of the front and back flags to indicate * that a block is in use or free. So you do not want any odd * length blocks really putting length data in that bit. @@ -729,7 +729,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; { \ asm volatile ("cli %0; csync \n" : "=d" (_level) ); \ } - + /** * @ingroup CPUInterrupt @@ -941,7 +941,7 @@ void _CPU_Context_Initialize( /** * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation * - * This set of routines are used to implement fast searches for + * This set of routines are used to implement fast searches for * the most important ready task. */ @@ -966,7 +966,7 @@ void _CPU_Context_Initialize( /** * @ingroup CPUBitfield * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type + * set in @a _value. @a _value is of CPU dependent type * @a Priority_Bit_map_control. This type may be either 16 or 32 bits * wide although only the 16 least significant bits will be used. * @@ -1009,14 +1009,14 @@ void _CPU_Context_Initialize( if _value > 0x00ff _value >>=8 _number = 8; - + if _value > 0x0000f _value >=8 _number += 4 - + _number += bit_set_table[ _value ] @endverbatim - + * where bit_set_table[ 16 ] has values which indicate the first * bit set * @@ -1089,7 +1089,7 @@ void _CPU_Initialize(void); /** * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the + * This routine installs a "raw" interrupt handler directly into the * processor's vector table. * * @param[in] vector is the vector number @@ -1251,12 +1251,12 @@ static inline uint32_t CPU_swap_u32( ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return( swapped ); } diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h index 4708f37c50..a4c7be9a5e 100644 --- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h @@ -4,7 +4,7 @@ /* * Defines a couple of Macros used in cpu_asm.S - * + * * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. * written by Alain Schaefer <alain.schaefer@easc.ch> * and Antonio Giovanini <antonio@atos.com.br> diff --git a/cpukit/score/cpu/c4x/cpu_asm.S b/cpukit/score/cpu/c4x/cpu_asm.S index 020c3a8d9e..95c2b31290 100644 --- a/cpukit/score/cpu/c4x/cpu_asm.S +++ b/cpukit/score/cpu/c4x/cpu_asm.S @@ -70,7 +70,7 @@ * ) * * TMS320C3x General-Purpose Applications User's Guide, section 2.4 - * (p 2-11 and following), Context Switching in Interrupts and + * (p 2-11 and following), Context Switching in Interrupts and * Subroutines states that "If the program is in a subroutine, it * must preserve the dedicated C registers as follows:" * @@ -136,7 +136,7 @@ _local_restore: * efficient manner. It may simply be a label in _CPU_Context_switch. * * NOTE: May be unnecessary to reload some registers. - * + * * void _CPU_Context_restore( * Context_Control *new_context * ) @@ -191,10 +191,10 @@ SYM(_CPU_Context_restore): * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) * restore stack * #endif - * + * * if ( !_Context_Switch_necessary ) * goto the label "exit interrupt (simple case)" - * + * * if ( !_ISR_Signals_to_thread_executing ) * _ISR_Signals_to_thread_executing = FALSE; * goto the label "exit interrupt (simple case)" @@ -211,7 +211,7 @@ SYM(_CPU_Context_restore): .global SYM(_ISR_Handler_save_registers) SYM(_ISR_Handler_save_registers): - ; no push st because it is already pushed + ; no push st because it is already pushed ; no push ar2 because it is already pushed and vector number loaded push ar0 push ar1 @@ -279,7 +279,7 @@ SYM(_ISR_Handler_save_registers): ; no pop r4 because other part of register is in basic context popf r4 pop r4 - popf r3 + popf r3 pop r3 popf r2 pop r2 @@ -287,7 +287,7 @@ SYM(_ISR_Handler_save_registers): pop r1 popf r0 pop r0 - + pop bk pop rc pop re @@ -305,9 +305,9 @@ SYM(_ISR_Handler_save_registers): * Prologues so we can know the vector number. Generated by this script: * * i=0 - * while test $i -lt 64 + * while test $i -lt 64 * do - * + * * printf "\t.global\tSYM(rtems_irq_prologue_%X)\n" $i * printf "SYM(rtems_irq_prologue_%X):\n" $i * printf "\tpush\tst\n" @@ -316,7 +316,7 @@ SYM(_ISR_Handler_save_registers): * printf "\tbr\tSYM(_ISR_Handler_save_registers)\n" * printf "\n" * i=`expr $i + 1` - * + * * done */ diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c index e9c2dc64e0..d5300e1006 100644 --- a/cpukit/score/cpu/i386/cpu.c +++ b/cpukit/score/cpu/i386/cpu.c @@ -76,7 +76,7 @@ void _CPU_Initialize(void) * As a courtesy, we double-check here but it * may be too late (which is also why we don't * enable SSE here). - */ + */ { uint32_t cr4; __asm__ __volatile__("mov %%cr4, %0":"=r"(cr4)); diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h index 77e6c6bff3..731fcd73c7 100644 --- a/cpukit/score/cpu/i386/rtems/score/cpu.h +++ b/cpukit/score/cpu/i386/rtems/score/cpu.h @@ -360,7 +360,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; uint32_t _CPU_ISR_Get_level( void ); -/* Make sure interrupt stack has space for ISR +/* Make sure interrupt stack has space for ISR * 'vector' arg at the top and that it is aligned * properly. */ @@ -391,7 +391,7 @@ uint32_t _CPU_ISR_Get_level( void ); /* * Stack alignment note: - * + * * We want the stack to look to the '_entry_point' routine * like an ordinary stack frame as if '_entry_point' was * called from C-code. @@ -405,7 +405,7 @@ uint32_t _CPU_ISR_Get_level( void ); * ------ (alignment boundary) * SP-> return_addr return here when _entry_point returns which (never happens) * - * + * * Hence we must initialize the stack as follows * * [arg1 ]: n/a diff --git a/cpukit/score/cpu/i386/sse_test.c b/cpukit/score/cpu/i386/sse_test.c index a6e0fbd6bd..e54b77830b 100644 --- a/cpukit/score/cpu/i386/sse_test.c +++ b/cpukit/score/cpu/i386/sse_test.c @@ -1,18 +1,18 @@ /* $Id$ */ -/* +/* * Authorship * ---------- * This software was created by * Till Straumann <strauman@slac.stanford.edu>, 2009, * Stanford Linear Accelerator Center, Stanford University. - * + * * Acknowledgement of sponsorship * ------------------------------ * This software was produced by * the Stanford Linear Accelerator Center, Stanford University, * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * + * * Government disclaimer of liability * ---------------------------------- * Neither the United States nor the United States Department of Energy, @@ -21,18 +21,18 @@ * completeness, or usefulness of any data, apparatus, product, or process * disclosed, or represents that its use would not infringe privately owned * rights. - * + * * Stanford disclaimer of liability * -------------------------------- * Stanford University makes no representations or warranties, express or * implied, nor assumes any liability for the use of this software. - * + * * Stanford disclaimer of copyright * -------------------------------- * Stanford University, owner of the copyright, hereby disclaims its * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * + * freely use it for any purpose without restriction. + * * Maintenance of notices * ---------------------- * In the interest of clarity regarding the origin and status of this @@ -41,10 +41,10 @@ * or distributed by the recipient and are to be affixed to any copy of * software made or distributed by the recipient that contains a copy or * derivative of this software. - * + * * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 */ - + /* Code for testing FPU/SSE context save/restore across exceptions * (including interrupts). @@ -60,7 +60,7 @@ * 2b loads context from 1) into FPU/SSE * 2c raises an exception or interrupt * - * * (2d save FPU/SSE context after irq/exception returns to + * * (2d save FPU/SSE context after irq/exception returns to * separate area for verification * 2e reload original FP/SSE context.) * @@ -228,7 +228,7 @@ fp_ld(Context_Control_sse *p_ctxt, int i) #define SSECLOBBER \ "xmm0","xmm1","xmm2","xmm3", \ - "xmm4","xmm5","xmm6","xmm7" + "xmm4","xmm5","xmm6","xmm7" static void sse_clobber(uint32_t x) @@ -308,7 +308,7 @@ stor_ctxt(Context_Control_sse *p_ctxt) rval = 1; \ if ( !quiet ) \ fprintf(stderr,#fld" mismatch ("fmt" != "fmt")\n",a->fld, b->fld); \ - } + } #define FLTCMP(i) \ do { \ @@ -664,7 +664,7 @@ int errs = 0; /* Test if FP/SSE context is saved/restored across an exception */ sse_test_ohdl = _currentExcHandler; - _currentExcHandler = sse_test_ehdl; + _currentExcHandler = sse_test_ehdl; if ( (sse_tests & SSE_TEST_FPU_EXC) ) { if ( (st = exc_raise(FP_EXC)) ) { diff --git a/cpukit/score/cpu/lm32/cpu.c b/cpukit/score/cpu/lm32/cpu.c index 825a70f96b..b796b6a1e6 100644 --- a/cpukit/score/cpu/lm32/cpu.c +++ b/cpukit/score/cpu/lm32/cpu.c @@ -50,7 +50,7 @@ void _CPU_Initialize(void) * * XXX document implementation including references if appropriate */ - + uint32_t _CPU_ISR_Get_level( void ) { /* @@ -68,7 +68,7 @@ uint32_t _CPU_ISR_Get_level( void ) * * XXX document implementation including references if appropriate */ - + void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, diff --git a/cpukit/score/cpu/lm32/cpu_asm.S b/cpukit/score/cpu/lm32/cpu_asm.S index 02e1f6928a..bfed8cb1af 100644 --- a/cpukit/score/cpu/lm32/cpu_asm.S +++ b/cpukit/score/cpu/lm32/cpu_asm.S @@ -108,7 +108,7 @@ _CPU_Context_switch_restore: _CPU_Context_restore: mv r2, r1 bi _CPU_Context_switch_restore - + /* void _ISR_Handler() * * This routine provides the RTEMS interrupt management. @@ -125,7 +125,7 @@ _CPU_Context_restore: * handles interrupt nesting, software interrupt stack setup etc and * finally calls the user ISR. * At the end the saved registers are restored. - * + * */ .globl _ISR_Handler @@ -180,18 +180,18 @@ found_irq: mvhi r3, hi(__ISR_Handler) ori r3, r3, lo(__ISR_Handler) call r3 - + exit_isr: /* Restore the saved registers */ lw r1, (sp+4) - lw r2, (sp+8) - lw r3, (sp+12) - lw r4, (sp+16) - lw r5, (sp+20) - lw r6, (sp+24) - lw r7, (sp+28) - lw r8, (sp+32) - lw r9, (sp+36) + lw r2, (sp+8) + lw r3, (sp+12) + lw r4, (sp+16) + lw r5, (sp+20) + lw r6, (sp+24) + lw r7, (sp+28) + lw r8, (sp+32) + lw r9, (sp+36) lw r10, (sp+40) lw ra, (sp+44) lw ea, (sp+48) diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h index f6b6a9210c..41c30ca099 100644 --- a/cpukit/score/cpu/lm32/rtems/score/cpu.h +++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h @@ -13,7 +13,7 @@ * * + Anywhere there is an XXX, it should be replaced * with information about the CPU family being ported to. - * + * * + At the end of each comment section, there is a heading which * says "Port Specific Information:". When porting to RTEMS, * add CPU family specific information in this section @@ -168,7 +168,7 @@ extern "C" { /** * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? * * Port Specific Information: @@ -195,7 +195,7 @@ extern "C" { * an i387 and wish to leave floating point support out of RTEMS. */ -/** +/** * @def CPU_SOFTWARE_FP * * Does the CPU have no hardware floating point and GCC provides a @@ -203,7 +203,7 @@ extern "C" { * switched? * * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context + * is software implemented floating point that must be context * switched. The determination of whether or not this applies * is very tool specific and the state saved/restored is also * compiler specific. @@ -491,7 +491,7 @@ typedef struct { * This macro returns the stack pointer associated with @a _context. * * @param[in] _context is the thread context area to access - * + * * @return This method returns the stack pointer. */ #define _CPU_Context_Get_SP( _context ) \ @@ -562,14 +562,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_high; @@ -663,7 +663,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * * @note This does not have to be a power of 2 although it should be * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least + * to be a multiple of 2 is because the heap uses the least * significant field of the front and back flags to indicate * that a block is in use or free. So you do not want any odd * length blocks really putting length data in that bit. @@ -945,7 +945,7 @@ uint32_t _CPU_ISR_Get_level( void ); /** * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation * - * This set of routines are used to implement fast searches for + * This set of routines are used to implement fast searches for * the most important ready task. */ @@ -970,7 +970,7 @@ uint32_t _CPU_ISR_Get_level( void ); /** * @ingroup CPUBitfield * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type + * set in @a _value. @a _value is of CPU dependent type * @a Priority_Bit_map_control. This type may be either 16 or 32 bits * wide although only the 16 least significant bits will be used. * @@ -1013,14 +1013,14 @@ uint32_t _CPU_ISR_Get_level( void ); if _value > 0x00ff _value >>=8 _number = 8; - + if _value > 0x0000f _value >=8 _number += 4 - + _number += bit_set_table[ _value ] @endverbatim - + * where bit_set_table[ 16 ] has values which indicate the first * bit set * @@ -1092,7 +1092,7 @@ void _CPU_Initialize(void); /** * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the + * This routine installs a "raw" interrupt handler directly into the * processor's vector table. * * @param[in] vector is the vector number @@ -1254,12 +1254,12 @@ static inline uint32_t CPU_swap_u32( ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return swapped; } diff --git a/cpukit/score/cpu/lm32/rtems/score/lm32.h b/cpukit/score/cpu/lm32/rtems/score/lm32.h index c8327f47a9..06ad7eb398 100644 --- a/cpukit/score/cpu/lm32/rtems/score/lm32.h +++ b/cpukit/score/cpu/lm32/rtems/score/lm32.h @@ -1,6 +1,6 @@ /* lm32.h * - * This file sets up basic CPU dependency settings based on + * This file sets up basic CPU dependency settings based on * compiler settings. For example, it can determine if * floating point is available. This particular implementation * is specified to the NO CPU port. @@ -37,25 +37,25 @@ extern "C" { * that this port supports and which RTEMS CPU model they correspond * to. */ - + #if defined(rtems_multilib) /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. */ #define CPU_MODEL_NAME "rtems_multilib" #define LM32_HAS_FPU 0 #elif defined(__lm32__) - + #define CPU_MODEL_NAME "lm32" #define LM32_HAS_FPU 0 - + #else - + #error "Unsupported CPU Model" - + #endif /* |