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| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-05-15 15:10:38 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-05-15 15:10:38 +0000 |
| commit | 42bf1b9f13d9269d9a98de4bdc1a11365865ef42 (patch) | |
| tree | b0ea837f63ea5ac5d6d04473f492d6329a3ee450 /c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h | |
| parent | 2008-05-14 Till Straumann <strauman@slac.stanford.edu> (diff) | |
| download | rtems-42bf1b9f13d9269d9a98de4bdc1a11365865ef42.tar.bz2 | |
adapted gen83xx to new board
Diffstat (limited to 'c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h')
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h index ee06c2fee7..459aaee1cc 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h @@ -1110,6 +1110,12 @@ extern m83xxRegisters_t mpc83xx; #define BR7_OFF 0x05038 #define OR7_OFF 0x0503C +#define MRPTR_OFF 0x05084 +#define LSDMR_OFF 0x05094 +#define LSRT_OFF 0x050A4 +#define LCRR_OFF 0x050d4 + + #define CS0_BNDS_OFF 0x02000 #define CS1_BNDS_OFF 0x02008 #define CS2_BNDS_OFF 0x02010 @@ -1127,9 +1133,25 @@ extern m83xxRegisters_t mpc83xx; #define DDR_SDRAM_MODE_OFF 0x02118 #define DDR_SDRAM_MODE_2_OFF 0x0211C #define DDR_SDRAM_MD_CNTL_OFF 0x02120 -#define DDR_SDRAM_MD_ITVL_OFF 0x02124 +#define DDR_SDRAM_INTERVAL_OFF 0x02124 +#define DDR_SDRAM_DATA_INIT_OFF 0x02128 +#define DDRCDR_OFF 0x0012C #define DDR_SDRAM_CLK_CNTL_OFF 0x02130 #define DDR_SDRAM_INIT_ADDR_OFF 0x02148 +#define DDR_ERR_DISABLE_OFF 0x02E44 + +/* + * some bits in DDR_SDRAM_CFG register + */ +#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0)) /* enable memory */ +/* + * bits in DDR_SDRAM_CFG_2 register + */ +#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh */ +#define DDR_SDRAM_CFG_2_D_SR_IE (1 << (31- 1)) /* self refresh interrupt en */ +#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS (1 << (31- 2)) /* DLL reset disable */ +#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF (1 << (31- 5)) /* use diff. DQS */ +#define DDR_SDRAM_CFG_2_D_INIT (1 << (31-27)) /* Init DRAM with pattern */ /* * bits in reset configuration words/registers |