diff options
| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-05-15 15:10:38 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2008-05-15 15:10:38 +0000 |
| commit | 42bf1b9f13d9269d9a98de4bdc1a11365865ef42 (patch) | |
| tree | b0ea837f63ea5ac5d6d04473f492d6329a3ee450 /c | |
| parent | 2008-05-14 Till Straumann <strauman@slac.stanford.edu> (diff) | |
| download | rtems-42bf1b9f13d9269d9a98de4bdc1a11365865ef42.tar.bz2 | |
adapted gen83xx to new board
Diffstat (limited to 'c')
41 files changed, 1598 insertions, 610 deletions
diff --git a/c/src/ChangeLog b/c/src/ChangeLog index 746825b798..7f6a58b61e 100644 --- a/c/src/ChangeLog +++ b/c/src/ChangeLog @@ -1,3 +1,12 @@ +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * libchip/i2c/spi-flash-m25p40.c, libchip/i2c/spi-flash-m25p40.h, + * libchip/i2c/spi-fram-fm25l256.c, libchip/i2c/spi-fram-fm25l256.h, + * libchip/i2c/spi-memdrv.c, libchip/i2c/spi-memdrv.h, + * libchip/Makefile.am: + derived a generic spi memory driver from spi-flash-m25p40, + added descriptor for fram fm25l256 + 2008-05-07 Till Straumann <strauman@slac.stanford.edu> PR 649/bsps diff --git a/c/src/lib/libbsp/arm/edb7312/preinstall.am b/c/src/lib/libbsp/arm/edb7312/preinstall.am index 0ec4ca8354..adc827bee9 100644 --- a/c/src/lib/libbsp/arm/edb7312/preinstall.am +++ b/c/src/lib/libbsp/arm/edb7312/preinstall.am @@ -68,3 +68,7 @@ $(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h +$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h + diff --git a/c/src/lib/libbsp/arm/nds/preinstall.am b/c/src/lib/libbsp/arm/nds/preinstall.am index 8a161c31b8..f349d937ce 100644 --- a/c/src/lib/libbsp/arm/nds/preinstall.am +++ b/c/src/lib/libbsp/arm/nds/preinstall.am @@ -1,6 +1,4 @@ -## -## $Id$ -## +## Automatically generated by ampolish3 - Do not edit if AMPOLISH3 $(srcdir)/preinstall.am: Makefile.am @@ -38,6 +36,10 @@ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h +$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h @@ -46,10 +48,6 @@ $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h -$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h - $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) @@ -58,6 +56,184 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds +$(PROJECT_INCLUDE)/rtems/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems + @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp) + +$(PROJECT_INCLUDE)/rtems/fb.h: fb/fb.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/fb.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/fb.h + +$(PROJECT_INCLUDE)/rtems/touchscreen.h: touchscreen/touchscreen.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/touchscreen.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/touchscreen.h + +$(PROJECT_INCLUDE)/rtems/sound.h: sound/sound.h $(PROJECT_INCLUDE)/rtems/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/sound.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/sound.h + $(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h + +$(PROJECT_INCLUDE)/libnds/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds + @: > $(PROJECT_INCLUDE)/libnds/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/$(dirstamp) + +$(PROJECT_INCLUDE)/libnds/gbfs.h: libnds/include/gbfs.h $(PROJECT_INCLUDE)/libnds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/gbfs.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/gbfs.h + +$(PROJECT_INCLUDE)/libnds/nds.h: libnds/include/nds.h $(PROJECT_INCLUDE)/libnds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds.h + +$(PROJECT_INCLUDE)/libnds/nds/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds + @: > $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + +$(PROJECT_INCLUDE)/libnds/nds/memory.h: libnds/include/nds/memory.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/memory.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/memory.h + +$(PROJECT_INCLUDE)/libnds/nds/system.h: libnds/include/nds/system.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/system.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/system.h + +$(PROJECT_INCLUDE)/libnds/nds/bios.h: libnds/include/nds/bios.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/bios.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/bios.h + +$(PROJECT_INCLUDE)/libnds/nds/registers_alt.h: libnds/include/nds/registers_alt.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h + +$(PROJECT_INCLUDE)/libnds/nds/interrupts.h: libnds/include/nds/interrupts.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/interrupts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/interrupts.h + +$(PROJECT_INCLUDE)/libnds/nds/card.h: libnds/include/nds/card.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/card.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/card.h + +$(PROJECT_INCLUDE)/libnds/nds/ipc.h: libnds/include/nds/ipc.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/ipc.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/ipc.h + +$(PROJECT_INCLUDE)/libnds/nds/timers.h: libnds/include/nds/timers.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/timers.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/timers.h + +$(PROJECT_INCLUDE)/libnds/nds/dma.h: libnds/include/nds/dma.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/dma.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/dma.h + +$(PROJECT_INCLUDE)/libnds/nds/reload.h: libnds/include/nds/reload.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/reload.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/reload.h + +$(PROJECT_INCLUDE)/libnds/nds/jtypes.h: libnds/include/nds/jtypes.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/jtypes.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/jtypes.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm9 + @: > $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + +$(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h: libnds/include/nds/arm9/ndsmotion.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h: libnds/include/nds/arm9/pcx.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/input.h: libnds/include/nds/arm9/input.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/math.h: libnds/include/nds/arm9/math.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/console.h: libnds/include/nds/arm9/console.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h: libnds/include/nds/arm9/sprite.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h: libnds/include/nds/arm9/videoGL.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h: libnds/include/nds/arm9/cache.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/image.h: libnds/include/nds/arm9/image.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h: libnds/include/nds/arm9/trig_lut.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/video.h: libnds/include/nds/arm9/video.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h: libnds/include/nds/arm9/exceptions.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h: libnds/include/nds/arm9/rumble.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/background.h: libnds/include/nds/arm9/background.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h: libnds/include/nds/arm9/boxtest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h: libnds/include/nds/arm9/postest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h + +$(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h: libnds/include/nds/arm9/sound.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h + +$(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm7 + @: > $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp) + +$(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h: libnds/include/nds/arm7/serial.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h + +$(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h: libnds/include/nds/arm7/audio.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h + +$(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h: libnds/include/nds/arm7/clock.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h + +$(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h: libnds/include/nds/arm7/touch.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h + +$(PROJECT_LIB)/coproc.bin: coproc.bin $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/coproc.bin +TMPINSTALL_FILES += $(PROJECT_LIB)/coproc.bin + diff --git a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am index d955cf2ae1..605316427f 100644 --- a/c/src/lib/libbsp/bfin/eZKit533/preinstall.am +++ b/c/src/lib/libbsp/bfin/eZKit533/preinstall.am @@ -36,10 +36,6 @@ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h -$(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h - $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h diff --git a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog index 6b618fadac..fe09aa673e 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog +++ b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog @@ -1,3 +1,36 @@ +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * network/network.c, start/start.S: + add support for different board + +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * irq/ipic.c: + make sure, that the masking operations in + ICTL and MSR are executed in order + +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * include/bsp.h, startup/bspstart.c, + * console/console.c, console/config.c: + derived module input frequencies from internal bus clock during + start time + +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * spi/spi_init.c: + added base frequency into softc structure, added fm25l256 driver + +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * i2c/i2c_init.c: + added base frequency into softc structure + +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * include/bsp.h, include/hwreg_vals.h, ./Makefile.am: + moved HW register settings from bsp.h to hwreg_vals.h + 2008-05-14 Joel Sherrill <joel.sherrill@OARcorp.com> * Makefile.am: Rework to avoid .rel files. diff --git a/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am b/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am index 1c60142d68..08e6e3ed71 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am @@ -45,7 +45,9 @@ startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \ pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c include_bsp_HEADERS = ./irq/irq.h \ + ./include/hwreg_vals.h \ ../../powerpc/shared/vectors/vectors.h + vectors_SOURCES = ../../powerpc/shared/vectors/vectors.h \ ../../powerpc/shared/vectors/vectors_init.c \ ../../powerpc/shared/vectors/vectors.S diff --git a/c/src/lib/libbsp/powerpc/gen83xx/console/config.c b/c/src/lib/libbsp/powerpc/gen83xx/console/config.c index 91e7b4ee56..224b11eb8d 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/console/config.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/console/config.c @@ -105,10 +105,11 @@ console_tbl Console_Port_Tbl[] = { Write_ns16550_register, /* setRegister */ NULL, /* getData */ NULL, /* setData */ - BSP_CSB_CLK_FRQ, /* ulClock */ + 0, /* ulClock (filled in init) */ 0 /* ulIntVector */ - }, - { + } +#if BSP_USE_UART2 + ,{ "/dev/ttyS1", /* sDeviceName */ SERIAL_NS16550, /* deviceType */ NS16550_FUNCTIONS, /* pDeviceFns */ @@ -124,8 +125,9 @@ console_tbl Console_Port_Tbl[] = { Write_ns16550_register, /* setRegister */ NULL, /* getData */ NULL, /* setData */ - BSP_CSB_CLK_FRQ, /* ulClock */ + 0, /* ulClock (filled in init) */ 0 /* ulIntVector */ } +#endif }; diff --git a/c/src/lib/libbsp/powerpc/gen83xx/console/console.c b/c/src/lib/libbsp/powerpc/gen83xx/console/console.c index b63733ee20..8d2cc8ab1d 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/console/console.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/console/console.c @@ -173,6 +173,11 @@ rtems_device_driver console_initialize( minor++) { /* + * transfer the real internal bus frequency into the + * console port table + */ + Console_Port_Tbl[minor].ulClock = BSP_bus_frequency; + /* * First perform the configuration dependant probe, then the * device dependant probe */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c b/c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c index 868cf0c8c5..173a12f53a 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c @@ -31,7 +31,8 @@ static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = { { /* our private fields */ reg_ptr: &mpc83xx.i2c[0], initialized: FALSE, - irq_number: BSP_IPIC_IRQ_I2C1 + irq_number : BSP_IPIC_IRQ_I2C1, + base_frq : 0 /* will be set during initiailization */ } }, /* second channel */ @@ -43,7 +44,8 @@ static mpc83xx_i2c_desc_t mpc83xx_i2c_bus_tbl[2] = { { /* our private fields */ reg_ptr: &mpc83xx.i2c[1], initialized: FALSE, - irq_number: BSP_IPIC_IRQ_I2C2 + irq_number : BSP_IPIC_IRQ_I2C2, + base_frq : 0 /* will be set during initiailization */ } } }; @@ -81,6 +83,19 @@ rtems_status_code bsp_register_i2c rtems_libi2c_initialize (); /* + * update input frequency of I2c modules into descriptor + */ + /* + * I2C1 is clocked with TSEC 1 + */ + if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) { + mpc83xx_i2c_bus_tbl[0].softc.base_frq = + (BSP_bus_frequency + /((mpc83xx.clk.sccr >> (31-1)) & 0x03)); + } + + mpc83xx_i2c_bus_tbl[1].softc.base_frq = BSP_bus_frequency; + /* * register first I2C bus */ ret_code = rtems_libi2c_register_bus("/dev/i2c1", @@ -98,6 +113,7 @@ rtems_status_code bsp_register_i2c return -ret_code; } i2c2_busno = ret_code; + /* * register EEPROM to bus 1, Address 0x50 */ @@ -107,6 +123,7 @@ rtems_status_code bsp_register_i2c if (ret_code < 0) { return -ret_code; } + /* * FIXME: register RTC driver, when available */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h b/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h index 28a5adb1b0..fa97939d53 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h @@ -20,166 +20,7 @@ #ifndef __GEN83xx_BSP_h #define __GEN83xx_BSP_h -/* - * distinguish board characteristics - */ -/* - * for Freescale MPC8349 EAMDS - */ -#if defined(MPC8349EAMDS) -/* - * two DUART channels supported - */ -#define GEN83xx_DUART_AVAIL_MASK 0x03 - -/* we need the low level initialization in start.S*/ -#define NEED_LOW_LEVEL_INIT -/* - * clocking infos - */ -#define BSP_CLKIN_FRQ 66000000L -#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */ - -/* - * Reset configuration words - */ -#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ - RCWLR_DDRCM_1_1 | \ - RCWLR_SPMF(4) | \ - RCWLR_COREPLL(4)) - -#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ - RCWHR_PCI_32 | \ - RCWHR_PCI1ARB_EN | \ - RCWHR_PCI2ARB_EN | \ - RCWHR_CORE_EN | \ - RCWHR_BMS_LOW | \ - RCWHR_BOOTSEQ_NONE | \ - RCWHR_SW_DIS | \ - RCWHR_ROMLOC_LB16 | \ - RCWHR_TSEC1M_GMII | \ - RCWHR_TSEC2M_GMII | \ - RCWHR_ENDIAN_BIG | \ - RCWHR_LALE_NORM | \ - RCWHR_LDP_PAR) -/* - * for JPK HSC_CM01 - */ -#elif defined(HSC_CM01) -/* - * one DUART channel (UART1) supported - */ -#define GEN83xx_DUART_AVAIL_MASK 0x01 - -/* we need the low level initialization in start.S*/ -#define NEED_LOW_LEVEL_INIT -/* - * clocking infos - */ -#define BSP_CLKIN_FRQ 66000000L -#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */ - -/* - * Reset configuration words - */ -#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ - RCWLR_DDRCM_1_1 | \ - RCWLR_SPMF(4) | \ - RCWLR_COREPLL(4)) - -#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ - RCWHR_PCI_32 | \ - RCWHR_PCI1ARB_EN | \ - RCWHR_PCI2ARB_EN | \ - RCWHR_CORE_EN | \ - RCWHR_BMS_LOW | \ - RCWHR_BOOTSEQ_NONE | \ - RCWHR_SW_DIS | \ - RCWHR_ROMLOC_LB16 | \ - RCWHR_TSEC1M_RGMII | \ - RCWHR_TSEC2M_GMII | \ - RCWHR_ENDIAN_BIG | \ - RCWHR_LALE_NORM | \ - RCWHR_LDP_PAR) -#else -#error "board type not defined" -#endif - -/* - * for JPK HSC_CM01 and freescale MPC8349EAMDS - */ -#if defined(MPC8349EAMDS) || defined(HSC_CM01) -/* - * address range definitions - */ -/* ROM definitions (8 MB, mirrored multiple times) */ -#define ROM_START 0xFE000000 -#define ROM_SIZE 0x02000000 -#define ROM_END (ROM_START+ROM_SIZE-1) -#define BOOT_START ROM_START -#define BOOT_END ROM_END - -/* SDRAM definitions (256 MB) */ -#define RAM_START 0x00000000 -#define RAM_SIZE 0x10000000 -#define RAM_END (RAM_START+RAM_SIZE-1) - - -/* working internal memory map base address */ -#define IMMRBAR 0xE0000000 - -/* - * working values for various registers, used in start/start.S - */ -/* - * Local Access Windows - * FIXME: decode bit settings - */ -#define LBLAWBAR0_VAL 0xFE000000 -#define LBLAWAR0_VAL 0x80000016 -#define LBLAWBAR1_VAL 0xF8000000 -#define LBLAWAR1_VAL 0x8000000E -#define LBLAWBAR2_VAL 0xF0000000 -#define LBLAWAR2_VAL 0x80000019 -#define DDRLAWBAR0_VAL 0x00000000 -#define DDRLAWAR0_VAL 0x8000001B -/* - * Local Bus (Memory) Controller - * FIXME: decode bit settings - */ -#define BR0_VAL 0xFE001001 -#define OR0_VAL 0xFF806FF7 -#define BR1_VAL 0xF8000801 -#define OR1_VAL 0xFFFFE8F0 -#define BR2_VAL 0xF0001861 -#define OR2_VAL 0xFC006901 -/* - * SDRAM registers - * FIXME: decode bit settings - */ -#define MRPTR_VAL 0x20000000 -#define LSRT_VAL 0x32000000 -#define LSDMR_VAL 0x4062D733 -#define LCRR_VAL 0x80000004 - -/* - * DDR-SDRAM registers - * FIXME: decode bit settings - */ -#define CS2_BNDS_VAL 0x00000007 -#define CS3_BNDS_VAL 0x0008000F -#define CS2_CONFIG_VAL 0x80000101 -#define CS3_CONFIG_VAL 0x80000101 -#define TIMING_CFG_1_VAL 0x36333321 -#define TIMING_CFG_2_VAL 0x00000800 -#define DDR_SDRAM_CFG_VAL 0xC2000000 -#define DDR_SDRAM_MODE_VAL 0x00000022 -#define DDR_SDRAM_INTTVL_VAL 0x045B0100 -#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 - -#else -#error "board type not defined" -#endif +#include <bsp/hwreg_vals.h> #ifndef ASM @@ -246,6 +87,12 @@ rtems_status_code bsp_register_spi(void); #endif #define PRINTK_MINOR BSP_UART1_MINOR +#if defined(MPC8249EAMDS) +#define BSP_USE_UART2 TRUE +#else +#define BSP_USE_UART2 FALSE +#endif + #define SINGLE_CHAR_MODE #define UARTS_USE_TERMIOS_INT 1 @@ -260,9 +107,10 @@ rtems_status_code bsp_register_spi(void); * floating point math. * (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0)) */ -#define BSP_CSB_CLK_FRQ (BSP_CLKIN_FRQ * BSP_SYSPLL_MF) + +extern unsigned int BSP_bus_frequency; #define BSP_Convert_decrementer( _value ) \ - (int) (((_value) * 4000) / (BSP_CSB_CLK_FRQ/10000)) + (int) (((_value) * 4000) / (BSP_bus_frequency/10000)) /* * Network driver configuration @@ -274,6 +122,7 @@ extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching); #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" +#if defined(MPC8349EAMDS) /* * i2c EEPROM device name */ @@ -285,6 +134,21 @@ extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching); */ #define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash" #define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash" +#endif /* defined(MPC8349EAMDS) */ + +#if defined(HSC_CM01) +/* + * i2c EEPROM device name + */ +#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" +#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" + +/* + * SPI FRAM device name + */ +#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram" +#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram" +#endif /* defined(HSC_CM01) */ #ifdef __cplusplus } diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h new file mode 100644 index 0000000000..ab503aa4cc --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @@ -0,0 +1,268 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + +#ifndef __GEN83xx_HWREG_VALS_h +#define __GEN83xx_HWREG_VALS_h + +#include <mpc83xx/mpc83xx.h> +/* + * distinguish board characteristics + */ +#if defined(MPC8349EAMDS) +/* + * for Freescale MPC8349 EAMDS + */ +/* + * two DUART channels supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x03 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 66000000L +#define RCFG_SYSPLL_MF 4 +#define RCFG_COREPLL_MF 4 + +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ + RCWLR_DDRCM_1_1 | \ + RCWLR_SPMF(RCFG_SYSPLL_MF) | \ + RCWLR_COREPLL(RCFG_COREPLL_MF)) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_EN | \ + RCWHR_PCI2ARB_EN | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + RCWHR_ROMLOC_LB16 | \ + RCWHR_TSEC1M_GMII | \ + RCWHR_TSEC2M_GMII | \ + RCWHR_ENDIAN_BIG | \ + RCWHR_LALE_NORM | \ + RCWHR_LDP_PAR) +#elif defined(HSC_CM01) +/* + * for JPK HSC_CM01 + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 30000000L +#define RCFG_SYSPLL_MF 11 +#define RCFG_COREPLL_MF 4 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ + RCWLR_DDRCM_1_1 | \ + RCWLR_SPMF(RCFG_SYSPLL_MF) | \ + RCWLR_COREPLL(RCFG_COREPLL_MF)) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_EN | \ + RCWHR_PCI2ARB_EN | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + RCWHR_ROMLOC_LB16 | \ + RCWHR_TSEC1M_RGMII | \ + RCWHR_TSEC2M_GMII | \ + RCWHR_ENDIAN_BIG | \ + RCWHR_LALE_NORM | \ + RCWHR_LDP_PAR) +#else +#error "board type not defined" +#endif + +#if defined(MPC8349EAMDS) +/************************** + * for Freescale MPC8349EAMDS + */ +/* + * address range definitions + */ +/* ROM definitions (8 MB, mirrored multiple times) */ +#define ROM_START 0xFE000000 +#define ROM_SIZE 0x02000000 +#define ROM_END (ROM_START+ROM_SIZE-1) +#define BOOT_START ROM_START +#define BOOT_END ROM_END + +/* SDRAM definitions (256 MB) */ +#define RAM_START 0x00000000 +#define RAM_SIZE 0x10000000 +#define RAM_END (RAM_START+RAM_SIZE-1) + + +/* working internal memory map base address */ +#define IMMRBAR 0xE0000000 + +/* + * working values for various registers, used in start/start.S + */ +/* + * Local Access Windows + * FIXME: decode bit settings + */ +#define LBLAWBAR0_VAL 0xFE000000 +#define LBLAWAR0_VAL 0x80000016 +#define LBLAWBAR1_VAL 0xF8000000 +#define LBLAWAR1_VAL 0x8000000E +#define LBLAWBAR2_VAL 0xF0000000 +#define LBLAWAR2_VAL 0x80000019 +#define DDRLAWBAR0_VAL 0x00000000 +#define DDRLAWAR0_VAL 0x8000001B +/* + * Local Bus (Memory) Controller + * FIXME: decode bit settings + */ +#define BR0_VAL 0xFE001001 +#define OR0_VAL 0xFF806FF7 +#define BR1_VAL 0xF8000801 +#define OR1_VAL 0xFFFFE8F0 +#define BR2_VAL 0xF0001861 +#define OR2_VAL 0xFC006901 +/* + * SDRAM registers + * FIXME: decode bit settings + */ +#define MRPTR_VAL 0x20000000 +#define LSRT_VAL 0x32000000 +#define LSDMR_VAL 0x4062D733 +#define LCRR_VAL 0x80000004 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define CS2_BNDS_VAL 0x00000007 +#define CS3_BNDS_VAL 0x0008000F +#define CS2_CONFIG_VAL 0x80000101 +#define CS3_CONFIG_VAL 0x80000101 +#define TIMING_CFG_1_VAL 0x36333321 +#define TIMING_CFG_2_VAL 0x00000800 +#define DDR_SDRAM_CFG_VAL 0xC2000000 +#define DDR_SDRAM_MODE_VAL 0x00000022 +#define DDR_SDRAM_INTTVL_VAL 0x045B0100 +#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 + +#elif defined(HSC_CM01) +/************************** + * for JPK HSC_CM01 + */ +/* + * address range definitions + */ +/* ROM definitions (8 MB, mirrored multiple times) */ +#define ROM_START 0xFE000000 +#define ROM_SIZE 0x02000000 +#define ROM_END (ROM_START+ROM_SIZE-1) +#define BOOT_START ROM_START +#define BOOT_END ROM_END + +/* SDRAM definitions (256 MB) */ +#define RAM_START 0x00000000 +#define RAM_SIZE 0x10000000 +#define RAM_END (RAM_START+RAM_SIZE-1) + + +/* working internal memory map base address */ +#define IMMRBAR 0xE0000000 + +/* + * working values for various registers, used in start/start.S + */ +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL ROM_START +#define LBLAWAR0_VAL 0x80000018 +#define LBLAWBAR1_VAL 0xF8000000 +#define LBLAWAR1_VAL 0x80000015 +#define DDRLAWBAR0_VAL RAM_START +#define DDRLAWAR0_VAL 0x8000001B +/* + * Local Bus (Memory) Controller + * FIXME: decode bit settings + */ +#define BR0_VAL 0xFE001001 +#define OR0_VAL 0xFE000E54 +#define BR3_VAL 0xF8001881 +#define OR3_VAL 0xFFC01100 +/* + * Local (memory) bus divider + * FIXME: decode bit settings + */ +#define LCRR_VAL 0x00010004 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80810102 +#define TIMING_CFG_0_VAL 0x00420802 +#define TIMING_CFG_1_VAL 0x3735A322 +#define TIMING_CFG_2_VAL 0x2F9044C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x44521632 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x43000008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x05080000 +#else +#error "board type not defined" +#endif + + +/************************** + * derived values for all boards + */ +/* value of input clock divider (derived from pll mode reg) */ +#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +/* value of system pll (derived from pll mode reg) */ +#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) +/* value of system pll (derived from pll mode reg) */ +#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f) + +#endif /* __GEN83xx_HWREG_VALS_h */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c b/c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c index ca782d4f9d..77b179cbd5 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c @@ -272,6 +272,13 @@ rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum) mpc83xx.ipic.simsr[1] &= mask_ptr->simsr_mask[1]; mpc83xx.ipic.semsr &= mask_ptr->semsr_mask ; mpc83xx.ipic.sermr &= mask_ptr->sermr_mask ; + + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + /* * reenable msr_ee */ @@ -293,6 +300,13 @@ rtems_status_code BSP_irq_handle_at_ipic(uint32_t excNum) * disable msr_enable */ _CPU_MSR_SET(msr_save); + + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + /* * restore initial masks */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/network/network.c b/c/src/lib/libbsp/powerpc/gen83xx/network/network.c index 106893d72e..e5e2a0a91c 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/network/network.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/network/network.c @@ -26,10 +26,16 @@ #include <mpc83xx/mpc83xx.h> #include <stdio.h> -#define TSEC_BITRATE 1000 #define TSEC_IFMODE_RGMII 0 #define TSEC_IFMODE_GMII 1 + +#if defined(MPC8349EAMDS) +#define TSEC_IFMODE TSEC_IFMODE_GMII +#endif + +#if defined(HSC_CM01) #define TSEC_IFMODE TSEC_IFMODE_RGMII +#endif /*=========================================================================*\ | Function: | @@ -61,6 +67,7 @@ int BSP_tsec_attach return 0; } if (attaching) { +#if (TSEC_IFMODE==TSEC_IFMODE_GMII) if (unitNumber == 1) { /* * init system I/O configuration registers @@ -73,13 +80,20 @@ int BSP_tsec_attach mpc83xx.gpio[1].gpdir = ((mpc83xx.gpio[1].gpdir & ~0x00000FFF) | 0x0000001f); } - } - if (unitNumber == 2) { + if (unitNumber == 2) { + /* + * init port registers (GPIO2DIR) for TSEC2 + */ + mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF) + | 0x00087881); + } +#endif +#if (TSEC_IFMODE==TSEC_IFMODE_RGMII) + /* - * init port registers (GPIO2DIR) for TSEC2 + * Nothing special needed for TSEC1 operation */ - mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF) - | 0x00087881); +#endif } /* * add MAC address into config->hardware_adderss diff --git a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am index 13da7c4999..69453171e5 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am @@ -81,6 +81,10 @@ $(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h +$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: ./include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwreg_vals.h + $(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h diff --git a/c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c b/c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c index f49ae95b6b..8fddc2b680 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c @@ -21,9 +21,11 @@ #include <bsp/irq.h> #include <bsp.h> #if defined(MPC8349EAMDS) -#include <libchip/i2c-2b-eeprom.h> #include <libchip/spi-flash-m25p40.h> #endif +#if defined(HSC_CM01) +#include <libchip/spi-fram-fm25l256.h> +#endif /*=========================================================================*\ | Board-specific adaptation functions | @@ -189,7 +191,8 @@ static mpc83xx_spi_desc_t bsp_spi_bus_desc = { { /* our private fields */ reg_ptr: &mpc83xx.spi, initialized: FALSE, - irq_number: BSP_IPIC_IRQ_SPI + irq_number: BSP_IPIC_IRQ_SPI, + base_frq : 0 /* filled in during init */ } }; @@ -248,6 +251,11 @@ rtems_status_code bsp_register_spi mpc83xx.gpio[0].gpdr &= ~(0xf << (31-27)); #endif /* + * update base frequency in spi descriptor + */ + bsp_spi_bus_desc.softc.base_frq = BSP_bus_frequency; + + /* * register SPI bus */ ret_code = rtems_libi2c_register_bus("/dev/spi", @@ -256,10 +264,10 @@ rtems_status_code bsp_register_spi return -ret_code; } spi_busno = ret_code; +#if defined(MPC8349EAMDS) /* - * register M25P40 Flash, when available + * register M25P40 Flash */ -#if defined(MPC8349EAMDS) ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FLASH_DEVICE_NAME, spi_flash_m25p40_rw_driver_descriptor, spi_busno,0x00); @@ -267,6 +275,17 @@ rtems_status_code bsp_register_spi return -ret_code; } #endif +#if defined(HSC_CM01) + /* + * register FM25L256 FRAM + */ + ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FRAM_DEVICE_NAME, + spi_fram_fm25l256_rw_driver_descriptor, + spi_busno,0x02); + if (ret_code < 0) { + return -ret_code; + } +#endif /* * FIXME: further drivers, when available */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S index fc719ab2b2..a982444464 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S +++ b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S @@ -85,6 +85,7 @@ .extern boot_card .extern MBAR +#if defined(RESET_CONF_WRD_L) .section ".resconf","ax" PUBLIC_VAR (reset_conf_words) reset_conf_words: @@ -97,6 +98,7 @@ reset_conf_words: REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff)) REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff)) REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff)) +#endif .section ".vectors","ax" PUBLIC_VAR (reset_vec) @@ -145,7 +147,6 @@ rom_entry: * NOTE: now r31 points to onchip registers */ /* - * FIXME: * we start from 0x100, so ROM is currently mapped to * 0x00000000.. * in the next step, ROM will be remapped to its final location @@ -223,6 +224,7 @@ start_code_in_rom: #ifdef OR3_VAL SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL #endif + /* * ROM startup: init SDRAM access window */ @@ -239,8 +241,20 @@ start_code_in_rom: SET_IMM_REGW r31,r30,DDRLAWAR1_OFF,DDRLAWAR1_VAL #endif /* + * ROM startup: init refresh interval + */ +#ifdef MRPTR_VAL + SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL +#endif + /* * ROM startup: init SDRAM */ +#ifdef LSRT_VAL + SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL +#endif +#ifdef LSDMR_VAL + SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL +#endif #ifdef CS0_BNDS_VAL SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL #endif @@ -277,8 +291,8 @@ start_code_in_rom: #ifdef TIMING_CFG_2_VAL SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL #endif -#ifdef DDR_SDRAM_CFG_VAL - SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL +#ifdef DDRCDR_VAL + SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL #endif #ifdef DDR_SDRAM_CFG_2_VAL SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL @@ -298,39 +312,123 @@ start_code_in_rom: #ifdef DDR_SDRAM_CLK_CNTL_VAL SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL #endif +#ifdef DDR_SDRAM_CFG_2_VAL + SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT +#endif + +#ifdef DDR_ERR_DISABLE_VAL + /* + * disable detect of RAM errors + */ + SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL +#endif +#ifdef DDR_SDRAM_DATA_INIT_VAL + /* + * set this value to initialize memory + */ + SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL +#endif #ifdef DDR_SDRAM_INIT_ADDR_VAL SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL #endif +#ifdef DDR_SDRAM_CFG_VAL /* - * FIXME: ROM startup: perform mode set commands etc for SDRAM + * config DDR SDRAM */ + SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN /* - * ROM startup: copy code to SDRAM + * FIXME: wait 200us */ - LA r30, _text_start /* get start address of text section in RAM */ - add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */ - LA r29, _text_start /* get start address of text section in RAM */ - LA r28, _text_size /* get size of RAM image */ - bl copy_image /* copy text section from ROM to RAM location */ - /* - * FIXME: ROM startup: copy data to SDRAM + * enable DDR SDRAM */ - LA r30, _data_start /* get start address of data section in RAM */ - add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */ - LA r29, _data_start /* get start address of data section in RAM */ - LA r28, _data_size /* get size of RAM image */ - bl copy_image /* copy initialized data section from ROM to RAM location */ + SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN + /* + * wait, until DDR_SDRAM_CFG_2_D_INIT is cleared + */ +1: lwz r30,DDR_SDRAM_CFG_2_OFF(r31) + andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT + bne 1b +#endif +#ifdef DDR_ERR_DISABLE_VAL2 + /* + * enable detect of some RAM errors + */ + SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2 +#endif +#ifdef DDR_SDRAM_INTERVAL_VAL + /* + * set the refresh interval + */ + SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL +#endif +start_rom_skip: + /* + * determine current execution address offset + */ + bl start_rom_skip1 +start_rom_skip1: + mflr r20 + LA r30,start_rom_skip1 + sub. r20,r20,r30 + /* + * execution address offset == 0? + * then do not relocate code and data + */ + beq start_code_in_ram + /* + * ROM or relocatable startup: copy startup code to SDRAM + */ + /* get start address of text section in RAM */ + LA r29, _text_start + /* get start address of text section in ROM (add reloc offset) */ + add r30, r20, r29 + /* get size of startup code */ + LA r28, end_reloc_startup + LA r31, _text_start + sub 28,r28,r31 + /* copy startup code from ROM to RAM location */ + bl copy_image + /* * ROM startup: jump to code copy in SDRAM */ - LA r29, start_code_in_ram /* get compile time address of label */ + /* get compile time address of label */ + LA r29, copy_rest_of_text mtlr r29 blr /* now further execution RAM */ +copy_rest_of_text: +#ifdef LCRR_VAL + SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL +#endif + /* + * ROM or relocatable startup: copy rest of code to SDRAM + */ + /* get start address of rest of code in RAM */ + LA r29, end_reloc_startup + /* get start address of text section in ROM (add reloc offset) */ + add r30, r20, r29 + /* get size of rest of code */ + LA r28, _text_start + LA r31, _text_size + add r28,r28,r31 + sub r28,r28,r29 + bl copy_image /* copy text section from ROM to RAM location */ + + /* + * ROM or relocatable startup: copy data to SDRAM + */ + /* get start address of data section in RAM */ + LA r29, _data_start + /* get start address of data section in ROM (add reloc offset) */ + add r30, r20, r29 + /* get size of RAM image */ + LA r28, _data_size + /* copy initialized data section from ROM to RAM location */ + bl copy_image start_code_in_ram: -start_rom_skip: /* * ROM/RAM startup: clear bss in SDRAM */ @@ -417,3 +515,4 @@ clr_mem_byte: clr_mem_end: blr /* return */ +end_reloc_startup: diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c index 28ccdf1c3d..f410794ad4 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c @@ -48,7 +48,7 @@ static char *BSP_heap_start, *BSP_heap_end; * Time base divisior: scaling value: * BSP_time_base_divisor = TB ticks per millisecond/BSP_bus_frequency */ -unsigned int BSP_bus_frequency = BSP_CSB_CLK_FRQ; +unsigned int BSP_bus_frequency; unsigned int BSP_time_base_divisor = 4000; /* 4 bus clicks per TB click */ /* @@ -188,9 +188,14 @@ void bsp_start(void) _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); /* + * this is evaluated during runtime, so it should be ok to set it + * before we initialize the drivers + */ + BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID; + /* * initialize the device driver parameters */ - bsp_clicks_per_usec = (BSP_CSB_CLK_FRQ/1000000); + bsp_clicks_per_usec = (BSP_bus_frequency/1000000); /* * Install our own set of exception vectors diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds index f81e4729ea..deb33b2371 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds @@ -43,7 +43,10 @@ SECTIONS mpc83xx_regs (NOLOAD) : { IMMRBAR = .; - *mpc83xx_regs*(*) + mpc83xx_regs*(.text) + mpc83xx_regs*(.data) + mpc83xx_regs*(.bss) + mpc83xx_regs*(*COM*) } > mpc83xx_regs .resconf 0x000 : diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01 b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01 index f9b3fdf6b1..35088240d6 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01 +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01 @@ -37,10 +37,13 @@ MEMORY SECTIONS { - mpc83xx_regs (NOLOAD) : + .mpc83xx_regs (NOLOAD) : { IMMRBAR = .; - *mpc83xx_regs*(*) + mpc83xx_regs*(.text) + mpc83xx_regs*(.data) + mpc83xx_regs*(.bss) + mpc83xx_regs*(*COM*) } > mpc83xx_regs .resconf 0x000 : diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds index 1be37410df..dabf983ca6 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds @@ -40,7 +40,10 @@ SECTIONS mpc83xx_regs (NOLOAD) : { IMMRBAR = .; - *mpc83xx_regs*(*) + mpc83xx_regs*(.text) + mpc83xx_regs*(.data) + mpc83xx_regs*(.bss) + mpc83xx_regs*(*COM*) } > mpc83xx_regs .resconf 0x000 : diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog index 043f6da661..5948b9ea7a 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog +++ b/c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog @@ -1,3 +1,9 @@ +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * irq/irq.c: + make sure, that the masking operations in + ICTL and MSR are executed in order + 2008-05-14 Joel Sherrill <joel.sherrill@OARcorp.com> * Makefile.am: Rework to avoid .rel files. diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c index 19fa082d1a..1a82989567 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c @@ -472,6 +472,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT)); ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; } + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); @@ -480,6 +486,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_SET(msr); + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + if (cpmIntr) { irq -= BSP_CPM_IRQ_LOWEST_OFFSET; ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq); diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog b/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog index 0e70b7ffc3..6ea1d39592 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog @@ -1,3 +1,9 @@ +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * irq/irq.c: + make sure, that the masking operations in + ICTL and MSR are executed in order + 2008-05-14 Joel Sherrill <joel.sherrill@OARcorp.com> * Makefile.am: Rework to avoid .rel files. diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c index 13e2d674df..29e5f9f9fa 100644 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c +++ b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c @@ -483,6 +483,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) m8260.sipnr_h |= SIU_MaskBit[irq].mask_h; m8260.sipnr_l |= SIU_MaskBit[irq].mask_l; + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + /* re-enable external exceptions */ _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; @@ -494,6 +500,12 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) /* disable exceptions again */ _CPU_MSR_SET(msr); + /* + * make sure, that the masking operations in + * ICTL and MSR are executed in order + */ + asm volatile("sync":::"memory"); + /* restore interrupt masks */ m8260.simr_h = old_simr_h; m8260.simr_l = old_simr_l; diff --git a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am index 76a8db09dd..7d7a1a4421 100644 --- a/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mvme3100/preinstall.am @@ -137,7 +137,8 @@ $(PROJECT_INCLUDE)/bsp/vpd.h: ../shared/motorola/vpd.h $(PROJECT_INCLUDE)/bsp/$( $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vpd.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vpd.h +if HAS_NETWORKING $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h: network/if_tsec_pub.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h - +endif diff --git a/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am b/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am index 357ad6f983..cb85530b95 100644 --- a/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am +++ b/c/src/lib/libbsp/powerpc/mvme5500/preinstall.am @@ -113,23 +113,6 @@ $(PROJECT_INCLUDE)/bsp/VPD.h: GT64260/VPD.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VPD.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VPD.h -if HAS_NETWORKING -$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h - -$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h - -$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h - -$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h -endif $(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VME.h @@ -158,6 +141,23 @@ $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(P $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h +if HAS_NETWORKING +$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h + +$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h + +$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h + +$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h +endif $(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT) TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT) diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index 48537805e5..437ad6d4a6 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,14 @@ +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * mpc83xx/network/tsec.c, mpc83xx/include/mpc83xx.h: + added support for RGMII interface and different board + +2008-05-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * mpc83xx/i2c/mpc83xx_i2cdrv.c, mpc83xx/i2c/mpc83xx_i2cdrv.h, + * mpc83xx/spi/mpc83xx_spidrv.c, mpc83xx/spi/mpc83xx_spidrv.h: + added base frequency into softc structure + 2008-05-14 Till Straumann <strauman@slac.stanford.edu> * new-exceptions/bspsupport/ppc_exc_bspsupp.h: added diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c index 57b97a0967..7db790b37b 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c +++ b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c @@ -31,7 +31,7 @@ /*=========================================================================*\ | Function: | \*-------------------------------------------------------------------------*/ -static int mpc83xx_i2c_find_clock_divider +static rtems_status_code mpc83xx_i2c_find_clock_divider ( /*-------------------------------------------------------------------------*\ | Purpose: | @@ -49,6 +49,7 @@ static int mpc83xx_i2c_find_clock_divider { int i; int fdr_val; + rtems_status_code sc = RTEMS_SUCCESSFUL; struct { int divider; int fdr_val; @@ -68,15 +69,23 @@ static int mpc83xx_i2c_find_clock_divider {49152,0x1E }, {61440,0x1F } }; - for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) { - fdr_val = dividers[i].fdr_val; - if (dividers[i].divider >= divider) - { - break; - } + if (divider <= 0) { + sc = RTEMS_INVALID_NUMBER; } - *result = fdr_val; - return 0; + + if (sc == RTEMS_SUCCESSFUL) { + sc = RTEMS_INVALID_NUMBER; + for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) { + fdr_val = dividers[i].fdr_val; + if (dividers[i].divider >= divider) + { + sc = RTEMS_SUCCESSFUL; + *result = fdr_val; + break; + } + } + } + return sc; } /*=========================================================================*\ @@ -313,7 +322,7 @@ static rtems_status_code mpc83xx_i2c_init * init frequency divider to 100kHz */ errval = mpc83xx_i2c_find_clock_divider(&fdr_val, - BSP_CSB_CLK_FRQ/3/100000); + softc_ptr->base_frq/100000); if (errval != 0) { return errval; } @@ -471,9 +480,6 @@ static rtems_status_code mpc83xx_i2c_send_addr return rc; } } - addr_byte = (0xf0 - | ((addr >> 7) & 0x06) - | ((rw) ? 1 : 0)); /* * send (final) byte */ @@ -525,6 +531,10 @@ static int mpc83xx_i2c_read_bytes softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MTX; softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_TXAK; /* + * FIXME: do we need to deactivate TXAK from the start, + * when only one byte is to be received? + */ + /* * we need a dummy transfer here to start the first read */ dummy = softc_ptr->reg_ptr->i2cdr; diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h index 793cd6d564..33f40003ad 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h @@ -28,10 +28,11 @@ extern "C" { #endif typedef struct mpc83xx_i2c_softc { - m83xxI2CRegisters_t *reg_ptr; - int initialized; - rtems_irq_number irq_number; - rtems_id irq_sema_id; + m83xxI2CRegisters_t *reg_ptr; /* ptr to HW registers */ + int initialized; /* TRUE: module is initialized */ + rtems_irq_number irq_number; /* IRQ number used for this module */ + uint32_t base_frq; /* input frq for baud rate divider */ + rtems_id irq_sema_id; /* SEMA used for IRQ signalling */ } mpc83xx_i2c_softc_t ; typedef struct { diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h index ee06c2fee7..459aaee1cc 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h @@ -1110,6 +1110,12 @@ extern m83xxRegisters_t mpc83xx; #define BR7_OFF 0x05038 #define OR7_OFF 0x0503C +#define MRPTR_OFF 0x05084 +#define LSDMR_OFF 0x05094 +#define LSRT_OFF 0x050A4 +#define LCRR_OFF 0x050d4 + + #define CS0_BNDS_OFF 0x02000 #define CS1_BNDS_OFF 0x02008 #define CS2_BNDS_OFF 0x02010 @@ -1127,9 +1133,25 @@ extern m83xxRegisters_t mpc83xx; #define DDR_SDRAM_MODE_OFF 0x02118 #define DDR_SDRAM_MODE_2_OFF 0x0211C #define DDR_SDRAM_MD_CNTL_OFF 0x02120 -#define DDR_SDRAM_MD_ITVL_OFF 0x02124 +#define DDR_SDRAM_INTERVAL_OFF 0x02124 +#define DDR_SDRAM_DATA_INIT_OFF 0x02128 +#define DDRCDR_OFF 0x0012C #define DDR_SDRAM_CLK_CNTL_OFF 0x02130 #define DDR_SDRAM_INIT_ADDR_OFF 0x02148 +#define DDR_ERR_DISABLE_OFF 0x02E44 + +/* + * some bits in DDR_SDRAM_CFG register + */ +#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0)) /* enable memory */ +/* + * bits in DDR_SDRAM_CFG_2 register + */ +#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh */ +#define DDR_SDRAM_CFG_2_D_SR_IE (1 << (31- 1)) /* self refresh interrupt en */ +#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS (1 << (31- 2)) /* DLL reset disable */ +#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF (1 << (31- 5)) /* use diff. DQS */ +#define DDR_SDRAM_CFG_2_D_INIT (1 << (31-27)) /* Init DRAM with pattern */ /* * bits in reset configuration words/registers diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c index 8b3ac09e96..95fca9f81d 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c +++ b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c @@ -115,14 +115,14 @@ static struct mpc83xx_tsec_struct tsec_driver[M83xx_TSEC_NIFACES]; */ #define M83xx_IEVENT_TXALL (M83xx_TSEC_IEVENT_GTSC \ | M83xx_TSEC_IEVENT_TXC \ - | M83xx_TSEC_IEVENT_TXB \ + /*| M83xx_TSEC_IEVENT_TXB*/ \ | M83xx_TSEC_IEVENT_TXF ) /* * mask for all Rx interrupts */ #define M83xx_IEVENT_RXALL (M83xx_TSEC_IEVENT_RXC \ - | M83xx_TSEC_IEVENT_RXB \ + /* | M83xx_TSEC_IEVENT_RXB */ \ | M83xx_TSEC_IEVENT_GRSC \ | M83xx_TSEC_IEVENT_RXF ) @@ -251,14 +251,14 @@ static void mpc83xx_tsec_hwinit * init transmit interrupt coalescing register */ reg_ptr->txic = (M83xx_TSEC_TXIC_ICEN - | M83xx_TSEC_TXIC_ICFCT(16) - | M83xx_TSEC_TXIC_ICTT(16)); + | M83xx_TSEC_TXIC_ICFCT(2) + | M83xx_TSEC_TXIC_ICTT(32)); /* * init receive interrupt coalescing register */ reg_ptr->rxic = (M83xx_TSEC_RXIC_ICEN - | M83xx_TSEC_RXIC_ICFCT(16) - | M83xx_TSEC_RXIC_ICTT(16)); + | M83xx_TSEC_RXIC_ICFCT(2) + | M83xx_TSEC_RXIC_ICTT(32)); /* * init MACCFG1 register */ @@ -673,7 +673,7 @@ static void mpc83xx_tsec_refill_rxbds BD_ptr->buffer = m->m_data; BD_ptr->length = 0; BD_ptr->status = (M83xx_BD_EMPTY - | M83xx_BD_INTERRUPT + | M83xx_BD_INTERRUPT | ((BD_ptr == sc->Rx_Last_BD) ? M83xx_BD_WRAP : 0)); @@ -971,7 +971,7 @@ static void mpc83xx_tsec_sendpacket } status = ((M83xx_BD_PAD_CRC | M83xx_BD_TX_CRC) | ((m->m_next == NULL) - ? M83xx_BD_LAST | M83xx_BD_INTERRUPT + ? M83xx_BD_LAST | M83xx_BD_INTERRUPT : 0) | ((CurrBD == sc->Tx_Last_BD) ? M83xx_BD_WRAP : 0)); @@ -1212,7 +1212,7 @@ static void mpc83xx_tsec_err_irq_handler /* * clear error events in IEVENT */ - sc->reg_ptr->tstat = M83xx_IEVENT_ERRALL; + sc->reg_ptr->ievent = M83xx_IEVENT_ERRALL; /* * has Rx been stopped? then restart it */ @@ -1546,6 +1546,18 @@ static void mpc83xx_tsec_stats rtems_ifmedia2str(media,NULL,0); printf ("\n"); } +#if 1 /* print all PHY registers */ + { + int reg; + uint32_t reg_val; + printf("****** PHY register values****\n"); + for (reg = 0;reg <= 31;reg++) { + mpc83xx_tsec_mdio_read(-1,sc,reg,®_val); + printf("%02d:0x%04x%c",reg,reg_val, + (((reg % 4) == 3) ? '\n' : ' ')); + } + } +#endif /* * print some statistics */ @@ -1713,13 +1725,6 @@ int rtems_mpc83xx_tsec_mode_adapt if (result != 0) { return result; } -#ifdef DEBUG - /* - * test: print current status - */ - rtems_ifmedia2str(media,NULL,0); - printf ("\n"); -#endif } while (IFM_NONE == IFM_SUBTYPE(media)); } @@ -1727,7 +1732,7 @@ int rtems_mpc83xx_tsec_mode_adapt * now set HW according to media results: */ /* - * if we are 1000MBit, then switch IF to GMII/byte mode + * if we are 1000MBit, then switch IF to byte mode */ if (IFM_1000_T == IFM_SUBTYPE(media)) { sc->reg_ptr->maccfg2 = @@ -1740,6 +1745,15 @@ int rtems_mpc83xx_tsec_mode_adapt | M83xx_TSEC_MACCFG2_IFMODE_NIB); } /* + * if we are 10MBit, then switch rate to 10M + */ + if (IFM_10_T == IFM_SUBTYPE(media)) { + sc->reg_ptr->ecntrl &= ~M83xx_TSEC_ECNTRL_R100M; + } + else { + sc->reg_ptr->ecntrl |= M83xx_TSEC_ECNTRL_R100M; + } + /* * if we are half duplex then switch to half duplex */ if (0 == (IFM_FDX & IFM_OPTIONS(media))) { @@ -1885,6 +1899,15 @@ static int mpc83xx_tsec_driver_attach ifp->if_snd.ifq_maxlen = ifqmaxlen; } +#if defined(HSC_CM01) + /* + * for HSC CM01: we need to configure the PHY to use maximum skew adjust + */ + + mpc83xx_tsec_mdio_write(-1,sc,31,1); + mpc83xx_tsec_mdio_write(-1,sc,28,0xf000); + mpc83xx_tsec_mdio_write(-1,sc,31,0); +#endif /* * Attach the interface */ diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c index 54b4588102..e94c72e7f6 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c +++ b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c @@ -41,6 +41,7 @@ static rtems_status_code mpc83xx_spi_baud_to_mode | Input Parameters: | \*-------------------------------------------------------------------------*/ uint32_t baudrate, /* desired baudrate */ + uint32_t base_frq, /* input frequency */ uint32_t *spimode /* result value */ ) /*-------------------------------------------------------------------------*\ @@ -53,7 +54,7 @@ static rtems_status_code mpc83xx_spi_baud_to_mode /* * determine clock divider and DIV16 bit */ - divider = (BSP_CSB_CLK_FRQ+baudrate-1)/baudrate; + divider = (base_frq+baudrate-1)/baudrate; if (divider > 64) { tmpmode = MPC83XX_SPIMODE_DIV16; divider /= 16; @@ -586,7 +587,9 @@ rtems_status_code mpc83xx_spi_set_tfr_mode * FIXME: set proper mode */ if (rc == RTEMS_SUCCESSFUL) { - rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,&spimode_baud); + rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate, + softc_ptr->base_frq, + &spimode_baud); } if (rc == RTEMS_SUCCESSFUL) { rc = mpc83xx_spi_char_mode(softc_ptr, diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h index 070e520d95..475419959d 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h @@ -32,6 +32,7 @@ typedef struct mpc83xx_spi_softc { m83xxSPIRegisters_t *reg_ptr; int initialized; rtems_irq_number irq_number; + uint32_t base_frq; /* input frq for baud rate divider */ rtems_id irq_sema_id; uint32_t curr_addr; /* current spi address */ uint8_t bytes_per_char; diff --git a/c/src/libchip/Makefile.am b/c/src/libchip/Makefile.am index 243c87d865..fc9da09a96 100644 --- a/c/src/libchip/Makefile.am +++ b/c/src/libchip/Makefile.am @@ -74,13 +74,16 @@ EXTRA_DIST += rtc/README.ds1643 rtc/README.icm7170 rtc/README.m48t08 \ # i2c if LIBCHIP include_libchip_HEADERS += i2c/i2c-ds1621.h i2c/i2c-2b-eeprom.h \ - i2c/spi-flash-m25p40.h + i2c/spi-memdrv.h \ + i2c/spi-flash-m25p40.h i2c/spi-fram-fm25l256.h noinst_LIBRARIES += libi2cio.a libi2cio_a_CPPFLAGS = $(AM_CPPFLAGS) libi2cio_a_SOURCES = i2c/i2c-ds1621.c i2c/i2c-2b-eeprom.c \ i2c/i2c-ds1621.h i2c/i2c-2b-eeprom.h \ - i2c/spi-flash-m25p40.c i2c/spi-flash-m25p40.h + i2c/spi-memdrv.c i2c/spi-memdrv.h \ + i2c/spi-flash-m25p40.c i2c/spi-flash-m25p40.h \ + i2c/spi-fram-fm25l256.c i2c/spi-fram-fm25l256.h endif # serial diff --git a/c/src/libchip/i2c/spi-flash-m25p40.c b/c/src/libchip/i2c/spi-flash-m25p40.c index 782b32f691..4e2e4b9423 100644 --- a/c/src/libchip/i2c/spi-flash-m25p40.c +++ b/c/src/libchip/i2c/spi-flash-m25p40.c @@ -15,11 +15,6 @@ | | +-----------------------------------------------------------------+ \*===============================================================*/ -/* - * FIXME: currently, this driver only supports read/write accesses - * erase accesses are to be completed - */ - #include <rtems.h> #include <rtems/libi2c.h> @@ -27,344 +22,39 @@ #include <libchip/spi-flash-m25p40.h> #include <rtems/libio.h> -#define FLASH_M25P40_CMD_WREN 0x06 -#define FLASH_M25P40_CMD_WRDIS 0x04 -#define FLASH_M25P40_CMD_RDID 0x9F -#define FLASH_M25P40_CMD_RDSR 0x05 -#define FLASH_M25P40_CMD_WRSR 0x01 -#define FLASH_M25P40_CMD_READ 0x03 -#define FLASH_M25P40_CMD_PP 0x02 /* page program */ -#define FLASH_M25P40_CMD_SE 0xD8 /* sector erase */ -#define FLASH_M25P40_CMD_BE 0xC7 /* bulk erase */ -#define FLASH_M25P40_CMD_DP 0xB9 /* deep power down */ -#define FLASH_M25P40_CMD_RES 0xAB /* release from deep power down */ - -#define M25P40_PAGE_SIZE 256 -#define M25P40_TOTAL_SIZE (512*1024) - -const rtems_libi2c_tfr_mode_t spi_flash_m25p40_tfr_mode = { - baudrate: 20000000, /* maximum bits per second */ - bits_per_char: 8, /* how many bits per byte/word/longword? */ - lsb_first: FALSE, /* FALSE: send MSB first */ - clock_inv: FALSE, /* FALSE: non-inverted clock (high active) */ - clock_phs: FALSE /* FALSE: clock starts in middle of data tfr */ -} ; - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code spi_flash_m25p40_wait_ms -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| wait a certain interval given in ms | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - int ms /* time to wait in milliseconds */ -) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| o = ok or error code | -\*=========================================================================*/ -{ - rtems_status_code rc = RTEMS_SUCCESSFUL; - rtems_interval ticks_per_second; - - rc = rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND,&ticks_per_second); - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_task_wake_after(ticks_per_second * ms / 1000); - } - return rc; -} - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code spi_flash_m25p40_write -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| write a block of data to flash | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_device_major_number major, /* major device number */ - rtems_device_major_number minor, /* minor device number */ - void *arg /* ptr to write argument struct */ -) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| o = ok or error code | -\*=========================================================================*/ -{ - rtems_status_code rc = RTEMS_SUCCESSFUL; - rtems_libio_rw_args_t *rwargs = arg; - unsigned off = rwargs->offset; - int cnt = rwargs->count; - unsigned char *buf = (unsigned char *)rwargs->buffer; - int bytes_sent = 0; - int curr_cnt; - unsigned char cmdbuf[4]; - int ret_cnt = 0; - /* - * check arguments - */ - if (rc == RTEMS_SUCCESSFUL) { - if ((cnt <= 0) || - (cnt > M25P40_TOTAL_SIZE) || - (off > (M25P40_TOTAL_SIZE-cnt))) { - rc = RTEMS_INVALID_SIZE; - } - else if (buf == NULL) { - rc = RTEMS_INVALID_ADDRESS; - } - } - /* - * select device, set transfer mode, address device - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_start(minor); - } - /* - * set transfer mode - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = -rtems_libi2c_ioctl(minor, - RTEMS_LIBI2C_IOCTL_SET_TFRMODE, - &spi_flash_m25p40_tfr_mode); - } - - /* - * address device - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_addr(minor,TRUE); - } - - /* - * send write_enable command - */ - if (rc == RTEMS_SUCCESSFUL) { - cmdbuf[0] = FLASH_M25P40_CMD_WREN; - ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1); - if (ret_cnt < 0) { - rc = -ret_cnt; - } - } - /* - * terminate transfer - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_stop(minor); - } - while ((rc == RTEMS_SUCCESSFUL) && - (cnt > bytes_sent)) { - curr_cnt = cnt; - if ((off / M25P40_PAGE_SIZE) != - ((off+curr_cnt+1) / M25P40_PAGE_SIZE)) { - curr_cnt = M25P40_PAGE_SIZE - (off % M25P40_PAGE_SIZE); - } - /* - * select device, set transfer mode - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_start(minor); - } - - /* - * address device - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_addr(minor,TRUE); - } - - /* - * set transfer mode - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = -rtems_libi2c_ioctl(minor, - RTEMS_LIBI2C_IOCTL_SET_TFRMODE, - &spi_flash_m25p40_tfr_mode); - } - /* - * send "page program" command and address - */ - if (rc == RTEMS_SUCCESSFUL) { - cmdbuf[0] = FLASH_M25P40_CMD_PP; - cmdbuf[1] = (off >> 16) & 0xff; - cmdbuf[2] = (off >> 8) & 0xff; - cmdbuf[3] = (off >> 0) & 0xff; - ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,4); - if (ret_cnt < 0) { - rc = -ret_cnt; - } - } - /* - * send write data - */ - if (rc == RTEMS_SUCCESSFUL) { - ret_cnt = rtems_libi2c_write_bytes(minor,buf,curr_cnt); - if (ret_cnt < 0) { - rc = -ret_cnt; - } - } - /* - * terminate transfer - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_stop(minor); - } - /* - * wait proper time for data to store: 5ms - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = spi_flash_m25p40_wait_ms(5); - } - /* - * adjust bytecount to be sent and pointers - */ - bytes_sent += curr_cnt; - off += curr_cnt; - buf += curr_cnt; - } - rwargs->bytes_moved = bytes_sent; - return rc; -} -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code spi_flash_m25p40_read -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| read a block of data from flash | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_device_major_number major, /* major device number */ - rtems_device_major_number minor, /* minor device number */ - void *arg /* ptr to read argument struct */ -) -/*-------------------------------------------------------------------------*\ -| Return Value: | -| o = ok or error code | -\*=========================================================================*/ -{ - rtems_status_code rc = RTEMS_SUCCESSFUL; - rtems_libio_rw_args_t *rwargs = arg; - unsigned off = rwargs->offset; - int cnt = rwargs->count; - unsigned char *buf = (unsigned char *)rwargs->buffer; - unsigned char cmdbuf[4]; - int ret_cnt = 0; - /* - * check arguments - */ - if (rc == RTEMS_SUCCESSFUL) { - if ((cnt <= 0) || - (cnt > M25P40_TOTAL_SIZE) || - (off > (M25P40_TOTAL_SIZE-cnt))) { - rc = RTEMS_INVALID_SIZE; - } - else if (buf == NULL) { - rc = RTEMS_INVALID_ADDRESS; - } - } - /* - * select device, set transfer mode, address device - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_start(minor); - } - /* - * set transfer mode - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = -rtems_libi2c_ioctl(minor, - RTEMS_LIBI2C_IOCTL_SET_TFRMODE, - &spi_flash_m25p40_tfr_mode); - } - /* - * address device - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_addr(minor,TRUE); - } - - if (off >= M25P40_TOTAL_SIZE) { - /* - * HACK: beyond size of Flash array? then read status register instead - */ - /* - * send read status register command - */ - if (rc == RTEMS_SUCCESSFUL) { - cmdbuf[0] = FLASH_M25P40_CMD_RDSR; - ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1); - if (ret_cnt < 0) { - rc = -ret_cnt; - } - } - } - else { - /* - * send read command and address - */ - if (rc == RTEMS_SUCCESSFUL) { - cmdbuf[0] = FLASH_M25P40_CMD_READ; - cmdbuf[1] = (off >> 16) & 0xff; - cmdbuf[2] = (off >> 8) & 0xff; - cmdbuf[3] = (off >> 0) & 0xff; - ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,4); - if (ret_cnt < 0) { - rc = -ret_cnt; - } - } - } - /* - * fetch read data - */ - if (rc == RTEMS_SUCCESSFUL) { - ret_cnt = rtems_libi2c_read_bytes (minor,buf,cnt); - if (ret_cnt < 0) { - rc = -ret_cnt; - } - } - - /* - * terminate transfer - */ - if (rc == RTEMS_SUCCESSFUL) { - rc = rtems_libi2c_send_stop(minor); +static spi_memdrv_t spi_flash_m25p40_rw_drv_t = { + {/* public fields */ + ops: &spi_memdrv_rw_ops, /* operations of general memdrv */ + size: sizeof (spi_flash_m25p40_rw_drv_t), + }, + { /* our private fields */ + baudrate: 2000000, + erase_before_program: TRUE, + empty_state: 0xff, + page_size: 256, /* programming page size in byte */ + sector_size: 64*1024, /* erase sector size in byte */ + mem_size: 512*1024 /* total capacity in byte */ } - rwargs->bytes_moved = (rc == RTEMS_SUCCESSFUL) ? ret_cnt : 0; - - return rc; -} - -static rtems_driver_address_table spi_flash_m25p40_rw_ops = { - read_entry: spi_flash_m25p40_read, - write_entry: spi_flash_m25p40_write -}; - -static rtems_libi2c_drv_t spi_flash_m25p40_rw_drv_tbl = { - ops: &spi_flash_m25p40_rw_ops, - size: sizeof (spi_flash_m25p40_rw_drv_tbl), }; rtems_libi2c_drv_t *spi_flash_m25p40_rw_driver_descriptor = -&spi_flash_m25p40_rw_drv_tbl; - -static rtems_driver_address_table spi_flash_m25p40_ro_ops = { - read_entry: spi_flash_m25p40_read, -}; - -static rtems_libi2c_drv_t spi_flash_m25p40_ro_drv_tbl = { - ops: &spi_flash_m25p40_ro_ops, - size: sizeof (spi_flash_m25p40_ro_drv_tbl), +&spi_flash_m25p40_rw_drv_t.libi2c_drv_entry; + +static spi_memdrv_t spi_flash_m25p40_ro_drv_t = { + {/* public fields */ + ops: &spi_memdrv_ro_ops, /* operations of general memdrv */ + size: sizeof (spi_flash_m25p40_ro_drv_t), + }, + { /* our private fields */ + baudrate: 2000000, + erase_before_program: TRUE, + empty_state: 0xff, + page_size: 256, /* programming page size in byte */ + sector_size: 64*1024, /* erase sector size in byte */ + mem_size: 512*1024 /* total capacity in byte */ + } }; rtems_libi2c_drv_t *spi_flash_m25p40_ro_driver_descriptor = -&spi_flash_m25p40_ro_drv_tbl; +&spi_flash_m25p40_ro_drv_t.libi2c_drv_entry; diff --git a/c/src/libchip/i2c/spi-flash-m25p40.h b/c/src/libchip/i2c/spi-flash-m25p40.h index 26aa37e6f1..f653c125e0 100644 --- a/c/src/libchip/i2c/spi-flash-m25p40.h +++ b/c/src/libchip/i2c/spi-flash-m25p40.h @@ -24,7 +24,7 @@ #ifndef _LIBCHIP_SPI_FLASH_M25P40_H #define _LIBCHIP_SPI_FLASH_M25P40_H -#include <rtems/libi2c.h> +#include <libchip/spi-memdrv.h> #ifdef __cplusplus extern "C" { diff --git a/c/src/libchip/i2c/spi-fram-fm25l256.c b/c/src/libchip/i2c/spi-fram-fm25l256.c new file mode 100644 index 0000000000..b09e97154b --- /dev/null +++ b/c/src/libchip/i2c/spi-fram-fm25l256.c @@ -0,0 +1,60 @@ +/*===============================================================*\ +| Project: SPI driver for FM25L256 like spi fram device | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ + +#include <rtems.h> +#include <rtems/libi2c.h> + +#include <libchip/spi-fram-fm25l256.h> +#include <rtems/libio.h> + + +static spi_memdrv_t spi_fram_fm25l256_rw_drv_t = { + {/* public fields */ + ops: &spi_memdrv_rw_ops, /* operations of general memdrv */ + size: sizeof (spi_fram_fm25l256_rw_drv_t), + }, + { /* our private fields */ + baudrate: 2000000, + erase_before_program: FALSE, + empty_state: 0xff, + page_size: 32*1024, /* programming page size in byte */ + sector_size: 1, /* erase sector size in byte */ + mem_size: 32*1024 /* total capacity in byte */ + } +}; + +rtems_libi2c_drv_t *spi_fram_fm25l256_rw_driver_descriptor = +&spi_fram_fm25l256_rw_drv_t.libi2c_drv_entry; + +static spi_memdrv_t spi_fram_fm25l256_ro_drv_t = { + {/* public fields */ + ops: &spi_memdrv_ro_ops, /* operations of general memdrv */ + size: sizeof (spi_fram_fm25l256_ro_drv_t), + }, + { /* our private fields */ + baudrate: 2000000, + erase_before_program: FALSE, + empty_state: 0xff, + page_size: 32*1024, /* programming page size in byte */ + sector_size: 1, /* erase sector size in byte */ + mem_size: 32*1024 /* total capacity in byte */ + } +}; + +rtems_libi2c_drv_t *spi_fram_fm25l256_ro_driver_descriptor = +&spi_fram_fm25l256_ro_drv_t.libi2c_drv_entry; diff --git a/c/src/libchip/i2c/spi-fram-fm25l256.h b/c/src/libchip/i2c/spi-fram-fm25l256.h new file mode 100644 index 0000000000..d2287c1c14 --- /dev/null +++ b/c/src/libchip/i2c/spi-fram-fm25l256.h @@ -0,0 +1,44 @@ +/*===============================================================*\ +| Project: SPI driver for FM25L256 like spi fram device | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ +/* + * FIXME: currently, this driver only supports read/write accesses + * erase accesses are to be completed + */ + + +#ifndef _LIBCHIP_SPI_FRAM_FM25L256_H +#define _LIBCHIP_SPI_FRAM_FM25L256_H + +#include <libchip/spi-memdrv.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * pass one of these descriptor pointers to rtems_libi2c_register_drv + */ +extern rtems_libi2c_drv_t *spi_fram_fm25l256_rw_driver_descriptor; + +extern rtems_libi2c_drv_t *spi_fram_fm25l256_ro_driver_descriptor; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_FRAM_FM25L256_H */ diff --git a/c/src/libchip/i2c/spi-memdrv.c b/c/src/libchip/i2c/spi-memdrv.c new file mode 100644 index 0000000000..106a02cacc --- /dev/null +++ b/c/src/libchip/i2c/spi-memdrv.c @@ -0,0 +1,445 @@ +/*===============================================================*\ +| Project: SPI driver for spi memory devices | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ +/* + * FIXME: currently, this driver only supports read/write accesses + * erase accesses are to be completed + */ + + +#include <rtems.h> +#include <rtems/libi2c.h> + +#include <libchip/spi-memdrv.h> +#include <rtems/libio.h> + +#define SPI_MEM_CMD_WREN 0x06 +#define SPI_MEM_CMD_WRDIS 0x04 +#define SPI_MEM_CMD_RDID 0x9F +#define SPI_MEM_CMD_RDSR 0x05 +#define SPI_MEM_CMD_WRSR 0x01 +#define SPI_MEM_CMD_READ 0x03 +#define SPI_MEM_CMD_PP 0x02 /* page program */ +#define SPI_MEM_CMD_SE 0xD8 /* sector erase */ +#define SPI_MEM_CMD_BE 0xC7 /* bulk erase */ +#define SPI_MEM_CMD_DP 0xB9 /* deep power down */ +#define SPI_MEM_CMD_RES 0xAB /* release from deep power down */ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_minor2param_ptr +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| translate given minor device number to param pointer | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_minor_number minor, /* minor number of device */ + spi_memdrv_param_t **param_ptr /* ptr to param ptr */ +) +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ +{ + rtems_status_code rc = RTEMS_SUCCESSFUL; + spi_memdrv_t *drv_ptr; + + if (rc == RTEMS_SUCCESSFUL) { + rc = -rtems_libi2c_ioctl(minor, + RTEMS_LIBI2C_IOCTL_GET_DRV_T, + &drv_ptr); + } + if ((rc == RTEMS_SUCCESSFUL) && + (drv_ptr->libi2c_drv_entry.size != sizeof(spi_memdrv_t))) { + rc = RTEMS_INVALID_SIZE; + } + if (rc == RTEMS_SUCCESSFUL) { + *param_ptr = &(drv_ptr->spi_memdrv_param); + } + return rc; +} + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_wait_ms +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| wait a certain interval given in ms | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int ms /* time to wait in milliseconds */ +) +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ +{ + rtems_status_code rc = RTEMS_SUCCESSFUL; + rtems_interval ticks_per_second; + + rc = rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND,&ticks_per_second); + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_task_wake_after(ticks_per_second * ms / 1000); + } + return rc; +} + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_write +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| write a block of data to flash | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_minor_number minor, /* minor device number */ + void *arg /* ptr to write argument struct */ +) +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ +{ + rtems_status_code rc = RTEMS_SUCCESSFUL; + rtems_libio_rw_args_t *rwargs = arg; + unsigned off = rwargs->offset; + int cnt = rwargs->count; + unsigned char *buf = (unsigned char *)rwargs->buffer; + int bytes_sent = 0; + int curr_cnt; + unsigned char cmdbuf[4]; + int ret_cnt = 0; + int cmd_size; + spi_memdrv_param_t *mem_param_ptr; + rtems_libi2c_tfr_mode_t tfr_mode = { + baudrate: 20000000, /* maximum bits per second */ + bits_per_char: 8, /* how many bits per byte/word/longword? */ + lsb_first: FALSE, /* FALSE: send MSB first */ + clock_inv: FALSE, /* FALSE: non-inverted clock (high active) */ + clock_phs: FALSE /* FALSE: clock starts in middle of data tfr */ + } ; + + /* + * get mem parameters + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = spi_memdrv_minor2param_ptr(minor,&mem_param_ptr); + } + /* + * check arguments + */ + if (rc == RTEMS_SUCCESSFUL) { + if ((cnt <= 0) || + (cnt > mem_param_ptr->mem_size) || + (off > (mem_param_ptr->mem_size-cnt))) { + rc = RTEMS_INVALID_SIZE; + } + else if (buf == NULL) { + rc = RTEMS_INVALID_ADDRESS; + } + } + while ((rc == RTEMS_SUCCESSFUL) && + (cnt > bytes_sent)) { + curr_cnt = cnt; + if ((mem_param_ptr->page_size > 0) && + (off / mem_param_ptr->page_size) != + ((off+curr_cnt+1) / mem_param_ptr->page_size)) { + curr_cnt = mem_param_ptr->page_size - (off % mem_param_ptr->page_size); + } + /* + * select device, set transfer mode, address device + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_start(minor); + } + /* + * set transfer mode + */ + if (rc == RTEMS_SUCCESSFUL) { + tfr_mode.baudrate = mem_param_ptr->baudrate; + rc = -rtems_libi2c_ioctl(minor, + RTEMS_LIBI2C_IOCTL_SET_TFRMODE, + &tfr_mode); + } + + /* + * address device + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_addr(minor,TRUE); + } + + /* + * send write_enable command + */ + if (rc == RTEMS_SUCCESSFUL) { + cmdbuf[0] = SPI_MEM_CMD_WREN; + ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1); + if (ret_cnt < 0) { + rc = -ret_cnt; + } + } + /* + * terminate transfer + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_stop(minor); + } + /* + * select device, set transfer mode + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_start(minor); + } + + /* + * address device + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_addr(minor,TRUE); + } + + /* + * set transfer mode + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = -rtems_libi2c_ioctl(minor, + RTEMS_LIBI2C_IOCTL_SET_TFRMODE, + &tfr_mode); + } + /* + * send "page program" command and address + */ + if (rc == RTEMS_SUCCESSFUL) { + cmdbuf[0] = SPI_MEM_CMD_PP; + if (mem_param_ptr->mem_size > 256*256) { + cmdbuf[1] = (off >> 16) & 0xff; + cmdbuf[2] = (off >> 8) & 0xff; + cmdbuf[3] = (off >> 0) & 0xff; + cmd_size = 4; + } + else if (mem_param_ptr->mem_size > 256) { + cmdbuf[1] = (off >> 8) & 0xff; + cmdbuf[2] = (off >> 0) & 0xff; + cmd_size = 3; + } + else { + cmdbuf[1] = (off >> 0) & 0xff; + cmd_size = 1; + } + + ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,cmd_size); + if (ret_cnt < 0) { + rc = -ret_cnt; + } + } + /* + * send write data + */ + if (rc == RTEMS_SUCCESSFUL) { + ret_cnt = rtems_libi2c_write_bytes(minor,buf,curr_cnt); + if (ret_cnt < 0) { + rc = -ret_cnt; + } + } + /* + * terminate transfer + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_stop(minor); + } + /* + * wait proper time for data to store: 5ms + * FIXME: select proper interval or poll, until device is finished + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = spi_memdrv_wait_ms(5); + } + /* + * adjust bytecount to be sent and pointers + */ + bytes_sent += curr_cnt; + off += curr_cnt; + buf += curr_cnt; + } + rwargs->bytes_moved = bytes_sent; + return rc; +} + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_read +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| read a block of data from flash | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_minor_number minor, /* minor device number */ + void *arg /* ptr to read argument struct */ +) +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ +{ + rtems_status_code rc = RTEMS_SUCCESSFUL; + rtems_libio_rw_args_t *rwargs = arg; + unsigned off = rwargs->offset; + int cnt = rwargs->count; + unsigned char *buf = (unsigned char *)rwargs->buffer; + unsigned char cmdbuf[4]; + int ret_cnt = 0; + int cmd_size; + spi_memdrv_param_t *mem_param_ptr; + rtems_libi2c_tfr_mode_t tfr_mode = { + baudrate: 20000000, /* maximum bits per second */ + bits_per_char: 8, /* how many bits per byte/word/longword? */ + lsb_first: FALSE, /* FALSE: send MSB first */ + clock_inv: FALSE, /* FALSE: non-inverted clock (high active) */ + clock_phs: FALSE /* FALSE: clock starts in middle of data tfr */ + } ; + + /* + * get mem parameters + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = spi_memdrv_minor2param_ptr(minor,&mem_param_ptr); + } + /* + * check arguments + */ + if (rc == RTEMS_SUCCESSFUL) { + if ((cnt <= 0) || + (cnt > mem_param_ptr->mem_size) || + (off > (mem_param_ptr->mem_size-cnt))) { + rc = RTEMS_INVALID_SIZE; + } + else if (buf == NULL) { + rc = RTEMS_INVALID_ADDRESS; + } + } + /* + * select device, set transfer mode, address device + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_start(minor); + } + /* + * set transfer mode + */ + if (rc == RTEMS_SUCCESSFUL) { + tfr_mode.baudrate = mem_param_ptr->baudrate; + rc = -rtems_libi2c_ioctl(minor, + RTEMS_LIBI2C_IOCTL_SET_TFRMODE, + &tfr_mode); + } + /* + * address device + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_addr(minor,TRUE); + } + + if (off >= mem_param_ptr->mem_size) { + /* + * HACK: beyond size of memory array? then read status register instead + */ + /* + * send read status register command + */ + if (rc == RTEMS_SUCCESSFUL) { + cmdbuf[0] = SPI_MEM_CMD_RDSR; + ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1); + if (ret_cnt < 0) { + rc = -ret_cnt; + } + } + } + else { + /* + * send read command and address + */ + if (rc == RTEMS_SUCCESSFUL) { + cmdbuf[0] = SPI_MEM_CMD_READ; + if (mem_param_ptr->mem_size > 256*256) { + cmdbuf[1] = (off >> 16) & 0xff; + cmdbuf[2] = (off >> 8) & 0xff; + cmdbuf[3] = (off >> 0) & 0xff; + cmd_size = 4; + } + else if (mem_param_ptr->mem_size > 256) { + cmdbuf[1] = (off >> 8) & 0xff; + cmdbuf[2] = (off >> 0) & 0xff; + cmd_size = 3; + } + else { + cmdbuf[1] = (off >> 0) & 0xff; + cmd_size = 1; + } + ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,cmd_size); + if (ret_cnt < 0) { + rc = -ret_cnt; + } + } + } + /* + * fetch read data + */ + if (rc == RTEMS_SUCCESSFUL) { + ret_cnt = rtems_libi2c_read_bytes (minor,buf,cnt); + if (ret_cnt < 0) { + rc = -ret_cnt; + } + } + + /* + * terminate transfer + */ + if (rc == RTEMS_SUCCESSFUL) { + rc = rtems_libi2c_send_stop(minor); + } + rwargs->bytes_moved = (rc == RTEMS_SUCCESSFUL) ? ret_cnt : 0; + + return rc; +} + +/* + * driver operation tables + */ +rtems_driver_address_table spi_memdrv_rw_ops = { + read_entry: spi_memdrv_read, + write_entry: spi_memdrv_write +}; + +rtems_driver_address_table spi_memdrv_ro_ops = { + read_entry: spi_memdrv_read, +}; + diff --git a/c/src/libchip/i2c/spi-memdrv.h b/c/src/libchip/i2c/spi-memdrv.h new file mode 100644 index 0000000000..fb95b3dd4f --- /dev/null +++ b/c/src/libchip/i2c/spi-memdrv.h @@ -0,0 +1,90 @@ +/*===============================================================*\ +| Project: SPI driver for spi memory devices | ++-----------------------------------------------------------------+ +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.com/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +\*===============================================================*/ + + +#ifndef _LIBCHIP_SPI_MEMDRV_H +#define _LIBCHIP_SPI_MEMDRV_H + +#include <rtems/libi2c.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_write +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| write a block of data to memory | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_major_number minor, /* minor device number */ + void *arg /* ptr to write argument struct */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code spi_memdrv_read +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| read a block of data from memory | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_device_major_number major, /* major device number */ + rtems_device_major_number minor, /* minor device number */ + void *arg /* ptr to read argument struct */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + + typedef struct { + uint32_t baudrate; /* tfr rate, bits per second */ + boolean erase_before_program; + uint32_t empty_state; /* value of erased cells */ + uint32_t page_size; /* programming page size in byte */ + uint32_t sector_size; /* erase sector size in byte */ + uint32_t mem_size /* total capacity in byte */ + } spi_memdrv_param_t; + + typedef struct { + rtems_libi2c_drv_t libi2c_drv_entry; /* general i2c/spi params */ + spi_memdrv_param_t spi_memdrv_param; /* private parameters */ + } spi_memdrv_t; + + extern rtems_driver_address_table spi_memdrv_rw_ops; + extern rtems_driver_address_table spi_memdrv_ro_ops; + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCHIP_SPI_MEMDRV_H */ diff --git a/c/src/libchip/preinstall.am b/c/src/libchip/preinstall.am index d12e43e345..d7d7824bd8 100644 --- a/c/src/libchip/preinstall.am +++ b/c/src/libchip/preinstall.am @@ -125,9 +125,17 @@ $(PROJECT_INCLUDE)/libchip/i2c-2b-eeprom.h: i2c/i2c-2b-eeprom.h $(PROJECT_INCLUD $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/i2c-2b-eeprom.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/i2c-2b-eeprom.h +$(PROJECT_INCLUDE)/libchip/spi-memdrv.h: i2c/spi-memdrv.h $(PROJECT_INCLUDE)/libchip/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-memdrv.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-memdrv.h + $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h: i2c/spi-flash-m25p40.h $(PROJECT_INCLUDE)/libchip/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h + +$(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h: i2c/spi-fram-fm25l256.h $(PROJECT_INCLUDE)/libchip/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h endif if LIBCHIP $(PROJECT_INCLUDE)/libchip/mc68681.h: serial/mc68681.h $(PROJECT_INCLUDE)/libchip/$(dirstamp) |