adapted gen83xx to new board

6 files changed, 97 insertions, 37 deletions

diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c
index 57b97a0967..7db790b37b 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c
@@ -31,7 +31,7 @@
 /*=========================================================================*\
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static int mpc83xx_i2c_find_clock_divider
+static rtems_status_code mpc83xx_i2c_find_clock_divider
 (
 /*-------------------------------------------------------------------------*\
 | Purpose:                                                                  |
@@ -49,6 +49,7 @@ static int mpc83xx_i2c_find_clock_divider
 {
   int i;
   int fdr_val;
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
   struct {
     int divider;
     int fdr_val;
@@ -68,15 +69,23 @@ static int mpc83xx_i2c_find_clock_divider
     {49152,0x1E }, {61440,0x1F }
   };
 
-  for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) {
-    fdr_val = dividers[i].fdr_val;
-    if (dividers[i].divider >= divider)
-      {
-	break;
-      }
+  if (divider <= 0) {
+    sc = RTEMS_INVALID_NUMBER;
   }
-  *result = fdr_val;
-  return 0;
+
+  if (sc == RTEMS_SUCCESSFUL) {
+    sc = RTEMS_INVALID_NUMBER;
+    for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) {
+      fdr_val = dividers[i].fdr_val;
+      if (dividers[i].divider >= divider)
+	{
+	  sc = RTEMS_SUCCESSFUL;
+	  *result = fdr_val;
+	  break;
+	}
+    }
+  }
+  return sc;
 }
 
 /*=========================================================================*\
@@ -313,7 +322,7 @@ static rtems_status_code mpc83xx_i2c_init
    * init frequency divider to 100kHz
    */
   errval = mpc83xx_i2c_find_clock_divider(&fdr_val,
-					  BSP_CSB_CLK_FRQ/3/100000);
+					  softc_ptr->base_frq/100000);
   if (errval != 0) {
     return errval;
   }
@@ -471,9 +480,6 @@ static rtems_status_code mpc83xx_i2c_send_addr
       return rc;
     }
   }
-  addr_byte = (0xf0 
-	       | ((addr >> 7) & 0x06)
-	       | ((rw) ? 1 : 0));
   /*
    * send (final) byte 
    */
@@ -525,6 +531,10 @@ static int mpc83xx_i2c_read_bytes
   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MTX;
   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_TXAK;
   /*
+   * FIXME: do we need to deactivate TXAK from the start, 
+   * when only one byte is to be received?
+   */
+  /*
    * we need a dummy transfer here to start the first read
    */
   dummy = softc_ptr->reg_ptr->i2cdr;
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h
index 793cd6d564..33f40003ad 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h
@@ -28,10 +28,11 @@ extern "C" {
 #endif
 
 typedef struct mpc83xx_i2c_softc {
-  m83xxI2CRegisters_t *reg_ptr;
-  int                  initialized;
-  rtems_irq_number     irq_number;
-  rtems_id             irq_sema_id;
+  m83xxI2CRegisters_t *reg_ptr;     /* ptr to HW registers             */
+  int                  initialized; /* TRUE: module is initialized     */
+  rtems_irq_number     irq_number;  /* IRQ number used for this module */
+  uint32_t             base_frq;    /* input frq for baud rate divider */
+  rtems_id             irq_sema_id; /* SEMA used for IRQ signalling    */
 } mpc83xx_i2c_softc_t ;
 
 typedef struct {
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
index ee06c2fee7..459aaee1cc 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
@@ -1110,6 +1110,12 @@ extern m83xxRegisters_t mpc83xx;
 #define BR7_OFF  0x05038
 #define OR7_OFF  0x0503C
 
+#define MRPTR_OFF                    0x05084
+#define LSDMR_OFF                    0x05094
+#define LSRT_OFF                     0x050A4
+#define LCRR_OFF                     0x050d4
+
+
 #define CS0_BNDS_OFF       0x02000
 #define CS1_BNDS_OFF       0x02008
 #define CS2_BNDS_OFF       0x02010
@@ -1127,9 +1133,25 @@ extern m83xxRegisters_t mpc83xx;
 #define DDR_SDRAM_MODE_OFF           0x02118
 #define DDR_SDRAM_MODE_2_OFF         0x0211C
 #define DDR_SDRAM_MD_CNTL_OFF        0x02120
-#define DDR_SDRAM_MD_ITVL_OFF        0x02124
+#define DDR_SDRAM_INTERVAL_OFF       0x02124
+#define DDR_SDRAM_DATA_INIT_OFF      0x02128
+#define DDRCDR_OFF                   0x0012C
 #define DDR_SDRAM_CLK_CNTL_OFF       0x02130
 #define DDR_SDRAM_INIT_ADDR_OFF      0x02148
+#define DDR_ERR_DISABLE_OFF          0x02E44
+
+/*
+ * some bits in DDR_SDRAM_CFG register
+ */
+#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0))     /* enable memory        */
+/*
+ * bits in DDR_SDRAM_CFG_2 register
+ */
+#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh        */
+#define DDR_SDRAM_CFG_2_D_SR_IE  (1 << (31- 1)) /* self refresh interrupt en */
+#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS  (1 << (31- 2)) /* DLL reset disable   */
+#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF  (1 << (31- 5)) /* use diff. DQS       */
+#define DDR_SDRAM_CFG_2_D_INIT   (1 << (31-27)) /* Init DRAM with pattern    */
 
 /*
  * bits in reset configuration words/registers
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
index 8b3ac09e96..95fca9f81d 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
@@ -115,14 +115,14 @@ static struct mpc83xx_tsec_struct tsec_driver[M83xx_TSEC_NIFACES];
  */
 #define M83xx_IEVENT_TXALL (M83xx_TSEC_IEVENT_GTSC	\
 			    | M83xx_TSEC_IEVENT_TXC 	\
-			    | M83xx_TSEC_IEVENT_TXB 	\
+			    /*| M83xx_TSEC_IEVENT_TXB*/	\
 			    | M83xx_TSEC_IEVENT_TXF )
 
 /*
  * mask for all Rx interrupts
  */
 #define M83xx_IEVENT_RXALL (M83xx_TSEC_IEVENT_RXC  	\
-			    | M83xx_TSEC_IEVENT_RXB  	\
+			    /* | M83xx_TSEC_IEVENT_RXB */	\
 			    | M83xx_TSEC_IEVENT_GRSC 	\
 			    | M83xx_TSEC_IEVENT_RXF  )
 
@@ -251,14 +251,14 @@ static void mpc83xx_tsec_hwinit
    * init transmit interrupt coalescing register
    */
   reg_ptr->txic = (M83xx_TSEC_TXIC_ICEN
-		   | M83xx_TSEC_TXIC_ICFCT(16)
-		   | M83xx_TSEC_TXIC_ICTT(16));
+		   | M83xx_TSEC_TXIC_ICFCT(2)
+		   | M83xx_TSEC_TXIC_ICTT(32));
   /*
    * init receive interrupt coalescing register
    */
   reg_ptr->rxic = (M83xx_TSEC_RXIC_ICEN
-		   | M83xx_TSEC_RXIC_ICFCT(16)
-		   | M83xx_TSEC_RXIC_ICTT(16));
+		   | M83xx_TSEC_RXIC_ICFCT(2)
+		   | M83xx_TSEC_RXIC_ICTT(32));
   /*
    * init MACCFG1 register
    */
@@ -673,7 +673,7 @@ static void mpc83xx_tsec_refill_rxbds
       BD_ptr->buffer   = m->m_data;
       BD_ptr->length   = 0;
       BD_ptr->status   = (M83xx_BD_EMPTY 
-			  | M83xx_BD_INTERRUPT 
+			  | M83xx_BD_INTERRUPT
 			  | ((BD_ptr == sc->Rx_Last_BD) 
 			     ? M83xx_BD_WRAP 
 			     : 0));
@@ -971,7 +971,7 @@ static void mpc83xx_tsec_sendpacket
       }
       status = ((M83xx_BD_PAD_CRC | M83xx_BD_TX_CRC)
 		| ((m->m_next == NULL)        
-		   ? M83xx_BD_LAST | M83xx_BD_INTERRUPT 
+		   ? M83xx_BD_LAST | M83xx_BD_INTERRUPT
 		   : 0)
 		| ((CurrBD == sc->Tx_Last_BD) ? M83xx_BD_WRAP : 0));
 		
@@ -1212,7 +1212,7 @@ static void mpc83xx_tsec_err_irq_handler
   /*
    * clear error events in IEVENT
    */
-  sc->reg_ptr->tstat = M83xx_IEVENT_ERRALL;
+  sc->reg_ptr->ievent = M83xx_IEVENT_ERRALL;
   /*
    * has Rx been stopped? then restart it
    */
@@ -1546,6 +1546,18 @@ static void mpc83xx_tsec_stats
     rtems_ifmedia2str(media,NULL,0);
     printf ("\n");
   }
+#if 1 /* print all PHY registers */
+  {
+    int reg;
+    uint32_t reg_val;
+    printf("****** PHY register values****\n");
+    for (reg = 0;reg <= 31;reg++) {
+      mpc83xx_tsec_mdio_read(-1,sc,reg,&reg_val);
+      printf("%02d:0x%04x%c",reg,reg_val,
+	     (((reg % 4) == 3) ? '\n' : ' '));
+    }
+  }
+#endif  
   /*
    * print some statistics
    */
@@ -1713,13 +1725,6 @@ int rtems_mpc83xx_tsec_mode_adapt
       if (result != 0) {
 	return result;
       }
-#ifdef DEBUG
-      /*
-       * test: print current status
-       */
-      rtems_ifmedia2str(media,NULL,0);
-      printf ("\n");
-#endif
     } while (IFM_NONE == IFM_SUBTYPE(media));
   }
 
@@ -1727,7 +1732,7 @@ int rtems_mpc83xx_tsec_mode_adapt
    * now set HW according to media results:
    */
   /*
-   * if we are 1000MBit, then switch IF to GMII/byte mode
+   * if we are 1000MBit, then switch IF to byte mode
    */
   if (IFM_1000_T == IFM_SUBTYPE(media)) {
     sc->reg_ptr->maccfg2 = 
@@ -1740,6 +1745,15 @@ int rtems_mpc83xx_tsec_mode_adapt
        | M83xx_TSEC_MACCFG2_IFMODE_NIB);
   }
   /*
+   * if we are 10MBit, then switch rate to 10M
+   */
+  if (IFM_10_T == IFM_SUBTYPE(media)) {
+    sc->reg_ptr->ecntrl &= ~M83xx_TSEC_ECNTRL_R100M;
+  }
+  else {
+    sc->reg_ptr->ecntrl |= M83xx_TSEC_ECNTRL_R100M;
+  }
+  /*
    * if we are half duplex then switch to half duplex
    */
   if (0 == (IFM_FDX & IFM_OPTIONS(media))) {
@@ -1885,6 +1899,15 @@ static int mpc83xx_tsec_driver_attach
     ifp->if_snd.ifq_maxlen = ifqmaxlen;
   }
 
+#if defined(HSC_CM01)
+  /*
+   * for HSC CM01: we need to configure the PHY to use maximum skew adjust
+   */
+  
+  mpc83xx_tsec_mdio_write(-1,sc,31,1);
+  mpc83xx_tsec_mdio_write(-1,sc,28,0xf000);
+  mpc83xx_tsec_mdio_write(-1,sc,31,0);
+#endif
   /*
    * Attach the interface
    */
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c
index 54b4588102..e94c72e7f6 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c
@@ -41,6 +41,7 @@ static rtems_status_code mpc83xx_spi_baud_to_mode
 | Input Parameters:                                                         |
 \*-------------------------------------------------------------------------*/
  uint32_t baudrate,                      /* desired baudrate               */
+ uint32_t base_frq,                      /* input frequency                */
  uint32_t *spimode                       /* result value                   */
 )
 /*-------------------------------------------------------------------------*\
@@ -53,7 +54,7 @@ static rtems_status_code mpc83xx_spi_baud_to_mode
   /*
    * determine clock divider and DIV16 bit
    */
-  divider = (BSP_CSB_CLK_FRQ+baudrate-1)/baudrate;
+  divider = (base_frq+baudrate-1)/baudrate;
   if (divider > 64) {
     tmpmode = MPC83XX_SPIMODE_DIV16;
     divider /= 16;
@@ -586,7 +587,9 @@ rtems_status_code mpc83xx_spi_set_tfr_mode
    * FIXME: set proper mode
    */
   if (rc == RTEMS_SUCCESSFUL) {
-    rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,&spimode_baud);
+    rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,
+				  softc_ptr->base_frq,
+				  &spimode_baud);
   }
   if (rc == RTEMS_SUCCESSFUL) {
     rc = mpc83xx_spi_char_mode(softc_ptr,
diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h
index 070e520d95..475419959d 100644
--- a/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h
+++ b/c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h
@@ -32,6 +32,7 @@ typedef struct mpc83xx_spi_softc {
   m83xxSPIRegisters_t *reg_ptr;
   int                  initialized;
   rtems_irq_number     irq_number;
+  uint32_t             base_frq;    /* input frq for baud rate divider */
   rtems_id             irq_sema_id;
   uint32_t             curr_addr; /* current spi address */
   uint8_t              bytes_per_char;