Remove stray white spaces.

19 files changed, 191 insertions, 191 deletions

diff --git a/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c b/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
index b89cbb622f..1ae41b405a 100644
--- a/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
+++ b/c/src/lib/libbsp/mips/genmongoosev/console/conscfg.c
@@ -13,8 +13,8 @@
  *  $Id$
  */
 
-#include <bsp.h> 
- 
+#include <bsp.h>
+
 #include <libchip/serial.h>
 #include <libchip/mg5uart.h>
 
@@ -88,6 +88,6 @@ rtems_device_minor_number  Console_Port_Minor;
 #include <rtems/bspIo.h>
 
 void GENMG5_output_char(char c) { write( 2, &c, 1 ); }
-  
+
 BSP_output_char_function_type           BSP_output_char = GENMG5_output_char;
 BSP_polling_getchar_function_type       BSP_poll_char = NULL;
diff --git a/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h b/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
index fb62ae37b5..3beb8dc513 100644
--- a/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
+++ b/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h
@@ -45,7 +45,7 @@ extern "C" {
 
 
 
-/* 
+/*
  * assertSoftwareInt defined in vectorisrs.c the prototype is here so
  * userspace code can get to it directly.
  *  */
@@ -83,26 +83,26 @@ extern void assertSoftwareInterrupt(uint32_t);
 #if 1
 
 #define Install_tm27_vector( handler ) \
-    (void) set_vector( handler, MONGOOSEV_IRQ_SOFTWARE_1, 1 ); 
+    (void) set_vector( handler, MONGOOSEV_IRQ_SOFTWARE_1, 1 );
 
 
 
 #define Cause_tm27_intr()   assertSoftwareInterrupt(0);
 
-#define Clear_tm27_intr()  
+#define Clear_tm27_intr()
 #define Lower_tm27_intr()
 
 #else
 
 #define Install_tm27_vector( handler ) \
-    (void) set_vector( handler, MONGOOSEV_IRQ_TIMER1, 1 ); 
+    (void) set_vector( handler, MONGOOSEV_IRQ_TIMER1, 1 );
 
 #define Cause_tm27_intr() \
   do { \
     ; \
   } while(0)
 
-#define Clear_tm27_intr() 
+#define Clear_tm27_intr()
 #define Lower_tm27_intr()
 
 #endif
@@ -120,7 +120,7 @@ extern rtems_configuration_table BSP_Configuration;
 /*
  * NOTE: Use the standard Console driver entry
  */
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
@@ -130,7 +130,7 @@ extern rtems_configuration_table BSP_Configuration;
 void bsp_cleanup( void );
 
 rtems_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int );
-   
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/c/src/lib/libbsp/mips/genmongoosev/start/start.S b/c/src/lib/libbsp/mips/genmongoosev/start/start.S
index 1647d4d34a..5c997d7449 100644
--- a/c/src/lib/libbsp/mips/genmongoosev/start/start.S
+++ b/c/src/lib/libbsp/mips/genmongoosev/start/start.S
@@ -43,7 +43,7 @@
 #include "mg5.h"
 
 
-	
+
 #ifdef __mips16
    /* This file contains 32 bit assembly code.  */
    .set nomips16
@@ -136,14 +136,14 @@ _branch:
    or     t0,t2
    jal    t0
    nop
-	
 
-			
-		
+
+
+
 
    li	k0,0
    li   k1,0
-	
+
    move t1,a1
    nop
    li	t2,0xa0000000	/* lower limit of kseg1 */
@@ -152,13 +152,13 @@ _branch:
    subu	t0,t1,t2
    srl  t0,31		/* shift high bit down to bit 0 */
    bnez t0,1f		/* booting from below kseg1 */
-	
+
    subu t0,t3,t1
    srl  t0,31		/* shift high bit down to bit 0 */
    bnez t0,1f		/* booting from above kseg1 */
 
-		
-	
+
+
    /*
    ** Call IcacheFlush. Masking used to call EEPROM address of IcacheFlush.  Label is RAM label.
    */
@@ -211,7 +211,7 @@ _branch:
    nop
 
 
-1:	
+1:
    /*
    ** Print ' RTEMS  b'.  Show that we are booting.
    */
@@ -431,7 +431,7 @@ _initialize_rtems:
    la		a0,_promIcache
    sw		k0,0(a0)
    nop
-	
+
    la		a0,_promDcache
    sw		k1,0(a0)
    nop
@@ -801,34 +801,34 @@ _cpuinit:
 
 
 
-	
 
 
-	
+
+
 /**********************************************************************
 **
 ** Keep the boot-time address of the I & D cache reset code for
-** later on.  If we need to clear the I/D caches, we <must> run from 
-** non-cached memory.  This means the relocated versions are useless, 
+** later on.  If we need to clear the I/D caches, we <must> run from
+** non-cached memory.  This means the relocated versions are useless,
 ** thankfully they are quite small.
 */
-	
+
 _promIcache:	.word 0
 _promDcache:	.word 0
 
-		
+
 
 	.globl promCopyIcacheFlush
 	.ent promCopyIcacheFlush
 	.set noreorder
-promCopyIcacheFlush:	
+promCopyIcacheFlush:
 	move	a0,ra
-	
+
 	la	t1,_promIcache
 	lw	t0,0(t1)
 	nop
 	beqz	t0,1f
-	
+
 	jal	t0
 	nop
 
@@ -836,20 +836,20 @@ promCopyIcacheFlush:
 	nop
 	.set reorder
 	.end promCopyIcacheFlush
-	
 
-	
+
+
 	.globl promCopyDcacheFlush
 	.ent promCopyDcacheFlush
 	.set noreorder
-promCopyDcacheFlush:	
+promCopyDcacheFlush:
 	move	a0,ra
-	
+
 	la	t1,_promDcache
 	lw	t0,0(t1)
 	nop
 	beqz	t0,1f
-	
+
 	jal	t0
 	nop
 
@@ -857,11 +857,11 @@ promCopyDcacheFlush:
 	nop
 	.set reorder
 	.end promCopyDcacheFlush
-			
-	
-		
 
-	
+
+
+
+
 /*******************************************************************************
 ** Function Name:   IcacheFlush
 ** Description:     This functions flushes the on chip icache.
@@ -879,7 +879,7 @@ IcacheFlush:
      li        t0, M_BIU
      lw        t1, 0(t0)
 
-     /* 
+     /*
      ** Isolate I cache
      */
      mfc0      t3, C0_SR        /* Read Status Register */
diff --git a/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c b/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c
index 05eedcb8b2..649cd64a0e 100644
--- a/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c
@@ -91,7 +91,7 @@ void bsp_start( void )
    extern int WorkspaceBase;
    extern void mips_install_isr_entries();
    extern void mips_gdb_stub_install(void);
-   
+
    /* Configure Number of Register Caches */
 
    Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
@@ -142,7 +142,7 @@ void bsp_start( void )
    /* mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) ); */
 
    /* to start up, only enable coprocessor 0 & timer int. per-task
-   ** processor settings will be applied as they are created, this 
+   ** processor settings will be applied as they are created, this
    ** is just to configure the processor for startup
    */
    mips_set_sr( (SR_CU0 | 0x400) );
@@ -166,7 +166,7 @@ void clear_cache( void )
 
 
 /*
- 
+
 //Structure filled in by get_mem_info.
 
 
diff --git a/c/src/lib/libbsp/mips/genmongoosev/startup/gdb-support.c b/c/src/lib/libbsp/mips/genmongoosev/startup/gdb-support.c
index 2b36051053..4c6ee61736 100644
--- a/c/src/lib/libbsp/mips/genmongoosev/startup/gdb-support.c
+++ b/c/src/lib/libbsp/mips/genmongoosev/startup/gdb-support.c
@@ -70,7 +70,7 @@ int mg5rdbgOpenGDBuart(int breakoninit)
    /* set up vectoring for gdb */
    mips_gdb_stub_install(-1);
 
-   /* 
+   /*
       this is a rough approximation of our memory map.  Yours is
       probably different.  It only needs to be sufficient for the stub
       to know what it can and can't do and where.
@@ -81,10 +81,10 @@ int mg5rdbgOpenGDBuart(int breakoninit)
    gdbstub_add_memsegment(0x81500000, 0x81ffffff, MEMOPT_READABLE | MEMOPT_WRITEABLE );
 
 
-   if( breakoninit ) 
+   if( breakoninit )
    {
       printf("gdbstub: GDB stub entered, connect host debugger now\n");
-      /* 
+      /*
          break to gdb.  We'll wait there for the operator to get their gdb
          going, then they can 'continue' or do whatever.
       */
@@ -145,10 +145,10 @@ void putDebugChar (char c)
       * configure dcic for trapping, user & kernel mode, PC traps and enable it *
       dcic = DCIC_TR | DCIC_UD | DCIC_KD | DCIC_PCE | DCIC_DE;
       * dcic = DCIC_UD | DCIC_KD | DCIC_PCE | DCIC_DE; *
-      mips_set_dcic( dcic ); 
+      mips_set_dcic( dcic );
 
       mips_get_bpcrm( reg, mask );
-      mips_get_dcic( dcic ); 
+      mips_get_dcic( dcic );
       * printf("bpc is %08X, bpc_mask is %08X, dcic is now %08X\n", reg, mask, dcic ); *
    }
 */
diff --git a/c/src/lib/libbsp/mips/genmongoosev/timer/timer.c b/c/src/lib/libbsp/mips/genmongoosev/timer/timer.c
index 6b6b99413c..24cf366dfb 100644
--- a/c/src/lib/libbsp/mips/genmongoosev/timer/timer.c
+++ b/c/src/lib/libbsp/mips/genmongoosev/timer/timer.c
@@ -1,4 +1,4 @@
-/* 
+/*
  *  This file implements a benchmark timer using a MONGOOSE-V timer.
  *
  *  COPYRIGHT (c) 1989-2001.
@@ -68,8 +68,8 @@ int Read_timer()
 
   tcr = MONGOOSEV_READ_REGISTER( TIMER_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER );
 
-  MONGOOSEV_WRITE_REGISTER( TIMER_BASE, 
-			    MONGOOSEV_TIMER_CONTROL_REGISTER, 
+  MONGOOSEV_WRITE_REGISTER( TIMER_BASE,
+			    MONGOOSEV_TIMER_CONTROL_REGISTER,
 			    0 );
 
   if ( tcr & MONGOOSEV_TIMER_CONTROL_TIMEOUT )
diff --git a/c/src/lib/libbsp/mips/jmr3904/console/console-io.c b/c/src/lib/libbsp/mips/jmr3904/console/console-io.c
index f6ede9e1db..9f5d59c3b0 100644
--- a/c/src/lib/libbsp/mips/jmr3904/console/console-io.c
+++ b/c/src/lib/libbsp/mips/jmr3904/console/console-io.c
@@ -93,7 +93,7 @@ void console_outbyte_polled(
 }
 
 /*
- *  console_inbyte_nonblocking 
+ *  console_inbyte_nonblocking
  *
  *  This routine polls for a character.
  */
diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
index 83ebc69e80..cf65dde83f 100644
--- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
+++ b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h
@@ -57,7 +57,7 @@ extern "C" {
 
 #define CLOCK_VECTOR TX3904_IRQ_TMR0
 
-#define Clear_tm27_intr()  
+#define Clear_tm27_intr()
 
 #define Lower_tm27_intr()
 #else
@@ -100,7 +100,7 @@ extern rtems_configuration_table BSP_Configuration;
 /*
  * NOTE: Use the standard Console driver entry
  */
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
diff --git a/c/src/lib/libbsp/mips/jmr3904/start/start.S b/c/src/lib/libbsp/mips/jmr3904/start/start.S
index d071f40a91..b415cfc2a7 100644
--- a/c/src/lib/libbsp/mips/jmr3904/start/start.S
+++ b/c/src/lib/libbsp/mips/jmr3904/start/start.S
@@ -33,9 +33,9 @@
 # else
 #  define LA(t,x) la t,x-PICBASE ; addu t,s0,t
 # endif
-#else /* __mips_embedded_pic */ 
+#else /* __mips_embedded_pic */
 # define LA(t,x) la t,x
-#endif /* __mips_embedded_pic */ 
+#endif /* __mips_embedded_pic */
 
 	.text
 	.align	2
@@ -76,7 +76,7 @@ relocate:
 	nop
 	.end _start
 
-	
+
 	.globl	_start_in_ram
 	.ent _start_in_ram
 _start_in_ram:
@@ -118,7 +118,7 @@ _start_in_ram:
 	li	v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
 	mtc0	v0, C0_SR
 2:
-/* Fix high bits, if any, of the PC so that exception handling 
+/* Fix high bits, if any, of the PC so that exception handling
    doesn't get confused.  */
 	LA (v0, 3f)
 	jr	v0
@@ -141,12 +141,12 @@ zerobss:
 	bltu	v0,v1,3b
 	addiu	v0,v0,4				# executed in delay slot
 
-	la	t0, _stack_init			# initialize stack so we 
+	la	t0, _stack_init			# initialize stack so we
 	/* We must subtract 24 bytes for the 3 8 byte arguments to main, in
 	   case main wants to write them back to the stack.  The caller is
 	   supposed to allocate stack space for parameters in registers in
 	   the old MIPS ABIs.  We must do this even though we aren't passing
-	   arguments, because main might be declared to have them. 
+	   arguments, because main might be declared to have them.
 
 	   Some ports need a larger alignment for the stack, so we subtract
 	   32, which satisifes the stack for the arguments and keeps the
@@ -169,7 +169,7 @@ init:
 						/* destructors */
 	move	a0,v0				/* pass through the exit code */
 	.end	init
-	
+
 /*
  * _sys_exit -- Exit from the application. Normally we cause a user trap
  *          to return to the ROM monitor for another run. NOTE: This is
diff --git a/c/src/lib/libbsp/mips/jmr3904/startup/bspstart.c b/c/src/lib/libbsp/mips/jmr3904/startup/bspstart.c
index 74a0fce605..bd41945129 100644
--- a/c/src/lib/libbsp/mips/jmr3904/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/jmr3904/startup/bspstart.c
@@ -36,7 +36,7 @@ char *rtems_progname;
 /*
  *  Use the shared implementations of the following routines
  */
- 
+
 void bsp_postdriver_hook(void);
 void bsp_libc_init( void *, uint32_t, int );
 
@@ -53,7 +53,7 @@ void bsp_libc_init( void *, uint32_t, int );
  *      not yet initialized.
  *
  */
- 
+
 void bsp_pretasking_hook(void)
 {
     extern int HeapBase;
@@ -68,7 +68,7 @@ void bsp_pretasking_hook(void)
 #endif
 
 }
- 
+
 /*
  *  bsp_start
  *
diff --git a/c/src/lib/libbsp/mips/jmr3904/timer/timer.c b/c/src/lib/libbsp/mips/jmr3904/timer/timer.c
index 101f6e4aa8..75bfb1477e 100644
--- a/c/src/lib/libbsp/mips/jmr3904/timer/timer.c
+++ b/c/src/lib/libbsp/mips/jmr3904/timer/timer.c
@@ -1,4 +1,4 @@
-/* 
+/*
  *  This file implements a benchmark timer using a TX39 timer.
  *
  *  NOTE: On the simulator, the count directly reflects instructions.
diff --git a/c/src/lib/libbsp/mips/p4000/console/console.c b/c/src/lib/libbsp/mips/p4000/console/console.c
index 43d63b1ef2..1183b06237 100644
--- a/c/src/lib/libbsp/mips/p4000/console/console.c
+++ b/c/src/lib/libbsp/mips/p4000/console/console.c
@@ -65,16 +65,16 @@ rtems_device_driver console_initialize(
 )
 {
   rtems_status_code status;
- 
+
   status = rtems_io_register_name(
     "/dev/console",
     major,
     (rtems_device_minor_number) 0
   );
- 
+
   if (status != RTEMS_SUCCESSFUL)
     rtems_fatal_error_occurred(status);
- 
+
   return RTEMS_SUCCESSFUL;
 }
 
@@ -179,7 +179,7 @@ rtems_device_driver console_open(
 #endif
   return RTEMS_SUCCESSFUL;
 }
- 
+
 /*
  *  Close entry point
  */
@@ -211,7 +211,7 @@ rtems_device_driver console_read(
   char *buffer;
   int maximum;
   int count = 0;
- 
+
   rw_args = (rtems_libio_rw_args_t *) arg;
 
   buffer = rw_args->buffer;
@@ -230,7 +230,7 @@ rtems_device_driver console_read(
 }
 
 /*
- * write bytes to the serial port. Stdout and stderr are the same. 
+ * write bytes to the serial port. Stdout and stderr are the same.
  */
 
 rtems_device_driver console_write(
diff --git a/c/src/lib/libbsp/mips/p4000/include/bsp.h b/c/src/lib/libbsp/mips/p4000/include/bsp.h
index 82aee0b5b7..4f78ec1106 100644
--- a/c/src/lib/libbsp/mips/p4000/include/bsp.h
+++ b/c/src/lib/libbsp/mips/p4000/include/bsp.h
@@ -73,8 +73,8 @@ extern uint32_t   mips_get_timer( void );
  *  Simple spin delay in microsecond units for device drivers.
  *  This is very dependent on the clock speed of the target.
  *
- *  NOTE: This macro generates a warning like "integer constant out 
- *        of range" which is safe to ignore.  In 64 bit mode, uint32_t  
+ *  NOTE: This macro generates a warning like "integer constant out
+ *        of range" which is safe to ignore.  In 64 bit mode, uint32_t
  *        types are actually 64 bits long so that comparisons between
  *        uint32_t   types and pointers are valid.  The warning is caused
  *        by code in the delay macro that is necessary for 64 bit mode.
@@ -108,7 +108,7 @@ extern rtems_configuration_table BSP_Configuration;
 /*
  * NOTE: Use the standard Console driver entry
  */
- 
+
 /*
  * NOTE: Use the standard Clock driver entry
  */
diff --git a/c/src/lib/libbsp/mips/p4000/start/start.S b/c/src/lib/libbsp/mips/p4000/start/start.S
index 1421c8b8d2..4bcd885e6a 100644
--- a/c/src/lib/libbsp/mips/p4000/start/start.S
+++ b/c/src/lib/libbsp/mips/p4000/start/start.S
@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
   $Id$
-*/ 
+*/
 
 /*************************************************************************
 **
@@ -44,7 +44,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 	.text
 
 
-#define TMP_STKSIZE  1024 
+#define TMP_STKSIZE  1024
 
 /**************************************************************************
 **
@@ -57,7 +57,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **		c) Clear all IntMask Enables
 **		d) Set kernel/disabled mode
 **	2)  Initialize Cause Register
-**		a)  clear software interrupt bits       
+**		a)  clear software interrupt bits
 **	3)  Determine FPU installed or not
 **		if not, clear CoProcessor 1 usable bit
 **	4)  Clear bss area
@@ -69,15 +69,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **	9)  Flush Instruction and Data caches
 ** 	10)  If there is a Translation Lookaside Buffer, Clear the TLB
 ** 	11)  Execute initialization code if the IDT/c library is to be used
-** 
+**
 ** 	12)  Jump to user's "main()" (boot_card() for RTEMS)
 ** 	13)  Jump to promexit
 **
-**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 
+**	IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
 **	This is used to mark code specific to R3xxx or R4xxx processors.
-**	IDT/C 6.x defines __mips to be the ISA level for which we're 
-**	generating code. This is used to make sure the stack etc. is 
-**	double word aligned, when using -mips3 (default) or -mips2, 
+**	IDT/C 6.x defines __mips to be the ISA level for which we're
+**	generating code. This is used to make sure the stack etc. is
+**	double word aligned, when using -mips3 (default) or -mips2,
 **	when compiling with IDT/C6.x
 **
 ***************************************************************************/
@@ -109,10 +109,10 @@ FRAME(start,sp,0,ra)
 #endif
 
 /*
-**	check to see if an fpu is really plugged in 
+**	check to see if an fpu is really plugged in
 */
 	li	t3,0xaaaa5555		/*  put a's and 5's in t3	*/
-	mtc1	t3,fp0			/* try to write them into fp0   */	
+	mtc1	t3,fp0			/* try to write them into fp0   */
 	mtc1	zero,fp1		/* try to write zero in fp	*/
 	mfc1	t0,fp0
 	mfc1	t1,fp1
@@ -136,13 +136,13 @@ FRAME(start,sp,0,ra)
 
 	mtc0	v0, C0_SR		/* reset status register */
 2:
-	la  	gp, _gp			
+	la  	gp, _gp
 
 	la	v0,_fbss 		/* clear bss before using it */
 	la	v1,end 			/* end of bss */
 3:	sw	zero,0(v0)
 	bltu	v0,v1,3b
-	add	v0,4 
+	add	v0,4
 
 
 /************************************************************************
@@ -156,7 +156,7 @@ FRAME(start,sp,0,ra)
 *************************************************************************/
 #if __mips==3
 	/* For MIPS 3, we need to be sure that the stack is aligned on a
-	 * double word boundary. 
+	 * double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 11f   /* Last three bits Zero, already aligned */
@@ -169,11 +169,11 @@ FRAME(start,sp,0,ra)
 	add	v1, v0, TMP_STKSIZE 	/* end of bss + length of tmp stack */
 	sub	v1, v1, (4*4)		/* overhead */
 	move	sp, v1			/* set sp to top of stack */
-4:	sw	zero, 0(v0)  
+4:	sw	zero, 0(v0)
 	bltu	v0, v1, 4b		/* clear out temp stack */
-	add	v0, 4 
-	
-	jal	mips_install_isr_entries/* install exception handlers */ 
+	add	v0, 4
+
+	jal	mips_install_isr_entries/* install exception handlers */
 	nop				/* MUST do before memory probes */
 
 	la	v0, 5f
@@ -191,7 +191,7 @@ FRAME(start,sp,0,ra)
 	jal	config_Icache
 	nop
 	jal	config_Dcache		/* determine size of D & I caches */
-	nop	
+	nop
 #endif
 #ifdef _R4000
 	jal	config_cache		/* determine size of D & I caches */
@@ -202,7 +202,7 @@ FRAME(start,sp,0,ra)
 
 #if __mips==3
 	/* For MIPS 3, we need to be sure that the stack (and hence v0
-	 * here) is aligned on a double word boundary. 
+	 * here) is aligned on a double word boundary.
 	 */
 	andi	t0, v0, 0x7
 	beqz	t0, 12f   /* Last three bits Zero, already aligned */
@@ -221,9 +221,9 @@ FRAME(start,sp,0,ra)
 
 /**************************************************************************
 **
-**  Permanent Stack - now know top of memory, put permanent stack there	
+**  Permanent Stack - now know top of memory, put permanent stack there
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	la	t2, _fbss		/* cache mode as linked */
 	and	t2, 0xF0000000		/* isolate segment */
@@ -237,16 +237,16 @@ FRAME(start,sp,0,ra)
 	move	v1, v0
 	subu	v1, P_STACKSIZE 	/* clear requested stack size */
 
-7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */ 
+7:	sw	zero, 0(v1)		/* clear P_STACKSIZE  stack */
 	bltu	v1,v0,7b
-	add	v1, 4 
+	add	v1, 4
 	.set	reorder
 
-#ifdef _R3000 
-	jal	flush_Icache	
+#ifdef _R3000
+	jal	flush_Icache
 	jal	flush_Dcache		/* flush Data & Instruction caches */
 #endif
-#ifdef _R4000 
+#ifdef _R4000
 	jal	flush_cache_nowrite	/* flush Data & Instruction caches */
 #endif
 
@@ -256,7 +256,7 @@ FRAME(start,sp,0,ra)
 **
 **	If this chip supports a Translation Lookaside Buffer, clear it
 **
-***************************************************************************/ 
+***************************************************************************/
 
 	.set	noreorder
 	mfc0	t1,  C0_SR		/* look at Status Register */
@@ -265,7 +265,7 @@ FRAME(start,sp,0,ra)
 #ifdef _R3000
 	li	t2, SR_TS		/* TLB Shutdown bit */
 	and 	t1,t2      		/* TLB Shutdown if 1 */
-	bnez	t1, 8f			/* skip clearing if no TLB */	
+	bnez	t1, 8f			/* skip clearing if no TLB */
 #endif
 
 #ifndef R4650
@@ -275,7 +275,7 @@ FRAME(start,sp,0,ra)
 
 /************************************************************************
 **
-**  Initialization required if using IDT/c or libc.a, standard C Lib 
+**  Initialization required if using IDT/c or libc.a, standard C Lib
 **
 **  can SKIP if not necessary for application
 **
diff --git a/c/src/lib/libbsp/mips/p4000/startup/bspstart.c b/c/src/lib/libbsp/mips/p4000/startup/bspstart.c
index 7ff8a8e381..a9fb9bce0a 100644
--- a/c/src/lib/libbsp/mips/p4000/startup/bspstart.c
+++ b/c/src/lib/libbsp/mips/p4000/startup/bspstart.c
@@ -26,7 +26,7 @@
 #include <bsp.h>
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
- 
+
 /*
  *  The original table from the application and our copy of it with
  *  some changes.
@@ -43,7 +43,7 @@ char *rtems_progname;
 /*
  *  Use the shared implementations of the following routines
  */
- 
+
 void bsp_postdriver_hook(void);
 void bsp_libc_init( void *, uint32_t, int );
 
@@ -60,7 +60,7 @@ void bsp_libc_init( void *, uint32_t, int );
  *      not yet initialized.
  *
  */
- 
+
 #define LIBC_HEAP_SIZE (64 * 1024)
 
 void bsp_pretasking_hook(void)
@@ -78,7 +78,7 @@ void bsp_pretasking_hook(void)
     rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
 #endif
 }
- 
+
 extern int end; /* defined by linker */
 
 /*
diff --git a/c/src/lib/libbsp/mips/p4000/startup/idtmem.S b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
index 3e2b373d72..eb843984ea 100644
--- a/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
+++ b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S
@@ -34,8 +34,8 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **************************************************************************/
 
 /*
- * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack 
- * to set mem_size. 
+ * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
+ * to set mem_size.
  */
 
 #include <rtems/mips/iregdef.h>
@@ -44,12 +44,12 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
 	.data
 mem_size:
-	.word	0	
+	.word	0
 dcache_size:
-	.word 	0		
+	.word 	0
 icache_size:
 #if __mips == 1
-	.word	MINCACHE	
+	.word	MINCACHE
 #endif
 #if __mips == 3
 	.word	0
@@ -71,11 +71,11 @@ scache_linesize:
 		.text
 
 #if __mips == 1
-#define CONFIGFRM ((2*4)+4)	
+#define CONFIGFRM ((2*4)+4)
 
 /*************************************************************************
 **
-** Config_Dcache() -- determine size of Data cache 
+** Config_Dcache() -- determine size of Data cache
 **
 **************************************************************************/
 
@@ -100,7 +100,7 @@ FRAME(config_Dcache,sp, CONFIGFRM, ra)
 	addu	sp,CONFIGFRM		/* pop stack */
 	j	ra
 ENDFRAME(config_Dcache)
- 
+
 
 /*************************************************************************
 **
@@ -123,7 +123,7 @@ FRAME(config_Icache,sp, CONFIGFRM, ra)
 	.set	reorder
 	jal	_size_cache		/* returns instruction cache size */
 	.set	noreorder
-	mtc0	zero,C0_SR		/* swap back caches */  
+	mtc0	zero,C0_SR		/* swap back caches */
 	nop
 	and	s0,~SR_PE		/* do not inadvertantly clear PE */
 	mtc0	s0,C0_SR		/* restore SR */
@@ -198,7 +198,7 @@ ENDFRAME(_size_cache)
 **
 ****************************************************************************/
 FRAME(flush_Dcache,sp,FLUSHFRM,ra)
-	lw      t2, dcache_size		
+	lw      t2, dcache_size
 	.set	noreorder
 	mfc0	t3,C0_SR		/* save SR */
 	nop
@@ -240,7 +240,7 @@ ENDFRAME(flush_Dcache)
 **
 ****************************************************************************/
 FRAME(flush_Icache,sp,FLUSHFRM,ra)
-	lw	t1,icache_size 
+	lw	t1,icache_size
 	.set	noreorder
 	mfc0	t3,C0_SR		/* save SR */
 	nop
@@ -346,7 +346,7 @@ FRAME(clear_Icache,sp,0,ra)
 	 */
 	.set	noreorder
 	mfc0	t3,C0_SR		/* save SR */
-	nop 
+	nop
 	la	v0,1f
 	li	v1,K1BASE
 	or	v0,v1
@@ -386,7 +386,7 @@ ENDFRAME(clear_Icache)
 
 /**************************************************************************
 **
-**  get_mem_conf - get memory configuration 
+**  get_mem_conf - get memory configuration
 **
 ***************************************************************************/
 
@@ -398,7 +398,7 @@ FRAME(get_mem_conf,sp,0,ra)
 	lw	t7, icache_size
 	sw	t7, 4(a0)
 	lw	t8, dcache_size
-	sw	t8, 8(a0) 
+	sw	t8, 8(a0)
 	j	ra
 
 ENDFRAME(get_mem_conf)
@@ -429,24 +429,24 @@ label:
 
 /* This is a bit of a hack really because it relies on minaddr=a0 */
 #define _doop1(op1) \
-	cache	op1,0(a0) 
+	cache	op1,0(a0)
 
 #define _doop2(op1, op2) \
 	cache	op1,0(a0) ;		\
-	cache	op2,0(a0) 
+	cache	op2,0(a0)
 
 /* specials for cache initialisation */
 #define _doop1lw1(op1) \
 	cache	op1,0(a0) ;		\
 	lw	zero,0(a0) ;		\
-	cache	op1,0(a0) 
+	cache	op1,0(a0)
 
 #define _doop121(op1,op2) \
 	cache	op1,0(a0) ;		\
 	nop;				\
 	cache	op2,0(a0) ;		\
 	nop;				\
-	cache	op1,0(a0) 
+	cache	op1,0(a0)
 
 #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
 	.set	noreorder ;		\
@@ -481,7 +481,7 @@ label:
 
 /*
  * static void _size_cache()    R4000
- * 
+ *
  * Internal routine to determine cache sizes by looking at R4000 config
  * register.  Sizes are returned in registers, as follows:
  *	t2	icache size
@@ -508,20 +508,20 @@ LEAF(_size_cache)
 	and	t1,t0,CFG_IB
 	bnez	t1,1f
 	li	t4,16
-1:	
+1:
 
 	li	t5,32
 	and	t1,t0,CFG_DB
 	bnez	t1,1f
 	li	t5,16
-1:	
+1:
 
 	move	t6,zero			# default to no scache
 	move	t7,zero			#
 
 	and	t1,t0,CFG_C_UNCACHED	# test config register
 	bnez	t1,1f			# no scache if uncached/non-coherent
-	
+
 	li	t6,0x100000		# assume 1Mb scache <<-NOTE
 	and	t1,t0,CFG_SBMASK
 	srl	t1,CFG_SBSHIFT
@@ -533,7 +533,7 @@ END(_size_cache)
 
 /*
  * void config_cache()   R4000
- * 
+ *
  * Work out size of I, D & S caches, assuming they are already initialised.
  */
 LEAF(config_cache)
@@ -563,7 +563,7 @@ LEAF(_init_cache)
 	move	v0,ra
 	bal	_size_cache
 	move	ra,v0
-	
+
 	/*
 	 * The caches may be in an indeterminate state,
 	 * so we force good parity into them by doing an
@@ -603,7 +603,7 @@ LEAF(_init_cache)
 1:	mtc0	v0,C0_SR
 	j	ra
 END(_init_cache)
-	
+
 
 /*
  * void flush_cache (void)   R4000
@@ -620,7 +620,7 @@ LEAF(flush_cache)
 	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
 	b	2f
 
-1:	
+1:
 	lw	a2,icache_size
 	blez	a2,2f
 	lw	a3,icache_linesize
@@ -636,7 +636,7 @@ LEAF(flush_cache)
 
 2:	j	ra
 END(flush_cache)
-	
+
 /*
  * void flush_cache_nowrite (void)   R4000
  *
@@ -673,7 +673,7 @@ LEAF(flush_cache_nowrite)
 2:	mtc0	v0,C0_SR
 	j	ra
 END(flush_cache_nowrite)
-	
+
 /*
  * void clean_cache (unsigned kva, size_t n)   R4000
  *
@@ -706,7 +706,7 @@ XLEAF(clear_cache)
 
 2:	j	ra
 END(clean_cache)
-	
+
 /*
  * void clean_dcache (unsigned kva, size_t n)   R4000
  *
@@ -721,7 +721,7 @@ LEAF(clean_dcache)
 
 2:	j	ra
 END(clean_dcache)
-	
+
 /*
  * void clean_dcache_indexed (unsigned kva, size_t n)   R4000
  *
@@ -745,7 +745,7 @@ LEAF(clean_dcache_indexed)
 
 2:	j	ra
 END(clean_dcache_indexed)
-	
+
 /*
  * void clean_dcache_nowrite (unsigned kva, size_t n)   R4000
  *
@@ -760,7 +760,7 @@ LEAF(clean_dcache_nowrite)
 
 2:	j	ra
 END(clean_dcache_nowrite)
-	
+
 /*
  * void clean_dcache_nowrite_indexed (unsigned kva, size_t n)   R4000
  *
@@ -792,7 +792,7 @@ LEAF(clean_dcache_nowrite_indexed)
 2:	mtc0	v0,C0_SR
 	j	ra
 END(clean_dcache_nowrite_indexed)
-	
+
 /*
  * void clean_icache (unsigned kva, size_t n)   R4000
  *
@@ -807,7 +807,7 @@ LEAF(clean_icache)
 
 2:	j	ra
 END(clean_icache)
-	
+
 /*
  * void clean_icache_indexed (unsigned kva, size_t n)   R4000
  *
@@ -831,7 +831,7 @@ LEAF(clean_icache_indexed)
 
 2:	j	ra
 END(clean_icache_indexed)
-	
+
 
 
 /*
@@ -847,7 +847,7 @@ LEAF(clean_scache)
 
 2:	j	ra
 END(clean_scache)
-	
+
 /*
  * void clean_scache_indexed (unsigned kva, size_t n)   R4000
  *
@@ -862,7 +862,7 @@ LEAF(clean_scache_indexed)
 
 2:	j	ra
 END(clean_scache_indexed)
-	
+
 /*
  * void clean_scache_nowrite (unsigned kva, size_t n)   R4000
  *
@@ -877,7 +877,7 @@ LEAF(clean_scache_nowrite)
 
 2:	j	ra
 END(clean_scache_nowrite)
-	
+
 /*
  * void clean_scache_nowrite_indexed (unsigned kva, size_t n)   R4000
  *
@@ -900,7 +900,7 @@ LEAF(clean_scache_nowrite_indexed)
 2:	mtc0	v0,C0_SR
 	j	ra
 END(clean_scache_nowrite_indexed)
-	
+
 /**************************************************************************
 **
 **  get_mem_conf - get memory configuration  R4000
@@ -915,9 +915,9 @@ FRAME(get_mem_conf,sp,0,ra)
 	lw	t7, icache_size
 	sw	t7, 4(a0)
 	lw	t8, dcache_size
-	sw	t8, 8(a0) 
+	sw	t8, 8(a0)
 	lw	t7, scache_size
-	sw	t7, 12(a0) 
+	sw	t7, 12(a0)
 	j	ra
 
 ENDFRAME(get_mem_conf)
@@ -925,7 +925,7 @@ ENDFRAME(get_mem_conf)
 #endif /* __mips == 3 */
 
 /*
- * void set_mem_size (mem_size) 
+ * void set_mem_size (mem_size)
  *
  * config_memory()'s memory size gets written into mem_size here.
  * Now we don't need to call config_cache() with memory size - New to IDTC6.0
diff --git a/c/src/lib/libbsp/mips/p4000/startup/idttlb.S b/c/src/lib/libbsp/mips/p4000/startup/idttlb.S
index e1267dbbc8..bfe741afcc 100644
--- a/c/src/lib/libbsp/mips/p4000/startup/idttlb.S
+++ b/c/src/lib/libbsp/mips/p4000/startup/idttlb.S
@@ -186,7 +186,7 @@ ENDFRAME(ret_tlbhi)
 FRAME(ret_tlbpid,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	v0,C0_TLBHI		# fetch tlb high 
+	mfc0	v0,C0_TLBHI		# fetch tlb high
 	nop
 	and	v0,TLBHI_PIDMASK	# isolate and position
 	srl	v0,TLBHI_PIDSHIFT
@@ -219,8 +219,8 @@ FRAME(tlbprobe,sp,0,ra)
 	mfc0	t0,C0_SR		/* fetch status reg */
 	and	a0,TLBHI_VPNMASK	/* isolate just the vpn */
 	and	t0,~SR_PE		/* don't inadvertantly clear pe */
-	mtc0	zero,C0_SR 
-	mfc0	t1,C0_TLBHI	
+	mtc0	zero,C0_SR
+	mfc0	t1,C0_TLBHI
 	sll	a1,TLBHI_PIDSHIFT	/* possition the pid */
 	and	a1,TLBHI_PIDMASK
 	or	a0,a1			/* build entry hi value */
@@ -271,7 +271,7 @@ ENDFRAME(tlbprobe)
 FRAME(resettlb,sp,0,ra)
 #if __mips == 1
 	.set	noreorder
-	mfc0	t0,C0_TLBHI		# fetch the current hi 
+	mfc0	t0,C0_TLBHI		# fetch the current hi
 	mfc0	v0,C0_SR		# fetch the status reg.
 	li	t2,K0BASE&TLBHI_VPNMASK
 	and	v0,~SR_PE		# dont inadvertantly clear PE
@@ -329,13 +329,13 @@ FRAME(map_tlb,sp,0,ra)
 
 	mtc0	zero,C0_SR
 	mtc0	a1,C0_TLBHI		# set the hi entry
-	mtc0	a2,C0_TLBLO		# set the lo entry 
+	mtc0	a2,C0_TLBLO		# set the lo entry
 	mtc0	a0,C0_INX		# load the index
 	nop
 	tlbwi				# put the hi/lo in tlb entry indexed
 	nop
-	mtc0	a3,C0_TLBHI		# put back the tlb hi reg 
-	mtc0	v0,C0_SR		# restore the status register 
+	mtc0	a3,C0_TLBHI		# put back the tlb hi reg
+	mtc0	v0,C0_SR		# restore the status register
 	j	ra
 	nop
 	.set	reorder
@@ -357,7 +357,7 @@ FRAME(map_tlb4000,sp,0,ra)
 	mfc0	t1,C0_TLBHI		# save current TLBPID
 	mfc0	v0,C0_SR		# save SR and disable interrupts
 	mtc0	zero,C0_SR
-	mtc0	t2,C0_PAGEMASK		# set 
+	mtc0	t2,C0_PAGEMASK		# set
 	mtc0	a1,C0_TLBHI		# set VPN and TLBPID
 	mtc0	a2,C0_TLBLO0		# set PPN and access bits
 	mtc0	a3,C0_TLBLO1		# set PPN and access bits
diff --git a/c/src/lib/libbsp/mips/shared/gdbstub/gdb_if.h b/c/src/lib/libbsp/mips/shared/gdbstub/gdb_if.h
index e2d94a89e5..bc8efb72ae 100644
--- a/c/src/lib/libbsp/mips/shared/gdbstub/gdb_if.h
+++ b/c/src/lib/libbsp/mips/shared/gdbstub/gdb_if.h
@@ -55,7 +55,7 @@ int rtems_gdb_stub_get_current_thread(void);
 int rtems_gdb_stub_get_next_thread(int);
 int rtems_gdb_stub_get_offsets(
   unsigned char **text_addr,
-  unsigned char **data_addr, 
+  unsigned char **data_addr,
   unsigned char **bss_addr
 );
 int rtems_gdb_stub_get_thread_regs(
@@ -66,7 +66,7 @@ int rtems_gdb_stub_set_thread_regs(
   int thread,
   unsigned int *registers
 );
-void rtems_gdb_process_query( 
+void rtems_gdb_process_query(
   char *inbuffer,
   char *outbuffer,
   int   do_threads,
diff --git a/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c b/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
index a2d4c5fd61..fc0f867d8b 100644
--- a/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
+++ b/c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
@@ -252,7 +252,7 @@ struct z0break
 
   /* the address pointer, really, really must be a pointer to
   ** a 32 bit quantity (likely 64 on the R4k), so the full instruction is read &
-  ** written.  Making it a char * as on the i386 will cause 
+  ** written.  Making it a char * as on the i386 will cause
   ** the zbreaks to mess up the breakpoint instructions
   */
   unsigned *address;
@@ -921,7 +921,7 @@ void gdb_stub_report_exception_info(
    *optr++ = ':';
    optr    = mem2hstr(optr, (unsigned char *)&frame->sp, R_SZ );
    *optr++ = ';';
-  
+
    *optr++ = highhex(PC); /*gdb_hexchars[PC]; */
    *optr++ = lowhex(PC);
    *optr++ = ':';
@@ -929,7 +929,7 @@ void gdb_stub_report_exception_info(
    *optr++ = ';';
 
 #if defined(GDB_STUB_ENABLE_THREAD_SUPPORT)
-   if (do_threads) 
+   if (do_threads)
    {
       *optr++ = 't';
       *optr++ = 'h';
@@ -974,7 +974,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
    long long    regval;
    void         *regptr;
    int          binary;
-   
+
 
    registers = (mips_register_t *)frame;
 
@@ -991,7 +991,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
       /* reapply all breakpoints regardless of how we came in */
       struct z0break *z0, *zother;
 
-      for (zother=z0break_list; zother!=NULL; zother=zother->next) 
+      for (zother=z0break_list; zother!=NULL; zother=zother->next)
       {
          if( zother->instr == 0xffffffff )
          {
@@ -1008,9 +1008,9 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
       if( *((unsigned *)frame->epc) == BREAK_INSTR )
       {
          /* see if its one of our zbreaks */
-         for (z0=z0break_list; z0!=NULL; z0=z0->next) 
+         for (z0=z0break_list; z0!=NULL; z0=z0->next)
          {
-            if( (unsigned)z0->address == frame->epc) 
+            if( (unsigned)z0->address == frame->epc)
                break;
          }
          if( z0 )
@@ -1020,7 +1020,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
             /* flag the breakpoint */
             z0->instr = 0xffffffff;
 
-            /* 
+            /*
                now when we return, we'll execute the original code in
                the original state.  This leaves our breakpoint inactive
                since the break instruction isn't there, but we'll reapply
@@ -1208,7 +1208,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
          {
             int testThread;
 
-            if( vhstr2thread(&inBuffer[1], &testThread) == NULL ) 
+            if( vhstr2thread(&inBuffer[1], &testThread) == NULL )
             {
                strcpy(outBuffer, "E01");
                break;
@@ -1225,20 +1225,20 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
          }
          break;
 #endif
-        
+
          case 'H':  /* set new thread */
 #if defined(GDB_STUB_ENABLE_THREAD_SUPPORT)
             if (inBuffer[1] != 'g') {
                break;
             }
-	  
+
             if (!do_threads) {
                break;
             }
-	  
+
             {
                int tmp, ret;
-	    
+
                /* Set new generic thread */
                if (vhstr2thread(&inBuffer[2], &tmp) == NULL) {
                   strcpy(outBuffer, "E01");
@@ -1256,7 +1256,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
                   break;
                }
 
-               /* Save current thread registers if necessary */ 
+               /* Save current thread registers if necessary */
                if (current_thread != thread) {
                   ret = rtems_gdb_stub_set_thread_regs(
                      current_thread, (unsigned int *) &current_thread_registers);
@@ -1274,7 +1274,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
                      break;
                   }
                }
-	    
+
                current_thread = tmp;
                strcpy(outBuffer, "OK");
             }
@@ -1285,7 +1285,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
 
 
          case 'Z':  /* Add breakpoint */
-         { 
+         {
             int ret, type, len;
             unsigned *address;
             struct z0break *z0;
@@ -1334,7 +1334,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
             /* Let us copy memory from address add stuff the break point in */
             /*
             *if (mem2hstr(z0->buf, address, 1) == NULL ||
-              !hstr2mem(address, "cc" , 1)) { 
+              !hstr2mem(address, "cc" , 1)) {
 
                * Memory error *
                z0->next = z0break_avail;
@@ -1367,7 +1367,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
 
                z0->prev = NULL;
                z0->next = znxt;
-               
+
                if( znxt ) znxt->prev = z0;
                z0break_list = z0;
             }
@@ -1378,18 +1378,18 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
 
 
          case 'z': /* remove breakpoint */
-            if (inBuffer[1] == 'z') 
+            if (inBuffer[1] == 'z')
             {
                goto dumpzbreaks;
-               
+
 
                /*
                 * zz packet - remove all breaks *
                 z0last = NULL;
 
-                for (z0=z0break_list; z0!=NULL; z0=z0->next) 
+                for (z0=z0break_list; z0!=NULL; z0=z0->next)
                 {
-                if(!hstr2mem(z0->address, z0->buf, R_SZ)) 
+                if(!hstr2mem(z0->address, z0->buf, R_SZ))
                 {
                 ret = 0;
                 }
@@ -1416,7 +1416,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
                int ret, type, len;
                unsigned *address;
                struct z0break *z0;
-              
+
 
                ret = parse_zbreak(inBuffer, &type, (unsigned char **)&address, &len);
                if (!ret) {
@@ -1433,20 +1433,20 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
                   strcpy(outBuffer, "E02");
                   break;
                }
-	   
+
                /* Let us check whether this break point set */
                for (z0=z0break_list; z0!=NULL; z0=z0->next) {
                   if (z0->address == address) {
                      break;
                   }
                }
-              
+
                if (z0 == NULL) {
                   /* Unknown breakpoint */
                   strcpy(outBuffer, "E03");
                   break;
                }
-	    
+
                /*
                if (!hstr2mem(z0->address, z0->buf, R_SZ)) {
                   strcpy(outBuffer, "E04");
@@ -1458,7 +1458,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
                   /* put the old instruction back  */
                   *(z0->address) = z0->instr;
                }
-   
+
                /* Unlink entry */
                {
                   struct z0break *zprv = z0->prev, *znxt = z0->next;
@@ -1474,7 +1474,7 @@ void handle_exception (rtems_vector_number vector, CPU_Interrupt_frame *frame)
                   z0->prev = NULL;
                   z0->next = znxt;
                }
-    
+
                strcpy(outBuffer, "OK");
             }
             break;
@@ -1605,7 +1605,7 @@ static int is_steppable(unsigned ptr)
 
 static char initialized = 0;   /* 0 means we are not initialized */
 
-void mips_gdb_stub_install(int enableThreads) 
+void mips_gdb_stub_install(int enableThreads)
 {
    /*
      These are the RTEMS-defined vectors for all the MIPS exceptions
@@ -1632,7 +1632,7 @@ void mips_gdb_stub_install(int enableThreads)
    int  i;
    rtems_isr_entry old;
 
-   if (initialized) 
+   if (initialized)
    {
       ASSERT(0);
       return;
@@ -1653,16 +1653,16 @@ void mips_gdb_stub_install(int enableThreads)
 
       z0break_avail = NULL;
       z0break_list  = NULL;
-   
+
       /* z0breaks list init, now we'll do it so it makes sense... */
-      for (i=0; i<BREAKNUM; i++) 
+      for (i=0; i<BREAKNUM; i++)
       {
          memset( (z0= &z0break_arr[i]), 0, sizeof(struct z0break));
 
          z0->next = z0break_avail;
          z0break_avail = z0;
       }
-   }     
+   }
 
    for(i=0; exceptionVector[i] > -1; i++)
    {