diff options
Diffstat (limited to 'c/src/lib/libbsp/mips/p4000/start/start.S')
| -rw-r--r-- | c/src/lib/libbsp/mips/p4000/start/start.S | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/c/src/lib/libbsp/mips/p4000/start/start.S b/c/src/lib/libbsp/mips/p4000/start/start.S index 1421c8b8d2..4bcd885e6a 100644 --- a/c/src/lib/libbsp/mips/p4000/start/start.S +++ b/c/src/lib/libbsp/mips/p4000/start/start.S @@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT $Id$ -*/ +*/ /************************************************************************* ** @@ -44,7 +44,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT .text -#define TMP_STKSIZE 1024 +#define TMP_STKSIZE 1024 /************************************************************************** ** @@ -57,7 +57,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT ** c) Clear all IntMask Enables ** d) Set kernel/disabled mode ** 2) Initialize Cause Register -** a) clear software interrupt bits +** a) clear software interrupt bits ** 3) Determine FPU installed or not ** if not, clear CoProcessor 1 usable bit ** 4) Clear bss area @@ -69,15 +69,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT ** 9) Flush Instruction and Data caches ** 10) If there is a Translation Lookaside Buffer, Clear the TLB ** 11) Execute initialization code if the IDT/c library is to be used -** +** ** 12) Jump to user's "main()" (boot_card() for RTEMS) ** 13) Jump to promexit ** -** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. ** This is used to mark code specific to R3xxx or R4xxx processors. -** IDT/C 6.x defines __mips to be the ISA level for which we're -** generating code. This is used to make sure the stack etc. is -** double word aligned, when using -mips3 (default) or -mips2, +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, ** when compiling with IDT/C6.x ** ***************************************************************************/ @@ -109,10 +109,10 @@ FRAME(start,sp,0,ra) #endif /* -** check to see if an fpu is really plugged in +** check to see if an fpu is really plugged in */ li t3,0xaaaa5555 /* put a's and 5's in t3 */ - mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 t3,fp0 /* try to write them into fp0 */ mtc1 zero,fp1 /* try to write zero in fp */ mfc1 t0,fp0 mfc1 t1,fp1 @@ -136,13 +136,13 @@ FRAME(start,sp,0,ra) mtc0 v0, C0_SR /* reset status register */ 2: - la gp, _gp + la gp, _gp la v0,_fbss /* clear bss before using it */ la v1,end /* end of bss */ 3: sw zero,0(v0) bltu v0,v1,3b - add v0,4 + add v0,4 /************************************************************************ @@ -156,7 +156,7 @@ FRAME(start,sp,0,ra) *************************************************************************/ #if __mips==3 /* For MIPS 3, we need to be sure that the stack is aligned on a - * double word boundary. + * double word boundary. */ andi t0, v0, 0x7 beqz t0, 11f /* Last three bits Zero, already aligned */ @@ -169,11 +169,11 @@ FRAME(start,sp,0,ra) add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ sub v1, v1, (4*4) /* overhead */ move sp, v1 /* set sp to top of stack */ -4: sw zero, 0(v0) +4: sw zero, 0(v0) bltu v0, v1, 4b /* clear out temp stack */ - add v0, 4 - - jal mips_install_isr_entries/* install exception handlers */ + add v0, 4 + + jal mips_install_isr_entries/* install exception handlers */ nop /* MUST do before memory probes */ la v0, 5f @@ -191,7 +191,7 @@ FRAME(start,sp,0,ra) jal config_Icache nop jal config_Dcache /* determine size of D & I caches */ - nop + nop #endif #ifdef _R4000 jal config_cache /* determine size of D & I caches */ @@ -202,7 +202,7 @@ FRAME(start,sp,0,ra) #if __mips==3 /* For MIPS 3, we need to be sure that the stack (and hence v0 - * here) is aligned on a double word boundary. + * here) is aligned on a double word boundary. */ andi t0, v0, 0x7 beqz t0, 12f /* Last three bits Zero, already aligned */ @@ -221,9 +221,9 @@ FRAME(start,sp,0,ra) /************************************************************************** ** -** Permanent Stack - now know top of memory, put permanent stack there +** Permanent Stack - now know top of memory, put permanent stack there ** -***************************************************************************/ +***************************************************************************/ la t2, _fbss /* cache mode as linked */ and t2, 0xF0000000 /* isolate segment */ @@ -237,16 +237,16 @@ FRAME(start,sp,0,ra) move v1, v0 subu v1, P_STACKSIZE /* clear requested stack size */ -7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ bltu v1,v0,7b - add v1, 4 + add v1, 4 .set reorder -#ifdef _R3000 - jal flush_Icache +#ifdef _R3000 + jal flush_Icache jal flush_Dcache /* flush Data & Instruction caches */ #endif -#ifdef _R4000 +#ifdef _R4000 jal flush_cache_nowrite /* flush Data & Instruction caches */ #endif @@ -256,7 +256,7 @@ FRAME(start,sp,0,ra) ** ** If this chip supports a Translation Lookaside Buffer, clear it ** -***************************************************************************/ +***************************************************************************/ .set noreorder mfc0 t1, C0_SR /* look at Status Register */ @@ -265,7 +265,7 @@ FRAME(start,sp,0,ra) #ifdef _R3000 li t2, SR_TS /* TLB Shutdown bit */ and t1,t2 /* TLB Shutdown if 1 */ - bnez t1, 8f /* skip clearing if no TLB */ + bnez t1, 8f /* skip clearing if no TLB */ #endif #ifndef R4650 @@ -275,7 +275,7 @@ FRAME(start,sp,0,ra) /************************************************************************ ** -** Initialization required if using IDT/c or libc.a, standard C Lib +** Initialization required if using IDT/c or libc.a, standard C Lib ** ** can SKIP if not necessary for application ** |