added Motorola MVME147 BSP submitted by Dominique le Campion

(Dominique.LECAMPION@enst-bretagne.fr), for Telecom Bretagne and
T.N.I. (Brest, France)

2 files changed, 112 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/m68k/mvme147/timer/timer.c b/c/src/lib/libbsp/m68k/mvme147/timer/timer.c
new file mode 100644
index 0000000000..aec88756dc
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/mvme147/timer/timer.c
@@ -0,0 +1,84 @@
+/*  Timer_init()
+ *
+ *  This routine initializes the PCC timer on the MVME147 board.
+ *
+ *  Input parameters:  NONE
+ *
+ *  Output parameters:  NONE
+ *
+ *  NOTE: It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  MVME147 port for TNI - Telecom Bretagne
+ *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
+ *  May 1996
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+
+#define TIMER_INT_LEVEL 6
+
+#define COUNTDOWN_VALUE 0
+/* Allows 0.4096 second delay betwin ints */
+/* Each tick is 6.25 us */
+
+int Ttimer_val;
+rtems_boolean Timer_driver_Find_average_overhead;
+
+rtems_isr timerisr();
+
+void Timer_initialize()
+{
+  (void) set_vector(timerisr, TIMER_1_VECTOR, 0); /* install ISR */
+
+  Ttimer_val = 0;                 /* clear timer ISR count */
+  pcc->timer1_int_control = 0x00; /* Disable T1 Interr. */
+  pcc->timer1_preload = COUNTDOWN_VALUE;
+  /* write countdown preload value */
+  pcc->timer1_control = 0x00; /* load preload value */
+  pcc->timer1_control = 0x07; /* clear T1 overflow counter, enable counter */
+  pcc->timer1_int_control = TIMER_INT_LEVEL|0x08; 
+  /* Enable Timer 1 and set its int. level */
+  
+}
+
+#define AVG_OVERHEAD      0  /* No need to start/stop the timer to read
+				its value on the MVME147 PCC: reads are not
+				synchronized whith the counter updates*/
+#define LEAST_VALID       10 /* Don't trust a value lower than this */
+
+int Read_timer()
+{
+  rtems_unsigned32 total;
+  rtems_unsigned16 counter_value;
+
+  counter_value = pcc->timer1_count; /* read the counter value */
+
+  total = ((Ttimer_val * 0x10000) + counter_value); /* in 6.25 us units */
+  /* DC note : just look at the assembly generated
+     to see gcc's impressive optimization ! */
+  return total;
+
+}
+
+rtems_status_code Empty_function( void )
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(
+  rtems_boolean find_flag
+)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}
diff --git a/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s b/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s
new file mode 100644
index 0000000000..a4102ffc91
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/mvme147/timer/timerisr.s
@@ -0,0 +1,28 @@
+#  timer_isr()
+#
+#  This routine provides the ISR for the PCC timer on the MVME147
+#  board.   The timer is set up to generate an interrupt at maximum
+#  intervals.
+#
+#  MVME147 port for TNI - Telecom Bretagne
+#  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
+#  May 1996
+#
+#  $Id$
+#
+
+#include "asm.h"
+
+BEGIN_CODE
+
+.set T1_CONTROL_REGISTER,  0xfffe1018    | timer 1 control register
+
+        PUBLIC (timerisr)
+SYM (timerisr):
+	orb	#0x80, T1_CONTROL_REGISTER | clear T1 int status bit
+        addql   #1, SYM (Ttimer_val)     | increment timer value
+end_timerisr:
+	rte	
+
+END_CODE
+END