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author | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 10:43:04 +0000 |
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committer | Ralf Corsepius <ralf.corsepius@rtems.org> | 2004-04-21 10:43:04 +0000 |
commit | 6128a4aa5e791ed4e0a655bfd346a52d92da7883 (patch) | |
tree | af53ca3f67ce405b6fbc6c98399c8e0c87e01a9e /c/src/lib/libbsp/arm/vegaplus/start | |
parent | 2004-04-20 Ralf Corsepius <ralf_corsepius@rtems.org> (diff) | |
download | rtems-6128a4aa5e791ed4e0a655bfd346a52d92da7883.tar.bz2 |
Remove stray white spaces.
Diffstat (limited to 'c/src/lib/libbsp/arm/vegaplus/start')
-rw-r--r-- | c/src/lib/libbsp/arm/vegaplus/start/start.S | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/c/src/lib/libbsp/arm/vegaplus/start/start.S b/c/src/lib/libbsp/arm/vegaplus/start/start.S index e811d1cac8..6c3c2ab141 100644 --- a/c/src/lib/libbsp/arm/vegaplus/start/start.S +++ b/c/src/lib/libbsp/arm/vegaplus/start/start.S @@ -9,7 +9,7 @@ * http://www.rtems.com/license/LICENSE. * */ - + /* Register definition */ .equ CNTL_BASE_ADR, 0xF3000 /* Base address of registers */ @@ -22,7 +22,7 @@ .equ CSCNTL1_2, 0x0C28 /* Offset of CS0CNTL */ .equ CNTL_CLK_ADR, 0xF2000 /* Base address of registers */ .equ CLKCNTL, 0x08F4 /* Offset of CS0CNTL */ -.equ INTHPAI, 0x0800 +.equ INTHPAI, 0x0800 .equ INTEOI, 0x0808 .equ EOI, 0x80 @@ -47,37 +47,37 @@ .equ MARK_STACK, 0 /*Fill every stack with a pattern for debug (0 or 1)*/ - + /*----------------------------------------------------------------------------- * Definitions ----------------------------------------------------------------------------*/ .equ PID_RAM_Limit, 0x1800 /* stack size definition */ -.equ FIQ_StackSize, 0x400 /* FIQ stack size */ -.equ IRQ_StackSize, 0xE00 /* IRQ stack size */ -.equ SVC_StackSize, 0x200 /* SVC stack size */ -.equ ABORT_StackSize, 0x100 /* ABORT stack size */ -.equ UNDEF_StackSize, 0x100 /* UNDEF stack size */ +.equ FIQ_StackSize, 0x400 /* FIQ stack size */ +.equ IRQ_StackSize, 0xE00 /* IRQ stack size */ +.equ SVC_StackSize, 0x200 /* SVC stack size */ +.equ ABORT_StackSize, 0x100 /* ABORT stack size */ +.equ UNDEF_StackSize, 0x100 /* UNDEF stack size */ /* sack size address */ -.equ Stack_Limit, PID_RAM_Limit +.equ Stack_Limit, PID_RAM_Limit .equ SVC_Stack, Stack_Limit -.equ ABORT_Stack, Stack_Limit - SVC_StackSize -.equ UNDEF_Stack, ABORT_Stack - ABORT_StackSize -.equ IRQ_Stack, UNDEF_Stack - UNDEF_StackSize -.equ FIQ_Stack, IRQ_Stack - IRQ_StackSize +.equ ABORT_Stack, Stack_Limit - SVC_StackSize +.equ UNDEF_Stack, ABORT_Stack - ABORT_StackSize +.equ IRQ_Stack, UNDEF_Stack - UNDEF_StackSize +.equ FIQ_Stack, IRQ_Stack - IRQ_StackSize .equ END_FIQ, FIQ_Stack - FIQ_StackSize .text .globl _start -/* +/* * This "strange" code is used to switch the memory access - * from 8 bits to 16 bits, because the vega plus accesses + * from 8 bits to 16 bits, because the vega plus accesses * the memory via 8 bits at reset time */ - + _start: .long 0x00300010 /*LDR r3,0x18*/ .long 0x00E5009F @@ -106,7 +106,7 @@ _start: .code 32 /* --- Initialise external bus*/ -Real_start: +Real_start: MOV r0,#CNTL_BASE_ADR /*Load timing configuration of CS0*/ @@ -116,7 +116,7 @@ Real_start: STR r1, [r0,#CSCNTL1_0] /* Load timing configuration and access mode of CS1 - NOTE : Important for macro REGION_INIT of Region_init.s + NOTE : Important for macro REGION_INIT of Region_init.s if initialisation of data in external RAM */ LDR r1, =0x2200 STR r1, [r0,#CSCNTL0_1] @@ -128,7 +128,7 @@ Real_start: STR r1, [r0,#CSCNTL0_2] LDR r1, =0xA2 STR r1, [r0,#CSCNTL1_2] - + MOV r0,#CNTL_CLK_ADR /* Load clock mode 55 MHz */ @@ -140,7 +140,7 @@ Real_start: LDR r1, =0x400000 /* execution address of region */ LDR r2, =_edata /* copy execution address into r2 */ -copy: +copy: CMP r1, r2 /* loop whilst r1 < r2 */ LDRLO r3, [r0], #4 STRLO r3, [r1], #4 @@ -149,15 +149,15 @@ copy: /* zero the bss */ LDR r1, =__bss_end__ /* get end of ZI region */ LDR r0, =__bss_start__ /* load base address of ZI region */ -zi_init: +zi_init: MOV r2, #0 CMP r0, r1 /* loop whilst r0 < r1 */ STRLOT r2, [r0], #4 - BLO zi_init + BLO zi_init + - /* Load basic ARM7 interrupt table */ -VectorInit: +VectorInit: MOV R8, #0 ADR R9, Vector_Init_Block LDMIA R9!, {R0-R7} /* Copy the Vectors (8 words) */ @@ -169,10 +169,10 @@ VectorInit: /******************************************************* standard exception vectors table - *** Must be located at address 0 -********************************************************/ + *** Must be located at address 0 +********************************************************/ -Vector_Init_Block: +Vector_Init_Block: LDR PC, Reset_Addr LDR PC, Undefined_Addr LDR PC, SWI_Addr @@ -183,36 +183,36 @@ Vector_Init_Block: LDR PC, FIQ_Addr .globl Reset_Addr -Reset_Addr: .long _start +Reset_Addr: .long _start Undefined_Addr: .long Undefined_Handler SWI_Addr: .long SWI_Handler Prefetch_Addr: .long Prefetch_Handler Abort_Addr: .long Abort_Handler - .long 0 + .long 0 IRQ_Addr: .long IRQ_Handler FIQ_Addr: .long FIQ_Handler - + /* The following handlers do not do anything useful */ .globl Undefined_Handler -Undefined_Handler: +Undefined_Handler: B Undefined_Handler .globl SWI_Handler -SWI_Handler: - B SWI_Handler +SWI_Handler: + B SWI_Handler .globl Prefetch_Handler -Prefetch_Handler: +Prefetch_Handler: B Prefetch_Handler .globl Abort_Handler -Abort_Handler: +Abort_Handler: B Abort_Handler .globl IRQ_Handler -IRQ_Handler: +IRQ_Handler: B IRQ_Handler .globl FIQ_Handler -FIQ_Handler: +FIQ_Handler: B FIQ_Handler -init2 : +init2 : /* --- Initialise stack pointer registers Set up the ABORT stack pointer last and stay in SVC mode */ MOV r0, #(Mode_ABORT | I_Bit | F_Bit) /* No interrupts */ |