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| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /bsps/riscv/riscv/start/bsp_fatal_halt.c | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to 'bsps/riscv/riscv/start/bsp_fatal_halt.c')
| -rw-r--r-- | bsps/riscv/riscv/start/bsp_fatal_halt.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c index d9708661a7..fb0787c606 100644 --- a/bsps/riscv/riscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -41,6 +41,9 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) #if RISCV_ENABLE_HTIF_SUPPORT != 0 htif_poweroff(); #endif +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + for(;;); +#endif fdt = bsp_fdt_get(); node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0"); |