diff options
| author | Chris Johns <chrisj@rtems.org> | 2017-12-23 18:18:56 +1100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-25 08:45:26 +0100 |
| commit | 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch) | |
| tree | 44759efe9374f13200a97e96d91bd9a2b7e5ce2a /bsps/powerpc | |
| parent | MAINTAINERS: Add myself to Write After Approval. (diff) | |
| download | rtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2 | |
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
Diffstat (limited to 'bsps/powerpc')
220 files changed, 87172 insertions, 0 deletions
diff --git a/bsps/powerpc/beatnik/headers.am b/bsps/powerpc/beatnik/headers.am new file mode 100644 index 0000000000..36df3cd759 --- /dev/null +++ b/bsps/powerpc/beatnik/headers.am @@ -0,0 +1,22 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gt_timer.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gti2creg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtintrreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtpcireg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/gtreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_em_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/if_mve_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/beatnik/include/bsp/irq.h diff --git a/bsps/powerpc/beatnik/include/bsp.h b/bsps/powerpc/beatnik/include/bsp.h new file mode 100644 index 0000000000..e980f1a056 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp.h @@ -0,0 +1,297 @@ +/* + * bsp.h -- contain BSP API definition. + */ + +/* + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. + * + * Modified for the 'beatnik' BSP by T. Straumann, 2005-2007. + */ + +#ifndef LIBBSP_BEATNIK_BSP_H +#define LIBBSP_BEATNIK_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <libcpu/io.h> +#include <bsp/vectors.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Board type */ +typedef enum { + Unknown = 0, + MVME5500, + MVME6100 +} BSP_BoardType; + +BSP_BoardType BSP_getBoardType(void); + +/* Discovery Version */ + +typedef enum { + unknown = 0, + GT_64260_A, /* Revision 0x10 */ + GT_64260_B, /* Revision 0x20 */ + MV_64360, +} DiscoveryVersion; + +/* Determine the type of discovery chip on this board; info + * is cached and repeated calls just return the cached value. + * + * If a non-zero argument is passed, the routine panics + * (rtems_panic) if no recognized bridge is found; + */ +DiscoveryVersion BSP_getDiscoveryVersion(int assertion); + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +/* + * base address definitions for several devices + */ +#define BSP_MV64x60_BASE (0xf1000000) +#define BSP_MV64x60_DEV1_BASE (0xf1100000) +#define BSP_UART_IOBASE_COM1 ((BSP_MV64x60_DEV1_BASE)+0x20000) +#define BSP_UART_IOBASE_COM2 ((BSP_MV64x60_DEV1_BASE)+0x21000) +#define BSP_UART_USE_SHARED_IRQS + +#define BSP_NVRAM_BASE_ADDR (0xf1110000) +#define BSP_NVRAM_END_ADDR (0xf1117fff) +#define BSP_NVRAM_RTC_START (0xf1117ff8) + +#define BSP_NVRAM_BOOTPARMS_START (0xf1111000) +#define BSP_NVRAM_BOOTPARMS_END (0xf1111fff) + + +/* This is only active/used during early init. It defines + * the hose0 base for the shared/generic pci code. + * Our own BSP specific pci initialization will then + * override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize) + */ + +#define PCI_CONFIG_ADDR (BSP_MV64x60_BASE + 0xcf8) +#define PCI_CONFIG_DATA (BSP_MV64x60_BASE + 0xcfc) + +/* our wonderful PCI initialization remaps everything to CPU addresses + * - before calling BSP_pci_initialize() this is NOT VALID, however + * and the deprecated inl()/outl() etc won't work! + */ +#define _IO_BASE 0x00000000 +/* wonderful MotLoad has the base address as seen from the + * CPU programmed into config space :-) + */ +#define PCI_MEM_BASE 0 +#define PCI_MEM_BASE_ADJUSTMENT 0 +#define PCI_DRAM_OFFSET 0 + +extern void BSP_motload_pci_fixup(void); + +/* PCI <-> local address mapping - no sophisticated windows + * (i.e., no support for cached regions etc. you read a BAR + * from config space and that's 1:1 where the CPU sees it). + * Our memory is mapped 1:1 to PCI also. + */ +#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a)) +#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a)) + +#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS 32 + +#define BSP_CONSOLE_PORT BSP_UART_COM1 +#define BSP_UART_BAUD_BASE 115200 + +/* I2C Devices */ +/* Note that the i2c addresses stated in the manual are + * left-shifted by one bit. + */ +#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ +#define BSP_USR_I2C_ADDR (0xAA>>1) /* the user EEPROM */ +#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ + +#define BSP_I2C_BUS_DESCRIPTOR gt64260_i2c_bus_descriptor + +#define BSP_I2C_BUS0_NAME "/dev/i2c0" + +#define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" +#define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" +#define BSP_I2C_DS1621_NAME "ds1621" +#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME +#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" + +#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) +#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) +#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) +#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME +#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) + + +/* Initialize the I2C driver and register all devices + * RETURNS 0 on success, -1 on error. + * + * Access to the VPD and user EEPROMS as well + * as the ds1621 temperature sensor is possible + * by means of file nodes + * + * /dev/i2c0.vpd-eeprom (read-only) + * /dev/i2c0.usr-eeprom (read-write) + * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) + * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) + */ +int BSP_i2c_initialize(void); + +/* Networking; */ +#if defined(RTEMS_NETWORKING) +#include <bsp/bsp_bsdnet_attach.h> +#endif + +/* NOT FOR PUBLIC USE BELOW HERE */ +#define BSP_PCI_HOSE0_MEM_BASE 0x80000000 /* must be aligned to size */ +#define BSP_PCI_HOSE0_MEM_SIZE 0x20000000 + +#define BSP_PCI_HOSE1_MEM_BASE 0xe0000000 + +#define BSP_DEV_AND_PCI_IO_BASE 0xf0000000 +#define BSP_DEV_AND_PCI_IO_SIZE 0x10000000 + +/* maintain coherency between CPU and GT64340 Ethernet + * (andpossibly other Discovery components). + */ +#define BSP_RW_PAGE_ATTRIBUTES TRIV121_ATTR_M + +extern unsigned BSP_pci_hose1_bus_base; + +void BSP_pci_initialize(void); + +/* Exception Handling */ + +/* Use a task notepad to attach user exception handler info; + * may be changed by application startup code (EPICS uses 11) + */ +#define BSP_EXCEPTION_NOTEPAD 14 + +#ifndef ASM + +#define outport_byte(port,value) outb(value,port) +#define outport_word(port,value) outw(value,port) +#define outport_long(port,value) outl(value,port) + +#define inport_byte(port,value) (value = inb(port)) +#define inport_word(port,value) (value = inw(port)) +#define inport_long(port,value) (value = inl(port)) +/* + * Vital Board data Start using DATA RESIDUAL + */ +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * Start of the heap + */ +extern unsigned int BSP_heap_start; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +extern char BSP_productIdent[20]; +extern char BSP_serialNumber[20]; + +extern char BSP_enetAddr0[7]; +extern char BSP_enetAddr1[7]; + +/* + * The commandline as passed from the bootloader. + */ +extern char *BSP_commandline_string; + + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +extern rtems_configuration_table BSP_Configuration; +extern void bsp_reset(void); +extern int BSP_disconnect_clock_handler (void); +extern int BSP_connect_clock_handler (void); + +/* clear hostbridge errors + * + * enableMCP: whether to enable MCP checkstop / machine check interrupts + * on the hostbridge and in HID0. + * + * NOTE: The 5500 and 6100 boards have NO PHYSICAL CONNECTION + * to MCP so 'enableMCP' will always fail! + * + * quiet : be silent + * + * RETURNS : PCI status (hose 0 in byte 0, host 1 in byte 1) and + * VME bridge status (upper 16 bits). + * Zero if no errors were found. + */ +extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* clear vme bridge errors and return (bridge-dependent) 16-bit status + * + * quiet : be silent + * + * RETURNS : 0 if there were no errors, non-zero, bridge-dependent + * 16-bit error status on error. + * + */ +extern unsigned short (*_BSP_clear_vmebridge_errors)(int); + +/* + * Prototypes for debug helpers + */ +void discovery_pic_set_debug_irq(int on); +void discovery_pic_install_debug_irq(void); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +uint32_t probeMemoryEnd(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/VMEConfig.h b/bsps/powerpc/beatnik/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..986a01674e --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/VMEConfig.h @@ -0,0 +1,114 @@ +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H + +/* BSP specific address space configuration parameters */ + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#define _VME_DRIVER_TSI148 +#define _VME_DRIVER_UNIVERSE + +/* + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout when setting BATs: + */ +#define _VME_A32_WIN0_ON_PCI 0x90000000 +/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate + * CSR for space. + */ +#define _VME_CSR_ON_PCI 0x9e000000 +#define _VME_A24_ON_PCI 0x9f000000 +#define _VME_A16_ON_PCI 0x9fff0000 + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map our RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0x90000000 + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +#define BSP_VME_INSTALL_IRQ_MGR(err) \ + do { \ + err = -1; \ + switch (BSP_getBoardType()) { \ + case MVME6100: \ + err = theOps->install_irq_mgr( \ + VMETSI148_IRQ_MGR_FLAG_SHARED, \ + 0, BSP_IRQ_GPP_0 + 20, \ + 1, BSP_IRQ_GPP_0 + 21, \ + 2, BSP_IRQ_GPP_0 + 22, \ + 3, BSP_IRQ_GPP_0 + 23, \ + -1); \ + break; \ +\ + case MVME5500: \ + err = theOps->install_irq_mgr( \ + VMEUNIVERSE_IRQ_MGR_FLAG_SHARED | \ + VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND, \ + 0, BSP_IRQ_GPP_0 + 12, \ + 1, BSP_IRQ_GPP_0 + 13, \ + 2, BSP_IRQ_GPP_0 + 14, \ + 3, BSP_IRQ_GPP_0 + 15, \ + -1); \ + break; \ +\ + default: \ + printk("WARNING: unknown board; "); \ + break; \ + } \ + if ( err ) \ + printk("VME interrupt manager NOT INSTALLED (error: %i)\n", err); \ + } while (0) + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h b/bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h new file mode 100644 index 0000000000..a12e9e2c86 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/bsp_bsdnet_attach.h @@ -0,0 +1,79 @@ +#ifndef BSP_BSDNET_ATTACH_INFO_H +#define BSP_BSDNET_ATTACH_INFO_H + +/* Author: Till Straumann, 2005; see ../../LICENSE */ + +/* Rationale: traditionally, BSPs only supported a single networking interface + * the BSP defined RTEMS_NETWORK_DRIVER_NAME & friends macros + * for applications to use. + * If more than one interface is present, this simple approach is + * not enough. + * Hence, this BSP exports a routine declaring all available interfaces + * so the application can make a choice. + */ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Fwd. decl just in case */ +struct rtems_bsdnet_ifconfig; + +typedef struct { + /* name of the interface */ + const char *name; + /* optional description (to be used by chooser 'help' function etc.) */ + const char *description; + /* driver 'attach' function */ + int (*attach_fn)(struct rtems_bsdnet_ifconfig*, int); +} BSP_NetIFDescRec, *BSP_NetIFDesc; + +/* Return a pointer to the (static) list of network interface descriptions + * of this board. + * + * NOTES: A NULL value is returned if e.g., the board type cannot be determined + * or for other reasons. + * The 'description' field is optional, i.e., may be NULL. + * The list is terminated by an element with a NULL name field. + * The interfaces are listed in the order they are labelled. + */ + +BSP_NetIFDesc +BSP_availableNetIFs(); + +/* Define this macro so applications can conditionally compile this API */ +#define BSP_HAS_MULTIPLE_NETIFS(x) BSP_availableNetIFs() + +/* Legacy macro; applications should use BSP_Available_NetIfs() to choose + * an interface and attach function. + */ +extern char BSP_auto_network_driver_name[20]; +#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_auto_network_driver_name + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_auto_enet_attach + +/* This routine checks the name field passed in the 'ifconfig'. + * If the name is NULL or points to the BSP_auto_network_driver_name + * array, the routine checks all interfaces for an active link and + * attaches the first alive one. + * It also updates 'ifconfig' to reflect the chosen interface's name + * and attach function. + * + * If another name is passed in, the routine scans + * the available interfaces for that name and uses it, if found. + * Eventually, a default interface is chosen (provided that + * the board type is successfully detected). + * + * Note that only ONE interface chained into rtems_bsdnet_config + * may use the "auto" name. + * + */ + +int +BSP_auto_enet_attach(struct rtems_bsdnet_ifconfig *ifconfig, int attaching); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h b/bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h new file mode 100644 index 0000000000..74160a3b84 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/early_enet_link_status.h @@ -0,0 +1,30 @@ +#ifndef BSP_EARLY_ENET_LINK_STATUS_H +#define BSP_EARLY_ENET_LINK_STATUS_H + +/* Determine link status of ethernet device before network is initialized */ + +/* T. Straumann, 2005; see ../../LICENSE */ + +#include <rtems.h> + +#ifdef __cplusplus + extern "C" { +#endif + +typedef struct { + int (*init)(int idx); /* perform enough initialization to access (default) phy */ + int (*read_phy)(int idx, unsigned reg); + int (*write_phy)(int idx, unsigned reg, unsigned val); + const char *name; /* driver name */ + unsigned char num_slots; /* max number of supported devices */ + unsigned char initialized; /* must be initialized to 0; */ +} rtems_bsdnet_early_link_check_ops; + +int +BSP_early_check_link_status(int unit, rtems_bsdnet_early_link_check_ops *ops); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/gt_timer.h b/bsps/powerpc/beatnik/include/bsp/gt_timer.h new file mode 100644 index 0000000000..4a68971d13 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gt_timer.h @@ -0,0 +1,133 @@ +#ifndef BSP_GT_TIMER_H +#define BSP_GT_TIMER_H + +/* Support for hardware timers in the discovery bridge */ + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/* Obtain the number of hardware timers present + * The 'timer' argument in the routines below addresses + * one of 0..(BSP_timer_instances()-1) + */ +int BSP_timer_instances(void); + +/* Setup timer but don't start yet; interrupts are enabled if an isr argument is passed + * no interrupts are generated otherwise. + * + * If 'reload' is nonzero then the period is automatically restarted. + * + * RETURNS: 0 on success, nonzero on error (argument error) + * + * NOTE: If an ISR is already connected, it must be removed by passing a NULL isr first. + */ +int BSP_timer_setup(uint32_t timer, void (*isr)(void *arg), void *arg, int reload); + +/* Stop timer; + * + * RETURNS: 0 on success, nonzero on argument error + */ +int BSP_timer_stop(uint32_t timer); + +/* Start timer with 'period' (in ticks) + * + * RETURNS: 0 on success, nonzero on argument error + */ +int BSP_timer_start(uint32_t timer, uint32_t period); + +/* read decrementing timer on the fly + * + * RETURNS: current count in ticks + */ +uint32_t BSP_timer_read(uint32_t timer); + +/* get clock rate in Hz */ +uint32_t BSP_timer_clock_get(uint32_t timer); + +/* Initialize timer facility -- to be used by BSP implementors only + * + * RETURNS: 0 on success, nonzero if ISR wrapper couldn't be installed + */ +int BSP_timers_initialize(void); + +/* WATCHDOG TIMER (resets board if enabled and not 'petted' for + * some time). + */ + +/* Enable watchdog and set a timeout (in us) + * RETURNS 0 on success + */ +int BSP_watchdog_enable(uint32_t timeout_us); + +/* Disable watchdog + * RETURNS 0 on success + */ +int BSP_watchdog_disable(void); + +/* Check status -- unfortunately there seems to be no way + * to read the running value... + * + * RETURNS nonzero if enabled/running, zero if disabled/stopped + */ +int BSP_watchdog_status(void); + +/* Pet the watchdog (rearm to configured timeout) + * RETURNS: 0 on success, nonzero on failure (watchdog + * currently not running). + */ +int BSP_watchdog_pet(void); + + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h b/bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h new file mode 100644 index 0000000000..b75e16cdf8 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gti2c_busdrv.h @@ -0,0 +1,62 @@ +#ifndef GT_64260_BUS_DRIVER_H +#define GT_64260_BUS_DRIVER_H +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#include <rtems.h> +#include <rtems/libi2c.h> + +/* for registration with libi2c */ +extern rtems_libi2c_bus_t *gt64260_i2c_bus_descriptor; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/gti2creg.h b/bsps/powerpc/beatnik/include/bsp/gti2creg.h new file mode 100644 index 0000000000..33e566f5bc --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gti2creg.h @@ -0,0 +1,83 @@ +/* $NetBSD: gti2creg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */ + +/* + * Copyright (c) 2005 Brocade Communcations, inc. + * All rights reserved. + * + * Written by Matt Thomas for Brocade Communcations, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of Brocade Communications, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_MARVELL_GTI2CREG_H_ +#define _DEV_MARVELL_GTI2CREG_H_ + +#define I2C_REG_SlaveAddr 0xc000 +#define I2C_REG_ExtSlaveAddr 0xc010 +#define I2C_REG_Data 0xc004 +#define I2C_REG_Control 0xc008 +#define I2C_REG_Status 0xc00c +#define I2C_REG_BaudRate 0xc00c +#define I2C_REG_SoftReset 0xc01c + +#define I2C_SlaveAddr_GCE 0x0001 /* Act as Slave */ +#define I2C_SlaveAddr_SAddr 0x7E + +#define I2C_Control_ACK 0x04 +#define I2C_Control_IFlg 0x08 +#define I2C_Control_Stop 0x10 +#define I2C_Control_Start 0x20 +#define I2C_Control_TWSIEn 0x40 +#define I2C_Control_IntEn 0x80 + +/* + * F(I2C) = F(Tclk) / ( 10 * (M + 1) * (2^(N+1))) + * For Tclk = 100MHz, M = 4, N = 4: F = 62.5KHz + * For Tclk = 100MHz, M = 13, N = 3: F = 96.2KHz + */ +#define I2C_BaudRate(M, N) (((M) << 3) | (N)) +#define I2C_BaudRate_62_5K I2C_BaudRate(4, 4) +#define I2C_BaudRate_96_2K I2C_BaudRate(13, 3) + +#define I2C_Status_BusError 0x00 /* Bus error */ +#define I2C_Status_Started 0x08 /* Start condition xmitted */ +#define I2C_Status_ReStarted 0x10 /* Repeated start condition xmitted */ +#define I2C_Status_AddrWriteAck 0x18 /* Adr + wr bit xmtd, ack rcvd */ +#define I2C_Status_AddrWriteNoAck 0x20 /* Adr + wr bit xmtd, NO ack rcvd */ +#define I2C_Status_MasterWriteAck 0x28 /* Master xmtd data byte, ack rcvd */ +#define I2C_Status_MasterWriteNoAck 0x30 /* Master xmtd data byte, NO ack rcvd*/ +#define I2C_Status_MasterLostArb 0x38 /* Master lost arbitration during + address or data transfer */ +#define I2C_Status_AddrReadAck 0x40 /* Adr + rd bit xmtd, ack rcvd */ +#define I2C_Status_AddrReadNoAck 0x48 /* Adr + rd bit xmtd, NO ack rcvd */ +#define I2C_Status_MasterReadAck 0x50 /* Master rcvd data bye, ack rcvd */ +#define I2C_Status_MasterReadNoAck 0x58 /* Master rcvd data bye, NO ack rcvd */ +#define I2C_Status_2ndAddrWriteAck 0xd0 /* 2nd adr + wr bit xmid, ack rcvd */ +#define I2C_Status_2ndAddrWriteNoAck 0xd8 /* 2nd adr + wr bit xmid, NO ack rcvd */ +#define I2C_Status_2ndAddrReadAck 0xe0 /* 2nd adr + rd bit xmid, ack rcvd */ +#define I2C_Status_2ndAddrReadNoAck 0xe8 /* 2nd adr + rd bit xmtd, NO ack rcvd */ +#define I2C_Status_Idle 0xf8 /* Idle */ + +#endif /* _DEV_MARVELL_GTI2CREG_H_ */ diff --git a/bsps/powerpc/beatnik/include/bsp/gtintrreg.h b/bsps/powerpc/beatnik/include/bsp/gtintrreg.h new file mode 100644 index 0000000000..bd3f69514e --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gtintrreg.h @@ -0,0 +1,257 @@ +/* $NetBSD: gtintrreg.h,v 1.3 2005/02/27 00:27:21 perry Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * gt64260intr.h: defines for GT-64260 system controller interrupts + * + * creation Sun Jan 7 18:05:59 PST 2001 cliff + * + * NOTE: + * Galileo GT-64260 manual bit defines assume Little Endian + * ordering of bits within bytes, i.e. + * bit #0 --> 0x01 + * vs. Motorola Big Endian bit numbering where + * bit #0 --> 0x80 + * Consequently we define bits in Little Endian format and plan + * to swizzle bytes during programmed I/O by using lwbrx/swbrx + * to load/store GT-64260 registers. + */ + + +#ifndef _DISCOVERY_GT64260INTR_H +#define _DISCOVERY_GT64260INTR_H + +#define BIT(n) (1<<(n)) + + +/* + * GT-64260 Interrupt Controller Register Map + */ +#define ICR_260_MIC_LO 0xc18 /* main interrupt cause low */ +#define ICR_260_MIC_HI 0xc68 /* main interrupt cause high */ +#define ICR_260_CIM_LO 0xc1c /* CPU interrupt mask low */ +#define ICR_260_CIM_HI 0xc6c /* CPU interrupt mask high */ +#define ICR_260_CSC 0xc70 /* CPU select cause */ +#define ICR_260_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */ +#define ICR_260_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */ +#define ICR_260_P0SC 0xc74 /* PCI_0 select cause */ +#define ICR_260_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */ +#define ICR_260_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */ +#define ICR_260_P1SC 0xcf4 /* PCI_1 select cause */ +#define ICR_260_CI0M 0xe60 /* CPU int[0] mask */ +#define ICR_260_CI1M 0xe64 /* CPU int[1] mask */ +#define ICR_260_CI2M 0xe68 /* CPU int[2] mask */ +#define ICR_260_CI3M 0xe6c /* CPU int[3] mask */ + +/* + * MV64360 Interrupt Controller Register Map + */ +#define ICR_360_MIC_LO 0x004 /* main interrupt cause low */ +#define ICR_360_MIC_HI 0x00c /* main interrupt cause high */ +#define ICR_360_C0IM_LO 0x014 /* CPU 0 interrupt mask low */ +#define ICR_360_C0IM_HI 0x01c /* CPU 0 interrupt mask high */ +#define ICR_360_C0SC 0x024 /* CPU 0 select cause */ +#define ICR_360_C1IM_LO 0x034 /* CPU 1 interrupt mask low */ +#define ICR_360_C1IM_HI 0x03c /* CPU 1 interrupt mask high */ +#define ICR_360_C1SC 0x044 /* CPU 1 select cause */ +#define ICR_360_I0M_LO 0x014 /* Int 0 mask low */ +#define ICR_360_I0M_HI 0x01c /* Int 0 mask high */ +#define ICR_360_I0SC 0x024 /* Int 0 select cause */ +#define ICR_360_I1M_LO 0x034 /* Int 1 mask low */ +#define ICR_360_I1M_HI 0x03c /* Int 1 mask high */ +#define ICR_360_C1SC 0x044 /* Int 1 select cause */ + + +/* + * IRQs: + * we define IRQs based on bit number in the + * ICU_LEN dimensioned hardware portion of the imask_t bit vector + * which consists of 64 bits of Main Cause and Mask register pairs + * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI) + * as well as 32 bits in GPP registers (see intr.h): + * + * IRQs: + * 31.............................0 63.............................32 + * | | | + * imask_t index: | | | + * | | | | + * ^--------- IM_PIC_LO ----------^ ^------ IM_PIC_HI ------------^ + * | | | + * Bitmasks: | | | + * | | | | + * ^--------- IML_* --------------^ ^------ IMH_* ----------------^ + * | | | + * Registers: | | | + * | | | | + * ^--------- ICR_MIC_LO ---------^ ^------ ICR_MIC_HI -----------^ + * ^--------- ICR_CIM_LO ---------^ ^------ ICR_CIM_HI -----------^ + * + * IRQs: + * 95............................64 127............................96 + * | | | + * imask_t index: | | | + * | | | | + * ^-------- IMASK_GPP ----------^ ^----- IMASK_SOFTINT --------^ + * | | | + * Bitmasks: | | | + * | | | | + * ^--------- GPP_* --------------^ ^------ SIBIT(irq) -----------^ + * | | | + * Registers: | | | + * | | | | + * ^--- GT_GPP_Interrupt_Cause ---^ ^------- (none) -----------^ + * ^--- GT_GPP_Interrupt_Mask ---^ + * + * + * Note that GPP interrupts are summarized in the Main Cause Register. + * + * Some IRQs are "resvered" undefined due to gaps in HW register utilization. + */ +#define IRQ_DEV 1 /* device interface interrupt */ +#define IRQ_DMA 2 /* DMA addres error interrupt */ +#define IRQ_CPU 3 /* CPU interface interrupt */ +#define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */ +#define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */ +#define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */ +#define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */ +#define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */ +#define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */ +#define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */ +#define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */ +#define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */ +#define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */ +#define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ +#define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ +#define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */ +#define IRQ_ECC 17 /* ECC error interrupt */ +#define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ +#define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ +#define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ +#define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ +#define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ +#define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ +#define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ +#define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ +#define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ +#define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ +#define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ +#define IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ +#define IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ +#define IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ +#define IRQ_SDMA (32+4) /* SDMA interrupt */ +#define IRQ_I2C (32+5) /* I2C interrupt */ +#define IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ +#define IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ +#define IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ +#define IRQ_COMM (32+11) /* Comm unit interrupt */ +#define IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt */ +#define IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt */ +#define IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt */ +#define IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt */ + +/* + * low word interrupt mask register bits + */ +#define IML_SUM BIT(0) +#define IML_DEV BIT(IRQ_DEV) +#define IML_DMA BIT(IRQ_DMA) +#define IML_CPU BIT(IRQ_CPU) +#define IML_IDMA0_1 BIT(IRQ_IDMA0_1) +#define IML_IDMA2_3 BIT(IRQ_IDMA2_3) +#define IML_IDMA4_5 BIT(IRQ_IDMA4_5) +#define IML_IDMA6_7 BIT(IRQ_IDMA6_7) +#define IML_TIME0_1 BIT(IRQ_TIME0_1) +#define IML_TIME2_3 BIT(IRQ_TIME2_3) +#define IML_TIME4_5 BIT(IRQ_TIME4_5) +#define IML_TIME6_7 BIT(IRQ_TIME6_7) +#define IML_PCI0_0 BIT(IRQ_PCI0_0) +#define IML_PCI0_1 BIT(IRQ_PCI0_1) +#define IML_PCI0_2 BIT(IRQ_PCI0_2) +#define IML_PCI0_3 BIT(IRQ_PCI0_3) +#define IML_PCI1_0 BIT(IRQ_PCI1_0) +#define IML_ECC BIT(IRQ_ECC) +#define IML_PCI1_1 BIT(IRQ_PCI1_1) +#define IML_PCI1_2 BIT(IRQ_PCI1_2) +#define IML_PCI1_3 BIT(IRQ_PCI1_3) +#define IML_PCI0OUT_LO BIT(IRQ_PCI0OUT_LO) +#define IML_PCI0OUT_HI BIT(IRQ_PCI0OUT_HI) +#define IML_PCI1OUT_LO BIT(IRQ_PCI1OUT_LO) +#define IML_PCI1OUT_HI BIT(IRQ_PCI1OUT_HI) +#define IML_PCI0IN_LO BIT(IRQ_PCI0IN_LO) +#define IML_PCI0IN_HI BIT(IRQ_PCI0IN_HI) +#define IML_PCI1IN_LO BIT(IRQ_PCI1IN_LO) +#define IML_PCI1IN_HI BIT(IRQ_PCI1IN_HI) +#define IML_RES (BIT(25)|BIT(30)|BIT(31)) + +/* + * high word interrupt mask register bits + */ +#define IMH_ETH0 BIT(IRQ_ETH0-32) +#define IMH_ETH1 BIT(IRQ_ETH1-32) +#define IMH_ETH2 BIT(IRQ_ETH2-32) +#define IMH_SDMA BIT(IRQ_SDMA-32) +#define IMH_I2C BIT(IRQ_I2C-32) +#define IMH_BRG BIT(IRQ_BRG-32) +#define IMH_MPSC0 BIT(IRQ_MPSC0-32) +#define IMH_MPSC1 BIT(IRQ_MPSC1-32) +#define IMH_COMM BIT(IRQ_COMM-32) +#define IMH_GPP7_0 BIT(IRQ_GPP7_0-32) +#define IMH_GPP15_8 BIT(IRQ_GPP15_8-32) +#define IMH_GPP23_16 BIT(IRQ_GPP23_16-32) +#define IMH_GPP31_24 BIT(IRQ_GPP31_24-32) +#define IMH_GPP_SUM (IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24) +#define IMH_RES (BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \ + |BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \ + |BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \ + |BIT(31)) + +/* + * ICR_CSC "Select Cause" register bits + */ +#define CSC_SEL BIT(30) /* HI/LO select */ +#define CSC_STAT BIT(31) /* ? "irq active" : "irq none" */ +#define CSC_CAUSE ~(CSC_SEL|CSC_STAT) + + +/* + * CPU Int[n] Mask bit(s) + */ +#define CPUINT_SEL 0x80000000 /* HI/LO select */ + +#endif /* _DISCOVERY_GT64260INTR_H */ diff --git a/bsps/powerpc/beatnik/include/bsp/gtpcireg.h b/bsps/powerpc/beatnik/include/bsp/gtpcireg.h new file mode 100644 index 0000000000..d01fc702ac --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gtpcireg.h @@ -0,0 +1,964 @@ +/* $NetBSD: gtpcireg.h,v 1.4 2005/12/11 12:22:16 christos Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_GTPCIREG_H +#define _DEV_GTPCIREG_H + +#define PCI__BIT(bit) (1U << (bit)) +#define PCI__MASK(bit) (PCI__BIT(bit) - 1) +#define PCI__GEN(bus, off, num) (((off)^((bus) << 7))+((num) << 4)) +#define PCI__EXT(data, bit, len) (((data) >> (bit)) & PCI__MASK(len)) +#define PCI__CLR(data, bit, len) ((data) &= ~(PCI__MASK(len) << (bit))) +#define PCI__INS(bit, new) ((new) << (bit)) + +#define PCI_SYNC_REG(bus) (0xc0 | ((bus) << 3)) + +/* + * Table 185: PCI Slave ADDRess Decoding Register Map + */ +#define PCI_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c08, 0) +#define PCI_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0c0c, 0) +#define PCI_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c10, 0) +#define PCI_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0c14, 0) +#define PCI_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d08, 0) +#define PCI_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0d0c, 0) +#define PCI_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d10, 0) +#define PCI_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0d14, 0) +#define PCI_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0d18, 0) +#define PCI_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0d1c, 0) +#define PCI_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d20, 0) +#define PCI_P2P_IO_BAR_SIZE(bus) PCI__GEN(bus, 0x0d24, 0) +#define PCI_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0d28, 0) +#define PCI_EXPANSION_ROM_BAR_SIZE(bus) PCI__GEN(bus, 0x0d2c, 0) +#define PCI_DAC_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e00, 0) +#define PCI_DAC_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e04, 0) +#define PCI_DAC_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e08, 0) +#define PCI_DAC_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e0c, 0) +#define PCI_DAC_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e10, 0) +#define PCI_DAC_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e14, 0) +#define PCI_DAC_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e18, 0) +#define PCI_DAC_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e1c, 0) +#define PCI_DAC_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0e20, 0) +#define PCI_DAC_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e24, 0) +#define PCI_DAC_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e28, 0) +#define PCI_DAC_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0e2c, 0) +#define PCI_BASE_ADDR_REGISTERS_ENABLE(bus) PCI__GEN(bus, 0x0c3c, 0) +#define PCI_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c48, 0) +#define PCI_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d48, 0) +#define PCI_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c4c, 0) +#define PCI_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d4c, 0) +#define PCI_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c50, 0) +#define PCI_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d50, 0) +#define PCI_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d58, 0) +#define PCI_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c54, 0) +#define PCI_ADDR_DECODE_CONTROL(bus) PCI__GEN(bus, 0x0d3c, 0) +#define PCI_BOOTCS_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d54, 0) +#define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d5c, 0) +#define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d60, 0) +#define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d64, 0) +#define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d68, 0) +#define PCI_P2P_IO_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d6c, 0) +#define PCI_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d70, 0) +#define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f00, 0) +#define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f04, 0) +#define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f08, 0) +#define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f0c, 0) +#define PCI_DAC_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f10, 0) +#define PCI_DAC_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f14, 0) +#define PCI_DAC_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f18, 0) +#define PCI_DAC_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f1c, 0) +#define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f20, 0) +#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f24, 0) +#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f28, 0) +#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f2c, 0) +#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f30, 0) +#define PCI_DAC_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f34, 0) +#define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f38, 0) + +/* + * Table 186: PCI Control Register Map + */ +#define PCI_COMMAND(bus) PCI__GEN(bus, 0x0c00, 0) +#define PCI_MODE(bus) PCI__GEN(bus, 0x0d00, 0) +#define PCI_TIMEOUT_RETRY(bus) PCI__GEN(bus, 0x0c04, 0) +#define PCI_READ_BUFFER_DISCARD_TIMER(bus) PCI__GEN(bus, 0x0d04, 0) +#define PCI_MSI_TRIGGER_TIMER(bus) PCI__GEN(bus, 0x0c38, 0) +#define PCI_ARBITER_CONTROL(bus) PCI__GEN(bus, 0x1d00, 0) +#define PCI_INTERFACE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d08, 0) +#define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d0c, 0) +#define PCI_INTERFACE_XBAR_TIMEOUT(bus) PCI__GEN(bus, 0x1d04, 0) +#define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d18, 0) +#define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d1c, 0) +#define PCI_SYNC_BARRIER(bus) PCI__GEN(bus, 0x1d10, 0) +#define PCI_P2P_CONFIGURATION(bus) PCI__GEN(bus, 0x1d14, 0) +#define PCI_P2P_SWAP_CONTROL(bus) PCI__GEN(bus, 0x1d54, 0) +#define PCI_ACCESS_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1e00, n) +#define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1e04, n) +#define PCI_ACCESS_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1e08, n) + + +/* + * Table 187: PCI Snoop Control Register Map + */ +#define PCI_SNOOP_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1f00, n) +#define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1f04, n) +#define PCI_SNOOP_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1f08, n) + +/* + * Table 188: PCI Configuration ACCESS_Register Map + */ +#define PCI_CONFIG_ADDR(bus) PCI__GEN(bus, 0x0cf8, 0) +#define PCI_CONFIG_DATA(bus) PCI__GEN(bus, 0x0cfc, 0) +#define PCI_INTR_ACK(bus) PCI__GEN(bus, 0x0c34, 0) + +/* + * Table 189: PCI ERROR Report Register Map + */ +#define PCI_SERR_MASK(bus) PCI__GEN(bus, 0x0c28, 0) +#define PCI_ERROR_ADDRESS_LOW(bus) PCI__GEN(bus, 0x1d40, 0) +#define PCI_ERROR_ADDRESS_HIGH(bus) PCI__GEN(bus, 0x1d44, 0) +#define PCI_ERROR_DATA_LOW(bus) PCI__GEN(bus, 0x1d48, 0) +#define PCI_ERROR_DATA_HIGH(bus) PCI__GEN(bus, 0x1d4c, 0) +#define PCI_ERROR_COMMAND(bus) PCI__GEN(bus, 0x1d50, 0) +#define PCI_ERROR_CAUSE(bus) PCI__GEN(bus, 0x1d58, 0) +#define PCI_ERROR_MASK(bus) PCI__GEN(bus, 0x1d5c, 0) + + + +/* + * Table 223: PCI Base Address Registers Enable + * If a bit is clear, the BAR is enabled. If set, disabled. The GT64260] + * prevents disabling both memory mapped and I/O mapped BARs (bits 9 and 10 + * cannot simultaneously be set to 1). + */ +#define PCI_BARE_SCS0En PCI__BIT(0) /* SCS[0]* BAR Enable */ +#define PCI_BARE_SCS1En PCI__BIT(1) /* SCS[1]* BAR Enable */ +#define PCI_BARE_SCS2En PCI__BIT(2) /* SCS[2]* BAR Enable */ +#define PCI_BARE_SCS3En PCI__BIT(3) /* SCS[3]* BAR Enable */ +#define PCI_BARE_CS0En PCI__BIT(4) /* CS[0]* BAR Enable */ +#define PCI_BARE_CS1En PCI__BIT(5) /* CS[1]* BAR Enable */ +#define PCI_BARE_CS2En PCI__BIT(6) /* CS[2]* BAR Enable */ +#define PCI_BARE_CS3En PCI__BIT(7) /* CS[3]* BAR Enable */ +#define PCI_BARE_BootCSEn PCI__BIT(8) /* BootCS* BAR Enable */ +#define PCI_BARE_IntMemEn PCI__BIT(9) /* Memory Mapped Internal + * Registers BAR Enable */ +#define PCI_BARE_IntIOEn PCI__BIT(10) /* I/O Mapped Internal + * Registers BAR Enable */ +#define PCI_BARE_P2PMem0En PCI__BIT(11) /* P2P Mem0 BAR Enable */ +#define PCI_BARE_P2PMem1En PCI__BIT(12) /* P2P Mem1 BAR Enable */ +#define PCI_BARE_P2PIOEn PCI__BIT(13) /* P2P IO BAR Enable */ +#define PCI_BARE_CPUEn PCI__BIT(14) /* CPU BAR Enable */ +#define PCI_BARE_DSCS0En PCI__BIT(15) /* DAC SCS[0]* BAR Enable */ +#define PCI_BARE_DSCS1En PCI__BIT(16) /* DAC SCS[1]* BAR Enable */ +#define PCI_BARE_DSCS2En PCI__BIT(17) /* DAC SCS[2]* BAR Enable */ +#define PCI_BARE_DSCS3En PCI__BIT(18) /* DAC SCS[3]* BAR Enable */ +#define PCI_BARE_DCS0En PCI__BIT(19) /* DAC CS[0]* BAR Enable */ +#define PCI_BARE_DCS1En PCI__BIT(20) /* DAC CS[1]* BAR Enable */ +#define PCI_BARE_DCS2En PCI__BIT(21) /* DAC CS[2]* BAR Enable */ +#define PCI_BARE_DCS3En PCI__BIT(22) /* DAC CS[3]* BAR Enable */ +#define PCI_BARE_DBootCSEn PCI__BIT(23) /* DAC BootCS* BAR Enable */ +#define PCI_BARE_DP2PMem0En PCI__BIT(24) /* DAC P2P Mem0 BAR Enable */ +#define PCI_BARE_DP2PMem1En PCI__BIT(25) /* DAC P2P Mem1 BAR Enable */ +#define PCI_BARE_DCPUEn PCI__BIT(26) /* DAC CPU BAR Enable */ + +/* + * Table 254: PCI Address Decode Control + * Bits 7:4 and 31:25 are reserved + * 00:00 RemapWrDis Address Remap Registers Write Disable + * 0: Writes to a BAR result in updating the + * corresponding remap register with the BAR's + * new value. + * 1: Writes to a BAR have no affect on the + * corresponding Remap register value. + * 01:01 ExpRomDev Expansion ROM Device (0: CS[3]; 1: BootCS) + * 02:02 VPDDev VPD Device (0: CS[3]; 1: BootCS) + * 03:03 MsgAcc Messaging registers access + * 0: Messaging unit registers are accessible on + * lowest 4Kbyte of SCS[0] BAR space. + * 1: Messaging unit registers are only accessible + * as part of the GT64260 internal space. + * 07:04 Reserved + * 24:08 VPDHighAddr VPD High Address bits + * [31:15] of VPD the address. + * 31:25 Reserved + */ +#define PCI_ADC_RemapWrDis PCI__BIT(0) +#define PCI_ADC_ExpRomDev PCI__BIT(1) +#define PCI_ADC_VPDDev PCI__BIT(2) +#define PCI_ADC_MsgAcc PCI__BIT(3) +#define PCI_ADC_VPDHighAddr_GET(v) PCI__EXT(v, 8, 16) + + +/* + * Table 255: PCI Command + * 00:00 MByteSwap PCI Master Byte Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 0, the GTO64260 PCI master swaps the bytes + * of the incoming and outgoing PCI data (swap the 8 bytes + * of a longword). + * 01:01 Reserved + * 02:02 Reserved Must be 0. + * 03:03 Reserved + * 04:04 MWrCom PCI Master Write Combine Enable + * When set to 1, write combining is enabled. + * 05:05 MRdCom PCI Master Read Combine Enable + * When set to 1, read combining is enabled. + * 06:06 MWrTrig PCI Master Write Trigger + * 0: Accesses the PCI bus only when the whole burst is + * written into the master write buffer. + * 1: Accesses the PCI bus when the first data is written + * into the master write buffer. + * 07:07 MRdTrig PCI Master Read Trigger + * 0: Returns read data to the initiating unit only when + * the whole burst is written into master read buffer. + * 1: Returns read data to the initiating unit when the + * first read data is written into master read buffer. + * 08:08 MRdLine PCI Master Memory Read Line Enable + * (0: Disable; 1: Enable) + * 09:09 MRdMul PCI Master Memory Read Multiple Enable + * (0: Disable; 1: Enable) + * 10:10 MWordSwap PCI Master Word Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 1, the GT64260 PCI master swaps the 32-bit + * words of the incoming and outgoing PCI data. + * 11:11 SWordSwap PCI Slave Word Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 1, the GT64260 PCI slave swaps the 32-bit + * words of the incoming and outgoing PCI data. + * 12:12 IntBusCtl PCI Interface Unit Internal Bus Control + * NOTE: Reserved for Galileo Technology usage + * 0: Enable internal bus sharing between master and + * slave interfaces. + * 1: Disable internal bus sharing between master and + * slave interfaces. + * 13:13 SBDis PCI Slave Sync Barrier Disable + * When set to 1, the PCI configuration read transaction + * will stop act as sync barrier transaction. + * 14:14 Reserved Must be 0 + * 15:15 MReq64 PCI Master REQ64* Enable (0: Disable; 1: Enable) + * 16:16 SByteSwap PCI Slave Byte Swap + * NOTE: GT-64120 and GT-64130 compatible. + * When set to 0, the GT64260 PCI slave swaps the bytes of + * the incoming and outgoing PCI data (swap the 8 bytes of + * a long-word). + * 17:17 MDACEn PCI Master DAC Enable + * 0: Disable (The PCI master never drives the DAC cycle) + * 1: Enable (In case the upper 32-bit address is not 0, + * the PCI master drives the DAC cycle) + * 18:18 M64Allign PCI Master REQ64* assertion on non-aligned + * 0: Disable (The master asserts REQ64* only if + * the address is 64-bit aligned) + * 1: Enable (The master asserts REQ64* even if + * the address is not 64-bit aligned) + * 19:19 PErrProp Parity/ECC Errors Propagation Enable + * 0: Disable (The PCI interface always drives + * correct parity on the PAR signal) + * 1: Enable (In case of slave read bad ECC from + * SDRAM, or master write with bad parity/ECC + * indication from the initiator, the PCI interface + * drives bad parity on the PAR signal) + * 20:20 SSwapEn PCI Slave Swap Enable + * NOTE: Even if the SSwapEn bit is set to 1 and + * the PCI address does not match any of the + * Access Control registers, slave data swapping + * works according to SByteSwap and SWordSwap bits. + * 0: PCI slave data swapping is determined via + * SByteSwap and SWordSwap bits (bits 16 and 11), + * as in the GT-64120/130. + * 1: PCI slave data swapping is determined via PCISwap + * bits [25:24] in the PCI Access Control registers. + * 21:21 MSwapEn PCI Master Swap Enable + * 0: PCI master data swapping is determined via + * MByteSwap and MWordSwap bits (bits 0 and 10), + * as in the GT-64120/130. + * 1: PCI master data swapping is determined via + * PCISwap bits in CPU to PCI Address Decoding + * registers. + * 22:22 MIntSwapEn PCI Master Configuration Transactions Data Swap Enable + * NOTE: Reserved for Galileo Technology usage. + * 0: Disable (The PCI master configuration transaction + * to the PCI bus is always in Little Endian convention) + * 1: Enable (The PCI master configuration transaction to + * the PCI bus is determined according to the setting + * of MSwapEn bit) + * 23:23 LBEn PCI Loop Back Enable + * NOTE: Reserved for Galileo Technology usage. + * 0: Disable (The PCI slave does not respond to + * transactions initiated by the PCI master) + * 1: Enable (The PCI slave does respond to + * transactions initiated by the PCI master, + * if targeted to the slave (address match) + * 26:24 SIntSwap PCI Slave data swap control on PCI accesses to the + * GT64260 internal and configuration registers. + * Bits encoding are the same as bits[26:24] in PCI Access + * Control registers. + * 27:27 Reserved Must be 0. + * 31:28 Reserved Read only. + */ +#define PCI_CMD_MByteSwap PCI__BIT(0) +#define PCI_CMD_MBZ0_2 PCI__BIT(2) +#define PCI_CMD_MWrCom PCI__BIT(4) +#define PCI_CMD_MRdCom PCI__BIT(5) +#define PCI_CMD_MWrTrig PCI__BIT(6) +#define PCI_CMD_MRdTrig PCI__BIT(7) +#define PCI_CMD_MRdLine PCI__BIT(8) +#define PCI_CMD_MRdMul PCI__BIT(9) +#define PCI_CMD_MWordSwap PCI__BIT(10) +#define PCI_CMD_SWordSwap PCI__BIT(11) +#define PCI_CMD_IntBusCtl PCI__BIT(12) +#define PCI_CMD_SBDis PCI__BIT(13) +#define PCI_CMD_MBZ0_14 PCI__BIT(14) +#define PCI_CMD_MReq64 PCI__BIT(15) +#define PCI_CMD_SByteSwap PCI__BIT(16) +#define PCI_CMD_MDCAEn PCI__BIT(17) +#define PCI_CMD_M64Allign PCI__BIT(18) +#define PCI_CMD_PErrProp PCI__BIT(19) +#define PCI_CMD_SSwapEn PCI__BIT(20) +#define PCI_CMD_MSwapEn PCI__BIT(21) +#define PCI_CMD_MIntSwapEn PCI__BIT(22) +#define PCI_CMD_LBEn PCI__BIT(23) +#define PCI_CMD_SIntSwap_GET(v) PCI__EXT(v, 24, 3) +#define PCI_CMD_MBZ0_27 PCI__BIT(27) + + +/* + * Table 256: PCI Mode + * 00:00 PciID PCI Interface ID -- Read Only (PCI_0: 0x0; PCI_1: 0x1) + * 01:01 Reserved + * 02:02 Pci64 64-bit PCI Interface -- Read Only + * When set to 1, the PCI interface is configured to a + * 64 bit interface. + * 07:03 Reserved + * 08:08 ExpRom Expansion ROM Enable -- Read Only from PCI + * When set to 1, the expansion ROM BAR is enabled. + * 09:09 VPD VPD Enable -- Read Only from PCI + * When set to 1, VPD is supported. + * 10:10 MSI MSI Enable -- Read Only from PCI + * When set to 1, MSI is supported. + * 11:11 PMG Power Management Enable -- Read Only from PCI + * When set to 1, PMG is supported. + * 12:12 HotSwap CompactPCI Hot Swap Enable -- Read Only from PCI + * When set to 1, HotSwap is supported. + * 13:13 BIST BIST Enable -- Read only from PCI + * If set to 1, BIST is enabled. + * 30:14 Reserved + * 31:31 PRst PCI Interface Reset Indication -- Read Only + * Set to 0 as long as the RST* pin is asserted. + */ +#define PCI_MODE_PciID_GET(v) PCI__EXT(v, 0, 1) +#define PCI_MODE_Pci64 PCI__BIT(2) +#define PCI_MODE_ExpRom PCI__BIT(8) +#define PCI_MODE_VPD PCI__BIT(9) +#define PCI_MODE_MSI PCI__BIT(10) +#define PCI_MODE_PMG PCI__BIT(11) +#define PCI_MODE_HotSwap PCI__BIT(12) +#define PCI_MODE_BIST PCI__BIT(13) +#define PCI_MODE_PRst PCI__BIT(31) + +/* + * Table 257: PCI Timeout and Retry + * 07:00 Timeout0 Specifies the number of PClk cycles the GT64260 slave + * holds the PCI bus before terminating a transaction + * with RETRY. + * 15:08 Timeout1 Specifies the number of PClk cycles the GT64260 slave + * holds the PCI bus before terminating a transaction + * with DISCONNECT. + * 23:16 RetryCtr Retry Counter + * Specifies the number of retries of the GT64260 Master. + * The GT64260 generates an interrupt when this timer + * expires. A 0x00 value means a retry forever. + * 31:24 Reserved + */ +#define PCI_TMORTRY_Timeout0_GET(v) PCI__EXT(v, 0, 8) +#define PCI_TMORTRY_Timeout1_GET(v) PCI__EXT(v, 8, 8) +#define PCI_TMORTRY_RetryCtr_GET(v) PCI__EXT(v, 16, 8) + + +/* + * Table 258: PCI Read Buffer Discard Timer + * 15:00 Timer Specifies the number of PClk cycles the GT64260 + * slave keeps an non-accessed read buffers (non com- + * pleted delayed read) before invalidating the buffer. + * 23:16 RdBufEn Slave Read Buffers Enable + * Each bit corresponds to one of the eight read buffers. + * If set to 1, buffer is enabled. + * 31:24 Reserved + */ +#define PCI_RdBufDisTmr_Timer_GET(v) PCI__EXT(v, 0, 16) +#define PCI_RdBufDisTmr_RdBufEn_GET(v) PCI__EXT(v, 16, 8) +#define PCI_RdBufDisTmr_RdBufEn0(v) PCI__BIT(16) +#define PCI_RdBufDisTmr_RdBufEn1(v) PCI__BIT(17) +#define PCI_RdBufDisTmr_RdBufEn2(v) PCI__BIT(18) +#define PCI_RdBufDisTmr_RdBufEn3(v) PCI__BIT(19) +#define PCI_RdBufDisTmr_RdBufEn4(v) PCI__BIT(20) +#define PCI_RdBufDisTmr_RdBufEn5(v) PCI__BIT(21) +#define PCI_RdBufDisTmr_RdBufEn6(v) PCI__BIT(22) +#define PCI_RdBufDisTmr_RdBufEn7(v) PCI__BIT(23) + +/* + * Table 259: MSI Trigger Timer + * 15:00 Timer Specifies the number of TClk cycles between consecutive + * MSI requests. + * 31:16 Reserved + */ +#define PCI_MSITrigger_Timer_GET(v) PCI__EXT(v, 0, 16) + +/* + * Table 260: PCI Arbiter Control + * NOTE: If HPPV (bits [28:21]) is set to 0 and PAEn is set to 1, + * priority scheme is reversed. This means that high priority + * requests are granted if no low priority request is pending. + * 00:00 Reserved Must be 0. 0x0 + * 01:01 BDEn Broken Detection Enable + * If set to 1, broken master detection is enabled. A mas- + * ter is said to be broken if it fails to respond to grant + * assertion within a window specified in BV (bits [6:3]). + * 02:02 PAEn Priority Arbitration Enable + * 0: Low priority requests are granted only when no high + * priority request is pending + * 1: Weighted round robin arbitration is performed + * between high priority and low priority groups. + * 06:03 BV Broken Value + * This value sets the maximum number of cycles that the + * arbiter waits for a PCI master to respond to its grant + * assertion. If a PCI master fails to assert FRAME* within + * this time, the PCI arbiter aborts the transaction and + * performs a new arbitration cycle and a maskable + * interrupt is generated. Must be greater than 0. + * NOTE: The PCI arbiter waits for the current + * transaction to end before starting to + * count the wait-for-broken cycles. + * Must be greater than 1 for masters that performs address + * stepping (such as the GTO 64260 PCI master), since they + * require GNT* assertion for two cycles. + * 13:07 P[6:0] Priority + * These bits assign priority levels to the requests + * connected to the PCI arbiter. When a PM bit is set to + * 1, priority of the associated request is high. The + * mapping between P[6:0] bits and the request/grant pairs + * are as follows: + * P[0]: internal PCI master P[1]: external REQ0/GNT0 + * P[2]: external REQ1/GNT1 P[3]: external REQ2/GNT2 + * P[4]: external REQ3/GNT3 P[5]: external REQ4/GNT4 + * P[6]: external REQ5/GNT5 + * 20:14 PD[6:0] Parking Disable + * Use these bits to disable parking on any of the PCI + * masters. When a PD bit is set to 1, parking on the + * associated PCI master is disabled. + * NOTE: The arbiter parks on the last master granted + * unless disabled through the PD bit. Also, if + * PD bits are all 1, the PCI arbiter parks on + * the internal PCI master. + * 28:21 HPPV High Priority Preset Value + * This is the preset value of the high priority counter + * (High_cnt). This counter decrements each time a high + * priority request is granted. When the counter reaches + * zero, it reloads with this preset value. The counter + * reloads when a low priority request is granted. + * 30:29 Reserved + * 31:31 EN Enable + * Setting this bit to 1 enables operation of the arbiter. + */ +#define PCI_ARBCTL_MBZ0_0 PCI__BIT(0) +#define PCI_ARBCTL_BDEn PCI__BIT(1) +#define PCI_ARBCTL_PAEn PCI__BIT(2) +#define PCI_ARBCTL_BV_GET(v) PCI__EXT(v, 3, 4) +#define PCI_ARBCTL_P_GET(v) PCI__EXT(v, 7, 7) +#define PCI_ARBCTL_PD_GET(v) PCI__EXT(v, 14, 7) +#define PCI_ARBCTL_HPPV_GET(v) PCI__EXT(v, 21, 7) +#define PCI_ARBCTL_EN PCI__BIT(31) + +#define PCI_ARBPRI_IntPci PCI__BIT(0) +#define PCI_ARBPRI_ExtReqGnt0 PCI__BIT(1) +#define PCI_ARBPRI_ExtReqGnt1 PCI__BIT(2) +#define PCI_ARBPRI_EXtReqGnt2 PCI__BIT(3) +#define PCI_ARBPRI_EXtReqGnt3 PCI__BIT(4) +#define PCI_ARBPRI_EXtReqGnt4 PCI__BIT(5) +#define PCI_ARBPRI_EXtReqGnt5 PCI__BIT(6) + +/* + * Table 261: PCI Interface Crossbar Control (Low) + * 03:00 Arb0 Slice 0 of PCI master pizza arbiter. + * 07:04 Arb1 Slice 1 of PCI master pizza arbiter. + * 11:08 Arb2 Slice 2 of PCI master pizza arbiter. + * 15:12 Arb3 Slice 3 of PCI master pizza arbiter. + * 19:16 Arb4 Slice 4 of PCI master pizza arbiter. + * 23:20 Arb5 Slice 5 of PCI master pizza arbiter. + * 27:24 Arb6 Slice 6 of PCI master pizza arbiter. + * 31:28 Arb7 Slice 7 of PCI master pizza arbiter. + */ +#define PCI_IFXBRCTL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4) +#define PCI_IFXBRCTL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\ + (v) |= PCI__INS((n)*4, s))) + +/* + * Table 262: PCI Interface Crossbar Control (High) + * 03:00 Arb8 Slice 8 of PCI master pizza arbiter. + * 07:04 Arb9 Slice 9 of PCI master pizza arbiter. + * 11:08 Arb10 Slice 10 of PCI master pizza arbiter. + * 15:12 Arb11 Slice 11 of PCI master pizza arbiter. + * 19:16 Arb12 Slice 12 of PCI master pizza arbiter. + * 23:20 Arb13 Slice 13 of PCI master pizza arbiter. + * 27:24 Arb14 Slice 14 of PCI master pizza arbiter. + * 31:28 Arb15 Slice 15 of PCI master pizza arbiter. + */ +#define PCI_IFXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4) +#define PCI_IFXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\ + (v) |= PCI__INS(((n)-8)*4, s))) + +/* + * Table 263: PCI Interface Crossbar Timeout + (NOTE: Reserved for Galileo Technology usage.) + * 07:00 Timeout Crossbar Arbiter Timeout Preset Value + * 15:08 Reserved + * 16:16 TimeoutEn Crossbar Arbiter Timer Enable (1: Disable) + * 31:17 Reserved + */ +#define PCI_IFXBRTMO_Timeout_GET(v) PCI__EXT(v, 0, 8) +#define PCI_IFXBRTMO_TimeoutEn PCI__BIT(16) + +/* + * Table 264: PCI Read Response Crossbar Control (Low) + * 03:00 Arb0 Slice 0 of PCI slave pizza arbiter. + * 07:04 Arb1 Slice 1 of PCI slave pizza arbiter. + * 11:08 Arb2 Slice 2 of PCI slave pizza arbiter. + * 15:12 Arb3 Slice 3 of PCI slave pizza arbiter. + * 19:16 Arb4 Slice 4 of PCI slave pizza arbiter. + * 23:20 Arb5 Slice 5 of PCI slave pizza arbiter. + * 27:24 Arb6 Slice 6 of PCI slave pizza arbiter. + * 31:28 Arb7 Slice 7 of PCI slave pizza arbiter. + */ +#define PCI_RRXBRCL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4) +#define PCI_RRXBRCL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\ + (v) |= PCI__INS((n)*4, s))) + + +/* + * Table 265: PCI Read Response Crossbar Control (High) + * 03:00 Arb8 Slice 8 of PCI slave pizza arbiter. + * 07:04 Arb9 Slice 9 of PCI slave pizza arbiter. + * 11:08 Arb10 Slice 10 of PCI slave pizza arbiter. + * 15:12 Arb11 Slice 11 of PCI slave pizza arbiter. + * 19:16 Arb12 Slice 12 of PCI slave pizza arbiter. + * 23:20 Arb13 Slice 13 of PCI slave pizza arbiter. + * 27:24 Arb14 Slice 14 of PCI slave pizza arbiter. + * 31:28 Arb15 Slice 15 of PCI slave pizza arbiter. + */ +#define PCI_RRXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4) +#define PCI_RRXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\ + (v) |= PCI__INS(((n)-8)*4, s))) + +/* + * Table 266: PCI Sync Barrier Virtual Register + * 31:0 SyncReg Sync Barrier Virtual Register + * PCI read from this register results in PCI slave sync barrier + * action. The returned data is un-deterministic. Read Only. + */ + +/* + * Table 267: PCI P2P Configuration + * 07:00 2ndBusL Secondary PCI Interface Bus Range Lower Boundary + * 15:08 2ndBusH Secondary PCI Interface Bus Range Upper Boundary + * 23:16 BusNum The PCI bus number to which the PCI interface + * is connected. + * 28:24 DevNum The PCI interface's device number. + * 31:29 Reserved Reserved. + */ +#define PCI_P2PCFG_2ndBusL_GET(v) PCI__EXT(v, 0, 8) +#define PCI_P2PCFG_2ndBusH_GET(v) PCI__EXT(v, 8, 8) +#define PCI_P2PCFG_BusNum_GET(v) PCI__EXT(v, 16, 8) +#define PCI_P2PCFG_DevNum_GET(v) PCI__EXT(v, 24, 5) + +/* + * Table 268: PCI P2P Swap Control + * 02:00 M0Sw P2P Mem0 BAR Swap Control + * 03:03 M0Req64 P2P Mem0 BAR Force REQ64 + * 06:04 M1Sw P2P Mem1 BAR Swap Control + * 07:07 M1Req64 P2P Mem1 BAR Force REQ64 + * 10:08 DM0Sw P2P DAC Mem0 BAR Swap Control + * 11:11 DM0Req64 P2P DAC Mem0 BAR Force REQ64 + * 14:12 DM1Sw P2P DAC Mem1 BAR Swap Control + * 15:15 DM1Req64 P2P DAC Mem1 BAR Force REQ64 + * 18:16 IOSw P2P I/O BAR Swap Control + * 19:19 Reserved + * 22:20 CfgSw P2P Configuration Swap Control + * 31:19 Reserved + */ +#define PCI_P2PSWAP_M0Sw_GET(v) PCI__EXT(v, 0, 3) +#define PCI_P2PSWAP_M0Req64 PCI__BIT(3) +#define PCI_P2PSWAP_M1Sw_GET(v) PCI__EXT(v, 4, 3) +#define PCI_P2PSWAP_M1Req64 PCI__BIT(7) +#define PCI_P2PSWAP_DM0Sw_GET(v) PCI__EXT(v, 8, 3) +#define PCI_P2PSWAP_DM0Req64 PCI__BIT(11) +#define PCI_P2PSWAP_DM1Sw_GET(v) PCI__EXT(v, 12, 3) +#define PCI_P2PSWAP_DM1Req64 PCI__BIT(15) +#define PCI_P2PSWAP_CfgSw_GET(v) PCI__EXT(v, 20, 3) + + + +/* + * Table 269: PCI Access Control Base (Low) + * 11:00 Addr Base Address Corresponds to address bits[31:20]. + * 12:12 PrefetchEn Read Prefetch Enable + * 0: Prefetch disabled (The PCI slave reads single words) + * 1: Prefetch enabled. + * 14:14 Reserved Must be 0 + * 15:15 Reserved + * 16:16 RdPrefetch PCI Read Aggressive Prefetch Enable; 0: Disable; + * 1: Enable (The PCI slave prefetches two + * bursts in advance) + * 17:17 RdLinePrefetch PCI Read Line Aggressive Prefetch Enable; 0: Disable; + * 1: Enable (PCI slave prefetch two bursts in advance) + * 18:18 RdMulPrefetch PCI Read Multiple Aggressive Prefetch Enable + * 0: Disable; 1: Enable (PCI slave prefetch two bursts in + * advance) + * 19:19 Reserved + * 21:20 MBurst PCI Max Burst + * Specifies the maximum burst size for a single transac- + * tion between a PCI slave and the other interfaces + * 00 - 4 64-bit words + * 01 - 8 64-bit words + * 10 - 16 64-bit words + * 11 - Reserved + * 23:22 Reserved + * 25:24 PCISwap Data Swap Control + * 00 - Byte Swap + * 01 - No swapping + * 10 - Both byte and word swap + * 11 - Word swap + * 26:26 Reserved Must be 0 + * 27:27 Reserved + * 28:28 AccProt Access Protect (0: PCI access is allowed; 1; Region is + not accessible from PCI) + * 29:29 WrProt Write Protect (0: PCI write is allowed; 1: Region is + * not writeable from PCI) + * 31:30 Reserved + */ +#define PCI_ACCCTLBASEL_Addr_GET(v) PCI__EXT(v, 0, 12) +#define PCI_ACCCTLBASEL_PrefetchEn PCI__BIT(12) +#define PCI_ACCCTLBASEL_MBZ0_14 PCI__BIT(14) +#define PCI_ACCCTLBASEL_RdPrefetch PCI__BIT(16) +#define PCI_ACCCTLBASEL_RdLinePrefetch PCI__BIT(17) +#define PCI_ACCCTLBASEL_RdMulPrefetch PCI__BIT(18) +#define PCI_ACCCTLBASEL_WBurst PCI__EXT(v, 20, 2) +#define PCI_ACCCTLBASEL_WBurst_8_QW PCI__INS(20, PCI_WBURST_8_QW) +#define PCI_ACCCTLBASEL_PCISwap PCI__EXT(v, 24, 2) +#define PCI_ACCCTLBASEL_PCISwap_NoSwap PCI__INS(24, PCI_PCISWAP_NoSwap) +#define PCI_ACCCTLBASEL_MBZ0_26 PCI__BIT(26) +#define PCI_ACCCTLBASEL_AccProt PCI__BIT(28) +#define PCI_ACCCTLBASEL_WrProt PCI__BIT(29) + +#define PCI_WBURST_4_QW 0x00 +#define PCI_WBURST_8_QW 0x01 +#define PCI_WBURST_16_QW 0x02 +#define PCI_WBURST_Reserved 0x04 + +#define PCI_PCISWAP_ByteSwap 0x00 +#define PCI_PCISWAP_NoSwap 0x01 +#define PCI_PCISWAP_ByteWordSwap 0x02 +#define PCI_PCISWAP_WordSwap 0x04 + +/* + * Table 293: PCI Snoop Control Base (Low) + * 11:00 Addr Base Address Corresponds to address bits[31:20]. + * 13:12 Snoop Snoop Type + * 31:14 Reserved + */ +#define PCI_SNOOPCTL_ADDR(v) PCI__EXT(v, 0, 12) +#define PCI_SNOOPCTL_TYPE(v) PCI__EXT(v, 12, 2) + +#define PCI_SNOOP_None 0 /* no snoop */ +#define PCI_SNOOP_WT 1 /* Snoop to WT region */ +#define PCI_SNOOP_WB 2 /* Snoop to WB region */ + + +/* + * Table 305: PCI Configuration Address + * + * 07:02 RegNum Register number. + * 10:08 FunctNum Function number. + * 15:11 DevNum Device number. + * 23:16 BusNum Bus number. + * 31:31 ConfigEn When set, an access to the Configuration Data + * register is translated into a Configuration + * or Special cycle on the PCI bus. + */ +#define PCI_CFG_MAKE_TAG(bus, dev, fun, reg) (PCI__BIT(31)|\ + PCI__INS(16, (bus))|\ + PCI__INS(11, (dev))|\ + PCI__INS( 8, (fun))|\ + PCI__INS( 0, (reg))) +#define PCI_CFG_GET_BUSNO(tag) PCI__EXT(tag, 16, 8) +#define PCI_CFG_GET_DEVNO(tag) PCI__EXT(tag, 11, 5) +#define PCI_CFG_GET_FUNCNO(tag) PCI__EXT(tag, 8, 3) +#define PCI_CFG_GET_REGNO(tag) PCI__EXT(tag, 0, 8) + +/* + * Table 306: PCI Configuration Data + * + * 31:00 ConfigData The data is transferred to/from the PCI bus when + * the CPU accesses this register and the ConfigEn + * bit in the Configuration Address register is set + * + * A CPU access to this register causes the GT64260 to perform a Configuration + * or Special cycle on the PCI bus. + */ + + +/* + * Table 307: PCI Interrupt Acknowledge (This register is READ ONLY) + * 31:00 IntAck A CPU read access to this register forces an + * interrupt acknowledge cycle on the PCI bus. + */ + + +/* + * Table 308: PCI SERR* Mask + * + * NOTE: The GT64260 asserts SERR* only if SERR* is enabled via the PCI Status + * and Command register. + * If the corresponding bit is set, then asserts SERR* upon ... + */ +#define PCI_SERRMSK_SAPerr PCI__BIT(0) /* PCI slave detection of bad + * address parity. */ +#define PCI_SERRMSK_SWrPerr PCI__BIT(1) /* PCI slave detection of bad + * write data parity. */ +#define PCI_SERRMSK_SRdPerr PCI__BIT(2) /* a PERR* response to read + * data driven by the PCI + * slave. */ +#define PCI_SERRMSK_MAPerr PCI__BIT(4) /* a PERR* response to an + * address driven by the PCI + * master. */ +#define PCI_SERRMSK_MWrPerr PCI__BIT(5) /* a PERR* response to write + * data driven by the PCI + * master. */ +#define PCI_SERRMSK_MRdPerr PCI__BIT(6) /* bad data parity detection + * during a PCI master read + * transaction. */ +#define PCI_SERRMSK_MMabort PCI__BIT(8) /* a PCI master generation of + * master abort. */ +#define PCI_SERRMSK_MTabort PCI__BIT(9) /* a PCI master detection of + * target abort. */ +#define PCI_SERRMSK_MRetry PCI__BIT(11) /* a PCI master reaching retry + * counter limit. */ +#define PCI_SERRMSK_SMabort PCI__BIT(16) /* a PCI slave detection of + * master abort. */ +#define PCI_SERRMSK_STabort PCI__BIT(17) /* a PCI slave termination of + * a transaction with Target + * Abort. */ +#define PCI_SERRMSK_SAccProt PCI__BIT(18) /* a PCI slave access protect + * violation. */ +#define PCI_SERRMSK_SWrProt PCI__BIT(19) /* a PCI slave write protect + * violation. */ +#define PCI_SERRMSK_SRdBuf PCI__BIT(20) /* the PCI slave's read buffer, + * discard timer expires */ +#define PCI_SERRMSK_Arb PCI__BIT(21) /* the internal PCI arbiter + * detection of a broken PCI + * master. */ + +#define PCI_SERRMSK_ALL_ERRS \ + (PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \ + |PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \ + |PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \ + |PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \ + |PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb) + + + +/* + * Table 309: PCI Error Address (Low) -- Read Only. + * 31:00 ErrAddr PCI address bits [31:0] are latched upon an error + * condition. Upon address latch, no new addresses can + * be registered (due to additional error condition) until + * the register is being read. + */ + + + +/* + * Table 310: PCI Error Address (High) Applicable only when running DAC cycles. + * 31:00 ErrAddr PCI address bits [63:32] are latched upon + * error condition. + * + * NOTE: Upon data sample, no new data is latched until the PCI Error Low + * Address register is read. This means that PCI Error Low Address + * register must bethe last register read by the interrupt handler. + */ + +/* + * Table 311: PCI Error Data (Low) + * 31:00 ErrData PCI data bits [31:00] are latched upon error condition. + */ + +/* + * Table 312: PCI Error Data (High) Applicable only when running + * 64-bit cycles. + * 31:00 ErrData PCI data bits [63:32] are latched upon error condition. + */ + +/* + * Table 313: PCI Error Command + * 03:00 ErrCmd PCI command is latched upon error condition. + * 07:04 Reserved + * 15:08 ErrBE PCI byte enable is latched upon error condition. + * 16:16 ErrPAR PCI PAR is latched upon error condition. + * 17:17 ErrPAR64 PCI PAR64 is latched upon error condition. + * Applicable only when running 64-bit cycles. + * 31:18 Reserved + * NOTE: Upon data sample, no new data is latched until the PCI Error Low + * Address register is read. This means that PCI Error Low Address register + * must be the last register read by the interrupt handler. + */ +#define PCI_ERRCMD_Cmd_GET(v) PCI__EXT(v, 0, 4) +#define PCI_ERRCMD_ByteEn_GET(v) PCI__EXT(v, 8, 8) +#define PCI_ERRCMD_PAR PCI__BIT(16) +#define PCI_ERRCMD_PAR64 PCI__BIT(17) + +/* + * Table 314: PCI Interrupt Cause + * 1. All bits are Clear Only. A cause bit set upon error event occurrence. + * A write of 0 clears the bit. A write of 1 has no affect. + * 2. PCI Interrupt bits are organized in four groups: + * bits[ 7: 0] for address and data parity errors, + * bits[15: 8] for PCI master transaction failure (possible external + * target problem), + * bits[23:16] for slave response failure (possible external master problem), + * bits[26:24] for external PCI events that require CPU handle. + */ +#define PCI_IC_SAPerr PCI__BIT(0) /* The PCI slave detected + * bad address parity. */ +#define PCI_IC_SWrPerr PCI__BIT(1) /* The PCI slave detected + * bad write data parity. */ +#define PCI_IC_SRdPerr PCI__BIT(2) /* PERR* response to read + * data driven by PCI slave. */ +#define PCI_IC_MAPerr PCI__BIT(4) /* PERR* response to address + * driven by the PCI master. */ +#define PCI_IC_MWrPerr PCI__BIT(5) /* PERR* response to write data + * driven by the PCI master. */ +#define PCI_IC_MRdPerr PCI__BIT(6) /* Bad data parity detected + * during the PCI master read + * transaction. */ +#define PCI_IC_MMabort PCI__BIT(8) /* The PCI master generated + * master abort. */ +#define PCI_IC_MTabort PCI__BIT(9) /* The PCI master detected + * target abort. */ +#define PCI_IC_MMasterEn PCI__BIT(10) /* An attempt to generate a PCI + * transaction while master is + * not enabled. */ +#define PCI_IC_MRetry PCI__BIT(11) /* The PCI master reached + * retry counter limit. */ +#define PCI_IC_SMabort PCI__BIT(16) /* The PCI slave detects an il- + * legal master termination. */ +#define PCI_IC_STabort PCI__BIT(17) /* The PCI slave terminates a + * transaction with Target + * Abort. */ +#define PCI_IC_SAccProt PCI__BIT(18) /* A PCI slave access protect + * violation. */ +#define PCI_IC_SWrProt PCI__BIT(19) /* A PCI slave write protect + * violation. */ +#define PCI_IC_SRdBuf PCI__BIT(20) /* A PCI slave read buffer + * discard timer expired. */ +#define PCI_IC_Arb PCI__BIT(21) /* Internal PCI arbiter detec- + * tion of a broken master. */ +#define PCI_IC_BIST PCI__BIT(24) /* PCI BIST Interrupt */ +#define PCI_IC_PMG PCI__BIT(25) /* PCI Power Management + * Interrupt */ +#define PCI_IC_PRST PCI__BIT(26) /* PCI Reset Assert */ + +/* +31:27 Sel Specifies the error event currently being reported in the +Error Address, Error Data, and Error Command registers. +*/ +#define PCI_IC_SEL_GET(v) PCI__EXT((v), 27, 5) +#define PCI_IC_SEL_SAPerr 0x00 +#define PCI_IC_SEL_SWrPerr 0x01 +#define PCI_IC_SEL_SRdPerr 0x02 +#define PCI_IC_SEL_MAPerr 0x04 +#define PCI_IC_SEL_MWrPerr 0x05 +#define PCI_IC_SEL_MRdPerr 0x06 +#define PCI_IC_SEL_MMabort 0x08 +#define PCI_IC_SEL_MTabort 0x09 +#define PCI_IC_SEL_MMasterEn 0x0a +#define PCI_IC_SEL_MRetry 0x0b +#define PCI_IC_SEL_SMabort 0x10 +#define PCI_IC_SEL_STabort 0x11 +#define PCI_IC_SEL_SAccProt 0x12 +#define PCI_IC_SEL_SWrProt 0x13 +#define PCI_IC_SEL_SRdBuf 0x14 +#define PCI_IC_SEL_Arb 0x15 +#define PCI_IC_SEL_BIST 0x18 +#define PCI_IC_SEL_PMG 0x19 +#define PCI_IC_SEL_PRST 0x1a + +#define PCI_IC_SEL_Strings { \ + "SAPerr", "SWrPerr", "SRdPerr", "Rsvd#03", \ + "MAPerr", "MWrPerr", "MRdPerr", "Rsvd#07", \ + "MMabort", "MTabort", "MMasterEn", "MRetry", \ + "Rsvd#0c", "Rsvd#0d", "Rsvd#0e", "Rsvd#0f", \ + "SMabort", "STabort", "SAccProt", "SWrProt", \ + "SRdBuf", "Arb", "Rsvd#16", "Rsvd#17", \ + "BIST", "PMG", "PRST", "Rsvd#1b", \ + "Rsvd#1c", "Rsvd#1d", "Rsvd#1e", "Rsvd#1f" } + +/* + * Table 315: PCI Error Mask + * If the corresponding bit is 1, that interrupt is enabled + * Bits 3, 7, 12:15, 22:23, 27:31 are reserved. + */ +#define PCI_ERRMASK_SAPErr PCI__BIT(0) +#define PCI_ERRMASK_SWrPErr PCI__BIT(1) +#define PCI_ERRMASK_SRdPErr PCI__BIT(2) +#define PCI_ERRMASK_MAPErr PCI__BIT(4) +#define PCI_ERRMASK_MWRPErr PCI__BIT(5) +#define PCI_ERRMASK_MRDPErr PCI__BIT(6) +#define PCI_ERRMASK_MMAbort PCI__BIT(8) +#define PCI_ERRMASK_MTAbort PCI__BIT(9) +#define PCI_ERRMASK_MMasterEn PCI__BIT(10) +#define PCI_ERRMASK_MRetry PCI__BIT(11) +#define PCI_ERRMASK_SMAbort PCI__BIT(16) +#define PCI_ERRMASK_STAbort PCI__BIT(17) +#define PCI_ERRMASK_SAccProt PCI__BIT(18) +#define PCI_ERRMASK_SWrProt PCI__BIT(19) +#define PCI_ERRMASK_SRdBuf PCI__BIT(20) +#define PCI_ERRMASK_Arb PCI__BIT(21) +#define PCI_ERRMASK_BIST PCI__BIT(24) +#define PCI_ERRMASK_PMG PCI__BIT(25) +#define PCI_ERRMASK_PRST PCI__BIT(26) + +#endif /* _DEV_GTPCIREG_H_ */ diff --git a/bsps/powerpc/beatnik/include/bsp/gtreg.h b/bsps/powerpc/beatnik/include/bsp/gtreg.h new file mode 100644 index 0000000000..a6c87e2047 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/gtreg.h @@ -0,0 +1,854 @@ +/* $NetBSD: gtreg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DISCOVERY_DEV_GTREG_H_ +#define _DISCOVERY_DEV_GTREG_H_ + + +#define GT__BIT(bit) (1U << (bit)) +#define GT__MASK(bit) (GT__BIT(bit) - 1) +#define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) +#define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) +#define GT__INS(new, bit) ((new) << (bit)) + + +/* + * Table 30: CPU Address Decode Register Map + */ +#define GT_SCS0_Low_Decode 0x0008 +#define GT_SCS0_High_Decode 0x0010 +#define GT_SCS1_Low_Decode 0x0208 +#define GT_SCS1_High_Decode 0x0210 +#define GT_SCS2_Low_Decode 0x0018 +#define GT_SCS2_High_Decode 0x0020 +#define GT_SCS3_Low_Decode 0x0218 +#define GT_SCS3_High_Decode 0x0220 +#define GT_CS0_Low_Decode 0x0028 +#define GT_CS0_High_Decode 0x0030 +#define GT_CS1_Low_Decode 0x0228 +#define GT_CS1_High_Decode 0x0230 +#define GT_CS2_Low_Decode 0x0248 +#define GT_CS2_High_Decode 0x0250 +#define GT_CS3_Low_Decode 0x0038 +#define GT_CS3_High_Decode 0x0040 +#define GT_BootCS_Low_Decode 0x0238 +#define GT_BootCS_High_Decode 0x0240 +#define GT_PCI0_IO_Low_Decode 0x0048 +#define GT_PCI0_IO_High_Decode 0x0050 +#define GT_PCI0_Mem0_Low_Decode 0x0058 +#define GT_PCI0_Mem0_High_Decode 0x0060 +#define GT_PCI0_Mem1_Low_Decode 0x0080 +#define GT_PCI0_Mem1_High_Decode 0x0088 +#define GT_PCI0_Mem2_Low_Decode 0x0258 +#define GT_PCI0_Mem2_High_Decode 0x0260 +#define GT_PCI0_Mem3_Low_Decode 0x0280 +#define GT_PCI0_Mem3_High_Decode 0x0288 +#define GT_PCI1_IO_Low_Decode 0x0090 +#define GT_PCI1_IO_High_Decode 0x0098 +#define GT_PCI1_Mem0_Low_Decode 0x00a0 +#define GT_PCI1_Mem0_High_Decode 0x00a8 +#define GT_PCI1_Mem1_Low_Decode 0x00b0 +#define GT_PCI1_Mem1_High_Decode 0x00b8 +#define GT_PCI1_Mem2_Low_Decode 0x02a0 +#define GT_PCI1_Mem2_High_Decode 0x02a8 +#define GT_PCI1_Mem3_Low_Decode 0x02b0 +#define GT_PCI1_Mem3_High_Decode 0x02b8 +#define GT_Internal_Decode 0x0068 +#define GT_CPU0_Low_Decode 0x0290 +#define GT_CPU0_High_Decode 0x0298 +#define GT_CPU1_Low_Decode 0x02c0 +#define GT_CPU1_High_Decode 0x02c8 +/* ts, 2005/8: it seems that these are implicitely written + * when setting the 'Low_Decode' regs... + */ +#define GT_PCI0_IO_Remap 0x00f0 +#define GT_PCI0_Mem0_Remap_Low 0x00f8 +#define GT_PCI0_Mem0_Remap_High 0x0320 +#define GT_PCI0_Mem1_Remap_Low 0x0100 +#define GT_PCI0_Mem1_Remap_High 0x0328 +#define GT_PCI0_Mem2_Remap_Low 0x02f8 +#define GT_PCI0_Mem2_Remap_High 0x0330 +#define GT_PCI0_Mem3_Remap_Low 0x0300 +#define GT_PCI0_Mem3_Remap_High 0x0338 +#define GT_PCI1_IO_Remap 0x0108 +#define GT_PCI1_Mem0_Remap_Low 0x0110 +#define GT_PCI1_Mem0_Remap_High 0x0340 +#define GT_PCI1_Mem1_Remap_Low 0x0118 +#define GT_PCI1_Mem1_Remap_High 0x0348 +#define GT_PCI1_Mem2_Remap_Low 0x0310 +#define GT_PCI1_Mem2_Remap_High 0x0350 +#define GT_PCI1_Mem3_Remap_Low 0x0318 +#define GT_PCI1_Mem3_Remap_High 0x0358 + + +/* + * Table 31: CPU Control Register Map + */ +#define GT_CPU_Cfg 0x0000 +#define GT_CPU_Mode 0x0120 +#define GT_CPU_Master_Ctl 0x0160 +#define GT_CPU_If_Xbar_Ctl_Low 0x0150 +#define GT_CPU_If_Xbar_Ctl_High 0x0158 +#define GT_CPU_If_Xbar_Timeout 0x0168 +#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 +#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 + +/* + * Table 32: CPU Sync Barrier Register Map + */ +#define GT_260_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) +#define GT_260_PCI0_Sync_Barrier 0x00c0 +#define GT_260_PCI1_Sync_Barrier 0x00c8 + +/* + * Table 33: CPU Access Protection Register Map + */ +#define GT_Protect_Low_0 0x0180 +#define GT_Protect_High_0 0x0188 +#define GT_Protect_Low_1 0x0190 +#define GT_Protect_High_1 0x0198 +#define GT_Protect_Low_2 0x01a0 +#define GT_Protect_High_2 0x01a8 +#define GT_Protect_Low_3 0x01b0 +#define GT_Protect_High_3 0x01b8 +#define GT_260_Protect_Low_4 0x01c0 +#define GT_260_Protect_High_4 0x01c8 +#define GT_260_Protect_Low_5 0x01d0 +#define GT_260_Protect_High_5 0x01d8 +#define GT_260_Protect_Low_6 0x01e0 +#define GT_260_Protect_High_6 0x01e8 +#define GT_260_Protect_Low_7 0x01f0 +#define GT_260_Protect_High_7 0x01f8 + +/* + * Table 34: Snoop Control Register Map + */ +#define GT_260_Snoop_Base_0 0x0380 +#define GT_260_Snoop_Top_0 0x0388 +#define GT_260_Snoop_Base_1 0x0390 +#define GT_260_Snoop_Top_1 0x0398 +#define GT_260_Snoop_Base_2 0x03a0 +#define GT_260_Snoop_Top_2 0x03a8 +#define GT_260_Snoop_Base_3 0x03b0 +#define GT_260_Snoop_Top_3 0x03b8 + +/* + * Table 35: CPU Error Report Register Map + */ +#define GT_CPU_Error_Address_Low 0x0070 +#define GT_CPU_Error_Address_High 0x0078 +#define GT_CPU_Error_Data_Low 0x0128 +#define GT_CPU_Error_Data_High 0x0130 +#define GT_CPU_Error_Parity 0x0138 +#define GT_CPU_Error_Cause 0x0140 +#define GT_CPU_Error_Mask 0x0148 + +#define GT_DecodeAddr_SET(g, r, v) \ + do { \ + gt_read((g), GT_Internal_Decode); \ + gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ + while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ + } while (0) + +#define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) +#define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) + +#define GT_MPP_Control0 0xf000 +#define GT_MPP_Control1 0xf004 +#define GT_MPP_Control2 0xf008 +#define GT_MPP_Control3 0xf00c + +#define GT_GPP_IO_Control 0xf100 +#define GT_GPP_Level_Control 0xf110 +#define GT_GPP_Value 0xf104 +#define GT_GPP_Interrupt_Cause 0xf108 +#define GT_GPP_Interrupt_Mask 0xf10c +/* + * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 + * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 + * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 + * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 + * Table 44: CS[0]* Low Decode Address, Offset: 0x028 + * Table 46: CS[1]* Low Decode Address, Offset: 0x228 + * Table 48: CS[2]* Low Decode Address, Offset: 0x248 + * Table 50: CS[3]* Low Decode Address, Offset: 0x038 + * Table 52: BootCS* Low Decode Address, Offset: 0x238 + * Table 75: CPU 0 Low Decode Address, Offset: 0x290 + * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 + * + * 11:00 LowAddr SCS[0] Base Address + * 31:12 Reserved Must be 0. + */ + +/* + * Table 37: SCS[0]* High Decode Address, Offset: 0x010 + * Table 39: SCS[1]* High Decode Address, Offset: 0x210 + * Table 41: SCS[2]* High Decode Address, Offset: 0x020 + * Table 43: SCS[3]* High Decode Address, Offset: 0x220 + * Table 45: CS[0]* High Decode Address, Offset: 0x030 + * Table 47: CS[1]* High Decode Address, Offset: 0x230 + * Table 49: CS[2]* High Decode Address, Offset: 0x250 + * Table 51: CS[3]* High Decode Address, Offset: 0x040 + * Table 53: BootCS* High Decode Address, Offset: 0x240 + * Table 76: CPU 0 High Decode Address, Offset: 0x298 + * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 + * + * 11:00 HighAddr SCS[0] Top Address + * 31:12 Reserved + */ + +/* + * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 + * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 + * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 + * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 + * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 + * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 + * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 + * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 + * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 + * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 + * + * 11:00 LowAddr PCI IO/Memory Space Base Address + * 23:12 Reserved + * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; + * 1: No swapping; 2: Both byte and word swap; + * 3: Word swap; 4..7: Reserved) + * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when + * configured to 64-bit PCI bus and not I/O) + * 0: Assert s REQ64* only when transaction + * is longer than 64-bits. + * 1: Always assert REQ64*. + * 31:28 Reserved + */ +#define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) +#define GT_PCISwap_ByteSwap 0 +#define GT_PCISwap_NoSwap 1 +#define GT_PCISwap_ByteWordSwap 2 +#define GT_PCISwap_WordSwap 3 +#define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) + +/* + * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 + * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 + * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 + * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 + * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 + * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 + * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 + * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 + * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 + * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 + * + * 11:00 HighAddr PCI_0 I/O Space Top Address + * 31:12 Reserved + */ + +/* + * Table 74: Internal Space Decode, Offset: 0x068 + * 15:00 IntDecode GT64260 Internal Space Base Address + * 23:16 Reserved + * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. + * NOTE: Reserved for Galileo Technology usage. + * Relevant only for PCI master configuration + * transactions on the PCI bus. + * 31:27 Reserved + */ + +/* + * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 + * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 + * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 + * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 + * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 + * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 + * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 + * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 + * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 + * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 + * + * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) + * 31:12 Reserved + */ + +/* + * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 + * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 + * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 + * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 + * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 + * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 + * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 + * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 + * + * 31:00 Remap PCI Memory Address Remap (high 32 bits) + */ + +/* + * Table 97: CPU Configuration, Offset: 0x000 + * 07:00 NoMatchCnt CPU Address Miss Counter + * 08:08 NoMatchCntEn CPU Address Miss Counter Enable + * NOTE: Relevant only if multi-GT is enabled. + * (0: Disabled; 1: Enabled) + * 09:09 NoMatchCntExt CPU address miss counter MSB + * 10:10 Reserved + * 11:11 AACKDelay Address Acknowledge Delay + * 0: AACK* is asserted one cycle after TS*. + * 1: AACK* is asserted two cycles after TS*. + * 12:12 Endianess Must be 0 + * NOTE: The GT64260 does not support the PowerPC + * Little Endian convention + * 13:13 Pipeline Pipeline Enable + * 0: Disabled. The GT64260 will not respond with + * AACK* to a new CPU transaction, before the + * previous transaction data phase completes. + * 1: Enabled. + * 14:14 Reserved + * 15:15 TADelay Transfer Acknowledge Delay + * 0: TA* is asserted one cycle after AACK* + * 1: TA* is asserted two cycles after AACK* + * 16:16 RdOOO Read Out of Order Completion + * 0: Not Supported, Data is always returned in + * order (DTI[0-2] is always driven + * 1: Supported + * 17:17 StopRetry Relevant only if PCI Retry is enabled + * 0: Keep Retry all PCI transactions targeted + * to the GT64260. + * 1: Stop Retry of PCI transactions. + * 18:18 MultiGTDec Multi-GT Address Decode + * 0: Normal address decoding + * 1: Multi-GT address decoding + * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 21:20 Reserved + * 22:22 PErrProp Parity Error Propagation + * 0: GT64260 always drives good parity on + * DP[0-7] during CPU reads. + * 1: GT64260 drives bad parity on DP[0-7] in case + * the read response from the target interface + * comes with erroneous data indication + * (e.g. ECC error from SDRAM interface). + * 25:23 Reserved + * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 27:27 RemapWrDis Address Remap Registers Write Control + * 0: Write to Low Address decode register. + * Results in writing of the corresponding + * Remap register. + * 1: Write to Low Address decode register. No + * affect on the corresponding Remap register. + * 28:28 ConfSBDis Configuration Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 29:29 IOSBDis I/O Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 30:30 ClkSync Clocks Synchronization + * 0: The CPU interface is running with SysClk, + * which is asynchronous to TClk. + * 1: The CPU interface is running with TClk. + * 31:31 Reserved + */ +#define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) +#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) +#define GT_CPUCfg_NoMatchCntExt GT__BIT(10) +#define GT_CPUCfg_AACKDelay GT__BIT(11) +#define GT_CPUCfg_Endianess GT__BIT(12) +#define GT_CPUCfg_Pipeline GT__BIT(13) +#define GT_CPUCfg_TADelay GT__BIT(15) +#define GT_CPUCfg_RdOOO GT__BIT(16) +#define GT_CPUCfg_StopRetry GT__BIT(17) +#define GT_CPUCfg_MultiGTDec GT__BIT(18) +#define GT_CPUCfg_DPValid GT__BIT(19) +#define GT_CPUCfg_PErrProp GT__BIT(22) +#define GT_CPUCfg_APValid GT__BIT(26) +#define GT_CPUCfg_RemapWrDis GT__BIT(27) +#define GT_CPUCfg_ConfSBDis GT__BIT(28) +#define GT_CPUCfg_IOSBDis GT__BIT(29) +#define GT_CPUCfg_ClkSync GT__BIT(30) + +/* + * Table 98: CPU Mode, Offset: 0x120, Read only + * 01:00 MultiGTID Multi-GT ID + * Represents the ID to which the GT64260 responds + * to during a multi-GT address decoding period. + * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration + * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions + * 07:04 CPUType + * 0x0-0x3: Reserved + * 0x4: 64-bit PowerPC CPU, 60x bus + * 0x5: 64-bit PowerPC CPU, MPX bus + * 0x6-0xf: Reserved + * 31:08 Reserved + */ +#define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) +#define GT_CPUMode_MultiGT GT__BIT(2) +#define GT_CPUMode_RetryEn GT__BIT(3) +#define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) + +/* + * Table 99: CPU Master Control, Offset: 0x160 + * 07:00 Reserved + * 08:08 IntArb CPU Bus Internal Arbiter Enable + * NOTE: Only relevant to 60x bus mode. When + * running MPX bus, the GT64260 internal + * arbiter must be used. + * 0: Disabled. External arbiter is required. + * 1: Enabled. Use the GT64260 CPU bus arbiter. + * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control + * NOTE: This bit must be set to 1. It is reserved + * for Galileo Technology usage. + * 0: Enable internal bus sharing between master + * and slave interfaces. + * 1: Disable internal bus sharing between master + * and slave interfaces. + * 10:10 MWrTrig Master Write Transaction Trigger + * 0: With first valid write data + * 1: With last valid write data + * 11:11 MRdTrig Master Read Response Trigger + * 0: With first valid read data + * 1: With last valid read data + * 12:12 CleanBlock Clean Block Snoop Transaction Support + * 0: CPU does not support clean block (603e,750) + * 1: CPU supports clean block (604e,G4) + * 13:13 FlushBlock Flush Block Snoop Transaction Support + * 0: CPU does not support flush block (603e,750) + * 1: CPU supports flush block (604e,G4) + * 31:14 Reserved + */ +#define GT_CPUMstrCtl_IntArb GT__BIT(8) +#define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) +#define GT_CPUMstrCtl_MWrTrig GT__BIT(10) +#define GT_CPUMstrCtl_MRdTrig GT__BIT(11) +#define GT_CPUMstrCtl_CleanBlock GT__BIT(12) +#define GT_CPUMstrCtl_FlushBlock GT__BIT(13) + +#define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ +#define GT_ArbSlice_DEVICE 0x1 /* Device request */ +#define GT_ArbSlice_NULL 0x2 /* NULL request */ +#define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ +#define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ +#define GT_ArbSlice_COMM 0x5 /* Comm unit access */ +#define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ +#define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ + /* 0x8-0xf: Reserved */ + +/* Pass in the slice number (from 0..16) as 'n' + */ +#define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) + +/* + * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 + * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter + */ + +/* + * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 + * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter + */ + +/* + * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 + * NOTE: Reserved for Galileo Technology usage. + * 07:00 Timeout Crossbar Arbiter Timeout Preset Value + * 15:08 Reserved + * 16:16 TimeoutEn Crossbar Arbiter Timer Enable + * (0: Enable; 1: Disable) + * 31:17 Reserved + */ + +/* + * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 + * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter + */ +/* + * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 + * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter + */ + +/* + * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 + * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 + * NOTE: The read data is random and should be ignored. + * 31:00 SyncBarrier A CPU read from this register creates a + * synchronization barrier cycle. + */ + +/* + * Table 107: CPU Protect Address 0 Low, Offset: 0x180 + * Table 109: CPU Protect Address 1 Low, Offset: 0x190 + * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 + * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 + * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 + * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 + * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 + * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 + * + * 11:00 LowAddr CPU Protect Region Base Address + * Corresponds to address bits[31:20]. + * 15:12 Reserved. Must be 0 + * 16:16 AccProtect CPU Access Protect + * Access is (0: allowed; 1: forbidden) + * 17:17 WrProtect CPU Write Protect + * Writes are (0: allowed; 1: forbidden) + * 18:18 CacheProtect CPU caching protect. Caching (block read) + * is (0: allowed; 1: forbidden) + * 31:19 Reserved + */ +#define GT_CPU_AccProtect GT__BIT(16) +#define GT_CPU_WrProtect GT__BIT(17) +#define GT_CPU_CacheProtect GT__BIT(18) + +/* + * Table 108: CPU Protect Address 0 High, Offset: 0x188 + * Table 110: CPU Protect Address 1 High, Offset: 0x198 + * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 + * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 + * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 + * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 + * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 + * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 + * + * 11:00 HighAddr CPU Protect Region Top Address + * Corresponds to address bits[31:20] + * 31:12 Reserved + */ + +/* + * Table 123: Snoop Base Address 0, Offset: 0x380 + * Table 125: Snoop Base Address 1, Offset: 0x390 + * Table 127: Snoop Base Address 2, Offset: 0x3a0 + * Table 129: Snoop Base Address 3, Offset: 0x3b0 + * + * 11:00 LowAddr Snoop Region Base Address [31:20] + * 15:12 Reserved Must be 0. + * 17:16 Snoop Snoop Type + * 0x0: No Snoop + * 0x1: Snoop to WT region + * 0x2: Snoop to WB region + * 0x3: Reserved + * 31:18 Reserved + */ +#define GT_Snoop_GET(v) GT__EXT((v), 16, 2) +#define GT_Snoop_INS(v) GT__INS((v), 16) +#define GT_Snoop_None 0 +#define GT_Snoop_WT 1 +#define GT_Snoop_WB 2 + + +/* + * Table 124: Snoop Top Address 0, Offset: 0x388 + * Table 126: Snoop Top Address 1, Offset: 0x398 + * Table 128: Snoop Top Address 2, Offset: 0x3a8 + * Table 130: Snoop Top Address 3, Offset: 0x3b8 + * 11:00 HighAddr Snoop Region Top Address [31:20] + * 31:12 Reserved + */ + + +/* + * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. + * In case of multiple errors, only the first one is latched. New error + * report latching is enabled only after the CPU Error Address Low register + * is being read. + * 31:00 ErrAddr Latched address bits [31:0] of a CPU + * transaction in case of: + * o illegal address (failed address decoding) + * o access protection violation + * o bad data parity + * o bad address parity + * Upon address latch, no new address are + * registered (due to additional error condition), + * until the register is being read. + */ + +/* + * Table 132: CPU Error Address High, Offset: 0x078, Read Only. + * Once data is latched, no new data can be registered (due to additional + * error condition), until CPU Error Low Address is being read (which + * implies, it should be the last being read by the interrupt handler). + * 03:00 Reserved + * 07:04 ErrPar Latched address parity bits in case + * of bad CPU address parity detection. + * 31:08 Reserved + */ +#define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) + +/* + * Table 133: CPU Error Data Low, Offset: 0x128, Read only. + * 31:00 PErrData Latched data bits [31:0] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 134: CPU Error Data High, Offset: 0x130, Read only. + * 31:00 PErrData Latched data bits [63:32] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 135: CPU Error Parity, Offset: 0x138, Read only. + * 07:00 PErrPar Latched data parity bus in case of bad data + * parity sampled on write transactions or on + * master read transactions. + * 31:10 Reserved + */ +#define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) + +/* + * Table 136: CPU Error Cause, Offset: 0x140 + * Bits[7:0] are clear only. A cause bit is set upon an error condition + * occurrence. Write a 0 value to clear the bit. Writing a 1 value has + * no affect. + * 00:00 AddrOut CPU Address Out of Range + * 01:01 AddrPErr Bad Address Parity Detected + * 02:02 TTErr Transfer Type Violation. + * The CPU attempts to burst (read or write) to an + * internal register. + * 03:03 AccErr Access to a Protected Region + * 04:04 WrErr Write to a Write Protected Region + * 05:05 CacheErr Read from a Caching protected region + * 06:06 WrDataPErr Bad Write Data Parity Detected + * 07:07 RdDataPErr Bad Read Data Parity Detected + * 26:08 Reserved + * 31:27 Sel Specifies the error event currently being + * reported in Error Address, Error Data, and + * Error Parity registers. + * 0x0: AddrOut + * 0x1: AddrPErr + * 0x2: TTErr + * 0x3: AccErr + * 0x4: WrErr + * 0x5: CacheErr + * 0x6: WrDataPErr + * 0x7: RdDataPErr + * 0x8-0x1f: Reserved + */ +#define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) +#define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) +#define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) +#define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) +#define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) +#define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) +#define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) +#define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) + +#define GT_CPUError_Sel_AddrOut 0 +#define GT_CPUError_Sel_AddrPErr 1 +#define GT_CPUError_Sel_TTErr 2 +#define GT_CPUError_Sel_AccErr 3 +#define GT_CPUError_Sel_WrErr 4 +#define GT_CPUError_Sel_CacheErr 5 +#define GT_CPUError_Sel_WrDataPErr 6 +#define GT_CPUError_Sel_RdDataPErr 7 + +#define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) + +/* + * Table 137: CPU Error Mask, Offset: 0x148 + * 00:00 AddrOut If set to 1, enables AddrOut interrupt. + * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. + * 02:02 TTErr If set to 1, enables TTErr interrupt. + * 03:03 AccErr If set to 1, enables AccErr interrupt. + * 04:04 WrErr If set to 1, enables WrErr interrupt. + * 05:05 CacheErr If set to 1, enables CacheErr interrupt. + * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. + * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. + * 31:08 Reserved + */ + +/* + * Comm Unit Interrupt registers + */ + +/* Comm Unit Arbiter Control */ +#define GT_CommUnitArb_Ctrl 0xf300 +/* GPP IRQs level vs. edge sensitivity */ +#define GT_CommUnitArb_Ctrl_GPP_Ints_Level_Sensitive (1<<10) + +#define GT_CommUnitIntr_Cause 0xf310 +#define GT_CommUnitIntr_Mask 0xf314 +#define GT_CommUnitIntr_ErrAddr 0xf318 + +#define GT_CommUnitIntr_E0 0x00000007 +#define GT_CommUnitIntr_E1 0x00000070 +#define GT_CommUnitIntr_E2 0x00000700 +#define GT_CommUnitIntr_S0 0x00070000 +#define GT_CommUnitIntr_S1 0x00700000 +#define GT_CommUnitIntr_Sel 0x70000000 + +/* + * SDRAM Error Report (ECC) Registers + */ +#define GT_260_ECC_Data_Lo 0x484 /* latched Error Data (low) */ +#define GT_260_ECC_Data_Hi 0x480 /* latched Error Data (high) */ +#define GT_260_ECC_Addr 0x490 /* latched Error Address */ +#define GT_260_ECC_Rec 0x488 /* latched ECC code from SDRAM */ +#define GT_260_ECC_Calc 0x48c /* latched ECC code from SDRAM */ +#define GT_260_ECC_Ctl 0x494 /* ECC Control */ +#define GT_260_ECC_Count 0x498 /* ECC 1-bit error count */ + +/* Timer/Counter Registers (t. straumann) + */ +#define GT_TIMER_0 0x0850 /* preset / running value */ +#define GT_TIMER_1 0x0854 +#define GT_TIMER_2 0x0858 +#define GT_TIMER_3 0x085c + +#define GT_TIMER_0_3_Ctl 0x0864 + +#define GT_TIMER_0_Ctl_Enb 0x00000001 /* enable timer */ +#define GT_TIMER_0_Ctl_Rld 0x00000002 /* reload after expiration */ +#define GT_TIMER_1_Ctl_Enb 0x00000100 /* enable timer */ +#define GT_TIMER_1_Ctl_Rld 0x00000200 /* reload after expiration */ +#define GT_TIMER_2_Ctl_Enb 0x00010000 /* enable timer */ +#define GT_TIMER_2_Ctl_Rld 0x00020000 /* reload after expiration */ +#define GT_TIMER_3_Ctl_Enb 0x01000000 /* enable timer */ +#define GT_TIMER_3_Ctl_Rld 0x02000000 /* reload after expiration */ + +#define GT_TIMER_0_3_Intr_Cse 0x0868 +#define GT_TIMER_0_Intr 0x00000001 +#define GT_TIMER_1_Intr 0x00000002 +#define GT_TIMER_2_Intr 0x00000004 +#define GT_TIMER_3_Intr 0x00000008 +#define GT_TIMER_Intr_Smry 0x80000000 /* Interrupt Summary */ + +#define GT_TIMER_0_3_Intr_Msk 0x086c + +/* + * Watchdog Registers + */ +#define GT_WDOG_Config 0xb410 +#define GT_WDOG_Value 0xb414 +#define GT_WDOG_Value_NMI GT__MASK(24) +#define GT_WDOG_Config_Preset GT__MASK(24) +#define GT_WDOG_Config_Ctl1a GT__BIT(24) +#define GT_WDOG_Config_Ctl1b GT__BIT(25) +#define GT_WDOG_Config_Ctl2a GT__BIT(26) +#define GT_WDOG_Config_Ctl2b GT__BIT(27) +#define GT_WDOG_Config_Enb GT__BIT(31) + +#define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) +#define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) + +/* + * Device Bus Interrupts + */ +#define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ +#define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ +#define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ + +/* + * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK + */ +#define GT_DEVBUS_DBurstErr GT__BIT(0) +#define GT_DEVBUS_DRdyErr GT__BIT(1) +#define GT_DEVBUS_Sel GT__BIT(27) +#define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) + +/* MV64360 */ +/* Enable individual CPU windows by *clearing* respective bits + * in MV_64360_BASE_ADDR_DISBL + * + * Bit ordering is: + * + * SDRAM_CS_0..3 (1<<0..3) + * DEV_CS_0..3 (1<<4..7) + * BOOT_CS_0..3 (1<<8) + * PCI_0_IO (1<<9) + * PCI_0_MEM_0..3 (1<<10..13) + * PCI_1_IO (1<<14) + * PCI_1_MEM_0..3 (1<<15..18) + * INTERNAL_SRAM (1<<19) + * MV64x60_REGS (1<<20) + */ +#define MV_64360_BASE_ADDR_DISBL (0x278) + +/* Internal SRAM */ +#define MV_64360_SRAM_BASE (0x268) +#define MV_64360_SRAM_CTRL (0x380) +/* Control register bits */ +#define MV_64360_SRAM_CacheWb GT__BIT(1) +/* default setup used by linux, motload (uses 90 instead of b0), ... + * Comments say: + * - parity enabled, + * - parity error propagation + * - arbitration not parked for CPU only + * - other bits are reserved + */ +#define MV_64360_SRAM_Ctl_Setup (0x001600b0) + +#define MV_64360_SRAM_TEST_MODE (0x3f4) +#define MV_64340_SRAM_ERR_CAUSE (0x388) +#define MV_64340_SRAM_ERR_ADDR (0x390) +#define MV_64340_SRAM_ERR_ADDR_HI (0X3f8) +#define MV_64340_SRAM_ERR_DATA_LO (0x398) +#define MV_64340_SRAM_ERR_DATA_HI (0x3a0) +#define MV_64340_SRAM_ERR_DATA_PARITY (0x3a8) + +#endif /* !_DISCOVERY_DEV_GTREG_H */ diff --git a/bsps/powerpc/beatnik/include/bsp/if_em_pub.h b/bsps/powerpc/beatnik/include/bsp/if_em_pub.h new file mode 100644 index 0000000000..eb970e465b --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/if_em_pub.h @@ -0,0 +1,22 @@ +#ifndef RTEMS_BSDNET_IF_EM_PUBLIC_SYMBOLS_H +#define RTEMS_BSDNET_IF_EM_PUBLIC_SYMBOLS_H + +#include <rtems.h> +#include <rtems/rtems_bsdnet.h> +#include <bsp/early_enet_link_status.h> + +#ifdef __cplusplus + extern "C" { +#endif + +extern int rtems_em_attach(struct rtems_bsdnet_ifconfig *, int); +extern int rtems_em_pci_setup(int); +extern rtems_bsdnet_early_link_check_ops rtems_em_early_link_check_ops; + +#ifdef __cplusplus + } +#endif + +#endif + + diff --git a/bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h b/bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h new file mode 100644 index 0000000000..8ea849efb1 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/if_gfe_pub.h @@ -0,0 +1,30 @@ +#ifndef RTEMS_BSDNET_IF_GFE_PUBLIC_SYMBOLS_H +#define RTEMS_BSDNET_IF_GFE_PUBLIC_SYMBOLS_H + +#include <rtems.h> +#include <rtems/rtems_bsdnet.h> +#include <bsp/early_enet_link_status.h> +#include <net/ethernet.h> + +#ifdef __cplusplus + extern "C" { +#endif + +extern int +rtems_gfe_attach(struct rtems_bsdnet_ifconfig *, int); + + +/* enet_addr must be 6 bytes long */ +int +rtems_gfe_setup(int unit, char *enet_addr, uint32_t base_addr); + +extern rtems_bsdnet_early_link_check_ops +rtems_gfe_early_link_check_ops; + +#ifdef __cplusplus + } +#endif + +#endif + + diff --git a/bsps/powerpc/beatnik/include/bsp/if_mve_pub.h b/bsps/powerpc/beatnik/include/bsp/if_mve_pub.h new file mode 100644 index 0000000000..0a84310d72 --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/if_mve_pub.h @@ -0,0 +1,422 @@ +#ifndef RTEMS_BSDNET_IF_MVE_PUBLIC_SYMBOLS_H +#define RTEMS_BSDNET_IF_MVE_PUBLIC_SYMBOLS_H + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ +#include <rtems.h> +#include <rtems/rtems_bsdnet.h> +#include <bsp/early_enet_link_status.h> +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +extern int rtems_mve_attach(struct rtems_bsdnet_ifconfig *, int); +extern rtems_bsdnet_early_link_check_ops rtems_mve_early_link_check_ops; + +/* Low-level Driver API. + * This provides driver access to applications that want to use e.g., the second + * ethernet interface w/o running the BSD TCP/IP stack. + */ + +/* Opaque handle */ +struct mveth_private; + +/* Direct assignment of MVE flags to user API relies on irqs and x-irqs not overlapping */ +#define BSP_MVE_IRQ_RX (1<<2) +#define BSP_MVE_IRQ_TX (1<<0) +#define BSP_MVE_IRQ_LINK (1<<16) + +/* Setup an interface. + * Allocates resources for descriptor rings and sets up the driver software structure. + * + * Arguments: + * unit: + * interface # (1..2). The interface must not be attached to BSD. + * + * driver_tid: + * ISR posts RTEMS event # ('unit' - 1) to task with ID 'driver_tid' and disables interrupts + * from this interface. + * + * void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred): + * Pointer to user-supplied callback to release a buffer that had been sent + * by BSP_mve_send_buf() earlier. The callback is passed 'cleanup_txbuf_arg' + * and a flag indicating whether the send had been successful. + * The driver no longer accesses 'user_buf' after invoking this callback. + * CONTEXT: This callback is executed either by BSP_mve_swipe_tx() or + * BSP_mve_send_buf(), BSP_mve_init_hw(), BSP_mve_stop_hw() (the latter + * ones calling BSP_mve_swipe_tx()). + * void *cleanup_txbuf_arg: + * Closure argument that is passed on to 'cleanup_txbuf()' callback; + * + * void *(*alloc_rxbuf)(int *p_size, unsigned long *p_data_addr), + * Pointer to user-supplied callback to allocate a buffer for subsequent + * insertion into the RX ring by the driver. + * RETURNS: opaque handle to the buffer (which may be a more complex object + * such as an 'mbuf'). The handle is not used by the driver directly + * but passed back to the 'consume_rxbuf()' callback. + * Size of the available data area and pointer to buffer's data area + * in '*psize' and '*p_data_area', respectively. + * If no buffer is available, this routine should return NULL in which + * case the driver drops the last packet and re-uses the last buffer + * instead of handing it out to 'consume_rxbuf()'. + * CONTEXT: Called when initializing the RX ring (BSP_mve_init_hw()) or when + * swiping it (BSP_mve_swipe_rx()). + * + * + * void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len); + * Pointer to user-supplied callback to pass a received buffer back to + * the user. The driver no longer accesses the buffer after invoking this + * callback (with 'len'>0, see below). 'user_buf' is the buffer handle + * previously generated by 'alloc_rxbuf()'. + * The callback is passed 'cleanup_rxbuf_arg' and a 'len' + * argument giving the number of bytes that were received. + * 'len' may be <=0 in which case the 'user_buf' argument is NULL. + * 'len' == 0 means that the last 'alloc_rxbuf()' had failed, + * 'len' < 0 indicates a receiver error. In both cases, the last packet + * was dropped/missed and the last buffer will be re-used by the driver. + * NOTE: the data are 'prefixed' with two bytes, i.e., the ethernet packet header + * is stored at offset 2 in the buffer's data area. Also, the FCS (4 bytes) + * is appended. 'len' accounts for both. + * CONTEXT: Called from BSP_mve_swipe_rx(). + * void *cleanup_rxbuf_arg: + * Closure argument that is passed on to 'consume_rxbuf()' callback; + * + * rx_ring_size, tx_ring_size: + * How many big to make the RX and TX descriptor rings. Note that the sizes + * may be 0 in which case a reasonable default will be used. + * If either ring size is < 0 then the RX or TX will be disabled. + * Note that it is illegal in this case to use BSP_mve_swipe_rx() or + * BSP_mve_swipe_tx(), respectively. + * + * irq_mask: + * Interrupts to enable. OR of flags from above. + * + */ +struct mveth_private * +BSP_mve_setup( + int unit, + rtems_id driver_tid, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void *cleanup_txbuf_arg, + void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void *consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + +/* + * Alternate 'setup' routine allowing the user to install an ISR rather + * than a task ID. + * All parameters (other than 'isr' / 'isr_arg') and the return value + * are identical to the BSP_mve_setup() entry point. + */ +struct mveth_private * +BSP_mve_setup_1( + int unit, + void (*isr)(void *isr_arg), + void *isr_arg, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void *cleanup_txbuf_arg, + void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void *consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + + +/* + * Initialize interface hardware + * + * 'mp' handle obtained by from BSP_mve_setup(). + * 'promisc' whether to set promiscuous flag. + * 'enaddr' pointer to six bytes with MAC address. Read + * from the device if NULL. + * + * Note: Multicast filters are cleared by this routine. + * However, in promiscuous mode the mcast filters + * are programmed to accept all multicast frames. + */ +void +BSP_mve_init_hw(struct mveth_private *mp, int promisc, unsigned char *enaddr); + +/* + * Clear multicast hash filter. No multicast frames are accepted + * after executing this routine (unless the hardware was initialized + * in 'promiscuous' mode). + */ +void +BSP_mve_mcast_filter_clear(struct mveth_private *mp); + +/* + * Program multicast filter to accept all multicast frames + */ +void +BSP_mve_mcast_filter_accept_all(struct mveth_private *mp); + +/* + * Add a MAC address to the multicast filter. + * Existing entries are not changed but note that + * the filter is imperfect, i.e., multiple MAC addresses + * may alias to a single filter entry. Hence software + * filtering must still be performed. + * + * If a higher-level driver implements IP multicasting + * then multiple IP addresses may alias to the same MAC + * address. This driver maintains a 'reference-count' + * which is incremented every time the same MAC-address + * is passed to this routine; the address is only removed + * from the filter if BSP_mve_mcast_filter_accept_del() + * is called the same number of times (or by BSP_mve_mcast_filter_clear). + */ +void +BSP_mve_mcast_filter_accept_add(struct mveth_private *mp, unsigned char *enaddr); + +/* + * Remove a MAC address from the multicast filter. + * This routine decrements the reference count of the given + * MAC-address and removes it from the filter once the + * count reaches zero. + */ +void +BSP_mve_mcast_filter_accept_del(struct mveth_private *mp, unsigned char *enaddr); + +/* + * Shutdown hardware and clean out the rings + */ +void +BSP_mve_stop_hw(struct mveth_private *mp); + +/* calls BSP_mve_stop_hw(), releases all resources and marks the interface + * as unused. + * RETURNS 0 on success, nonzero on failure. + * NOTE: the handle MUST NOT be used after successful execution of this + * routine. + */ +int +BSP_mve_detach(struct mveth_private *mp); + +/* + * Enqueue a mbuf chain or a raw data buffer for transmission; + * RETURN: #bytes sent or -1 if there are not enough free descriptors + * + * If 'len' is <=0 then 'm_head' is assumed to point to a mbuf chain. + * OTOH, a raw data packet (or a different type of buffer) + * may be send (non-BSD driver) by pointing data_p to the start of + * the data and passing 'len' > 0. + * 'm_head' is passed back to the 'cleanup_txbuf()' callback. + * + * Comments: software cache-flushing incurs a penalty if the + * packet cannot be queued since it is flushed anyways. + * The algorithm is slightly more efficient in the normal + * case, though. + * + * RETURNS: # bytes enqueued to device for transmission or -1 if no + * space in the TX ring was available. + */ +int +BSP_mve_send_buf(struct mveth_private *mp, void *m_head, void *data_p, int len); + +/* Descriptor scavenger; cleanup the TX ring, passing all buffers + * that have been sent to the cleanup_tx() callback. + * This routine is called from BSP_mve_send_buf(), BSP_mve_init_hw(), + * BSP_mve_stop_hw(). + * + * RETURNS: number of buffers processed. + */ +int +BSP_mve_swipe_tx(struct mveth_private *mp); + +/* Retrieve all received buffers from the RX ring, replacing them + * by fresh ones (obtained from the alloc_rxbuf() callback). The + * received buffers are passed to consume_rxbuf(). + * + * RETURNS: number of buffers processed. + */ +int +BSP_mve_swipe_rx(struct mveth_private *mp); + +/* read ethernet address from hw to buffer */ +void +BSP_mve_read_eaddr(struct mveth_private *mp, unsigned char *eaddr); + +/* read/write media word. + * 'cmd': can be SIOCGIFMEDIA, SIOCSIFMEDIA, 0 or 1. The latter + * are aliased to the former for convenience. + * 'parg': pointer to media word. + * + * RETURNS: 0 on success, nonzero on error + * + * NOTE: This routine is thread-safe. + */ +int +BSP_mve_media_ioctl(struct mveth_private *mp, int cmd, int *parg); + +/* Interrupt related routines */ + +/* Note: the BSP_mve_enable/disable/ack_irqs() entry points + * are deprecated. + * The newer API where the user passes a mask allows + * for more selective control. + */ + +/* Enable all supported interrupts at device */ +void +BSP_mve_enable_irqs(struct mveth_private *mp); + +/* Disable all supported interrupts at device */ +void +BSP_mve_disable_irqs(struct mveth_private *mp); + +/* Acknowledge (and clear) all supported interrupts. + * RETURNS: interrupts that were raised. + */ +uint32_t +BSP_mve_ack_irqs(struct mveth_private *mp); + +/* Enable interrupts included in 'mask' (leaving + * already enabled interrupts on). If the mask + * includes bits that were not passed to the 'setup' + * routine then the behavior is undefined. + */ +void +BSP_mve_enable_irq_mask(struct mveth_private *mp, uint32_t irq_mask); + +/* Disable interrupts included in 'mask' (leaving + * other ones that are currently enabled on). If the + * mask includes bits that were not passed to the 'setup' + * routine then the behavior is undefined. + * + * RETURNS: Bitmask of interrupts that were enabled upon entry + * into this routine. This can be used to restore the + * previous state. + */ +uint32_t +BSP_mve_disable_irq_mask(struct mveth_private *mp, uint32_t irq_mask); + +/* Acknowledge and clear selected interrupts. + * + * RETURNS: All pending interrupts. + * + * NOTE: Only pending interrupts contained in 'mask' + * are cleared. Others are left pending. + * + * This routine can be used to check for pending + * interrupts (pass mask == 0) or to clear all + * interrupts (pass mask == -1). + */ +uint32_t +BSP_mve_ack_irq_mask(struct mveth_private *mp, uint32_t mask); + +/* If the PHY link status changes then some + * internal settings in the ethernet controller's + * serial port need to be updated to match the + * PHY settings. Use this routine to perform the + * necessary steps after a link change has been + * detected. + * + * RETURNS: 0 on success, -1 if the PHY state + * could not be determined. + * + * The current state of the media as read + * by BSP_mve_media_ioctl() is returned in + * *pmedia. + * + * NOTE: This routine calls BSP_mve_media_ioctl(). + */ +int +BSP_mve_ack_link_chg(struct mveth_private *mp, int *pmedia); + +/* Retrieve the driver daemon TID that was passed to + * BSP_mve_setup(). + */ + +rtems_id +BSP_mve_get_tid(struct mveth_private *mp); + +/* Dump statistics to file (stdout if NULL) + * + * NOTE: this routine is not thread safe + */ +void +BSP_mve_dump_stats(struct mveth_private *mp, FILE *f); + +/* + * + * Example driver task loop (note: no synchronization of + * buffer access shown!). + * RTEMS_EVENTx = 0,1 or 2 depending on IF unit. + * + * / * setup (obtain handle) and initialize hw here * / + * + * do { + * / * ISR disables IRQs and posts event * / + * rtems_event_receive( RTEMS_EVENTx, RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &evs ); + * irqs = BSP_mve_ack_irqs(handle); + * if ( irqs & BSP_MVE_IRQ_TX ) { + * BSP_mve_swipe_tx(handle); / * cleanup_txbuf() callback executed * / + * } + * if ( irqs & BSP_MVE_IRQ_RX ) { + * BSP_mve_swipe_rx(handle); / * alloc_rxbuf() and consume_rxbuf() executed * / + * } + * if ( irqs & BSP_MVE_IRQ_LINK ) { + * / * update serial port settings from current link status * / + * BSP_mve_ack_link_chg(handle, 0); + * } + * BSP_mve_enable_irqs(handle); + * } while (1); + * + */ + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/bsp/irq.h b/bsps/powerpc/beatnik/include/bsp/irq.h new file mode 100644 index 0000000000..e5f9558ecf --- /dev/null +++ b/bsps/powerpc/beatnik/include/bsp/irq.h @@ -0,0 +1,133 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified by T. Straumann for the beatnik BSP, 2005-2007 + * Some information may be based on mvme5500/irq/irq.h by K. Feng. + */ + +#ifndef LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H +#define LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include <rtems/irq.h> +#include <bsp/vectors.h> + +/* This BSP also passes a pointer to the interrupt frame to the handler. + * The PPC ABI guarantees that this will not mess up handlers written + * without knowledge of this feature. + */ + +typedef void (*BSP_rtems_irq_hdl)(rtems_irq_hdl_param,BSP_Exception_frame*); + + +/* legal priorities are 0 <= priority <= MAX_PRIO; 0 effectively disables the interrupt */ +#define BSP_IRQ_MAX_PRIO 4 +#define BSP_IRQ_MIN_PRIO 1 + +/* Note that priorites are only honoured for 'PCI' interrupt numbers. + * The discovery pic has no support for hardware priorites; hence they + * are handled in software + */ +#define BSP_IRQ_DEFAULT_PRIORITY 2 + + +#define BSP_PCI_IRQ_LOWEST_OFFSET 0 /* IMPLEMENTATION RELIES ON discovery pic INTERRUPTS HAVING NUMBERS 0..95 */ +#define BSP_IRQ_DEV 1 /* device interface interrupt */ +#define BSP_IRQ_DMA 2 /* DMA addres error interrupt (260) */ +#define BSP_IRQ_CPU 3 /* CPU interface interrupt */ +#define BSP_IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt (260) */ +#define BSP_IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt (260) */ +#define BSP_IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt (260) */ +#define BSP_IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt (260) */ +#define BSP_IRQ_TIME0_1 8 /* Timer 0..1 interrupt; Timer 0 on 64360 */ +#define BSP_IRQ_TIME2_3 9 /* Timer 2..3 interrupt; Timer 1 on 64360 */ +#define BSP_IRQ_TIME4_5 10 /* Timer 4..5 interrupt; Timer 2 on 64360 */ +#define BSP_IRQ_TIME6_7 11 /* Timer 6..7 interrupt; Timer 3 on 64360 */ +#define BSP_IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary (PCI 0 interrupt summary on 64360) */ +#define BSP_IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary (SRAM PAR ERROR on 64360) */ +#define BSP_IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ +#define BSP_IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ +#define BSP_IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary (PCI 1 interrupt summary on 64360) */ +#define BSP_IRQ_ECC 17 /* ECC error interrupt */ +#define BSP_IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ +#define BSP_IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ +#define BSP_IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ +#define BSP_IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ +#define BSP_IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ +#define BSP_IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ +#define BSP_IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ +#define BSP_IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ +#define BSP_IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ +#define BSP_IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ +#define BSP_IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ +#define BSP_IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ +#define BSP_IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ +#define BSP_IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ +#define BSP_IRQ_SDMA (32+4) /* SDMA interrupt */ +#define BSP_IRQ_I2C (32+5) /* I2C interrupt */ +#define BSP_IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ +#define BSP_IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ +#define BSP_IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ +#define BSP_IRQ_COMM (32+11) /* Comm unit interrupt */ +#define BSP_IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt summary */ +#define BSP_IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt summary */ +#define BSP_IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt summary */ +#define BSP_IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt summary */ +#define BSP_IRQ_GPP_0 64 + +#define BSP_PCI_IRQ_NUMBER (64+32) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_PROCESSOR_IRQ_NUMBER 1 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + +/* summary */ + +#define BSP_IRQ_NUMBER (BSP_PCI_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER) +#define BSP_LOWEST_OFFSET 0 +#define BSP_MAX_OFFSET (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1) +#define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET + +#define BSP_UART_COM1_IRQ BSP_IRQ_GPP_0 +#define BSP_UART_COM2_IRQ BSP_IRQ_GPP_0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + + +#include <bsp/irq_supp.h> + +int BSP_irq_is_enabled_at_pic(rtems_irq_number irq); + +/* set priority of an interrupt; must not be called from ISR level */ +int BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri); + +/* Not for public use */ +void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + + +#endif + +#endif diff --git a/bsps/powerpc/beatnik/include/tm27.h b/bsps/powerpc/beatnik/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/beatnik/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/gen5200/headers.am b/bsps/powerpc/gen5200/headers.am new file mode 100644 index 0000000000..7a98ad9ec4 --- /dev/null +++ b/bsps/powerpc/gen5200/headers.am @@ -0,0 +1,45 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/ata.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/i2c.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/i2cdrv.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mpc5200.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mscan-base.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mscan.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/nvram.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/slicetimer.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/u-boot-config.h + +include_bsp_bestcommdir = $(includedir)/bsp/bestcomm +include_bsp_bestcomm_HEADERS = +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h +include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h + +include_bsp_bestcomm_includedir = $(includedir)/bsp/bestcomm/include +include_bsp_bestcomm_include_HEADERS = +include_bsp_bestcomm_include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h + +include_bsp_bestcomm_include_mgt5200dir = $(includedir)/bsp/bestcomm/include/mgt5200 +include_bsp_bestcomm_include_mgt5200_HEADERS = +include_bsp_bestcomm_include_mgt5200_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h +include_bsp_bestcomm_include_mgt5200_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h + +include_bsp_bestcomm_task_apidir = $(includedir)/bsp/bestcomm/task_api +include_bsp_bestcomm_task_api_HEADERS = +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h +include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h diff --git a/bsps/powerpc/gen5200/include/bsp.h b/bsps/powerpc/gen5200/include/bsp.h new file mode 100644 index 0000000000..40ac1116c5 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp.h @@ -0,0 +1,266 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + +#ifndef LIBBSP_POWERPC_GEN5200_BSP_H +#define LIBBSP_POWERPC_GEN5200_BSP_H + +#include <bspopts.h> + +#include <libcpu/powerpc-utility.h> + +/* + * Some symbols defined in the linker command file. + */ + +LINKER_SYMBOL(bsp_ram_start); +LINKER_SYMBOL(bsp_ram_end); +LINKER_SYMBOL(bsp_ram_size); + +LINKER_SYMBOL(bsp_rom_start); +LINKER_SYMBOL(bsp_rom_end); +LINKER_SYMBOL(bsp_rom_size); + +LINKER_SYMBOL(bsp_dpram_start); +LINKER_SYMBOL(bsp_dpram_end); +LINKER_SYMBOL(bsp_dpram_size); + +LINKER_SYMBOL(bsp_section_text_start); +LINKER_SYMBOL(bsp_section_text_end); +LINKER_SYMBOL(bsp_section_text_size); + +LINKER_SYMBOL(bsp_section_data_start); +LINKER_SYMBOL(bsp_section_data_end); +LINKER_SYMBOL(bsp_section_data_size); + +LINKER_SYMBOL(bsp_section_bss_start); +LINKER_SYMBOL(bsp_section_bss_end); +LINKER_SYMBOL(bsp_section_bss_size); + +LINKER_SYMBOL(bsp_interrupt_stack_start); +LINKER_SYMBOL(bsp_interrupt_stack_end); +LINKER_SYMBOL(bsp_interrupt_stack_size); + +LINKER_SYMBOL(bsp_work_area_start); + +LINKER_SYMBOL(MBAR); + +/* Provide legacy defines */ + +#ifdef MPC5200_BOARD_PM520_ZE30 +#define PM520_ZE30 +#endif + +#ifdef MPC5200_BOARD_PM520_CR825 +#define PM520_CR825 +#endif + +#ifdef MPC5200_BOARD_ICECUBE +#define icecube +#endif + +#ifdef MPC5200_BOARD_BRS5L +#define BRS5L +#endif + +/* + * distinguish board characteristics + */ +/* + * for PM520 mdule on a ZE30 carrier + */ +#if defined(MPC5200_BOARD_PM520_ZE30) +#define PM520 +#endif +/* + * for PM520 mdule on a CR825 carrier + */ +#if defined(MPC5200_BOARD_PM520_CR825) +#define PM520 +#endif + +#if !defined(HAS_UBOOT) + /* we need the low level initialization in start.S*/ + #define NEED_LOW_LEVEL_INIT +#endif + +#if defined(MPC5200_BOARD_BRS5L) +/* + * IMD Custom Board BRS5L + */ + +#define HAS_NVRAM_93CXX + +#elif defined(MPC5200_BOARD_BRS6L) + #define MPC5200_BRS6L_FPGA_BEGIN 0x800000 + #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024) + #define MPC5200_BRS6L_FPGA_END \ + (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE) + + #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000 + #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024) + #define MPC5200_BRS6L_MRAM_END \ + (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE) +#elif defined (PM520) + +/* Nothing special */ + +#elif defined (MPC5200_BOARD_ICECUBE) +/* + * Codename: IceCube + * Compatible Boards: + * Freescape MPC5200LITE + * Embedded Planet EP5200 + */ + +#elif defined (MPC5200_BOARD_DP2) + +/* Nothing special */ + +#else +#error "board type not defined" +#endif + +#ifndef ASM + +#include <rtems.h> +#include <bsp/i2cdrv.h> +#include <bsp/irq.h> +#include <bsp/vectors.h> +#include <bsp/u-boot.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc5200_fec_driver_attach_detach + +/* miscellaneous stuff assumed to exist */ + +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +/* +#define NOCACHE_MEM_SIZE 512*1024 +*/ + +/* + * Device Driver Table Entries + */ + +#ifdef HAS_NVRAM_93CXX +#define NVRAM_DRIVER_TABLE_ENTRY \ + { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ + nvram_driver_read, nvram_driver_write, NULL } +#endif + +/* + * indicate, that BSP has IDE driver + */ +#define RTEMS_BSP_HAS_IDE_DRIVER + +/* functions */ + +/* #define SHOW_MORE_INIT_SETTINGS 1 */ + +/* ata modes */ +/* #undef ATA_USE_INT */ +#define ATA_USE_INT + +/* clock settings */ +#if defined(HAS_UBOOT) +#define IPB_CLOCK (bsp_uboot_board_info.bi_ipbfreq) +#define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq) +#define G2_CLOCK (bsp_uboot_board_info.bi_intfreq) +#elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L) +#define IPB_CLOCK 66000000 /* 66 MHz */ +#define XLB_CLOCK 132000000 /* 132 MHz */ +#define G2_CLOCK 396000000 /* 396 MHz */ +#else +#define IPB_CLOCK 33000000 /* 33 MHz */ +#define XLB_CLOCK 66000000 /* 66 MHz */ +#define G2_CLOCK 231000000 /* 231 MHz */ +#endif + +#if defined(HAS_UBOOT) +#define GEN5200_CONSOLE_BAUD (bsp_uboot_board_info.bi_baudrate) +#else +#define GEN5200_CONSOLE_BAUD 115200 +#endif + +/* + * Convert decrement value to tenths of microsecnds (used by + * shared timer driver). + * + * + CPU has a XLB_CLOCK bus, + * + There are 4 bus cycles per click + * + We return value in 1/10 microsecond units. + * Modified following equation to integer equation to remove + * floating point math. + * (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0)) + */ + +#define BSP_Convert_decrementer( _value ) \ + (int) (((_value) * 4000) / (XLB_CLOCK/10000)) + +/* slicetimer settings */ +#define USE_SLICETIMER_0 TRUE +#define USE_SLICETIMER_1 FALSE + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* BSP specific IRQ Benchmarking support */ +void BSP_IRQ_Benchmarking_Reset(void); +void BSP_IRQ_Benchmarking_Report(void); + +#if defined(HAS_UBOOT) + /* Routine to obtain U-Boot environment variables */ + const char *bsp_uboot_getenv( + const char *name + ); +#endif + +void cpu_init(void); + +int mpc5200_eth_mii_read( + int phyAddr, + void *arg, + unsigned regAddr, + uint32_t *retVal +); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* GEN5200 */ diff --git a/bsps/powerpc/gen5200/include/bsp/ata.h b/bsps/powerpc/gen5200/include/bsp/ata.h new file mode 100644 index 0000000000..3d8ccfc49a --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/ata.h @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef GEN5200_ATA_H +#define GEN5200_ATA_H + +#include "bestcomm.h" + +#include <assert.h> + +#include <rtems.h> +#include <rtems/diskdevs.h> +#include <rtems/bdbuf.h> + +#include <libchip/ata_internal.h> +#include <libchip/ide_ctrl_io.h> +#include <libchip/ide_ctrl_cfg.h> + +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define DCTRL_SRST BSP_BBIT8(5) +#define DCTRL_NIEN BSP_BBIT8(6) + +#define DAST_BSY BSP_BBIT8(0) +#define DAST_DRDY BSP_BBIT8(1) +#define DAST_DRQ BSP_BBIT8(4) +#define DAST_ERR BSP_BBIT8(7) + +#define DST_BSY BSP_BBIT16(0) +#define DST_DRDY BSP_BBIT16(1) +#define DST_DRQ BSP_BBIT16(4) +#define DST_ERR BSP_BBIT16(7) + +#define DDMA_HUT BSP_BBIT8(1) +#define DDMA_FR BSP_BBIT8(2) +#define DDMA_FE BSP_BBIT8(3) +#define DDMA_IE BSP_BBIT8(4) +#define DDMA_UDMA BSP_BBIT8(5) +#define DDMA_READ BSP_BBIT8(6) +#define DDMA_WRITE BSP_BBIT8(7) + +#define ATA_SECTOR_SHIFT 9 + +#define ATA_PER_TRANSFER_SECTOR_COUNT_MAX 256 + +typedef union { + struct { + uint8_t alternate_status; + uint8_t reserved_0[3]; + uint16_t data; + uint8_t reserved_1[2]; + uint8_t error; + uint8_t reserved_2[3]; + uint8_t sector_count; + uint8_t reserved_3[3]; + uint8_t sector; + uint8_t reserved_4[3]; + uint8_t cylinder_low; + uint8_t reserved_5[3]; + uint8_t cylinder_high; + uint8_t reserved_6[3]; + uint8_t head; + uint8_t reserved_7[3]; + uint16_t status; + uint8_t reserved_8[2]; + } read; + + struct { + uint8_t control; + uint8_t reserved_0[3]; + uint16_t data; + uint8_t reserved_1[2]; + uint8_t feature; + uint8_t reserved_2[3]; + uint8_t sector_count; + uint8_t reserved_3[3]; + uint8_t sector; + uint8_t reserved_4[3]; + uint8_t cylinder_low; + uint8_t reserved_5[3]; + uint8_t cylinder_high; + uint8_t reserved_6[3]; + uint8_t head; + uint8_t reserved_7[3]; + uint8_t command; + uint8_t dma_control; + uint8_t reserved_8[2]; + } write; +} ata_drive_registers; + +#define ATA ((volatile ata_drive_registers *) 0xf0003a5c) + +static inline bool ata_is_data_request(void) +{ + return (ATA->read.alternate_status & DAST_DRQ) != 0; +} + +static inline bool ata_is_drive_ready_for_selection(void) +{ + return (ATA->read.alternate_status & (DAST_BSY | DAST_DRQ)) == 0; +} + +static inline void ata_wait_400_nano_seconds(void) +{ + ATA->read.alternate_status; +} + +static inline void ata_wait_for_drive_ready(void) +{ + while ((ATA->read.alternate_status & (DAST_BSY | DAST_DRQ | DAST_DRDY)) != DAST_DRDY) { + /* Wait */ + } +} + +static inline void ata_wait_for_not_busy(void) +{ + ata_wait_400_nano_seconds(); + + while ((ATA->read.alternate_status & DAST_BSY) != 0) { + /* Wait */ + } +} + +static inline bool ata_wait_for_data_request(void) +{ + ata_wait_400_nano_seconds(); + + uint8_t alternate_status; + do { + alternate_status = ATA->read.alternate_status; + } while ((alternate_status & DAST_BSY) == DAST_BSY); + + return (alternate_status & (DAST_ERR | DAST_DRQ)) == DAST_DRQ; +} + +static inline bool ata_check_status(void) +{ + return (ATA->read.status & (DST_BSY | DST_ERR)) == 0; +} + +static inline void ata_clear_interrupts(void) +{ + ATA->read.status; +} + +static inline uint8_t ata_read_or_write_sectors_command(bool read) +{ + return read ? 0x20 : 0x30; +} + +static inline rtems_blkdev_bnum ata_max_transfer_count(rtems_blkdev_bnum sector_count) +{ + return sector_count > ATA_PER_TRANSFER_SECTOR_COUNT_MAX ? + ATA_PER_TRANSFER_SECTOR_COUNT_MAX + : sector_count; +} + +static inline void ata_flush_sector(uint16_t *begin) +{ + /* XXX: The dcbi operation does not work properly */ + rtems_cache_flush_multiple_data_lines(begin, ATA_SECTOR_SIZE); +} + +void ata_reset_device(void); + +bool ata_set_transfer_mode(uint8_t mode); + +bool ata_execute_io_command(uint8_t command, uint32_t lba, uint32_t sector_count); + +static inline bool ata_execute_io_command_with_sg(uint8_t command, const rtems_blkdev_sg_buffer *sg) +{ + uint32_t lba = sg->block; + uint32_t sector_count = sg->length / ATA_SECTOR_SIZE; + return ata_execute_io_command(command, lba, sector_count); +} + +typedef struct { + const rtems_blkdev_sg_buffer *sg; + + size_t sg_count; + + rtems_blkdev_bnum sg_buffer_offset_mask; + + int sg_index_shift; +} ata_sg_context; + +static inline void ata_sg_reset(ata_sg_context *self, const rtems_blkdev_sg_buffer *sg, size_t sg_count) +{ + self->sg = sg; + self->sg_count = sg_count; + uint32_t sectors_per_buffer = self->sg[0].length >> ATA_SECTOR_SHIFT; + self->sg_buffer_offset_mask = sectors_per_buffer - 1; + self->sg_index_shift = __builtin_ffs((int) sectors_per_buffer) - 1; +} + +static inline void ata_sg_create_default(ata_sg_context *self) +{ + ata_sg_reset(self, NULL, 0); +} + +static inline void ata_sg_create(ata_sg_context *self, const rtems_blkdev_sg_buffer *sg, size_t sg_count) +{ + ata_sg_reset(self, sg, sg_count); +} + +static inline rtems_blkdev_bnum ata_sg_get_start_sector(const ata_sg_context *self) +{ + return self->sg[0].block; +} + +static inline rtems_blkdev_bnum ata_sg_get_sector_count(const ata_sg_context *self) +{ + return (self->sg_buffer_offset_mask + 1) * self->sg_count; +} + +static inline uint16_t *ata_sg_get_sector_data_begin(const ata_sg_context *self, rtems_blkdev_bnum relative_sector) +{ + uint16_t *begin = (uint16_t *)(self->sg[relative_sector >> self->sg_index_shift].buffer); + + return begin + ((relative_sector & self->sg_buffer_offset_mask) << (ATA_SECTOR_SHIFT - 1)); +} + +static inline uint16_t *ata_sg_get_sector_data_end(const ata_sg_context *self, uint16_t *begin) +{ + return begin + ATA_SECTOR_SIZE / 2; +} + +typedef struct { + rtems_id lock; + + bool card_present; +} ata_driver; + +void ata_driver_create(ata_driver *self, const char *device_file_path, rtems_block_device_ioctl io_control); + +void ata_driver_destroy(ata_driver *self); + +static inline void ata_driver_lock(const ata_driver *self) +{ + rtems_status_code sc = rtems_semaphore_obtain(self->lock, RTEMS_WAIT, RTEMS_NO_TIMEOUT); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void ata_driver_unlock(const ata_driver *self) +{ + rtems_status_code sc = rtems_semaphore_release(self->lock); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline bool ata_driver_is_card_present(const ata_driver *self) +{ + return self->card_present; +} + +static inline void ata_driver_io_request( + ata_driver *self, + rtems_blkdev_request *request, + bool (*transfer)(ata_driver *, bool, rtems_blkdev_sg_buffer *, size_t) +) +{ + assert(request->req == RTEMS_BLKDEV_REQ_READ || request->req == RTEMS_BLKDEV_REQ_WRITE); + bool read = request->req != RTEMS_BLKDEV_REQ_WRITE; + rtems_blkdev_sg_buffer *sg = &request->bufs[0]; + uint32_t sg_count = request->bufnum; + ata_driver_lock(self); + bool ok = (*transfer)(self, read, sg, sg_count); + ata_driver_unlock(self); + rtems_status_code sc = ok ? RTEMS_SUCCESSFUL : RTEMS_IO_ERROR; + rtems_blkdev_request_done(request, sc); +} + +static inline int ata_driver_io_control( + rtems_disk_device *dd, + uint32_t cmd, + void *arg, + bool (*transfer)(ata_driver *, bool, rtems_blkdev_sg_buffer *, size_t) +) +{ + ata_driver *self = (ata_driver *) rtems_disk_get_driver_data(dd); + + switch (cmd) { + case RTEMS_BLKIO_REQUEST: + ata_driver_io_request(self, (rtems_blkdev_request *) arg, transfer); + return 0; + case RTEMS_BLKIO_CAPABILITIES: + *(uint32_t *) arg = RTEMS_BLKDEV_CAP_MULTISECTOR_CONT; + return 0; + default: + return rtems_blkdev_ioctl(dd, cmd, arg); + } +} + +int ata_driver_io_control_pio_polled( + rtems_disk_device *dd, + uint32_t cmd, + void *arg +); + +typedef struct { + ata_driver super; + + bestcomm_task task; + + bool read; + + ata_sg_context sg_context; + + rtems_blkdev_bnum transfer_current; + + rtems_blkdev_bnum transfer_end; +} ata_driver_dma_pio_single; + +void ata_driver_dma_pio_single_create( + ata_driver_dma_pio_single *self, + const char *device_file_path, + TaskId task_index +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* GEN5200_ATA_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm.h b/bsps/powerpc/gen5200/include/bsp/bestcomm.h new file mode 100644 index 0000000000..366465565a --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef GEN5200_BESTCOMM_H +#define GEN5200_BESTCOMM_H + +#include "bestcomm_ops.h" + +#include <assert.h> + +#include <rtems.h> + +#include <bsp/mpc5200.h> +#include <bsp/bestcomm/bestcomm_api.h> +#include <bsp/bestcomm/bestcomm_glue.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup BestComm BestComm Support + * + * @ingroup BestCommm + * + * @brief BestComm support. + * + * @{ + */ + +typedef struct { + uint32_t *tdt_begin; + uint32_t *tdt_last; + volatile uint32_t (*var_table)[32]; + uint32_t fdt_and_pragmas; + uint32_t reserved_0; + uint32_t reserved_1; + uint32_t *context_begin; + uint32_t reserved_2; +} bestcomm_task_entry; + +#define BESTCOMM_TASK_ENTRY_TABLE ((volatile bestcomm_task_entry *) 0xf0008000) + +#define BESTCOMM_IRQ_EVENT RTEMS_EVENT_13 + +typedef struct { + int task_index; + rtems_id event_task_id; +} bestcomm_irq; + +void bestcomm_irq_create(bestcomm_irq *self, int task_index); + +void bestcomm_irq_destroy(const bestcomm_irq *self); + +static inline void bestcomm_irq_enable(const bestcomm_irq *self) +{ + bestcomm_glue_irq_enable(self->task_index); +} + +static inline void bestcomm_irq_disable(const bestcomm_irq *self) +{ + bestcomm_glue_irq_disable(self->task_index); +} + +static inline void bestcomm_irq_clear(const bestcomm_irq *self) +{ + SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend, self->task_index); +} + +static inline int bestcomm_irq_get_task_index(const bestcomm_irq *self) +{ + return self->task_index; +} + +static inline rtems_id bestcomm_irq_get_event_task_id(const bestcomm_irq *self) +{ + return self->event_task_id; +} + +static inline void bestcomm_irq_set_event_task_id(bestcomm_irq *self, rtems_id id) +{ + self->event_task_id = id; +} + +static inline void bestcomm_irq_wakeup_event_task(const bestcomm_irq *self) +{ + rtems_status_code sc = rtems_event_send(self->event_task_id, BESTCOMM_IRQ_EVENT); + assert(sc == RTEMS_SUCCESSFUL); +} + +static inline void bestcomm_irq_wait(const bestcomm_irq *self) +{ + rtems_event_set events; + rtems_status_code sc = rtems_event_receive( + BESTCOMM_IRQ_EVENT, + RTEMS_EVENT_ALL | RTEMS_WAIT, + RTEMS_NO_TIMEOUT, + &events + ); + assert(sc == RTEMS_SUCCESSFUL); + assert(events == BESTCOMM_IRQ_EVENT); +} + +static inline bool bestcomm_irq_peek(const bestcomm_irq *self) +{ + rtems_event_set events; + rtems_status_code sc = rtems_event_receive(0, 0, 0, &events); + assert(sc == RTEMS_SUCCESSFUL); + + return (events & BESTCOMM_IRQ_EVENT) != 0; +} + +typedef struct { + volatile uint16_t *task_control_register; + + volatile uint32_t (*variable_table)[32]; + + TaskId task_index; + + bestcomm_irq irq; + + uint32_t *tdt_begin; + + size_t tdt_opcode_count; +} bestcomm_task; + +void bestcomm_task_create(bestcomm_task *self, TaskId task_index); + +void bestcomm_task_create_and_load( + bestcomm_task *self, + TaskId task_index, + const uint32_t *tdt_source_begin, + size_t tdt_size +); + +void bestcomm_task_destroy(bestcomm_task *self); + +void bestcomm_task_load(bestcomm_task *self, const uint32_t *tdt_source_begin, size_t tdt_size); + +static inline void bestcomm_task_set_priority(bestcomm_task *self, int priority) +{ + /* Allow higher priority initiator to block current initiator */ + mpc5200.sdma.ipr[self->task_index] = SDMA_IPR_PRIOR(priority); +} + +static inline void bestcomm_task_irq_enable(const bestcomm_task *self) +{ + bestcomm_irq_enable(&self->irq); +} + +static inline void bestcomm_task_irq_disable(const bestcomm_task *self) +{ + bestcomm_irq_disable(&self->irq); +} + +static inline void bestcomm_task_irq_clear(const bestcomm_task *self) +{ + bestcomm_irq_clear(&self->irq); +} + +static inline rtems_id bestcomm_task_get_event_task_id(const bestcomm_task *self) +{ + return bestcomm_irq_get_event_task_id(&self->irq); +} + +static inline void bestcomm_task_set_event_task_id(bestcomm_task *self, rtems_id id) +{ + bestcomm_irq_set_event_task_id(&self->irq, id); +} + +static inline void bestcomm_task_associate_with_current_task(bestcomm_task *self) +{ + bestcomm_task_set_event_task_id(self, rtems_task_self()); +} + +static inline void bestcomm_task_start(const bestcomm_task *self) +{ + *self->task_control_register = SDMA_TCR_EN | SDMA_TCR_HIGH_EN; +} + +static inline void bestcomm_task_start_with_autostart(const bestcomm_task *self) +{ + *self->task_control_register = (uint16_t) + (SDMA_TCR_EN | SDMA_TCR_HIGH_EN | SDMA_TCR_AUTO_START | SDMA_TCR_AS(self->task_index)); +} + +static inline void bestcomm_task_stop(const bestcomm_task *self) +{ + *self->task_control_register = 0; +} + +static inline void bestcomm_task_wakeup_event_task(const bestcomm_task *self) +{ + bestcomm_irq_wakeup_event_task(&self->irq); +} + +static inline void bestcomm_task_wait(const bestcomm_task *self) +{ + bestcomm_irq_wait(&self->irq); +} + +static inline bool bestcomm_task_peek(const bestcomm_task *self) +{ + return bestcomm_irq_peek(&self->irq); +} + +static inline bool bestcomm_task_is_running(const bestcomm_task *self) +{ + return (*self->task_control_register & SDMA_TCR_EN) != 0; +} + +static inline uint32_t bestcomm_get_task_variable(const bestcomm_task *self, size_t index) +{ + assert(index < VAR_COUNT); + return (*self->variable_table)[index]; +} + +static inline volatile uint32_t *bestcomm_task_get_address_of_variable(const bestcomm_task *self, size_t index) +{ + assert(index < VAR_COUNT); + return &(*self->variable_table)[index]; +} + +static inline void bestcomm_task_set_variable(const bestcomm_task *self, size_t index, uint32_t value) +{ + assert(index < VAR_COUNT); + (*self->variable_table)[index] = value; +} + +static inline uint32_t bestcomm_task_get_increment_and_condition(const bestcomm_task *self, size_t index) +{ + assert(index < INC_COUNT); + return (*self->variable_table)[INC(index)]; +} + +static inline void bestcomm_task_set_increment_and_condition_32( + const bestcomm_task *self, + size_t index, + uint32_t inc_and_cond +) +{ + assert(index < INC_COUNT); + (*self->variable_table)[INC(index)] = inc_and_cond; +} + +static inline void bestcomm_task_set_increment_and_condition( + const bestcomm_task *self, + size_t index, + int16_t inc, + int cond +) +{ + bestcomm_task_set_increment_and_condition_32(self, index, INC_INIT(cond, inc)); +} + +static inline void bestcomm_task_set_increment(const bestcomm_task *self, size_t index, int16_t inc) +{ + bestcomm_task_set_increment_and_condition_32(self, index, INC_INIT(0, inc)); +} + +void bestcomm_task_clear_variables(const bestcomm_task *self); + +static inline uint32_t bestcomm_task_get_opcode(const bestcomm_task *self, size_t index) +{ + assert(index < self->tdt_opcode_count); + return self->tdt_begin[index]; +} + +static inline void bestcomm_task_set_opcode(bestcomm_task *self, size_t index, uint32_t opcode) +{ + assert(index < self->tdt_opcode_count); + self->tdt_begin[index] = opcode; +} + +static inline void bestcomm_task_set_initiator(const bestcomm_task *self, int initiator) +{ + rtems_interrupt_level level; + rtems_interrupt_disable(level); + *self->task_control_register = BSP_BFLD16SET(*self->task_control_register, initiator, 3, 7); + rtems_interrupt_enable(level); +} + +static inline volatile bestcomm_task_entry *bestcomm_task_get_task_entry(const bestcomm_task *self) +{ + return &BESTCOMM_TASK_ENTRY_TABLE[self->task_index]; +} + +static inline void bestcomm_task_set_pragma(const bestcomm_task *self, int bit_pos, bool enable) +{ + volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self); + uint32_t mask = BSP_BIT32(bit_pos); + uint32_t bit = enable ? mask : 0; + entry->fdt_and_pragmas = (entry->fdt_and_pragmas & ~mask) | bit; +} + +static inline void bestcomm_task_enable_precise_increment(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_PRECISE_INC, enable); +} + +static inline void bestcomm_task_enable_error_reset(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_RST_ERROR_NO, !enable); +} + +static inline void bestcomm_task_enable_pack_data(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_PACK, enable); +} + +static inline void bestcomm_task_enable_integer_mode(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_INTEGER, enable); +} + +static inline void bestcomm_task_enable_speculative_read(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_SPECREAD, enable); +} + +static inline void bestcomm_task_enable_combined_write(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_CW, enable); +} + +static inline void bestcomm_task_enable_read_buffer(const bestcomm_task *self, bool enable) +{ + bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_RL, enable); +} + +static inline volatile uint16_t *bestcomm_task_get_task_control_register(const bestcomm_task *self) +{ + return self->task_control_register; +} + +static inline int bestcomm_task_get_task_index(const bestcomm_task *self) +{ + return self->task_index; +} + +static inline void bestcomm_task_free_tdt(bestcomm_task *self) +{ + bestcomm_free(self->tdt_begin); + self->tdt_begin = NULL; +} + +static inline void bestcomm_task_clear_pragmas(const bestcomm_task *self) +{ + volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self); + entry->fdt_and_pragmas &= ~0xffU; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* GEN5200_BESTCOMM_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h new file mode 100644 index 0000000000..f1fa22d1d5 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h @@ -0,0 +1,460 @@ +#ifndef __BESTCOMM_API_H +#define __BESTCOMM_API_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/*! + * \file bestcomm_api.h + * + * Bestcomm_api.h is the only header necessary for inclusion by user + * code. The include path the C compiler searches to find .h files + * should contain bestcomm/capi and one of bestcomm/code_dma/image_*. + * This second entry selects which set of BestComm tasks will be used. + * Of course the appropriate files in image_* must also be compiled and + * linked. + */ + +#include <rtems.h> + +#include "include/ppctypes.h" +#include "include/mgt5200/sdma.h" +#include "task_api/tasksetup_bdtable.h" +#include "task_api/bestcomm_cntrl.h" +#include "task_api/bestcomm_api_mem.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \brief TaskSetup() debugging + * + * Define this macro as follows for debugging printf()s to see + * what the API receives and sets from the TaskSetupParamSet_t + * struct. Implemented in capi/task_api/tasksetup_general.h. + * + * \verbatim + * >0 : print basic debug messages + * >=10: also print C-API interface variables + * >=20: also print task API interface variables + * else: do nothing + * \endverbatim + */ +#define DEBUG_BESTCOMM_API 0 + +/*! + * \brief Maximum number of tasks in the system. + * This number is hardware-dependent and not user configuration. + */ +#define MAX_TASKS 16 + +/* + * This may need to be removed in certain implementations. + */ +#ifndef NULL +# define NULL ((void *)0) +#endif /* NULL */ + +typedef sint8 TaskId; +typedef sint32 BDIdx; + +/* + * Special "task IDs" for interrupt handling API functions + */ +/*! \brief Debug interrupt "task ID" */ +#define DEBUG_INTR_ID SDMA_INT_BIT_DBG + +/*! \brief TEA interrupt "task ID" */ +#define TEA_INTR_ID SDMA_INT_BIT_TEA + +/*! \brief Task start autostart enable */ +#define TASK_AUTOSTART_ENABLE 1 + +/*! \brief Task start autostart disable */ +#define TASK_AUTOSTART_DISABLE 0 + +/*! \brief Task start interrupt enable */ +#define TASK_INTERRUPT_ENABLE 1 + +/*! \brief Task start interrupt disable */ +#define TASK_INTERRUPT_DISABLE 0 + +/* + * Buffer descriptor flags to pass to TaskBDAssign(). + */ +/*! \brief Transmit frame done */ +#define TASK_BD_TFD (1 << SDMA_DRD_BIT_TFD) + +/*! \brief Interrupt on frame done */ +#define TASK_BD_INT (1 << SDMA_DRD_BIT_INT) + +/*! + * \brief Data transfer size + */ +typedef enum { + SZ_FLEX = 3, /*!< invalid for TaskSetupParamSet_t */ + SZ_UINT8 = 1, /*!< 1-byte */ + SZ_UINT16 = 2, /*!< 2-byte */ + SZ_UINT32 = 4 /*!< 4-byte */ +} Sz_t; + +/*! + * \brief API error codes + */ +typedef enum { + TASK_ERR_NO_ERR = -1, /*!< No error */ + TASK_ERR_NO_INTR = TASK_ERR_NO_ERR, + /*!< No interrupt */ + TASK_ERR_INVALID_ARG = -2, /*!< Invalid function argument */ + TASK_ERR_BD_RING_FULL = -3, /*!< Buffer descriptor ring full*/ + TASK_ERR_API_ALREADY_INITIALIZED + = -4, /*!< API has already been initialized */ + TASK_ERR_SIZE_TOO_LARGE = -5, /*!< Buffer descriptor cannot support size parameter */ + TASK_ERR_BD_RING_EMPTY = -6, /*!< Buffer descriptor ring is empty*/ + TASK_ERR_BD_BUSY = -7, /*!< The buffer descriptor is in use + by the BestComm */ + TASK_ERR_TASK_RUNNING = -8 /*!< The task is running. */ + +} TaskErr_t; + +/*! + * \brief BestComm initiators + * + * These are assigned by TaskSetup(). + */ +typedef enum { + + INITIATOR_ALWAYS = 0, + INITIATOR_SCTMR_0 = 1, + INITIATOR_SCTMR_1 = 2, + INITIATOR_FEC_RX = 3, + INITIATOR_FEC_TX = 4, + INITIATOR_ATA_RX = 5, + INITIATOR_ATA_TX = 6, + INITIATOR_SCPCI_RX = 7, + INITIATOR_SCPCI_TX = 8, + INITIATOR_PSC3_RX = 9, + INITIATOR_PSC3_TX = 10, + INITIATOR_PSC2_RX = 11, + INITIATOR_PSC2_TX = 12, + INITIATOR_PSC1_RX = 13, + INITIATOR_PSC1_TX = 14, + INITIATOR_SCTMR_2 = 15, + + INITIATOR_SCLPC = 16, + INITIATOR_PSC5_RX = 17, + INITIATOR_PSC5_TX = 18, + INITIATOR_PSC4_RX = 19, + INITIATOR_PSC4_TX = 20, + INITIATOR_I2C2_RX = 21, + INITIATOR_I2C2_TX = 22, + INITIATOR_I2C1_RX = 23, + INITIATOR_I2C1_TX = 24, + INITIATOR_PSC6_RX = 25, + INITIATOR_PSC6_TX = 26, + INITIATOR_IRDA_RX = 25, + INITIATOR_IRDA_TX = 26, + INITIATOR_SCTMR_3 = 27, + INITIATOR_SCTMR_4 = 28, + INITIATOR_SCTMR_5 = 29, + INITIATOR_SCTMR_6 = 30, + INITIATOR_SCTMR_7 = 31 + +} MPC5200Initiator_t; + +/*! + * \brief Parameters for TaskSetup() + * + * All parameters can be hard-coded by the task API. Hard-coded values + * will be changed in the struct passed to TaskSetup() for the user to + * examine later. + */ +typedef struct { + uint32 NumBD; /*!< Number of buffer descriptors */ + + union { + uint32 MaxBuf; /*!< Maximum buffer size */ + uint32 NumBytes; /*!< Number of bytes to transfer */ + } Size; /*!< Buffer size union for BD and non-BD tasks */ + + MPC5200Initiator_t + Initiator; /*!< BestComm initiator (ignored if hard-wired) */ + uint32 StartAddrSrc; /*!< Address of the DMA source (e.g. a FIFO) */ + sint16 IncrSrc; /*!< Amount to increment source pointer */ + Sz_t SzSrc; /*!< Size of source data access */ + uint32 StartAddrDst; /*!< Address of the DMA destination (e.g. a FIFO) */ + sint16 IncrDst; /*!< Amount to increment data pointer */ + Sz_t SzDst; /*!< Size of destination data access */ +} TaskSetupParamSet_t; + +/*! + * \brief Parameters for TaskDebug() + * + * TaskDebug() and the contents of this data structure are yet to be + * determined. + */ +typedef struct { + int dummy; /* Some compilers don't like empty struct typedefs */ +} TaskDebugParamSet_t; + +/*! + * \brief Generic buffer descriptor. + * + * It is generally used as a pointer which should be cast to one of the + * other BD types based on the number of buffers per descriptor. + */ +typedef struct { + uint32 Status; /*!< Status and length bits */ +} TaskBD_t; + +/*! + * \brief Single buffer descriptor. + */ +typedef struct { + uint32 Status; /*!< Status and length bits */ + uint32 DataPtr[1]; /*!< Pointer to data buffer */ +} TaskBD1_t; + +/*! + * \brief Dual buffer descriptor. + */ +typedef struct { + uint32 Status; /*!< Status and length bits */ + uint32 DataPtr[2]; /*!< Pointer to data buffers */ +} TaskBD2_t; + + + +/*************************** + * Start of API Prototypes + ***************************/ + +#include "bestcomm_priv.h" +#include "dma_image.capi.h" + +/*! + * \brief Initialize a single task. + * \param TaskName Type of task to initialize. E.g. PCI transmit, + * ethernet receive, general purpose dual-pointer. + * Values expected can be found in the TaskName_t + * enum defined in dma_image.capi.h. + * \param TaskSetupParams Task-specific parameters. The user must fill out + * the pertinent parts of a TaskSetupParamSet_t + * data structure. + * \returns TaskId task identification token which is a required + * parameter for most other API functions. + * + * This function returns a task identification token which is a required + * parameter for most other API functions. + * + * Certain values of the structure pointed to by TaskParams are set + * as a side-effect based on task type. These may be examined after + * a successful call to TaskSetup(). User-specified values may be + * overridden. + * + * TaskId TaskSetup( TaskName_t TaskName, + * TaskSetupParamSet_t *TaskSetupParams ); + */ +#define TaskSetupHelper(TaskName, TaskSetupParams) \ + TaskSetup_ ## TaskName (TaskName ## _api, TaskSetupParams) +#define TaskSetup(TaskName, TaskSetupParams) \ + TaskSetupHelper(TaskName, TaskSetupParams) + +const char *TaskVersion(void); + +int TasksInitAPI(uint8 *MBarRef); + +int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys); + +void TasksLoadImage(sdma_regs *sdma); +int TasksAttachImage(sdma_regs *sdma); + +int TaskStart(TaskId taskId, uint32 autoStartEnable, + TaskId autoStartTask, uint32 intrEnable); +int TaskStop(TaskId taskId); +static int TaskStatus(TaskId taskId); +BDIdx TaskBDAssign(TaskId taskId, void *buffer0, void *buffer1, + int size, uint32 bdFlags); +BDIdx TaskBDRelease(TaskId taskId); +BDIdx TaskBDReset(TaskId taskId); +static TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd); +static TaskBD_t *TaskGetBDRing(TaskId taskId); +int TaskDebug(TaskId taskId, TaskDebugParamSet_t *paramSet); +static int TaskIntClear(TaskId taskId); +static TaskId TaskIntStatus(TaskId taskId); +static int TaskIntPending(TaskId taskId); +static TaskId TaskIntSource(void); +static uint16 TaskBDInUse(TaskId taskId); + + +/*! + * \brief Get the enable/disable status of a task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns Boolean true indicates enabled or false indicates disabled + * or invalid taskId. + */ +static inline int TaskStatus(TaskId taskId) +{ + return SDMA_TASK_STATUS(SDMA_TCR, taskId) & 0x8000; +} + +/*! + * \brief Return a pointer to a buffer descriptor at index BDIdx + * \param taskId Task handle passed back from a successful TaskSetup() + * \param bd Buffer descriptor handle returned by + * TaskBDAssign() or TaskBDRelease(). + * \returns Pointer to the requested buffer descriptor or NULL on error. + * + * The returned pointer should be cast to the appropriate buffer + * descriptor type, TaskBD1_t or TaskBD2_t. + */ +static inline TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd) +{ + void *bdTab; + + bdTab = TaskBDIdxTable[taskId].BDTablePtr; + if (TaskBDIdxTable[taskId].numPtr == 1) { + return (TaskBD_t *)&(((TaskBD1_t *)bdTab)[bd]); + } else { + return (TaskBD_t *)&(((TaskBD2_t *)bdTab)[bd]); + } +} + +/*! + * \brief Return a pointer to the first buffer descriptor in the ring. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns Pointer to the array of buffer descriptors making up the + * ring or NULL on error. + * + * A device driver author may choose to use this in lieu of + * TaskBDAssign()/TaskBDRelease() to get direct access to the + * BD ring with the warning that the underlying data structure may change. + * Use at one's own discretion. + */ +static inline TaskBD_t *TaskGetBDRing(TaskId taskId) +{ + return (TaskBD_t *) TaskBDIdxTable[taskId].BDTablePtr; +} + +/*! + * \brief Clear the interrupt for a given BestComm task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns TASK_ERR_NO_ERR (which is not really an error) for success + */ +static inline int TaskIntClear(TaskId taskId) +{ + SDMA_CLEAR_IEVENT(SDMA_INT_PEND, taskId); + return TASK_ERR_NO_ERR; /* success */ +} + +/*! + * \brief Get the interrupt status for a given task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns TASK_ERR_NO_INTR (which is not really an error) for no interrupt + * pending, taskId for a regular interrupt, DEBUG_INTR_ID for + * a debug interrupt and TEA_INTR_ID for a TEA interrupt. + * \b Note: TaskIntStatus() may return 0, but this means that that + * taskId 0 is interrupt pending. + */ +static inline TaskId TaskIntStatus(TaskId taskId) +{ + uint32 pending; + + pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK); + + if (SDMA_INT_TEST(pending, taskId)) { + return taskId; + } else if (SDMA_INT_TEST(pending, DEBUG_INTR_ID)) { + return DEBUG_INTR_ID; + } else if (SDMA_INT_TEST(pending, TEA_INTR_ID)) { + return TEA_INTR_ID; + } + + return TASK_ERR_NO_INTR; +} + +/*! + * \brief Get the interrupt pending status for a given task. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns 0 if task does not have a pending interrupt. 1 if the task + * has an interrupt pending. + */ +static inline int TaskIntPending(TaskId taskId) +{ + uint32 pending; + + pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK); + if (SDMA_INT_TEST(pending, taskId)) { + return 1; + } else { + return 0; + } +} + +/*! + * \brief Returns the task ID of an interrupting BestComm task. + * \returns TASK_ERR_NO_INTR (which is not really an error) for no interrupt + * pending or the taskId of the interrupting task. + * + * The user must query TaskIntStatus() to discover if this is a debug + * or TEA interrupt. This function is designed for use by an operating + * system interrupt handler. + */ +static inline TaskId TaskIntSource(void) +{ + uint32 pending; + uint32 mask = 1 << (MAX_TASKS - 1); + TaskId i; + + pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK); + + if (SDMA_INT_TEST(pending, SDMA_INT_BIT_TEA)) { + return (TaskId)SDMA_TEA_SOURCE(SDMA_INT_PEND); + } + + for (i = (MAX_TASKS - 1); i >= 0; --i, mask >>= 1) { + if (pending & mask) { + return i; + } + } + + return TASK_ERR_NO_INTR; +} + +/*! + * \brief Get a count of in-use buffer descriptors. + * \param taskId Task handle passed back from a successful TaskSetup() + * \returns Count of the current number of BDs in use by the given task. + */ +static inline uint16 TaskBDInUse(TaskId taskId) +{ + return TaskBDIdxTable[taskId].currBDInUse; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __BESTCOMM_API_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h new file mode 100644 index 0000000000..18827b77c7 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h @@ -0,0 +1,114 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2004-2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares glue functions to the Freescale BestComm API | +\*===============================================================*/ +#ifndef _BESTCOMM_GLUE_H +#define _BESTCOMM_GLUE_H + +#include <rtems/irq-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_irq_enable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| enable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int bestcomm_taskno /* task number to enable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_irq_disable +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| disable interrupt for given task number | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int bestcomm_taskno /* task number to disable */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_irq_install +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| install given function as bestcomm interrupt handler | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + int bestcomm_taskno, /* task number for handler */ + rtems_interrupt_handler handler, /* function to call */ + void *arg + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +void bestcomm_glue_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the bestcomm module (if not yet done): | +| - load code | +| - initialize registers | +| - initialize bus arbiter | +| - initialize interrupt control | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + void /* none */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| none | +\*=========================================================================*/ + +void *bestcomm_malloc(size_t size); + +void bestcomm_free(void *ptr); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _BESTCOMM_GLUE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h new file mode 100644 index 0000000000..102fc082cb --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h @@ -0,0 +1,38 @@ +#ifndef __BESTCOMM_PRIV_H +#define __BESTCOMM_PRIV_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/* + * Global variables necessitated by the TaskSetup_*() location in + * separate files from the main code and the inline functions. These are + * private data structures that should not be manipulated by API users. + */ + +extern TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS]; +extern int TaskRunning[MAX_TASKS]; +extern sint64 MBarPhysOffsetGlobal; + +#endif /* __BESTCOMM_PRIV_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h new file mode 100644 index 0000000000..6b07cbcb2a --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h @@ -0,0 +1,84 @@ +#ifndef __DMA_IMAGE_CAPI_H +#define __DMA_IMAGE_CAPI_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + + +#include "dma_image.h" + +typedef enum { + TASK_PCI_TX, + TASK_PCI_RX, + TASK_FEC_TX, + TASK_FEC_RX, + TASK_LPC, + TASK_ATA, + TASK_CRC16_DP_0, + TASK_CRC16_DP_1, + TASK_GEN_DP_0, + TASK_GEN_DP_1, + TASK_GEN_DP_2, + TASK_GEN_DP_3, + TASK_GEN_TX_BD, + TASK_GEN_RX_BD, + TASK_GEN_DP_BD_0, + TASK_GEN_DP_BD_1 +} TaskName_t; + +TaskId TaskSetup_TASK_PCI_TX (TASK_PCI_TX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_PCI_RX (TASK_PCI_RX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_FEC_TX (TASK_FEC_TX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_FEC_RX (TASK_FEC_RX_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_LPC (TASK_LPC_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_ATA (TASK_ATA_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_CRC16_DP_0(TASK_CRC16_DP_0_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_CRC16_DP_1(TASK_CRC16_DP_1_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_0 (TASK_GEN_DP_0_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_1 (TASK_GEN_DP_1_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_2 (TASK_GEN_DP_2_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_3 (TASK_GEN_DP_3_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_TX_BD (TASK_GEN_TX_BD_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_RX_BD (TASK_GEN_RX_BD_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_BD_0(TASK_GEN_DP_BD_0_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); +TaskId TaskSetup_TASK_GEN_DP_BD_1(TASK_GEN_DP_BD_1_api_t *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams); + +#endif /* __DMA_IMAGE_CAPI_H */ + diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h new file mode 100644 index 0000000000..1f8b86cded --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h @@ -0,0 +1,472 @@ +#ifndef __DMA_IMAGE_H +#define __DMA_IMAGE_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + + +#include "include/ppctypes.h" + +void init_dma_image_TASK_PCI_TX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_PCI_RX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_FEC_TX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_FEC_RX(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_LPC(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_ATA(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_CRC16_DP_0(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_CRC16_DP_1(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_0(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_1(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_2(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_3(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_TX_BD(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_RX_BD(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_BD_0(uint8 *vMem_taskBar, sint64 vMemOffset); +void init_dma_image_TASK_GEN_DP_BD_1(uint8 *vMem_taskBar, sint64 vMemOffset); + +/* MBAR_TASK_TABLE is the first address of task table */ +#ifndef MBAR_TASK_TABLE +#define MBAR_TASK_TABLE 0xf0008000UL +#endif + +/* MBAR_DMA_FREE is the first free address after task table */ +#define MBAR_DMA_FREE MBAR_TASK_TABLE + 0x00001500UL + +/* TASK_BAR is the first address of the Entry table */ +#define TASK_BAR MBAR_TASK_TABLE + 0x00000000UL +#define TASK_BAR_OFFSET 0x00000000UL + +typedef struct task_info0 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrDstFIFO; + volatile sint16 *IncrBytes; + volatile uint32 *AddrPktSizeReg; + volatile sint16 *IncrSrc; + volatile uint32 *AddrSCStatusReg; + volatile uint32 *Bytes; + volatile uint32 *IterExtra; + volatile uint32 *StartAddrSrc; +} TASK_PCI_TX_api_t; +extern TASK_PCI_TX_api_t *TASK_PCI_TX_api; + +typedef struct task_info1 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[5]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrPktSizeReg; + volatile sint16 *IncrBytes; + volatile uint32 *AddrSrcFIFO; + volatile sint16 *IncrDst; + volatile uint32 *Bytes; + volatile uint32 *IterExtra; + volatile uint32 *StartAddrDst; +} TASK_PCI_RX_api_t; +extern TASK_PCI_RX_api_t *TASK_PCI_RX_api; + +typedef struct task_info2 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[22]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrDRD; + volatile uint32 AddrDRDIdx; + volatile sint16 *IncrBytes; + volatile uint32 *AddrDstFIFO; + volatile sint16 *IncrSrc; + volatile uint32 *AddrEnable; + volatile sint16 *IncrSrcMA; + volatile uint32 *BDTableBase; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_FEC_TX_api_t; +extern TASK_FEC_TX_api_t *TASK_FEC_TX_api; + +typedef struct task_info3 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[13]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *AddrSrcFIFO; + volatile sint16 *IncrDst; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDstMA; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_FEC_RX_api_t; +extern TASK_FEC_RX_api_t *TASK_FEC_RX_api; + +typedef struct task_info4 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_LPC_api_t; +extern TASK_LPC_api_t *TASK_LPC_api; + +typedef struct task_info5 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDst; + volatile uint32 *BDTableLast; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_ATA_api_t; +extern TASK_ATA_api_t *TASK_ATA_api; + +typedef struct task_info6 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[9]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_CRC16_DP_0_api_t; +extern TASK_CRC16_DP_0_api_t *TASK_CRC16_DP_0_api; + +typedef struct task_info7 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[9]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_CRC16_DP_1_api_t; +extern TASK_CRC16_DP_1_api_t *TASK_CRC16_DP_1_api; + +typedef struct task_info8 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_0_api_t; +extern TASK_GEN_DP_0_api_t *TASK_GEN_DP_0_api; + +typedef struct task_info9 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_1_api_t; +extern TASK_GEN_DP_1_api_t *TASK_GEN_DP_1_api; + +typedef struct task_info10 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_2_api_t; +extern TASK_GEN_DP_2_api_t *TASK_GEN_DP_2_api; + +typedef struct task_info11 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[4]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *Bytes; + volatile sint16 *IncrBytes; + volatile uint32 *IterExtra; + volatile sint16 *IncrDst; + volatile sint16 *IncrDstMA; + volatile sint16 *IncrSrc; + volatile uint32 *StartAddrDst; + volatile sint16 *IncrSrcMA; + volatile uint32 *StartAddrSrc; +} TASK_GEN_DP_3_api_t; +extern TASK_GEN_DP_3_api_t *TASK_GEN_DP_3_api; + +typedef struct task_info12 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[8]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrDstFIFO; + volatile sint16 *IncrBytes; + volatile uint32 *AddrEnable; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableBase; + volatile sint16 *IncrSrcMA; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_TX_BD_api_t; +extern TASK_GEN_TX_BD_api_t *TASK_GEN_TX_BD_api; + +typedef struct task_info13 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *AddrSrcFIFO; + volatile sint16 *IncrDst; + volatile uint32 *BDTableBase; + volatile uint32 *BDTableLast; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_RX_BD_api_t; +extern TASK_GEN_RX_BD_api_t *TASK_GEN_RX_BD_api; + +typedef struct task_info14 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDst; + volatile uint32 *BDTableLast; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_DP_BD_0_api_t; +extern TASK_GEN_DP_BD_0_api_t *TASK_GEN_DP_BD_0_api; + +typedef struct task_info15 { + volatile uint32 TaskNum; + volatile uint32 *PtrStartTDT; + volatile uint32 *PtrEndTDT; + volatile uint32 *PtrVarTab; + volatile uint32 *PtrFDT; + volatile uint32 *PtrCSave; + volatile uint32 NumDRD; + volatile uint32 *DRD[7]; + volatile uint32 NumVar; + volatile uint32 *var; + volatile uint32 NumInc; + volatile uint32 *inc; + volatile uint8 *TaskPragma; + volatile uint32 *AddrEnable; + volatile sint16 *IncrBytes; + volatile uint32 *BDTableBase; + volatile sint16 *IncrDst; + volatile uint32 *BDTableLast; + volatile sint16 *IncrSrc; + volatile uint32 *BDTableStart; + volatile uint32 *Bytes; +} TASK_GEN_DP_BD_1_api_t; +extern TASK_GEN_DP_BD_1_api_t *TASK_GEN_DP_BD_1_api; + + +#endif /* __DMA_IMAGE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h new file mode 100644 index 0000000000..9e4b94cd10 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h @@ -0,0 +1,61 @@ +#ifndef __MGT5200_MGT5200_H +#define __MGT5200_MGT5200_H + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +#define MBAR_CS 0x0000 +#define MBAR_SDRAM 0x0100 +#define MBAR_CDM 0x0200 +#define MBAR_LPC 0x0300 +#define MBAR_SCTMR 0x0400 +#define MBAR_INT_CTRL 0x0500 +#define MBAR_GPTIMER 0x0600 +#define MBAR_SLTIMER 0x0700 +#define MBAR_RTCLOCK 0x0800 +#define MBAR_MSCAN 0x0900 +#define MBAR_GPIO_STD 0x0B00 +#define MBAR_GPIO_WKUP 0x0C00 +#define MBAR_XCPCI 0x0D00 +#define MBAR_SPI 0x0F00 +#define MBAR_USB 0x1000 +#define MBAR_SDMA 0x1200 +#define MBAR_BDLC 0x1300 +#define MBAR_IR 0x1400 +#define MBAR_XLB_ARB 0x1F00 +#define MBAR_PSC1 0x2000 +#define MBAR_PSC2 0x2200 +#define MBAR_PSC3 0x2400 +#define MBAR_PSC4 0x2600 +#define MBAR_PSC5 0x2800 +#define MBAR_PSC6 0x2C00 +#define MBAR_IRDA 0x2C00 +#define MBAR_ETHERNET 0x3000 +#define MBAR_SCPCI 0x3800 +#define MBAR_ATA 0x3A00 +#define MBAR_SCLPC 0x3C00 +#define MBAR_I2C 0x3D00 +#define MBAR_SRAM 0x8000 + +#endif /* __MGT5200_MGT5200_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h new file mode 100644 index 0000000000..52d84777ad --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h @@ -0,0 +1,153 @@ +#ifndef __MGT5200_SDMA_H +#define __MGT5200_SDMA_H + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +typedef struct sdma_register_set { + volatile uint32 taskBar; /* MBAR_SDMA + 0x00 sdTpb */ + volatile uint32 currentPointer; /* MBAR_SDMA + 0x04 sdMdeComplex */ + volatile uint32 endPointer; /* MBAR_SDMA + 0x08 sdMdeComplex */ + volatile uint32 variablePointer; /* MBAR_SDMA + 0x0c sdMdeComplex */ + + volatile uint8 IntVect1; /* MBAR_SDMA + 0x10 sdPtd */ + volatile uint8 IntVect2; /* MBAR_SDMA + 0x11 sdPtd */ + volatile uint16 PtdCntrl; /* MBAR_SDMA + 0x12 sdPtd */ + + volatile uint32 IntPend; /* MBAR_SDMA + 0x14 sdPtd */ + volatile uint32 IntMask; /* MBAR_SDMA + 0x18 sdPtd */ + + volatile uint32 TCR01; /* MBAR_SDMA + 0x1c sdPtd */ + volatile uint32 TCR23; /* MBAR_SDMA + 0x20 sdPtd */ + volatile uint32 TCR45; /* MBAR_SDMA + 0x24 sdPtd */ + volatile uint32 TCR67; /* MBAR_SDMA + 0x28 sdPtd */ + volatile uint32 TCR89; /* MBAR_SDMA + 0x2c sdPtd */ + volatile uint32 TCRAB; /* MBAR_SDMA + 0x30 sdPtd */ + volatile uint32 TCRCD; /* MBAR_SDMA + 0x34 sdPtd */ + volatile uint32 TCREF; /* MBAR_SDMA + 0x38 sdPtd */ + + volatile uint8 IPR0; /* MBAR_SDMA + 0x3c sdPtd */ + volatile uint8 IPR1; /* MBAR_SDMA + 0x3d sdPtd */ + volatile uint8 IPR2; /* MBAR_SDMA + 0x3e sdPtd */ + volatile uint8 IPR3; /* MBAR_SDMA + 0x3f sdPtd */ + volatile uint8 IPR4; /* MBAR_SDMA + 0x40 sdPtd */ + volatile uint8 IPR5; /* MBAR_SDMA + 0x41 sdPtd */ + volatile uint8 IPR6; /* MBAR_SDMA + 0x42 sdPtd */ + volatile uint8 IPR7; /* MBAR_SDMA + 0x43 sdPtd */ + volatile uint8 IPR8; /* MBAR_SDMA + 0x44 sdPtd */ + volatile uint8 IPR9; /* MBAR_SDMA + 0x45 sdPtd */ + volatile uint8 IPR10; /* MBAR_SDMA + 0x46 sdPtd */ + volatile uint8 IPR11; /* MBAR_SDMA + 0x47 sdPtd */ + volatile uint8 IPR12; /* MBAR_SDMA + 0x48 sdPtd */ + volatile uint8 IPR13; /* MBAR_SDMA + 0x49 sdPtd */ + volatile uint8 IPR14; /* MBAR_SDMA + 0x4a sdPtd */ + volatile uint8 IPR15; /* MBAR_SDMA + 0x4b sdPtd */ + volatile uint8 IPR16; /* MBAR_SDMA + 0x4c sdPtd */ + volatile uint8 IPR17; /* MBAR_SDMA + 0x4d sdPtd */ + volatile uint8 IPR18; /* MBAR_SDMA + 0x4e sdPtd */ + volatile uint8 IPR19; /* MBAR_SDMA + 0x4f sdPtd */ + volatile uint8 IPR20; /* MBAR_SDMA + 0x50 sdPtd */ + volatile uint8 IPR21; /* MBAR_SDMA + 0x51 sdPtd */ + volatile uint8 IPR22; /* MBAR_SDMA + 0x52 sdPtd */ + volatile uint8 IPR23; /* MBAR_SDMA + 0x53 sdPtd */ + volatile uint8 IPR24; /* MBAR_SDMA + 0x54 sdPtd */ + volatile uint8 IPR25; /* MBAR_SDMA + 0x55 sdPtd */ + volatile uint8 IPR26; /* MBAR_SDMA + 0x56 sdPtd */ + volatile uint8 IPR27; /* MBAR_SDMA + 0x57 sdPtd */ + volatile uint8 IPR28; /* MBAR_SDMA + 0x58 sdPtd */ + volatile uint8 IPR29; /* MBAR_SDMA + 0x59 sdPtd */ + volatile uint8 IPR30; /* MBAR_SDMA + 0x5a sdPtd */ + volatile uint8 IPR31; /* MBAR_SDMA + 0x5b sdPtd */ + + volatile uint32 cReqSelect; /* MBAR_SDMA + 0x5c sdPtd */ + volatile uint32 taskSize0; /* MBAR_SDMA + 0x60 sdPtd */ + volatile uint32 taskSize1; /* MBAR_SDMA + 0x64 sdPtd */ + volatile uint32 MDEDebug; /* MBAR_SDMA + 0x68 sdMdeComplex */ + volatile uint32 ADSDebug; /* MBAR_SDMA + 0x6c sdAdsTop */ + volatile uint32 Value1; /* MBAR_SDMA + 0x70 sdDbg */ + volatile uint32 Value2; /* MBAR_SDMA + 0x74 sdDbg */ + volatile uint32 Control; /* MBAR_SDMA + 0x78 sdDbg */ + volatile uint32 Status; /* MBAR_SDMA + 0x7c sdDbg */ + volatile uint32 PTDDebug; /* MBAR_SDMA + 0x80 sdPtd */ +} sdma_regs; + +#define SDMA_PTDCNTRL_TI 0x8000 +#define SDMA_PTDCNTRL_TEA 0x4000 +#define SDMA_PTDCNTRL_HE 0x2000 +#define SDMA_PTDCNTRL_PE 0x0001 + +#define SDMA_CREQSELECT_REQ31_MASK (~0xC0000000UL) +#define SDMA_CREQSELECT_REQ30_MASK (~0x30000000UL) +#define SDMA_CREQSELECT_REQ29_MASK (~0x0C000000UL) +#define SDMA_CREQSELECT_REQ28_MASK (~0x03000000UL) +#define SDMA_CREQSELECT_REQ27_MASK (~0x00C00000UL) +#define SDMA_CREQSELECT_REQ26_MASK (~0x00300000UL) +#define SDMA_CREQSELECT_REQ25_MASK (~0x000C0000UL) +#define SDMA_CREQSELECT_REQ24_MASK (~0x00030000UL) +#define SDMA_CREQSELECT_REQ23_MASK (~0x0000C000UL) +#define SDMA_CREQSELECT_REQ22_MASK (~0x00003000UL) +#define SDMA_CREQSELECT_REQ21_MASK (~0x00000C00UL) +#define SDMA_CREQSELECT_REQ20_MASK (~0x00000300UL) +#define SDMA_CREQSELECT_REQ19_MASK (~0x000000C0UL) +#define SDMA_CREQSELECT_REQ18_MASK (~0x00000030UL) +#define SDMA_CREQSELECT_REQ17_MASK (~0x0000000CUL) +#define SDMA_CREQSELECT_REQ16_MASK (~0x00000003UL) + +#define SDMA_CREQSELECT_REQ31_ALWAYS31 0xC0000000UL +#define SDMA_CREQSELECT_REQ30_ALWAYS30 0x30000000UL +#define SDMA_CREQSELECT_REQ29_ALWAYS29 0x0C000000UL +#define SDMA_CREQSELECT_REQ28_ALWAYS28 0x03000000UL +#define SDMA_CREQSELECT_REQ27_ALWAYS27 0x00C00000UL +#define SDMA_CREQSELECT_REQ26_ALWAYS26 0x00300000UL +#define SDMA_CREQSELECT_REQ25_ALWAYS25 0x000C0000UL +#define SDMA_CREQSELECT_REQ24_ALWAYS24 0x00030000UL +#define SDMA_CREQSELECT_REQ23_ALWAYS23 0x0000C000UL +#define SDMA_CREQSELECT_REQ22_ALWAYS22 0x00003000UL +#define SDMA_CREQSELECT_REQ21_ALWAYS21 0x00000C00UL +#define SDMA_CREQSELECT_REQ20_ALWAYS20 0x00000300UL +#define SDMA_CREQSELECT_REQ19_ALWAYS19 0x000000C0UL +#define SDMA_CREQSELECT_REQ18_ALWAYS18 0x00000030UL +#define SDMA_CREQSELECT_REQ17_ALWAYS17 0x0000000CUL +#define SDMA_CREQSELECT_REQ16_ALWAYS16 0x00000003UL + +#define SDMA_CREQSELECT_REQ31_SCTIMER7 0x00000000UL +#define SDMA_CREQSELECT_REQ30_SCTIMER6 0x00000000UL +#define SDMA_CREQSELECT_REQ29_SCTIMER5 0x00000000UL +#define SDMA_CREQSELECT_REQ28_SCTIMER4 0x00000000UL +#define SDMA_CREQSELECT_REQ27_SCTIMER3 0x00000000UL +#define SDMA_CREQSELECT_REQ26_PSC6_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ25_PSC6_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ24_I2C1_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ23_I2C1_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ22_I2C2_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ21_I2C2_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ20_PSC4_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ19_PSC4_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ18_PSC5_TX 0x00000000UL +#define SDMA_CREQSELECT_REQ17_PSC5_RX 0x00000000UL +#define SDMA_CREQSELECT_REQ16_LP 0x00000000UL + +#define SDMA_CREQSELECT_ALWAYS30 0xC0000000UL + +#endif /* __MGT5200_SDMA_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h new file mode 100644 index 0000000000..ff2aed1997 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h @@ -0,0 +1,43 @@ +#ifndef __PPCTYPES_H +#define __PPCTYPES_H + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef unsigned long long uint64; + +typedef signed char sint8; +typedef signed short sint16; +typedef signed long sint32; +typedef signed long long sint64; + +typedef volatile unsigned char reg8; +typedef volatile unsigned short reg16; +typedef volatile unsigned long reg32; +typedef volatile unsigned long long reg64; + +#endif /* __PPCTYPES_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h new file mode 100644 index 0000000000..dc529d6a22 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h @@ -0,0 +1,67 @@ +#ifndef __TASK_API_BESTCOMM_API_MEM_H +#define __TASK_API_BESTCOMM_API_MEM_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +#include "../include/mgt5200/mgt5200.h" + +/* + * An extern global variable is used here for the MBAR since it must + * be passed into the API for processes that use virtual memory. + */ +extern uint8 *MBarGlobal; + +#define SDMA_TASK_BAR (MBarGlobal+MBAR_SDMA+0x000) +#define SDMA_INT_PEND (MBarGlobal+MBAR_SDMA+0x014) +#define SDMA_INT_MASK (MBarGlobal+MBAR_SDMA+0x018) +#define SDMA_TCR (MBarGlobal+MBAR_SDMA+0x01C) +#define SDMA_TASK_SIZE (MBarGlobal+MBAR_SDMA+0x060) + +#define PCI_TX_PKT_SIZE (MBarGlobal+MBAR_SCPCI+0x000) +#define PCI_TX_NTBIT (MBarGlobal+MBAR_SCPCI+0x01C) +#define PCI_TX_FIFO (MBarGlobal+MBAR_SCPCI+0x040) +#define PCI_TX_FIFO_STAT (MBarGlobal+MBAR_SCPCI+0x045) +#define PCI_TX_FIFO_GRAN (MBarGlobal+MBAR_SCPCI+0x048) +#define PCI_TX_FIFO_ALARM (MBarGlobal+MBAR_SCPCI+0x04E) + +#define PCI_RX_PKT_SIZE (MBarGlobal+MBAR_SCPCI+0x080) +#define PCI_RX_NTBIT (MBarGlobal+MBAR_SCPCI+0x09C) +#define PCI_RX_FIFO (MBarGlobal+MBAR_SCPCI+0x0C0) +#define PCI_RX_FIFO_STAT (MBarGlobal+MBAR_SCPCI+0x0C5) +#define PCI_RX_FIFO_GRAN (MBarGlobal+MBAR_SCPCI+0x0C8) +#define PCI_RX_FIFO_ALARM (MBarGlobal+MBAR_SCPCI+0x0CE) + + +#define FEC_RX_FIFO (MBarGlobal+MBAR_ETHERNET+0x184) +#define FEC_RX_FIFO_STAT (MBarGlobal+MBAR_ETHERNET+0x188) +#define FEC_RX_FIFO_GRAN (MBarGlobal+MBAR_ETHERNET+0x18C) +#define FEC_RX_FIFO_ALARM (MBarGlobal+MBAR_ETHERNET+0x198) + +#define FEC_TX_FIFO (MBarGlobal+MBAR_ETHERNET+0x1A4) +#define FEC_TX_FIFO_STAT (MBarGlobal+MBAR_ETHERNET+0x1A8) +#define FEC_TX_FIFO_GRAN (MBarGlobal+MBAR_ETHERNET+0x1AC) +#define FEC_TX_FIFO_ALARM (MBarGlobal+MBAR_ETHERNET+0x1B8) + +#endif /* __TASK_API_BESTCOMM_API_MEM_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h new file mode 100644 index 0000000000..3712bae3d0 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h @@ -0,0 +1,282 @@ +#ifndef __TASK_API_BESTCOMM_CNTRL_H +#define __TASK_API_BESTCOMM_CNTRL_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/******************************************************************************* + * Defines to control SmartDMA and its tasks. These defines are used for the + * task build process to minimize disconnects at the task/driver interface. + ******************************************************************************/ + +#define SDMA_INT_BIT_DBG 31 /* debug interrupt bit */ +#define SDMA_INT_BIT_TEA 28 /* TEA interrupt bit */ +#define SDMA_INT_BIT_TEA_TASK 24 /* lsb for TEA task number */ +#define SDMA_INT_BIT_IMPL 0x9000FFFF + +#define SDMA_PTDCTRL_BIT_TEA 14 /* TEA detection enable bit */ + +#define SDMA_TCR_BIT_AUTO 15 /* auto start bit */ +#define SDMA_TCR_BIT_HOLD 5 /* hold initiator bit */ + +#define SDMA_STAT_BIT_ALARM 17 +#define SDMA_FIFO_ALARM_MASK 0x0020000 + +#define SDMA_DRD_BIT_TFD 27 /* mark last buffer of frame */ +#define SDMA_DRD_BIT_INT 26 /* interrupt after buffer processed */ +#define SDMA_DRD_BIT_INIT 21 /* lsb position of initiator */ +#define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */ +#define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */ +#define SDMA_BD_BIT_READY 30 /* Status BD ready bit */ +#ifdef SAS_COMPILE + #define SDMA_BD_MASK_READY constant(1<<SDMA_BD_BIT_READY) +#else + #define SDMA_BD_MASK_READY (1<<SDMA_BD_BIT_READY) +#endif +#define SDMA_BD_MASK_SIGN 0x7FFFFFFF /* task code needs Status>0 */ + +#define SDMA_PRAGMA_BIT_RSV 7 /* reserved pragma bit */ +#define SDMA_PRAGMA_BIT_PRECISE_INC 6 /* increment 0=when possible, 1=iter end */ +#define SDMA_PRAGMA_BIT_RST_ERROR_NO 5 /* don't reset errors on task enable */ +#define SDMA_PRAGMA_BIT_PACK 4 /* pack data enable */ +#define SDMA_PRAGMA_BIT_INTEGER 3 /* data alignment 0=frac(msb), 1=int(lsb) */ +#define SDMA_PRAGMA_BIT_SPECREAD 2 /* XLB speculative read enable */ +#define SDMA_PRAGMA_BIT_CW 1 /* write line buffer enable */ +#define SDMA_PRAGMA_BIT_RL 0 /* read line buffer enable */ + +#define SDMA_TASK_ENTRY_BYTES 32 /* Bytes per task in entry table */ +#define SDMA_TASK_GROUP_NUM 16 /* Number of tasks per task group */ +#define SDMA_TASK_GROUP_BYTES (SDMA_TASK_ENTRY_BYTES*SDMA_TASK_GROUP_NUM) + + +/******************************************************************************* + * Task group control macros, use when TaskNum > 15 + ******************************************************************************/ +#define SDMA_TASKNUM_EXT(OldTaskNum) (OldTaskNum%16) + +#define SDMA_TASKBAR_CHANGE(sdma, OldTaskNum) { \ + sdma->taskBar += (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \ +} + +#define SDMA_TASKBAR_RESTORE(sdma, OldTaskNum) { \ + sdma->taskBar -= (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \ +} + + +/******************************************************************************* + * Task control macros + ******************************************************************************/ +#define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000 | \ + ((AutoStart!=0)<<7) | \ + (AutoStartNum&0xF) ); \ +} + +#define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)((*(((volatile uint16 *)RegAddr)+TaskNum) & \ + (uint16) 0xff30) | ((uint16)(0x0000 | \ + ((AutoStart!=0)<<7) | \ + (AutoStartNum&0xF)) )); \ +} + +#define SDMA_TASK_ENABLE(RegAddr, TaskNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) |= (uint16)0x8000; \ +} + +#define SDMA_TASK_DISABLE(RegAddr, TaskNum) { \ + *(((volatile uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \ +} + +#define SDMA_TASK_STATUS(RegAddr, TaskNum) \ + *(((volatile uint16 *)RegAddr)+TaskNum) + + +/******************************************************************************* + * Interrupt control macros + ******************************************************************************/ +#define SDMA_INT_ENABLE(RegAddr, Bit) \ + do { \ + rtems_interrupt_level level; \ + rtems_interrupt_disable(level); \ + *((volatile uint32 *) RegAddr) &= ~((uint32) (1 << Bit)); \ + rtems_interrupt_enable(level); \ + } while (0) + +#define SDMA_INT_DISABLE(RegAddr, Bit) \ + do { \ + rtems_interrupt_level level; \ + rtems_interrupt_disable(level); \ + *((volatile uint32 *) (RegAddr)) |= ((uint32)(1 << Bit)); \ + rtems_interrupt_enable(level); \ + } while (0) + +#define SDMA_INT_SOURCE(RegPend, RegMask) \ + (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL) + +#define SDMA_INT_PENDING(RegPend, RegMask) \ + (*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask)))) + +#define SDMA_INT_TEST(IntSource, Bit) \ + (((uint32)IntSource) & ((uint32)(1<<Bit))) + +/* + * define SDMA_INT_FIND to get int bit rather than scan all bits use + * cntlzw + */ + +/* Clear the IntPend bit */ +#define SDMA_CLEAR_IEVENT(RegAddr, Bit) { \ + *((volatile uint32 *)RegAddr) = ((uint32)(1<<Bit)); \ +} + +#define SDMA_GET_PENDINGBIT(sdma, Bit) \ + (sdma->IntPend & (uint32)(1<<Bit)) + +#define SDMA_GET_MASKBIT(sdma, Bit) \ + (sdma->IntMask & (uint32)(1<<Bit)) + + +/******************************************************************************* + * SmartDMA FIFO control macros + ******************************************************************************/ + +/******************************************************************************* + * SmartDMA TEA detection control macros + ******************************************************************************/ +/* Enable SmartDMA TEA detection and TEA interrupt */ +#define SDMA_TEA_ENABLE(sdma) { \ + SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_TEA); \ + sdma->PtdCntrl &= ~((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \ +} + +/* Disable SmartDMA TEA detection and TEA interrupt */ +#define SDMA_TEA_DISABLE(sdma) { \ + SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_TEA); \ + sdma->PtdCntrl |= ((uint32)(1<<SDMA_PTDCTRL_BIT_TEA)); \ +} + +/* Clear the TEA interrupt */ +#define SDMA_TEA_CLEAR(sdma) { \ + sdma->IntPend = ((uint32)(0x1F<<SDMA_INT_BIT_TEA_TASK)); \ +} + +/* Determine which task caused a TEA on the XLB */ +#define SDMA_TEA_SOURCE(RegPend) \ + (uint32)(((*(volatile uint32 *)RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF) + + +/******************************************************************************* + * SmartDMA debug control macros + ******************************************************************************/ +/* Enable the SmartDMA debug unit and DBG interrupt */ +/* add sdma->dbg_regs setup? */ +#define SDMA_DBG_ENABLE(sdma) { \ + SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_DBG); \ +} + +#define SDMA_DBG_DISABLE(sdma) { \ + SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_DBG); \ +} + +/* Clear the debug interrupt */ +#define SDMA_DBG_CLEAR(sdma) { \ + SDMA_CLEAR_IEVENT(sdma, SDMA_INT_BIT_DBG); \ +} + +#define SDMA_DBG_MDE(dst, sdma, addr) { \ + sdma->MDEDebug = addr; \ + dst = sdma->MDEDebug; \ +} + +#define SDMA_DBG_ADS(dst, sdma, addr) { \ + sdma->ADSDebug = addr; \ + dst = sdma->ADSDebug; \ +} + +#define SDMA_DBG_PTD(dst, sdma, addr) { \ + sdma->PTDDebug = addr; \ + dst = sdma->PTDDebug; \ +} + + +/******************************************************************************* + * Initiator control macros + ******************************************************************************/ + +/* This macro may not work, getting compile errors */ +/* Set the Transfer Size */ +/* Note that masking the size w/ 0x3 gives the desired value for uint32 */ +/* (expressed as 4), namely 0. */ +#define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize) \ + *(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) = \ + (uint8)((*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) & \ + ((TaskNum%2) ? 0xf0 : 0x0f)) | \ + ((uint8)(((SrcSize & 0x3)<<2) | \ + ( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2)))))); + +/* This macro may not work */ +/* Set the Initiator in TCR */ +#define SDMA_SET_INIT(RegAddr, TaskNum, Initiator) \ +{ \ + *(((volatile uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF; \ + *(((volatile uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) | \ + (0<<SDMA_TCR_BIT_HOLD)); \ +} + +/* Change DRD initiator number */ +#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \ + int i; \ + for (i=0; i<task->NumDRD; i++) { \ + if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \ + SDMA_INIT_WRITE(task->DRD[i],newInitiator); \ + } \ + } \ +} + +/* Set the Initiator Priority */ +#define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority) \ + *(((volatile uint8 *)&sdma->IPR0)+initiator) = priority; + + +/* Read DRD initiator number */ +#define SDMA_INIT_READ(PtrDRD) \ + (((*(volatile uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F) + +/* Write DRD initiator number */ +#define SDMA_INIT_WRITE(PtrDRD, Initiator) { \ + *(volatile uint32 *)PtrDRD = ((*(volatile uint32 *)PtrDRD) & 0xFC1FFFFF) | \ + (Initiator<<SDMA_DRD_BIT_INIT); \ +} + +/* Change DRD initiator number */ +#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) { \ + int i; \ + for (i=0; i<task->NumDRD; i++) { \ + if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) { \ + SDMA_INIT_WRITE(task->DRD[i],newInitiator); \ + } \ + } \ +} + +#endif /* __TASK_API_BESTCOMM_CNTRL_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h new file mode 100644 index 0000000000..7f261d21ee --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h @@ -0,0 +1,86 @@ +#ifndef __TASK_API_TASKSETUP_BDTABLE_H +#define __TASK_API_TASKSETUP_BDTABLE_H 1 + +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/* + * Table of BD rings for all BestComm tasks indexed by task ID. + * + * +-----+------+--------------+ +------+-------+ + * 0: |numBD|numPtr|BDTablePtr ---|--->|status|dataPtr| + * +-----+------+--------------+ +------+-------+ + * 1: |numBD|numPtr|BDTablePtr | |status|dataPtr| + * +-----+------+--------------+ . . . + * 2: |numBD|numPtr|BDTablePtr ---|-+ . . . + * . . . | . . . + * . . . | |status|dataPtr| + * . . . | +------+-------+ + * 15:|numBD|numPtr|BDTablePtr | | + * +-----+------+--------------+ | + * | + * V + * +------+--------+--------+ + * |status|dataPtr0|dataPtr1| + * +------+--------+--------+ + * |status|dataPtr0|dataPtr1| + * . . . . + * . . . . + * . . . . + * |status|dataPtr0|dataPtr1| + * +------+--------+--------+ + */ +typedef struct { + uint16 numBD; /* Size of BD ring */ + uint8 numPtr; /* Number of data buffer pointers per BD */ + uint8 apiConfig; /* API configuration flags */ + void *BDTablePtr; /* Pointer to BD tables, must be cast to TaskBD1_t */ + /* or TaskBD2_t */ + volatile uint32 + *BDStartPtr; /* Task's current BD pointer. This pointer is + * used to set a task's BD pointer upon startup. + * It is only valid for BD tasks and only after + * TaskSetup() or TaskBDReset() are called. You + * cannot use this to track a task's BD pointer. + */ + uint16 currBDInUse; /* Current number of buffer descriptors assigned but*/ + /* not released yet. */ +} TaskBDIdxTable_t; + +typedef enum { + API_CONFIG_NONE = 0x00, + API_CONFIG_BD_FLAG = 0x01 +} ApiConfig_t; + +/* + * Allocates BD table if needed and updates the BD index table. + * Do we want to hide this from the C API since it operates on task API? + */ +void TaskSetup_BDTable(volatile uint32 *BasePtr, + volatile uint32 *LastPtr, + volatile uint32 *StartPtr, + int TaskNum, uint32 NumBD, uint16 MaxBD, + uint8 NumPtr, ApiConfig_t ApiConfig, uint32 Status ); + +#endif /* __TASK_API_TASKSETUP_BDTABLE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h new file mode 100644 index 0000000000..be7bb9d7b0 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h @@ -0,0 +1,624 @@ +/****************************************************************************** +* +* Copyright (c) 2004 Freescale Semiconductor, Inc. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +******************************************************************************/ + +/* + * Task builder generates a set #defines per configured task to + * condition this templete file. + */ + +/********************************************************** + * + * Required #defines: + * ------------------ + * TASKSETUP_NAME: + * TaskSetup function name, set to TaskSetup_<TASK_NAME> + * TASK_API: + * task API defined in dma_image.h + * MAX_BD: + * <=0 : non-BD task + * else: number of BD in BD table + * BD_FLAG: + * 0 : no flag implemented for BD + * else: flags can be passed on a per BD basis + * MISALIGNED: + * 0 : task API supports Bytes%IncrBytes==0 + * else: task API supports any parameter settings + * AUTO_START: + * <-1 : do not start a task after task completion + * -1 : auto start the task after task completion + * <MAX_TASKS: auto start task with the TaskID = AUTO_START + * else : do not start a task after task completion + * INITIATOR_DATA: + * <0 : runtime configurable + * else: assume INITATOR_DATA equal hard-coded task initiator + * TYPE_SRC: (needs to be consistent with Task API) + * FLEX_T : Task API TYPE_SRC = flex, SzSrc defines size + * UINT8_T : Task API TYPE_SRC = char + * UINT16_T: Task API TASK_SRC = short + * UINT32_T: Task API TASK_SRC = int + * INCR_TYPE_SRC: + * 0 : FIFO address, do not implement data pointer + * 1 : automatic, set INCR_SRC based on SzSrc parameter + * 2 : runtime, set INCR_SRC to IncrSrc parameter + * else: used hard-coded INCR_SRC + * INCR_SRC: + * INCR_TYPE_SRC=0: force INCR_SRC=0 + * else : use for src pointer increment + * TYPE_DST: (needs to be consistent with Task API) + * FLEX_T : Task API TYPE_DST = flex, SzDst defines size + * UINT8_T : Task API TYPE_DST = char + * UINT16_T: Task API TASK_DST = short + * UINT32_T: Task API TASK_DST = int + * INCR_TYPE_DST: + * 0 : FIFO address, do not implement data pointer + * 1 : automatic, set INCR_DST based on SzDst parameter + * 2 : runtime, set INCR_DST to IncrDst parameter + * else: used hard-coded INCR_DST + * INCR_DST: + * INCR_TYPE_DST=0: force INCR_DST=0 + * else : use for dst pointer increment + * PRECISE_INCREMENT: + * 0 : increment when possible + * else: increment at end of iteration + * NO_ERROR_RESET: + * 0 : reset error flags on task enable + * else: leave error flags unmodified on task enable + * PACK_DATA: + * 0 : do not pack data + * else: pack data based on data type + * INTEGER_MODE: + * 0 : type conversions handle as fixed point numbers + * else: type conversions handle as integers + * WRITE_LINE_BUFFER: + * 0 : do not use write line buffers + * else: enable write line buffers + * READ_LINE_BUFFER: + * 0 : do not use read line buffers + * else: enable read line buffers + * SPEC_READS: + * 0 : do not speculatively read + * else: speculatively read data ahead of DMA engine + * + * Optional #defines: + * ------------------ + * MAX_TASKS: + * 1 : #define MAX_TASKS>0 + * else: 16 + * ITERATIONS: + * 1 : #define ITERATIONS>0 + * else: 1 + * INCR_BYTES: + * This macro is defined based on following priority: + * 1 : INCR_SRC != 0 + * 2 : DST_TYPE != 0 + * 3 : #defined INCR_BYTES<0 + * else: -4 (SZ_UINT32) + * DEBUG_BESTCOMM_API: + * >0 : print basic debug messages + * >=10: also print C-API interface variables + * >=20: also print task API interface variables + * else: do nothing + * + **********************************************************/ + +#if defined(__rtems__) || defined(MPC5200_BAPI_LIBC_HEADERS) +#include <stdlib.h> +#endif + +#include "../dma_image.h" + +#include "../bestcomm_api.h" +#include "tasksetup_bdtable.h" + +#include "bestcomm_api_mem.h" +#include "bestcomm_cntrl.h" + +#ifndef DEBUG_BESTCOMM_API + #define DEBUG_BESTCOMM_API 0 +#endif + +#ifdef FLEX_T + #undef FLEX_T +#endif +#define FLEX_T SZ_FLEX + +#ifdef UINT8_T + #undef UINT8_T +#endif +#define UINT8_T SZ_UINT8 + +#ifdef UINT16_T + #undef UINT16_T +#endif +#define UINT16_T SZ_UINT16 + +#ifdef UINT32_T + #undef UINT32_T +#endif +#define UINT32_T SZ_UINT32 + +#if (INCR_TYPE_SRC==0) /* FIFO address, no data pointer */ + #undef INCR_SRC + #define INCR_SRC 0 +#endif + +#if (INCR_TYPE_DST==0) /* FIFO address, no data pointer */ + #undef INCR_DST + #define INCR_DST 0 +#endif + +#ifndef MAX_TASKS + #define MAX_TASKS 16 +#else + #if (MAX_TASKS<=0) + #undef MAX_TASKS + #define MAX_TASKS 16 + #endif +#endif + +#ifndef ITERATIONS + #define ITERATIONS 1 +#else + #if (ITERATIONS<=0) + #undef ITERATIONS + #define ITERATIONS 1 + #endif +#endif + +#ifndef INCR_BYTES + #define INCR_BYTES -4 +#else + #if (INCR_BYTES>=0) + #undef INCR_BYTES + #define INCR_BYTES -4 + #endif +#endif + +/* + * These ifndefs will go away when support in task_capi wrappers + * in the image directories + */ +#ifndef PRECISE_INCREMENT + #define PRECISE_INCREMENT 0 /* bit=6 SAS->1, increment 0=when possible, 1=at the end of interation */ +#endif +#ifndef NO_ERROR_RESET + #define NO_ERROR_RESET 0 /* bit=5 SAS->0, do not reset error codes on task enable */ +#endif +#ifndef PACK_DATA + #define PACK_DATA 0 /* bit=4 SAS->0, pack data enable */ +#endif +#ifndef INTEGER_MODE + #define INTEGER_MODE 0 /* bit=3 SAS->0, 0=fractional(msb aligned), 1=integer(lsb aligned) */ +#endif +#ifndef SPEC_READS + #define SPEC_READS 1 /* bit=2 SAS->0, XLB speculative read enable */ +#endif +#ifndef WRITE_LINE_BUFFER + #define WRITE_LINE_BUFFER 1 /* bit=1 SAS->0, write line buffer enable */ +#endif +#ifndef READ_LINE_BUFFER + #define READ_LINE_BUFFER 1 /* bit=0 SAS->0, read line buffer enable */ +#endif +#define SDMA_PRAGMA (0 <<SDMA_PRAGMA_BIT_RSV ) | \ + (PRECISE_INCREMENT<<SDMA_PRAGMA_BIT_PRECISE_INC ) | \ + (NO_ERROR_RESET <<SDMA_PRAGMA_BIT_RST_ERROR_NO) | \ + (PACK_DATA <<SDMA_PRAGMA_BIT_PACK ) | \ + (INTEGER_MODE <<SDMA_PRAGMA_BIT_INTEGER ) | \ + (SPEC_READS <<SDMA_PRAGMA_BIT_SPECREAD ) | \ + (WRITE_LINE_BUFFER<<SDMA_PRAGMA_BIT_CW ) | \ + (READ_LINE_BUFFER <<SDMA_PRAGMA_BIT_RL ) + +#ifndef TASKSETUP_NAME + #define PREPEND_TASKSETUP(name) TaskSetup_ ## name + #define FUNC_PREPEND_TASKSETUP(name) PREPEND_TASKSETUP(name) + #define TASKSETUP_NAME FUNC_PREPEND_TASKSETUP(TASK_BASE) +#endif + +#ifndef TASK_API + #define APPEND_API(name) name ## _api_t + #define FUNC_APPEND_API(name) APPEND_API(name) + #define TASK_API FUNC_APPEND_API(TASK_BASE) +#endif + +#ifndef INIT_DMA_IMAGE + #define PREPEND_INITDMA(name) init_dma_image_ ## name + #define FUNC_PREPEND_INITDMA(name) PREPEND_INITDMA(name) + #define INIT_DMA_IMAGE FUNC_PREPEND_INITDMA(TASK_BASE) +#endif + +#define DRD_INIT_MASK 0xfc1fffff +#define DRD_EXT_FLAG 0x40000000 +#define DRD_INIT_OFFSET 21 + +TaskId TASKSETUP_NAME(TASK_API *TaskAPI, + TaskSetupParamSet_t *TaskSetupParams) +{ + TaskId TaskNum; +#if ((MAX_BD>0)||(DEBUG_BESTCOMM_API>0)) + uint32 Status = 0; +#endif +#if ((MAX_BD>0)&&((INCR_TYPE_SRC!=0)||(INCR_TYPE_DST!=0))||(DEBUG_BESTCOMM_API>0)) + uint8 NumPtr = 0; +#endif +#if (INITIATOR_DATA<0) /* runtime configurable */ + uint32 i, ext; +#endif + + INIT_DMA_IMAGE((uint8 *)(((sdma_regs *)(SDMA_TASK_BAR))->taskBar), MBarPhysOffsetGlobal); + + TaskNum = (TaskId)SDMA_TASKNUM_EXT(TaskAPI->TaskNum); + + TaskRunning[TaskNum] = 0; + +#if (DEBUG_BESTCOMM_API>0) + printf("\nBestComm API Debug Display Mode Enabled\n\n"); + printf("TaskSetup: TaskID=%d\n", TaskNum); + if (Status!=0) { + printf("TaskSetup: Rx task\n"); + } else { + printf("TaskSetup: Tx or DP task\n"); + } +#endif + + /* Set the task pragma settings */ + *(TaskAPI->TaskPragma)= (uint8) SDMA_PRAGMA; + +#if (MAX_BD>0) /* Buffer Descriptors */ + + #if (INCR_TYPE_SRC!=0) + ++NumPtr; + #endif + #if (INCR_TYPE_DST!=0) + ++NumPtr; + #endif + + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Using %d buffer descriptors, each with %d data pointers\n", MAX_BD, NumPtr); + #endif + + /* Allocate BD table SRAM storage, + * and pass addresses to task API */ + + TaskSetup_BDTable(TaskAPI->BDTableBase, + TaskAPI->BDTableLast, + TaskAPI->BDTableStart, + TaskNum, + TaskSetupParams->NumBD, + MAX_BD, NumPtr, + BD_FLAG, Status); + + *TaskAPI->AddrEnable = (uint32)((uint32)(((uint16 *)SDMA_TCR)+TaskNum) + MBarPhysOffsetGlobal); + + #if BD_FLAG + + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Buffer descriptor flags are enabled\n"); + #endif + + /* always assume 2nd to last DRD */ + *((TaskAPI->AddrDRD)) = (uint32)((uint32)TaskAPI->DRD[TaskAPI->AddrDRDIdx] + MBarPhysOffsetGlobal); + #endif /* #if BD_FLAG */ + +#else /* No Buffer Descriptors */ + +/* #error ATA should not be non-BD */ + + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Task will complete %d iterations before disabling\n"); + #endif + + *((TaskAPI->IterExtra)) = (uint32)(ITERATIONS-1); +#endif /* #if (MAX_BD>0) */ + +/* Setup auto start */ +#if (AUTO_START <= -2 ) /* do not start a task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto task start disabled\n"); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 0, TaskNum); +#elif (AUTO_START <= -1 ) /* restart task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto start task\n"); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 1, TaskNum); +#elif (AUTO_START < MAX_TASKS) /* start specific task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto start task with TaskID=%d\n", AUTO_START); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 1, AUTO_START); +#else /* do not start a task */ + #if (DEBUG_BESTCOMM_API>0) + printf("TaskSetup: Auto task start disabled\n"); + #endif + SDMA_TASK_CFG(SDMA_TCR, TaskNum, 0, TaskNum); +#endif + +#if (INITIATOR_DATA<0) /* runtime configurable */ + SDMA_SET_INIT(SDMA_TCR, TaskNum, TaskSetupParams->Initiator); + + /* + * Hard-code the task initiator in the DRD to avoid a problem w/ the + * hold initiator bit in the TCR. + */ + ext = 0; + for (i = 0; i < TaskAPI->NumDRD; i++) { + if (ext == 0) + { +#if (DEBUG_BESTCOMM_API>=10) + printf("TaskSetup: DRD[%d] initiator = %d\n", i, ((*(TaskAPI->DRD[i]) & ~DRD_INIT_MASK) >> DRD_INIT_OFFSET)); +#endif + if (((*(TaskAPI->DRD[i]) & ~DRD_INIT_MASK) >> DRD_INIT_OFFSET) != INITIATOR_ALWAYS) { +#if (DEBUG_BESTCOMM_API>=10) + printf("TaskSetup: Replacing DRD[%d] initiator with %d\n", i, TaskSetupParams->Initiator); +#endif + *(TaskAPI->DRD[i]) = (*(TaskAPI->DRD[i]) & DRD_INIT_MASK) + | (TaskSetupParams->Initiator << DRD_INIT_OFFSET); + } + + if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) != 0) + { + ext = 1; + } + } + else + { + if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) == 0) + { + ext = 0; + } + } + } + +#else /* INITIATOR_DATA >= 0 */ + TaskSetupParams->Initiator = INITIATOR_DATA; +#endif + +#if (DEBUG_BESTCOMM_API>=10) + printf("\nTaskSetup: C-API Parameter Settings Passed to TaskSetup:\n"); + printf("TaskSetup: NumBD = %d\n", TaskSetupParams->NumBD); + #if (MAX_BD>0) + printf("TaskSetup: MaxBuf = %d\n", TaskSetupParams->Size.MaxBuf); + #else + printf("TaskSetup: NumBytes = %d\n", TaskSetupParams->Size.NumBytes); + #endif + printf("TaskSetup: Initiator = %d\n", TaskSetupParams->Initiator); + printf("TaskSetup: StartAddrSrc = 0x%08X\n", TaskSetupParams->StartAddrSrc); + printf("TaskSetup: IncrSrc = %d\n", TaskSetupParams->IncrSrc); + printf("TaskSetup: SzSrc = %d\n", TaskSetupParams->SzSrc); + printf("TaskSetup: StartAddrDst = 0x%08X\n", TaskSetupParams->StartAddrDst); + printf("TaskSetup: IncrDst = %d\n", TaskSetupParams->IncrDst); + printf("TaskSetup: SzDst = %d\n", TaskSetupParams->SzDst); +#endif + +#if (DEBUG_BESTCOMM_API>=20) + printf("\nTaskSetup: Task-API Parameter Settings Before TaskSetup Initialization:\n"); + printf("TaskSetup: TaskNum = %d\n", (TaskAPI->TaskNum)); + printf("TaskSetup: TaskPragma = 0x%02X\n", *((TaskAPI->TaskPragma))); + printf("TaskSetup: TCR = 0x%04x\n", SDMA_TASK_STATUS(SDMA_TCR, TaskNum)); + + #if (MAX_BD>0) + printf("TaskSetup: BDTableBase = 0x%08X\n", *((TaskAPI->BDTableBase))); + printf("TaskSetup: BDTableLast = 0x%08X\n", *((TaskAPI->BDTableLast))); + printf("TaskSetup: BDTableStart = 0x%08X\n", *((TaskAPI->BDTableStart))); + printf("TaskSetup: AddrEnable = 0x%08X\n", *((TaskAPI->AddrEnable))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #endif + #if (BD_FLAG) + printf("TaskSetup: AddrDRD = 0x%08X\n", *((TaskAPI->AddrDRD))); + printf("TaskSetup: AddrDRDIdx = %d\n", ((TaskAPI->AddrDRDIdx))); + #endif + #else + printf("TaskSetup: IterExtra = %d\n", *((TaskAPI->IterExtra))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #else + printf("TaskSetup: StartAddrSrc = 0x%08X\n", *((TaskAPI->StartAddrSrc))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #else + printf("TaskSetup: StartAddrDst = 0x%08X\n", *((TaskAPI->StartAddrDst))); + #endif + #endif + #if (INCR_TYPE_SRC!=0) + printf("TaskSetup: IncrSrc = 0x%04X\n", *((TaskAPI->IncrSrc))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrSrcMA = 0x%04X\n", *((TaskAPI->IncrSrcMA))); + #endif + #endif + #if (INCR_TYPE_DST!=0) + printf("TaskSetup: IncrDst = 0x%04X\n", *((TaskAPI->IncrDst))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrDstMA = 0x%04X\n", *((TaskAPI->IncrDstMA))); + #endif + #endif + printf("TaskSetup: Bytes = %d\n", *((TaskAPI->Bytes))); + printf("TaskSetup: IncrBytes = %d\n", *((TaskAPI->IncrBytes))); +#endif + + + *((TaskAPI->Bytes)) = (uint32)TaskSetupParams->Size.MaxBuf; + + +#if (TYPE_SRC!=FLEX_T) /* size fixed in task code */ + TaskSetupParams->SzSrc = TYPE_SRC; +#endif + +#if (INCR_TYPE_SRC==0) /* no data pointer */ + TaskSetupParams->IncrSrc = (sint16)0; + *((TaskAPI->AddrSrcFIFO)) = (uint32)TaskSetupParams->StartAddrSrc; +#else + + #if (INCR_TYPE_SRC==1) /* automatic */ + if (TaskSetupParams->IncrSrc!=0) { + TaskSetupParams->IncrSrc = (sint16)+TaskSetupParams->SzSrc; + } else { + TaskSetupParams->IncrSrc = (sint16)+TaskSetupParams->IncrSrc; + } + #elif (INCR_TYPE_SRC!=2) /* hard-coded */ + TaskSetupParams->IncrSrc = (sint16)INCR_SRC; + #endif + *((TaskAPI->IncrSrc)) = (sint16)TaskSetupParams->IncrSrc; + + #if (MAX_BD>0) /* pointer in BD Table */ + /* pass back address of first BD */ + TaskSetupParams->StartAddrSrc = (uint32)TaskGetBDRing(TaskNum); + #else + *((TaskAPI->StartAddrSrc)) = (uint32)TaskSetupParams->StartAddrSrc; + #endif + + #if MISALIGNED | MISALIGNED_START + if (TaskSetupParams->IncrSrc < 0) { + *((TaskAPI->IncrSrcMA)) = (sint16)-1; + } else if (TaskSetupParams->IncrSrc > 0) { + *((TaskAPI->IncrSrcMA)) = (sint16)+1; + } else { + *((TaskAPI->IncrSrcMA)) = (sint16)0; + } + #endif +#endif + + +#if (TYPE_DST!=FLEX_T) /* size fixed in task code */ + TaskSetupParams->SzDst = TYPE_DST; +#endif + +#if (INCR_TYPE_DST==0) /* no data pointer */ + TaskSetupParams->IncrDst = (sint16)0; + *((TaskAPI->AddrDstFIFO)) = (uint32)TaskSetupParams->StartAddrDst; +#else + #if (INCR_TYPE_DST==1) /* automatic */ + if (TaskSetupParams->IncrDst!=0) { + TaskSetupParams->IncrDst = (sint16)+TaskSetupParams->SzDst; + } else { + TaskSetupParams->IncrDst = (sint16)+TaskSetupParams->IncrDst; + } + #elif (INCR_TYPE_DST!=2) /* hard-coded */ + TaskSetupParams->IncrDst = (sint16)INCR_DST; + #endif + *((TaskAPI->IncrDst)) = (sint16)TaskSetupParams->IncrDst; + + #if (MAX_BD>0) + /* pass back address of first BD */ + TaskSetupParams->StartAddrDst = (uint32)TaskGetBDRing(TaskNum); + #else + *((TaskAPI->StartAddrDst)) = (uint32)TaskSetupParams->StartAddrDst; + #endif + + #if MISALIGNED | MISALIGNED_START + if (TaskSetupParams->IncrDst < 0) { + *((TaskAPI->IncrDstMA)) = (sint16)-1; + } else if (TaskSetupParams->IncrDst > 0) { + *((TaskAPI->IncrDstMA)) = (sint16)+1; + } else { + *((TaskAPI->IncrDstMA)) = (sint16)0; + } + #endif +#endif + +/* always use macro, only affect code with #define TYPE_? flex */ + SDMA_SET_SIZE(SDMA_TASK_SIZE, TaskNum, TaskSetupParams->SzSrc, TaskSetupParams->SzDst); + + + if (TaskSetupParams->IncrSrc != 0) { + *((TaskAPI->IncrBytes)) = (sint16)-abs(TaskSetupParams->IncrSrc); + } else if (TaskSetupParams->IncrDst != 0) { + *((TaskAPI->IncrBytes)) = (sint16)-abs(TaskSetupParams->IncrDst); + } else { + *((TaskAPI->IncrBytes)) = (sint16)-abs(INCR_BYTES); + } + + +#if (DEBUG_BESTCOMM_API>=10) + printf("\nTaskSetup: C-API Parameter Settings Returned from TaskSetup:\n"); + printf("TaskSetup: NumBD = %d\n", TaskSetupParams->NumBD); + #if (MAX_BD>0) + printf("TaskSetup: MaxBuf = %d\n", TaskSetupParams->Size.MaxBuf); + #else + printf("TaskSetup: NumBytes = %d\n", TaskSetupParams->Size.NumBytes); + #endif + printf("TaskSetup: Initiator = %d\n", TaskSetupParams->Initiator); + printf("TaskSetup: StartAddrSrc = 0x%08X\n", TaskSetupParams->StartAddrSrc); + printf("TaskSetup: IncrSrc = %d\n", TaskSetupParams->IncrSrc); + printf("TaskSetup: SzSrc = %d\n", TaskSetupParams->SzSrc); + printf("TaskSetup: StartAddrDst = 0x%08X\n", TaskSetupParams->StartAddrDst); + printf("TaskSetup: IncrDst = %d\n", TaskSetupParams->IncrDst); + printf("TaskSetup: SzDst = %d\n", TaskSetupParams->SzDst); +#endif + +#if (DEBUG_BESTCOMM_API>=20) + printf("\nTaskSetup: Task-API Parameter Settings After TaskSetup Initialization:\n"); + printf("TaskSetup: TaskNum = %d\n", ((TaskAPI->TaskNum))); + printf("TaskSetup: TaskPragma = 0x%02X\n", *((TaskAPI->TaskPragma))); + + #if (MAX_BD>0) + printf("TaskSetup: BDTableBase = 0x%08X\n", *((TaskAPI->BDTableBase))); + printf("TaskSetup: BDTableLast = 0x%08X\n", *((TaskAPI->BDTableLast))); + printf("TaskSetup: BDTableStart = 0x%08X\n", *((TaskAPI->BDTableStart))); + printf("TaskSetup: AddrEnable = 0x%08X\n", *((TaskAPI->AddrEnable))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #endif + #if (BD_FLAG) + printf("TaskSetup: AddrDRD = 0x%08X\n", *((TaskAPI->AddrDRD))); + printf("TaskSetup: AddrDRDIdx = %d\n", ((TaskAPI->AddrDRDIdx))); + #endif + #else + printf("TaskSetup: IterExtra = %d\n", *((TaskAPI->IterExtra))); + #if (INCR_TYPE_SRC==0) + printf("TaskSetup: AddrSrcFIFO = 0x%08X\n", *((TaskAPI->AddrSrcFIFO))); + #else + printf("TaskSetup: StartAddrSrc = 0x%08X\n", *((TaskAPI->StartAddrSrc))); + #endif + #if (INCR_TYPE_DST==0) + printf("TaskSetup: AddrDstFIFO = 0x%08X\n", *((TaskAPI->AddrDstFIFO))); + #else + printf("TaskSetup: StartAddrDst = 0x%08X\n", *((TaskAPI->StartAddrDst))); + #endif + #endif + #if (INCR_TYPE_SRC!=0) + printf("TaskSetup: IncrSrc = 0x%04X\n", *((TaskAPI->IncrSrc))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrSrcMA = 0x%04X\n", *((TaskAPI->IncrSrcMA))); + #endif + #endif + #if (INCR_TYPE_DST!=0) + printf("TaskSetup: IncrDst = 0x%04X\n", *((TaskAPI->IncrDst))); + #if (MISALIGNED | MISALIGNED_START) + printf("TaskSetup: IncrDstMA = 0x%04X\n", *((TaskAPI->IncrDstMA))); + #endif + #endif + printf("TaskSetup: Bytes = %d\n", *((TaskAPI->Bytes))); + printf("TaskSetup: IncrBytes = %d\n", *((TaskAPI->IncrBytes))); +#endif + + return TaskNum; +} diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h b/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h new file mode 100644 index 0000000000..2b74adf366 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef BESTCOMM_OPS_H +#define BESTCOMM_OPS_H + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup BestCommOps BestComm Ops + * + * @ingroup BestComm + * + * @brief BestComm ops. + * + * @{ + */ + +#define VAR(i) (i) +#define VAR_COUNT 24 +#define INC(i) (24 + (i)) +#define INC_COUNT 8 +#define IDX(i) (48 + (i)) +#define IDX_COUNT 8 + +#define COND_ONCE 0 +#define COND_LT 1 +#define COND_GT 2 +#define COND_NE 3 +#define COND_EQ 4 +#define COND_LE 5 +#define COND_GE 6 +#define COND_FOREVER 7 + +#define INC_INIT(cond, val) \ + (BSP_FLD32(cond, 29, 31) \ + | BSP_FLD32((int16_t) (val), 0, 15)) + +#define TERM_FIRST 0 +#define TERM_SECOND 1 +#define TERM_INIT 2 +#define TERM_UNUSED 3 + +#define DEREF 1 + +#define LCD_TERM(val) BSP_FLD32(val, 13, 14) + +#define LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \ + (BSP_BIT32(31) \ + | BSP_FLD32(deref0, 29, 29) \ + | BSP_FLD32(iniidx0, 23, 28) \ + | BSP_FLD32(deref1, 21, 21) \ + | BSP_FLD32(iniidx1, 15, 20) \ + | LCD_TERM(term) \ + | BSP_FLD32(termop, 6, 11) \ + | BSP_FLD32(inc0, 3, 5) \ + | BSP_FLD32(inc1, 0, 2)) + +#define LCDEXT(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \ + (BSP_BIT32(30) \ + | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1)) + +#define LCDPLUS(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \ + (BSP_BIT32(22) \ + | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1)) + +#define LCDINIT(val) \ + (BSP_BIT32(31) \ + | BSP_FLD32((val) >> 13, 15, 29) \ + | LCD_TERM(TERM_INIT) \ + | BSP_FLD32(val, 0, 12)) + +#define MORE 0x4 + +#define TFD 0x2 + +#define INT 0x1 + +#define DRD_FLAGS(val) BSP_FLD32(val, 26, 28) + +#define INIT_ALWAYS 0 +#define INIT_SCTMR_0 1 +#define INIT_SCTMR_1 2 +#define INIT_FEC_RX 3 +#define INIT_FEC_TX 4 +#define INIT_ATA_RX 5 +#define INIT_ATA_TX 6 +#define INIT_SCPCI_RX 7 +#define INIT_SCPCI_TX 8 +#define INIT_PSC3_RX 9 +#define INIT_PSC3_TX 10 +#define INIT_PSC2_RX 11 +#define INIT_PSC2_TX 12 +#define INIT_PSC1_RX 13 +#define INIT_PSC1_TX 14 +#define INIT_SCTMR_2 15 +#define INIT_SCLPC 16 +#define INIT_PSC5_RX 17 +#define INIT_PSC5_TX 18 +#define INIT_PSC4_RX 19 +#define INIT_PSC4_TX 20 +#define INIT_I2C2_RX 21 +#define INIT_I2C2_TX 22 +#define INIT_I2C1_RX 23 +#define INIT_I2C1_TX 24 +#define INIT_PSC6_RX 25 +#define INIT_PSC6_TX 26 +#define INIT_IRDA_RX 25 +#define INIT_IRDA_TX 26 +#define INIT_SCTMR_3 27 +#define INIT_SCTMR_4 28 +#define INIT_SCTMR_5 29 +#define INIT_SCTMR_6 30 +#define INIT_SCTMR_7 31 + +#define DRD_INIT(val) BSP_FLD32(val, 21, 25) + +#define SZ_8 1 +#define SZ_16 2 +#define SZ_32 0 +#define SZ_DYN 3 + +#define DRD_RS(val) BSP_FLD32(val, 19, 20) + +#define DRD_WS(val) BSP_FLD32(val, 17, 18) + +#define DEST_VAR(val) (val) +#define DEST_IDX(val) (BSP_BIT32(5) | (val)) +#define DEST_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val)) + +#define SRC_VAR(val) (val) +#define SRC_INC(val) (BSP_BIT32(5) | (val)) +#define SRC_EU_RESULT (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0)) +#define SRC_DEREF_EU_RESULT (BSP_BIT32(6) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0)) +#define SRC_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | (val)) +#define SRC_DEREF_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | BSP_BIT32(4) | (val)) +#define SRC_NONE (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0)) + +#define DRD1A(flags, init, dest, ws, src, rs) \ + (DRD_FLAGS(flags) \ + | DRD_INIT(init) \ + | DRD_RS(rs) \ + | DRD_WS(ws) \ + | BSP_FLD32(dest, 10, 15) \ + | BSP_FLD32(src, 3, 9)) + +#define DRD1AEURESULT(flags, init, dest, ws, rs) \ + (DRD1A(flags, init, rs, ws, dest, SRC_EU_RESULT) \ + | BSP_FLD32(1, 0, 3)) + +#define FUNC_LOAD_ACC 0 +#define FUNC_UNLOAD_ACC 1 +#define FUNC_AND 2 +#define FUNC_OR 3 +#define FUNC_XOR 4 +#define FUNC_ANDN 5 +#define FUNC_NOT 6 +#define FUNC_ADD 7 +#define FUNC_SUB 8 +#define FUNC_LSH 9 +#define FUNC_RSH 10 +#define FUNC_CRC8 11 +#define FUNC_CRC16 12 +#define FUNC_CRC32 13 +#define FUNC_ENDIAN32 14 +#define FUNC_ENDIAN16 15 + +#define DRD2A(flags, func) \ + (BSP_BIT32(30) | BSP_BIT32(29) \ + | DRD_FLAGS(flags) \ + | BSP_FLD32(func, 0, 3)) + +#define DRD2A5(flags, init, func, ws, rs) \ + (DRD2A(flags, func) \ + | DRD_RS(rs) \ + | DRD_WS(ws) \ + | DRD_INIT(init)) + +#define OP_VAR(val) (val) +#define OP_EU_RESULT (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(1) | BSP_BIT32(0)) +#define OP_NONE (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0)) +#define OP_IDX(val) (BSP_BIT32(5) | (val)) +#define OP_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val)) + +#define DRD2B1(dest, op0, op1) \ + (BSP_FLD32(dest, 22, 27) \ + | BSP_FLD32(SRC_EU_RESULT, 14, 20) \ + | BSP_FLD32(3, 12, 13) \ + | BSP_FLD32(op0, 6, 11) \ + | BSP_FLD32(op1, 0, 5)) + +#define DRD2B2(op0, op1) \ + (BSP_BIT32(29) \ + | BSP_FLD32(3, 26, 27) \ + | BSP_FLD32(op0, 20, 25) \ + | BSP_FLD32(op1, 14, 19) \ + | BSP_FLD32(0, 12, 13) \ + | BSP_FLD32(OP_NONE, 6, 11) \ + | BSP_FLD32(OP_NONE, 0, 5)) + +#define NOP 0x1f8 + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* BESTCOMM_OPS_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/i2c.h b/bsps/powerpc/gen5200/include/bsp/i2c.h new file mode 100644 index 0000000000..e5d7d472dd --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/i2c.h @@ -0,0 +1,243 @@ +/* + * Generic I2C bus interface for RTEMS + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __RTEMS__I2C_H__ +#define __RTEMS__I2C_H__ + +#include <rtems.h> +#include <bsp.h> +/* This header file define the generic interface to i2c buses available in + * system. This interface may be used by user applications or i2c-device + * drivers (like RTC, NVRAM, etc). + * + * Functions i2c_initialize and i2c_transfer declared in this header usually + * implemented in particular board support package. Usually this + * implementation is a simple wrapper or multiplexor to I2C controller + * driver which is available in system. It may be generic "software + * controller" I2C driver which control SDA and SCL signals directly (if SDA + * and SCL is general-purpose I/O pins), or driver for hardware I2C + * controller (standalone or integrated with processors: MBus controller in + * ColdFire processors, I2C controller in PowerQUICC and so on). + * + * i2c_transfer is a very generic low-level function. Higher-level function + * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too. + */ + +/* I2C Bus Number type */ +typedef uint32_t i2c_bus_number; + +/* I2C device address */ +typedef uint16_t i2c_address; + +/* I2C error codes generated during message transfer */ +typedef enum i2c_message_status { + I2C_SUCCESSFUL = 0, + I2C_TIMEOUT, + I2C_NO_DEVICE, + I2C_ARBITRATION_LOST, + I2C_NO_ACKNOWLEDGE, + I2C_NO_DATA, + I2C_RESOURCE_NOT_AVAILABLE +} i2c_message_status; + +/* I2C Message */ +typedef struct i2c_message { + i2c_address addr; /* I2C slave device address */ + uint16_t flags; /* message flags (see below) */ + i2c_message_status status; /* message transfer status code */ + uint16_t len; /* Number of bytes to read or write */ + uint8_t *buf; /* pointer to data array */ +} i2c_message; + +/* I2C message flag */ +#define I2C_MSG_ADDR_10 (0x01) /* 10-bit address */ +#define I2C_MSG_WR (0x02) /* transfer direction for this message + from master to slave */ +#define I2C_MSG_ERRSKIP (0x04) /* Skip message if last transfered message + is failed */ +/* Type for function which is called when transfer over I2C bus is finished */ +typedef void (*i2c_transfer_done) (void * arg); + +/* i2c_initialize -- + * I2C driver initialization. This function usually called on device + * driver initialization state, before initialization task. All I2C + * buses are initialized; reasonable slow data transfer rate is + * selected for each bus. + * + * PARAMETERS: + * major - I2C device major number + * minor - I2C device minor number + * arg - RTEMS driver initialization argument + * + * RETURNS: + * RTEMS status code + */ +rtems_device_driver +i2c_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* i2c_select_clock_rate -- + * select I2C bus clock rate for specified bus. Some bus controller do not + * allow to select arbitrary clock rate; in this case nearest possible + * slower clock rate is selected. + * + * PARAMETERS: + * bus - I2C bus number + * bps - data transfer rate for this bytes in bits per second + * + * RETURNS: + * RTEMS_SUCCESSFUL, if operation performed successfully, + * RTEMS_INVALID_NUMBER, if wrong bus number is specified, + * RTEMS_UNSATISFIED, if bus do not support data transfer rate selection + * or specified data transfer rate could not be used. + */ +rtems_status_code +i2c_select_clock_rate(i2c_bus_number bus, int bps); + +/* i2c_transfer -- + * Initiate multiple-messages transfer over specified I2C bus or + * put request into queue if bus or some other resource is busy. (This + * is non-blocking function). + * + * PARAMETERS: + * bus - I2C bus number + * nmsg - number of messages + * msg - pointer to messages array + * done - function which is called when transfer is finished + * done_arg_ptr - arbitrary argument ptr passed to done funciton + * + * RETURNS: + * RTEMS_SUCCESSFUL if transfer initiated successfully, or error + * code if something failed. + */ +rtems_status_code +i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg, + i2c_transfer_done done, void *done_arg); + +/* i2c_transfer_wait -- + * Initiate I2C bus transfer and block until this transfer will be + * finished. This function wait the semaphore if system in + * SYSTEM_STATE_UP state, or poll done flag in other states. + * + * PARAMETERS: + * bus - I2C bus number + * msg - pointer to transfer messages array + * nmsg - number of messages in transfer + * + * RETURNS: + * I2C_SUCCESSFUL, if tranfer finished successfully, + * I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed, + * value of status field of first error-finished message in transfer, + * if something wrong. + */ +i2c_message_status +i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg); + +/* i2c_poll -- + * Poll I2C bus controller for events and hanle it. This function is + * used when I2C driver operates in poll-driven mode. + * + * PARAMETERS: + * bus - bus number to be polled + * + * RETURNS: + * none + */ +void +i2c_poll(i2c_bus_number bus); + +/* i2c_write -- + * Send single message over specified I2C bus to addressed device and + * wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - data to be sent to device + * size - data buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrbyte -- + * Send single one-byte long message over specified I2C bus to + * addressed device and wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - byte message to be sent to device + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t cmd); + +/* i2c_read -- + * receive single message over specified I2C bus from addressed device. + * This call will wait while transfer is finished. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * buf - buffer for received message + * size - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size); + +/* i2c_wrrd -- + * Send message over I2C bus to specified device and receive message + * from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * bufw - data to be sent to device + * sizew - send data buffer size + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew, + void *bufr, int sizer); + +/* i2c_wbrd -- + * Send one-byte message over I2C bus to specified device and receive + * message from the same device during single transfer. + * + * PARAMETERS: + * bus - I2C bus number + * addr - address of I2C device + * cmd - one-byte message to be sent over I2C bus + * bufr - buffer for received message + * sizer - receive buffer size + * + * RETURNS: + * transfer status + */ +i2c_message_status +i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t cmd, + void *bufr, int sizer); + +#endif diff --git a/bsps/powerpc/gen5200/include/bsp/i2cdrv.h b/bsps/powerpc/gen5200/include/bsp/i2cdrv.h new file mode 100644 index 0000000000..4b4a1ec141 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/i2cdrv.h @@ -0,0 +1,35 @@ +/* + * i2cdrv.h -- I2C bus driver prototype and definitions + * + * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia + * Author: Victor V. Vengerov <vvv@oktet.ru> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __I2CDRV_H__ +#define __I2CDRV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_DRIVER_TABLE_ENTRY \ + { i2cdrv_initialize, NULL, NULL, NULL, NULL, NULL } + +/* i2cdrv_initialize -- + * I2C driver initialization (rtems I/O driver primitive) + */ +rtems_device_driver +i2cdrv_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __I2CDRV_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/irq.h b/bsps/powerpc/gen5200/include/bsp/irq.h new file mode 100644 index 0000000000..5a0b3bd29e --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/irq.h @@ -0,0 +1,212 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005, 2010 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains declarations for the irq controller handler | +\*===============================================================*/ +/***********************************************************************/ +/* */ +/* Module: irq.h */ +/* Date: 07/17/2003 */ +/* Purpose: RTEMS MPC5x00 CPU interrupt header file */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Description: This include file describe the data structure and */ +/* the functions implemented by rtems to write */ +/* interrupt handlers. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Code */ +/* References: MPC8260ads CPU interrupt header file */ +/* Module: irq.h */ +/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ +/* Version 1.1 */ +/* Date: 10/10/2002 */ +/* */ +/* Author(s) / Copyright(s): */ +/* */ +/* Copyright (C) 1999 valette@crf.canon.fr */ +/* */ +/* This code is heavilly inspired by the public specification of */ +/* STREAM V2 that can be found at: */ +/* */ +/* <http://www.chorus.com/Documentation/index.html> by following */ +/* the STREAM API Specification Document link. */ +/* */ +/* Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> */ +/* Surrey Satellite Technology Limited */ +/* The interrupt handling on the mpc8260 seems quite different from */ +/* the 860 (I don't know the 860 well). Although some interrupts */ +/* are routed via the CPM irq and some are direct to the SIU they */ +/* all appear logically the same.Therefore I removed the distinction */ +/* between SIU and CPM interrupts. */ +/* */ +/* The license and distribution terms for this file may be */ +/* found in the file LICENSE in this distribution or at */ +/* http://www.rtems.org/license/LICENSE. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Partially based on the code references which are named above. */ +/* Adaptions, modifications, enhancements and any recent parts of */ +/* the code are under the right of */ +/* */ +/* IPR Engineering, Dachauer Straße 38, D-80335 München */ +/* Copyright(C) 2003 */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* IPR Engineering makes no representation or warranties with */ +/* respect to the performance of this computer program, and */ +/* specifically disclaims any responsibility for any damages, */ +/* special or consequential, connected with the use of this program. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Version history: 1.0 */ +/* */ +/***********************************************************************/ + +#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H +#define LIBBSP_POWERPC_GEN5200_IRQ_H + +#define PMCE_CE_SHADOW (1U << (31 - 31)) +#define PMCE_CSE_STICKY (1U << (31 - 21)) +#define PMCE_MSE_STICKY (1U << (31 - 10)) +#define PMCE_PSE_STICKY (1U << (31 - 2)) +#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U) +#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU) +#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU) + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_PER_IRQ_NUMBER 22 +#define BSP_PER_IRQ_LOWEST_OFFSET 0 +#define BSP_PER_IRQ_MAX_OFFSET \ + (BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */ +/* + * Main IRQ handlers related definitions + */ +#define BSP_MAIN_IRQ_NUMBER 17 +#define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */ +#define BSP_MAIN_IRQ_MAX_OFFSET \ + (BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */ +/* + * Critical IRQ handlers related definitions + */ +#define BSP_CRIT_IRQ_NUMBER 4 +#define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */ +#define BSP_CRIT_IRQ_MAX_OFFSET \ + (BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */ +/* + * Summary of SIU interrupts + */ +#define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */ +#define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ +#define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */ +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */ +#define BSP_PROCESSOR_IRQ_MAX_OFFSET \ + (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */ +/* + * Summary + */ +#define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */ +#define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */ + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ +typedef enum { + BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3, + BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4, + BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5, + BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6, + BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7, + BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8, + BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9, + BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10, + BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11, + BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12, + BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13, + BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14, + BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15, + BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16, + BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17, + BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18, + BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19, + BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20, + BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21, + + /* SL_TIMER1 -- handler entry only used in case of SMI */ + BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3, + /* LO_INT -- handler entry never used (only placeholder) */ + BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4, + BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5, + BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6, + BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7, + BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8, + BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9, + BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10, + BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12, + BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13, + BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14, + BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15, + BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16, + + BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1, + /* HI_INT -- handler entry never used (only placeholder) */ + BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3, + + BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 +} rtems_irq_symbolic_name; + +#define BSP_CRIT_IRQ_PRIO_LEVELS 4 +#define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6 + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +#endif + +#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/mpc5200.h b/bsps/powerpc/gen5200/include/bsp/mpc5200.h new file mode 100644 index 0000000000..263e66fb9e --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/mpc5200.h @@ -0,0 +1,1369 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains definitions for the mpc5200 hw registers | +\*===============================================================*/ + +#ifndef __MPC5200_h__ +#define __MPC5200_h__ + +/* Additional Harpo Core SPR definitions (603le only) */ +#define CSRR0 58 /* Critical Interrupt SRR0 */ +#define CSRR1 59 /* Critical Interrupt SRR1 */ +#define DABR2 1000 /* Data Address Breakpoint #2 */ +#define DBCR 1001 /* Data Address Breakpoint Control */ +#define IBCR 1002 /* Instruction Breakpoint Control */ +#define IABR2 1018 /* Instruction Breakpoint #2 */ + +/* + * Initial post-reset location of MGT5100 module base address register (MBAR) + */ +#define MBAR_RESET 0x80000000 + +/* + * Location and size of onchip SRAM (relative to MBAR) + */ +#define ONCHIP_SRAM_OFFSET 0x8000 +#define ONCHIP_SRAM_SIZE 0x4000 + +#ifndef ASM +#include <rtems.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define MPC5200_CAN_NO 2 +#define MPC5200_PSC_NO 6 + /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap + * from PSC5, therefore we instantiate seven(!) PSC register sets + */ +#define MPC5200_PSC_REG_SETS 7 + +#define MPC5200_GPT_NO 8 +#define MPC5200_SLT_NO 2 + +/* + * Bit fields for FEC interrupts, ievent and imask above. + */ +#define FEC_INTR_HBERR 0x80000000 /* heartbeat error */ +#define FEC_INTR_BABR 0x40000000 /* babbling receive error */ +#define FEC_INTR_BABT 0x20000000 /* babbling transmit error */ +#define FEC_INTR_GRA 0x10000000 /* graceful stop complete */ +#define FEC_INTR_TFINT 0x08000000 /* transmit frame interrupt */ +/* 0x04000000 reserved */ +/* 0x02000000 reserved */ +/* 0x01000000 reserved */ +#define FEC_INTR_MII 0x00800000 /* MII interrupt */ +/* 0x00400000 reserved */ +#define FEC_INTR_LATE_COL 0x00200000 /* late collision */ +#define FEC_INTR_COL_RETRY 0x00100000 /* collision retry limit */ +#define FEC_INTR_XFIFO_UN 0x00080000 /* transmit FIFO error */ +#define FEC_INTR_XFIFO_ERR 0x00040000 /* transmit FIFO error */ +#define FEC_INTR_RFIFO_ERR 0x00020000 /* receive FIFO error */ +/* 0x00010000 reserved */ +/* 0x0000ffff reserved */ +#define FEC_INTR_HBEEN FEC_INTR_HBERR +#define FEC_INTR_BREN FEC_INTR_BABR +#define FEC_INTR_BTEN FEC_INTR_BABT +#define FEC_INTR_GRAEN FEC_INTR_GRA +#define FEC_INTR_TFINTEN FEC_INTR_TFINT +#define FEC_INTR_MIIEN FEC_INTR_MII +#define FEC_INTR_LCEN FEC_INTR_LATE_COL +#define FEC_INTR_CRLEN FEC_INTR_COL_RETRY +#define FEC_INTR_XFUNEN FEC_INTR_XFIFO_UN +#define FEC_INTR_XFERREN FEC_INTR_XFIFO_ERR +#define FEC_INTR_RFERREN FEC_INTR_RFIFO_ERR +#define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */ +#define FEC_INTR_MASK_ALL 0x00000000 /* mask all interrupt events */ + +/* + * Bit fields for FEC ethernet control, ecntrl above. + */ +#define FEC_ECNTRL_TAG 0xf0000000 /* TBUS tag bits */ +/* 0x08000000 reserved */ +#define FEC_ECNTRL_TESTMD 0x04000000 /* test mode */ +/* 0x03fffff8 reserved */ +#define FEC_ECNTRL_OE 0x00000004 /* FEC output enable */ +#define FEC_ECNTRL_EN 0x00000002 /* ethernet enable */ +#define FEC_ECNTRL_RESET 0x00000001 /* ethernet controller reset */ + +/* + * Bit fields for FEC receive control, r_cntrl above. + */ +/* 0xf1000000 reserved */ +#define FEC_RCNTRL_MAX_FL 0x07ff0000 /* maximum frame length */ +#define FEC_RCNTRL_MAX_FL_SHIFT 16 +/* 0x0000ffc0 reserved */ +#define FEC_RCNTRL_FCE 0x00000020 /* flow control enable */ +#define FEC_RCNTRL_BC_REJ 0x00000010 /* broadcast frame reject */ +#define FEC_RCNTRL_PROM 0x00000008 /* promiscuous mode */ +#define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */ +#define FEC_RCNTRL_DRT 0x00000002 /* disable receive on transmit */ +#define FEC_RCNTRL_LOOP 0x00000001 /* internal loopback */ + +/* + * Bit fields for FEC transmit control, x_cntrl above. + */ +/* 0xffffffe0 reserved */ +#define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */ +#define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame */ +#define FEC_XCNTRL_FDEN 0x00000004 /* full duplex enable */ +#define FEC_XCNTRL_HBC 0x00000002 /* heartbeat control */ +#define FEC_XCNTRL_GTS 0x00000001 /* graceful transmit stop */ + +/* + * Bit fields for FEC transmit status, x_status above. + */ +/* 0xfc000000 reserved */ +#define FEC_XSTAT_DEF 0x02000000 /* defer */ +#define FEC_XSTAT_HB 0x01000000 /* heartbeat error */ +#define FEC_XSTAT_LC 0x00800000 /* late collision */ +#define FEC_XSTAT_RL 0x00400000 /* retry limit */ +#define FEC_XSTAT_RC 0x003c0000 /* retry count */ +#define FEC_XSTAT_UN 0x00020000 /* underrun */ +#define FEX_XSTAT_CSL 0x00010000 /* carrier sense lost */ +/* 0x0000ffff reserved */ + +/* + * Bit fields for FEC transmit FIFO watermark, x_wmrk above. + */ +#define FEC_XWMRK_64 0x00000000 /* 64 bytes written to TxFIFO */ +#define FEC_XWMRK_128 0x00000001 /* 128 bytes written to TxFIFO */ +#define FEC_XWMRK_192 0x00000002 /* 192 bytes written to TxFIFO */ +#define FEC_XWMRK_256 0x00000003 /* 256 bytes written to TxFIFO */ +#define FEC_XWMRK_320 0x00000004 /* 320 bytes written to TxFIFO */ +#define FEC_XWMRK_384 0x00000005 /* 384 bytes written to TxFIFO */ +#define FEC_XWMRK_448 0x00000006 /* 448 bytes written to TxFIFO */ +#define FEC_XWMRK_512 0x00000007 /* 512 bytes written to TxFIFO */ +#define FEC_XWMRK_576 0x00000008 /* 576 bytes written to TxFIFO */ +#define FEC_XWMRK_640 0x00000009 /* 640 bytes written to TxFIFO */ +#define FEC_XWMRK_704 0x0000000a /* 704 bytes written to TxFIFO */ +#define FEC_XWMRK_768 0x0000000b /* 768 bytes written to TxFIFO */ +#define FEC_XWMRK_832 0x0000000c /* 832 bytes written to TxFIFO */ +#define FEC_XWMRK_896 0x0000000d /* 896 bytes written to TxFIFO */ +#define FEC_XWMRK_960 0x0000000e /* 960 bytes written to TxFIFO */ +#define FEC_XWMRK_1024 0x0000000f /* 1024 bytes written to TxFIFO */ + +/* + * Bit fields for FEC transmit finite state machine. + */ +/* 0xfc000000 reserved */ +#define FEC_FSM_CRC 0x02000000 /* append CRC (typical use) */ +#define FEC_FSM_ENFSM 0x01000000 /* enable CRC FSM (typical use) */ +/* 0x00ffffff reserved */ + +/* + * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status + * and tfifo_cntrl. + */ +#define FEC_FIFO_STAT_IP 0x80000000 /* illegal pointer, sticky */ +/* 0x70000000 reserved */ +#define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */ +#define FEC_FIFO_STAT_FAE 0x00800000 /* frame accept error */ +#define FEC_FIFO_STAT_RXW 0x00400000 /* receive wait condition */ +#define FEC_FIFO_STAT_UF 0x00200000 /* underflow */ +#define FEC_FIFO_STAT_OF 0x00100000 /* overflow */ +#define FEC_FIFO_STAT_FR 0x00080000 /* frame ready, read-only */ +#define FEC_FIFO_STAT_FULL 0x00040000 /* full alarm, read-only */ +#define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm */ +#define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */ +/* 0x0000ffff reserved */ +#define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP \ + | FEC_FIFO_STAT_FAE \ + | FEC_FIFO_STAT_RXW \ + | FEC_FIFO_STAT_UF \ + | FEC_FIFO_STAT_OF \ + ) + +/* 0x80000000 reserved */ +#define FEC_FIFO_CNTRL_WCTL 0x40000000 /* write control */ +#define FEC_FIFO_CNTRL_WFR 0x20000000 /* write frame */ +/* 0x10000000 reserved */ +#define FEC_FIFO_CNTRL_FRAME 0x08000000 /* frame mode enable */ +#define FEC_FIFO_CNTRL_GR 0x07000000 /* last transfer granularity */ +#define FEC_FIFO_CNTRL_GR_SHIFT 24 +#define FEC_FIFO_CNTRL_IP_MASK 0x00800000 /* illegal pointer mask */ +#define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask */ +#define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask */ +#define FEC_FIFO_CNTRL_UF_MASK 0x00100000 /* underflow mask */ +#define FEC_FIFO_CNTRL_OF_MASK 0x00080000 /* overflow mask */ +/* 0x0007ffff reserved */ + +#define SDMA_TCR_EN BSP_BBIT16(0) +#define SDMA_TCR_VAL BSP_BBIT16(1) +#define SDMA_TCR_ALW_INIT BSP_BBIT16(2) +#define SDMA_TCR_IN(val) BSP_BFLD16(val, 3, 7) +#define SDMA_TCR_AUTO_START BSP_BBIT16(8) +#define SDMA_TCR_HIGH_EN BSP_BBIT16(9) +#define SDMA_TCR_HOLD BSP_BBIT16(10) +#define SDMA_TCR_AS(val) BSP_BFLD16(val, 12, 15) + +#define SDMA_IPR_HOLD BSP_BBIT8(0) +#define SDMA_IPR_PRIOR(val) BSP_BFLD8(val, 5, 7) + +#define SDMA_REQMUX_SET_31(reg, val) BSP_BFLD32SET(reg, val, 0, 1) +#define SDMA_REQMUX_SET_30(reg, val) BSP_BFLD32SET(reg, val, 2, 3) +#define SDMA_REQMUX_SET_29(reg, val) BSP_BFLD32SET(reg, val, 4, 5) +#define SDMA_REQMUX_SET_28(reg, val) BSP_BFLD32SET(reg, val, 6, 7) +#define SDMA_REQMUX_SET_27(reg, val) BSP_BFLD32SET(reg, val, 8, 9) +#define SDMA_REQMUX_SET_26(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define SDMA_REQMUX_SET_25(reg, val) BSP_BFLD32SET(reg, val, 12, 13) +#define SDMA_REQMUX_SET_24(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define SDMA_REQMUX_SET_23(reg, val) BSP_BFLD32SET(reg, val, 16, 17) +#define SDMA_REQMUX_SET_22(reg, val) BSP_BFLD32SET(reg, val, 18, 19) +#define SDMA_REQMUX_SET_21(reg, val) BSP_BFLD32SET(reg, val, 20, 21) +#define SDMA_REQMUX_SET_20(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define SDMA_REQMUX_SET_19(reg, val) BSP_BFLD32SET(reg, val, 24, 25) +#define SDMA_REQMUX_SET_18(reg, val) BSP_BFLD32SET(reg, val, 26, 27) +#define SDMA_REQMUX_SET_17(reg, val) BSP_BFLD32SET(reg, val, 28, 29) +#define SDMA_REQMUX_SET_16(reg, val) BSP_BFLD32SET(reg, val, 30, 31) + +/* SDMA / BestComm */ +typedef struct { + uint32_t taskBar; + uint32_t currentPointer; + uint32_t endPointer; + uint32_t variablePointer; + uint8_t IntVect1; + uint8_t IntVect2; + uint16_t PtdCntrl; + uint32_t IntPend; + uint32_t IntMask; + uint16_t tcr [16]; + uint8_t ipr [32]; + uint32_t cReqSelect; + uint32_t task_size0; + uint32_t task_size1; + uint32_t reserved_0; + uint32_t reserved_1; + uint32_t Value1; + uint32_t Value2; + uint32_t Control; + uint32_t Status; +} mpc5200_sdma; + +typedef struct { +#define CSC_CFG_WAITP(val) BSP_BFLD32(val, 0, 7) +#define CSC_CFG_WAITX(val) BSP_BFLD32(val, 8, 15) +#define CSC_CFG_MX BSP_BBIT32(16) +#define CSC_CFG_AA BSP_BBIT32(18) +#define CSC_CFG_CE BSP_BBIT32(19) +#define CSC_CFG_AS(val) BSP_BFLD32(val, 20, 21) +#define CSC_CFG_DS(val) BSP_BFLD32(val, 22, 23) +#define CSC_CFG_BANK(val) BSP_BFLD32(val, 24, 25) +#define CSC_CFG_WTYP(val) BSP_BFLD32(val, 26, 27) +#define CSC_CFG_WS BSP_BBIT32(28) +#define CSC_CFG_RS BSP_BBIT32(29) +#define CSC_CFG_WO BSP_BBIT32(30) +#define CSC_CFG_RO BSP_BBIT32(31) + uint32_t config_0; + uint32_t config_1; + uint32_t config_2; + uint32_t config_3; + uint32_t config_4; + uint32_t config_5; + +#define CSC_CTRL_ME BSP_BBIT32(7) + uint32_t control; + +#define CSC_STAT_WOERR BSP_BBIT32(2) +#define CSC_STAT_ROERR BSP_BBIT32(3) +#define CSC_STAT_GET_CSXERR(reg) BSP_BFLD32GET(reg, 5, 7) + uint32_t status; + + uint32_t config_6; + uint32_t config_7; + +#define CSC_BST_CTRL_CW7 BSP_BBIT32(0) +#define CSC_BST_CTRL_SLB7 BSP_BBIT32(1) +#define CSC_BST_CTRL_BRE7 BSP_BBIT32(3) +#define CSC_BST_CTRL_CW6 BSP_BBIT32(4) +#define CSC_BST_CTRL_SLB6 BSP_BBIT32(5) +#define CSC_BST_CTRL_BRE6 BSP_BBIT32(7) +#define CSC_BST_CTRL_CW5 BSP_BBIT32(8) +#define CSC_BST_CTRL_SLB5 BSP_BBIT32(9) +#define CSC_BST_CTRL_BRE5 BSP_BBIT32(11) +#define CSC_BST_CTRL_CW4 BSP_BBIT32(12) +#define CSC_BST_CTRL_SLB4 BSP_BBIT32(13) +#define CSC_BST_CTRL_BRE4 BSP_BBIT32(15) +#define CSC_BST_CTRL_CW3 BSP_BBIT32(16) +#define CSC_BST_CTRL_SLB3 BSP_BBIT32(17) +#define CSC_BST_CTRL_BRE3 BSP_BBIT32(19) +#define CSC_BST_CTRL_CW2 BSP_BBIT32(20) +#define CSC_BST_CTRL_SLB2 BSP_BBIT32(21) +#define CSC_BST_CTRL_BRE2 BSP_BBIT32(23) +#define CSC_BST_CTRL_CW1 BSP_BBIT32(24) +#define CSC_BST_CTRL_SLB1 BSP_BBIT32(25) +#define CSC_BST_CTRL_BRE1 BSP_BBIT32(27) +#define CSC_BST_CTRL_CW0 BSP_BBIT32(28) +#define CSC_BST_CTRL_SLB0 BSP_BBIT32(29) +#define CSC_BST_CTRL_BRE0 BSP_BBIT32(31) + uint32_t burst_control; + +#define CSC_DCYC_CTRL_DC7(val) BSP_BFLD32(val, 2, 3) +#define CSC_DCYC_CTRL_SET_DC7(reg, val) BSP_BFLD32SET(reg, val, 2, 3) +#define CSC_DCYC_CTRL_DC6(val) BSP_BFLD32(val, 6, 7) +#define CSC_DCYC_CTRL_SET_DC6(reg, val) BSP_BFLD32SET(reg, val, 6, 7) +#define CSC_DCYC_CTRL_DC5(val) BSP_BFLD32(val, 10, 11) +#define CSC_DCYC_CTRL_SET_DC5(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define CSC_DCYC_CTRL_DC4(val) BSP_BFLD32(val, 14, 15) +#define CSC_DCYC_CTRL_SET_DC4(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define CSC_DCYC_CTRL_DC3(val) BSP_BFLD32(val, 18, 19) +#define CSC_DCYC_CTRL_SET_DC3(reg, val) BSP_BFLD32SET(reg, val, 18, 19) +#define CSC_DCYC_CTRL_DC2(val) BSP_BFLD32(val, 22, 23) +#define CSC_DCYC_CTRL_SET_DC2(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define CSC_DCYC_CTRL_DC1(val) BSP_BFLD32(val, 26, 27) +#define CSC_DCYC_CTRL_SET_DC1(reg, val) BSP_BFLD32SET(reg, val, 26, 27) +#define CSC_DCYC_CTRL_DC0(val) BSP_BFLD32(val, 30, 31) +#define CSC_DCYC_CTRL_SET_DC0(reg, val) BSP_BFLD32SET(reg, val, 30, 31) + uint32_t deadcycle_control; + + uint8_t reserved [208]; +} mpc5200_csc; + +typedef struct { + uint32_t memory_address_base; + uint32_t cs0_start_address; + uint32_t cs0_stop_address; + uint32_t cs1_start_address; + uint32_t cs1_stop_address; + uint32_t cs2_start_address; + uint32_t cs2_stop_address; + uint32_t cs3_start_address; + uint32_t cs3_stop_address; + uint32_t cs4_start_address; + uint32_t cs4_stop_address; + uint32_t cs5_start_address; + uint32_t cs5_stop_address; + uint32_t sdram_chip_select_0; + uint32_t sdram_chip_select_1; + uint8_t reserved_0 [16]; + uint32_t boot_start_address; + uint32_t boot_stop_address; + +#define MM_IPBI_CTRL_CS7ENA BSP_BBIT16(4) +#define MM_IPBI_CTRL_CS6ENA BSP_BBIT16(5) +#define MM_IPBI_CTRL_BOOTENA BSP_BBIT16(6) +#define MM_IPBI_CTRL_CS5ENA BSP_BBIT16(10) +#define MM_IPBI_CTRL_CS4ENA BSP_BBIT16(11) +#define MM_IPBI_CTRL_CS3ENA BSP_BBIT16(12) +#define MM_IPBI_CTRL_CS2ENA BSP_BBIT16(13) +#define MM_IPBI_CTRL_CS1ENA BSP_BBIT16(14) +#define MM_IPBI_CTRL_CS0ENA BSP_BBIT16(15) + uint16_t ipbi_control; + + uint16_t wait_state_enable; + uint32_t cs6_start_address; + uint32_t cs6_stop_address; + uint32_t cs7_start_address; + uint32_t cs7_stop_address; + uint8_t reserved_1 [152]; +} mpc5200_mm; + +/* +************************************************************************* +* MPC5x00 internal register memory map * +************************************************************************* +*/ +typedef struct mpc5200_ { + /* + * memory map registers (MBAR + 0) + */ + volatile mpc5200_mm mm; + + /* + * SDRAM memory controller registers (MBAR + 0x100) + */ + volatile uint8_t mc[0x100]; + + /* + * clock distribution module registers (MBAR + 0x200) + */ + volatile uint8_t cdm[0x100]; + + /* + * chip selct controller registers(MBAR + 0x300) + */ + volatile mpc5200_csc csc; + + /* + * SmartComm timer registers (MBAR + 0x400) + */ + volatile uint8_t sct[0x100]; + + /* + * interrupt controller registers (MBAR + 0x500) + */ + volatile uint32_t per_mask; /* + 0x00 */ + volatile uint32_t per_pri_1; /* + 0x04 */ + volatile uint32_t per_pri_2; /* + 0x08 */ + volatile uint32_t per_pri_3; /* + 0x0C */ + +#define ICTL_EET_ECLR0 BSP_BBIT32(4) +#define ICTL_EET_ECLR1 BSP_BBIT32(5) +#define ICTL_EET_ECLR2 BSP_BBIT32(6) +#define ICTL_EET_ECLR3 BSP_BBIT32(7) +#define ICTL_EET_ETYPE0(val) BSP_BFLD32(val, 8, 9) +#define ICTL_EET_ETYPE1(val) BSP_BFLD32(val, 10, 11) +#define ICTL_EET_ETYPE2(val) BSP_BFLD32(val, 12, 13) +#define ICTL_EET_ETYPE3(val) BSP_BFLD32(val, 14, 15) +#define ICTL_EET_SET_ETYPE0(reg, val) BSP_BFLD32SET(reg, val, 8, 9) +#define ICTL_EET_SET_ETYPE1(reg, val) BSP_BFLD32SET(reg, val, 10, 11) +#define ICTL_EET_SET_ETYPE2(reg, val) BSP_BFLD32SET(reg, val, 12, 13) +#define ICTL_EET_SET_ETYPE3(reg, val) BSP_BFLD32SET(reg, val, 14, 15) +#define ICTL_EET_MEE BSP_BBIT32(19) +#define ICTL_EET_EENA0 BSP_BBIT32(20) +#define ICTL_EET_EENA1 BSP_BBIT32(21) +#define ICTL_EET_EENA2 BSP_BBIT32(22) +#define ICTL_EET_EENA3 BSP_BBIT32(23) +#define ICTL_EET_CEB BSP_BBIT32(31) + + volatile uint32_t ext_en_type; /* + 0x10 */ + volatile uint32_t crit_pri_main_mask;/* + 0x14 */ + volatile uint32_t main_pri_1; /* + 0x18 */ + volatile uint32_t main_pri_2; /* + 0x1C */ + volatile uint32_t res1; /* + 0x20 */ + volatile uint32_t pmce; /* + 0x24 */ + volatile uint32_t csa; /* + 0x28 */ + volatile uint32_t msa; /* + 0x2C */ + volatile uint32_t psa; /* + 0x30 */ + volatile uint32_t res2; /* + 0x34 */ + volatile uint32_t psa_be; /* + 0x38 */ + volatile uint8_t res3[0xC4]; /* + 0x3C */ + + /* + * general pupose timer registers (MBAR + 0x600/+ 0x610/+ 0x620/+ 0x630/+ 0x640/+ 0x650/+ 0x660/+ 0x670) + */ + struct mpc5200_gpt { + volatile uint32_t emsel; /* + 0x00 */ + volatile uint32_t count_in; /* + 0x04 */ + volatile uint32_t pwm_conf; /* + 0x08 */ + volatile uint32_t status; /* + 0x0C */ + } gpt[MPC5200_GPT_NO]; + +#define GPT_STATUS_RESET 0x0000000F +#define GPT_STATUS_TEXP (1 << 3) +#define GPT_STATUS_PIN (1 << 8) +#define GPT_EMSEL_GPIO_DIR (2 << 4) +#define GPT_EMSEL_GPIO_OUT (1 << 4) +#define GPT_EMSEL_GPIO_OUT_HIGH (3 << 4) +#define GPT_EMSEL_TIMER_MS_GPIO (4 << 0) +#define GPT_EMSEL_GPIO_IN (0 << 0) +#define GPT_EMSEL_CE (1 << 12) +#define GPT_EMSEL_ST_CONT (1 << 10) +#define GPT_EMSEL_INTEN (1 << 8) +#define GPT_EMSEL_WDEN (1 << 15) + +#define GPT0 0 +#define GPT1 1 +#define GPT2 2 +#define GPT3 3 +#define GPT4 4 +#define GPT5 5 +#define GPT6 6 +#define GPT7 7 + + volatile uint8_t gpt_res[0x80]; + + /* + * slice time registers (MBAR + 0x700/+ 0x710) + */ + struct mpc5200_slt { + volatile uint32_t tcr; /* + 0x00 */ + volatile uint32_t cntrl; /* + 0x04 */ + volatile uint32_t cvr; /* + 0x08 */ + volatile uint32_t tsr; /* + 0x0C */ + } slt[MPC5200_SLT_NO]; + + volatile uint8_t slt_res[0xE0]; + + /* + * real time clock registers (MBAR + 0x800) + */ + volatile uint8_t rtc[0x100]; + + + /* + * MSCAN registers (MBAR + 0x900 /+ 0x980) + */ + struct mpc5200_mscan { + volatile uint8_t ctl0; /* + 0x0 */ + volatile uint8_t ctl1; /* + 0x1 */ + volatile uint8_t res1; /* + 0x2 */ + volatile uint8_t res2; /* + 0x3 */ + volatile uint8_t btr0; /* + 0x4 */ + volatile uint8_t btr1; /* + 0x5 */ + volatile uint8_t res3; /* + 0x6 */ + volatile uint8_t res4; /* + 0x7 */ + volatile uint8_t rflg; /* + 0x8 */ + volatile uint8_t rier; /* + 0x9 */ + volatile uint8_t res5; /* + 0xA */ + volatile uint8_t res6; /* + 0xB */ + volatile uint8_t tflg; /* + 0xC */ + volatile uint8_t tier; /* + 0xD */ + volatile uint8_t res7; /* + 0xE */ + volatile uint8_t res8; /* + 0xF */ + volatile uint8_t tarq; /* + 0x10 */ + volatile uint8_t taak; /* + 0x11 */ + volatile uint8_t res9; /* + 0x12 */ + volatile uint8_t res10; /* + 0x13 */ + volatile uint8_t bsel; /* + 0x14 */ + volatile uint8_t idac; /* + 0x15 */ + volatile uint8_t res11; /* + 0x16 */ + volatile uint8_t res12; /* + 0x17 */ + volatile uint8_t res13; /* + 0x18 */ + volatile uint8_t res14; /* + 0x19 */ + volatile uint8_t res15; /* + 0x1A */ + volatile uint8_t res16; /* + 0x1B */ + volatile uint8_t rxerr; /* + 0x1C */ + volatile uint8_t txerr; /* + 0x1D */ + volatile uint8_t res17; /* + 0x1E */ + volatile uint8_t res18; /* + 0x1F */ + volatile uint8_t idar0; /* + 0x20 */ + volatile uint8_t idar1; /* + 0x21 */ + volatile uint8_t res19; /* + 0x22 */ + volatile uint8_t res20; /* + 0x23 */ + volatile uint8_t idar2; /* + 0x24 */ + volatile uint8_t idar3; /* + 0x25 */ + volatile uint8_t res21; /* + 0x26 */ + volatile uint8_t res22; /* + 0x27 */ + volatile uint8_t idmr0; /* + 0x28 */ + volatile uint8_t idmr1; /* + 0x29 */ + volatile uint8_t res23; /* + 0x2A */ + volatile uint8_t res24; /* + 0x2B */ + volatile uint8_t idmr2; /* + 0x2C */ + volatile uint8_t idmr3; /* + 0x2D */ + volatile uint8_t res25; /* + 0x2E */ + volatile uint8_t res26; /* + 0x2F */ + volatile uint8_t idar4; /* + 0x30 */ + volatile uint8_t idar5; /* + 0x31 */ + volatile uint8_t res27; /* + 0x32 */ + volatile uint8_t res28; /* + 0x33 */ + volatile uint8_t idar6; /* + 0x34 */ + volatile uint8_t idar7; /* + 0x35 */ + volatile uint8_t res29; /* + 0x36 */ + volatile uint8_t res30; /* + 0x37 */ + volatile uint8_t idmr4; /* + 0x38 */ + volatile uint8_t idmr5; /* + 0x39 */ + volatile uint8_t res31; /* + 0x3A */ + volatile uint8_t res32; /* + 0x3B */ + volatile uint8_t idmr6; /* + 0x3C */ + volatile uint8_t idmr7; /* + 0x3D */ + volatile uint8_t res33; /* + 0x3E */ + volatile uint8_t res34; /* + 0x3F */ + volatile uint8_t rxidr0; /* + 0x40 */ + volatile uint8_t rxidr1; /* + 0x41 */ + volatile uint8_t res35; /* + 0x42 */ + volatile uint8_t res36; /* + 0x43 */ + volatile uint8_t rxidr2; /* + 0x44 */ + volatile uint8_t rxidr3; /* + 0x45 */ + volatile uint8_t res37; /* + 0x46 */ + volatile uint8_t res38; /* + 0x47 */ + volatile uint8_t rxdsr0; /* + 0x48 */ + volatile uint8_t rxdsr1; /* + 0x49 */ + volatile uint8_t res39; /* + 0x4A */ + volatile uint8_t res40; /* + 0x4B */ + volatile uint8_t rxdsr2; /* + 0x4C */ + volatile uint8_t rxdsr3; /* + 0x4D */ + volatile uint8_t res41; /* + 0x4E */ + volatile uint8_t res42; /* + 0x4F */ + volatile uint8_t rxdsr4; /* + 0x50 */ + volatile uint8_t rxdsr5; /* + 0x51 */ + volatile uint8_t res43; /* + 0x52 */ + volatile uint8_t res44; /* + 0x53 */ + volatile uint8_t rxdsr6; /* + 0x54 */ + volatile uint8_t rxdsr7; /* + 0x55 */ + volatile uint8_t res45; /* + 0x56 */ + volatile uint8_t res46; /* + 0x57 */ + volatile uint8_t rxdlr; /* + 0x58 */ + volatile uint8_t res47; /* + 0x59 */ + volatile uint8_t res48; /* + 0x5A */ + volatile uint8_t res49; /* + 0x5B */ + volatile uint8_t rxtimh; /* + 0x5C */ + volatile uint8_t rxtiml; /* + 0x5D */ + volatile uint8_t res50; /* + 0x5E */ + volatile uint8_t res51; /* + 0x5F */ + volatile uint8_t txidr0; /* + 0x60 */ + volatile uint8_t txidr1; /* + 0x61 */ + volatile uint8_t res52; /* + 0x62 */ + volatile uint8_t res53; /* + 0x63 */ + volatile uint8_t txidr2; /* + 0x64 */ + volatile uint8_t txidr3; /* + 0x65 */ + volatile uint8_t res54; /* + 0x66 */ + volatile uint8_t res55; /* + 0x67 */ + volatile uint8_t txdsr0; /* + 0x68 */ + volatile uint8_t txdsr1; /* + 0x69 */ + volatile uint8_t res56; /* + 0x6A */ + volatile uint8_t res57; /* + 0x6B */ + volatile uint8_t txdsr2; /* + 0x6C */ + volatile uint8_t txdsr3; /* + 0x6D */ + volatile uint8_t res58; /* + 0x6E */ + volatile uint8_t res59; /* + 0x6F */ + volatile uint8_t txdsr4; /* + 0x70 */ + volatile uint8_t txdsr5; /* + 0x71 */ + volatile uint8_t res60; /* + 0x72 */ + volatile uint8_t res61; /* + 0x73 */ + volatile uint8_t txdsr6; /* + 0x74 */ + volatile uint8_t txdsr7; /* + 0x75 */ + volatile uint8_t res62; /* + 0x76 */ + volatile uint8_t res63; /* + 0x77 */ + volatile uint8_t txdlr; /* + 0x78 */ + volatile uint8_t txtbpr; /* + 0x79 */ + volatile uint8_t res64; /* + 0x7A */ + volatile uint8_t res65; /* + 0x7B */ + volatile uint8_t txtimh; /* + 0x7C */ + volatile uint8_t txtiml; /* + 0x7D */ + volatile uint8_t res66; /* + 0x7E */ + volatile uint8_t res67; /* + 0x7F */ + } mscan[MPC5200_CAN_NO]; + + volatile uint8_t res[0x100]; + + /* + * GPIO standard registers (MBAR + 0xB00) + */ + volatile uint32_t gpiopcr; /* + 0x00 */ + #define GPIO_PCR_CHIP_SELECT_1 0x80000000 + #define GPIO_PCR_CHIP_ALTS 0x30000000 + #define GPIO_PCR_CHIP_ALTS_NONE 0x00000000 + #define GPIO_PCR_CHIP_ALTS_CAN 0x10000000 + #define GPIO_PCR_CHIP_ALTS_SPI 0x20000000 + #define GPIO_PCR_CHIP_ALTS_BOTH 0x30000000 + #define GPIO_PCR_CHIP_SELECT_7 0x08000000 + #define GPIO_PCR_CHIP_SELECT_6 0x04000000 + #define GPIO_PCR_CHIP_SELECT_ATA 0x03000000 + #define GPIO_PCR_CHIP_SELECT_IR_USB_CLK 0x00800000 + #define GPIO_PCR_IRDA 0x00700000 + #define GPIO_PCR_ETHERNET 0x000F0000 + #define GPIO_PCR_PCI_DIS 0x00008000 + #define GPIO_PCR_USB_SE 0x00004000 + #define GPIO_PCR_USB_GPIO 0x00003000 + #define GPIO_PCR_PSC3 0x00000F00 + #define GPIO_PCR_PSC2 0x00000070 + #define GPIO_PCR_PSC1 0x00000007 + + #define GPIO_S_PIN_IR_USB_CLK BSP_BBIT32(2) + #define GPIO_S_PIN_IRDA_TX BSP_BBIT32(3) + #define GPIO_S_PIN_ETH_11 BSP_BBIT32(4) + #define GPIO_S_PIN_ETH_10 BSP_BBIT32(5) + #define GPIO_S_PIN_ETH_9 BSP_BBIT32(6) + #define GPIO_S_PIN_ETH_8 BSP_BBIT32(7) + #define GPIO_S_PIN_USB1_8 BSP_BBIT32(12) + #define GPIO_S_PIN_USB1_7 BSP_BBIT32(13) + #define GPIO_S_PIN_USB1_6 BSP_BBIT32(14) + #define GPIO_S_PIN_USB1_0 BSP_BBIT32(15) + #define GPIO_S_PIN_PSC3_7 BSP_BBIT32(18) + #define GPIO_S_PIN_PSC3_6 BSP_BBIT32(19) + #define GPIO_S_PIN_PSC3_3 BSP_BBIT32(20) + #define GPIO_S_PIN_PSC3_2 BSP_BBIT32(21) + #define GPIO_S_PIN_PSC3_1 BSP_BBIT32(22) + #define GPIO_S_PIN_PSC3_0 BSP_BBIT32(23) + #define GPIO_S_PIN_PSC2_3 BSP_BBIT32(24) + #define GPIO_S_PIN_PSC2_2 BSP_BBIT32(25) + #define GPIO_S_PIN_PSC2_1 BSP_BBIT32(26) + #define GPIO_S_PIN_PSC2_0 BSP_BBIT32(27) + #define GPIO_S_PIN_PSC1_3 BSP_BBIT32(28) + #define GPIO_S_PIN_PSC1_2 BSP_BBIT32(29) + #define GPIO_S_PIN_PSC1_1 BSP_BBIT32(30) + #define GPIO_S_PIN_PSC1_0 BSP_BBIT32(31) + + volatile uint32_t gpiosen; /* + 0x04 */ + volatile uint32_t gpiosod; /* + 0x08 */ + volatile uint32_t gpiosdd; /* + 0x0C */ + volatile uint32_t gpiosdo; /* + 0x10 */ + volatile uint32_t gpiosdi; /* + 0x14 */ + + #define GPIO_O_PIN_ETH_7 BSP_BBIT32(0) + #define GPIO_O_PIN_ETH_6 BSP_BBIT32(1) + #define GPIO_O_PIN_ETH_5 BSP_BBIT32(2) + #define GPIO_O_PIN_ETH_4 BSP_BBIT32(3) + #define GPIO_O_PIN_ETH_3 BSP_BBIT32(4) + #define GPIO_O_PIN_ETH_2 BSP_BBIT32(5) + #define GPIO_O_PIN_ETH_1 BSP_BBIT32(6) + #define GPIO_O_PIN_ETH_0 BSP_BBIT32(7) + #define GPIO_O_PIN_I2C_3 BSP_BBIT32(13) + #define GPIO_O_PIN_I2C_0 BSP_BBIT32(14) + #define GPIO_O_PIN_I2C_1 BSP_BBIT32(15) + + volatile uint32_t gpiooe; /* + 0x18 */ + volatile uint32_t gpioodo; /* + 0x1C */ + + #define GPIO_I_PIN_ETH_16 BSP_BBIT32(0) + #define GPIO_I_PIN_ETH_15 BSP_BBIT32(1) + #define GPIO_I_PIN_ETH_14 BSP_BBIT32(2) + #define GPIO_I_PIN_ETH_13 BSP_BBIT32(3) + #define GPIO_I_PIN_USB1_9 BSP_BBIT32(4) + #define GPIO_I_PIN_PSC3_8 BSP_BBIT32(5) + #define GPIO_I_PIN_PSC3_5 BSP_BBIT32(6) + #define GPIO_I_PIN_PSC3_4 BSP_BBIT32(7) + + volatile uint32_t gpiosie; /* + 0x20 */ + #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000 + #define GPIO_SIE_SINT_6_ETH_15_PIN 0x40000000 + #define GPIO_SIE_SINT_5_ETH_14_PIN 0x20000000 + #define GPIO_SIE_SINT_4_ETH_13_PIN 0x10000000 + #define GPIO_SIE_SINT_3_USB1_9_PIN 0x08000000 + #define GPIO_SIE_SINT_2_PSC3_8_PIN 0x04000000 + #define GPIO_SIE_SINT_1_PSC3_5_PIN 0x02000000 + #define GPIO_SIE_SINT_0_PSC3_4_PIN 0x01000000 + + volatile uint32_t gpiosiod; /* + 0x24 */ + + volatile uint32_t gpiosidd; /* + 0x28 */ + #define GPIO_SIDD_SINT_7_ETH_16_PIN 0x80000000 + #define GPIO_SIDD_SINT_6_ETH_15_PIN 0x40000000 + #define GPIO_SIDD_SINT_5_ETH_14_PIN 0x20000000 + #define GPIO_SIDD_SINT_4_ETH_13_PIN 0x10000000 + #define GPIO_SIDD_SINT_3_USB1_9_PIN 0x08000000 + #define GPIO_SIDD_SINT_2_PSC3_8_PIN 0x04000000 + #define GPIO_SIDD_SINT_1_PSC3_5_PIN 0x02000000 + #define GPIO_SIDD_SINT_0_PSC3_4_PIN 0x01000000 + + volatile uint32_t gpiosido; /* + 0x2C */ + + volatile uint32_t gpiosiie; /* + 0x30 */ + #define GPIO_SIIE_SINT_7_ETH_16_PIN 0x80000000 + #define GPIO_SIIE_SINT_6_ETH_15_PIN 0x40000000 + #define GPIO_SIIE_SINT_5_ETH_14_PIN 0x20000000 + #define GPIO_SIIE_SINT_4_ETH_13_PIN 0x10000000 + #define GPIO_SIIE_SINT_3_USB1_9_PIN 0x08000000 + #define GPIO_SIIE_SINT_2_PSC3_8_PIN 0x04000000 + #define GPIO_SIIE_SINT_1_PSC3_5_PIN 0x02000000 + #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000 + + volatile uint32_t gpiosiit; /* + 0x34 */ + #define GPIO_SIIT_SET_ETH_16_PIN(reg, val) BSP_BFLD32SET(reg, val, 0, 1) + #define GPIO_SIIT_SET_ETH_15_PIN(reg, val) BSP_BFLD32SET(reg, val, 2, 3) + #define GPIO_SIIT_SET_ETH_14_PIN(reg, val) BSP_BFLD32SET(reg, val, 4, 5) + #define GPIO_SIIT_SET_ETH_13_PIN(reg, val) BSP_BFLD32SET(reg, val, 6, 7) + #define GPIO_SIIT_SET_USB1_9_PIN(reg, val) BSP_BFLD32SET(reg, val, 8, 9) + #define GPIO_SIIT_SET_PSC3_8_PIN(reg, val) BSP_BFLD32SET(reg, val, 10, 11) + #define GPIO_SIIT_SET_PSC3_5_PIN(reg, val) BSP_BFLD32SET(reg, val, 12, 13) + #define GPIO_SIIT_SET_PSC3_4_PIN(reg, val) BSP_BFLD32SET(reg, val, 14, 15) + + #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000 + #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000 + #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000 + #define GPIO_SIIT_SINT_4_ETH_13_PIN_MASK 0x03000000 + #define GPIO_SIIT_SINT_3_USB1_9_PIN_MASK 0x00c00000 + #define GPIO_SIIT_SINT_2_PSC3_8_PIN_MASK 0x00300000 + #define GPIO_SIIT_SINT_1_PSC3_5_PIN_MASK 0x000c0000 + #define GPIO_SIIT_SINT_0_PSC3_4_PIN_MASK 0x00030000 + + #define GPIO_SIIT_ON_ANY_TRANSITION 0x00000000 + #define GPIO_SIIT_ON_RISING_EDGE 0x00000001 + #define GPIO_SIIT_ON_FALLING_EDGE 0x00000002 + #define GPIO_SIIT_ON_PULSE 0x00000003 + + #define GPIO_SIIT_SINT_7_ETH_16_PIN_SHIFT 16 + #define GPIO_SIIT_SINT_6_ETH_15_PIN_SHIFT 18 + #define GPIO_SIIT_SINT_5_ETH_14_PIN_SHIFT 20 + #define GPIO_SIIT_SINT_4_ETH_13_PIN_SHIFT 22 + #define GPIO_SIIT_SINT_3_USB1_9_PIN_SHIFT 24 + #define GPIO_SIIT_SINT_2_PSC3_8_PIN_SHIFT 26 + #define GPIO_SIIT_SINT_1_PSC3_5_PIN_SHIFT 28 + #define GPIO_SIIT_SINT_0_PSC3_4_PIN_SHIFT 30 + + volatile uint32_t gpiosime; /* + 0x38 */ + #define GPIO_SIME_MASTER_ENABLE 0x10000000 + + volatile uint32_t gpiosist; /* + 0x3C */ + #define GPIO_SIST_SINT_7_ETH_16_PIN_STATUS 0x80000000 + #define GPIO_SIST_SINT_6_ETH_15_PIN_STATUS 0x40000000 + #define GPIO_SIST_SINT_5_ETH_14_PIN_STATUS 0x20000000 + #define GPIO_SIST_SINT_4_ETH_13_PIN_STATUS 0x10000000 + #define GPIO_SIST_SINT_3_USB1_9_PIN_STATUS 0x08000000 + #define GPIO_SIST_SINT_2_PSC3_8_PIN_STATUS 0x04000000 + #define GPIO_SIST_SINT_1_PSC3_5_PIN_STATUS 0x02000000 + #define GPIO_SIST_SINT_0_PSC3_4_PIN_STATUS 0x01000000 + #define GPIO_SIST_SINT_7_ETH_16_PIN_VALUE 0x00800000 + #define GPIO_SIST_SINT_6_ETH_15_PIN_VALUE 0x00400000 + #define GPIO_SIST_SINT_5_ETH_14_PIN_VALUE 0x00200000 + #define GPIO_SIST_SINT_4_ETH_13_PIN_VALUE 0x00100000 + #define GPIO_SIST_SINT_3_USB1_9_PIN_VALUE 0x00080000 + #define GPIO_SIST_SINT_2_PSC3_8_PIN_VALUE 0x00040000 + #define GPIO_SIST_SINT_1_PSC3_5_PIN_VALUE 0x00020000 + #define GPIO_SIST_SINT_0_PSC3_4_PIN_VALUE 0x00010000 + + #define GPIO_SIST_SINT_CLEAR_ALL 0xff000000 + + volatile uint8_t res4[0xC0]; + + /* + * GPIO wakeup registers (MBAR + 0xC00) + */ + + #define GPIO_W_PIN_GPIO_WKUP_7 BSP_BBIT32(0) + #define GPIO_W_PIN_GPIO_WKUP_6 BSP_BBIT32(1) + #define GPIO_W_PIN_PSC6_1 BSP_BBIT32(2) + #define GPIO_W_PIN_PSC6_0 BSP_BBIT32(3) + #define GPIO_W_PIN_ETH_17 BSP_BBIT32(4) + #define GPIO_W_PIN_PSC3_9 BSP_BBIT32(5) + #define GPIO_W_PIN_PSC2_4 BSP_BBIT32(6) + #define GPIO_W_PIN_PSC1_4 BSP_BBIT32(7) + + volatile uint32_t gpiowe; /* + 0x00 */ + volatile uint32_t gpiowod; /* + 0x04 */ + volatile uint32_t gpiowdd; /* + 0x08 */ + volatile uint32_t gpiowdo; /* + 0x0C */ + volatile uint32_t gpiowue; /* + 0x10 */ + volatile uint32_t gpiowsie; /* + 0x14 */ + volatile uint32_t gpiowt; /* + 0x18 */ + volatile uint32_t gpiowme; /* + 0x1C */ + volatile uint32_t gpiowi; /* + 0x20 */ + volatile uint32_t gpiows; /* + 0x24 */ + volatile uint8_t gpiow_res[0xD8]; + + /* + * PPC PCI registers (MBAR + 0xD00) + */ + volatile uint8_t ppci[0x100]; + + /* + * consumer infrared registers (MBAR + 0xE00) + */ + volatile uint8_t ir[0x100]; + + /* + * serial peripheral interface registers (MBAR + 0xF00) + */ + volatile uint8_t spi[0x100]; + + /* + * universal serial bus registers (MBAR + 0x1000) + */ + volatile uint8_t usb[0x200]; + + /* + * SmartComm DMA registers (MBAR + 0x1200) + */ + volatile mpc5200_sdma sdma; + + volatile uint32_t EU00; /* + 0x80 sdMac macer reg */ + volatile uint32_t EU01; /* + 0x84 sdMac macemr reg */ + volatile uint32_t EU02; /* + 0x88 unused */ + volatile uint32_t EU03; /* + 0x8c unused */ + volatile uint32_t EU04; /* + 0x90 unused */ + volatile uint32_t EU05; /* + 0x94 unused */ + volatile uint32_t EU06; /* + 0x98 unused */ + volatile uint32_t EU07; /* + 0x9c unused */ + volatile uint32_t EU10; /* + 0xa0 unused */ + volatile uint32_t EU11; /* + 0xa4 unused */ + volatile uint32_t EU12; /* + 0xa8 unused */ + volatile uint32_t EU13; /* + 0xac unused */ + volatile uint32_t EU14; /* + 0xb0 unused */ + volatile uint32_t EU15; /* + 0xb4 unused */ + volatile uint32_t EU16; /* + 0xb8 unused */ + volatile uint32_t EU17; /* + 0xbc unused */ + volatile uint32_t EU20; /* + 0xc0 unused */ + volatile uint32_t EU21; /* + 0xc4 unused */ + volatile uint32_t EU22; /* + 0xc8 unused */ + volatile uint32_t EU23; /* + 0xcc unused */ + volatile uint32_t EU24; /* + 0xd0 unused */ + volatile uint32_t EU25; /* + 0xd4 unused */ + volatile uint32_t EU26; /* + 0xd8 unused */ + volatile uint32_t EU27; /* + 0xdc unused */ + volatile uint32_t EU30; /* + 0xe0 unused */ + volatile uint32_t EU31; /* + 0xe4 unused */ + volatile uint32_t EU32; /* + 0xe8 unused */ + volatile uint32_t EU33; /* + 0xec unused */ + volatile uint32_t EU34; /* + 0xf0 unused */ + volatile uint32_t EU35; /* + 0xf4 unused */ + volatile uint32_t EU36; /* + 0xf8 unused */ + volatile uint32_t EU37; /* + 0xfc unused */ +#if 0 + volatile uint32_t res8[0x340]; +#else + volatile uint8_t res_1300[0xc00]; + + volatile uint32_t reserved0; /* MBAR_XLB_ARB + 0x0000 reserved */ + volatile uint32_t reserved1; /* MBAR_XLB_ARB + 0x0004 reserved */ + volatile uint32_t reserved2; /* MBAR_XLB_ARB + 0x0008 reserved */ + volatile uint32_t reserved3; /* MBAR_XLB_ARB + 0x000c reserved */ + volatile uint32_t reserved4; /* MBAR_XLB_ARB + 0x0010 reserved */ + volatile uint32_t reserved5; /* MBAR_XLB_ARB + 0x0014 reserved */ + volatile uint32_t reserved6; /* MBAR_XLB_ARB + 0x0018 reserved */ + volatile uint32_t reserved7; /* MBAR_XLB_ARB + 0x001c reserved */ + volatile uint32_t reserved8; /* MBAR_XLB_ARB + 0x0020 reserved */ + volatile uint32_t reserved9; /* MBAR_XLB_ARB + 0x0024 reserved */ + volatile uint32_t reserved10; /* MBAR_XLB_ARB + 0x0028 reserved */ + volatile uint32_t reserved11; /* MBAR_XLB_ARB + 0x002c reserved */ + volatile uint32_t reserved12; /* MBAR_XLB_ARB + 0x0030 reserved */ + volatile uint32_t reserved13; /* MBAR_XLB_ARB + 0x0034 reserved */ + volatile uint32_t reserved14; /* MBAR_XLB_ARB + 0x0038 reserved */ + volatile uint32_t reserved15; /* MBAR_XLB_ARB + 0x003c reserved */ + +#define XLB_CFG_PLDIS BSP_BBIT32(0) +#define XLB_CFG_BSDIS BSP_BBIT32(15) +#define XLB_CFG_SE BSP_BBIT32(16) +#define XLB_CFG_USE_WWF BSP_BBIT32(17) +#define XLB_CFG_TBEN BSP_BBIT32(18) +#define XLB_CFG_WS BSP_BBIT32(20) +#define XLB_CFG_SP(val) BSP_BFLD32(val, 21, 23) +#define XLB_CFG_SET_SP(reg, val) BSP_BFLD32SET(reg, val, 21, 23) +#define XLB_CFG_PM(val) BSP_BFLD32(val, 25, 26) +#define XLB_CFG_SET_PM(reg, val) BSP_BFLD32SET(reg, val, 25, 26) +#define XLB_CFG_BA BSP_BBIT32(28) +#define XLB_CFG_DT BSP_BBIT32(29) +#define XLB_CFG_AT BSP_BBIT32(30) + + volatile uint32_t config; /* MBAR_XLB_ARB + 0x0040 */ + volatile uint32_t version; /* MBAR_XLB_ARB + 0x0044 */ + +#define XLB_ST_SEA BSP_BBIT32(23) +#define XLB_ST_MM BSP_BBIT32(24) +#define XLB_ST_TTA BSP_BBIT32(25) +#define XLB_ST_TTR BSP_BBIT32(26) +#define XLB_ST_ECW BSP_BBIT32(27) +#define XLB_ST_TTM BSP_BBIT32(28) +#define XLB_ST_BA BSP_BBIT32(29) +#define XLB_ST_DT BSP_BBIT32(30) +#define XLB_ST_AT BSP_BBIT32(31) + /* read only = 0x0001 */ + volatile uint32_t xlb_status; /* MBAR_XLB_ARB + 0x0048 */ + volatile uint32_t int_enable; /* MBAR_XLB_ARB + 0x004c */ + volatile uint32_t add_capture; /* MBAR_XLB_ARB + 0x0050 read only */ + volatile uint32_t bus_sig_capture; /* MBAR_XLB_ARB + 0x0054 read only */ + volatile uint32_t add_time_out; /* MBAR_XLB_ARB + 0x0058 */ + volatile uint32_t data_time_out; /* MBAR_XLB_ARB + 0x005c */ + volatile uint32_t bus_time_out; /* MBAR_XLB_ARB + 0x0060 */ + volatile uint32_t priority_enable; /* MBAR_XLB_ARB + 0x0064 */ + volatile uint32_t priority; /* MBAR_XLB_ARB + 0x0068 */ + volatile uint32_t arb_base_addr2; /* MBAR_XLB_ARB + 0x006c */ + volatile uint32_t snoop_window; /* MBAR_XLB_ARB + 0x0070 */ + + volatile uint32_t reserved16; /* MBAR_XLB_ARB + 0x0074 reserved */ + volatile uint32_t reserved17; /* MBAR_XLB_ARB + 0x0078 reserved */ + volatile uint32_t reserved18; /* MBAR_XLB_ARB + 0x007c reserved */ + + volatile uint32_t control; /* MBAR_XLB_ARB + 0x0080 */ + volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */ + volatile uint32_t int_total_count; /* MBAR_XLB_ARB + 0x0088 */ + + volatile uint32_t reserved19; /* MBAR_XLB_ARB + 0x008c reserved */ + + volatile uint32_t lower_address; /* MBAR_XLB_ARB + 0x0090 */ + volatile uint32_t higher_address; /* MBAR_XLB_ARB + 0x0094 */ + volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */ + volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */ + volatile uint8_t res_0x1fa0[0x60]; + + +#endif + /* + * programmable serial controller 1 (MBAR + 0x2000) + */ + + struct mpc5200_psc { + volatile uint8_t mr; /* + 0x00 */ + volatile uint8_t res1[3]; + volatile uint16_t sr_csr; /* + 0x04 */ + volatile uint16_t res2[1]; + volatile uint16_t cr; /* + 0x08 */ + volatile uint16_t res3[1]; + volatile uint32_t rb_tb; /* + 0x0c */ + volatile uint16_t ipcr_acr; /* + 0x10 */ + volatile uint16_t res4[1]; + volatile uint16_t isr_imr; /* + 0x14 */ +#define ISR_TX_RDY (1 << 8) +#define ISR_RX_RDY_FULL (1 << 9) +#define ISR_RB (1 << 15) +#define ISR_FE (1 << 14) +#define ISR_PE (1 << 13) +#define ISR_OE (1 << 12) +#define ISR_ERROR (ISR_FE | ISR_PE | ISR_OE) + +#define IMR_TX_RDY (1 << 8) +#define IMR_RX_RDY_FULL (1 << 9) + volatile uint16_t res5[1]; + volatile uint8_t ctur; /* + 0x18 */ + volatile uint8_t res6[3]; + volatile uint8_t ctlr; /* + 0x1C */ + volatile uint8_t res7[0x13]; + volatile uint8_t ivr; /* + 0x30 */ + volatile uint8_t res8[3]; + volatile uint8_t ip; /* + 0x34 */ + volatile uint8_t res9[3]; + volatile uint8_t op1; /* + 0x38 */ + volatile uint8_t res10[3]; + volatile uint8_t op0; /* + 0x3C */ + volatile uint8_t res11[3]; + volatile uint8_t sicr; /* + 0x40 */ + volatile uint8_t res12[0x17]; + volatile uint16_t rfnum; /* + 0x58 */ + volatile uint16_t res13[1]; + volatile uint16_t tfnum; /* + 0x5C */ + volatile uint16_t res14[1]; + volatile uint16_t rfdata; /* + 0x60 */ + volatile uint16_t res15[1]; + volatile uint16_t rfstat; /* + 0x64 */ + volatile uint16_t res16[1]; + volatile uint8_t rfcntl; /* + 0x68 */ + volatile uint8_t res17[5]; + volatile uint16_t rfalarm; /* + 0x6E */ + volatile uint8_t res18[2]; + volatile uint16_t rfrptr; /* + 0x72 */ + volatile uint16_t res19[1]; + volatile uint16_t rfwptr; /* + 0x76 */ + volatile uint16_t res20[1]; + volatile uint16_t rflrfptr; /* + 0x7A */ + volatile uint16_t rflwfptr; /* + 0x7C */ + volatile uint16_t res21[1]; + volatile uint16_t tfdata; /* + 0x80 */ + volatile uint16_t res22[1]; + volatile uint16_t tfstat; /* + 0x84 */ + volatile uint16_t res23[1]; + volatile uint8_t tfcntl; /* + 0x88 */ + volatile uint8_t res24[5]; + volatile uint16_t tfalarm; /* + 0x8E */ + volatile uint8_t res25[2]; + volatile uint16_t tfrptr; /* + 0x92 */ + volatile uint16_t res26[1]; + volatile uint16_t tfwptr; /* + 0x96 */ + volatile uint16_t res27[1]; + volatile uint16_t tflrfptr; /* + 0x96 */ + volatile uint16_t tflwfptr; /* + 0x9C */ + volatile uint16_t res28[1]; /* end at offset 0x9F */ + volatile uint8_t res29[0x160]; + } psc[MPC5200_PSC_REG_SETS]; + /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap + * from PSC5, therefore we instantiate seven(!) PSC register sets + */ + +#define TX_FIFO_SIZE 256 +#define RX_FIFO_SIZE 512 + + + volatile uint8_t irda[0x200]; + + /* + * ethernet registers (MBAR + 0x3000) + */ + + /* Control and status Registers (offset 000-1FF) */ + + volatile uint32_t fec_id; /* + 0x000 */ + volatile uint32_t ievent; /* + 0x004 */ + volatile uint32_t imask; /* + 0x008 */ + + volatile uint32_t res9[1]; /* + 0x00C */ + volatile uint32_t r_des_active; /* + 0x010 */ + volatile uint32_t x_des_active; /* + 0x014 */ + volatile uint32_t r_des_active_cl; /* + 0x018 */ + volatile uint32_t x_des_active_cl; /* + 0x01C */ + volatile uint32_t ivent_set; /* + 0x020 */ + volatile uint32_t ecntrl; /* + 0x024 */ + + volatile uint32_t res10[6]; /* + 0x028-03C */ + volatile uint32_t mii_data; /* + 0x040 */ + volatile uint32_t mii_speed; /* + 0x044 */ + volatile uint32_t mii_status; /* + 0x048 */ + + volatile uint32_t res11[5]; /* + 0x04C-05C */ + volatile uint32_t mib_data; /* + 0x060 */ + volatile uint32_t mib_control; /* + 0x064 */ + + volatile uint32_t res12[6]; /* + 0x068-7C */ + volatile uint32_t r_activate; /* + 0x080 */ + volatile uint32_t r_cntrl; /* + 0x084 */ + volatile uint32_t r_hash; /* + 0x088 */ + volatile uint32_t r_data; /* + 0x08C */ + volatile uint32_t ar_done; /* + 0x090 */ + volatile uint32_t r_test; /* + 0x094 */ + volatile uint32_t r_mib; /* + 0x098 */ + volatile uint32_t r_da_low; /* + 0x09C */ + volatile uint32_t r_da_high; /* + 0x0A0 */ + + volatile uint32_t res13[7]; /* + 0x0A4-0BC */ + volatile uint32_t x_activate; /* + 0x0C0 */ + volatile uint32_t x_cntrl; /* + 0x0C4 */ + volatile uint32_t backoff; /* + 0x0C8 */ + volatile uint32_t x_data; /* + 0x0CC */ + volatile uint32_t x_status; /* + 0x0D0 */ + volatile uint32_t x_mib; /* + 0x0D4 */ + volatile uint32_t x_test; /* + 0x0D8 */ + volatile uint32_t fdxfc_da1; /* + 0x0DC */ + volatile uint32_t fdxfc_da2; /* + 0x0E0 */ + volatile uint32_t paddr1; /* + 0x0E4 */ + volatile uint32_t paddr2; /* + 0x0E8 */ + volatile uint32_t op_pause; /* + 0x0EC */ + + volatile uint32_t res14[4]; /* + 0x0F0-0FC */ + volatile uint32_t instr_reg; /* + 0x100 */ + volatile uint32_t context_reg; /* + 0x104 */ + volatile uint32_t test_cntrl; /* + 0x108 */ + volatile uint32_t acc_reg; /* + 0x10C */ + volatile uint32_t ones; /* + 0x110 */ + volatile uint32_t zeros; /* + 0x114 */ + volatile uint32_t iaddr1; /* + 0x118 */ + volatile uint32_t iaddr2; /* + 0x11C */ + volatile uint32_t gaddr1; /* + 0x120 */ + volatile uint32_t gaddr2; /* + 0x124 */ + volatile uint32_t random; /* + 0x128 */ + volatile uint32_t rand1; /* + 0x12C */ + volatile uint32_t tmp; /* + 0x130 */ + + volatile uint32_t res15[3]; /* + 0x134-13C */ + volatile uint32_t fifo_id; /* + 0x140 */ + volatile uint32_t x_wmrk; /* + 0x144 */ + volatile uint32_t fcntrl; /* + 0x148 */ + volatile uint32_t r_bound; /* + 0x14C */ + volatile uint32_t r_fstart; /* + 0x150 */ + volatile uint32_t r_count; /* + 0x154 */ + volatile uint32_t r_lag; /* + 0x158 */ + volatile uint32_t r_read; /* + 0x15C */ + volatile uint32_t r_write; /* + 0x160 */ + volatile uint32_t x_count; /* + 0x164 */ + volatile uint32_t x_lag; /* + 0x168 */ + volatile uint32_t x_retry; /* + 0x16C */ + volatile uint32_t x_write; /* + 0x170 */ + volatile uint32_t x_read; /* + 0x174 */ + + volatile uint32_t res16[2]; /* + 0x178-17C */ + volatile uint32_t fm_cntrl; /* + 0x180 */ + volatile uint32_t rfifo_data; /* + 0x184 */ + volatile uint32_t rfifo_status; /* + 0x188 */ + volatile uint32_t rfifo_cntrl; /* + 0x18C */ + volatile uint32_t rfifo_lrf_ptr; /* + 0x190 */ + volatile uint32_t rfifo_lwf_ptr; /* + 0x194 */ + volatile uint32_t rfifo_alarm; /* + 0x198 */ + volatile uint32_t rfifo_rdptr; /* + 0x19C */ + volatile uint32_t rfifo_wrptr; /* + 0x1A0 */ + volatile uint32_t tfifo_data; /* + 0x1A4 */ + volatile uint32_t tfifo_status; /* + 0x1A8 */ + volatile uint32_t tfifo_cntrl; /* + 0x1AC */ + volatile uint32_t tfifo_lrf_ptr; /* + 0x1B0 */ + volatile uint32_t tfifo_lwf_ptr; /* + 0x1B4 */ + volatile uint32_t tfifo_alarm; /* + 0x1B8 */ + volatile uint32_t tfifo_rdptr; /* + 0x1BC */ + volatile uint32_t tfifo_wrptr; /* + 0x1C0 */ + + volatile uint32_t reset_cntrl; /* + 0x1C4 */ + volatile uint32_t xmit_fsm; /* + 0x1C8 */ + + volatile uint32_t res17[3]; /* + 0x1CC-1D4 */ + volatile uint32_t rdes_data0; /* + 0x1D8 */ + volatile uint32_t rdes_data1; /* + 0x1DC */ + volatile uint32_t r_length; /* + 0x1E0 */ + volatile uint32_t x_length; /* + 0x1E4 */ + volatile uint32_t x_addr; /* + 0x1E8 */ + volatile uint32_t cdes_data; /* + 0x1EC */ + volatile uint32_t status; /* + 0x1F0 */ + volatile uint32_t dma_control; /* + 0x1F4 */ + volatile uint32_t des_cmnd; /* + 0x1F8 */ + volatile uint32_t data; /* + 0x1FC */ + + volatile uint8_t RES[0x600]; + + +#if 0 + /* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32_t rmon_t_drop; /* + 0x200 */ + volatile uint32_t rmon_t_packets; /* + 0x204 */ + volatile uint32_t rmon_t_bc_pkt; /* + 0x208 */ + volatile uint32_t rmon_t_mc_pkt; /* + 0x20C */ + volatile uint32_t rmon_t_crc_align; /* + 0x210 */ + volatile uint32_t rmon_t_undersize; /* + 0x214 */ + volatile uint32_t rmon_t_oversize; /* + 0x218 */ + volatile uint32_t rmon_t_frag; /* + 0x21C */ + volatile uint32_t rmon_t_jab; /* + 0x220 */ + volatile uint32_t rmon_t_col; /* + 0x224 */ + volatile uint32_t rmon_t_p64; /* + 0x228 */ + volatile uint32_t rmon_t_p65to127; /* + 0x22C */ + volatile uint32_t rmon_t_p128to255; /* + 0x230 */ + volatile uint32_t rmon_t_p256to511; /* + 0x234 */ + volatile uint32_t rmon_t_p512to1023; /* + 0x238 */ + volatile uint32_t rmon_t_p1024to2047; /* + 0x23C */ + volatile uint32_t rmon_t_p_gte2048; /* + 0x240 */ + volatile uint32_t rmon_t_octets; /* + 0x244 */ + volatile uint32_t ieee_t_drop; /* + 0x248 */ + volatile uint32_t ieee_t_frame_ok; /* + 0x24C */ + volatile uint32_t ieee_t_1col; /* + 0x250 */ + volatile uint32_t ieee_t_mcol; /* + 0x254 */ + volatile uint32_t ieee_t_def; /* + 0x258 */ + volatile uint32_t ieee_t_lcol; /* + 0x25C */ + volatile uint32_t ieee_t_excol; /* + 0x260 */ + volatile uint32_t ieee_t_macerr; /* + 0x264 */ + volatile uint32_t ieee_t_cserr; /* + 0x268 */ + volatile uint32_t ieee_t_sqe; /* + 0x26C */ + volatile uint32_t t_fdxfc; /* + 0x270 */ + volatile uint32_t ieee_t_octets_ok; /* + 0x274 */ + + volatile uint32_t res18[2]; /* + 0x278-27C */ + volatile uint32_t rmon_r_drop; /* + 0x280 */ + volatile uint32_t rmon_r_packets; /* + 0x284 */ + volatile uint32_t rmon_r_bc_pkt; /* + 0x288 */ + volatile uint32_t rmon_r_mc_pkt; /* + 0x28C */ + volatile uint32_t rmon_r_crc_align; /* + 0x290 */ + volatile uint32_t rmon_r_undersize; /* + 0x294 */ + volatile uint32_t rmon_r_oversize; /* + 0x298 */ + volatile uint32_t rmon_r_frag; /* + 0x29C */ + volatile uint32_t rmon_r_jab; /* + 0x2A0 */ + + volatile uint32_t rmon_r_resvd_0; /* + 0x2A4 */ + + volatile uint32_t rmon_r_p64; /* + 0x2A8 */ + volatile uint32_t rmon_r_p65to127; /* + 0x2AC */ + volatile uint32_t rmon_r_p128to255; /* + 0x2B0 */ + volatile uint32_t rmon_r_p256to511; /* + 0x2B4 */ + volatile uint32_t rmon_r_p512to1023; /* + 0x2B8 */ + volatile uint32_t rmon_r_p1024to2047; /* + 0x2BC */ + volatile uint32_t rmon_r_p_gte2048; /* + 0x2C0 */ + volatile uint32_t rmon_r_octets; /* + 0x2C4 */ + volatile uint32_t ieee_r_drop; /* + 0x2C8 */ + volatile uint32_t ieee_r_frame_ok; /* + 0x2CC */ + volatile uint32_t ieee_r_crc; /* + 0x2D0 */ + volatile uint32_t ieee_r_align; /* + 0x2D4 */ + volatile uint32_t r_macerr; /* + 0x2D8 */ + volatile uint32_t r_fdxfc; /* + 0x2DC */ + volatile uint32_t ieee_r_octets_ok; /* + 0x2E0 */ + + volatile uint32_t res19[6]; /* + 0x2E4-2FC */ + + volatile uint32_t res20[64]; /* + 0x300-3FF */ + + volatile uint32_t res21[256]; /* + 0x400-800 */ +#endif + + /* + * SmartComm DMA PCI registers (MBAR + 0x3800) + */ + volatile uint8_t pci[0x200]; + + /* + * advanced technology attachment registers (MBAR + 0x3A00) + */ + + /* ATA host registers (offset 0x00-0x28) */ + volatile uint32_t ata_hcfg; /* + 0x00 */ + volatile uint32_t ata_hsr; /* + 0x04 */ + volatile uint32_t ata_pio1; /* + 0x08 */ + volatile uint32_t ata_pio2; /* + 0x0C */ + volatile uint32_t ata_dma1; /* + 0x10 */ + volatile uint32_t ata_dma2; /* + 0x14 */ + volatile uint32_t ata_udma1; /* + 0x18 */ + volatile uint32_t ata_udma2; /* + 0x1C */ + volatile uint32_t ata_udma3; /* + 0x20 */ + volatile uint32_t ata_udma4; /* + 0x24 */ + volatile uint32_t ata_udma5; /* + 0x28 */ + volatile uint32_t ata_res1[4]; /* + 0x2C-0x3C */ + + /* ATA FIFO registers (offset 0x3C-0x50) */ + volatile uint32_t ata_rtfdwr; /* + 0x3C */ + +#define ATA_RTFSR_ERR BSP_BBIT32(9) +#define ATA_RTFSR_UF BSP_BBIT32(10) +#define ATA_RTFSR_OF BSP_BBIT32(11) +#define ATA_RTFSR_FULL BSP_BBIT32(12) +#define ATA_RTFSR_HI BSP_BBIT32(13) +#define ATA_RTFSR_LO BSP_BBIT32(14) +#define ATA_RTFSR_EMPTY BSP_BBIT32(15) + + volatile uint32_t ata_rtfsr; /* + 0x40 */ + +#define ATA_RTFCR_WFR BSP_BBIT32(2) +#define ATA_RTFCR_GR(val) BSP_BFLD32(val, 5, 7) + + volatile uint32_t ata_rtfcr; /* + 0x44 */ + volatile uint32_t ata_rtfar; /* + 0x48 */ + volatile uint32_t ata_rtfrpr; /* + 0x4C */ + volatile uint32_t ata_rtfwpr; /* + 0x50 */ + volatile uint32_t ata_res2[2]; /* + 0x54-0x5C */ + + /* ATA drive registers (offset 0x5C-0x80) */ + volatile uint32_t ata_dctr_dasr; /* + 0x5C */ + volatile uint32_t ata_ddr; /* + 0x60 */ + volatile uint32_t ata_dfr_der; /* + 0x64 */ + volatile uint32_t ata_dscr; /* + 0x68 */ + volatile uint32_t ata_dsnr; /* + 0x6C */ + volatile uint32_t ata_dclr; /* + 0x70 */ + volatile uint32_t ata_dchr; /* + 0x74 */ + volatile uint32_t ata_ddhr; /* + 0x78 */ + volatile uint32_t ata_dcr_dsr; /* + 0x7C */ + volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */ + + /* + * inter-integrated circuit registers (MBAR + 0x3D00) + */ + struct mpc5200_i2c_regs_s { + volatile uint8_t madr; /* i2c address reg. + 0x00 */ + volatile uint8_t res_1[3]; + volatile uint8_t mfdr; /* i2c freq. divider reg. + 0x04 */ + volatile uint8_t res_5[3]; + volatile uint8_t mcr; /* i2c control reg. + 0x08 */ + volatile uint8_t res_9[3]; + +#define MPC5200_I2C_MCR_MEN (1 << (7-0)) +#define MPC5200_I2C_MCR_MIEN (1 << (7-1)) +#define MPC5200_I2C_MCR_MSTA (1 << (7-2)) +#define MPC5200_I2C_MCR_MTX (1 << (7-3)) +#define MPC5200_I2C_MCR_TXAK (1 << (7-4)) +#define MPC5200_I2C_MCR_RSTA (1 << (7-5)) + + volatile uint8_t msr; /* i2c status reg. + 0x0C */ + volatile uint8_t res_d[3]; +#define MPC5200_I2C_MSR_CF (1 << (7-0)) +#define MPC5200_I2C_MSR_MAAS (1 << (7-1)) +#define MPC5200_I2C_MSR_BB (1 << (7-2)) +#define MPC5200_I2C_MSR_MAL (1 << (7-3)) +#define MPC5200_I2C_MSR_SRW (1 << (7-5)) +#define MPC5200_I2C_MSR_MIF (1 << (7-6)) +#define MPC5200_I2C_MSR_RXAK (1 << (7-7)) + volatile uint8_t mdr; /* i2c data I/O reg. + 0x10 */ + volatile uint8_t res_11[3]; + volatile uint8_t res_14[12]; /* reserved + 0x14 */ + volatile uint8_t icr; /* i2c irq ctrl reg. + 0x20 */ +#define MPC5200_I2C_ICR_BNBE2 (1 << (7-0)) +#define MPC5200_I2C_ICR_TE2 (1 << (7-1)) +#define MPC5200_I2C_ICR_RE2 (1 << (7-2)) +#define MPC5200_I2C_ICR_IE2 (1 << (7-3)) +#define MPC5200_I2C_ICR_MASK2 (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\ + |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2) +#define MPC5200_I2C_ICR_BNBE1 (1 << (7-4)) +#define MPC5200_I2C_ICR_TE1 (1 << (7-5)) +#define MPC5200_I2C_ICR_RE1 (1 << (7-6)) +#define MPC5200_I2C_ICR_IE1 (1 << (7-7)) +#define MPC5200_I2C_ICR_MASK1 (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\ + |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1) + volatile uint8_t res_21[3]; + volatile uint32_t res_24[7]; /* reserved + 0x24 */ + } i2c_regs[2]; + volatile uint8_t res_3d80[0x280]; + + /* + * on-chip static RAM memory locations (MBAR + 0x4000) + */ + volatile uint8_t sram_res0x4000[0x4000]; + volatile uint8_t sram[0x4000]; + +} mpc5200_t; + +extern volatile mpc5200_t mpc5200; + +#ifdef __cplusplus +} +#endif + +#endif /*ASM*/ + +#endif /* __MPC5200_h__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/mscan-base.h b/bsps/powerpc/gen5200/include/bsp/mscan-base.h new file mode 100644 index 0000000000..a2b8737d8e --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/mscan-base.h @@ -0,0 +1,284 @@ +/** + * @file + * + * @ingroup m + * + * @brief MSCAN register definitions and support functions. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_MSCAN_BASE_H +#define LIBBSP_MSCAN_BASE_H + +#include <stdbool.h> + +#include <bsp/mpc5200.h> + +/** + * @defgroup m MSCAN + * + * @{ + */ + +#define MSCAN_BIT_RATE_MIN 10000 + +#define MSCAN_BIT_RATE_MAX 1000000 + +#define MSCAN_BIT_RATE_DEFAULT 125000 + +#define MSCAN_FILTER_NUMBER_MIN 0 + +#define MSCAN_FILTER_NUMBER_2 2 + +#define MSCAN_FILTER_NUMBER_4 4 + +#define MSCAN_FILTER_NUMBER_MAX 8 + +#define MSCAN_FILTER_ID_DEFAULT 0U + +#define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU + +#define MSCAN_TRANSMIT_BUFFER_NUMBER 3 + +/** + * @name MSCAN Control Register 0 (CANCTL0) + * + * @{ + */ + +#define CTL0_RXFRM (1 << 7) +#define CTL0_RXACT (1 << 6) +#define CTL0_CSWAI (1 << 5) +#define CTL0_SYNCH (1 << 4) +#define CTL0_TIME (1 << 3) +#define CTL0_WUPE (1 << 2) +#define CTL0_SLPRQ (1 << 1) +#define CTL0_INITRQ (1 << 0) + +/** @} */ + +/** + * @name MSCAN Control Register 1 (CANCTL1) + * + * @{ + */ + +#define CTL1_CANE (1 << 7) +#define CTL1_CLKSRC (1 << 6) +#define CTL1_LOOPB (1 << 5) +#define CTL1_LISTEN (1 << 4) +#define CTL1_WUPM (1 << 2) +#define CTL1_SLPAK (1 << 1) +#define CTL1_INITAK (1 << 0) + +/** @} */ + +/** + * @name MSCAN Bus Timing Register 0 (CANBTR0) + * + * @{ + */ + +#define BTR0_SJW_MASK 0xc0 +#define BTR0_BRP_MASK 0x3f + +#define BTR0_SJW( btr0) ((btr0) << 6) +#define BTR0_BRP( btr0) ((btr0) << 0) + +#define BTR0_GET_SJW( btr0) (((btr0) & BTR0_SJW_MASK) >> 6) +#define BTR0_GET_BRP( btr0) (((btr0) & BTR0_BRP_MASK) >> 0) + +/** @} */ + +/** + * @name MSCAN Bus Timing Register 1 (CANBTR1) + * + * @{ + */ + +#define BTR1_SAMP_MASK 0x80 +#define BTR1_TSEG1_MASK 0x0f +#define BTR1_TSEG2_MASK 0x70 + +#define BTR1_SAMP (1 << 7) +#define BTR1_TSEG1( btr1) ((btr1) << 0) +#define BTR1_TSEG2( btr1) ((btr1) << 4) + +#define BTR1_GET_TSEG1( btr0) (((btr0) & BTR1_TSEG1_MASK) >> 0) +#define BTR1_GET_TSEG2( btr0) (((btr0) & BTR1_TSEG2_MASK) >> 4) + +/** @} */ + +/** + * @name MSCAN Receiver Flag Register (CANRFLG) + * + * @{ + */ + +#define RFLG_WUPIF (1 << 7) +#define RFLG_CSCIF (1 << 6) +#define RFLG_RSTAT_MASK (3 << 4) +#define RFLG_RSTAT_OK (0 << 4) +#define RFLG_RSTAT_WRN (1 << 4) +#define RFLG_RSTAT_ERR (2 << 4) +#define RFLG_RSTAT_OFF (3 << 4) +#define RFLG_TSTAT_MASK (3 << 2) +#define RFLG_TSTAT_OK (0 << 2) +#define RFLG_TSTAT_WRN (1 << 2) +#define RFLG_TSTAT_ERR (2 << 2) +#define RFLG_TSTAT_OFF (3 << 2) +#define RFLG_OVRIF (1 << 1) +#define RFLG_RXF (1 << 0) +#define RFLG_GET_RX_STATE(rflg) (((rflg) >> 4) & 0x03) +#define RFLG_GET_TX_STATE(rflg) (((rflg) >> 2) & 0x03) + +/** @} */ + +/** + * @name MSCAN Receiver Interrupt Enable Register (CANRIER) + * + * @{ + */ + +#define RIER_WUPIE (1 << 7) +#define RIER_CSCIE (1 << 6) +#define RIER_RSTAT(rier) ((rier) << 4) +#define RIER_TSTAT(rier) ((rier) << 2) +#define RIER_OVRIE (1 << 1) +#define RIER_RXFIE (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Flag Register (CANTFLG) + * + * @{ + */ + +#define TFLG_TXE2 (1 << 2) +#define TFLG_TXE1 (1 << 1) +#define TFLG_TXE0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Interrupt Enable Register (CANTIER) + * + * @{ + */ + +#define TIER_TXEI2 (1 << 2) +#define TIER_TXEI1 (1 << 1) +#define TIER_TXEI0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Message Abort Request (CANTARQ) + * + * @{ + */ + +#define TARQ_ABTRQ2 (1 << 2) +#define TARQ_ABTRQ1 (1 << 1) +#define TARQ_ABTRQ0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK) + * + * @{ + */ + +#define TAAK_ABTRQ2 (1 << 2) +#define TAAK_ABTRQ1 (1 << 1) +#define TAAK_ABTRQ0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN Transmit Buffer Selection (CANBSEL) + * + * @{ + */ + +#define BSEL_TX2 (1 << 2) +#define BSEL_TX1 (1 << 1) +#define BSEL_TX0 (1 << 0) + +/** @} */ + +/** + * @name MSCAN ID Acceptance Control Register (CANIDAC) + * + * @{ + */ + +#define IDAC_IDAM1 (1 << 5) +#define IDAC_IDAM0 (1 << 4) +#define IDAC_IDAM (IDAC_IDAM1 | IDAC_IDAM0) +#define IDAC_IDHIT( idac) ((idac) & 0x7) + +/** @} */ + +/** + * @brief MSCAN registers. + */ +typedef struct mpc5200_mscan mscan; + +/** + * @brief MSCAN context that has to be saved throughout the initialization + * mode. + */ +typedef struct { + uint8_t ctl0; + uint8_t rier; + uint8_t tier; +} mscan_context; + +bool mscan_enable( volatile mscan *m, unsigned bit_rate); + +void mscan_disable( volatile mscan *m); + +void mscan_interrupts_disable( volatile mscan *m); + +bool mscan_set_bit_rate( volatile mscan *m, unsigned bit_rate); + +void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context); + +void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context); + +void mscan_sleep_mode_enter( volatile mscan *m); + +void mscan_sleep_mode_leave( volatile mscan *m); + +volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i); + +volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i); + +unsigned mscan_filter_number( volatile mscan *m); + +bool mscan_set_filter_number( volatile mscan *m, unsigned number); + +bool mscan_filter_operation( volatile mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask); + +void mscan_filter_clear( volatile mscan *m); + +void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec); + +/** @} */ + +#endif /* LIBBSP_MSCAN_BASE_H */ diff --git a/bsps/powerpc/gen5200/include/bsp/mscan.h b/bsps/powerpc/gen5200/include/bsp/mscan.h new file mode 100644 index 0000000000..9cb7fd44e7 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/mscan.h @@ -0,0 +1,127 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file has to be included by application when using mscan | +\*===============================================================*/ +#ifndef __MSCAN_H__ +#define __MSCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MSCAN_A_DEV_NAME "/dev/mscana" +#define MSCAN_B_DEV_NAME "/dev/mscanb" +#define MSCAN_0_DEV_NAME "/dev/mscan0" +#define MSCAN_1_DEV_NAME "/dev/mscan1" +#define MSCAN_A 0 +#define MSCAN_B 1 + +#define MSCAN_MAX_DATA_BYTES 8 + +#define MSCAN_MESS_ID_RTR (1 << 15) +#define MSCAN_MESS_ID_RTR_MASK (1 << 15) +#define MSCAN_MESS_ID_ID_MASK ((1 << 11)-1) +#define MSCAN_MESS_ID_HAS_RTR(id) (((id)&MSCAN_MESS_ID_RTR_MASK)==MSCAN_MESS_ID_RTR) + +#define MSCAN_SET_RX_ID 1 +#define MSCAN_GET_RX_ID 2 +#define MSCAN_SET_RX_ID_MASK 3 +#define MSCAN_GET_RX_ID_MASK 4 +#define MSCAN_SET_TX_ID 5 +#define MSCAN_GET_TX_ID 6 +#define TOUCAN_MSCAN_INIT 7 +#define MSCAN_SET_BAUDRATE 8 +#define SET_TX_BUF_NO 9 + +struct can_message + { + /* uint16_t mess_len; */ + uint16_t mess_id; + uint16_t mess_time_stamp; + uint8_t mess_data[MSCAN_MAX_DATA_BYTES]; + uint8_t mess_len; + uint8_t mess_rtr; + uint32_t toucan_tx_idx; + }; + +struct mscan_rx_parms + { + struct can_message *rx_mess; + uint32_t rx_timeout; + uint8_t rx_flags; + }; + +struct mscan_tx_parms + { + struct can_message *tx_mess; + uint32_t tx_idx; + }; + +struct mscan_ctrl_parms + { + uint32_t ctrl_id; + uint32_t ctrl_id_mask; + uint8_t ctrl_reg_no; + uint8_t ctrl_tx_buf_no; + uint32_t ctrl_can_bitrate; + void (*toucan_cb_fnc)(int16_t); + }; + + +rtems_device_driver mscan_initialize( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_open( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_close( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_read( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_write( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +rtems_device_driver mscan_control( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + + +#define MSCAN_DRIVER_TABLE_ENTRY \ + { mscan_initialize, mscan_open, mscan_close, \ + mscan_read, mscan_write, mscan_control } + +#ifdef __cplusplus +} +#endif + +#endif /* __MSCAN_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/nvram.h b/bsps/powerpc/gen5200/include/bsp/nvram.h new file mode 100644 index 0000000000..b05c35986f --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/nvram.h @@ -0,0 +1,141 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the nvram declarations | +\*===============================================================*/ +/***********************************************************************/ +/* */ +/* Module: nvram.h */ +/* Date: 07/17/2003 */ +/* Purpose: RTEMS M93C64-based header file */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Description: M93C46 is a serial microwire EEPROM which contains */ +/* 1Kbit (128 bytes/64 words) of non-volatile memory. */ +/* The device can be configured for byte- or word- */ +/* access. The driver provides a file-like interface */ +/* to this memory. */ +/* */ +/* MPC5x00 PIN settings: */ +/* */ +/* PSC3_6 (output) -> MC93C46 serial data in (D) */ +/* PSC3_7 (input) -> MC93C46 serial data out (Q) */ +/* PSC3_8 (output) -> MC93C46 chip select input (S) */ +/* PSC3_9 (output) -> MC93C46 serial clock (C) */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Code */ +/* References: DS1307-based Non-Volatile memory device driver */ +/* Module: nvram.h */ +/* Project: RTEMS 4.6.0pre1 / MCF5206Elite BSP */ +/* Version 1.1 */ +/* Date: 10/26/2001 */ +/* Author: Victor V. Vengerov */ +/* Copyright: Copyright (C) 2000 OKTET Ltd.,St.-Petersburg,Russia */ +/* */ +/* The license and distribution terms for this file may be */ +/* found in the file LICENSE in this distribution or at */ +/* http://www.rtems.org/license/LICENSE. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Partially based on the code references which are named above. */ +/* Adaptions, modifications, enhancements and any recent parts of */ +/* the code are under the right of */ +/* */ +/* IPR Engineering, Dachauer Straße 38, D-80335 München */ +/* Copyright(C) 2003 */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* IPR Engineering makes no representation or warranties with */ +/* respect to the performance of this computer program, and */ +/* specifically disclaims any responsibility for any damages, */ +/* special or consequential, connected with the use of this program. */ +/* */ +/*---------------------------------------------------------------------*/ +/* */ +/* Version history: 1.0 */ +/* */ +/***********************************************************************/ + +#ifndef __NVRAM_H__ +#define __NVRAM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* include <bsp.h> */ +#include <bsp.h> + +/* Macros for TBL read access */ +#define TBL_READ(count) __asm__ volatile ("mftb %0\n" : "=r" (count) : "0" (count)) +#define TMBASE_CLOCK (G2_CLOCK/4) + +/* Simple usec delay function prototype */ +void wait_usec(unsigned long); + +/* nvram_driver_initialize -- + * Non-volatile memory device driver initialization. + */ +rtems_device_driver +nvram_driver_initialize(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_open -- + * Non-volatile memory device driver open primitive. + */ +rtems_device_driver +nvram_driver_open(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_close -- + * Non-volatile memory device driver close primitive. + */ +rtems_device_driver +nvram_driver_close(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_read -- + * Non-volatile memory device driver read primitive. + */ +rtems_device_driver +nvram_driver_read(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +/* nvram_driver_write -- + * Non-volatile memory device driver write primitive. + */ +rtems_device_driver +nvram_driver_write(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* __NVRAM_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/slicetimer.h b/bsps/powerpc/gen5200/include/bsp/slicetimer.h new file mode 100644 index 0000000000..e089dbc8ad --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/slicetimer.h @@ -0,0 +1,69 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC5200 BSP | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2005 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares functions to use the slice timer module +\*===============================================================*/ +#ifndef __SLICETIMER_H__ +#define __SLICETIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SLT0 0 +#define SLT1 1 + +#define SLT0_INT_FREQUENCY 10000 +#define SLT1_INT_FREQUENCY 0 + +#define SLT_CNTRL_RW (1 << 26) +#define SLT_CNTRL_INTEN (1 << 25) +#define SLT_CNTRL_TIMEN (1 << 24) + +#define SLT_TSR_ST (1 << 24) + +#define SLT_TSR_COUNT(freq) ((freq) ? ((IPB_CLOCK)/(freq)) : (0xFFFFFF)) + +rtems_device_driver slt_initialize( rtems_device_major_number, + rtems_device_minor_number, + void * + ); + +#define SLTIME_DRIVER_TABLE_ENTRY \ + { slt_initialize, NULL, NULL, \ + NULL, NULL, NULL } + +void mpc5200_slt_isr(uint32_t); +rtems_isr mpc5200_slt0_isr(rtems_irq_hdl_param); +rtems_isr mpc5200_slt1_isr(rtems_irq_hdl_param); +void mpc5200_init_slt(uint32_t); +void mpc5200_set_slt_count(uint32_t); +void mpc5200_enable_slt_int(uint32_t); +void mpc5200_disable_slt_int(uint32_t); +uint32_t mpc5200_check_slt_status(uint32_t); +/*void sltOn(const rtems_irq_connect_data *); +void sltOff(const rtems_irq_connect_data *); +int sltIsOn(const rtems_irq_connect_data *);*/ +void Install_slt(rtems_device_minor_number); + +#ifdef __cplusplus +} +#endif + +#endif /* __SLICETIMER_H__ */ diff --git a/bsps/powerpc/gen5200/include/bsp/u-boot-config.h b/bsps/powerpc/gen5200/include/bsp/u-boot-config.h new file mode 100644 index 0000000000..2fee83bce9 --- /dev/null +++ b/bsps/powerpc/gen5200/include/bsp/u-boot-config.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H +#define LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H + +#define CONFIG_MPC5xxx + +#endif /* LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H */ diff --git a/bsps/powerpc/gen5200/include/tm27.h b/bsps/powerpc/gen5200/include/tm27.h new file mode 100644 index 0000000000..ff43cc9ab6 --- /dev/null +++ b/bsps/powerpc/gen5200/include/tm27.h @@ -0,0 +1,66 @@ +/* + * @file + * @ingroup powerpc_gen5200 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <bsp/fatal.h> +#include <bsp/irq.h> + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} + +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + bsp_fatal(MPC5200_FATAL_TM27_IRQ_INSTALL); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 8; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/gen83xx/headers.am b/bsps/powerpc/gen83xx/headers.am new file mode 100644 index 0000000000..39d4333934 --- /dev/null +++ b/bsps/powerpc/gen83xx/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/tsec-config.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen83xx/include/bsp/u-boot-config.h diff --git a/bsps/powerpc/gen83xx/include/bsp.h b/bsps/powerpc/gen83xx/include/bsp.h new file mode 100644 index 0000000000..59fd20de54 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp.h @@ -0,0 +1,163 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + + +#ifndef LIBBSP_POWERPC_GEN83XX_BSP_H +#define LIBBSP_POWERPC_GEN83XX_BSP_H + +#define BSP_FEATURE_IRQ_EXTENSION + +#include <bspopts.h> + +#include <libcpu/powerpc-utility.h> + +#include <bsp/hwreg_vals.h> + +/* + * Some symbols defined in the linker command file. + */ + +LINKER_SYMBOL(bsp_ram_start); +LINKER_SYMBOL(bsp_ram_end); +LINKER_SYMBOL(bsp_ram_size); + +LINKER_SYMBOL(bsp_rom_start); +LINKER_SYMBOL(bsp_rom_end); +LINKER_SYMBOL(bsp_rom_size); + +LINKER_SYMBOL(bsp_section_text_start); +LINKER_SYMBOL(bsp_section_text_end); +LINKER_SYMBOL(bsp_section_text_size); + +LINKER_SYMBOL(bsp_section_data_start); +LINKER_SYMBOL(bsp_section_data_end); +LINKER_SYMBOL(bsp_section_data_size); + +LINKER_SYMBOL(bsp_section_bss_start); +LINKER_SYMBOL(bsp_section_bss_end); +LINKER_SYMBOL(bsp_section_bss_size); + +LINKER_SYMBOL(bsp_interrupt_stack_start); +LINKER_SYMBOL(bsp_interrupt_stack_end); +LINKER_SYMBOL(bsp_interrupt_stack_size); + +LINKER_SYMBOL(bsp_work_area_start); + +LINKER_SYMBOL(IMMRBAR); + +#ifndef ASM + +#include <rtems.h> +#include <bsp/vectors.h> +#include <bsp/irq.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * indicate, that BSP has no IDE driver + */ +#undef RTEMS_BSP_HAS_IDE_DRIVER + +/* misc macros */ +#define BSP_ARRAY_CNT(arr) (sizeof(arr)/sizeof(arr[0])) + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +/* functions */ +rtems_status_code bsp_register_i2c(void); +rtems_status_code bsp_register_spi(void); + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach + +#ifdef MPC83XX_BOARD_MPC8313ERDB + #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec2" + #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec1" +#else + #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" + #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" +#endif + +#if defined(MPC83XX_BOARD_MPC8349EAMDS) +/* + * i2c EEPROM device name + */ +#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" +#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" + +/* + * SPI Flash device name + */ +#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash" +#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash" +#endif /* defined(MPC83XX_BOARD_MPC8349EAMDS) */ + +#if defined(MPC83XX_BOARD_HSC_CM01) +/* + * i2c EEPROM device name + */ +#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" +#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" + +/* + * SPI FRAM device name + */ +#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram" +#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram" +#endif /* defined(MPC83XX_BOARD_HSC_CM01) */ + +extern unsigned int BSP_bus_frequency; + +extern uint32_t bsp_clicks_per_usec; + +/* + * Convert decrementer value to tenths of microseconds (used by shared timer + * driver). + */ +#define BSP_Convert_decrementer( _value ) \ + ((int) (((_value) * 10) / bsp_clicks_per_usec)) + +void mpc83xx_zero_4( void *dest, size_t n); + +void cpu_init( void); + +void bsp_restart(void *addr); + +#if defined(HAS_UBOOT) + /* Routine to obtain U-Boot environment variables */ + const char *bsp_uboot_getenv( + const char *name + ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* GEN83xx */ diff --git a/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h b/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h new file mode 100644 index 0000000000..c7a5bac9c2 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/hwreg_vals.h @@ -0,0 +1,381 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains board specific definitions | +\*===============================================================*/ + + +#ifndef __GEN83xx_HWREG_VALS_h +#define __GEN83xx_HWREG_VALS_h + +#include <mpc83xx/mpc83xx.h> +#include <bsp.h> + +#ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0 + #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB08 | RCWHR_RLEXT_NAND) +#else + #define MPC83XX_RCWHR_BOOT_DEVICE (RCWHR_ROMLOC_LB16 | RCWHR_RLEXT_LGCY) +#endif + +/* + * distinguish board characteristics + */ +#if defined(MPC83XX_BOARD_MPC8349EAMDS) +/* + * for Freescale MPC8349 EAMDS + */ +/* + * two DUART channels supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x03 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 66000000L +#define RCFG_SYSPLL_MF 4 +#define RCFG_COREPLL_MF 4 + +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ + RCWLR_DDRCM_1_1 | \ + RCWLR_SPMF(RCFG_SYSPLL_MF) | \ + RCWLR_COREPLL(RCFG_COREPLL_MF)) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_EN | \ + RCWHR_PCI2ARB_EN | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + MPC83XX_RCWHR_BOOT_DEVICE | \ + RCWHR_TSEC1M_GMII | \ + RCWHR_TSEC2M_GMII | \ + RCWHR_ENDIAN_BIG | \ + RCWHR_LALE_NORM | \ + RCWHR_LDP_PAR) +#elif defined(MPC83XX_BOARD_HSC_CM01) +/* + * for JPK HSC_CM01 + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 30000000L +#define RCFG_SYSPLL_MF 11 +#define RCFG_COREPLL_MF 4 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ + RCWLR_DDRCM_1_1 | \ + RCWLR_SPMF(RCFG_SYSPLL_MF) | \ + RCWLR_COREPLL(RCFG_COREPLL_MF)) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_DIS | \ + RCWHR_PCI2ARB_DIS | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + MPC83XX_RCWHR_BOOT_DEVICE | \ + RCWHR_TSEC1M_RGMII | \ + RCWHR_TSEC2M_GMII | \ + RCWHR_ENDIAN_BIG | \ + RCWHR_LALE_EARLY | \ + RCWHR_LDP_SPC) + +#elif defined(MPC83XX_BOARD_BR_UID) +/* + * for BR UID + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 25000000L +#define RCFG_SYSPLL_MF 5 +#define RCFG_COREPLL_MF 5 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L \ + (RCWLR_LBIUCM_1_1 \ + | RCWLR_DDRCM_2_1 \ + | RCWLR_SPMF(RCFG_SYSPLL_MF) \ + | RCWLR_COREPLL(RCFG_COREPLL_MF) \ + | RCWLR_CEVCOD_1_2 \ + | RCWLR_CEPMF(8) \ + ) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_DIS | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + MPC83XX_RCWHR_BOOT_DEVICE | \ + RCWHR_ENDIAN_BIG) + +#elif defined( HAS_UBOOT) + +/* TODO */ + +#else + +#error "board type not defined" + +#endif + +#if defined(MPC83XX_BOARD_MPC8349EAMDS) +/************************** + * for Freescale MPC83XX_BOARD_MPC8349EAMDS + */ + +/* + * working values for various registers, used in start/start.S + */ + +/* + * Local Access Windows + * FIXME: decode bit settings + */ +#define LBLAWBAR0_VAL 0xFE000000 +#define LBLAWAR0_VAL 0x80000016 +#define LBLAWBAR1_VAL 0xF8000000 +#define LBLAWAR1_VAL 0x8000000E +#define LBLAWBAR2_VAL 0xF0000000 +#define LBLAWAR2_VAL 0x80000019 +#define DDRLAWBAR0_VAL 0x00000000 +#define DDRLAWAR0_VAL 0x8000001B +/* + * Local Bus (Memory) Controller + * FIXME: decode bit settings + */ +#define BR0_VAL 0xFE001001 +#define OR0_VAL 0xFF806FF7 +#define BR1_VAL 0xF8000801 +#define OR1_VAL 0xFFFFE8F0 +#define BR2_VAL 0xF0001861 +#define OR2_VAL 0xFC006901 +/* + * SDRAM registers + * FIXME: decode bit settings + */ +#define MRPTR_VAL 0x20000000 +#define LSRT_VAL 0x32000000 +#define LSDMR_VAL 0x4062D733 +#define LCRR_VAL 0x80000004 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define CS2_BNDS_VAL 0x00000007 +#define CS3_BNDS_VAL 0x0008000F +#define CS2_CONFIG_VAL 0x80000101 +#define CS3_CONFIG_VAL 0x80000101 +#define TIMING_CFG_1_VAL 0x36333321 +#define TIMING_CFG_2_VAL 0x00000800 +#define DDR_SDRAM_CFG_VAL 0xC2000000 +#define DDR_SDRAM_MODE_VAL 0x00000022 +#define DDR_SDRAM_INTTVL_VAL 0x045B0100 +#define DDR_SDRAM_CLK_CNTL_VAL 0x00000000 + +#elif defined(MPC83XX_BOARD_HSC_CM01) +/************************** + * for JPK HSC_CM01 + */ + +/* fpga BCSR register */ +#define FPGA_START 0xF8000000 +#define FPGA_SIZE 0x8000 +#define FPGA_END (FPGA_START+FPGA_SIZE-1) + +/* + * working values for various registers, used in start/start.S + */ + +/* fpga config 16 MB size */ +#define FPGA_CONFIG_START 0xF8000000 +#define FPGA_CONFIG_SIZE 0x01000000 +/* fpga register 8 MB size */ +#define FPGA_REGISTER_START 0xF9000000 +#define FPGA_REGISTER_SIZE 0x00800000 +/* fpga fifo 8 MB size */ +#define FPGA_FIFO_START 0xF9800000 +#define FPGA_FIFO_SIZE 0x00800000 + +#define FPGA_START (FPGA_CONFIG_START) +// fpga window size 32 MByte +#define FPGA_SIZE (0x02000000) +#define FPGA_END (FPGA_START+FPGA_SIZE-1) + +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL bsp_rom_start +#define LBLAWAR0_VAL 0x80000018 +#define LBLAWBAR1_VAL (FPGA_CONFIG_START) +#define LBLAWAR1_VAL 0x80000018 +#define DDRLAWBAR0_VAL bsp_ram_start +#define DDRLAWAR0_VAL 0x8000001B +/* + * Local Bus (Memory) Controller + * FIXME: decode bit settings + */ +#define BR0_VAL (0xFE000000 | 0x01001) +#define OR0_VAL 0xFE000E54 +// fpga config access range (UPM_A) (32 kByte) +#define BR2_VAL (FPGA_CONFIG_START | 0x01881) +#define OR2_VAL 0xFFFF9100 + +// fpga register access range (UPM_B) (8 MByte) +#define BR3_VAL (FPGA_REGISTER_START | 0x018A1) +#define OR3_VAL 0xFF801100 + +// fpga fifo access range (UPM_C) (8 MByte) +#define BR4_VAL (FPGA_FIFO_START | 0x018C1) +#define OR4_VAL 0xFF801100 + +/* + * SDRAM registers + */ +#define MRPTR_VAL 0x20000000 +#define LSRT_VAL 0x32000000 +#define LSDMR_VAL 0x4062D733 +#define LCRR_VAL 0x80010004 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80810102 +#define TIMING_CFG_0_VAL 0x00420802 +#define TIMING_CFG_1_VAL 0x3735A322 +#define TIMING_CFG_2_VAL 0x2F9044C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x44521632 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x63000008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x05080000 + +#elif defined(MPC83XX_BOARD_BR_UID) +/************************** + * for BR UID + */ + +/* + * working values for various registers, used in start/start.S + */ + +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL bsp_rom_start +#define LBLAWAR0_VAL 0x80000018 +#define DDRLAWBAR0_VAL bsp_ram_start +#define DDRLAWAR0_VAL 0x8000001B + + +/* + * clocking for local bus: + * ALE active for 1 clock + * local bus clock = 1/2 csb clock + */ +#define LCRR_VAL 0x80010002 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80014202 +#define TIMING_CFG_0_VAL 0x00220802 +#define TIMING_CFG_1_VAL 0x26259222 +#define TIMING_CFG_2_VAL 0x111048C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x200F1632 +#define DDR_SDRAM_MODE_2_VAL 0x40006000 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x43100008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x01E8222E + +#elif defined( HAS_UBOOT) + +/* TODO */ + +#else + +#error "board type not defined" + +#endif + +/************************** + * derived values for all boards + */ +/* value of input clock divider (derived from pll mode reg) */ +#if MPC83XX_CHIP_TYPE != 8309 + #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1) +#else + /* On the MPC8309 this bit is reserved */ + #define BSP_SYSPLL_CKID 1 +#endif +/* value of system pll (derived from pll mode reg) */ +#define BSP_SYSPLL_MF ((mpc83xx.clk.spmr>>(31-7))&0x0f) +/* value of system pll (derived from pll mode reg) */ +#define BSP_COREPLL_MF ((mpc83xx.clk.spmr>>(31-15))&0x7f) + +#endif /* __GEN83xx_HWREG_VALS_h */ diff --git a/bsps/powerpc/gen83xx/include/bsp/irq.h b/bsps/powerpc/gen83xx/include/bsp/irq.h new file mode 100644 index 0000000000..dc084ed2a2 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/irq.h @@ -0,0 +1,184 @@ +/*===============================================================*\ +| Project: RTEMS generic MPC83xx BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007, 2010 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ + + +#ifndef GEN83xx_IRQ_IRQ_H +#define GEN83xx_IRQ_IRQ_H + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#include <bspopts.h> + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_IPIC_PER_IRQ_NUMBER 128 +#define BSP_IPIC_IRQ_LOWEST_OFFSET 0 +#define BSP_IPIC_IRQ_MAX_OFFSET (BSP_IPIC_IRQ_LOWEST_OFFSET\ + +BSP_IPIC_PER_IRQ_NUMBER-1) + +#define BSP_IS_IPIC_IRQ(irqnum) \ + (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 1 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_IPIC_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_IPIC_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_IPIC_IRQ_FIRST = BSP_IPIC_IRQ_LOWEST_OFFSET, + BSP_IPIC_IRQ_ERROR = BSP_IPIC_IRQ_LOWEST_OFFSET + 0, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_DMA1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 3, + BSP_IPIC_IRQ_UART = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, + BSP_IPIC_IRQ_FLEXCAN = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, +#else + BSP_IPIC_IRQ_UART1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, + BSP_IPIC_IRQ_UART2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, + BSP_IPIC_IRQ_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 11, +#endif + BSP_IPIC_IRQ_I2C1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 14, + BSP_IPIC_IRQ_I2C2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 15, + BSP_IPIC_IRQ_SPI = BSP_IPIC_IRQ_LOWEST_OFFSET + 16, + BSP_IPIC_IRQ_IRQ1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 17, + BSP_IPIC_IRQ_IRQ2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 18, + BSP_IPIC_IRQ_IRQ3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 19, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_QUICC_HI = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, + BSP_IPIC_IRQ_QUICC_LO = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, +#else + BSP_IPIC_IRQ_IRQ4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 20, + BSP_IPIC_IRQ_IRQ5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 21, + BSP_IPIC_IRQ_IRQ6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 22, + BSP_IPIC_IRQ_IRQ7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 23, + BSP_IPIC_IRQ_TSEC1_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, + BSP_IPIC_IRQ_TSEC1_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, + BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34, + BSP_IPIC_IRQ_TSEC2_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 35, + BSP_IPIC_IRQ_TSEC2_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 36, + BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37, +#endif + BSP_IPIC_IRQ_USB_DR = BSP_IPIC_IRQ_LOWEST_OFFSET + 38, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_ESDHC = BSP_IPIC_IRQ_LOWEST_OFFSET + 42, +#else + BSP_IPIC_IRQ_USB_MPH = BSP_IPIC_IRQ_LOWEST_OFFSET + 39, +#endif + BSP_IPIC_IRQ_IRQ0 = BSP_IPIC_IRQ_LOWEST_OFFSET + 48, + BSP_IPIC_IRQ_RTC_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 64, + BSP_IPIC_IRQ_PIT = BSP_IPIC_IRQ_LOWEST_OFFSET + 65, + BSP_IPIC_IRQ_PCI1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 66, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_MSIR1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, +#else + BSP_IPIC_IRQ_PCI2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, +#endif + BSP_IPIC_IRQ_RTC_ALR = BSP_IPIC_IRQ_LOWEST_OFFSET + 68, + BSP_IPIC_IRQ_MU = BSP_IPIC_IRQ_LOWEST_OFFSET + 69, + BSP_IPIC_IRQ_SBA = BSP_IPIC_IRQ_LOWEST_OFFSET + 70, + BSP_IPIC_IRQ_DMA = BSP_IPIC_IRQ_LOWEST_OFFSET + 71, + BSP_IPIC_IRQ_GTM4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 72, + BSP_IPIC_IRQ_GTM8 = BSP_IPIC_IRQ_LOWEST_OFFSET + 73, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_QUICC_PORTS = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, + BSP_IPIC_IRQ_GPIO = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, +#else + BSP_IPIC_IRQ_GPIO1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, + BSP_IPIC_IRQ_GPIO2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, +#endif + BSP_IPIC_IRQ_DDR = BSP_IPIC_IRQ_LOWEST_OFFSET + 76, + BSP_IPIC_IRQ_LBC = BSP_IPIC_IRQ_LOWEST_OFFSET + 77, + BSP_IPIC_IRQ_GTM2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 78, + BSP_IPIC_IRQ_GTM6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 79, + BSP_IPIC_IRQ_PMC = BSP_IPIC_IRQ_LOWEST_OFFSET + 80, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_MSIR2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 81, + BSP_IPIC_IRQ_MSIR3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 82, +#else + BSP_IPIC_IRQ_GTM3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 84, + BSP_IPIC_IRQ_GTM7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 85, +#endif +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_MSIR4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 86, + BSP_IPIC_IRQ_MSIR5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 87, + BSP_IPIC_IRQ_MSIR6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 88, + BSP_IPIC_IRQ_MSIR7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 89, +#endif + BSP_IPIC_IRQ_GTM1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 90, + BSP_IPIC_IRQ_GTM5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 91, +#if MPC83XX_CHIP_TYPE / 10 == 830 + BSP_IPIC_IRQ_DMA1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 94, + BSP_IPIC_IRQ_DPTC = BSP_IPIC_IRQ_LOWEST_OFFSET + 95, +#endif + + BSP_IPIC_IRQ_LAST = BSP_IPIC_IRQ_MAX_OFFSET, + } rtems_irq_symbolic_name; + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask); + +#define MPC83XX_IPIC_INTERRUPT_NORMAL 0 + +#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1 + +#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2 + +rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type); + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* GEN83XX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/gen83xx/include/bsp/tsec-config.h b/bsps/powerpc/gen83xx/include/bsp/tsec-config.h new file mode 100644 index 0000000000..5ec0ccbad1 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/tsec-config.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H +#define LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TSEC_COUNT 2 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H */ diff --git a/bsps/powerpc/gen83xx/include/bsp/u-boot-config.h b/bsps/powerpc/gen83xx/include/bsp/u-boot-config.h new file mode 100644 index 0000000000..c2271c965b --- /dev/null +++ b/bsps/powerpc/gen83xx/include/bsp/u-boot-config.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H +#define LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H + +#define CONFIG_MPC83xx +#define CONFIG_HAS_ETH1 + +#endif /* LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H */ diff --git a/bsps/powerpc/gen83xx/include/tm27.h b/bsps/powerpc/gen83xx/include/tm27.h new file mode 100644 index 0000000000..22787473a5 --- /dev/null +++ b/bsps/powerpc/gen83xx/include/tm27.h @@ -0,0 +1,62 @@ +/** + * @file + * + * @brief Support file for Timer Test 27. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 + #error "This is an RTEMS internal file you must not include directly." +#endif /* _RTEMS_TMTEST27 */ + +#ifndef TMTESTS_TM27_H +#define TMTESTS_TM27_H + +#include <libcpu/powerpc-utility.h> +#include <bsp/vectors.h> + +#define MUST_WAIT_FOR_INTERRUPT 1 + +static void (*tm27_interrupt_handler)(rtems_vector_number); + +static int tm27_exception_handler( BSP_Exception_frame *frame, unsigned number) +{ + (*tm27_interrupt_handler)( 0); + + return 0; +} + +void Install_tm27_vector( void (*handler)(rtems_vector_number)) +{ + int rv = 0; + + tm27_interrupt_handler = handler; + + rv = ppc_exc_set_handler( ASM_DEC_VECTOR, tm27_exception_handler); + if (rv < 0) { + printk( "Error installing clock interrupt handler!\n"); + } +} + +#define Cause_tm27_intr() \ + ppc_set_decrementer_register( 8) + +#define Clear_tm27_intr() \ + ppc_set_decrementer_register( UINT32_MAX) + +#define Lower_tm27_intr() \ + (void) ppc_external_exceptions_enable() + +#endif /* TMTESTS_TM27_H */ diff --git a/bsps/powerpc/haleakala/headers.am b/bsps/powerpc/haleakala/headers.am new file mode 100644 index 0000000000..ed8becdf81 --- /dev/null +++ b/bsps/powerpc/haleakala/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/mmu_405.h +include_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/haleakala/include/bsp/irq.h diff --git a/bsps/powerpc/haleakala/include/bsp.h b/bsps/powerpc/haleakala/include/bsp.h new file mode 100644 index 0000000000..b26e739e60 --- /dev/null +++ b/bsps/powerpc/haleakala/include/bsp.h @@ -0,0 +1,87 @@ +/* bsp.h + * + * Generic 405EX bsp.h + * derived from virtex/include/bsp.h + * by Michael Hamel ADInstruments Ltd 2008 + * + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * + */ + +#ifndef LIBBSP_POWERPC_HALEAKALA_BSP_H +#define LIBBSP_POWERPC_HALEAKALA_BSP_H + +#include <bspopts.h> + +#ifdef ASM + + + /* Definition of where to store registers in alignment handler */ + #define ALIGN_REGS 0x0140 + +#else + + #include <rtems.h> + #include <libcpu/io.h> + #include <bsp/irq.h> + #include <bsp/vectors.h> + #include <bsp/default-initial-extension.h> + + #ifdef __cplusplus + extern "C" { + #endif + + /* Network Defines */ + #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + + struct rtems_bsdnet_ifconfig; + int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching); + #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach + + #define BSP_UART_IOBASE_COM1 0xEF600200 /* PPC405EX */ + #define BSP_UART_IOBASE_COM2 0xEF600300 + + #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ + + #define BSP_UART_BAUD_BASE (11059200 / 16) /* Kilauea ext clock, max speed */ + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* BSP_H */ diff --git a/bsps/powerpc/haleakala/include/bsp/irq.h b/bsps/powerpc/haleakala/include/bsp/irq.h new file mode 100644 index 0000000000..c413ec3172 --- /dev/null +++ b/bsps/powerpc/haleakala/include/bsp/irq.h @@ -0,0 +1,166 @@ +/*===============================================================*\ +| Project: RTEMS Haleakala BSP | +| by Michael Hamel ADInstruments Ltd 2008 | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | +\*===============================================================*/ + + +#ifndef Haleakala_IRQ_IRQ_H +#define Haleakala_IRQ_IRQ_H + +/* Implemented for us in bsp_irq_dispatch_list */ +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#include <rtems/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + + /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. + These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ + + /* + + #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC_IRQ_NUMBER (32) + + */ + /* PPC405EX interrupt vectors */ + #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9) + #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10) + #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) + #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12) + #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13) + #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14) + #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15) + #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32) + #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4) + #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5) + #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6) + #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) + #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) + #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) + + #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) + #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) + #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) + #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19) + #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20) + #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21) + #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22) + #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23) + #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24) + #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25) + #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26) + #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27) + #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28) + #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29) + #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30) + #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31) + + #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64) + #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0) + #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1) + #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) + #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) + #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) + + #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) + + #define BSP_UIC_IRQ_NUMBER (95) + + + #define BSP_UIC_IRQ_LOWEST_OFFSET 0 + #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1) + + #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */ + #define BSP_UART_COM2_IRQ BSP_UIC_UART1 + + /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */ + + #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ + #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 + #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + + #define BSP_PROCESSOR_IRQ_NUMBER (3) + #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) + #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + + /* Summary and totals */ + + #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) + #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) + #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c + #include <bsp/irq_supp.h> + + #ifdef __cplusplus + } + #endif +#endif /* ASM */ + +#endif /* Haleakala_IRQ_IRQ_H */ diff --git a/bsps/powerpc/haleakala/include/mmu_405.h b/bsps/powerpc/haleakala/include/mmu_405.h new file mode 100644 index 0000000000..e11cfa7738 --- /dev/null +++ b/bsps/powerpc/haleakala/include/mmu_405.h @@ -0,0 +1,77 @@ +#ifndef _mmu_405_h +#define _mmu_405_h + +/* + Simple interface to the PowerPC 405 MMU + + The intention here is just to allow the MMU to be used to define cacheability and + read/write/execute permissions in a simple enough way to fit entirely into the + 64-entry TLB cache. + + This code does not do address relocation and does not generate any MMU-related interrupts. + + The process ID support is there for a possible future extension where RTEMS supports + setting the process ID on task switches, which allows per-process stack protection + + This code will call fatal_error() if your add_space() calls overrun the 64 entries + + Michael Hamel ADInstruments 2008 + +*/ + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stdint.h" + +enum { + kAllProcessIDs = 0 +}; + +typedef enum MMUAccessType { + executable, + readOnlyData, + readOnlyNoCache, + readWriteData, + readWriteNoCache, + readWriteExecutable +} MMUAccessType; + +/* Initialise and clear the MMU */ +void mmu_initialise(); + +/* Turn on/off data access translation */ +bool mmu_enable_data(bool enable); + +/* Turn on instruction translation */ +bool mmu_enable_code(bool enable); + +/* Define properties for an area of memory (must be 1K-aligned) */ +void mmu_add_space(uint32_t startAddr, uint32_t endAddr, MMUAccessType permissions, uint8_t processID); + +/* Delete a memory property definition */ +void mmu_remove_space(uint32_t startAddr, uint32_t endAddr); + +/* Return number of TLB entries out of total in use */ +int mmu_get_tlb_count(); + +/* Allocate a new process ID and return it */ +uint8_t mmu_new_processID(); + +/* Free a process ID that has been in use */ +void mmu_free_processID(uint8_t freeThis); + +/* Return the current process ID */ +uint8_t mmu_current_processID(); + +/* Change the process ID to ID and return the old value */ +uint8_t mmu_set_processID(uint8_t toID); + + +#ifdef __cplusplus +} +#endif + +#endif //_mmu_405.h
\ No newline at end of file diff --git a/bsps/powerpc/haleakala/include/tm27.h b/bsps/powerpc/haleakala/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/haleakala/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/headers.am b/bsps/powerpc/headers.am new file mode 100644 index 0000000000..5033d8ae5a --- /dev/null +++ b/bsps/powerpc/headers.am @@ -0,0 +1,101 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../bsps/powerpc/include/ictrl.h +include_HEADERS += ../../../../../bsps/powerpc/include/mpc5xx.h +include_HEADERS += ../../../../../bsps/powerpc/include/mpc8260.h +include_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx.h +include_HEADERS += ../../../../../bsps/powerpc/include/nvram.h +include_HEADERS += ../../../../../bsps/powerpc/include/tty_drv.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/consoleIo.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/flashPgm.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/flashPgmPvt.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/irq_supp.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/linker-symbols.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/motorola.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/openpic.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/pci.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/pnp.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/residual.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/start.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/tictac.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/tsec.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/u-boot-board-info.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/uart.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/vectors.h +include_bsp_HEADERS += ../../../../../bsps/powerpc/include/bsp/vpd.h + +include_libcpudir = $(includedir)/libcpu +include_libcpu_HEADERS = +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/bat.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/byteorder.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/c_clock.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/cpuIdent.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/e500_mmu.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/io.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/irq.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/mmu.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/page.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/pgtable.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/powerpc-utility.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/pte121.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/raw_exception.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/spr.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/stackTrace.h +include_libcpu_HEADERS += ../../../../../bsps/powerpc/include/libcpu/vectors.h + +include_mpc55xxdir = $(includedir)/mpc55xx +include_mpc55xx_HEADERS = +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/dspi.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/edma.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/emios.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc551x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc555x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc556x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc5668.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/fsl-mpc567x.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/mpc55xx.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/reg-defs.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/regs-edma.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/regs-mmu.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/regs.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/siu.h +include_mpc55xx_HEADERS += ../../../../../bsps/powerpc/include/mpc55xx/watchdog.h + +include_mpc5xxdir = $(includedir)/mpc5xx +include_mpc5xx_HEADERS = +include_mpc5xx_HEADERS += ../../../../../bsps/powerpc/include/mpc5xx/console.h + +include_mpc8260dir = $(includedir)/mpc8260 +include_mpc8260_HEADERS = +include_mpc8260_HEADERS += ../../../../../bsps/powerpc/include/mpc8260/console.h +include_mpc8260_HEADERS += ../../../../../bsps/powerpc/include/mpc8260/cpm.h +include_mpc8260_HEADERS += ../../../../../bsps/powerpc/include/mpc8260/mmu.h + +include_mpc83xxdir = $(includedir)/mpc83xx +include_mpc83xx_HEADERS = +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/gtm.h +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/mpc83xx.h +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h +include_mpc83xx_HEADERS += ../../../../../bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h + +include_mpc8xxdir = $(includedir)/mpc8xx +include_mpc8xx_HEADERS = +include_mpc8xx_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx/console.h +include_mpc8xx_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx/cpm.h +include_mpc8xx_HEADERS += ../../../../../bsps/powerpc/include/mpc8xx/mmu.h + +include_ppc4xxdir = $(includedir)/ppc4xx +include_ppc4xx_HEADERS = +include_ppc4xx_HEADERS += ../../../../../bsps/powerpc/include/ppc4xx/ppc405ex.h +include_ppc4xx_HEADERS += ../../../../../bsps/powerpc/include/ppc4xx/ppc405gp.h + +include_rtems_powerpcdir = $(includedir)/rtems/powerpc +include_rtems_powerpc_HEADERS = +include_rtems_powerpc_HEADERS += ../../../../../bsps/powerpc/include/rtems/powerpc/cache.h +include_rtems_powerpc_HEADERS += ../../../../../bsps/powerpc/include/rtems/powerpc/debugmod.h +include_rtems_powerpc_HEADERS += ../../../../../bsps/powerpc/include/rtems/powerpc/powerpc.h diff --git a/bsps/powerpc/include/bsp/consoleIo.h b/bsps/powerpc/include/bsp/consoleIo.h new file mode 100644 index 0000000000..e62c9d143c --- /dev/null +++ b/bsps/powerpc/include/bsp/consoleIo.h @@ -0,0 +1,38 @@ +/* + * consoleIo.h -- console I/O package interface + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef __CONSOLE_IO_H +#define __CONSOLE_IO_H + +typedef enum { + CONSOLE_LOG = 1, + CONSOLE_SERIAL = 2, + CONSOLE_VGA = 3, + CONSOLE_VACUUM = 4 +}ioType; + +typedef volatile unsigned char * __io_ptr; + +typedef struct { + __io_ptr io_base; + __io_ptr isa_mem_base; +} board_memory_map; + +extern board_memory_map *ptr_mem_map; + +extern int select_console(ioType t); +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern void debug_putc(const unsigned char c); +extern void debug_putc_onlcr(const char c); +extern int debug_getc(void); +extern int debug_tstc(void); +int kbdreset(void); + +#endif diff --git a/bsps/powerpc/include/bsp/flashPgm.h b/bsps/powerpc/include/bsp/flashPgm.h new file mode 100644 index 0000000000..19f2c4708e --- /dev/null +++ b/bsps/powerpc/include/bsp/flashPgm.h @@ -0,0 +1,209 @@ +#ifndef BSP_FLASH_PGM_API_H +#define BSP_FLASH_PGM_API_H + +/* Trivial Flash Programmer */ + +/* Author: Till Straumann <strauman@slac.stanford.edu>, 2006 + * NOTE: copyright info at the bottom of this file + */ + +/* IMPORTANT NOTE + * + * The flash API is NOT THREAD SAFE. During the execution of any of the + * BSP_flashXXX() routines, flash (residing in the same device) + * MUST NOT be accessed by other threads in ANY way (NOT EVEN READ!). + * Read operations may return internal device register contents + * instead of memory array data when issued while a flash device + * is erased, written or queried by the library. + * + * The routines are intended for occasional maintenance use only + * (i.e., not for implementing a file system or similar). + * + * While polling for the completion of block erase operations the + * CPU is yielded to other threads. Busy waiting (interrupts and + * thread dispatching remain enabled) on write operations is employed. + */ + +#include <stdio.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/* Disengage flash write protection. Write protection is implemented + * at the board or chipset level by disabling all write operations/bus cycles + * to the flash device(s). + * With write protection enabled, nothing but 'ordinary' (array) read operations + * are possible. + * Write protection must be disabled not only to erase and write contents + * but also in order to read ID, size, status etc. + * None of the operations (except for BSP_flashWriteEnable()) are possible + * on a write-protected device. + * + * 'bank': flash bank # (usually 0) + * RETURNS: 0 on success, nonzero on error (printing message to stderr). + * + * NOTES: - some boards (MVME5500) don't support 'bank' granularity but + * enable/disable write protection for all devices at once. + * - a jumper-based protection mechanism might be in place + * in addition to the software-based one. Consult the user's + * manual of your board for more information. + */ +int +BSP_flashWriteEnable(int bank); + +/* Engage flash write protection (see above) + */ +int +BSP_flashWriteDisable(int bank); + +/* Erase a region of flash memory. + * 'bank': flash bank # (usually 0). + * 'offset': destination address offset (from start of bank). + * 'size': number of bytes to erase. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * RETURNS: 0 on success, nonzero on error (printing messages to stderr). + * + * NOTES: - 'offset' and 'size' must be block-aligned. Common 16-bit devices + * have a block size of 0x20000 bytes. If two such devices are + * operated in parallel to form a 32-bit word then the 'effective' + * block size is 0x40000 bytes. The block size can be queried by + * BSP_flashBlockSize(int bank); + * + * - erase operation is verified. + */ +int +BSP_flashErase(int bank, uint32_t offset, uint32_t size, int quiet); + +/* Write data from a buffer to flash. The target area is erased if necessary. + * + * 'bank': flash bank # (usually 0). + * 'offset': destination address offset (from start of bank). + * 'src': data source block address (in memory). + *'n_bytes': number of bytes to copy. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * NOTES: - Erase operations are only performed where necessary. I.e., + * if one or both of the boundaries of the destination region is/are + * not block-aligned then adjacent data are preserved provided that + * the relevant chunks of the destination are blank (erased). + * + * | <neighbour> fffffff | + * ^--- destination ----- ^ + * | : block boundary + * f : blank/erased pieces + * + * (If the start of the destination region up to the next block boundary + * is blank then '<neighbour>'-data is preserved. The end of the + * destination is treated the same way.) + * + * - user confirmation is requested before changes are made + * + * - 'src' must not point into the destination bank (no copy + * within a flash bank). + * + * - erase and write operations are verified. + * + * RETURNS: 0 on success, nonzero on error (message printed to stderr). + */ +int +BSP_flashWrite(int bank, uint32_t offset, const char *src, uint32_t n_bytes, int quiet); + +/* Copy contents of a file to flash. + * + * 'fname': Path of a file. + * 'quiet': if non-zero, suppress confirmation message / prompt + * if > 1 also suppress the progress indicator. + * + * NOTES: Convenience wrapper around BSP_flashWrite(); see above for + * args and return value. + */ +int +BSP_flashWriteFile(int bank, uint32_t offset, const char *path, int quiet); + +/* Dump info about available flash to file + * (stdout is used if f==NULL). + * + * RETURNS: 0 + * NOTES: Write protection must be disengaged (see above); + */ +int +BSP_flashDumpInfo(FILE *f); + +/* + * Obtain starting-address of flash bank (as seen from CPU) + * (returns ((uint32_t) -1) if the bank argument is invalid). + */ + +uint32_t +BSP_flashStart(int bank); + +/* + * Obtain size of flash bank (returns ((uint32_t) -1) if the + * bank argument is invalid). + */ +uint32_t +BSP_flashSize(int bank); + +/* + * Obtain block size of flash bank (sector size times + * number of devices in parallel; the block size determines + * alignment and granularity accepted by BSP_flashErase() + * (returns ((uint32_t) -1) if the bank argument is invalid). + */ +uint32_t +BSP_flashBlockSize(int bank); + +#ifdef __cplusplus + } +#endif + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#endif diff --git a/bsps/powerpc/include/bsp/flashPgmPvt.h b/bsps/powerpc/include/bsp/flashPgmPvt.h new file mode 100644 index 0000000000..c26b8ed01d --- /dev/null +++ b/bsps/powerpc/include/bsp/flashPgmPvt.h @@ -0,0 +1,274 @@ +#ifndef FLASH_GLUE_INTERFACE_H +#define FLASH_GLUE_INTERFACE_H + + +/* Trivial flash programmer (for restrictions see below) */ + +/* Author: Till Straumann <strauman@slac.stanford.edu>, 2006 */ + +/* DO NOT INCLUDE THIS HEADER FROM APPLICATION CODE */ + +/* + * Glue interface -- to be used only internally by BSP + * and chip drivers: + * - BSP provides info about what chip drivers to use + * as well as 'wiring' info (how many devices are + * operated in parallel etc). + * - Chip drivers provide low-level 'methods' / 'ops' + * for performing basic operations which are used + * by the code in 'flash.c'. + */ + +/* To keep things simple, this API makes a few assumptions about the + * hardware: + * + * - devices operate with 16-bit data width + * - two devices are used in parallel (stride 4) to + * provide 32-bit data. I.e., the devices are + * organized like this: + * unsigned short flash[FLASH_SIZE][2]; + * - no endianness issues (i.e., flash endianness == CPU endianness) + * - fixed block size + * - fixed buffer size + * - all devices in a bank are identical + * - NOT THREAD SAFE; no locking scheme is implemented. + * - cannot copy within same flash bank. + * - write-timeout uses polling/busy-wait + * + * FIXME: code should be revised to remove assumptions on stride and 16-bit + * width to make it more generic. + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <stdint.h> + +#define NumberOf(arr) (sizeof(arr)/sizeof(arr[0])) + +#define FLASH_STRIDE(b) 4 /* bytes; currently fixed */ +#define FLASH_WIDTH(b) ((b)->width) +#define FLASH_NDEVS(b) (FLASH_STRIDE(b)/FLASH_WIDTH(b)) + +/* Type declarations */ + +/* Registers */ +typedef uint8_t _u8_a_t __attribute__((may_alias)); +typedef uint16_t _u16_a_t __attribute__((may_alias)); +typedef uint32_t _u32_a_t __attribute__((may_alias)); + +/* Register addresses */ +typedef volatile _u8_a_t *A8; +typedef volatile _u16_a_t *A16; +typedef volatile _u32_a_t *A32; + +struct flash_bank_ops; + +/* + * Description of a flash bank. Multiple + * devices that are used in parallel to + * make up words of FLASH_STRIDE bytes + * are a 'physical' bank. + * + * A bank can even be a 'logical' bank + * if it includes chip-select logic, i.e., + * int can contain multiple adjacent + * 'physical' banks + * + * The BSP must provide an array of 'bankdesc' + * structs and it must initialize the fields + * + * 'start' + * size of bank; may be set to zero to instruct + * the driver to scan a bank of 'max_size' for + * devices (i.e., bank may not be fully populated) + * 'max_size' + * size of fully populated bank (defines address range + * that is scanned for devices). + * If 'max_size' is negative then scanning starts from + * the top rather than from the bottom. + * 'width' + * width of a single device (in bytes). E.g., if + * 2 16-bit devices are used to form a (ATM fixed) + * stride of 4 then 'width = 2'. If four 8-bit + * devices are employed then 'width=1'. + * 'knownVendors' + * array of vendors descriptions to use for scanning + * the bank. + * + */ +struct bankdesc { + uint32_t start; /* start of bank (CPU address) */ + uint32_t size; /* in bytes (figured out automatically) */ + int max_size; /* in case multiple banks are adjacent; + * if max_size < 0 then the bank is scanned + * backwards (from top->bottom) for devices + */ + int width; /* FIXME there might be implicit assumptions still + * that width == 2 + */ + struct vendesc *knownVendors; + /* TODO: we assume identical devices within a bank... */ + + /* The next three variables cache information obtained + * from the applicable vendor and device descriptions. + * They are written by BSP_flashCheckId(). + */ + uint32_t fblksz; /* block size in bytes; includes counting + * parallel 16-bit devices, i.e., if a + * single device has a block-size of xxx + * then fblksz = xxx*ndevs. + */ + struct devdesc *dd; + struct flash_bank_ops *ops; +}; + +struct devdesc { + uint32_t id; /* numerical ID (matched against + * ID read from device). + */ + char *name; /* informational name */ + uint32_t size; /* bytes */ + uint32_t bufsz; /* size of write buffer (bytes) */ + uint32_t fblksz; /* sector/block size (bytes) */ +}; + +struct vendesc { + uint32_t id; /* numerical ID (matched against + * ID read from device). + */ + char *name; /* informational name */ + + /* array of supported devices; + * the 'ops' specified below + * are used to access these devices + */ + struct devdesc *known_devs; + /* access methods for talking to + * devices associated with this + * vendor description. + */ + struct flash_bank_ops *ops; +}; + +/* Device Access Methods ('ops'); these must be + * implemented by low-level chip drivers + */ + +struct flash_bank_ops { +/* Read vendor/device ID; Return 0 on success, nonzero if unable to read id */ + int (*get_id)(struct bankdesc *b, uint32_t addr, uint32_t *pVendorId, uint32_t *pDeviceId); +/* Unlock block holding 'addr'ess + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + + void (*unlock_block)(struct bankdesc *b, uint32_t addr); +/* Lock block holding 'addr'ess + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + + void (*lock_block)(struct bankdesc *b, uint32_t addr); +/* Erase single block holding 'addr'ess. The routine may + * assume that the address is block/sector aligned. + * + * RETURNS: zero on error, device status on failure. + * + * NOTES: - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + int (*erase_block)(struct bankdesc *b, uint32_t addr); +/* Query the status of the device and assert it's readiness + * leave off in array-reading mode. + * + * RETURNS: 0 on success, error status (result of status query) on error. + * + * NOTES: - error message is printed to stderr. + * - device switched back to array mode on exit. + * - 'addr' must be 32-bit aligned. + */ + uint32_t (*check_ready)(struct bankdesc *b, uint32_t addr); +/* Dump status bits (F_CMD_RD_STA results); + * 'verbose' prints non-error bits, too + */ + void (*print_stat)(struct bankdesc *b, uint32_t sta, int verbose); +/* Switch to array mode; 'addr' can be assumed to be stride-aligned */ + void (*array_mode)(struct bankdesc *b, uint32_t addr); +/* Write N bytes from 'src' to flash: + * 'src[0] .. src[N-1]' -> addr[0]..addr[N-1]. + * N may be assumed to be a multiple of 'stride' + * RETURNS: failure status or zero on success. + */ + uint32_t (*write_line)(struct bankdesc *b, uint32_t addr, const char *src, uint32_t N); +}; + +/* BSP ops (detect banks, handle write-protection on board); + * these must be implemented by the BSP. + */ + +struct flash_bsp_ops { +/* Return descriptor for bank # 'bank' or NULL (invalid arg) */ + struct bankdesc *(*bankcheck)(int bank, int quiet); +/* set (enbl:1), clear (enbl:0) or query (enbl:-1) + * on-board write protection. + * + * RETURNS 0 on success, nonzero on error. + */ + int (*flash_wp)(int bank, int enbl); +/* read a running us clock (for polling timeout) */ + uint32_t (*read_us_timer)(); +}; + +/* This must be provided by the BSP */ +extern struct flash_bsp_ops BSP_flashBspOps; + +/* Available low-level flash drivers, so far */ +extern struct vendesc BSP_flash_vendor_intel[]; +extern struct vendesc BSP_flash_vendor_spansion[]; + +#endif diff --git a/bsps/powerpc/include/bsp/irq_supp.h b/bsps/powerpc/include/bsp/irq_supp.h new file mode 100644 index 0000000000..65af48c87f --- /dev/null +++ b/bsps/powerpc/include/bsp/irq_supp.h @@ -0,0 +1,124 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef IRQ_SHARED_IRQ_C_GLUE_H +#define IRQ_SHARED_IRQ_C_GLUE_H +/* + * This header describes the routines that are needed by the shared + * version of 'irq.c' (implementing the RTEMS irq API). They + * must be provided by the BSP. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef BSP_SHARED_HANDLER_SUPPORT +#define BSP_SHARED_HANDLER_SUPPORT 1 +#endif + +#include <rtems.h> +#include <rtems/irq.h> + +#include <bsp/vectors.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * PIC-independent functions to enable/disable interrupt lines at + * the pic. + * + * NOTE: the routines must ignore requests for enabling/disabling + * interrupts that are outside of the range handled by the + * PIC(s). + */ +extern void BSP_enable_irq_at_pic(const rtems_irq_number irqLine); +/* + * RETURNS: nonzero (> 0 ) if irq was enabled originally, zero if irq + * was off and negative value if there was an error. + */ +extern int BSP_disable_irq_at_pic(const rtems_irq_number irqLine); + +/* + * Initialize the PIC. + */ +extern int BSP_setup_the_pic(rtems_irq_global_settings* config); + +/* IRQ dispatcher to be defined by the PIC driver; note that it MUST + * implement shared interrupts. + * Note also that the exception frame passed to this handler is not very + * meaningful. Only the volatile registers and vector info are stored. + * + ******************************************************************* + * The routine must return zero if the interrupt was handled. If a + * nonzero value is returned the dispatcher may panic and flag an + * uncaught exception. + ******************************************************************* + */ +int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum); + +/* + * Snippet to be used by PIC drivers and by bsp_irq_dispatch_list + * traverses list of shared handlers for a given interrupt + * + */ + +static inline void +bsp_irq_dispatch_list_base( + rtems_irq_connect_data *tbl, + unsigned irq, + rtems_irq_hdl sentinel +) +{ + rtems_irq_connect_data* vchain; + for( vchain = &tbl[irq]; + ((intptr_t)vchain != -1 && vchain->hdl != sentinel); + vchain = (rtems_irq_connect_data*)vchain->next_handler ) + { + vchain->hdl(vchain->handle); + } +} + + +/* + * Snippet to be used by PIC drivers; + * enables interrupts, traverses list of + * shared handlers for a given interrupt + * and restores original irq level + * + * Note that _ISR_Get_level() & friends are preferable to + * manipulating MSR directly. + */ + +static inline void +bsp_irq_dispatch_list( + rtems_irq_connect_data *tbl, + unsigned irq, + rtems_irq_hdl sentinel +) +{ + register uint32_t l_orig; + + l_orig = _ISR_Get_level(); + + /* Enable all interrupts */ + _ISR_Set_level(0); + + + bsp_irq_dispatch_list_base( tbl, irq, sentinel ); + + /* Restore original level */ + _ISR_Set_level(l_orig); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/include/bsp/linker-symbols.h b/bsps/powerpc/include/bsp/linker-symbols.h new file mode 100644 index 0000000000..de7a6c483d --- /dev/null +++ b/bsps/powerpc/include/bsp/linker-symbols.h @@ -0,0 +1,139 @@ +/** + * @file + * + * @ingroup powerpc_linker + * + * @brief Symbols defined in linker command base file. + */ + +/* + * Copyright (c) 2010, 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H +#define LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H + +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup powerpc_linker Linker Support + * + * @ingroup powerpc_shared + * + * @brief Linker support. + * + * @{ + */ + +LINKER_SYMBOL(bsp_section_start_begin) +LINKER_SYMBOL(bsp_section_start_end) +LINKER_SYMBOL(bsp_section_start_size) + +LINKER_SYMBOL(bsp_section_fast_text_begin) +LINKER_SYMBOL(bsp_section_fast_text_end) +LINKER_SYMBOL(bsp_section_fast_text_size) +LINKER_SYMBOL(bsp_section_fast_text_load_begin) +LINKER_SYMBOL(bsp_section_fast_text_load_end) + +LINKER_SYMBOL(bsp_section_text_begin) +LINKER_SYMBOL(bsp_section_text_end) +LINKER_SYMBOL(bsp_section_text_size) +LINKER_SYMBOL(bsp_section_text_load_begin) +LINKER_SYMBOL(bsp_section_text_load_end) + +LINKER_SYMBOL(bsp_section_rodata_begin) +LINKER_SYMBOL(bsp_section_rodata_end) +LINKER_SYMBOL(bsp_section_rodata_size) +LINKER_SYMBOL(bsp_section_rodata_load_begin) +LINKER_SYMBOL(bsp_section_rodata_load_end) + +LINKER_SYMBOL(bsp_section_fast_data_begin) +LINKER_SYMBOL(bsp_section_fast_data_end) +LINKER_SYMBOL(bsp_section_fast_data_size) +LINKER_SYMBOL(bsp_section_fast_data_load_begin) +LINKER_SYMBOL(bsp_section_fast_data_load_end) + +LINKER_SYMBOL(bsp_section_data_begin) +LINKER_SYMBOL(bsp_section_data_end) +LINKER_SYMBOL(bsp_section_data_size) +LINKER_SYMBOL(bsp_section_data_load_begin) +LINKER_SYMBOL(bsp_section_data_load_end) + +LINKER_SYMBOL(bsp_section_bss_begin) +LINKER_SYMBOL(bsp_section_bss_end) +LINKER_SYMBOL(bsp_section_bss_size) + +LINKER_SYMBOL(bsp_section_sbss_begin) +LINKER_SYMBOL(bsp_section_sbss_end) +LINKER_SYMBOL(bsp_section_sbss_size) + +LINKER_SYMBOL(bsp_section_rwextra_begin) +LINKER_SYMBOL(bsp_section_rwextra_end) +LINKER_SYMBOL(bsp_section_rwextra_size) + +LINKER_SYMBOL(bsp_section_work_begin) +LINKER_SYMBOL(bsp_section_work_end) +LINKER_SYMBOL(bsp_section_work_size) + +LINKER_SYMBOL(bsp_section_stack_begin) +LINKER_SYMBOL(bsp_section_stack_end) +LINKER_SYMBOL(bsp_section_stack_size) + +LINKER_SYMBOL(bsp_section_nocache_begin) +LINKER_SYMBOL(bsp_section_nocache_end) +LINKER_SYMBOL(bsp_section_nocache_size) +LINKER_SYMBOL(bsp_section_nocache_load_begin) +LINKER_SYMBOL(bsp_section_nocache_load_end) + +LINKER_SYMBOL(bsp_section_nocachenoload_begin) +LINKER_SYMBOL(bsp_section_nocachenoload_end) +LINKER_SYMBOL(bsp_section_nocachenoload_size) + +LINKER_SYMBOL(bsp_section_nocacheheap_begin) +LINKER_SYMBOL(bsp_section_nocacheheap_end) +LINKER_SYMBOL(bsp_section_nocacheheap_size) + +LINKER_SYMBOL(bsp_section_nvram_begin) +LINKER_SYMBOL(bsp_section_nvram_end) +LINKER_SYMBOL(bsp_section_nvram_size) + +#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) + +#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) + +#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) + +#define BSP_NOCACHE_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nocache." # subsection))) + +#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) + +#define BSP_NOCACHENOLOAD_SUBSECTION(subsection) \ + __attribute__((section(".bsp_noload_nocache." # subsection))) + +#define BSP_NVRAM_SECTION __attribute__((section(".bsp_nvram"))) + +#define BSP_NVRAM_SUBSECTION(subsection) \ + __attribute__((section(".bsp_nvram." # subsection))) + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H */ diff --git a/bsps/powerpc/include/bsp/motorola.h b/bsps/powerpc/include/bsp/motorola.h new file mode 100644 index 0000000000..14360d56d1 --- /dev/null +++ b/bsps/powerpc/include/bsp/motorola.h @@ -0,0 +1,69 @@ +/* motorola.h + * + * This include file describe the data structure and the functions implemented + * by rtems to identify motorola boards. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H +#define LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H + +#include <bsp/residual.h> +#include <bsp/pci.h> + +typedef enum { + PREP_IBM = 0, + PREP_Radstone = 1, + PREP_Motorola = 2 +} prep_t; + +typedef enum { + MVME_2400 = 0, + MVME_2400_750 = 1, + GENESIS = 2, + POWERSTACK_E = 3, + BLACKAWK = 4, + OMAHA = 5, + UTAH = 6, + POWERSTACK_EX = 7, + MESQUITE = 8, + SITKA = 9, + MESQUITE_W_HAC = 10, + MTX_PLUS = 11, + MTX_WO_PP = 12, + MTX_W_PP = 13, + MVME_2300 = 14, + MVME_2300SC_2600 = 15, + MVME_2600_W_MVME712M = 16, + MVME_2600_2700_W_MVME761 = 17, + MVME_3600_W_MVME712M = 18, + MVME_3600_W_MVME761 = 19, + MVME_1600 = 20, + /* In the table, slot 21 is the marker for end of automatic probe and scan */ + MVME_2100 = 22, + MOTOROLA_UNKNOWN = 255 +} motorolaBoard; + +typedef enum { + HOST_BRIDGE_RAVEN = 0, + HOST_BRIDGE_HAWK = 1, + HOST_BRIDGE_UNKNOWN = 255 +} motorolaHostBridge; + +#define MOTOROLA_CPUTYPE_REG 0x800 +#define MOTOROLA_BASETYPE_REG 0x803 + +extern prep_t checkPrepBoardType(RESIDUAL *res); +extern prep_t currentPrepType; +extern motorolaBoard getMotorolaBoard(void); +extern motorolaBoard currentBoard; +extern const char* motorolaBoardToString(motorolaBoard); +extern const struct _int_map *motorolaIntMap(motorolaBoard board); +extern const void *motorolaIntSwizzle(motorolaBoard board); + +#endif /* LIBBSP_POWERPC_SHARED_MOTOROLA_MOTOROLA_H */ diff --git a/bsps/powerpc/include/bsp/openpic.h b/bsps/powerpc/include/bsp/openpic.h new file mode 100644 index 0000000000..df782596b5 --- /dev/null +++ b/bsps/powerpc/include/bsp/openpic.h @@ -0,0 +1,378 @@ +/* + * openpic.h -- OpenPIC definitions + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is based on the following documentation: + * + * The Open Programmable Interrupt Controller (PIC) + * Register Interface Specification Revision 1.2 + * + * Issue Date: October 1995 + * + * Issued jointly by Advanced Micro Devices and Cyrix Corporation + * + * AMD is a registered trademark of Advanced Micro Devices, Inc. + * Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc. + * All Rights Reserved. + * + * To receive a copy of this documentation, send an email to openpic@amd.com. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + * Modified to compile in RTEMS development environment + * by Eric Valette + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_OPENPIC_H +#define _RTEMS_OPENPIC_H + + /* + * OpenPIC supports up to 2048 interrupt sources and up to 32 processors + */ +#define OPENPIC_MAX_SOURCES 2048 +#define OPENPIC_MAX_PROCESSORS 32 + +#define OPENPIC_NUM_TIMERS 4 +#define OPENPIC_NUM_IPI 4 +#define OPENPIC_NUM_PRI 16 +#define OPENPIC_NUM_VECTORS 256 + + /* + * Vector numbers + */ + +#define OPENPIC_VEC_SOURCE 0x10 /* and up */ +#define OPENPIC_VEC_TIMER 0x40 /* and up */ +#define OPENPIC_VEC_IPI 0x50 /* and up */ +#define OPENPIC_VEC_SPURIOUS 99 + + /* + * OpenPIC Registers are 32 bits and aligned on 128 bit boundaries + */ + +typedef struct _OpenPIC_Reg { + unsigned int Reg; /* Little endian! */ + char Pad[0xc]; +} OpenPIC_Reg; + + /* + * Per Processor Registers + */ + +typedef struct _OpenPIC_Processor { + /* + * Private Shadow Registers (for SLiC backwards compatibility) + */ + unsigned int IPI0_Dispatch_Shadow; /* Write Only */ + char Pad1[0x4]; + unsigned int IPI0_Vector_Priority_Shadow; /* Read/Write */ + char Pad2[0x34]; + /* + * Interprocessor Interrupt Command Ports + */ + OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */ + /* + * Current Task Priority Register + */ + OpenPIC_Reg _Current_Task_Priority; /* Read/Write */ + char Pad3[0x10]; + /* + * Interrupt Acknowledge Register + */ + OpenPIC_Reg _Interrupt_Acknowledge; /* Read Only */ + /* + * End of Interrupt (EOI) Register + */ + OpenPIC_Reg _EOI; /* Read/Write */ + char Pad5[0xf40]; +} OpenPIC_Processor; + + /* + * Timer Registers + */ + +typedef struct _OpenPIC_Timer { + OpenPIC_Reg _Current_Count; /* Read Only */ + OpenPIC_Reg _Base_Count; /* Read/Write */ + OpenPIC_Reg _Vector_Priority; /* Read/Write */ + OpenPIC_Reg _Destination; /* Read/Write */ +} OpenPIC_Timer; + + /* + * Global Registers + */ + +typedef struct _OpenPIC_Global { + /* + * Feature Reporting Registers + */ + OpenPIC_Reg _Feature_Reporting0; /* Read Only */ + OpenPIC_Reg _Feature_Reporting1; /* Future Expansion */ + /* + * Global Configuration Registers + */ + OpenPIC_Reg _Global_Configuration0; /* Read/Write */ + OpenPIC_Reg _Global_Configuration1; /* Future Expansion */ + /* + * Vendor Specific Registers + */ + OpenPIC_Reg _Vendor_Specific[4]; + /* + * Vendor Identification Register + */ + OpenPIC_Reg _Vendor_Identification; /* Read Only */ + /* + * Processor Initialization Register + */ + OpenPIC_Reg _Processor_Initialization; /* Read/Write */ + /* + * IPI Vector/Priority Registers + */ + OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */ + /* + * Spurious Vector Register + */ + OpenPIC_Reg _Spurious_Vector; /* Read/Write */ + /* + * Global Timer Registers + */ + OpenPIC_Reg _Timer_Frequency; /* Read/Write */ + OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS]; + char Pad1[0xee00]; +} OpenPIC_Global; + + /* + * Interrupt Source Registers + */ + +typedef struct _OpenPIC_Source { + OpenPIC_Reg _Vector_Priority; /* Read/Write */ + OpenPIC_Reg _Destination; /* Read/Write */ +} OpenPIC_Source; + + /* + * OpenPIC Register Map + */ + +struct OpenPIC { + char Pad1[0x1000]; + /* + * Global Registers + */ + OpenPIC_Global Global; + /* + * Interrupt Source Configuration Registers + */ + OpenPIC_Source Source[OPENPIC_MAX_SOURCES]; + /* + * Per Processor Registers + */ + OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS]; +}; + +extern volatile struct OpenPIC *OpenPIC; + + /* + * Current Task Priority Register + */ + +#define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f + + /* + * Who Am I Register + */ + +#define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f + + /* + * Feature Reporting Register 0 + */ + +#define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000 +#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16 +#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00 +#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8 +#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff + + /* + * Global Configuration Register 0 + */ + +#define OPENPIC_CONFIG_RESET 0x80000000 +#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000 +#define OPENPIC_CONFIG_BASE_MASK 0x000fffff + + /* + * Vendor Identification Register + */ + +#define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000 +#define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16 +#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 +#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8 +#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff + + /* + * Vector/Priority Registers + */ + +#define OPENPIC_MASK 0x80000000 +#define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ +#define OPENPIC_PRIORITY_MASK 0x000f0000 +#define OPENPIC_PRIORITY_SHIFT 16 +#define OPENPIC_VECTOR_MASK 0x000000ff + + /* + * Interrupt Source Registers + */ + +#define OPENPIC_SENSE_POLARITY 0x00800000 /* Undoc'd */ +#define OPENPIC_SENSE_LEVEL 0x00400000 + + /* + * Timer Registers + */ + +#define OPENPIC_COUNT_MASK 0x7fffffff +#define OPENPIC_TIMER_TOGGLE 0x80000000 +#define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000 + + /* + * Aliases to make life simpler + */ + +/* Per Processor Registers */ +#define IPI_Dispatch(i) _IPI_Dispatch[i].Reg +#define Current_Task_Priority _Current_Task_Priority.Reg +#define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg +#define EOI _EOI.Reg + +/* Global Registers */ +#define Feature_Reporting0 _Feature_Reporting0.Reg +#define Feature_Reporting1 _Feature_Reporting1.Reg +#define Global_Configuration0 _Global_Configuration0.Reg +#define Global_Configuration1 _Global_Configuration1.Reg +#define Vendor_Specific(i) _Vendor_Specific[i].Reg +#define Vendor_Identification _Vendor_Identification.Reg +#define Processor_Initialization _Processor_Initialization.Reg +#define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg +#define Spurious_Vector _Spurious_Vector.Reg +#define Timer_Frequency _Timer_Frequency.Reg + +/* Timer Registers */ +#define Current_Count _Current_Count.Reg +#define Base_Count _Base_Count.Reg +#define Vector_Priority _Vector_Priority.Reg +#define Destination _Destination.Reg + +/* Interrupt Source Registers */ +#define Vector_Priority _Vector_Priority.Reg +#define Destination _Destination.Reg + + /* + * Vendor and Device IDs + */ + +#define OPENPIC_VENDOR_ID_APPLE 0x14 +#define OPENPIC_DEVICE_ID_APPLE_HYDRA 0x46 + + /* + * OpenPIC Operations + */ + +/* + * Handle EPIC differences. Unfortunately, I don't know of an easy + * way to tell an EPIC from a normal PIC at run-time. Therefore, + * the BSP must enable a few quirks if it knows that an EPIC is being + * used: + * - If the BSP uses the serial interrupt mode / 'multiplexer' then + * EOI must be delayed by at least 16 SRAM_CLK cycles to avoid + * spurious interrupts. + * It is the BSP's responsibility to set up an appropriate delay + * (in timebase-clock cycles) at init time using + * 'openpic_set_eoi_delay()'. This is ONLY necessary when using + * an EPIC in serial mode. + * - The EPIC sources start at an offset of 16 in the register + * map, i.e., on an EPIC you'd say Sources[ x + 16 ] where + * on a PIC you would say Sources[ x ]. + * Again, the BSP can set an offset that is used by the + * calls dealing with 'Interrupt Sources' + * openpic_enable_irq() + * openpic_disable_irq() + * openpic_initirq() + * openpic_mapirq() + * openpic_set_sense() + * openpic_get_source_priority() + * openpic_set_source_priority() + * the desired source offset parameter is passed to openpic_init(). + * + * The routine 'openpic_set_eoi_delay()' returns the previous/old + * value of the delay parameter. + */ +extern unsigned openpic_set_eoi_delay(unsigned tb_cycles); + + +/* Global Operations */ + +/* num_sources: number of sources to use; if zero this value + * is read from the device, if nonzero the value read from + * the device is overridden. + * 'polarities' and 'senses' are arrays defining the desired + * polarities (active hi [nonzero]/lo [zero]) and + * senses (level [nonzero]/edge [zero]). + * Either of the two array pointers may be NULL resulting + * in the driver choosing default values of: 'active low' + * and 'level sensitive', respectively. + * NOTE: if you do pass arrays then their size must either + * match the number of sources read from the device or + * that value must be overridden by specifying + * a non-zero 'num_sources' parameter. + * + * Nonzero 'epic_freq' activates the EOI delay if the EPIC is + * configured in serial mode (driver assumes firmware performs initial + * EPIC setup). The BSP must pass the clock frequency of the EPIC + * serial interface here. + */ +extern void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq); + +extern void openpic_reset(void); +extern void openpic_enable_8259_pass_through(void); +extern void openpic_disable_8259_pass_through(void); +extern unsigned int openpic_irq(unsigned int cpu); +extern void openpic_eoi(unsigned int cpu); +extern unsigned int openpic_get_priority(unsigned int cpu); +extern void openpic_set_priority(unsigned int cpu, unsigned int pri); +extern unsigned int openpic_get_spurious(void); +extern void openpic_set_spurious(unsigned int vector); +extern void openpic_init_processor(unsigned int cpumask); + +/* Interprocessor Interrupts */ +extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector); +extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask); + +/* Timer Interrupts */ +extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector); +extern void openpic_settimer(unsigned int timer, unsigned int base_count, int irq_enable); +extern unsigned int openpic_gettimer(unsigned int timer); +extern void openpic_maptimer(unsigned int timer, unsigned int cpumask); + +/* Interrupt Sources */ +extern void openpic_enable_irq(unsigned int irq); +extern int openpic_disable_irq(unsigned int irq); +extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity, + int is_level); +extern void openpic_mapirq(unsigned int irq, unsigned int cpumask); +extern void openpic_set_sense(unsigned int irq, int sense); +extern unsigned int openpic_get_source_priority(unsigned int irq); +extern void openpic_set_source_priority(unsigned int irq, unsigned int pri); + +#endif /* RTEMS_OPENPIC_H */ diff --git a/bsps/powerpc/include/bsp/pci.h b/bsps/powerpc/include/bsp/pci.h new file mode 100644 index 0000000000..42dc43875b --- /dev/null +++ b/bsps/powerpc/include/bsp/pci.h @@ -0,0 +1,84 @@ +/* + * PCI defines and function prototypes + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI System Design Guide + */ + +/* + * Copyright 1994, Drew Eckhardt + * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> + */ + +#ifndef BSP_POWERPC_PCI_H +#define BSP_POWERPC_PCI_H + +#include <rtems/pci.h> +#include <stdio.h> + +struct _pin_routes +{ + int pin; + int int_name[4]; +}; +struct _int_map +{ + int bus; + int slot; + int opts; + struct _pin_routes pin_route[5]; +}; + +/* If there's a conflict between a name in the routing table and + * what's already set on the device, reprogram the device setting + * to reflect int_name[0] for the routing table entry + */ +#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) + +/* + * This is assumed to be provided by the BSP. + */ +void detect_host_bridge(void); + +void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); + +/* FIXME: This probably belongs into rtems/pci.h */ +extern unsigned char pci_bus_count(); + +/* FIXME: This also is generic and could go into rtems/pci.h */ + +/* Scan pci config space and run a user callback on each + * device present; the user callback may return 0 to + * continue the scan or a value > 0 to abort the scan. + * Return values < 0 are reserved and must not be used. + * + * RETURNS: a (opaque) handle pointing to the bus/slot/fn-triple + * just after where the scan was aborted by a callback + * returning 1 (see above) or NULL if all devices were + * scanned. + * The handle may be passed to this routine to resume the + * scan continuing with the device after the one causing the + * abort. + * Pass a NULL 'handle' argument to start scanning from + * the beginning (bus/slot/fn = 0/0/0). + */ +typedef void *BSP_PciScanHandle; +typedef int (*BSP_PciScannerCb)(int bus, int slot, int fun, void *uarg); + +BSP_PciScanHandle +BSP_pciScan(BSP_PciScanHandle handle, BSP_PciScannerCb cb, void *uarg); + +/* Dump basic config. space info to a file. The argument may + * be NULL in which case 'stdout' is used. + * NOTE: the C-library must be functional before you can use + * this routine. + */ +void +BSP_pciConfigDump(FILE *fp); + +#endif /* BSP_POWERPC_PCI_H */ diff --git a/bsps/powerpc/include/bsp/pnp.h b/bsps/powerpc/include/bsp/pnp.h new file mode 100644 index 0000000000..203a1a46d3 --- /dev/null +++ b/bsps/powerpc/include/bsp/pnp.h @@ -0,0 +1,644 @@ +/* 11/02/95 */ +/*----------------------------------------------------------------------------*/ +/* Plug and Play header definitions */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for PnP on PowerPC Reference Platform */ +/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993. It */ +/* (or later versions) is available on Compuserve in the PLUGPLAY area. */ +/* This code has extensions to that specification, namely new short and */ +/* long tag types for platform dependent information */ + +/* Warning: LE notation used throughout this file */ + +/* For enum's: if given in hex then they are bit significant, i.e. */ +/* only one bit is on for each enum */ + + +#ifndef _PNP_ +#define _PNP_ + +#ifndef ASM +#define MAX_MEM_REGISTERS 9 +#define MAX_IO_PORTS 20 +#define MAX_IRQS 7 +/*#define MAX_DMA_CHANNELS 7*/ + +/* Interrupt controllers */ + +#define PNPinterrupt0 "PNP0000" /* AT Interrupt Controller */ +#define PNPinterrupt1 "PNP0001" /* EISA Interrupt Controller */ +#define PNPinterrupt2 "PNP0002" /* MCA Interrupt Controller */ +#define PNPinterrupt3 "PNP0003" /* APIC */ +#define PNPExtInt "IBM000D" /* PowerPC Extended Interrupt Controller */ + +/* Timers */ + +#define PNPtimer0 "PNP0100" /* AT Timer */ +#define PNPtimer1 "PNP0101" /* EISA Timer */ +#define PNPtimer2 "PNP0102" /* MCA Timer */ + +/* DMA controllers */ + +#define PNPdma0 "PNP0200" /* AT DMA Controller */ +#define PNPdma1 "PNP0201" /* EISA DMA Controller */ +#define PNPdma2 "PNP0202" /* MCA DMA Controller */ + +/* start of August 15, 1994 additions */ +/* CMOS */ +#define PNPCMOS "IBM0009" /* CMOS */ + +/* L2 Cache */ +#define PNPL2 "IBM0007" /* L2 Cache */ + +/* NVRAM */ +#define PNPNVRAM "IBM0008" /* NVRAM */ + +/* Power Management */ +#define PNPPM "IBM0005" /* Power Management */ +/* end of August 15, 1994 additions */ + +/* Keyboards */ + +#define PNPkeyboard0 "PNP0300" /* IBM PC/XT KB Cntlr (83 key, no mouse) */ +#define PNPkeyboard1 "PNP0301" /* Olivetti ICO (102 key) */ +#define PNPkeyboard2 "PNP0302" /* IBM PC/AT KB Cntlr (84 key) */ +#define PNPkeyboard3 "PNP0303" /* IBM Enhanced (101/2 key, PS/2 mouse) */ +#define PNPkeyboard4 "PNP0304" /* Nokia 1050 KB Cntlr */ +#define PNPkeyboard5 "PNP0305" /* Nokia 9140 KB Cntlr */ +#define PNPkeyboard6 "PNP0306" /* Standard Japanese KB Cntlr */ +#define PNPkeyboard7 "PNP0307" /* Microsoft Windows (R) KB Cntlr */ + +/* Parallel port controllers */ + +#define PNPparallel0 "PNP0400" /* Standard LPT Parallel Port */ +#define PNPparallel1 "PNP0401" /* ECP Parallel Port */ +#define PNPepp "IBM001C" /* EPP Parallel Port */ + +/* Serial port controllers */ + +#define PNPserial0 "PNP0500" /* Standard PC Serial port */ +#define PNPSerial1 "PNP0501" /* 16550A Compatible Serial port */ + +/* Disk controllers */ + +#define PNPdisk0 "PNP0600" /* Generic ESDI/IDE/ATA Compat HD Cntlr */ +#define PNPdisk1 "PNP0601" /* Plus Hardcard II */ +#define PNPdisk2 "PNP0602" /* Plus Hardcard IIXL/EZ */ + +/* Diskette controllers */ + +#define PNPdiskette0 "PNP0700" /* PC Standard Floppy Disk Controller */ + +/* Display controllers */ + +#define PNPdisplay0 "PNP0900" /* VGA Compatible */ +#define PNPdisplay1 "PNP0901" /* Video Seven VGA */ +#define PNPdisplay2 "PNP0902" /* 8514/A Compatible */ +#define PNPdisplay3 "PNP0903" /* Trident VGA */ +#define PNPdisplay4 "PNP0904" /* Cirrus Logic Laptop VGA */ +#define PNPdisplay5 "PNP0905" /* Cirrus Logic VGA */ +#define PNPdisplay6 "PNP0906" /* Tseng ET4000 or ET4000/W32 */ +#define PNPdisplay7 "PNP0907" /* Western Digital VGA */ +#define PNPdisplay8 "PNP0908" /* Western Digital Laptop VGA */ +#define PNPdisplay9 "PNP0909" /* S3 */ +#define PNPdisplayA "PNP090A" /* ATI Ultra Pro/Plus (Mach 32) */ +#define PNPdisplayB "PNP090B" /* ATI Ultra (Mach 8) */ +#define PNPdisplayC "PNP090C" /* XGA Compatible */ +#define PNPdisplayD "PNP090D" /* ATI VGA Wonder */ +#define PNPdisplayE "PNP090E" /* Weitek P9000 Graphics Adapter */ +#define PNPdisplayF "PNP090F" /* Oak Technology VGA */ + +/* Peripheral busses */ + +#define PNPbuses0 "PNP0A00" /* ISA Bus */ +#define PNPbuses1 "PNP0A01" /* EISA Bus */ +#define PNPbuses2 "PNP0A02" /* MCA Bus */ +#define PNPbuses3 "PNP0A03" /* PCI Bus */ +#define PNPbuses4 "PNP0A04" /* VESA/VL Bus */ + +/* RTC, BIOS, planar devices */ + +#define PNPspeaker0 "PNP0800" /* AT Style Speaker Sound */ +#define PNPrtc0 "PNP0B00" /* AT RTC */ +#define PNPpnpbios0 "PNP0C00" /* PNP BIOS (only created by root enum) */ +#define PNPpnpbios1 "PNP0C01" /* System Board Memory Device */ +#define PNPpnpbios2 "PNP0C02" /* Math Coprocessor */ +#define PNPpnpbios3 "PNP0C03" /* PNP BIOS Event Notification Interrupt */ + +/* PCMCIA controller */ + +#define PNPpcmcia0 "PNP0E00" /* Intel 82365 Compatible PCMCIA Cntlr */ + +/* Mice */ + +#define PNPmouse0 "PNP0F00" /* Microsoft Bus Mouse */ +#define PNPmouse1 "PNP0F01" /* Microsoft Serial Mouse */ +#define PNPmouse2 "PNP0F02" /* Microsoft Inport Mouse */ +#define PNPmouse3 "PNP0F03" /* Microsoft PS/2 Mouse */ +#define PNPmouse4 "PNP0F04" /* Mousesystems Mouse */ +#define PNPmouse5 "PNP0F05" /* Mousesystems 3 Button Mouse - COM2 */ +#define PNPmouse6 "PNP0F06" /* Genius Mouse - COM1 */ +#define PNPmouse7 "PNP0F07" /* Genius Mouse - COM2 */ +#define PNPmouse8 "PNP0F08" /* Logitech Serial Mouse */ +#define PNPmouse9 "PNP0F09" /* Microsoft Ballpoint Serial Mouse */ +#define PNPmouseA "PNP0F0A" /* Microsoft PNP Mouse */ +#define PNPmouseB "PNP0F0B" /* Microsoft PNP Ballpoint Mouse */ + +/* Modems */ + +#define PNPmodem0 "PNP9000" /* Specific IDs TBD */ + +/* Network controllers */ + +#define PNPnetworkC9 "PNP80C9" /* IBM Token Ring */ +#define PNPnetworkCA "PNP80CA" /* IBM Token Ring II */ +#define PNPnetworkCB "PNP80CB" /* IBM Token Ring II/Short */ +#define PNPnetworkCC "PNP80CC" /* IBM Token Ring 4/16Mbs */ +#define PNPnetwork27 "PNP8327" /* IBM Token Ring (All types) */ +#define PNPnetworket "IBM0010" /* IBM Ethernet used by Power PC */ +#define PNPneteisaet "IBM2001" /* IBM Ethernet EISA adapter */ +#define PNPAMD79C970 "IBM0016" /* AMD 79C970 (PCI Ethernet) */ + +/* SCSI controllers */ + +#define PNPscsi0 "PNPA000" /* Adaptec 154x Compatible SCSI Cntlr */ +#define PNPscsi1 "PNPA001" /* Adaptec 174x Compatible SCSI Cntlr */ +#define PNPscsi2 "PNPA002" /* Future Domain 16-700 Compat SCSI Cntlr*/ +#define PNPscsi3 "PNPA003" /* Panasonic CDROM Adapter (SBPro/SB16) */ +#define PNPscsiF "IBM000F" /* NCR 810 SCSI Controller */ +#define PNPscsi825 "IBM001B" /* NCR 825 SCSI Controller */ +#define PNPscsi875 "IBM0018" /* NCR 875 SCSI Controller */ + +/* Sound/Video, Multimedia */ + +#define PNPmm0 "PNPB000" /* Sound Blaster Compatible Sound Device */ +#define PNPmm1 "PNPB001" /* MS Windows Sound System Compat Device */ +#define PNPmmF "IBM000E" /* Crystal CS4231 Audio Device */ +#define PNPv7310 "IBM0015" /* ASCII V7310 Video Capture Device */ +#define PNPmm4232 "IBM0017" /* Crystal CS4232 Audio Device */ +#define PNPpmsyn "IBM001D" /* YMF 289B chip (Yamaha) */ +#define PNPgp4232 "IBM0012" /* Crystal CS4232 Game Port */ +#define PNPmidi4232 "IBM0013" /* Crystal CS4232 MIDI */ + +/* Operator Panel */ +#define PNPopctl "IBM000B" /* Operator's panel */ + +/* Service Processor */ +#define PNPsp "IBM0011" /* IBM Service Processor */ +#define PNPLTsp "IBM001E" /* Lightning/Terlingua Support Processor */ +#define PNPLTmsp "IBM001F" /* Lightning/Terlingua Mini-SP */ + +/* Memory Controller */ +#define PNPmemctl "IBM000A" /* Memory controller */ + +/* Graphics Assist */ +#define PNPg_assist "IBM0014" /* Graphics Assist */ + +/* Miscellaneous Device Controllers */ +#define PNPtablet "IBM0019" /* IBM Tablet Controller */ + +/* PNP Packet Handles */ + +#define S1_Packet 0x0A /* Version resource */ +#define S2_Packet 0x15 /* Logical DEVID (without flags) */ +#define S2_Packet_flags 0x16 /* Logical DEVID (with flags) */ +#define S3_Packet 0x1C /* Compatible device ID */ +#define S4_Packet 0x22 /* IRQ resource (without flags) */ +#define S4_Packet_flags 0x23 /* IRQ resource (with flags) */ +#define S5_Packet 0x2A /* DMA resource */ +#define S6_Packet 0x30 /* Depend funct start (w/o priority) */ +#define S6_Packet_priority 0x31 /* Depend funct start (w/ priority) */ +#define S7_Packet 0x38 /* Depend funct end */ +#define S8_Packet 0x47 /* I/O port resource (w/o fixed loc) */ +#define S9_Packet_fixed 0x4B /* I/O port resource (w/ fixed loc) */ +#define S14_Packet 0x71 /* Vendor defined */ +#define S15_Packet 0x78 /* End of resource (w/o checksum) */ +#define S15_Packet_checksum 0x79 /* End of resource (w/ checksum) */ +#define L1_Packet 0x81 /* Memory range */ +#define L1_Shadow 0x20 /* Memory is shadowable */ +#define L1_32bit_mem 0x18 /* 32-bit memory only */ +#define L1_8_16bit_mem 0x10 /* 8- and 16-bit supported */ +#define L1_Decode_Hi 0x04 /* decode supports high address */ +#define L1_Cache 0x02 /* read cacheable, write-through */ +#define L1_Writeable 0x01 /* Memory is writeable */ +#define L2_Packet 0x82 /* ANSI ID string */ +#define L3_Packet 0x83 /* Unicode ID string */ +#define L4_Packet 0x84 /* Vendor defined */ +#define L5_Packet 0x85 /* Large I/O */ +#define L6_Packet 0x86 /* 32-bit Fixed Loc Mem Range Desc */ +#define END_TAG 0x78 /* End of resource */ +#define DF_START_TAG 0x30 /* Dependent function start */ +#define DF_START_TAG_priority 0x31 /* Dependent function start */ +#define DF_END_TAG 0x38 /* Dependent function end */ +#define SUBOPTIMAL_CONFIGURATION 0x2 /* Priority byte sub optimal config */ + +/* Device Base Type Codes */ + +typedef enum _PnP_BASE_TYPE { + Reserved = 0, + MassStorageDevice = 1, + NetworkInterfaceController = 2, + DisplayController = 3, + MultimediaController = 4, + MemoryController = 5, + BridgeController = 6, + CommunicationsDevice = 7, + SystemPeripheral = 8, + InputDevice = 9, + ServiceProcessor = 0x0A, /* 11/2/95 */ + } PnP_BASE_TYPE; + +/* Device Sub Type Codes */ + +typedef enum _PnP_SUB_TYPE { + SCSIController = 0, + IDEController = 1, + FloppyController = 2, + IPIController = 3, + OtherMassStorageController = 0x80, + + EthernetController = 0, + TokenRingController = 1, + FDDIController = 2, + OtherNetworkController = 0x80, + + VGAController= 0, + SVGAController= 1, + XGAController= 2, + OtherDisplayController = 0x80, + + VideoController = 0, + AudioController = 1, + OtherMultimediaController = 0x80, + + RAM = 0, + FLASH = 1, + OtherMemoryDevice = 0x80, + + HostProcessorBridge = 0, + ISABridge = 1, + EISABridge = 2, + MicroChannelBridge = 3, + PCIBridge = 4, + PCMCIABridge = 5, + VMEBridge = 6, + OtherBridgeDevice = 0x80, + + RS232Device = 0, + ATCompatibleParallelPort = 1, + OtherCommunicationsDevice = 0x80, + + ProgrammableInterruptController = 0, + DMAController = 1, + SystemTimer = 2, + RealTimeClock = 3, + L2Cache = 4, + NVRAM = 5, + PowerManagement = 6, + CMOS = 7, + OperatorPanel = 8, + ServiceProcessorClass1 = 9, + ServiceProcessorClass2 = 0xA, + ServiceProcessorClass3 = 0xB, + GraphicAssist = 0xC, + SystemPlanar = 0xF, /* 10/5/95 */ + OtherSystemPeripheral = 0x80, + + KeyboardController = 0, + Digitizer = 1, + MouseController = 2, + TabletController = 3, /* 10/27/95 */ + OtherInputController = 0x80, + + GeneralMemoryController = 0, + } PnP_SUB_TYPE; + +/* Device Interface Type Codes */ + +typedef enum _PnP_INTERFACE { + General = 0, + GeneralSCSI = 0, + GeneralIDE = 0, + ATACompatible = 1, + + GeneralFloppy = 0, + Compatible765 = 1, + NS398_Floppy = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26E_Floppy = 3, /* Ports 26E and 26F */ + NS15C_Floppy = 4, /* Ports 15C and 15D */ + NS2E_Floppy = 5, /* Ports 2E and 2F */ + CHRP_Floppy = 6, /* CHRP Floppy in PR*P system */ + + GeneralIPI = 0, + + GeneralEther = 0, + GeneralToken = 0, + GeneralFDDI = 0, + + GeneralVGA = 0, + GeneralSVGA = 0, + GeneralXGA = 0, + + GeneralVideo = 0, + GeneralAudio = 0, + CS4232Audio = 1, /* CS 4232 Plug 'n Play Configured */ + + GeneralRAM = 0, + GeneralFLASH = 0, + PCIMemoryController = 0, /* PCI Config Method */ + RS6KMemoryController = 1, /* RS6K Config Method */ + + GeneralHostBridge = 0, + GeneralISABridge = 0, + GeneralEISABridge = 0, + GeneralMCABridge = 0, + GeneralPCIBridge = 0, + PCIBridgeDirect = 0, + PCIBridgeIndirect = 1, + PCIBridgeRS6K = 2, + GeneralPCMCIABridge = 0, + GeneralVMEBridge = 0, + + GeneralRS232 = 0, + COMx = 1, + Compatible16450 = 2, + Compatible16550 = 3, + NS398SerPort = 4, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26ESerPort = 5, /* Ports 26E and 26F */ + NS15CSerPort = 6, /* Ports 15C and 15D */ + NS2ESerPort = 7, /* Ports 2E and 2F */ + + GeneralParPort = 0, + LPTx = 1, + NS398ParPort = 2, /* NS Super I/O wired to use index + register at port 398 and data + register at port 399 */ + NS26EParPort = 3, /* Ports 26E and 26F */ + NS15CParPort = 4, /* Ports 15C and 15D */ + NS2EParPort = 5, /* Ports 2E and 2F */ + + GeneralPIC = 0, + ISA_PIC = 1, + EISA_PIC = 2, + MPIC = 3, + RS6K_PIC = 4, + + GeneralDMA = 0, + ISA_DMA = 1, + EISA_DMA = 2, + + GeneralTimer = 0, + ISA_Timer = 1, + EISA_Timer = 2, + GeneralRTC = 0, + ISA_RTC = 1, + + StoreThruOnly = 1, + StoreInEnabled = 2, + RS6KL2Cache = 3, + + IndirectNVRAM = 0, /* Indirectly addressed */ + DirectNVRAM = 1, /* Memory Mapped */ + IndirectNVRAM24 = 2, /* Indirectly addressed - 24 bit */ + + GeneralPowerManagement = 0, + EPOWPowerManagement = 1, + PowerControl = 2, /* d1378 */ + + GeneralCMOS = 0, + + GeneralOPPanel = 0, + HarddiskLight = 1, + CDROMLight = 2, + PowerLight = 3, + KeyLock = 4, + ANDisplay = 5, /* AlphaNumeric Display */ + SystemStatusLED = 6, /* 3 digit 7 segment LED */ + CHRP_SystemStatusLED = 7, /* CHRP LEDs in PR*P system */ + + GeneralServiceProcessor = 0, + + TransferData = 1, + IGMC32 = 2, + IGMC64 = 3, + + GeneralSystemPlanar = 0, /* 10/5/95 */ + + } PnP_INTERFACE; + +/* PnP resources */ + +/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */ + +typedef struct _SERIAL_ID { + unsigned char VendorID0; /* Bit(7)=0 */ + /* Bits(6:2)=1st character in */ + /* compressed ASCII */ + /* Bits(1:0)=2nd character in */ + /* compressed ASCII bits(4:3) */ + unsigned char VendorID1; /* Bits(7:5)=2nd character in */ + /* compressed ASCII bits(2:0) */ + /* Bits(4:0)=3rd character in */ + /* compressed ASCII */ + unsigned char VendorID2; /* Product number - vendor assigned */ + unsigned char VendorID3; /* Product number - vendor assigned */ + +/* Serial number is to provide uniqueness if more than one board of same */ +/* type is in system. Must be "FFFFFFFF" if feature not supported. */ + + unsigned char Serial0; /* Unique serial number bits (7:0) */ + unsigned char Serial1; /* Unique serial number bits (15:8) */ + unsigned char Serial2; /* Unique serial number bits (23:16) */ + unsigned char Serial3; /* Unique serial number bits (31:24) */ + unsigned char Checksum; + } SERIAL_ID; + +typedef enum _PnPItemName { + Unused = 0, + PnPVersion = 1, + LogicalDevice = 2, + CompatibleDevice = 3, + IRQFormat = 4, + DMAFormat = 5, + StartDepFunc = 6, + EndDepFunc = 7, + IOPort = 8, + FixedIOPort = 9, + Res1 = 10, + Res2 = 11, + Res3 = 12, + SmallVendorItem = 14, + EndTag = 15, + MemoryRange = 1, + ANSIIdentifier = 2, + UnicodeIdentifier = 3, + LargeVendorItem = 4, + MemoryRange32 = 5, + MemoryRangeFixed32 = 6, + } PnPItemName; + +/* Define a bunch of access functions for the bits in the tag field */ + +/* Tag type - 0 = small; 1 = large */ +#define tag_type(t) (((t) & 0x80)>>7) +#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7)) + +/* Small item name is 4 bits - one of PnPItemName enum above */ +#define tag_small_item_name(t) (((t) & 0x78)>>3) +#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3)) + +/* Small item count is 3 bits - count of further bytes in packet */ +#define tag_small_count(t) ((t) & 0x07) +#define set_tag_count(t,v) (t = (t & 0x78) | (v)) + +/* Large item name is 7 bits - one of PnPItemName enum above */ +#define tag_large_item_name(t) ((t) & 0x7f) +#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v)) + +/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */ + +typedef union _PnP_TAG_PACKET { + struct _S1_Pack{ /* VERSION PACKET */ + unsigned char Tag; /* small tag = 0x0a */ + unsigned char Version[2]; /* PnP version, Vendor version */ + } S1_Pack; + + struct _S2_Pack{ /* LOGICAL DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x15 or 0x16 */ + unsigned char DevId[4]; /* Logical device id */ + unsigned char Flags[2]; /* bit(0) boot device; */ + /* bit(7:1) cmd in range x31-x37 */ + /* bit(7:0) cmd in range x28-x3f (opt)*/ + } S2_Pack; + + struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ + unsigned char Tag; /* small tag = 0x1c */ + unsigned char CompatId[4]; /* Compatible device id */ + } S3_Pack; + + struct _S4_Pack{ /* IRQ PACKET */ + unsigned char Tag; /* small tag = 0x22 or 0x23 */ + unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ + /* bit(0) is IRQ8 ... */ + unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ + /* bit(0) - high true edge sensitive */ + /* bit(1) - low true edge sensitive */ + /* bit(2) - high true level sensitive*/ + /* bit(3) - low true level sensitive */ + /* bit(7:4) - must be 0 */ + } S4_Pack; + + struct _S5_Pack{ /* DMA PACKET */ + unsigned char Tag; /* small tag = 0x2a */ + unsigned char DMAMask; /* bit(0) is channel 0 ... */ + unsigned char DMAInfo; + } S5_Pack; + + struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x30 or 0x31 */ + unsigned char Priority; /* Optional; if missing then x01; else*/ + /* x00 = best possible */ + /* x01 = acceptible */ + /* x02 = sub-optimal but functional */ + } S6_Pack; + + struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ + unsigned char Tag; /* small tag = 0x38 */ + } S7_Pack; + + struct _S8_Pack{ /* VARIABLE I/O PORT PACKET */ + unsigned char Tag; /* small tag x47 */ + unsigned char IOInfo; /* x0 = decode only bits(9:0); */ +#define ISAAddr16bit 0x01 /* x01 = decode bits(15:0) */ + unsigned char RangeMin[2]; /* Min base address */ + unsigned char RangeMax[2]; /* Max base address */ + unsigned char IOAlign; /* base alignmt, incr in 1B blocks */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S8_Pack; + + struct _S9_Pack{ /* FIXED I/O PORT PACKET */ + unsigned char Tag; /* small tag = 0x4b */ + unsigned char Range[2]; /* base address 10 bits */ + unsigned char IONum; /* number of contiguous I/O ports */ + } S9_Pack; + + struct _S14_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* small tag = 0x7m m = 1-7 */ + union _S14_Data{ + unsigned char Data[7]; /* Vendor defined */ + struct _S14_PPCPack{ /* Pr*p s14 pack */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[6]; /* Vendor defined */ + } S14_PPCPack; + } S14_Data; + } S14_Pack; + + struct _S15_Pack{ /* END PACKET */ + unsigned char Tag; /* small tag = 0x78 or 0x79 */ + unsigned char Check; /* optional - checksum */ + } S15_Pack; + + struct _L1_Pack{ /* MEMORY RANGE PACKET */ + unsigned char Tag; /* large tag = 0x81 */ + unsigned char Count0; /* x09 */ + unsigned char Count1; /* x00 */ + unsigned char Data[9]; /* a variable array of bytes, */ + /* count in tag */ + } L1_Pack; + + struct _L2_Pack{ /* ANSI ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x82 */ + unsigned char Count0; /* Length of string */ + unsigned char Count1; + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L2_Pack; + + struct _L3_Pack{ /* UNICODE ID STRING PACKET */ + unsigned char Tag; /* large tag = 0x83 */ + unsigned char Count0; /* Length + 2 of string */ + unsigned char Count1; + unsigned char Country0; /* TBD */ + unsigned char Country1; /* TBD */ + unsigned char Identifier[1]; /* a variable array of bytes, */ + /* count in tag */ + } L3_Pack; + + struct _L4_Pack{ /* VENDOR DEFINED PACKET */ + unsigned char Tag; /* large tag = 0x84 */ + unsigned char Count0; + unsigned char Count1; + union _L4_Data{ + unsigned char Data[1]; /* a variable array of bytes, */ + /* count in tag */ + struct _L4_PPCPack{ /* Pr*p L4 packet */ + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[1]; /* a variable array of bytes, */ + /* count in tag */ + } L4_PPCPack; + } L4_Data; + } L4_Pack; + + struct _L5_Pack{ + unsigned char Tag; /* large tag = 0x85 */ + unsigned char Count0; /* Count = 17 */ + unsigned char Count1; + unsigned char Data[17]; + } L5_Pack; + + struct _L6_Pack{ + unsigned char Tag; /* large tag = 0x86 */ + unsigned char Count0; /* Count = 9 */ + unsigned char Count1; + unsigned char Data[9]; + } L6_Pack; + + } PnP_TAG_PACKET; + +#endif /* ASM */ +#endif /* ndef _PNP_ */ diff --git a/bsps/powerpc/include/bsp/residual.h b/bsps/powerpc/include/bsp/residual.h new file mode 100644 index 0000000000..1bf1a34e20 --- /dev/null +++ b/bsps/powerpc/include/bsp/residual.h @@ -0,0 +1,356 @@ +/* 7/18/95 */ +/*----------------------------------------------------------------------------*/ +/* Residual Data header definitions and prototypes */ +/*----------------------------------------------------------------------------*/ + +/* Structure map for RESIDUAL on PowerPC Reference Platform */ +/* residual.h - Residual data structure passed in r3. */ +/* Load point passed in r4 to boot image. */ +/* For enum's: if given in hex then they are bit significant, */ +/* i.e. only one bit is on for each enum */ +/* Reserved fields must be filled with zeros. */ + + +#ifndef _RESIDUAL_ +#define _RESIDUAL_ + +#ifndef ASM + +#include <stdint.h> + +#define MAX_CPUS 32 /* These should be set to the maximum */ +#define MAX_MEMS 64 /* number possible for this system. */ +#define MAX_DEVICES 256 /* Changing these will change the */ +#define AVE_PNP_SIZE 32 /* structure, hence the version of */ +#define MAX_MEM_SEGS 64 /* this header file. */ + +/*----------------------------------------------------------------------------*/ +/* Public structures... */ +/*----------------------------------------------------------------------------*/ + +#include <bsp/pnp.h> + +typedef enum _L1CACHE_TYPE { + NoneCAC = 0, + SplitCAC = 1, + CombinedCAC = 2 + } L1CACHE_TYPE; + +typedef enum _TLB_TYPE { + NoneTLB = 0, + SplitTLB = 1, + CombinedTLB = 2 + } TLB_TYPE; + +typedef enum _FIRMWARE_SUPPORT { + Conventional = 0x01, + OpenFirmware = 0x02, + Diagnostics = 0x04, + LowDebug = 0x08, + Multiboot = 0x10, + LowClient = 0x20, + Hex41 = 0x40, + FAT = 0x80, + ISO9660 = 0x0100, + SCSI_InitiatorID_Override = 0x0200, + Tape_Boot = 0x0400, + FW_Boot_Path = 0x0800 + } FIRMWARE_SUPPORT; + +typedef enum _FIRMWARE_SUPPLIERS { + IBMFirmware = 0x00, + MotoFirmware = 0x01, /* 7/18/95 */ + FirmWorks = 0x02, /* 10/5/95 */ + Bull = 0x03, /* 04/03/96 */ + QEMU = ('q'<<24) | ('e'<<16) | ('m'<<8) | ('u'<<0), + } FIRMWARE_SUPPLIERS; + +typedef enum _ENDIAN_SWITCH_METHODS { + UsePort92 = 0x01, + UsePCIConfigA8 = 0x02, + UseFF001030 = 0x03, + } ENDIAN_SWITCH_METHODS; + +typedef enum _SPREAD_IO_METHODS { + UsePort850 = 0x00, +/*UsePCIConfigA8 = 0x02,*/ + } SPREAD_IO_METHODS; + +typedef struct _VPD { + + /* Box dependent stuff */ + unsigned char PrintableModel[32]; /* Null terminated string. + Must be of the form: + vvv,<20h>,<model designation>,<0x0> + where vvv is the vendor ID + e.g. IBM PPS MODEL 6015<0x0> */ + unsigned char Serial[16]; /* 12/94: + Serial Number; must be of the form: + vvv<serial number> where vvv is the + vendor ID. + e.g. IBM60151234567<20h><20h> */ + unsigned char Reserved[48]; + unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ + unsigned long FirmwareSupports; /* See FirmwareSupport enum */ + unsigned long NvramSize; /* Size of nvram in bytes */ + unsigned long NumSIMMSlots; + unsigned short EndianSwitchMethod; /* See EndianSwitchMethods enum */ + unsigned short SpreadIOMethod; /* See SpreadIOMethods enum */ + unsigned long SmpIar; + unsigned long RAMErrLogOffset; /* Heap offset to error log */ + unsigned long Reserved5; + unsigned long Reserved6; + unsigned long ProcessorHz; /* Processor clock frequency in Hertz */ + unsigned long ProcessorBusHz; /* Processor bus clock frequency */ + unsigned long Reserved7; + unsigned long TimeBaseDivisor; /* (Bus clocks per timebase tic)*1000 */ + unsigned long WordWidth; /* Word width in bits */ + unsigned long PageSize; /* Page size in bytes */ + unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache + for which coherency is maintained; + normally <= CacheLineSize. */ + unsigned long GranuleSize; /* Unit of lock allocation to avoid */ + /* false sharing of locks. */ + + /* L1 Cache variables */ + unsigned long CacheSize; /* L1 Cache size in KB. This is the */ + /* total size of the L1, whether */ + /* combined or split */ + unsigned long CacheAttrib; /* L1CACHE_TYPE */ + unsigned long CacheAssoc; /* L1 Cache associativity. Use this + for combined cache. If split, put + zeros here. */ + unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use + for combined cache. If split, put + zeros here. */ + /* For split L1 Cache: (= combined if combined cache) */ + unsigned long I_CacheSize; + unsigned long I_CacheAssoc; + unsigned long I_CacheLineSize; + unsigned long D_CacheSize; + unsigned long D_CacheAssoc; + unsigned long D_CacheLineSize; + + /* Translation Lookaside Buffer variables */ + unsigned long TLBSize; /* Total number of TLBs on the system */ + unsigned long TLBAttrib; /* Combined I+D or split TLB */ + unsigned long TLBAssoc; /* TLB Associativity. Use this for + combined TLB. If split, put zeros + here. */ + /* For split TLB: (= combined if combined TLB) */ + unsigned long I_TLBSize; + unsigned long I_TLBAssoc; + unsigned long D_TLBSize; + unsigned long D_TLBAssoc; + + unsigned long ExtendedVPD; /* Offset to extended VPD area; + null if unused */ + } VPD; + +typedef enum _DEVICE_FLAGS { + Enabled = 0x4000, /* 1 - PCI device is enabled */ + Integrated = 0x2000, + Failed = 0x1000, /* 1 - device failed POST code tests */ + Static = 0x0800, /* 0 - dynamically configurable + 1 - static */ + Dock = 0x0400, /* 0 - not a docking station device + 1 - is a docking station device */ + Boot = 0x0200, /* 0 - device cannot be used for BOOT + 1 - can be a BOOT device */ + Configurable = 0x0100, /* 1 - device is configurable */ + Disableable = 0x80, /* 1 - device can be disabled */ + PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ + ReadOnly = 0x20, /* 1 - device is read only */ + Removable = 0x10, /* 1 - device is removable */ + ConsoleIn = 0x08, + ConsoleOut = 0x04, + Input = 0x02, + Output = 0x01 + } DEVICE_FLAGS; + +typedef enum _BUS_ID { + ISADEVICE = 0x01, + EISADEVICE = 0x02, + PCIDEVICE = 0x04, + PCMCIADEVICE = 0x08, + PNPISADEVICE = 0x10, + MCADEVICE = 0x20, + MXDEVICE = 0x40, /* Devices on mezzanine bus */ + PROCESSORDEVICE = 0x80, /* Devices on processor bus */ + VMEDEVICE = 0x100, + } BUS_ID; + +typedef struct _DEVICE_ID { + unsigned long BusId; /* See BUS_ID enum above */ + unsigned long DevId; /* Big Endian format */ + unsigned long SerialNum; /* For multiple usage of a single + DevId */ + unsigned long Flags; /* See DEVICE_FLAGS enum above */ + unsigned char BaseType; /* See pnp.h for bit definitions */ + unsigned char SubType; /* See pnp.h for bit definitions */ + unsigned char Interface; /* See pnp.h for bit definitions */ + unsigned char Spare; + } DEVICE_ID; + +typedef union _BUS_ACCESS { + struct _PnPAccess{ + unsigned char CSN; + unsigned char LogicalDevNumber; + unsigned short ReadDataPort; + } PnPAccess; + struct _ISAAccess{ + unsigned char SlotNumber; /* ISA Slot Number generally not + available; 0 if unknown */ + unsigned char LogicalDevNumber; + unsigned short ISAReserved; + } ISAAccess; + struct _MCAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short MCAReserved; + } MCAAccess; + struct _PCMCIAAccess{ + unsigned char SlotNumber; + unsigned char LogicalDevNumber; + unsigned short PCMCIAReserved; + } PCMCIAAccess; + struct _EISAAccess{ + unsigned char SlotNumber; + unsigned char FunctionNumber; + unsigned short EISAReserved; + } EISAAccess; + struct _PCIAccess{ + unsigned char BusNumber; + unsigned char DevFuncNumber; + unsigned short PCIReserved; + } PCIAccess; + struct _ProcBusAccess{ + unsigned char BusNumber; + unsigned char BUID; + unsigned short ProcBusReserved; + } ProcBusAccess; + } BUS_ACCESS; + +/* Per logical device information */ +typedef struct _PPC_DEVICE { + DEVICE_ID DeviceId; + BUS_ACCESS BusAccess; + + /* The following three are offsets into the DevicePnPHeap */ + /* All are in PnP compressed format */ + unsigned long AllocatedOffset; /* Allocated resource description */ + unsigned long PossibleOffset; /* Possible resource description */ + unsigned long CompatibleOffset; /* Compatible device identifiers */ + } PPC_DEVICE; + +typedef enum _CPU_STATE { + CPU_GOOD = 0, /* CPU is present, and active */ + CPU_GOOD_FW = 1, /* CPU is present, and in firmware */ + CPU_OFF = 2, /* CPU is present, but inactive */ + CPU_FAILED = 3, /* CPU is present, but failed POST */ + CPU_NOT_PRESENT = 255 /* CPU not present */ + } CPU_STATE; + +typedef struct _PPC_CPU { + unsigned long CpuType; /* Result of mfspr from Processor + Version Register (PVR). + PVR(0-15) = Version (e.g. 601) + PVR(16-31 = EC Level */ + unsigned char CpuNumber; /* CPU Number for this processor */ + unsigned char CpuState; /* CPU State, see CPU_STATE enum */ + unsigned short Reserved; + } PPC_CPU; + +typedef struct _PPC_MEM { + unsigned long SIMMSize; /* 0 - absent or bad + 8M, 32M (in MB) */ + } PPC_MEM; + +typedef enum _MEM_USAGE { + Other = 0x8000, + ResumeBlock = 0x4000, /* for use by power management */ + SystemROM = 0x2000, /* Flash memory (populated) */ + UnPopSystemROM = 0x1000, /* Unpopulated part of SystemROM area */ + IOMemory = 0x0800, + SystemIO = 0x0400, + SystemRegs = 0x0200, + PCIAddr = 0x0100, + PCIConfig = 0x80, + ISAAddr = 0x40, + Unpopulated = 0x20, /* Unpopulated part of System Memory */ + Free = 0x10, /* Free part of System Memory */ + BootImage = 0x08, /* BootImage part of System Memory */ + FirmwareCode = 0x04, /* FirmwareCode part of System Memory */ + FirmwareHeap = 0x02, /* FirmwareHeap part of System Memory */ + FirmwareStack = 0x01 /* FirmwareStack part of System Memory*/ + } MEM_USAGE; + +typedef struct _MEM_MAP { + unsigned long Usage; /* See MEM_USAGE above */ + unsigned long BasePage; /* Page number measured in 4KB pages */ + unsigned long PageCount; /* Page count measured in 4KB pages */ + } MEM_MAP; + +typedef struct _RESIDUAL { + unsigned long ResidualLength; /* Length of Residual */ + unsigned char Version; /* of this data structure */ + unsigned char Revision; /* of this data structure */ + unsigned short EC; /* of this data structure */ + /* VPD */ + VPD VitalProductData; + /* CPU */ + unsigned short MaxNumCpus; /* Max CPUs in this system */ + unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ + /* that there are unpopulated or */ + /* otherwise unusable cpu locations */ + PPC_CPU Cpus[MAX_CPUS]; + /* Memory */ + unsigned long TotalMemory; /* Total amount of memory installed */ + unsigned long GoodMemory; /* Total amount of good memory */ + unsigned long ActualNumMemSegs; + MEM_MAP Segs[MAX_MEM_SEGS]; + unsigned long ActualNumMemories; + PPC_MEM Memories[MAX_MEMS]; + /* Devices */ + unsigned long ActualNumDevices; + PPC_DEVICE Devices[MAX_DEVICES]; + unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE]; + } RESIDUAL; + +#ifndef NULL +#define NULL 0 +#endif + +static inline int +residual_fw_is_qemu(RESIDUAL *r) +{ + return QEMU == r->VitalProductData.FirmwareSupplier; +} + +extern RESIDUAL residualCopy; + +extern void print_residual_device_info(void); +#ifndef __BOOT__ +extern PPC_DEVICE *residual_find_device(RESIDUAL *res, unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +#else +extern PPC_DEVICE *residual_find_device(unsigned long BusMask, + unsigned char * DevID, int BaseType, + int SubType, int Interface, int n); +#endif +extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag, + int n); +extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, + unsigned packet_type, + int n); +/* + * Prototypes for methods called only from .S for dependency tracking + */ +uint32_t res_copy(void); + +#endif /* ASM */ +#endif /* ndef _RESIDUAL_ */ diff --git a/bsps/powerpc/include/bsp/start.h b/bsps/powerpc/include/bsp/start.h new file mode 100644 index 0000000000..ab718a87ee --- /dev/null +++ b/bsps/powerpc/include/bsp/start.h @@ -0,0 +1,84 @@ +/** + * @file + * + * @ingroup powerpc_start + * + * @brief System low level start. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SHARED_START_H +#define LIBBSP_POWERPC_SHARED_START_H + +#include <stddef.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup powerpc_start PowerPC System Start + * + * @ingroup powerpc_shared + * + * @brief PowerPC low level start. + * + * @{ + */ + +#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) + +#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) + +/** +* @brief System start entry. +*/ +void _start(void); + +/** + * Zeros @a byte_count bytes starting at @a begin. + * + * It wraps around in case of an address overflow. The stack will not be used. + * The code is position independent. It uses the data cache block zero + * instruction in case the data cache is enabled. There are no alignment + * constains for @a begin and @a byte_count. + * + * @see bsp_start_zero_begin, bsp_start_zero_end, and bsp_start_zero_size. + */ +void BSP_START_TEXT_SECTION bsp_start_zero(void *begin, size_t byte_count); + +/** + * @brief Symbol which equals the bsp_start_zero() code begin. + */ +extern char bsp_start_zero_begin []; + +/** + * @brief Symbol which equals the bsp_start_zero() code end. + */ +extern char bsp_start_zero_end []; + +/** + * @brief Symbol which equals the bsp_start_zero() code size. + */ +extern char bsp_start_zero_size []; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_SHARED_START_H */ diff --git a/bsps/powerpc/include/bsp/tictac.h b/bsps/powerpc/include/bsp/tictac.h new file mode 100644 index 0000000000..31c7386943 --- /dev/null +++ b/bsps/powerpc/include/bsp/tictac.h @@ -0,0 +1,78 @@ +/** + * @file + * + * @ingroup powerpc_shared + * + * @brief Header file for tic-tac code. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @brief Reset reference ticks for tac(). + */ +static inline void tic() +{ + uint32_t tmp; + asm volatile ( + "mftb 0;" + "stw 0, ppc_tic_tac@sdarel(13);" + : "=r" (tmp) + ); +} + +/** + * @brief Returns number of ticks since last tic(). + */ +static inline uint32_t tac() +{ + uint32_t ticks; + uint32_t tmp; + asm volatile ( + "mftb %0;" + "lwz %1, ppc_tic_tac@sdarel(13);" + "subf %0, %1, %0;" + : "=r" (ticks), "=r" (tmp) + ); + return ticks; +} + +/** + * @brief Reset reference ticks for bam(). + */ +static inline void boom() +{ + uint32_t tmp; + asm volatile ( + "mftb 0;" + "stw 0, ppc_boom_bam@sdarel(13);" + : "=r" (tmp) + ); +} + +/** + * @brief Returns number of ticks since last boom(). + */ +static inline uint32_t bam() +{ + uint32_t ticks; + uint32_t tmp; + asm volatile ( + "mftb %0;" + "lwz %1, ppc_boom_bam@sdarel(13);" + "subf %0, %1, %0;" + : "=r" (ticks), "=r" (tmp) + ); + return ticks; +} diff --git a/bsps/powerpc/include/bsp/tsec.h b/bsps/powerpc/include/bsp/tsec.h new file mode 100644 index 0000000000..4efbfa2ab0 --- /dev/null +++ b/bsps/powerpc/include/bsp/tsec.h @@ -0,0 +1,380 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares the MPC83xx TSEC networking driver | +\*===============================================================*/ + +#ifndef LIBCPU_POWERPC_TSEC_H +#define LIBCPU_POWERPC_TSEC_H + +#include <stdint.h> + +#include <bsp/irq.h> +#include <bsp/tsec-config.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + /* + * this enumeration defines the index + * of a given rmon mib counter + * in the tsec_rmon_mib array + */ +typedef enum { + /* TSEC1 Transmit and Receive Counters */ + TSEC_RMON_TR64, /* 0x2_4680 Transmit and receive 64-byte frame counter register R/W 0x0000_0000 15.5.3.7.1/15-60 */ + TSEC_RMON_TR127, /* 0x2_4684 Transmit and receive 65- to 127-byte frame counter register R/W 0x0000_0000 15.5.3.7.2/15-61 */ + TSEC_RMON_TR255, /* 0x2_4688 Transmit and receive 128- to 255-byte frame counter register R/W 0x0000_0000 15.5.3.7.3/15-61 */ + TSEC_RMON_TR511, /* 0x2_468C Transmit and receive 256- to 511-byte frame counter register R/W 0x0000_0000 15.5.3.7.4/15-62 */ + TSEC_RMON_TR1K, /* 0x2_4690 Transmit and receive 512- to 1023-byte frame counter register R/W 0x0000_0000 15.5.3.7.5/15-62 */ + TSEC_RMON_TRMAX, /* 0x2_4694 Transmit and receive 1024- to 1518-byte frame counter register R/W 0x0000_0000 15.5.3.7.6/15-63 */ + TSEC_RMON_TRMGV, /* 0x2_4698 Transmit and receive 1519- to 1522-byte good VLAN frame count register R/W 0x0000_0000 15.5.3.7.7/15-63 */ + /* TSEC1 Receive Counters */ + TSEC_RMON_RBYT, /* 0x2_469C Receive byte counter register R/W 0x0000_0000 15.5.3.7.8/15-64 */ + TSEC_RMON_RPKT, /* 0x2_46A0 Receive packet counter register R/W 0x0000_0000 15.5.3.7.9/15-64 */ + TSEC_RMON_RFCS, /* 0x2_46A4 Receive FCS error counter register R/W 0x0000_0000 15.5.3.7.10/15-65 */ + TSEC_RMON_RMCA, /* 0x2_46A8 Receive multicast packet counter register R/W 0x0000_0000 15.5.3.7.11/15-65 */ + TSEC_RMON_RBCA, /* 0x2_46AC Receive broadcast packet counter register R/W 0x0000_0000 15.5.3.7.12/15-66 */ + TSEC_RMON_RXCF, /* 0x2_46B0 Receive control frame packet counter register R/W 0x0000_0000 15.5.3.7.13/15-66 */ + TSEC_RMON_RXPF, /* 0x2_46B4 Receive PAUSE frame packet counter register R/W 0x0000_0000 15.5.3.7.14/15-67 */ + TSEC_RMON_RXUO, /* 0x2_46B8 Receive unknown OP code counter register R/W 0x0000_0000 15.5.3.7.15/15-67 */ + TSEC_RMON_RALN, /* 0x2_46BC Receive alignment error counter register R/W 0x0000_0000 15.5.3.7.16/15-68 */ + TSEC_RMON_RFLR, /* 0x2_46C0 Receive frame length error counter register R/W 0x0000_0000 15.5.3.7.17/15-68 */ + TSEC_RMON_RCDE, /* 0x2_46C4 Receive code error counter register R/W 0x0000_0000 15.5.3.7.18/15-69 */ + TSEC_RMON_RCSE, /* 0x2_46C8 Receive carrier sense error counter register R/W 0x0000_0000 15.5.3.7.19/15-69 */ + TSEC_RMON_RUND, /* 0x2_46CC Receive undersize packet counter register R/W 0x0000_0000 15.5.3.7.20/15-70 */ + TSEC_RMON_ROVR, /* 0x2_46D0 Receive oversize packet counter register R/W 0x0000_0000 15.5.3.7.21/15-70 */ + TSEC_RMON_RFRG, /* 0x2_46D4 Receive fragments counter register R/W 0x0000_0000 15.5.3.7.22/15-71 */ + TSEC_RMON_RJBR, /* 0x2_46D8 Receive jabber counter register R/W 0x0000_0000 15.5.3.7.23/15-71 */ + TSEC_RMON_RDRP, /* 0x2_46DC Receive drop register R/W 0x0000_0000 15.5.3.7.24/15-72 */ + /* TSEC1 Transmit Counters */ + TSEC_RMON_TBYT, /* 0x2_46E0 Transmit byte counter register R/W 0x0000_0000 15.5.3.7.25/15-72 */ + TSEC_RMON_TPKT, /* 0x2_46E4 Transmit packet counter register R/W 0x0000_0000 15.5.3.7.26/15-73 */ + TSEC_RMON_TMCA, /* 0x2_46E8 Transmit multicast packet counter register R/W 0x0000_0000 15.5.3.7.27/15-73 */ + TSEC_RMON_TBCA, /* 0x2_46EC Transmit broadcast packet counter register R/W 0x0000_0000 15.5.3.7.28/15-74 */ + TSEC_RMON_TXPF, /* 0x2_46F0 Transmit PAUSE control frame counter register R/W 0x0000_0000 15.5.3.7.29/15-74 */ + TSEC_RMON_TDFR, /* 0x2_46F4 Transmit deferral packet counter register R/W 0x0000_0000 15.5.3.7.30/15-75 */ + TSEC_RMON_TEDF, /* 0x2_46F8 Transmit excessive deferral packet counter register R/W 0x0000_0000 15.5.3.7.31/15-75 */ + TSEC_RMON_TSCL, /* 0x2_46FC Transmit single collision packet counter register R/W 0x0000_0000 15.5.3.7.32/15-76 */ + TSEC_RMON_TMCL, /* 0x2_4700 Transmit multiple collision packet counter register R/W 0x0000_0000 15.5.3.7.33/15-76 */ + TSEC_RMON_TLCL, /* 0x2_4704 Transmit late collision packet counter register R/W 0x0000_0000 15.5.3.7.34/15-77 */ + TSEC_RMON_TXCL, /* 0x2_4708 Transmit excessive collision packet counter register R/W 0x0000_0000 15.5.3.7.35/15-77 */ + TSEC_RMON_TNCL, /* 0x2_470C Transmit total collision counter register R/W 0x0000_0000 15.5.3.7.36/15-78 */ + TSEC_RESERVED1, /* 0x2_4710 Reserved, should be cleared R 0x0000_0000 */ + TSEC_RMON_TDRP, /* 0x2_4714 Transmit drop frame counter register R/W 0x0000_0000 15.5.3.7.37/15-78 */ + TSEC_RMON_TJBR, /* 0x2_4718 Transmit jabber frame counter register R/W 0x0000_0000 15.5.3.7.38/15-79 */ + TSEC_RMON_TFCS, /* 0x2_471C Transmit FCS error counter register R/W 0x0000_0000 15.5.3.7.39/15-79 */ + TSEC_RMON_TXCF, /* 0x2_4720 Transmit control frame counter register R/W 0x0000_0000 15.5.3.7.40/15-80 */ + TSEC_RMON_TOVR, /* 0x2_4724 Transmit oversize frame counter register R/W 0x0000_0000 15.5.3.7.41/15-80 */ + TSEC_RMON_TUND, /* 0x2_4728 Transmit undersize frame counter register R/W 0x0000_0000 15.5.3.7.42/15-81 */ + TSEC_RMON_TFRG, /* 0x2_472C Transmit fragments frame counter register R/W 0x0000_0000 15.5.3.7.43/15-81 */ + TSEC_RMON_CNT +} tsec_rmon_idx; + + /* TSEC1/2 General Control and Status Registers */ +typedef struct { + uint8_t reserved0x2_4000[0x24010-0x24000]; /* 0x2_4000--0x2_400F Reserved, should be cleared */ + uint32_t ievent; /* 0x2_4010 Interrupt event register R/W 0x0000_0000 15.5.3.1.1/15-19 */ + uint32_t imask; /* 0x2_4014 Interrupt mask register R/W 0x0000_0000 15.5.3.1.2/15-22 */ + uint32_t edis; /* 0x2_4018 Error disabled register R/W 0x0000_0000 15.5.3.1.3/15-24 */ + uint8_t reserved0x2_401c[0x24020-0x2401c]; /* 0x2_401c--0x2_401f Reserved, should be cleared */ + uint32_t ecntrl; /* 0x2_4020 Ethernet control register R/W 0x0000_0000 15.5.3.1.4/15-25 */ + uint32_t minflr; /* 0x2_4024 Minimum frame length register R/W 0x0000_0040 15.5.3.1.5/15-26 */ + uint32_t ptv; /* 0x2_4028 Pause time value register R/W 0x0000_0000 15.5.3.1.6/15-27 */ + uint32_t dmactrl; /* 0x2_402C DMA control register R/W 0x0000_0000 15.5.3.1.7/15-28 */ + uint32_t tbipa; /* 0x2_4030 TBI PHY address register R/W 0x0000_0000 15.5.3.1.8/15-29 */ + uint8_t reserved0x2_4034[0x2408c-0x24034]; /* 0x2_4034--0x2_408b Reserved, should be cleared */ + /* TSEC1 FIFO Control and Status Registers */ + uint32_t fifo_tx_thr; /* 0x2_408C FIFO transmit threshold register R/W 0x0000_0100 15.5.3.2.1/15-30 */ + uint8_t reserved0x2_4090[0x24094-0x24090]; /* 0x2_4090--0x2_4093 Reserved, should be cleared */ + uint32_t fifo_tx_sp; /* 0x2_4094 FIFO transmit space available register R/W 0x0000_0010 15.5.3.2.2/15-31 */ + uint32_t fifo_tx_starve; /* 0x2_4098 FIFO transmit starve register R/W 0x0000_0080 15.5.3.2.3/15-31 */ + uint32_t fifo_tx_starve_shutoff; /* 0x2_409C FIFO transmit starve shutoff register R/W 0x0000_0100 15.5.3.2.4/15-32 */ + uint8_t reserved0x2_40A0[0x24100-0x240A0]; /* 0x2_40A0--0x2_40ff Reserved, should be cleared */ + /* TSEC1 Transmit Control and Status Registers */ + uint32_t tctrl; /* 0x2_4100 Transmit control register R/W 0x0000_0000 15.5.3.3.1/15-33 */ + uint32_t tstat; /* 0x2_4104 Transmit status register R/W 0x0000_0000 15.5.3.3.2/15-34 */ + uint8_t reserved0x2_4108[0x24110-0x24108]; /* 0x2_4108 Reserved, should be cleared R 0x0000_0000 */ + uint32_t txic; /* 0x2_4110 Transmit interrupt coalescing configuration register R/W 0x0000_0000 */ + uint8_t reserved0x2_4114[0x24124-0x24114]; /* 0x2_4114--0x2_4120 Reserved, should be cleared */ + uint32_t ctbptr; /* 0x2_4124 Current TxBD pointer register R 0x0000_0000 15.5.3.3.5/15-36 */ + uint8_t reserved0x2_4128[0x24184-0x24128]; /* 0x2_4128--0x2_4180 Reserved, should be cleared */ + uint32_t tbptr; /* 0x2_4184 TxBD pointer register R/W 0x0000_0000 15.5.3.3.6/15-36 */ + uint8_t reserved0x2_4188[0x24204-0x24188]; /* 0x2_4188--0x2_4200 Reserved, should be cleared */ + uint32_t tbase; /* 0x2_4204 TxBD base address register R/W 0x0000_0000 15.5.3.3.7/15-37 */ + uint8_t reserved0x2_4208[0x242B0-0x24208]; /* 0x2_4208--0x2_42AC Reserved, should be cleared */ + uint32_t ostbd; /* 0x2_42B0 Out-of-sequence TxBD register R/W 0x0800_0000 15.5.3.3.8/15-37 */ + uint32_t ostbdp; /* 0x2_42B4 Out-of-sequence Tx data buffer pointer register R/W 0x0000_0000 15.5.3.3.9/15-39 */ + uint8_t reserved0x2_42B8[0x24300-0x242B8]; /* 0x2_42B8--0x2_42FC Reserved, should be cleared */ + /* TSEC1 Receive Control and Status Registers */ + uint32_t rctrl; /* 0x2_4300 Receive control register R/W 0x0000_0000 15.5.3.4.1/15-40 */ + uint32_t rstat; /* 0x2_4304 Receive status register R/W 0x0000_0000 15.5.3.4.2/15-41 */ + uint8_t reserved0x2_4308[0x2430C-0x24308]; /* 0x2_4308 Reserved, should be cleared R 0x0000_0000 */ + uint32_t rbdlen; /* 0x2_430C RxBD data length register R 0x0000_0000 15.5.3.4.3/15-41 */ + uint32_t rxic; /* 0x2_4310 Receive interrupt coalescing configuration register R/W 0x0000_0000 15.5.3.4.4/15-42 */ + uint8_t reserved0x2_4314[0x24324-0x24314]; /* 0x2_4314--0x2_4320 Reserved, should be cleared */ + uint32_t crbptr; /* 0x2_4324 Current RxBD pointer register R 0x0000_0000 15.5.3.4.5/15-43 */ + uint8_t reserved0x2_4328[0x24340-0x24328]; /* 0x2_4328--0x2_433C Reserved, should be cleared */ + uint32_t mrblr; /* 0x2_4340 Maximum receive buffer length register R/W 0x0000_0000 15.5.3.4.6/15-43 */ + uint8_t reserved0x2_4344[0x24384-0x24344]; /* 0x2_4344--0x2_4380 Reserved, should be cleared */ + uint32_t rbptr; /* 0x2_4384 RxBD pointer register R/W 0x0000_0000 15.5.3.4.7/15-44 */ + uint8_t reserved0x2_4388[0x24404-0x24388]; /* 0x2_4388--0x2_4400 Reserved, should be cleared */ + uint32_t rbase; /* 0x2_4404 RxBD base address register R/W 0x0000_0000 15.5.3.4.8/15-44 */ + uint8_t reserved0x2_4408[0x24500-0x24408]; /* 0x2_4408--0x2_44FC Reserved, should be cleared */ + /* TSEC1 MAC Registers */ + uint32_t maccfg1; /* 0x2_4500 MAC configuration register 1 R/W, R 0x0000_0000 15.5.3.6.1/15-48 */ + uint32_t maccfg2; /* 0x2_4504 MAC configuration register 2 R/W 0x0000_7000 15.5.3.6.2/15-49 */ + uint32_t ipgifg; /* 0x2_4508 Inter-packet gap/inter-frame gap register R/W 0x4060_5060 15.5.3.6.3/15-51 */ + uint32_t hafdup; /* 0x2_450C Half-duplex register R/W 0x00A1_F037 15.5.3.6.4/15-52 */ + uint32_t maxfrm; /* 0x2_4510 Maximum frame length register R/W 0x0000_0600 15.5.3.6.5/15-53 */ + uint8_t reserved0x2_4514[0x24520-0x24514]; /* 0x2_4514--0x2_451C Reserved, should be cleared */ + uint32_t miimcfg; /* 0x2_4520 MII management configuration register R/W 0x0000_0000 15.5.3.6.6/15-53 */ + uint32_t miimcom; /* 0x2_4524 MII management command register R/W 0x0000_0000 15.5.3.6.7/15-54 */ + uint32_t miimadd; /* 0x2_4528 MII management address register R/W 0x0000_0000 15.5.3.6.8/15-55 */ + uint32_t miimcon; /* 0x2_452C MII management control register W 0x0000_0000 15.5.3.6.9/15-56 */ + uint32_t miimstat; /* 0x2_4530 MII management status register R 0x0000_0000 15.5.3.6.10/15-56 */ + uint32_t miimind; /* 0x2_4534 MII management indicator register R 0x0000_0000 15.5.3.6.11/15-57 */ + uint8_t reserved0x2_4538[0x2453c-0x24538]; /* 0x2_4538 Reserved, should be cleared $ $ */ + uint32_t ifstat; /* 0x2_453C Interface status register Special 0x0000_0001 15.5.3.6.12/15-58 */ + uint32_t macstnaddr[2]; /* 0x2_4540 Station address register, part 1/2 R/W 0x0000_0000 15.5.3.6.13/15-58 */ + uint8_t reserved0x2_4548[0x24680-0x24548]; /* 0x2_4548--0x2_467C Reserved, should be cleared */ + + /* TSEC1 RMON MIB Registers */ + uint32_t rmon_mib[TSEC_RMON_CNT]; + + /* TSEC1 General Registers */ + uint32_t car[2]; /* 0x2_4730 Carry register one/two register R 0x0000_0000 15.5.3.7.44/15-82 */ + uint32_t cam[2]; /* 0x2_4738 Carry register one/two mask register R/W 0xFE01_FFFF 15.5.3.7.46/15-85 */ + uint8_t reserved0x2_4740[0x24800-0x24740]; /* 0x2_4740--0x2_47FC Reserved, should be cleared */ + + /* TSEC1 Hash Function Registers */ + uint32_t iaddr[8]; /* 0x2_4800 Individual address register 0-7 R/W 0x0000_0000 15.5.3.8.1/15-87 */ + uint8_t reserved0x2_4820[0x24880-0x24820]; /* 0x2_4820--0x2_487C Reserved, should be cleared */ + uint32_t gaddr[8]; /* 0x2_4880 Group address register 0-7 R/W 0x0000_0000 15.5.3.8.2/15-88 */ + uint8_t reserved0x2_48A0[0x24B00-0x248A0]; /* 0x2_48A0--0x2_4AFF Reserved, should be cleared */ + + /* TSEC1 Attribute Registers */ + uint8_t reserved0x2_4B00[0x24BF8-0x24B00]; /* 0x2_4B00--0x2_4BF4 Reserved, should be cleared */ + uint32_t attr; /* 0x2_4BF8 Attribute register R 0x0000_0000 */ + uint32_t attreli; /* 0x2_4BFC Attribute extract length and extract index register R/W 0x0000_0000 */ + uint8_t reserved0x2_4C00[0x25000-0x24C00]; /* 0x2_4C00--0x2_4FFF Reserved, should be cleared */ +} tsec_registers; + +/* + * TSEC IEVENT/IMASK bit definitions + */ +#define TSEC_IEVENT_BABR (1<<(31- 0)) +#define TSEC_IEVENT_RXC (1<<(31- 1)) +#define TSEC_IEVENT_BSY (1<<(31- 2)) +#define TSEC_IEVENT_EBERR (1<<(31- 3)) +#define TSEC_IEVENT_MSRO (1<<(31- 5)) +#define TSEC_IEVENT_GTSC (1<<(31- 6)) +#define TSEC_IEVENT_BABT (1<<(31- 7)) +#define TSEC_IEVENT_TXC (1<<(31- 8)) +#define TSEC_IEVENT_TXE (1<<(31- 9)) +#define TSEC_IEVENT_TXB (1<<(31-10)) +#define TSEC_IEVENT_TXF (1<<(31-11)) +#define TSEC_IEVENT_LC (1<<(31-13)) +#define TSEC_IEVENT_CRL_XDA (1<<(31-14)) +#define TSEC_IEVENT_XFUN (1<<(31-15)) +#define TSEC_IEVENT_RXB (1<<(31-16)) +#define TSEC_IEVENT_MMRD (1<<(31-21)) +#define TSEC_IEVENT_MMWR (1<<(31-22)) +#define TSEC_IEVENT_GRSC (1<<(31-23)) +#define TSEC_IEVENT_RXF (1<<(31-24)) + +/* + * TSEC DMACTRL bit definitions + */ +#define TSEC_DMACTL_TDSEN (1<<(31-24)) +#define TSEC_DMACTL_TBDSEN (1<<(31-25)) +#define TSEC_DMACTL_GRS (1<<(31-27)) +#define TSEC_DMACTL_GTS (1<<(31-28)) +#define TSEC_DMACTL_WWR (1<<(31-30)) +#define TSEC_DMACTL_WOP (1<<(31-31)) + +/* + * TSEC TSTAT bit definitions + */ +#define TSEC_TSTAT_THLT (1<<(31-0)) + +/* + * TSEC RSTAT bit definitions + */ +#define TSEC_RSTAT_QHLT (1<<(31-8)) + /* + * TSEC ECNTRL bit positions + */ +#define TSEC_ECNTRL_CLRCNT (1 << (31-17)) /* Clear stat counters */ +#define TSEC_ECNTRL_AUTOZ (1 << (31-18)) /* auto-zero read counters */ +#define TSEC_ECNTRL_STEN (1 << (31-19)) /* enable statistics */ +#define TSEC_ECNTRL_TBIM (1 << (31-26)) /* ten-bit-interface */ +#define TSEC_ECNTRL_RPM (1 << (31-27)) /* reduced signal mode */ +#define TSEC_ECNTRL_R100M (1 << (31-28)) /* RGMII100 mode */ + /* + * TSEC EDIS bit positions + */ +#define TSEC_EDIS_BSYDIS (1 << (31- 2)) /* Busy disable */ +#define TSEC_EDIS_EBERRDIS (1 << (31- 3)) /* bus error disable */ +#define TSEC_EDIS_TXEDIS (1 << (31- 9)) /* Tx error disable */ +#define TSEC_EDIS_LCDIS (1 << (31-13)) /* Late collision disable */ +#define TSEC_EDIS_CRLXDADIS (1 << (31-14)) /* Collision Retry disable */ +#define TSEC_EDIS_FUNDIS (1 << (31-15)) /* Tx FIFO underrun disable*/ + + /* + * TSEC RCTRL bit positions + */ +#define TSEC_RCTRL_BC_REJ (1 << (31-27)) /* Broadcast Reject */ +#define TSEC_RCTRL_PROM (1 << (31-28)) /* Promiscuous */ +#define TSEC_RCTRL_RSF (1 << (31-29)) /* Receive short frames */ + + /* + * TSEC TXIC bit positions + */ +#define TSEC_TXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ +#define TSEC_TXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ +#define TSEC_TXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ + + /* + * TSEC RXIC bit positions + */ +#define TSEC_RXIC_ICEN (1 << (31- 0)) /* Irq coalescing enable */ +#define TSEC_RXIC_ICFCT(n) (((n)&0xff) << (31-10)) /* Frame coal. cnt */ +#define TSEC_RXIC_ICTT(n) (((n)&0xffff) << (31-31)) /* Buf. coal. cnt */ + + /* + * TSEC MACCFG1 bit positions + */ +#define TSEC_MACCFG1_SOFTRST (1 << (31- 0)) /* Soft Reset */ +#define TSEC_MACCFG1_RES_RXMC (1 << (31-12)) /* Reset Rx MAC block */ +#define TSEC_MACCFG1_RES_TXMC (1 << (31-13)) /* Reset Tx MAC block */ +#define TSEC_MACCFG1_RES_RXFUN (1 << (31-14)) /* Reset Rx function blk*/ +#define TSEC_MACCFG1_RES_TXFUN (1 << (31-15)) /* Reset Tx function blk*/ +#define TSEC_MACCFG1_LOOPBACK (1 << (31-23)) /* Loopback mode */ +#define TSEC_MACCFG1_RX_FLOW (1 << (31-26)) /* Receive Flow Ctrl */ +#define TSEC_MACCFG1_TX_FLOW (1 << (31-27)) /* Transmit Flow Ctrl */ +#define TSEC_MACCFG1_SYNVRXEN (1 << (31-28)) /* Sync Receive Enable */ +#define TSEC_MACCFG1_RXEN (1 << (31-29)) /* Receive Enable */ +#define TSEC_MACCFG1_SYNVTXEN (1 << (31-30)) /* Sync Transmit Enable */ +#define TSEC_MACCFG1_TXEN (1 << (31-31)) /* Transmit Enable */ + + /* + * TSEC MACCFG2 bit positions + */ +#define TSEC_MACCFG2_PRELEN(n) (((n)&0x0f) << (31-19)) /* Preamble len*/ + +#define TSEC_MACCFG2_IFMODE_MSK (3 << (31-23)) /* mode mask */ +#define TSEC_MACCFG2_IFMODE_NIB (1 << (31-23)) /* nibble mode */ +#define TSEC_MACCFG2_IFMODE_BYT (2 << (31-23)) /* byte mode */ + +#define TSEC_MACCFG2_HUGE_FRAME (1 << (31-26)) /* Huge Frame */ +#define TSEC_MACCFG2_LENGTH_CHK (1 << (31-27)) /* Length Check */ +#define TSEC_MACCFG2_PAD_CRC (1 << (31-29)) /* MAC adds PAD/CRC */ +#define TSEC_MACCFG2_CRC_EN (1 << (31-30)) /* CRC enable */ +#define TSEC_MACCFG2_FULLDUPLEX (1 << (31-31)) /* Full Duplex Mode */ + + /* + * TSEC MIIMADD bit positions + */ +#define TSEC_MIIMADD_PHY(n) (((n) & 0x3f)<<(31- 23)) /* PHY addr */ +#define TSEC_MIIMADD_REGADDR(n) (((n) & 0x3f)<<(31- 31)) /* PHY addr */ + + /* + * TSEC MIIMCOM bit positions + */ +#define TSEC_MIIMCOM_SCAN (1 << (31-30)) /* Scan command */ +#define TSEC_MIIMCOM_READ (1 << (31-31)) /* Read command */ + + /* + * TSEC MIIMIND bit positions + */ +#define TSEC_MIIMIND_NVAL (1 << (31-29)) /* not valid */ +#define TSEC_MIIMIND_SCAN (1 << (31-30)) /* Scan in progress */ +#define TSEC_MIIMIND_BUSY (1 << (31-31)) /* Acc. in progress */ + + /* + * TSEC ATTR bit positions + */ +#define TSEC_ATTR_RDSEN (1 << (31-24)) /* read data snoop */ +#define TSEC_ATTR_RBDSEN (1 << (31-25)) /* read BD snoop */ + +typedef struct { + volatile uint16_t status; + volatile uint16_t length; + volatile void *buffer; +} PQBufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define BD_EMPTY (1<<15) +#define BD_RO1 (1<<14) +#define BD_WRAP (1<<13) +#define BD_INTERRUPT (1<<12) +#define BD_LAST (1<<11) +#define BD_CONTROL_CHAR (1<<11) +#define BD_FIRST_IN_FRAME (1<<10) +#define BD_MISS (1<<8) +#define BD_BROADCAST (1<<7) +#define BD_MULTICAST (1<<6) +#define BD_LONG (1<<5) +#define BD_NONALIGNED (1<<4) +#define BD_SHORT (1<<3) +#define BD_CRC_ERROR (1<<2) +#define BD_OVERRUN (1<<1) +#define BD_COLLISION (1<<0) + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define BD_READY (1<<15) +#define BD_PAD_CRC (1<<14) +/* WRAP/Interrupt as in Rx BDs */ +#define BD_TX_CRC (1<<10) +#define BD_DEFER (1<<9) +#define BD_TO1 (1<<8) +#define BD_HFE_ (1<<7) +#define BD_LATE_COLLISION (1<<7) +#define BD_RETRY_LIMIT (1<<6) +#define BD_RETRY_COUNT(x) (((x)&0x3C)>>2) +#define BD_UNDERRUN (1<<1) +#define BD_TXTRUNC (1<<0) + +struct rtems_bsdnet_ifconfig; + +typedef struct { + int unit_number; + char *unit_name; + volatile tsec_registers *reg_ptr; + volatile tsec_registers *mdio_ptr; + rtems_irq_number irq_num_tx; + rtems_irq_number irq_num_rx; + rtems_irq_number irq_num_err; + int phy_default; +} tsec_config; + +int tsec_driver_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_TSEC_H */ diff --git a/bsps/powerpc/include/bsp/u-boot-board-info.h b/bsps/powerpc/include/bsp/u-boot-board-info.h new file mode 100644 index 0000000000..b377705687 --- /dev/null +++ b/bsps/powerpc/include/bsp/u-boot-board-info.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __U_BOOT_H__ +#define __U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + unsigned long bi_immr_base; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long bi_mbar_base; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83xx) + unsigned long bi_immrbar; +#endif +#if defined(CONFIG_MPC8220) + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_inpfreq; /* Input Freq, In MHz */ + unsigned long bi_pcifreq; /* PCI Freq, in MHz */ + unsigned long bi_pevfreq; /* PEV Freq, in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ + unsigned long bi_vcofreq; /* VCO Freq, in MHz */ +#endif + unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#if defined(CONFIG_CPM2) + unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ + unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ + unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ + unsigned long bi_vco; /* VCO Out from PLL, in MHz */ +#endif +#if defined(CONFIG_MPC512X) + unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ +#endif /* CONFIG_MPC512X */ +#if defined(CONFIG_MPC5xxx) + unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ + unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ +#endif + unsigned long bi_baudrate; /* Console Baudrate */ +#if defined(CONFIG_405) || \ + defined(CONFIG_405GP) || \ + defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ + defined(CONFIG_440) + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ + unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ + unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ +#endif +#if defined(CONFIG_HYMOD) + hymod_conf_t bi_hymod_conf; /* hymod configuration information */ +#endif + +#ifdef CONFIG_HAS_ETH1 + unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH2 + unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH4 + unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH5 + unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + unsigned int bi_opbfreq; /* OPB clock in Hz */ + int bi_iic_fast[2]; /* Use fast i2c mode */ +#endif +#if defined(CONFIG_NX823) + unsigned char bi_sernum[8]; +#endif +#if defined(CONFIG_4xx) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ +#elif defined(CONFIG_405EP) || defined(CONFIG_440) + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ +#else + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ +#endif +#endif /* defined(CONFIG_4xx) */ +} bd_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __U_BOOT_H__ */ diff --git a/bsps/powerpc/include/bsp/uart.h b/bsps/powerpc/include/bsp/uart.h new file mode 100644 index 0000000000..b7539b5b7b --- /dev/null +++ b/bsps/powerpc/include/bsp/uart.h @@ -0,0 +1,190 @@ + +/* + * This software is Copyright (C) 1998 by T.sqware - all rights limited + * It is provided in to the public domain "as is", can be freely modified + * as far as this copyight notice is kept unchanged, but does not imply + * an endorsement by T.sqware of the product in which it is included. + */ + +#ifndef _BSPUART_H +#define _BSPUART_H + +#include <bsp/irq.h> + +#include <sys/ioctl.h> +#include <rtems/libio.h> + +void BSP_uart_init(int uart, int baud, int hwFlow); +void BSP_uart_set_baud(int uart, int baud); +void BSP_uart_intr_ctrl(int uart, int cmd); +void BSP_uart_throttle(int uart); +void BSP_uart_unthrottle(int uart); +int BSP_uart_polled_status(int uart); +void BSP_uart_polled_write(int uart, int val); +int BSP_uart_polled_read(int uart); +void BSP_uart_termios_set(int uart, void *ttyp); +ssize_t BSP_uart_termios_write_com(int minor, const char *buf, size_t len); +int BSP_uart_termios_read_com (int minor); +void BSP_uart_termios_isr_com1(void *unused); +void BSP_uart_termios_isr_com2(void *unused); +void BSP_uart_dbgisr_com1(void); +void BSP_uart_dbgisr_com2(void); +int BSP_uart_install_isr(int uart, rtems_irq_hdl handler); +int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler); +ssize_t BSP_uart_termios_write_polled(int minor, const char *buf, size_t len); +int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg); +int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg); + +extern unsigned BSP_poll_char_via_serial(void); +extern void BSP_output_char_via_serial(const char val); +extern int BSPConsolePort; +extern int BSPBaseBaud; + +/* Special IOCTLS to install a lowlevel 'BREAK' handler */ + +/* pass a BSP_UartBreakCb pointer to ioctl when retrieving + * or installing break callback + */ +typedef void (*BSP_UartBreakCbProc)( + int uartMinor, + unsigned uartRBRLSRStatus, + void *termiosPrivatePtr, + void *private +); + +typedef struct BSP_UartBreakCbRec_ { + BSP_UartBreakCbProc handler; /* NOTE: handler runs in INTERRUPT CONTEXT */ + void *private; /* closure pointer which is passed to the callback */ +} BSP_UartBreakCbRec, *BSP_UartBreakCb; + +#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec)) +#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec)) + +/* + * Command values for BSP_uart_intr_ctrl(), + * values are strange in order to catch errors + * with assert + */ +#define BSP_UART_INTR_CTRL_DISABLE (0) +#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ +#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ +#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ + +/* Return values for uart_polled_status() */ +#define BSP_UART_STATUS_ERROR (-1) /* No character */ +#define BSP_UART_STATUS_NOCHAR (0) /* No character */ +#define BSP_UART_STATUS_CHAR (1) /* Character present */ +#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ + +/* PC UART definitions */ +#define BSP_UART_COM1 (0) +#define BSP_UART_COM2 (1) + +/* + * Offsets from base + */ + +/* DLAB 0 */ +#define RBR (0) /* Rx Buffer Register (read) */ +#define THR (0) /* Tx Buffer Register (write) */ +#define IER (1) /* Interrupt Enable Register */ + +/* DLAB X */ +#define IIR (2) /* Interrupt Ident Register (read) */ +#define FCR (2) /* FIFO Control Register (write) */ +#define LCR (3) /* Line Control Register */ +#define MCR (4) /* Modem Control Register */ +#define LSR (5) /* Line Status Register */ +#define MSR (6) /* Modem Status Register */ +#define SCR (7) /* Scratch register */ + +/* DLAB 1 */ +#define DLL (0) /* Divisor Latch, LSB */ +#define DLM (1) /* Divisor Latch, MSB */ +#define AFR (2) /* Alternate Function register */ + +/* + * Interrupt source definition via IIR + */ +#define MODEM_STATUS 0 +#define NO_MORE_INTR 1 +#define TRANSMITTER_HODING_REGISTER_EMPTY 2 +#define RECEIVER_DATA_AVAIL 4 +#define RECEIVER_ERROR 6 +#define CHARACTER_TIMEOUT_INDICATION 12 + +/* + * Bits definition of IER + */ +#define RECEIVE_ENABLE 0x1 +#define TRANSMIT_ENABLE 0x2 +#define RECEIVER_LINE_ST_ENABLE 0x4 +#define MODEM_ENABLE 0x8 +#define INTERRUPT_DISABLE 0x0 + +/* + * Bits definition of the Line Status Register (LSR) + */ +#define DR 0x01 /* Data Ready */ +#define OE 0x02 /* Overrun Error */ +#define PE 0x04 /* Parity Error */ +#define FE 0x08 /* Framing Error */ +#define BI 0x10 /* Break Interrupt */ +#define THRE 0x20 /* Transmitter Holding Register Empty */ +#define TEMT 0x40 /* Transmitter Empty */ +#define ERFIFO 0x80 /* Error receive Fifo */ + +/* + * Bits definition of the MODEM Control Register (MCR) + */ +#define DTR 0x01 /* Data Terminal Ready */ +#define RTS 0x02 /* Request To Send */ +#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */ +#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */ +#define LB 0x10 /* Enable Internal Loop Back */ + +/* + * Bits definition of the Line Control Register (LCR) + */ +#define CHR_5_BITS 0 +#define CHR_6_BITS 1 +#define CHR_7_BITS 2 +#define CHR_8_BITS 3 + +#define WL 0x03 /* Word length mask */ +#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ +#define PEN 0x08 /* Parity Enabled */ +#define EPS 0x10 /* Even Parity Select, otherwise Odd */ +#define SP 0x20 /* Stick Parity */ +#define BCB 0x40 /* Break Control Bit */ +#define DLAB 0x80 /* Enable Divisor Latch Access */ + +/* + * Bits definition of the MODEM Status Register (MSR) + */ +#define DCTS 0x01 /* Delta Clear To Send */ +#define DDSR 0x02 /* Delta Data Set Ready */ +#define TERI 0x04 /* Trailing Edge Ring Indicator */ +#define DDCD 0x08 /* Delta Carrier Detect Indicator */ +#define CTS 0x10 /* Clear To Send (when loop back is active) */ +#define DSR 0x20 /* Data Set Ready (when loop back is active) */ +#define RI 0x40 /* Ring Indicator (when loop back is active) */ +#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */ + +/* + * Bits definition of the FIFO Control Register : WD16C552 or NS16550 + */ + +#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ +#define FIFO_EN 0x01 /* Enable the FIFO */ +#define XMIT_RESET 0x02 /* Transmit FIFO Reset */ +#define RCV_RESET 0x04 /* Receive FIFO Reset */ +#define FCR3 0x08 /* do not understand manual! */ + +#define RECEIVE_FIFO_TRIGGER1 0x00 /* trigger RX interrupt after 1 byte */ +#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger RX interrupt after 4 bytes */ +#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger RX interrupt after 8 bytes */ +#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */ +#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ + +#endif /* _BSPUART_H */ diff --git a/bsps/powerpc/include/bsp/vectors.h b/bsps/powerpc/include/bsp/vectors.h new file mode 100644 index 0000000000..81526eb4b0 --- /dev/null +++ b/bsps/powerpc/include/bsp/vectors.h @@ -0,0 +1,493 @@ +/** + * @file + * + * @ingroup ppc_exc + * @ingroup ppc_exc_frame + * + * @brief PowerPC Exceptions API. + */ + +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> + * + * Copyright (C) 2009 embedded brains GmbH. + * + * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> + * to support 603, 603e, 604, 604e exceptions + * + * Moved to "libcpu/powerpc/new-exceptions" and consolidated + * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + * to be common for all PPCs with new exceptions. + * + * Derived from file "libcpu/powerpc/new-exceptions/raw_exception.h". + * Derived from file "libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h". + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */ + +#ifndef LIBCPU_VECTORS_H +#define LIBCPU_VECTORS_H + +#include <bspopts.h> +#include <rtems/score/cpuimpl.h> +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup ppc_exc PowerPC Exceptions + * + * @brief XXX + * + * @{ + */ + +#define ASM_RESET_VECTOR 0x01 +#define ASM_MACH_VECTOR 0x02 +#define ASM_PROT_VECTOR 0x03 +#define ASM_ISI_VECTOR 0x04 +#define ASM_EXT_VECTOR 0x05 +#define ASM_ALIGN_VECTOR 0x06 +#define ASM_PROG_VECTOR 0x07 +#define ASM_FLOAT_VECTOR 0x08 +#define ASM_DEC_VECTOR 0x09 +#define ASM_SYS_VECTOR 0x0C +#define ASM_TRACE_VECTOR 0x0D + +#define ASM_PPC405_APU_UNAVAIL_VECTOR ASM_60X_VEC_ASSIST_VECTOR + +#define ASM_8XX_FLOATASSIST_VECTOR 0x0E +#define ASM_8XX_SOFTEMUL_VECTOR 0x10 +#define ASM_8XX_ITLBMISS_VECTOR 0x11 +#define ASM_8XX_DTLBMISS_VECTOR 0x12 +#define ASM_8XX_ITLBERROR_VECTOR 0x13 +#define ASM_8XX_DTLBERROR_VECTOR 0x14 +#define ASM_8XX_DBREAK_VECTOR 0x1C +#define ASM_8XX_IBREAK_VECTOR 0x1D +#define ASM_8XX_PERIFBREAK_VECTOR 0x1E +#define ASM_8XX_DEVPORT_VECTOR 0x1F + +#define ASM_5XX_FLOATASSIST_VECTOR 0x0E +#define ASM_5XX_SOFTEMUL_VECTOR 0x10 +#define ASM_5XX_IPROT_VECTOR 0x13 +#define ASM_5XX_DPROT_VECTOR 0x14 +#define ASM_5XX_DBREAK_VECTOR 0x1C +#define ASM_5XX_IBREAK_VECTOR 0x1D +#define ASM_5XX_MEBREAK_VECTOR 0x1E +#define ASM_5XX_NMEBREAK_VECTOR 0x1F + +#define ASM_60X_VEC_VECTOR 0x0A +#define ASM_60X_PERFMON_VECTOR 0x0F +#define ASM_60X_IMISS_VECTOR 0x10 +#define ASM_60X_DLMISS_VECTOR 0x11 +#define ASM_60X_DSMISS_VECTOR 0x12 +#define ASM_60X_ADDR_VECTOR 0x13 +#define ASM_60X_SYSMGMT_VECTOR 0x14 +#define ASM_60X_VEC_ASSIST_VECTOR 0x16 +#define ASM_60X_ITM_VECTOR 0x17 + +/* Book E */ +#define ASM_BOOKE_CRIT_VECTOR 0x01 +/* We could use the std. decrementer vector # on bookE, too, + * but the bookE decrementer has slightly different semantics + * so we use a different vector (which happens to be + * the PIT vector on the 405 which is like the booke decrementer) + */ +#define ASM_BOOKE_DEC_VECTOR 0x10 +#define ASM_BOOKE_ITLBMISS_VECTOR 0x11 +#define ASM_BOOKE_DTLBMISS_VECTOR 0x12 +#define ASM_BOOKE_FIT_VECTOR 0x13 +#define ASM_BOOKE_WDOG_VECTOR 0x14 +#define ASM_BOOKE_APU_VECTOR 0x18 +#define ASM_BOOKE_DEBUG_VECTOR ASM_TRACE_VECTOR + +/* e200 and e500 */ +#define ASM_E500_SPE_UNAVAILABLE_VECTOR ASM_60X_VEC_VECTOR +#define ASM_E500_EMB_FP_DATA_VECTOR 0x19 +#define ASM_E500_EMB_FP_ROUND_VECTOR 0x1A +#define ASM_E500_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR + +/* e300 */ +#define ASM_E300_CRIT_VECTOR 0x0A +#define ASM_E300_PERFMON_VECTOR ASM_60X_PERFMON_VECTOR +#define ASM_E300_IMISS_VECTOR ASM_60X_IMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_DLMISS_VECTOR ASM_60X_DLMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_DSMISS_VECTOR ASM_60X_DSMISS_VECTOR /* Special case: Shadowed GPRs */ +#define ASM_E300_ADDR_VECTOR ASM_60X_ADDR_VECTOR +#define ASM_E300_SYSMGMT_VECTOR ASM_60X_SYSMGMT_VECTOR + +/* + * If you change that number make sure to adjust the wrapper code in ppc_exc.S + * and that ppc_exc_handler_table will be correctly initialized. + */ +#define LAST_VALID_EXC 0x1F + +/* DO NOT USE -- this symbol is DEPRECATED + * (only used by libbsp/shared/vectors/vectors.S + * which should not be used by new BSPs). + */ +#define ASM_60X_VEC_VECTOR_OFFSET 0xf20 + +#define ASM_PPC405_FIT_VECTOR_OFFSET 0x1010 +#define ASM_PPC405_WDOG_VECTOR_OFFSET 0x1020 +#define ASM_PPC405_TRACE_VECTOR_OFFSET 0x2000 + +/** @} */ + +/** + * @defgroup ppc_exc_frame PowerPC Exception Frame + * + * @brief XXX + * + * @{ + */ + +/* + * The callee (high level exception code written in C) + * will store the Link Registers (return address) at entry r1 + 4 !!!. + * So let room for it!!!. + */ +#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 + +#define EXC_GENERIC_SIZE (PPC_EXC_FRAME_SIZE + PPC_STACK_RED_ZONE_SIZE) + +#define PPC_EXC_INTERRUPT_FRAME_SIZE CPU_INTERRUPT_FRAME_SIZE + +#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) +#define EXC_VEC_OFFSET EXC_GENERIC_SIZE +#ifndef PPC_CACHE_ALIGNMENT +#error "Missing include file!" +#endif +/* 20 volatile registers + * + cache-aligned area for vcsr, vrsave + * + area for alignment + */ +#define EXC_VEC_SIZE (16*20 + 2*PPC_CACHE_ALIGNMENT) +#else +#define EXC_VEC_SIZE (0) +#endif + +/* + * maintain the EABI requested 8 bytes aligment + * As SVR4 ABI requires 16, make it 16 (as some + * exception may need more registers to be processed...) + */ +#define EXCEPTION_FRAME_END (EXC_GENERIC_SIZE + EXC_VEC_SIZE) + +/** @} */ + +#ifndef ASM + +/** + * @ingroup ppc_exc_frame + * + * @{ + */ + +typedef CPU_Exception_frame BSP_Exception_frame; + +/** @} */ + +/** + * @ingroup ppc_exc + * + * @{ + */ + +/** + * @brief Global exception handler type. + */ +typedef void (*exception_handler_t)(BSP_Exception_frame*); + +/** + * @brief Default global exception handler. + */ +void C_exception_handler(BSP_Exception_frame* excPtr); + +void BSP_printStackTrace(const BSP_Exception_frame *excPtr); + +/** + * @brief Exception categories. + * + * Exceptions of different categories use different SRR registers to save the + * machine state and do different things in the prologue and epilogue. + * + * For now, the CPU descriptions assume this fits into 8 bits. + */ +typedef enum { + PPC_EXC_INVALID = 0, + PPC_EXC_ASYNC = 1, + PPC_EXC_CLASSIC = 2, + PPC_EXC_CLASSIC_ASYNC = PPC_EXC_CLASSIC | PPC_EXC_ASYNC, + PPC_EXC_405_CRITICAL = 4, + PPC_EXC_405_CRITICAL_ASYNC = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC, + PPC_EXC_BOOKE_CRITICAL = 6, + PPC_EXC_BOOKE_CRITICAL_ASYNC = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC, + PPC_EXC_E500_MACHCHK = 8, + PPC_EXC_E500_MACHCHK_ASYNC = PPC_EXC_E500_MACHCHK | PPC_EXC_ASYNC, + PPC_EXC_NAKED = 10 +} ppc_exc_category; + +/** + * @brief Categorie set type. + */ +typedef uint8_t ppc_exc_categories [LAST_VALID_EXC + 1]; + +static inline bool ppc_exc_is_valid_category(ppc_exc_category category) +{ + return (unsigned) category <= (unsigned) PPC_EXC_NAKED; +} + +/** + * @brief Returns the entry address of the vector. + * + * @param[in] vector The vector number. + * @param[in] vector_base The vector table base address. + */ +void *ppc_exc_vector_address(unsigned vector, void *vector_base); + +/** + * @brief Returns the category set for a CPU of type @a cpu, or @c NULL if + * there is no category set available for this CPU. + */ +const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu); + +/** + * @brief Returns the category set for the current CPU, or @c NULL if there is + * no category set available for this CPU. + */ +static inline const ppc_exc_categories *ppc_exc_current_categories(void) +{ + return ppc_exc_categories_for_cpu(ppc_cpu_current()); +} + +/** + * @brief Returns the category for the vector @a vector using the category set + * @a categories. + */ +ppc_exc_category ppc_exc_category_for_vector( + const ppc_exc_categories *categories, + unsigned vector +); + +/** + * @brief Makes a minimal prologue for the vector @a vector with the category + * @a category. + * + * The minimal prologue will be copied to @a prologue. Not more than + * @a prologue_size bytes will be copied. Returns the actual minimal prologue + * size in bytes in @a prologue_size. + * + * @retval RTEMS_SUCCESSFUL Minimal prologue successfully made. + * @retval RTEMS_INVALID_ID Invalid vector number. + * @retval RTEMS_INVALID_NUMBER Invalid category. + * @retval RTEMS_INVALID_SIZE Prologue size to small. + */ +rtems_status_code ppc_exc_make_prologue( + unsigned vector, + void *vector_base, + ppc_exc_category category, + uint32_t *prologue, + size_t *prologue_size +); + +static inline void ppc_exc_initialize_interrupt_stack( + uintptr_t stack_begin, + uintptr_t stack_size +) +{ + uintptr_t stack_end = stack_begin + stack_size; + uintptr_t stack_pointer = stack_end - PPC_MINIMUM_STACK_FRAME_SIZE; + + /* Ensure proper interrupt stack alignment */ + stack_pointer &= ~((uintptr_t) CPU_STACK_ALIGNMENT - 1); + + /* Tag interrupt stack bottom */ + *(uint32_t *) stack_pointer = 0; + + /* Move interrupt stack values to special purpose registers */ + PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG1, stack_pointer); + PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG2, stack_begin); +} + +/** + * @brief Initializes the exception handling. + * + * @see ppc_exc_initialize(). + */ +void ppc_exc_initialize_with_vector_base( + uintptr_t interrupt_stack_begin, + uintptr_t interrupt_stack_size, + void *vector_base +); + +/** + * @brief Initializes the exception handling. + * + * If the initialization fails, then this is a fatal error. The fatal error + * source is RTEMS_FATAL_SOURCE_BSP and the fatal error code is + * PPC_FATAL_EXCEPTION_INITIALIZATION. + * + * Possible error reasons are + * - no category set available for the current CPU, + * - the register r13 does not point to the small data area anchor required by + * SVR4/EABI, or + * - the minimal prologue creation failed. + */ +static inline void ppc_exc_initialize( + uintptr_t interrupt_stack_begin, + uintptr_t interrupt_stack_size +) +{ + ppc_exc_initialize_with_vector_base( + interrupt_stack_begin, + interrupt_stack_size, + NULL + ); +} + +/** + * @brief High-level exception handler type. + * + * @retval 0 The exception was handled and normal execution may resume. + * @retval -1 Reject the exception resulting in a call of the global exception + * handler. + * @retval other Reserved, do not use. + */ +typedef int (*ppc_exc_handler_t)(BSP_Exception_frame *f, unsigned vector); + +/** + * @brief Default high-level exception handler. + * + * @retval -1 Always. + */ +int ppc_exc_handler_default(BSP_Exception_frame *f, unsigned int vector); + +#ifndef PPC_EXC_CONFIG_BOOKE_ONLY + +/** + * @brief Bits for MSR update. + * + * Bits in MSR that are enabled during execution of exception handlers / ISRs + * (on classic PPC these are DR/IR/RI [default], on bookE-style CPUs they should + * be set to 0 during initialization) + * + * By default, the setting of these bits that is in effect when exception + * handling is initialized is used. + */ +extern uint32_t ppc_exc_msr_bits; + +#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */ + +/** + * @brief Cache write back check flag. + * + * (See README under CAVEATS). During initialization + * a check is performed to assert that write-back + * caching is enabled for memory accesses. If a BSP + * runs entirely without any caching then it should + * set this variable to zero prior to initializing + * exceptions in order to skip the test. + * NOTE: The code does NOT support mapping memory + * with cache-attributes other than write-back + * (unless the entire cache is physically disabled) + */ +extern uint32_t ppc_exc_cache_wb_check; + +#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER + /** + * @brief High-level exception handler table. + */ + extern ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; + + /** + * @brief Global exception handler. + */ + extern exception_handler_t globalExceptHdl; +#else /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ + /** + * @brief High-level exception handler table. + */ + extern const ppc_exc_handler_t ppc_exc_handler_table [LAST_VALID_EXC + 1]; + + /** + * @brief Interrupt dispatch routine provided by BSP. + */ + void bsp_interrupt_dispatch(uintptr_t exception_number); +#endif /* PPC_EXC_CONFIG_USE_FIXED_HANDLER */ + +/** + * @brief Set high-level exception handler. + * + * Hook C exception handlers. + * - handlers for asynchronous exceptions run on the ISR stack + * with thread-dispatching disabled. + * - handlers for synchronous exceptions run on the task stack + * with thread-dispatching enabled. + * + * If a particular slot is NULL then the traditional 'globalExcHdl' is used. + * + * ppc_exc_set_handler() registers a handler (returning 0 on success, + * -1 if the vector argument is too big). + * + * It is legal to set a NULL handler. This leads to the globalExcHdl + * being called if an exception for 'vector' occurs. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_INVALID_ID Invalid vector number. + * @retval RTEMS_RESOURCE_IN_USE Handler table is read-only and handler does + * not match. + */ +rtems_status_code ppc_exc_set_handler(unsigned vector, ppc_exc_handler_t hdl); + +/** + * @brief Returns the currently active high-level exception handler. + */ +ppc_exc_handler_t ppc_exc_get_handler(unsigned vector); + +/** + * @brief Function for DAR access. + * + * CPU support may store the address of a function here + * that can be used by the default exception handler to + * obtain fault-address info which is helpful. Unfortunately, + * the SPR holding this information is not uniform + * across PPC families so we need assistance from + * CPU support + */ +extern uint32_t (*ppc_exc_get_DAR)(void); + +void +ppc_exc_wrapup(BSP_Exception_frame *f); + +/** + * @brief Standard aligment handler. + * + * @retval 0 Performed a dcbz instruction. + * @retval -1 Otherwise. + */ +int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum); + +/** @} */ + +/* + * Compatibility with pc386 + */ +typedef exception_handler_t cpuExcHandlerType; + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* LIBCPU_VECTORS_H */ diff --git a/bsps/powerpc/include/bsp/vpd.h b/bsps/powerpc/include/bsp/vpd.h new file mode 100644 index 0000000000..23e49ac9f0 --- /dev/null +++ b/bsps/powerpc/include/bsp/vpd.h @@ -0,0 +1,143 @@ +#ifndef PPC_MOTLOAD_VPD_H +#define PPC_MOTLOAD_VPD_H + +/* MotLoad VPD format */ + +/* Till Straumann, 2005; see copyright notice at the end of this file */ + +#ifdef __cplusplus + extern "C" { +#endif + +/* +VPD = "MOTOROLA" , { field } + +field = type_byte, length_byte, { data } +*/ + +/* Known fields so far */ +typedef enum { + ProductIdent = 0x01, /* String */ + AssemblyNumber = 0x02, /* String */ + SerialNumber = 0x03, /* String */ + CpuClockHz = 0x05, /* binary (5bytes), 0x01 byte appended to unsigned int */ + BusClockHz = 0x06, /* binary (5bytes), 0x01 byte appended to unsigned int */ + EthernetAddr = 0x08, /* binary (7bytes), 0x00 byte appended, 2nd has 0x01 appended */ + CpuType = 0x09, /* String */ + EEpromCrc = 0x0a, /* binary (4bytes) */ + FlashConfig = 0x0b, /* binary */ + L2CacheConfig = 0x0e, /* binary */ + VPDRevision = 0x0f, /* binary (4bytes) */ + L3CacheConfig = 0x19, /* binary */ + End = 0xff +} VpdKey; + +typedef struct { + VpdKey key; /* key for the data item to be read into 'buf' */ + char instance; /* instance # (starting with 0) - some keys are present more than one time */ + void *buf; /* pointer to area where the data item is to be stored */ + int buflen; /* available space in the buffer */ + char found; /* set by BSP_vpdRetrieveFields() to the original length as found in the PROM */ +} VpdBufRec, *VpdBuf; + + +#define VPD_END { key:End, } + + +/* Scan the VPD EEPROM for a number of fields + * + * Pass an array of VpdBufRec items. The routine + * fills the 'buf'fers for all keys that are found + * and sets the 'found' field to the original length + * of the data (i.e., as found in the PROM) so that + * the routine could be called again with a larger + * buffer. + * + * NOTE: - the array must be terminated by a VPD_END record! + * - no CRC check is performed. + * - INTERRUPT MANAGEMENT MUST BE FUNCTIONAL + * + * RETURNS: 0 on success, -1 if any read errors were + * encountered or if the "MOTOROLA" header + * was not found. + */ +int +BSP_vpdRetrieveFields(VpdBuf data); + +/* Example: + * Read 2nd ethernet address: + * + * char enet_addr_2[6]; + * + * VpdBufRec enetVpd [] = { + * { key: EthernetAddr, instance: 1, buf: enet_addr_2, buflen: 2}, + * VPD_END + * }; + * + * if ( BSP_vpdRetrieveFields(enetVpd) ) { + * error("ethernet address couldn't be read\n"); + * } else if ( enetVpd[0].found < 6 ) { + * error("2nd ethernet address not found in VPD\n"); + * } else { + * use_it(enet_addr_2); + * } + */ + + +/* Simple wrapper if only one field is needed + * + * RETURNS: original length if key is found, -1 on error or if key is not found + */ +int +BSP_vpdRetrieveKey(VpdKey k, void *buf, int buflen, int instance); + +#ifdef __cplusplus + } +#endif + +/* + * Authorship + * ---------- + * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was + * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'beatnik' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#endif diff --git a/bsps/powerpc/include/ictrl.h b/bsps/powerpc/include/ictrl.h new file mode 100644 index 0000000000..303ece825d --- /dev/null +++ b/bsps/powerpc/include/ictrl.h @@ -0,0 +1,75 @@ +#ifndef _ICTRL_H +#define _ICTRL_H + +/* + * mpc505/509 external interrupt controller management. + * + * FIXME: should be somehow merged into general RTEMS interrupt + * management code. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define _SIU_IRQENABLE ((unsigned long volatile *const)0x8007EFA8) +#define _SIU_IRQPEND ((unsigned long volatile *const)0x8007EFA0) + +/* Interrupt masks. */ +enum { + IMASK_EXT0 = 0x80000000, + IMASK_EXT1 = 0x20000000, + IMASK_EXT2 = 0x08000000, + IMASK_EXT3 = 0x02000000, + IMASK_EXT4 = 0x00800000, + IMASK_EXT5 = 0x00200000, + IMASK_EXT6 = 0x00080000, + IMASK_ALL = IMASK_EXT0 | IMASK_EXT1 | IMASK_EXT2 | IMASK_EXT3 | + IMASK_EXT4 | IMASK_EXT5 | IMASK_EXT6 +}; + +/* Interrupt numbers. */ +typedef enum { + IRQ_EXT0, + IRQ_EXT1, + IRQ_EXT2, + IRQ_EXT3, + IRQ_EXT4, + IRQ_EXT5, + IRQ_EXT6, + NUM_IRQS +} ExtInt; + +/* Type of external interrupt handlers */ +typedef void (*ExtIsrHandler) (void); + +/* Initialization. Must be called once after RTEMS interrupts sybsystem + is initiailized. 'predriver_hook' is one of such places. */ +extern void extIsrInit( void ); + +/* Set interrupt handler 'handler' for external interrupt number + 'interrupt'. */ +extern void extIrqSetHandler(ExtInt interrupt, ExtIsrHandler handler); + +/* Check is external interrupt 'irq' (IMASK_XXXX) is pended. */ +#define extIrqIsSet(irq) \ + (*_SIU_IRQPEND & (irq)) + +/* Enable external interrupt 'irq' (IMASK_XXXX) processing. */ +#define extIrqEnable(irq) \ + (*_SIU_IRQENABLE |= (irq)) + +/* Disable external interrupt 'irq' (IMASK_XXXX) processing. */ +#define extIrqDisable(irq) \ + (*_SIU_IRQENABLE &= ~(irq)) + +/* Check if external interrupt 'irq' (IMASK_XXXX) processing is + enabled. */ +#define extIrqGetEnable \ + (*_SIU_IRQENABLE) + +#ifdef __cplusplus +} +#endif + +#endif /* _ICTRL_H */ diff --git a/bsps/powerpc/include/libcpu/bat.h b/bsps/powerpc/include/libcpu/bat.h new file mode 100644 index 0000000000..2a27e810ee --- /dev/null +++ b/bsps/powerpc/include/libcpu/bat.h @@ -0,0 +1,85 @@ +/* + * bat.h + * + * This file contains declaration of C function to + * Instantiate 60x/7xx ppc Block Address Translation (BAT) registers. + * More detailed information can be found on motorola + * site and more precisely in the following book : + * + * MPC750 + * Risc Microporcessor User's Manual + * Motorola REF : MPC750UM/AD 8/97 + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_BAT_H +#define _LIBCPU_BAT_H + +#include <libcpu/mmu.h> +#include <libcpu/pgtable.h> + +#define IO_PAGE (_PAGE_NO_CACHE | _PAGE_GUARDED | _PAGE_RW) + +#ifndef ASM +/* Take no risks -- the essential parts of this routine run with + * interrupts disabled! + * + * The routine does basic parameter checks: + * - Index must be 0..3 (0..7 on 7455, 7457). + * If an index > 3 is requested the 745x is + * programmed to enable the higher BATs. + * - Size must be a power of two and <= 1<<28 + * (<=1<<31 on 7455, 7457. Also, on these processors + * the special value 0xffffffff is allowed which stands + * for 1<<32). + * If a size > 1<<28 is requested, the 745x is + * programmed to enable the larger block sizes. + * - Bat ranges must not overlap. + * - Physical & virtual addresses must be aligned + * to the size. + * + * RETURNS: zero on success, nonzero on failure. + */ +extern int setdbat(int bat_index, unsigned long virt, unsigned long phys, + unsigned int size, int flags); + +/* Same as setdbat but sets IBAT */ +extern int setibat(int bat_index, unsigned long virt, unsigned long phys, + unsigned int size, int flags); + +/* read DBAT # 'idx' into *pu / *pl. NULL pointers may be passed. + * If pu and pl are NULL, the bat contents are dumped to the console (printk). + * + * RETURNS: upper BAT contents or (-1) if index is invalid + */ +extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl); + +/* Same as getdbat but reads IBAT */ +extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl); + +/* Do not use the asm-routines; they are obsolete; use setdbat() instead */ +extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart); +extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart); +extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart); +extern void asm_setdbat3(unsigned int uperPart, unsigned int lowerPart); +#else + +/* Initialize all bats (upper and lower) to zero. This routine should *only* + * be called during early BSP initialization when no C-ABI is available + * yet. + * This routine clobbers r3 and r4. + * NOTE: on 7450 CPUs all 8 dbat/ibat units are cleared. On 601 CPUs only + * 4 ibats. + */ + .globl CPU_clear_bats_early + .type CPU_clear_bats_early,@function + +#endif + +#endif /* _LIBCPU_BAT_H */ diff --git a/bsps/powerpc/include/libcpu/byteorder.h b/bsps/powerpc/include/libcpu/byteorder.h new file mode 100644 index 0000000000..0654fefb58 --- /dev/null +++ b/bsps/powerpc/include/libcpu/byteorder.h @@ -0,0 +1,54 @@ +/* + * byteorder.h + * + * This file contains inline implementation of function to + * deal with endian conversion. + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_BYTEORDER_H +#define _LIBCPU_BYTEORDER_H + +#ifdef __cplusplus +extern "C" { +#endif + +static inline unsigned ld_le16(volatile uint16_t *addr) +{ + unsigned val; + + __asm__ volatile ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); + return val; +} + +static inline void st_le16(volatile uint16_t *addr, unsigned val) +{ + __asm__ volatile ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); +} + +static inline unsigned ld_le32(volatile uint32_t *addr) +{ + unsigned val; + + __asm__ volatile ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); + return val; +} + +static inline void st_le32(volatile uint32_t *addr, unsigned val) +{ + __asm__ volatile ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBCPU_BYTEORDER_H */ diff --git a/bsps/powerpc/include/libcpu/c_clock.h b/bsps/powerpc/include/libcpu/c_clock.h new file mode 100644 index 0000000000..bd4918fb44 --- /dev/null +++ b/bsps/powerpc/include/libcpu/c_clock.h @@ -0,0 +1,56 @@ +/* + * Clock Tick Device Driver + * + * This routine utilizes the Decrementer Register common to the PPC family. + * + * The tick frequency is directly programmed to the configured number of + * microseconds per tick. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to support the MPC750. + * Modifications Copyright (c) 1999 Eric Valette valette@crf.canon.fr + */ + +#ifndef _LIBCPU_C_CLOCK_H +#define _LIBCPU_C_CLOCK_H + +#include <rtems.h> + +/* + * These functions and variables represent the API exported by the + * CPU to the BSP. + */ + +extern void clockOff (void* unused); +extern void clockOn (void* unused); +extern void clockIsr (void* unused); +/* bookE decrementer is slightly different */ +extern void clockIsrBookE (void *unused); +extern int clockIsOn (void* unused); + +/* + * These functions and variables represent the assumptions of this + * driver on the BSP. + */ + +extern int BSP_disconnect_clock_handler (void); +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +#endif diff --git a/bsps/powerpc/include/libcpu/cpuIdent.h b/bsps/powerpc/include/libcpu/cpuIdent.h new file mode 100755 index 0000000000..e051deba92 --- /dev/null +++ b/bsps/powerpc/include/libcpu/cpuIdent.h @@ -0,0 +1,158 @@ +/* + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> + * Surrey Satellite Technology Limited + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_CPUIDENT_H +#define _LIBCPU_CPUIDENT_H + +#include <stdbool.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ASM +typedef enum +{ + PPC_601 = 0x1, + PPC_5XX = 0x2, + PPC_603 = 0x3, + PPC_604 = 0x4, + PPC_603e = 0x6, + PPC_603ev = 0x7, + PPC_750 = 0x8, + PPC_750_IBM = 0x7000, + PPC_604e = 0x9, + PPC_604r = 0xA, + PPC_7400 = 0xC, + PPC_405 = 0x2001, /* Xilinx Virtex-II Pro or -4 */ + PPC_405EX = 0x1291, /* + 405EXr */ + PPC_405GP = 0x4011, /* + 405CR */ + PPC_405GPr = 0x5091, + PPC_405EZ = 0x4151, + PPC_405EP = 0x5121, + PPC_440 = 0x7ff2, /* Xilinx Virtex-5*/ + PPC_7455 = 0x8001, /* Kate Feng */ + PPC_7457 = 0x8002, + PPC_620 = 0x16, + PPC_860 = 0x50, + PPC_821 = PPC_860, + PPC_823 = PPC_860, + PPC_8260 = 0x81, + PPC_8240 = PPC_8260, + PPC_8245 = 0x8081, + PPC_8540 = 0x8020, + PPC_e500v2 = 0x8021, + PPC_e6500 = 0x8040, + PPC_603le = 0x8082, /* 603le core, in MGT5100 and MPC5200 */ + PPC_e300c1 = 0x8083, /* e300c1 core, in MPC83xx*/ + PPC_e300c2 = 0x8084, /* e300c2 core */ + PPC_e300c3 = 0x8085, /* e300c3 core */ + PPC_e200z0 = 0x8170, + PPC_e200z1 = 0x8140, + PPC_e200z4 = 0x8150, + PPC_e200z6 = 0x8110, + PPC_e200z7 = 0x8160, + PPC_PSIM = 0xfffe, /* GDB PowerPC simulator -- fake version */ + PPC_UNKNOWN = 0xffff +} ppc_cpu_id_t; + +/* Bitfield of for identifying features or groups of cpu flavors. + * DO NOT USE DIRECTLY (as implementation may change) + * only use the 'ppc_is_xxx() / ppc_has_xxx()' macros/inlines + * below. + */ + +typedef struct { + unsigned has_altivec : 1; + unsigned has_fpu : 1; + unsigned has_hw_ptbl_lkup : 1; +#define PPC_BOOKE_405 1 /* almost like booke but with some significant differences */ +#define PPC_BOOKE_STD 2 +#define PPC_BOOKE_E500 3 /* bookE with extensions */ + unsigned is_bookE : 2; + unsigned has_16byte_clne : 1; + unsigned is_60x : 1; + unsigned has_8_bats : 1; + unsigned has_epic : 1; + unsigned has_shadowed_gprs : 1; +} ppc_feature_t; + +extern ppc_feature_t current_ppc_features; +extern ppc_cpu_id_t current_ppc_cpu; + +typedef unsigned short ppc_cpu_revision_t; + +extern ppc_cpu_id_t get_ppc_cpu_type (void); +extern const char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu); +extern ppc_cpu_revision_t get_ppc_cpu_revision (void); +extern ppc_cpu_revision_t current_ppc_revision; + +/* PUBLIC ACCESS ROUTINES */ +#define _PPC_FEAT_DECL(x) \ +static inline unsigned ppc_cpu_##x(void) { \ + if ( PPC_UNKNOWN == current_ppc_cpu ) \ + get_ppc_cpu_type(); \ + return current_ppc_features.x; \ +} + +_PPC_FEAT_DECL(has_altivec) +/* has_fpu not implemented yet */ +_PPC_FEAT_DECL(has_hw_ptbl_lkup) +_PPC_FEAT_DECL(is_bookE) +_PPC_FEAT_DECL(is_60x) +_PPC_FEAT_DECL(has_8_bats) +_PPC_FEAT_DECL(has_epic) +_PPC_FEAT_DECL(has_shadowed_gprs) + +#undef _PPC_FEAT_DECL + +static inline ppc_cpu_id_t ppc_cpu_current(void) +{ + return current_ppc_cpu; +} + +static inline bool ppc_cpu_is_e200(void) +{ + return (ppc_cpu_current() & 0xff80) == 0x8100; +} + +static inline bool ppc_cpu_is_specific_e200(ppc_cpu_id_t id) +{ + return (ppc_cpu_current() & 0xfff0) == id; +} + +static inline bool ppc_cpu_is_e300(void) +{ + return ppc_cpu_current() == PPC_e300c1 + || ppc_cpu_current() == PPC_e300c2 + || ppc_cpu_current() == PPC_e300c3; +} + +static inline bool ppc_cpu_is_e500(void) +{ + return ppc_cpu_current() == PPC_8540 + || ppc_cpu_current() == PPC_e500v2; +} + +static inline bool ppc_cpu_is(ppc_cpu_id_t cpu) +{ + return ppc_cpu_current() == cpu; +} + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/include/libcpu/e500_mmu.h b/bsps/powerpc/include/libcpu/e500_mmu.h new file mode 100644 index 0000000000..84920e0d14 --- /dev/null +++ b/bsps/powerpc/include/libcpu/e500_mmu.h @@ -0,0 +1,230 @@ +#ifndef RTEMS_E500_MMU_DRIVER_H +#define RTEMS_E500_MMU_DRIVER_H + +/* + * Routines to manipulate e500 TLBs; TLB0 (fixed 4k page size) + * is not very useful so we mostly focus on TLB1 (variable page size) + */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <rtems.h> +#include <inttypes.h> +#include <stdio.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Some routines require or return a index 'key'. This + * is simply the TLB entry # ORed with E500_SELTLB_0 + * or E500_SELTLB_1 specifying an entry in TLB0 or TLB1, + * respectively. + */ +typedef int rtems_e500_tlb_idx; +#define E500_SELTLB_0 0x0000 +#define E500_SELTLB_1 0x1000 + +/* Cache the relevant TLB1 entries so that we can + * make sure the user cannot create conflicting + * (overlapping) entries. + * Keep them public for informational purposes. + */ +typedef struct { + struct { + uint32_t va_epn: 20; + uint32_t va_tid: 12; + } va; + uint32_t rpn; + struct { + uint32_t sz: 4; + uint32_t ts: 1; + uint32_t v: 1; + uint32_t perm: 10; + uint32_t wimge: 7; + } att; +} E500_tlb_va_cache_t; + +extern E500_tlb_va_cache_t rtems_e500_tlb_va_cache[16]; + +/* + * Dump (cleartext) content info from cached TLB entries + * to a file (stdout if f==NULL). + */ +void +rtems_e500_dmptlbc(FILE *f); + +/* + * Read a TLB entry from the hardware; if it is a TLB1 entry + * then the current settings are stored in the + * rtems_e500_tlb_va_cache[] structure. + * + * The routine can perform this operation quietly or + * print information to a file. + * + * 'key': TLB entry index ORed with selector bit + * (E500_SELTLB_0 for TLB0, E500_SELTLB_1 for TLB1). + * 'quiet': perform operation silently (no info printed) + * if nonzero. + * 'f': open FILE where to print information. May be + * NULL in which case 'stdout' is used. + * + * RETURNS: + * 0: success; TLB entry is VALID + * +1: success but TLB entry is INVALID + * < 0: error (-1: invalid argument) + */ +int +rtems_e500_prtlb(rtems_e500_tlb_idx key, int quiet, FILE *f); + +/* Initialize cache; verify that TLB0 is unused; + * + * RETURNS: zero on success, nonzero on error (TLB0 + * seems to be in use); in this case the + * driver will refuse to change TLB1 entries + * (other than disabling them). + */ +int +rtems_e500_initlb(void); + +/* + * Write TLB1 entry (can also be used to disable an entry). + * + * The routine checks against the cached data in + * rtems_e500_tlb_va[] to prevent the user from generating + * overlapping entries. + * + * 'idx': TLB 1 entry # to manipulate + * 'ea': Effective address (must be page aligned) + * 'pa': Physical address (must be page aligned) + * 'sz': Page size selector; page size is + * 1024 * 2^(2*sz) bytes. + * 'sz' may also be one of the following: + * - page size in bytes ( >= 1024 ); the selector + * value is then computed by this routine. + * However, 'sz' must be a valid page size + * or -1 will be returned. + * - a value < 0 to invalidate/disable the + * TLB entry. + * 'attr': Page attributes; ORed combination of WIMGE, + * PERMissions, TID and TS. Use ATTR_xxx macros + * + * RETURNS: 0 on success, nonzero on error: + * + * >0: requested mapping would overlap with + * existing mapping in other entry. Return + * value gives conflicting entry + 1; i.e., + * if a value of 4 is returned then the request + * conflicts with existing mapping in entry 3. + * -1: invalid argument + * -3: driver not initialized (or initialization + * failed because TLB0 is in use). + * <0: other error + * + */ +#define E500_TLB_ATTR_WIMGE(x) ((x)&0x7f) /* includes user bits */ +#define E500_TLB_ATTR_WIMGE_GET(x) ((x)&0x7f) +#define E500_TLB_ATTR_TS (1<<7) +#define E500_TLB_ATTR_PERM(x) (((x)&0x3ff)<<8) +#define E500_TLB_ATTR_PERM_GET(x) (((x)>>8)&0x3ff) +#define E500_TLB_ATTR_TID(x) (((x)&0xfff)<<20) +#define E500_TLB_ATTR_TID_GET(x) (((x)>>20)&0xfff) + +int +rtems_e500_wrtlb(int idx, uint32_t ea, uint32_t pa, int sz, uint32_t attr); + +/* + * Check if a ts/tid/ea/sz mapping overlaps + * with an existing entry. + * + * ASSUMPTION: all TLB0 (fixed 4k pages) are invalid and always unused. + * + * NOTE: 'sz' is the 'logarithmic' size selector; the page size + * is 1024*2^(2*sz). + * + * RETURNS: + * >= 0: index of TLB1 entry that already provides a mapping + * which overlaps within the ea range. + * -1: SUCCESS (no conflicting entry found) + * <=-2: ERROR (invalid input) + */ +int +rtems_e500_matchtlb(uint32_t ea, uint32_t tid, int ts, int sz); + +/* Find TLB index that maps 'ea/as' combination + * + * RETURNS: index 'key'; i.e., the index number plus + * a bit (E500_SELTLB_1) which indicates whether + * the mapping was found in TLB0 (4k fixed page + * size) or in TLB1 (variable page size). + * + * On error (no mapping) -1 is returned. + */ +rtems_e500_tlb_idx +rtems_e500_ftlb(uint32_t ea, int as); + +/* Mark TLB entry as invalid ('disabled'). Unlike + * rtems_e500_wrtlb() with a negative size argument + * this routine also can disable TLB0 entries. + * + * 'key': TLB entry index ORed with selector bit + * (E500_SELTLB_0 for TLB0, E500_SELTLB_1 for TLB1). + * + * RETURNS: zero on success, nonzero on error (TLB + * unchanged). + * + * NOTE: If a TLB1 entry is disabled the associated + * entry in rtems_e500_va_cache[] is also + * marked as disabled. + */ +int +rtems_e500_clrtlb(rtems_e500_tlb_idx key); + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/include/libcpu/io.h b/bsps/powerpc/include/libcpu/io.h new file mode 100644 index 0000000000..841df81f47 --- /dev/null +++ b/bsps/powerpc/include/libcpu/io.h @@ -0,0 +1,139 @@ +/* + * io.h + * + * This file contains inline implementation of function to + * deal with IO. + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef _LIBCPU_IO_H +#define _LIBCPU_IO_H + + +#define PREP_ISA_IO_BASE 0x80000000 +#define PREP_ISA_MEM_BASE 0xc0000000 +#define PREP_PCI_DRAM_OFFSET 0x80000000 + +#define CHRP_ISA_IO_BASE 0xfe000000 +#define CHRP_ISA_MEM_BASE 0xfd000000 +#define CHRP_PCI_DRAM_OFFSET 0x00000000 + +/* _IO_BASE, _ISA_MEM_BASE, PCI_DRAM_OFFSET are now defined by bsp.h */ + +#ifndef ASM + +#include <bsp.h> /* for _IO_BASE & friends */ +#include <stdint.h> + +/* NOTE: The use of these macros is DISCOURAGED. + * you should consider e.g. using in_xxx / out_xxx + * with a device specific base address that is + * defined by the BSP. This makes drivers easier + * to port. + */ +#define inb(port) in_8((uint8_t *)((port)+_IO_BASE)) +#define outb(val, port) out_8((uint8_t *)((port)+_IO_BASE), (val)) +#define inw(port) in_le16((uint16_t *)((port)+_IO_BASE)) +#define outw(val, port) out_le16((uint16_t *)((port)+_IO_BASE), (val)) +#define inl(port) in_le32((uint32_t *)((port)+_IO_BASE)) +#define outl(val, port) out_le32((uint32_t *)((port)+_IO_BASE), (val)) + +/* + * Enforce In-order Execution of I/O: + * Acts as a barrier to ensure all previous I/O accesses have + * completed before any further ones are issued. + */ +static inline void eieio(void) +{ + __asm__ __volatile__ ("eieio"); +} + + +/* Enforce in-order execution of data I/O. + * No distinction between read/write on PPC; use eieio for all three. + */ +#define iobarrier_rw() eieio() +#define iobarrier_r() eieio() +#define iobarrier_w() eieio() + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + */ +static inline uint8_t in_8(const volatile uint8_t *addr) +{ + uint8_t ret; + + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_8(volatile uint8_t *addr, uint8_t val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +static inline uint16_t in_le16(const volatile uint16_t *addr) +{ + uint16_t ret; + + __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +static inline uint16_t in_be16(const volatile uint16_t *addr) +{ + uint16_t ret; + + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_le16(volatile uint16_t *addr, uint16_t val) +{ + __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +static inline void out_be16(volatile uint16_t *addr, uint16_t val) +{ + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +static inline uint32_t in_le32(const volatile uint32_t *addr) +{ + uint32_t ret; + + __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +static inline uint32_t in_be32(const volatile uint32_t *addr) +{ + uint32_t ret; + + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_le32(volatile uint32_t *addr, uint32_t val) +{ + __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +static inline void out_be32(volatile uint32_t *addr, uint32_t val) +{ + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +#endif /* ASM */ +#endif /* _LIBCPU_IO_H */ diff --git a/bsps/powerpc/include/libcpu/irq.h b/bsps/powerpc/include/libcpu/irq.h new file mode 100644 index 0000000000..ab06041d24 --- /dev/null +++ b/bsps/powerpc/include/libcpu/irq.h @@ -0,0 +1,199 @@ +/* + * irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_IRQ_H +#define _LIBCPU_IRQ_H + +#include <rtems/irq.h> + +#define CPU_ASM_IRQ_VECTOR_BASE 0x0 + +#ifndef ASM + +extern volatile unsigned int ppc_cached_irq_mask; + +/* + * Symblolic IRQ names and related definitions. + */ + + /* + * Base vector for our USIU IRQ handlers. + */ +#define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE) + /* + * USIU IRQ handler related definitions + */ +#define CPU_USIU_IRQ_COUNT (16) /* 16 reserved but in the future... */ +#define CPU_USIU_IRQ_MIN_OFFSET (0) +#define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1) + /* + * UIMB IRQ handlers related definitions + */ +#define CPU_UIMB_IRQ_COUNT (32 - 8) /* first 8 overlap USIU */ +#define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE) +#define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1) + /* + * PowerPc exceptions handled as interrupt where a rtems managed interrupt + * handler might be connected + */ +#define CPU_PROC_IRQ_COUNT (1) +#define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1) +#define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1) + /* + * Summary + */ +#define CPU_IRQ_COUNT (CPU_PROC_IRQ_MAX_OFFSET + 1) +#define CPU_MIN_OFFSET (CPU_USIU_IRQ_MIN_OFFSET) +#define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET) + /* + * USIU IRQ symbolic name definitions. + */ +#define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0) +#define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1) + +#define CPU_USIU_EXT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 2) +#define CPU_USIU_INT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 3) + +#define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4) +#define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5) + +#define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6) +#define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7) + +#define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8) +#define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9) + +#define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10) +#define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11) + +#define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12) +#define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13) + +#define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14) +#define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15) + + /* + * Symbolic names for UISU interrupt sources. + */ +#define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6) +#define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7) + + /* + * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to + * the USIU interrupts of the same number, because they are detected in + * the USIU pending register rather than the UIMB pending register. + */ +#define CPU_UIMB_IRQ_0 (CPU_USIU_INT_IRQ_0) +#define CPU_UIMB_IRQ_1 (CPU_USIU_INT_IRQ_1) +#define CPU_UIMB_IRQ_2 (CPU_USIU_INT_IRQ_2) +#define CPU_UIMB_IRQ_3 (CPU_USIU_INT_IRQ_3) +#define CPU_UIMB_IRQ_4 (CPU_USIU_INT_IRQ_4) +#define CPU_UIMB_IRQ_5 (CPU_USIU_INT_IRQ_5) +#define CPU_UIMB_IRQ_6 (CPU_USIU_INT_IRQ_6) +#define CPU_UIMB_IRQ_7 (CPU_USIU_INT_IRQ_7) + +#define CPU_UIMB_IRQ_8 (CPU_UIMB_IRQ_MIN_OFFSET+ 0) +#define CPU_UIMB_IRQ_9 (CPU_UIMB_IRQ_MIN_OFFSET+ 1) +#define CPU_UIMB_IRQ_10 (CPU_UIMB_IRQ_MIN_OFFSET+ 2) +#define CPU_UIMB_IRQ_11 (CPU_UIMB_IRQ_MIN_OFFSET+ 3) +#define CPU_UIMB_IRQ_12 (CPU_UIMB_IRQ_MIN_OFFSET+ 4) +#define CPU_UIMB_IRQ_13 (CPU_UIMB_IRQ_MIN_OFFSET+ 5) +#define CPU_UIMB_IRQ_14 (CPU_UIMB_IRQ_MIN_OFFSET+ 6) +#define CPU_UIMB_IRQ_15 (CPU_UIMB_IRQ_MIN_OFFSET+ 7) +#define CPU_UIMB_IRQ_16 (CPU_UIMB_IRQ_MIN_OFFSET+ 8) +#define CPU_UIMB_IRQ_17 (CPU_UIMB_IRQ_MIN_OFFSET+ 9) +#define CPU_UIMB_IRQ_18 (CPU_UIMB_IRQ_MIN_OFFSET+ 0) +#define CPU_UIMB_IRQ_19 (CPU_UIMB_IRQ_MIN_OFFSET+11) +#define CPU_UIMB_IRQ_20 (CPU_UIMB_IRQ_MIN_OFFSET+12) +#define CPU_UIMB_IRQ_21 (CPU_UIMB_IRQ_MIN_OFFSET+13) +#define CPU_UIMB_IRQ_22 (CPU_UIMB_IRQ_MIN_OFFSET+14) +#define CPU_UIMB_IRQ_23 (CPU_UIMB_IRQ_MIN_OFFSET+15) +#define CPU_UIMB_IRQ_24 (CPU_UIMB_IRQ_MIN_OFFSET+16) +#define CPU_UIMB_IRQ_25 (CPU_UIMB_IRQ_MIN_OFFSET+17) +#define CPU_UIMB_IRQ_26 (CPU_UIMB_IRQ_MIN_OFFSET+18) +#define CPU_UIMB_IRQ_27 (CPU_UIMB_IRQ_MIN_OFFSET+19) +#define CPU_UIMB_IRQ_28 (CPU_UIMB_IRQ_MIN_OFFSET+20) +#define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21) +#define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22) +#define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23) + + /* + * Symbolic names for UIMB interrupt sources. + */ +#define CPU_IRQ_SCI (CPU_UIMB_IRQ_5) + + /* + * Processor exceptions handled as rtems IRQ symbolic name definitions. + */ +#define CPU_DECREMENTER (CPU_PROC_IRQ_MIN_OFFSET) + +/* + * Convert an rtems_irq_number constant to an interrupt level + * suitable for programming into an I/O device's interrupt level field. + */ +int CPU_irq_level_from_symbolic_name(const rtems_irq_number name); + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ + +extern void CPU_rtems_irq_mng_init(unsigned cpuId); + +typedef struct MPC5XX_Interrupt_frame { + uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ + uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ + + /* This is what is left out of the primary contexts */ + uint32_t gpr0; + uint32_t gpr2; /* play safe */ + uint32_t gpr3; + uint32_t gpr4; + uint32_t gpr5; + uint32_t gpr6; + uint32_t gpr7; + uint32_t gpr8; + uint32_t gpr9; + uint32_t gpr10; + uint32_t gpr11; + uint32_t gpr12; + uint32_t gpr13; /* Play safe */ + uint32_t gpr28; /* For internal use by the IRQ handler */ + uint32_t gpr29; /* For internal use by the IRQ handler */ + uint32_t gpr30; /* For internal use by the IRQ handler */ + uint32_t gpr31; /* For internal use by the IRQ handler */ + uint32_t cr; /* Bits of this are volatile, so no-one may save */ + uint32_t ctr; + uint32_t xer; + uint32_t lr; + uint32_t pc; + uint32_t msr; + uint32_t pad[3]; +} MPC5XX_Interrupt_frame; + +void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum); + +#endif + +#endif diff --git a/bsps/powerpc/include/libcpu/mmu.h b/bsps/powerpc/include/libcpu/mmu.h new file mode 100644 index 0000000000..d3081316eb --- /dev/null +++ b/bsps/powerpc/include/libcpu/mmu.h @@ -0,0 +1,304 @@ +/* + * mmu.h + * + * PowerPC memory management structures + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_MMU_H +#define _LIBCPU_MMU_H + +#ifndef ASM +/* Hardware Page Table Entry */ +typedef struct _PTE { + unsigned long v:1; /* Entry is valid */ + unsigned long vsid:24; /* Virtual segment identifier */ + unsigned long h:1; /* Hash algorithm indicator */ + unsigned long api:6; /* Abbreviated page index */ + unsigned long rpn:20; /* Real (physical) page number */ + unsigned long :3; /* Unused */ + unsigned long r:1; /* Referenced */ + unsigned long c:1; /* Changed */ + unsigned long w:1; /* Write-thru cache mode */ + unsigned long i:1; /* Cache inhibited */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page protection */ +} PTE; + +/* Values for PP (assumes Ks=0, Kp=1) */ +#define PP_RWXX 0 /* Supervisor read/write, User none */ +#define PP_RWRX 1 /* Supervisor read/write, User read */ +#define PP_RWRW 2 /* Supervisor read/write, User read/write */ +#define PP_RXRX 3 /* Supervisor read, User read */ + +/* Segment Register */ +typedef struct _SEGREG { + unsigned long t:1; /* Normal or I/O type */ + unsigned long ks:1; /* Supervisor 'key' (normally 0) */ + unsigned long kp:1; /* User 'key' (normally 1) */ + unsigned long n:1; /* No-execute */ + unsigned long :4; /* Unused */ + unsigned long vsid:24; /* Virtual Segment Identifier */ +} SEGREG; + +/* Block Address Translation (BAT) Registers */ +typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ + unsigned long bepi:15; /* Effective page index (virtual address) */ + unsigned long :8; /* unused */ + unsigned long w:1; + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long ks:1; /* Supervisor key (normally 0) */ + unsigned long kp:1; /* User key (normally 1) */ + unsigned long pp:2; /* Page access protections */ +} P601_BATU; + +typedef struct _BATU { /* Upper part of BAT (all except 601) */ + unsigned long bepi:15; /* Effective page index (virtual address) */ + unsigned long :4; /* Unused */ + unsigned long bl:11; /* Block size mask */ + unsigned long vs:1; /* Supervisor valid */ + unsigned long vp:1; /* User valid */ +} BATU; + +typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ + unsigned long brpn:15; /* Real page index (physical address) */ + unsigned long :10; /* Unused */ + unsigned long v:1; /* Valid bit */ + unsigned long bl:6; /* Block size mask */ +} P601_BATL; + +typedef struct _BATL { /* Lower part of BAT (all except 601) */ + unsigned long brpn:15; /* Real page index (physical address) */ + unsigned long :10; /* Unused */ + unsigned long w:1; /* Write-thru cache */ + unsigned long i:1; /* Cache inhibit */ + unsigned long m:1; /* Memory coherence */ + unsigned long g:1; /* Guarded (MBZ in IBAT) */ + unsigned long :1; /* Unused */ + unsigned long pp:2; /* Page access protections */ +} BATL; + +typedef struct _BAT { + BATU batu; /* Upper register */ + BATL batl; /* Lower register */ +} BAT; + +typedef struct _P601_BAT { + P601_BATU batu; /* Upper register */ + P601_BATL batl; /* Lower register */ +} P601_BAT; + +/* Block size masks */ +#define BL_128K 0x000 +#define BL_256K 0x001 +#define BL_512K 0x003 +#define BL_1M 0x007 +#define BL_2M 0x00F +#define BL_4M 0x01F +#define BL_8M 0x03F +#define BL_16M 0x07F +#define BL_32M 0x0FF +#define BL_64M 0x1FF +#define BL_128M 0x3FF +#define BL_256M 0x7FF + +/* BAT Access Protection */ +#define BPP_XX 0x00 /* No access */ +#define BPP_RX 0x01 /* Read only */ +#define BPP_RW 0x02 /* Read/write */ + +/* + * Simulated two-level MMU. This structure is used by the kernel + * to keep track of MMU mappings and is used to update/maintain + * the hardware HASH table which is really a cache of mappings. + * + * The simulated structures mimic the hardware available on other + * platforms, notably the 80x86 and 680x0. + */ + +typedef struct _pte { + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ +} pte; + +#define PD_SHIFT (10+12) /* Page directory */ +#define PD_MASK 0x03FF +#define PT_SHIFT (12) /* Page Table */ +#define PT_MASK 0x03FF +#define PG_SHIFT (12) /* Page Entry */ + + +/* MMU context */ + +typedef struct _MMU_context { + SEGREG segs[16]; /* Segment registers */ + pte **pmap; /* Two-level page-map structure */ +} MMU_context; + +/* Used to set up SDR1 register */ +#define HASH_TABLE_SIZE_64K 0x00010000 +#define HASH_TABLE_SIZE_128K 0x00020000 +#define HASH_TABLE_SIZE_256K 0x00040000 +#define HASH_TABLE_SIZE_512K 0x00080000 +#define HASH_TABLE_SIZE_1M 0x00100000 +#define HASH_TABLE_SIZE_2M 0x00200000 +#define HASH_TABLE_SIZE_4M 0x00400000 +#define HASH_TABLE_MASK_64K 0x000 +#define HASH_TABLE_MASK_128K 0x001 +#define HASH_TABLE_MASK_256K 0x003 +#define HASH_TABLE_MASK_512K 0x007 +#define HASH_TABLE_MASK_1M 0x00F +#define HASH_TABLE_MASK_2M 0x01F +#define HASH_TABLE_MASK_4M 0x03F + +/* invalidate a TLB entry */ +static inline void _tlbie(unsigned long va) +{ + asm volatile ("tlbie %0" : : "r"(va)); +} + +extern void _tlbia(void); /* invalidate all TLB entries */ +#endif /* ASM */ + +/* Control/status registers for the MPC8xx. + * A write operation to these registers causes serialized access. + * During software tablewalk, the registers used perform mask/shift-add + * operations when written/read. A TLB entry is created when the Mx_RPN + * is written, and the contents of several registers are used to + * create the entry. + */ +#define MI_CTR 784 /* Instruction TLB control register */ +#define MI_GPM 0x80000000 /* Set domain manager mode */ +#define MI_PPM 0x40000000 /* Set subpage protection */ +#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MI_RESETVAL 0x00000000 /* Value of register at reset */ + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MI_AP 786 +#define MI_Ks 0x80000000 /* Should not be set */ +#define MI_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MI_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MI_EPN 787 +#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MI_EVALID 0x00000200 /* Entry is valid */ +#define MI_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the instruction TLB, it contains bits that get loaded into the + * TLB entry when the MI_RPN is written. + */ +#define MI_TWC 789 +#define MI_APG 0x000001e0 /* Access protection group (0) */ +#define MI_GUARDED 0x00000010 /* Guarded storage */ +#define MI_PSMASK 0x0000000c /* Mask of page size bits */ +#define MI_PS8MEG 0x0000000c /* 8M page size */ +#define MI_PS512K 0x00000004 /* 512K page size */ +#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MI_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the instruction TLB, using + * additional information from the MI_EPN, and MI_TWC registers. + */ +#define MI_RPN 790 + +/* Define an RPN value for mapping kernel memory to large virtual + * pages for boot initialization. This has real page number of 0, + * large page size, shared page, cache enabled, and valid. + * Also mark all subpages valid and write access. + */ +#define MI_BOOTINIT 0x000001fd + +#define MD_CTR 792 /* Data TLB control register */ +#define MD_GPM 0x80000000 /* Set domain manager mode */ +#define MD_PPM 0x40000000 /* Set subpage protection */ +#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ +#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ +#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ +#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ +#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ +#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ +#define MD_RESETVAL 0x04000000 /* Value of register at reset */ + +#define M_CASID 793 /* Address space ID (context) to match */ +#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ + + +/* These are the Ks and Kp from the PowerPC books. For proper operation, + * Ks = 0, Kp = 1. + */ +#define MD_AP 794 +#define MD_Ks 0x80000000 /* Should not be set */ +#define MD_Kp 0x40000000 /* Should always be set */ + +/* The effective page number register. When read, contains the information + * about the last instruction TLB miss. When MD_RPN is written, bits in + * this register are used to create the TLB entry. + */ +#define MD_EPN 795 +#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ +#define MD_EVALID 0x00000200 /* Entry is valid */ +#define MD_ASIDMASK 0x0000000f /* ASID match value */ + /* Reset value is undefined */ + +/* The pointer to the base address of the first level page table. + * During a software tablewalk, reading this register provides the address + * of the entry associated with MD_EPN. + */ +#define M_TWB 796 +#define M_L1TB 0xfffff000 /* Level 1 table base address */ +#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ + /* Reset value is undefined */ + +/* A "level 1" or "segment" or whatever you want to call it register. + * For the data TLB, it contains bits that get loaded into the TLB entry + * when the MD_RPN is written. It is also provides the hardware assist + * for finding the PTE address during software tablewalk. + */ +#define MD_TWC 797 +#define MD_L2TB 0xfffff000 /* Level 2 table base address */ +#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ +#define MD_APG 0x000001e0 /* Access protection group (0) */ +#define MD_GUARDED 0x00000010 /* Guarded storage */ +#define MD_PSMASK 0x0000000c /* Mask of page size bits */ +#define MD_PS8MEG 0x0000000c /* 8M page size */ +#define MD_PS512K 0x00000004 /* 512K page size */ +#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ +#define MD_WT 0x00000002 /* Use writethrough page attribute */ +#define MD_SVALID 0x00000001 /* Segment entry is valid */ + /* Reset value is undefined */ + + +/* Real page number. Defined by the pte. Writing this register + * causes a TLB entry to be created for the data TLB, using + * additional information from the MD_EPN, and MD_TWC registers. + */ +#define MD_RPN 798 + +/* This is a temporary storage register that could be used to save + * a processor working register during a tablewalk. + */ +#define M_TW 799 +#endif /* _LIBCPU_MMU_H */ diff --git a/bsps/powerpc/include/libcpu/page.h b/bsps/powerpc/include/libcpu/page.h new file mode 100644 index 0000000000..3efbdef5bc --- /dev/null +++ b/bsps/powerpc/include/libcpu/page.h @@ -0,0 +1,66 @@ +/* + * page.h + * + * PowerPC memory management structures + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_PAGE_H +#define _LIBCPU_PAGE_H + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#define PAGE_OFFSET 0xc0000000 + + +#ifndef ASM +/* + * .. while these make it easier on the compiler + */ +typedef unsigned long pte_t; +typedef unsigned long pmd_t; +typedef unsigned long pgd_t; +typedef unsigned long pgprot_t; + +#define pte_val(x) (x) +#define pmd_val(x) (x) +#define pgd_val(x) (x) +#define pgprot_val(x) (x) + +#define __pte(x) (x) +#define __pmd(x) (x) +#define __pgd(x) (x) +#define __pgprot(x) (x) + + +/* align addr on a size boundry - adjust address up if needed -- Cort */ +#define _ALIGN(addr,size) (((addr)+size-1)&(~(size-1))) + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) + + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) +/* map phys->virtual and virtual->phys for RAM pages */ + +#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET) +#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET)) + +#define MAP_NR(addr) (((unsigned long)addr-PAGE_OFFSET) >> PAGE_SHIFT) +#define MAP_PAGE_RESERVED (1<<15) + +extern unsigned long get_zero_page_fast(void); +#endif /* ASM */ +#endif /* _LIBCPU_PAGE_H */ diff --git a/bsps/powerpc/include/libcpu/pgtable.h b/bsps/powerpc/include/libcpu/pgtable.h new file mode 100644 index 0000000000..5be5874b4f --- /dev/null +++ b/bsps/powerpc/include/libcpu/pgtable.h @@ -0,0 +1,144 @@ +/* + * pgtable.h + * + * PowerPC memory management structures + * + * It is a stripped down version of linux ppc file... + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_PGTABLE_H +#define _LIBCPU_PGTABLE_H + +/* + * The PowerPC MMU uses a hash table containing PTEs, together with + * a set of 16 segment registers (on 32-bit implementations), to define + * the virtual to physical address mapping. + * + * We use the hash table as an extended TLB, i.e. a cache of currently + * active mappings. We maintain a two-level page table tree, much like + * that used by the i386, for the sake of the Linux memory management code. + * Low-level assembler code in head.S (procedure hash_page) is responsible + * for extracting ptes from the tree and putting them into the hash table + * when necessary, and updating the accessed and modified bits in the + * page table tree. + * + * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. + * We also use the two level tables, but we can put the real bits in them + * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, + * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has + * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit + * based upon user/super access. The TLB does not have accessed nor write + * protect. We assume that if the TLB get loaded with an entry it is + * accessed, and overload the changed bit for write protect. We use + * two bits in the software pte that are supposed to be set to zero in + * the TLB entry (24 and 25) for these indicators. Although the level 1 + * descriptor contains the guarded and writethrough/copyback bits, we can + * set these at the page level since they get copied from the Mx_TWC + * register when the TLB entry is loaded. We will use bit 27 for guard, since + * that is where it exists in the MD_TWC, and bit 26 for writethrough. + * These will get masked from the level 2 descriptor at TLB load time, and + * copied to the MD_TWC before it gets loaded. + */ + +/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */ +#define PMD_SHIFT 22 +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) + +/* PGDIR_SHIFT determines what a third-level page table entry can map */ +#define PGDIR_SHIFT 22 +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +/* + * entries per page directory level: our page-table tree is two-level, so + * we don't really have any PMD directory. + */ +#define PTRS_PER_PTE 1024 +#define PTRS_PER_PMD 1 +#define PTRS_PER_PGD 1024 +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) + +/* Just any arbitrary offset to the start of the vmalloc VM area: the + * current 64MB value just means that there will be a 64MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + * + * We no longer map larger than phys RAM with the BATs so we don't have + * to worry about the VMALLOC_OFFSET causing problems. We do have to worry + * about clashes between our early calls to ioremap() that start growing down + * from ioremap_base being run into the VM area allocations (growing upwards + * from VMALLOC_START). For this reason we have ioremap_bot to check when + * we actually run into our mappings setup in the early boot with the VM + * system. This really does become a problem for machines with good amounts + * of RAM. -- Cort + */ +#define VMALLOC_OFFSET (0x4000000) /* 64M */ +#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END ioremap_bot + +/* + * Bits in a linux-style PTE. These match the bits in the + * (hardware-defined) PowerPC PTE as closely as possible. + */ +#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ +#define _PAGE_USER 0x002 /* matches one of the PP bits */ +#define _PAGE_RW 0x004 /* software: user write access allowed */ +#define _PAGE_GUARDED 0x008 +#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ +#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ +#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ +#define _PAGE_DIRTY 0x080 /* C: page changed */ +#define _PAGE_ACCESSED 0x100 /* R: page referenced */ +#define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */ +#define _PAGE_SHARED 0 + +#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) + +#define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED +#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE + +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) + +#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \ + _PAGE_SHARED) +#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) +#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) +#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED) +#define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \ + _PAGE_NO_CACHE ) + +/* + * The PowerPC can only do execute protection on a segment (256MB) basis, + * not on a page basis. So we consider execute permission the same as read. + * Also, write permissions imply read permissions. + * This is the closest we can get.. + */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED +#endif /* _LIBCPU_PGTABLE_H */ diff --git a/bsps/powerpc/include/libcpu/powerpc-utility.h b/bsps/powerpc/include/libcpu/powerpc-utility.h new file mode 100644 index 0000000000..4d6af38485 --- /dev/null +++ b/bsps/powerpc/include/libcpu/powerpc-utility.h @@ -0,0 +1,985 @@ +/** + * @file + * + * @ingroup powerpc_shared + * + * @brief General purpose assembler macros, linker command file support and + * some inline functions for direct register access. + */ + +/* + * Copyright (c) 2008-2015 embedded brains GmbH. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * access function for Device Control Registers inspired by "ppc405common.h" + * from Michael Hamel ADInstruments May 2008 + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup powerpc_shared Shared PowerPC Code + */ + +#ifndef __LIBCPU_POWERPC_UTILITY_H +#define __LIBCPU_POWERPC_UTILITY_H + +#if !defined(ASM) + #include <rtems.h> +#endif + +#include <rtems/score/cpu.h> +#include <rtems/powerpc/registers.h> +#include <rtems/powerpc/powerpc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(ASM) + +#include <rtems/bspIo.h> +#include <rtems/system.h> + +#include <libcpu/cpuIdent.h> + +#define LINKER_SYMBOL(sym) extern char sym []; + +/** + * @brief Read one byte from @a src. + */ +static inline uint8_t ppc_read_byte(const volatile void *src) +{ + uint8_t value; + + __asm__ volatile ( + "lbz %0, 0(%1)" + : "=r" (value) + : "b" (src) + ); + + return value; +} + +/** + * @brief Read one half word from @a src. + */ +static inline uint16_t ppc_read_half_word(const volatile void *src) +{ + uint16_t value; + + __asm__ volatile ( + "lhz %0, 0(%1)" + : "=r" (value) + : "b" (src) + ); + + return value; +} + +/** + * @brief Read one word from @a src. + */ +static inline uint32_t ppc_read_word(const volatile void *src) +{ + uint32_t value; + + __asm__ volatile ( + "lwz %0, 0(%1)" + : "=r" (value) + : "b" (src) + ); + + return value; +} + +/** + * @brief Write one byte @a value to @a dest. + */ +static inline void ppc_write_byte(uint8_t value, volatile void *dest) +{ + __asm__ volatile ( + "stb %0, 0(%1)" + : + : "r" (value), "b" (dest) + ); +} + +/** + * @brief Write one half word @a value to @a dest. + */ +static inline void ppc_write_half_word(uint16_t value, volatile void *dest) +{ + __asm__ volatile ( + "sth %0, 0(%1)" + : + : "r" (value), "b" (dest) + ); +} + +/** + * @brief Write one word @a value to @a dest. + */ +static inline void ppc_write_word(uint32_t value, volatile void *dest) +{ + __asm__ volatile ( + "stw %0, 0(%1)" : + : "r" (value), "b" (dest) + ); +} + + +static inline void *ppc_stack_pointer(void) +{ + void *sp; + + __asm__ volatile ( + "mr %0, 1" + : "=r" (sp) + ); + + return sp; +} + +static inline void ppc_set_stack_pointer(void *sp) +{ + __asm__ volatile ( + "mr 1, %0" + : + : "r" (sp) + ); +} + +static inline void *ppc_link_register(void) +{ + void *lr; + + __asm__ volatile ( + "mflr %0" + : "=r" (lr) + ); + + return lr; +} + +static inline void ppc_set_link_register(void *lr) +{ + __asm__ volatile ( + "mtlr %0" + : + : "r" (lr) + ); +} + +static inline uint32_t ppc_machine_state_register(void) +{ + uint32_t msr; + + __asm__ volatile ( + "mfmsr %0" + : "=r" (msr) + ); + + return msr; +} + +static inline void ppc_set_machine_state_register(uint32_t msr) +{ + __asm__ volatile ( + "mtmsr %0" + : + : "r" (msr) + ); +} + +static inline void ppc_synchronize_data(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("sync"); +} + +static inline void ppc_light_weight_synchronize(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("lwsync"); +} + +static inline void ppc_synchronize_instructions(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("isync"); +} + +static inline void ppc_enforce_in_order_execution_of_io(void) +{ + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ("eieio"); +} + +static inline void ppc_data_cache_block_flush(void *addr) +{ + __asm__ volatile ( + "dcbf 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_flush_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbf %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_invalidate(void *addr) +{ + __asm__ volatile ( + "dcbi 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_invalidate_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbi %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_data_cache_block_store(const void *addr) +{ + __asm__ volatile ( + "dcbst 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_store_2( + const void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbst %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_touch(const void *addr) +{ + __asm__ volatile ( + "dcbt 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_touch_2( + const void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbt %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_touch_for_store(const void *addr) +{ + __asm__ volatile ( + "dcbtst 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_data_cache_block_touch_for_store_2( + const void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbtst %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +static inline void ppc_data_cache_block_clear_to_zero(void *addr) +{ + __asm__ volatile ( + "dcbz 0, %0" + : + : "r" (addr) + : "memory" + ); +} + +static inline void ppc_data_cache_block_clear_to_zero_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "dcbz %0, %1" + : + : "b" (base), "r" (offset) + : "memory" + ); +} + +static inline void ppc_instruction_cache_block_invalidate(void *addr) +{ + __asm__ volatile ( + "icbi 0, %0" + : + : "r" (addr) + ); +} + +static inline void ppc_instruction_cache_block_invalidate_2( + void *base, + uintptr_t offset +) +{ + __asm__ volatile ( + "icbi %0, %1" + : + : "b" (base), "r" (offset) + ); +} + +/** + * @brief Enables external exceptions. + * + * You can use this function to enable the external exceptions and restore the + * machine state with ppc_external_exceptions_disable() later. + */ +static inline uint32_t ppc_external_exceptions_enable(void) +{ + uint32_t current_msr; + uint32_t new_msr; + + RTEMS_COMPILER_MEMORY_BARRIER(); + + __asm__ volatile ( + "mfmsr %0;" + "ori %1, %0, 0x8000;" + "mtmsr %1" + : "=r" (current_msr), "=r" (new_msr) + ); + + return current_msr; +} + +/** + * @brief Restores machine state. + * + * @see ppc_external_exceptions_enable() + */ +static inline void ppc_external_exceptions_disable(uint32_t msr) +{ + ppc_set_machine_state_register(msr); + + RTEMS_COMPILER_MEMORY_BARRIER(); +} + +static inline uint32_t ppc_count_leading_zeros(uint32_t value) +{ + uint32_t count; + + __asm__ ( + "cntlzw %0, %1;" + : "=r" (count) + : "r" (value) + ); + + return count; +} + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) +/* Wonderful bookE doesn't have mftb/mftbu; they only + * define the TBRU/TBRL SPRs so we use these. Luckily, + * we run in supervisory mode so that should work on + * all CPUs. In user mode we'd have a problem... + * 2007/11/30, T.S. + * + * OTOH, PSIM currently lacks support for reading + * SPRs 268/269. You need GDB patch sim/2376 to avoid + * a crash... + * OTOH, the MPC8xx do not allow to read the timebase registers via mfspr. + * we NEED a mftb to access the time base. + * 2009/10/30 Th. D. + */ +#define CPU_Get_timebase_low( _value ) \ + __asm__ volatile( "mftb %0" : "=r" (_value) ) +#else +#define CPU_Get_timebase_low( _value ) \ + __asm__ volatile( "mfspr %0,268" : "=r" (_value) ) +#endif + +/* Must be provided for rtems_bsp_delay to work */ +extern uint32_t bsp_clicks_per_usec; + +#define rtems_bsp_delay( _microseconds ) \ + do { \ + uint32_t start, ticks, now; \ + CPU_Get_timebase_low( start ) ; \ + ticks = (_microseconds) * bsp_clicks_per_usec; \ + do \ + CPU_Get_timebase_low( now ) ; \ + while (now - start < ticks); \ + } while (0) + +#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ + do { \ + uint32_t start, now; \ + CPU_Get_timebase_low( start ); \ + do \ + CPU_Get_timebase_low( now ); \ + while (now - start < (_cycles)); \ + } while (0) + +/* + * Routines to access the decrementer register + */ + +#define PPC_Set_decrementer( _clicks ) \ + do { \ + __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \ + } while (0) + +#define PPC_Get_decrementer( _clicks ) \ + __asm__ volatile( "mfdec %0" : "=r" (_clicks) ) + +/* + * Routines to access the time base register + */ + +static inline uint64_t PPC_Get_timebase_register( void ) +{ + uint32_t tbr_low; + uint32_t tbr_high; + uint32_t tbr_high_old; + uint64_t tbr; + + do { +#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) +/* See comment above (CPU_Get_timebase_low) */ + __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old)); + __asm__ volatile( "mftb %0" : "=r" (tbr_low)); + __asm__ volatile( "mftbu %0" : "=r" (tbr_high)); +#else + __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); + __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low)); + __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high)); +#endif + } while ( tbr_high_old != tbr_high ); + + tbr = tbr_high; + tbr <<= 32; + tbr |= tbr_low; + return tbr; +} + +static inline void PPC_Set_timebase_register (uint64_t tbr) +{ + uint32_t tbr_low; + uint32_t tbr_high; + + tbr_low = (uint32_t) tbr; + tbr_high = (uint32_t) (tbr >> 32); + __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low)); + __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high)); + +} + +static inline uint32_t ppc_decrementer_register(void) +{ + uint32_t dec; + + PPC_Get_decrementer(dec); + + return dec; +} + +static inline void ppc_set_decrementer_register(uint32_t dec) +{ + PPC_Set_decrementer(dec); +} + +/** + * @brief Preprocessor magic for stringification of @a x. + */ +#define PPC_STRINGOF(x) #x + +/** + * @brief Returns the value of the Special Purpose Register with number @a spr. + * + * @note This macro uses a GNU C extension. + */ +#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \ + ({ \ + uint32_t val; \ + __asm__ volatile (\ + "mfspr %0, " PPC_STRINGOF(spr) \ + : "=r" (val) \ + ); \ + val;\ + } ) + +/** + * @brief Sets the Special Purpose Register with number @a spr to the value in + * @a val. + */ +#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \ + do { \ + __asm__ volatile (\ + "mtspr " PPC_STRINGOF(spr) ", %0" \ + : \ + : "r" (val) \ + ); \ + } while (0) + +/** + * @brief Sets in the Special Purpose Register with number @a spr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ + val |= mybits; \ + PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Sets in the Special Purpose Register with number @a spr all bits + * which are set in @a bits. The previous register value will be masked with + * @a mask. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + uint32_t mymask = mask; \ + _ISR_Local_disable(level); \ + val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ + val &= ~mymask; \ + val |= mybits; \ + PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Clears in the Special Purpose Register with number @a spr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ + val &= ~mybits; \ + PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Returns the value of the Thread Management Register with number @a tmr. + * + * @note This macro uses a GNU C extension. + */ +#define PPC_THREAD_MGMT_REGISTER(tmr) \ + ({ \ + uint32_t val; \ + __asm__ volatile (\ + "mftmr %0, " PPC_STRINGOF(tmr) \ + : "=r" (val) \ + ); \ + val;\ + } ) + +/** + * @brief Sets the Thread Management Register with number @a tmr to the value in + * @a val. + */ +#define PPC_SET_THREAD_MGMT_REGISTER(tmr, val) \ + do { \ + __asm__ volatile (\ + "mttmr " PPC_STRINGOF(tmr) ", %0" \ + : \ + : "r" (val) \ + ); \ + } while (0) + +/** + * @brief Returns the value of the Device Control Register with number @a dcr. + * + * The PowerPC 4XX family has Device Control Registers. + * + * @note This macro uses a GNU C extension. + */ +#define PPC_DEVICE_CONTROL_REGISTER(dcr) \ + ({ \ + uint32_t val; \ + __asm__ volatile (\ + "mfdcr %0, " PPC_STRINGOF(dcr) \ + : "=r" (val) \ + ); \ + val;\ + } ) + +/** + * @brief Sets the Device Control Register with number @a dcr to the value in + * @a val. + * + * The PowerPC 4XX family has Device Control Registers. + */ +#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \ + do { \ + __asm__ volatile (\ + "mtdcr " PPC_STRINGOF(dcr) ", %0" \ + : \ + : "r" (val) \ + ); \ + } while (0) + +/** + * @brief Sets in the Device Control Register with number @a dcr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ + val |= mybits; \ + PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Sets in the Device Control Register with number @a dcr all bits + * which are set in @a bits. The previous register value will be masked with + * @a mask. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + uint32_t mymask = mask; \ + _ISR_Local_disable(level); \ + val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ + val &= ~mymask; \ + val |= mybits; \ + PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +/** + * @brief Clears in the Device Control Register with number @a dcr all bits + * which are set in @a bits. + * + * Interrupts are disabled throughout this operation. + */ +#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ + do { \ + ISR_Level level; \ + uint32_t val; \ + uint32_t mybits = bits; \ + _ISR_Local_disable(level); \ + val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ + val &= ~mybits; \ + PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ + _ISR_Local_enable(level); \ + } while (0) + +static inline uint32_t ppc_time_base(void) +{ + uint32_t val; + + CPU_Get_timebase_low(val); + + return val; +} + +static inline void ppc_set_time_base(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val); +} + +static inline uint32_t ppc_time_base_upper(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(TBRU); +} + +static inline void ppc_set_time_base_upper(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val); +} + +static inline uint64_t ppc_time_base_64(void) +{ + return PPC_Get_timebase_register(); +} + +static inline void ppc_set_time_base_64(uint64_t val) +{ + PPC_Set_timebase_register(val); +} + +static inline uint32_t ppc_alternate_time_base(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL); +} + +static inline uint32_t ppc_alternate_time_base_upper(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU); +} + +static inline uint64_t ppc_alternate_time_base_64(void) +{ + uint32_t atbl; + uint32_t atbu_0; + uint32_t atbu_1; + + do { + atbu_0 = ppc_alternate_time_base_upper(); + atbl = ppc_alternate_time_base(); + atbu_1 = ppc_alternate_time_base_upper(); + } while (atbu_0 != atbu_1); + + return (((uint64_t) atbu_1) << 32) | ((uint64_t) atbl); +} + +static inline uint32_t ppc_processor_id(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR); +} + +static inline void ppc_set_processor_id(uint32_t val) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val); +} + +static inline uint32_t ppc_fsl_system_version(void) +{ + return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR); +} + +static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr) +{ + return (svr >> 28) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_sid(uint32_t svr) +{ + return (svr >> 16) & 0xfff; +} + +static inline uint32_t ppc_fsl_system_version_proc(uint32_t svr) +{ + return (svr >> 12) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_mfg(uint32_t svr) +{ + return (svr >> 8) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_mjrev(uint32_t svr) +{ + return (svr >> 4) & 0xf; +} + +static inline uint32_t ppc_fsl_system_version_mnrev(uint32_t svr) +{ + return (svr >> 0) & 0xf; +} + +void ppc_code_copy(void *dest, const void *src, size_t n); + +/* FIXME: Do not use this function */ +void printBAT(int bat, uint32_t upper, uint32_t lower); + +/* FIXME: Do not use this function */ +void ShowBATS(void); + +#endif /* ifndef ASM */ + +#if defined(ASM) +#include <rtems/asm.h> + +.macro LA reg, addr +#if defined(__powerpc64__) + lis \reg, (\addr)@highest + ori \reg, \reg, (\addr)@higher + rldicr \reg, \reg, 32, 31 + oris \reg, \reg, (\addr)@h + ori \reg, \reg, (\addr)@l +#else + lis \reg, (\addr)@h + ori \reg, \reg, (\addr)@l +#endif +.endm + +.macro LA32 reg, addr + lis \reg, (\addr)@h + ori \reg, \reg, (\addr)@l +.endm + +.macro LWI reg, value + lis \reg, (\value)@h + ori \reg, \reg, (\value)@l +.endm + +.macro LW reg, addr + lis \reg, \addr@ha + lwz \reg, \addr@l(\reg) +.endm + +/* + * Tests the bits in reg1 against the bits set in mask. A match is indicated + * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register + * reg2 is used to load the mask. + */ +.macro TSTBITS reg1, reg2, mask + LWI \reg2, \mask + and \reg1, \reg1, \reg2 + cmplw \reg1, \reg2 +.endm + +.macro SETBITS reg1, reg2, mask + LWI \reg2, \mask + or \reg1, \reg1, \reg2 +.endm + +.macro CLRBITS reg1, reg2, mask + LWI \reg2, \mask + andc \reg1, \reg1, \reg2 +.endm + +.macro GLOBAL_FUNCTION name + .global \name + .type \name, @function +\name: +.endm + +/* + * Obtain interrupt mask + */ +.macro GET_INTERRUPT_MASK mask + lis \mask, _PPC_INTERRUPT_DISABLE_MASK@h + ori \mask, \mask, _PPC_INTERRUPT_DISABLE_MASK@l +.endm + +/* + * Disables all asynchronous exeptions (interrupts) which may cause a context + * switch. + */ +.macro INTERRUPT_DISABLE level, mask + mfmsr \level + GET_INTERRUPT_MASK mask=\mask + andc \mask, \level, \mask + mtmsr \mask +.endm + +/* + * Restore previous machine state. + */ +.macro INTERRUPT_ENABLE level + mtmsr \level +.endm + +.macro SET_SELF_CPU_CONTROL reg_0, reg_1 +#if defined(RTEMS_SMP) + /* Use Book E Processor ID Register (PIR) */ + mfspr \reg_0, 286 + slwi \reg_0, \reg_0, PER_CPU_CONTROL_SIZE_LOG2 +#if defined(__powerpc64__) + LA \reg_1, _Per_CPU_Information + add \reg_0, \reg_0, \reg_1 +#else + addis \reg_0, \reg_0, _Per_CPU_Information@ha + addi \reg_0, \reg_0, _Per_CPU_Information@l +#endif + mtspr PPC_PER_CPU_CONTROL_REGISTER, \reg_0 +#endif +.endm + +.macro GET_SELF_CPU_CONTROL reg +#if defined(RTEMS_SMP) + mfspr \reg, PPC_PER_CPU_CONTROL_REGISTER +#else + lis \reg, _Per_CPU_Information@h + ori \reg, \reg, _Per_CPU_Information@l +#endif +.endm + +#define LINKER_SYMBOL(sym) .extern sym + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LIBCPU_POWERPC_UTILITY_H */ diff --git a/bsps/powerpc/include/libcpu/pte121.h b/bsps/powerpc/include/libcpu/pte121.h new file mode 100644 index 0000000000..a07e063f03 --- /dev/null +++ b/bsps/powerpc/include/libcpu/pte121.h @@ -0,0 +1,265 @@ +#ifndef _LIBCPU_PTE121_H +#define _LIBCPU_PTE121_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 4/2002, 2003, 2004, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/* Rudimentary page/hash table support for Powerpc + * + * A simple, static (i.e. no 'per-process' virtual + * address space etc.) page table providing + * one-to-one effective <-> virtual <-> physical + * address mapping. + * + * PURPOSE: + * 1) allow write-protection of text/read-only data areas + * 2) provide more effective-address space in case + * the BATs are not enough + * 3) allow 'alias' mappings. Such aliases can only use + * the upper bits of the VSID since VSID & 0xf and the + * PI are always mapped 1:1 to the RPN. + * LIMITATIONS: + * - no PTE replacement (makes no sense in a real-time + * environment, anyway) -> the page table just MUST + * be big enough!. + * - only one page table supported. + * - no locking implemented. If multiple threads modify + * the page table, it is the user's responsibility to + * implement exclusive access. + */ + + +/* I don't include mmu.h here because it says it's derived from linux + * and I want to avoid licensing problems + */ + +/* Abstract handle for a page table */ +typedef struct Triv121PgTblRec_ *Triv121PgTbl; + +/* A PTE entry */ +typedef struct PTERec_ { + volatile unsigned long v:1, vsid:24, h:1, api: 6; + volatile unsigned long rpn:20, pad: 3, r:1, c:1, wimg:4, marked:1, pp:2; +} PTERec, *APte; + +/* Initialize a trivial page table + * using 2^ldSize bytes of memory starting at + * 'base'. + * + * RETURNS: a handle to the internal data structure + * used to manage the page table. NULL on + * error. + * + * NOTES: - 'base' must be aligned to the size + * - minimal ldSize is 16 (== 64k) + * - this routine maps the page table itself + * with read-only access. While this prevents + * the CPU from overwriting the page table, + * it can still be corrupted by PCI bus masters + * (like DMA engines, [VME] bridges etc.) and + * even by this CPU if either the MMU is off + * or if there is a DBAT mapping granting write + * access... + */ +Triv121PgTbl +triv121PgTblInit(unsigned long base, unsigned ldSize); + +/* get the log2 of the minimal page table size needed + * for mapping 'size' bytes. + * + * EXAMPLE: create a page table which maps the entire + * physical memory. The page table itself shall + * be allocated at the top of the available + * memory (assuming 'memsize' is a power of two): + * + * ldSize = triv121PgTblLdMinSize(memsize); + * memsize -= (1<<ldSize); / * reduce memory available to RTEMS * / + * pgTbl = triv121PgTblInit(memsize,ldSize); + * + */ +unsigned long +triv121PgTblLdMinSize(unsigned long size); + +/* Map an address range 1:1 in pgTbl with the given protection; + * + * RETURNS: -1 (TRIV121_MAP_SUCCESS) on success; the page index + * for which no PTE could be allocated, on failure. + * + * NOTES: - This routine returns MINUS ONE ON SUCCESS + * - (parts) of a mapping which overlap with + * already existing PTEs are silently ignored. + * + * Therefore, you can e.g. first create + * a couple of write protected maps and + * finally map the entire memory r/w. This + * will leave the write protected maps + * intact. + */ +long +triv121PgTblMap( + Triv121PgTbl pgTbl, /* handle, returned by Init or Get */ + + long vsid, /* vsid for this mapping (contains topmost 4 bits of EA); + * + * NOTE: it is allowed to pass a VSID < 0 to tell this + * routine it should use a VSID corresponding to a + * 1:1:1 effective - virtual - physical mapping + */ + + unsigned long start, /* segment offset (lowermost 28 bits of EA) of address range + * + * NOTE: if VSID < 0 (TRIV121_121_VSID), 'start' is inter- + * preted as an effective address (EA), i.e. all 32 + * bits are used - the most significant four going into + * to the VSID... + */ + + unsigned long numPages, /* number of pages to map */ + + unsigned wimgAttr, /* 'wimg' attributes + * (Write thru, cache Inhibit, coherent Memory, + * Guarded memory) + */ + + unsigned protection /* 'pp' access protection: Super User + * + * 0 r/w none + * 1 r/w ro + * 2 r/w r/w + * 3 ro ro + */ +); + +#define TRIV121_ATTR_W 8 +#define TRIV121_ATTR_I 4 +#define TRIV121_ATTR_M 2 +#define TRIV121_ATTR_G 1 + +/* for I/O pages (e.g. PCI, VME addresses) use cache inhibited + * and guarded pages. RTM about the 'eieio' instruction! + */ +#define TRIV121_ATTR_IO_PAGE (TRIV121_ATTR_I|TRIV121_ATTR_G) + +#define TRIV121_PP_RO_PAGE (1) /* read-only for key = 1, unlocked by key=0 */ +#define TRIV121_PP_RW_PAGE (2) /* read-write for key = 1/0 */ + +#define TRIV121_121_VSID (-1) /* use 1:1 effective<->virtual address mapping */ +#define TRIV121_SEG_VSID (-2) /* lookup VSID in the segment register */ + +#define TRIV121_MAP_SUCCESS (-1) /* triv121PgTblMap() returns this on SUCCESS */ + +/* get a handle to the one and only page table + * (must have been initialized/allocated) + * + * RETURNS: NULL if the page table has not been initialized/allocated. + */ +Triv121PgTbl +triv121PgTblGet(void); + +/* + * compute the SDR1 register value for the page table + */ + +unsigned long +triv121PgTblSDR1(Triv121PgTbl pgTbl); + +/* + * Activate the page table: + * - set up the segment registers for a 1:1 effective <-> virtual address mapping, + * give user and supervisor keys. + * - set up the SDR1 register + * - flush all tlbs + * - 'lock' pgTbl, i.e. prevent all further modifications. + * + * NOTE: This routine does not change any BATs. Since these + * have priority over the page table, the user + * may have to switch overlapping BATs OFF in order + * for the page table mappings to take effect. + */ +void triv121PgTblActivate(Triv121PgTbl pgTbl); + +/* Find the PTE for a EA and print its contents to stdout + * RETURNS: pte for EA or NULL if no entry was found. + */ +APte triv121DumpEa(unsigned long ea); + +/* Find and return a PTE for a vsid/pi combination + * RETURNS: pte or NULL if no entry was found + */ +APte triv121FindPte(unsigned long vsid, unsigned long pi); + +/* + * Unmap an effective address + * + * RETURNS: pte that mapped the ea or NULL if no + * mapping existed. + */ +APte triv121UnmapEa(unsigned long ea); + +/* + * Change the WIMG and PP attributes of the page containing 'ea' + * + * NOTES: The 'wimg' and 'pp' may be <0 to indicate that no + * change is desired. + * + * RETURNS: Pointer to modified PTE or NULL if 'ea' is not mapped. + */ +APte triv121ChangeEaAttributes(unsigned long ea, int wimg, int pp); + +/* Make the whole page table writable + * NOTES: If the page table has not been initialized yet, + * this routine has no effect (i.e., after + * initialization the page table will still be read-only). + */ +void triv121MakePgTblRW(void); + +/* Make the whole page table read-only + */ +void triv121MakePgTblRO(void); + +/* Dump a pte to stdout */ +long triv121DumpPte(APte pte); + +#endif diff --git a/bsps/powerpc/include/libcpu/raw_exception.h b/bsps/powerpc/include/libcpu/raw_exception.h new file mode 100644 index 0000000000..dd0c483b0d --- /dev/null +++ b/bsps/powerpc/include/libcpu/raw_exception.h @@ -0,0 +1,161 @@ +/* + * raw_execption.h + * + * This file contains implementation of C function to + * Instantiate mpc5xx primary exception entries. + * More detailled information can be found on the Motorola + * site and more precisely in the following book: + * + * MPC555/MPC556 User's Manual + * Motorola REF : MPC555UM/D Rev. 3, 2000 October 15 + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libcpu/powerpc/mpc8xx/exceptions/raw_exception.h: + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _LIBCPU_RAW_EXCEPTION_H +#define _LIBCPU_RAW_EXCEPTION_H + +#include <libcpu/vectors.h> + +/* + * Exception Vectors as defined in the MPC555 User's Manual + */ + +#define ASM_RESET_VECTOR 0x01 +#define ASM_MACH_VECTOR 0x02 + +#define ASM_EXT_VECTOR 0x05 +#define ASM_ALIGN_VECTOR 0x06 +#define ASM_PROG_VECTOR 0x07 +#define ASM_FLOAT_VECTOR 0x08 +#define ASM_DEC_VECTOR 0x09 + +#define ASM_SYS_VECTOR 0x0C +#define ASM_TRACE_VECTOR 0x0D +#define ASM_FLOATASSIST_VECTOR 0x0E + +#define ASM_SOFTEMUL_VECTOR 0x10 + +#define ASM_IPROT_VECTOR 0x13 +#define ASM_DPROT_VECTOR 0x14 + +#define ASM_DBREAK_VECTOR 0x1C +#define ASM_IBREAK_VECTOR 0x1D +#define ASM_MEBREAK_VECTOR 0x1E +#define ASM_NMEBREAK_VECTOR 0x1F + +#define LAST_VALID_EXC ASM_NMEBREAK_VECTOR + +#ifndef ASM + +/* + * Type definition for raw exceptions. + */ + +typedef unsigned char rtems_vector; +struct __rtems_raw_except_connect_data__; +typedef unsigned char rtems_raw_except_hdl_size; + +typedef struct { + rtems_vector vector; + rtems_exception_handler_t* raw_hdl; +}rtems_raw_except_hdl; + +typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); +typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); +typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); + +typedef struct __rtems_raw_except_connect_data__{ + /* + * Exception vector (As defined in the manual) + */ + rtems_vector exceptIndex; + /* + * Exception raw handler. See comment on handler properties below in function prototype. + */ + rtems_raw_except_hdl hdl; + /* + * function for enabling raw exceptions. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage exceptions and thus the + * "on" routine must enable the except at processor level only. + * + */ + rtems_raw_except_enable on; + /* + * function for disabling raw exceptions. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage exceptions and thus the + * "on" routine must disable the except both at device and PIC level. + * + */ + rtems_raw_except_disable off; + /* + * function enabling to know what exception may currently occur + */ + rtems_raw_except_is_enabled isOn; +}rtems_raw_except_connect_data; + +typedef struct { + /* + * size of all the table fields (*Tbl) described below. + */ + unsigned int exceptSize; + /* + * Default handler used when disconnecting exceptions. + */ + rtems_raw_except_connect_data defaultRawEntry; + /* + * Table containing initials/current value. + */ + rtems_raw_except_connect_data* rawExceptHdlTbl; +}rtems_raw_except_global_settings; + +/* + * C callable function enabling to set up one raw idt entry + */ +extern int mpc5xx_set_exception (const rtems_raw_except_connect_data*); + +/* + * C callable function enabling to get one current raw idt entry + */ +extern int mpc5xx_get_current_exception (rtems_raw_except_connect_data*); + +/* + * C callable function enabling to remove one current raw idt entry + */ +extern int mpc5xx_delete_exception (const rtems_raw_except_connect_data*); + +/* + * C callable function enabling to check if vector is valid + */ +extern int mpc5xx_vector_is_valid(rtems_vector vector); + +inline static void* mpc5xx_get_vector_addr(rtems_vector vector) +{ + return ((void*) (((unsigned) vector) << 8)); +} +/* + * Exception global init. + */ +extern int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config); +extern int mpc5xx_get_exception_config (rtems_raw_except_global_settings** config); + +# endif /* ASM */ + +#define SIZEOF_ + +#endif diff --git a/bsps/powerpc/include/libcpu/spr.h b/bsps/powerpc/include/libcpu/spr.h new file mode 100644 index 0000000000..6c81d0ee91 --- /dev/null +++ b/bsps/powerpc/include/libcpu/spr.h @@ -0,0 +1,78 @@ +/* + * spr.h -- Access to special purpose registers. + * + * Copyright (C) 1998 Gabriel Paubert, paubert@iram.es + * + * Modified to compile in RTEMS development environment + * by Eric Valette + * + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + + +#ifndef _LIBCPU_SPR_H +#define _LIBCPU_SPR_H + +#include <rtems/powerpc/registers.h> + +#define __MFSPR(reg, val) \ + __asm__ __volatile__("mfspr %0,"#reg : "=r" (val)) + +#define __MTSPR(val, reg) \ + __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val)) + + +#define SPR_RW(reg) \ +static inline unsigned long _read_##reg(void) \ +{\ + unsigned long val;\ + __MFSPR(reg, val);\ + return val;\ +}\ +static inline void _write_##reg(unsigned long val)\ +{\ + __MTSPR(val,reg);\ + return;\ +} + +#define SPR_RO(reg) \ +static inline unsigned long _read_##reg(void) \ +{\ + unsigned long val;\ + __MFSPR(reg,val);\ + return val;\ +} + +static inline unsigned long _read_MSR(void) +{ + unsigned long val; + asm volatile("mfmsr %0" : "=r" (val)); + return val; +} + +static inline void _write_MSR(unsigned long val) +{ + asm volatile("mtmsr %0" : : "r" (val)); + return; +} + +static inline unsigned long _read_SR(void * va) +{ + unsigned long val; + asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va)); + return val; +} + +static inline void _write_SR(unsigned long val, void * va) +{ + asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory"); + return; +} + + +#endif diff --git a/bsps/powerpc/include/libcpu/stackTrace.h b/bsps/powerpc/include/libcpu/stackTrace.h new file mode 100644 index 0000000000..f73dc2eff2 --- /dev/null +++ b/bsps/powerpc/include/libcpu/stackTrace.h @@ -0,0 +1,8 @@ +#ifndef _LIBCPU_STACKTRACE_H +#define _LIBCPU_STACKTRACE_H + +void CPU_stack_take_snapshot(void **stack, int size, void *pc, void *lr, void *r1); + +void CPU_print_stack(void); + +#endif diff --git a/bsps/powerpc/include/libcpu/vectors.h b/bsps/powerpc/include/libcpu/vectors.h new file mode 100644 index 0000000000..2c8914e2a4 --- /dev/null +++ b/bsps/powerpc/include/libcpu/vectors.h @@ -0,0 +1,115 @@ +/* + * vectors.h Exception frame related contant and API. + * + * This include file describe the data structure and the functions implemented + * by rtems to handle exceptions. + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/vectors/vectors.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef _LIBCPU_VECTORS_H +#define _LIBCPU_VECTORS_H + + +/* + * Size of hardware vector table. + */ +#define NUM_EXCEPTIONS 0x20 + +/* + * The callee (high level exception code written in C) + * will store the Link Registers (return address) at entry r1 + 4 !!!. + * So let room for it!!!. + */ +#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 +#define SRR0_FRAME_OFFSET 8 +#define SRR1_FRAME_OFFSET 12 +#define EXCEPTION_NUMBER_OFFSET 16 +#define EXC_CR_OFFSET 20 +#define EXC_CTR_OFFSET 24 +#define EXC_XER_OFFSET 28 +#define EXC_LR_OFFSET 32 +#define GPR0_OFFSET 36 +#define GPR1_OFFSET 40 +#define GPR2_OFFSET 44 +#define GPR3_OFFSET 48 +#define GPR4_OFFSET 52 +#define GPR5_OFFSET 56 +#define GPR6_OFFSET 60 +#define GPR7_OFFSET 64 +#define GPR8_OFFSET 68 +#define GPR9_OFFSET 72 +#define GPR10_OFFSET 76 +#define GPR11_OFFSET 80 +#define GPR12_OFFSET 84 +#define GPR13_OFFSET 88 +#define GPR14_OFFSET 92 +#define GPR15_OFFSET 96 +#define GPR16_OFFSET 100 +#define GPR17_OFFSET 104 +#define GPR18_OFFSET 108 +#define GPR19_OFFSET 112 +#define GPR20_OFFSET 116 +#define GPR21_OFFSET 120 +#define GPR22_OFFSET 124 +#define GPR23_OFFSET 128 +#define GPR24_OFFSET 132 +#define GPR25_OFFSET 136 +#define GPR26_OFFSET 140 +#define GPR27_OFFSET 144 +#define GPR28_OFFSET 148 +#define GPR29_OFFSET 152 +#define GPR30_OFFSET 156 +#define GPR31_OFFSET 160 +/* + * maintain the EABI requested 8 bytes aligment + * As SVR4 ABI requires 16, make it 16 (as some + * exception may need more registers to be processed...) + */ +#define EXCEPTION_FRAME_END 176 + +#ifndef ASM + +#include <rtems.h> + +/* + * default raw exception handlers + */ + +extern void default_exception_vector_code_prolog(void); +extern int default_exception_vector_code_prolog_size; +extern void initialize_exceptions(void); + +typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr); +/*DEBUG typedef rtems_exception_handler_t cpuExcHandlerType; */ + +/* + * Exception handler table. + * + * This table contains pointers to assembly-language exception handlers. + * The common exception prologue in vectors.S looks up an entry in this + * table and jumps to it. No return address is saved, so the handlers in + * this table must return directly to the interrupted code. + * + * On entry to an exception handler, R1 points to a new exception stack + * frame in which R3, R4, and LR have been saved. R4 holds the exception + * number. + */ +extern rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS]; + +/* for compatability -- XXX remove */ +typedef rtems_exception_handler_t *cpuExcHandlerType; +extern cpuExcHandlerType *globalExceptHdl; + +#endif /* ASM */ + +#endif /* _LIBCPU_VECTORS_H */ diff --git a/bsps/powerpc/include/mpc55xx/dspi.h b/bsps/powerpc/include/mpc55xx/dspi.h new file mode 100644 index 0000000000..8ad98274ef --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/dspi.h @@ -0,0 +1,128 @@ +/** + * @file + * + * @ingroup mpc55xx_dspi + * + * @brief Header file for the LibI2C bus driver for the Deserial Serial Peripheral Interface (DSPI). + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup mpc55xx_dspi Deserial Serial Peripheral Interface (DSPI) + * + * @ingroup mpc55xx + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_DSPI_H +#define LIBCPU_POWERPC_MPC55XX_DSPI_H + +#include <rtems/libi2c.h> + +#include <mpc55xx/edma.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +struct DSPI_tag; + +typedef struct { + edma_channel_context edma; + rtems_id id; +} mpc55xx_dspi_edma_entry; + +/** + * @brief LibI2C bus driver entry. + */ +typedef struct { + /** + * @brief Standard bus driver fields. + */ + rtems_libi2c_bus_t bus; + + /** + * @brief Index in the bus table: @ref mpc55xx_dspi_bus_table. + */ + unsigned table_index; + + /** + * @brief Bus number (available after rtems_libi2c_register_bus()). + * + * @note You must set it in the initialization code after the bus registration. + */ + unsigned bus_number; + + /** + * @brief Hardware registers. + */ + volatile struct DSPI_tag *regs; + + /** + * @brief Selects SPI master or slave mode. + */ + bool master; + + /** + * @brief Data for the Push Register. + */ + union DSPI_PUSHR_tag push_data; + + /** + * @brief eDMA entry for transmission. + * + * The channel is fixed to a particular DSPI. + */ + mpc55xx_dspi_edma_entry edma_transmit; + + /** + * @brief eDMA entry for push data generation. + * + * You can choose every available channel. + */ + mpc55xx_dspi_edma_entry edma_push; + + /** + * @brief eDMA entry for receiving. + * + * The channel is fixed to a particular DSPI. + */ + mpc55xx_dspi_edma_entry edma_receive; + + /** + * @brief Idle character transmitted in read only mode. + */ + uint32_t idle_char; + + /** + * @brief Current baud. + */ + uint32_t baud; +} mpc55xx_dspi_bus_entry; + +/** + * @brief Number of DSPIs. + */ +#define MPC55XX_DSPI_NUMBER 4 + +/** + * @brief Table with bus driver entries. + */ +extern mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [ /* MPC55XX_DSPI_NUMBER */ ]; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_DSPI_H */ diff --git a/bsps/powerpc/include/mpc55xx/edma.h b/bsps/powerpc/include/mpc55xx/edma.h new file mode 100644 index 0000000000..281cdf1c28 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/edma.h @@ -0,0 +1,329 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Enhanced Direct Memory Access (eDMA). + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_EDMA_H +#define LIBCPU_POWERPC_MPC55XX_EDMA_H + +#include <mpc55xx/regs.h> + +#include <rtems.h> +#include <rtems/chain.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#if MPC55XX_CHIP_FAMILY == 551 + #define EDMA_CHANNEL_COUNT 16U +#elif MPC55XX_CHIP_FAMILY == 564 + #define EDMA_CHANNEL_COUNT 16U +#elif MPC55XX_CHIP_FAMILY == 567 + #define EDMA_CHANNEL_COUNT 96U +#else + #define EDMA_CHANNEL_COUNT 64U +#endif + +#define EDMA_MODULE_COUNT ((EDMA_CHANNEL_COUNT + 63U) / 64U) + +#define EDMA_CHANNELS_PER_MODULE 64U + +#if EDMA_MODULE_COUNT == 1 + #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \ + (&EDMA.TCD[(channel_index)]) +#elif EDMA_MODULE_COUNT == 2 + #define EDMA_TCD_BY_CHANNEL_INDEX(channel_index) \ + ((channel_index) < EDMA_CHANNELS_PER_MODULE ? \ + &EDMA_A.TCD[(channel_index)] \ + : &EDMA_B.TCD[(channel_index) - EDMA_CHANNELS_PER_MODULE]) +#else + #error "unsupported module count" +#endif + +/* FIXME: These values are only valid for the MPC5566 and MPC5674F */ +typedef enum { + EDMA_EQADC_A_FISR0_CFFF0 = 0, + EDMA_EQADC_A_FISR0_RFDF0 = 1, + EDMA_EQADC_A_FISR1_CFFF1 = 2, + EDMA_EQADC_A_FISR1_RFDF1 = 3, + EDMA_EQADC_A_FISR2_CFFF2 = 4, + EDMA_EQADC_A_FISR2_RFDF2 = 5, + EDMA_EQADC_A_FISR3_CFFF3 = 6, + EDMA_EQADC_A_FISR3_RFDF3 = 7, + EDMA_EQADC_A_FISR4_CFFF4 = 8, + EDMA_EQADC_A_FISR4_RFDF4 = 9, + EDMA_EQADC_A_FISR5_CFFF5 = 10, + EDMA_EQADC_A_FISR5_RFDF5 = 11, + EDMA_DSPI_B_SR_TFFF = 12, + EDMA_DSPI_B_SR_RFDF = 13, + EDMA_DSPI_C_SR_TFFF = 14, + EDMA_DSPI_C_SR_RFDF = 15, + EDMA_DSPI_D_SR_TFFF = 16, + EDMA_DSPI_D_SR_RFDF = 17, + EDMA_ESCI_A_COMBTX = 18, + EDMA_ESCI_A_COMBRX = 19, + EDMA_EMIOS_GFR_F0 = 20, + EDMA_EMIOS_GFR_F1 = 21, + EDMA_EMIOS_GFR_F2 = 22, + EDMA_EMIOS_GFR_F3 = 23, + EDMA_EMIOS_GFR_F4 = 24, + EDMA_EMIOS_GFR_F8 = 25, + EDMA_EMIOS_GFR_F9 = 26, + EDMA_ETPU_CDTRSR_A_DTRS0 = 27, + EDMA_ETPU_CDTRSR_A_DTRS1 = 28, + EDMA_ETPU_CDTRSR_A_DTRS2 = 29, + EDMA_ETPU_CDTRSR_A_DTRS14 = 30, + EDMA_ETPU_CDTRSR_A_DTRS15 = 31, + EDMA_DSPI_A_SR_TFFF = 32, + EDMA_DSPI_A_SR_RFDF = 33, + EDMA_ESCI_B_COMBTX = 34, + EDMA_ESCI_B_COMBRX = 35, + EDMA_EMIOS_GFR_F6 = 36, + EDMA_EMIOS_GFR_F7 = 37, + EDMA_EMIOS_GFR_F10 = 38, + EDMA_EMIOS_GFR_F11 = 39, + EDMA_EMIOS_GFR_F16 = 40, + EDMA_EMIOS_GFR_F17 = 41, + EDMA_EMIOS_GFR_F18 = 42, + EDMA_EMIOS_GFR_F19 = 43, + EDMA_ETPU_CDTRSR_A_DTRS12 = 44, + EDMA_ETPU_CDTRSR_A_DTRS13 = 45, + EDMA_ETPU_CDTRSR_A_DTRS28 = 46, + EDMA_ETPU_CDTRSR_A_DTRS29 = 47, + EDMA_SIU_EISR_EIF0 = 48, + EDMA_SIU_EISR_EIF1 = 49, + EDMA_SIU_EISR_EIF2 = 50, + EDMA_SIU_EISR_EIF3 = 51, + EDMA_ETPU_CDTRSR_B_DTRS0 = 52, + EDMA_ETPU_CDTRSR_B_DTRS1 = 53, + EDMA_ETPU_CDTRSR_B_DTRS2 = 54, + EDMA_ETPU_CDTRSR_B_DTRS3 = 55, + EDMA_ETPU_CDTRSR_B_DTRS12 = 56, + EDMA_ETPU_CDTRSR_B_DTRS13 = 57, + EDMA_ETPU_CDTRSR_B_DTRS14 = 58, + EDMA_ETPU_CDTRSR_B_DTRS15 = 59, + EDMA_ETPU_CDTRSR_B_DTRS28 = 60, + EDMA_ETPU_CDTRSR_B_DTRS29 = 61, + EDMA_ETPU_CDTRSR_B_DTRS30 = 62, + EDMA_ETPU_CDTRSR_B_DTRS31 = 63 + #if MPC55XX_CHIP_FAMILY == 567 + , + EDMA_EQADC_B_FISR0_CFFF0 = 64 + 0, + EDMA_EQADC_B_FISR0_RFDF0 = 64 + 1, + EDMA_EQADC_B_FISR1_CFFF1 = 64 + 2, + EDMA_EQADC_B_FISR1_RFDF1 = 64 + 3, + EDMA_EQADC_B_FISR2_CFFF2 = 64 + 4, + EDMA_EQADC_B_FISR2_RFDF2 = 64 + 5, + EDMA_EQADC_B_FISR3_CFFF3 = 64 + 6, + EDMA_EQADC_B_FISR3_RFDF3 = 64 + 7, + EDMA_EQADC_B_FISR4_CFFF4 = 64 + 8, + EDMA_EQADC_B_FISR4_RFDF4 = 64 + 9, + EDMA_EQADC_B_FISR5_CFFF5 = 64 + 10, + EDMA_EQADC_B_FISR5_RFDF5 = 64 + 11, + EDMA_DECFILTER_A_IB = 64 + 12, + EDMA_DECFILTER_A_OB = 64 + 13, + EDMA_DECFILTER_B_IB = 64 + 14, + EDMA_DECFILTER_B_OB = 64 + 15, + EDMA_DECFILTER_C_IB = 64 + 16, + EDMA_DECFILTER_C_OB = 64 + 17, + EDMA_DECFILTER_D_IB = 64 + 18, + EDMA_DECFILTER_D_OB = 64 + 19, + EDMA_DECFILTER_E_IB = 64 + 20, + EDMA_DECFILTER_E_OB = 64 + 21, + EDMA_DECFILTER_F_IB = 64 + 22, + EDMA_DECFILTER_F_OB = 64 + 23, + EDMA_DECFILTER_G_IB = 64 + 24, + EDMA_DECFILTER_G_OB = 64 + 25, + EDMA_DECFILTER_H_IB = 64 + 26, + EDMA_DECFILTER_H_OB = 64 + 27 + #endif +} edma_channel; + +typedef struct edma_channel_context { + rtems_chain_node node; + volatile struct tcd_t *edma_tcd; + void (*done)(struct edma_channel_context *, uint32_t); +} edma_channel_context; + +void mpc55xx_edma_init(void); + +/** + * @brief Obtains an eDMA channel. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_RESOURCE_IN_USE The channel is already in use. + */ +rtems_status_code mpc55xx_edma_obtain_channel_by_tcd( + volatile struct tcd_t *edma_tcd +); + +void mpc55xx_edma_release_channel_by_tcd(volatile struct tcd_t *edma_tcd); + +/** + * @brief Obtains an eDMA channel and registers the channel context. + * + * The done handler of the channel context will be called + * - during minor or major loop completions if interrupts are enabled in the + * corresponding TCD, or + * - in case a channel error occurs. + * + * An error status value not equal to zero indicates an error. + * + * @retval RTEMS_SUCCESSFUL Successful operation. + * @retval RTEMS_RESOURCE_IN_USE The channel is already in use. + * @retval RTEMS_IO_ERROR Unable to install interrupt handler for this channel. + */ +rtems_status_code mpc55xx_edma_obtain_channel( + edma_channel_context *ctx, + unsigned irq_priority +); + +void mpc55xx_edma_release_channel(edma_channel_context *ctx); + +/** + * @brief Copies a source TCD to an eDMA TCD. + * + * The DONE flag of the eDMA TCD is cleared before the actual copy operation. + * This enables the setting of channel link or scatter/gather options. + * + * This function can be used to start the channel if the START flags is + * set in the source TCD. + */ +void mpc55xx_edma_copy( + volatile struct tcd_t *edma_tcd, + const struct tcd_t *source_tcd +); + +/** + * @brief Copies a source TCD to an eDMA TCD and enables hardware requests. + * + * The DONE flag of the eDMA TCD is cleared before the actual copy operation. + * This enables the setting of channel link or scatter/gather options. + */ +void mpc55xx_edma_copy_and_enable_hardware_requests( + volatile struct tcd_t *edma_tcd, + const struct tcd_t *source_tcd +); + +void mpc55xx_edma_sg_link( + volatile struct tcd_t *edma_tcd, + const struct tcd_t *source_tcd +); + +static inline volatile struct EDMA_tag *mpc55xx_edma_by_tcd( + volatile struct tcd_t *edma_tcd +) +{ + return (volatile struct EDMA_tag *) + ((uintptr_t) edma_tcd & ~(uintptr_t) 0x1fff); +} + +static inline unsigned mpc55xx_edma_channel_by_tcd( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + + return edma_tcd - &edma->TCD[0]; +} + +static inline void mpc55xx_edma_enable_hardware_requests( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->SERQR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_disable_hardware_requests( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CERQR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_enable_error_interrupts( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->SEEIR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_disable_error_interrupts( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CEEIR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_set_start( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->SSBR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_clear_done( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CDSBR.R = (uint8_t) channel; +} + +static inline void mpc55xx_edma_clear_interrupts( + volatile struct tcd_t *edma_tcd +) +{ + volatile struct EDMA_tag *edma = mpc55xx_edma_by_tcd(edma_tcd); + unsigned channel = edma_tcd - &edma->TCD[0]; + + edma->CIRQR.R = (uint8_t) channel; +} + +static inline bool mpc55xx_edma_is_done( + volatile struct tcd_t *edma_tcd +) +{ + return edma_tcd->BMF.B.DONE; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_EDMA_H */ diff --git a/bsps/powerpc/include/mpc55xx/emios.h b/bsps/powerpc/include/mpc55xx/emios.h new file mode 100644 index 0000000000..d6ccadc07b --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/emios.h @@ -0,0 +1,197 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Enhanced Modular Input Output Subsystem (eMIOS). + */ + +/* + * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_EMIOS_H +#define LIBCPU_POWERPC_MPC55XX_EMIOS_H + +#include <mpc55xx/regs.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef MPC55XX_HAS_EMIOS + +/** + * @name eMIOS - Modes + * + * @{ + */ + +#define MPC55XX_EMIOS_MODE_GPIO_INPUT 0U +#define MPC55XX_EMIOS_MODE_GPIO_OUTPUT 1U +#define MPC55XX_EMIOS_MODE_SAIC 2U +#define MPC55XX_EMIOS_MODE_SAOC 3U +#define MPC55XX_EMIOS_MODE_IPWM 4U +#define MPC55XX_EMIOS_MODE_IPM 5U +#define MPC55XX_EMIOS_MODE_DAOC_SECOND 6U +#define MPC55XX_EMIOS_MODE_DAOC_BOTH 7U +#define MPC55XX_EMIOS_MODE_PEA_ACCU_CONT 8U +#define MPC55XX_EMIOS_MODE_PEA_ACCU_SINGLE 9U +#define MPC55XX_EMIOS_MODE_PEA_COUNT_CONT 10U +#define MPC55XX_EMIOS_MODE_PEA_COUNT_SINGLE 11U +#define MPC55XX_EMIOS_MODE_QDEC_COUNT_DIR 12U +#define MPC55XX_EMIOS_MODE_QDEC_PHASE 13U +#define MPC55XX_EMIOS_MODE_WPTA 14U +#define MPC55XX_EMIOS_MODE_RESERVED_15 15U +#define MPC55XX_EMIOS_MODE_MC_UP_INT_CLK 16U +#define MPC55XX_EMIOS_MODE_MC_UP_EXT_CLK 17U +#define MPC55XX_EMIOS_MODE_RESERVED_18 18U +#define MPC55XX_EMIOS_MODE_RESERVED_19 19U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_INT_CLK 20U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_EXT_CLK 21U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_CHANGE_INT_CLK 22U +#define MPC55XX_EMIOS_MODE_MC_UP_DOWN_CHANGE_EXT_CLK 23U +#define MPC55XX_EMIOS_MODE_OPWFM_B_IMMEDIATE 24U +#define MPC55XX_EMIOS_MODE_OPWFM_B_NEXT_PERIOD 25U +#define MPC55XX_EMIOS_MODE_OPWFM_AB_IMMEDIATE 26U +#define MPC55XX_EMIOS_MODE_OPWFM_AB_NEXT_PERIOD 27U +#define MPC55XX_EMIOS_MODE_OPWMC_TRAIL_TRAIL 28U +#define MPC55XX_EMIOS_MODE_OPWMC_TRAIL_LEAD 29U +#define MPC55XX_EMIOS_MODE_OPWMC_BOTH_TRAIL 30U +#define MPC55XX_EMIOS_MODE_OPWMC_BOTH_LEAD 31U +#define MPC55XX_EMIOS_MODE_OPWM_B_IMMEDIATE 32U +#define MPC55XX_EMIOS_MODE_OPWM_B_NEXT_PERIOD 33U +#define MPC55XX_EMIOS_MODE_OPWM_AB_IMMEDIATE 34U +#define MPC55XX_EMIOS_MODE_OPWM_AB_NEXT_PERIOD 35U +#define MPC55XX_EMIOS_MODE_RESERVED_36 36U +#define MPC55XX_EMIOS_MODE_RESERVED_37 37U +#define MPC55XX_EMIOS_MODE_RESERVED_38 38U +#define MPC55XX_EMIOS_MODE_RESERVED_39 39U +#define MPC55XX_EMIOS_MODE_RESERVED_40 40U +#define MPC55XX_EMIOS_MODE_RESERVED_41 41U +#define MPC55XX_EMIOS_MODE_RESERVED_42 42U +#define MPC55XX_EMIOS_MODE_RESERVED_43 43U +#define MPC55XX_EMIOS_MODE_RESERVED_44 44U +#define MPC55XX_EMIOS_MODE_RESERVED_45 45U +#define MPC55XX_EMIOS_MODE_RESERVED_46 46U +#define MPC55XX_EMIOS_MODE_RESERVED_47 47U +#define MPC55XX_EMIOS_MODE_RESERVED_48 48U +#define MPC55XX_EMIOS_MODE_RESERVED_49 49U +#define MPC55XX_EMIOS_MODE_RESERVED_50 50U +#define MPC55XX_EMIOS_MODE_RESERVED_51 51U +#define MPC55XX_EMIOS_MODE_RESERVED_52 52U +#define MPC55XX_EMIOS_MODE_RESERVED_53 53U +#define MPC55XX_EMIOS_MODE_RESERVED_54 54U +#define MPC55XX_EMIOS_MODE_RESERVED_55 55U +#define MPC55XX_EMIOS_MODE_RESERVED_56 56U +#define MPC55XX_EMIOS_MODE_RESERVED_57 57U +#define MPC55XX_EMIOS_MODE_RESERVED_58 58U +#define MPC55XX_EMIOS_MODE_RESERVED_59 59U +#define MPC55XX_EMIOS_MODE_RESERVED_60 60U +#define MPC55XX_EMIOS_MODE_RESERVED_61 61U +#define MPC55XX_EMIOS_MODE_RESERVED_62 62U +#define MPC55XX_EMIOS_MODE_RESERVED_63 63U +#define MPC55XX_EMIOS_MODE_RESERVED_64 64U +#define MPC55XX_EMIOS_MODE_RESERVED_65 65U +#define MPC55XX_EMIOS_MODE_RESERVED_66 66U +#define MPC55XX_EMIOS_MODE_RESERVED_67 67U +#define MPC55XX_EMIOS_MODE_RESERVED_68 68U +#define MPC55XX_EMIOS_MODE_RESERVED_69 69U +#define MPC55XX_EMIOS_MODE_RESERVED_70 70U +#define MPC55XX_EMIOS_MODE_RESERVED_71 71U +#define MPC55XX_EMIOS_MODE_RESERVED_72 72U +#define MPC55XX_EMIOS_MODE_RESERVED_73 73U +#define MPC55XX_EMIOS_MODE_RESERVED_74 74U +#define MPC55XX_EMIOS_MODE_RESERVED_75 75U +#define MPC55XX_EMIOS_MODE_RESERVED_76 76U +#define MPC55XX_EMIOS_MODE_RESERVED_77 77U +#define MPC55XX_EMIOS_MODE_RESERVED_78 78U +#define MPC55XX_EMIOS_MODE_RESERVED_79 79U +#define MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK 80U +#define MPC55XX_EMIOS_MODE_MCB_UP_EXT_CLK 81U +#define MPC55XX_EMIOS_MODE_RESERVED_82 82U +#define MPC55XX_EMIOS_MODE_RESERVED_83 83U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_ONE_INT_CLK 84U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_ONE_EXT_CLK 85U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_BOTH_INT_CLK 86U +#define MPC55XX_EMIOS_MODE_MCB_UP_DOWN_BOTH_EXT_CLK 87U +#define MPC55XX_EMIOS_MODE_OPWFMB_B 88U +#define MPC55XX_EMIOS_MODE_RESERVED_89 89U +#define MPC55XX_EMIOS_MODE_OPWFMB_AB 90U +#define MPC55XX_EMIOS_MODE_RESERVED_91 91U +#define MPC55XX_EMIOS_MODE_OPWMCB_TRAIL_TRAIL 92U +#define MPC55XX_EMIOS_MODE_OPWMCB_TRAIL_LEAD 93U +#define MPC55XX_EMIOS_MODE_OPWMCB_BOTH_TRAIL 94U +#define MPC55XX_EMIOS_MODE_OPWMCB_BOTH_LEAD 95U +#define MPC55XX_EMIOS_MODE_OPWMB_SECOND 96U +#define MPC55XX_EMIOS_MODE_RESERVED_97 97U +#define MPC55XX_EMIOS_MODE_OPWMB_BOTH 98U +#define MPC55XX_EMIOS_MODE_RESERVED_99 99U +#define MPC55XX_EMIOS_MODE_RESERVED_100 100U +#define MPC55XX_EMIOS_MODE_RESERVED_101 101U +#define MPC55XX_EMIOS_MODE_RESERVED_102 102U +#define MPC55XX_EMIOS_MODE_RESERVED_103 103U +#define MPC55XX_EMIOS_MODE_RESERVED_104 104U +#define MPC55XX_EMIOS_MODE_RESERVED_105 105U +#define MPC55XX_EMIOS_MODE_RESERVED_106 106U +#define MPC55XX_EMIOS_MODE_RESERVED_107 107U +#define MPC55XX_EMIOS_MODE_RESERVED_108 108U +#define MPC55XX_EMIOS_MODE_RESERVED_109 109U +#define MPC55XX_EMIOS_MODE_RESERVED_110 110U +#define MPC55XX_EMIOS_MODE_RESERVED_111 111U +#define MPC55XX_EMIOS_MODE_RESERVED_112 112U +#define MPC55XX_EMIOS_MODE_RESERVED_113 113U +#define MPC55XX_EMIOS_MODE_RESERVED_114 114U +#define MPC55XX_EMIOS_MODE_RESERVED_115 115U +#define MPC55XX_EMIOS_MODE_RESERVED_116 116U +#define MPC55XX_EMIOS_MODE_RESERVED_117 117U +#define MPC55XX_EMIOS_MODE_RESERVED_118 118U +#define MPC55XX_EMIOS_MODE_RESERVED_119 119U +#define MPC55XX_EMIOS_MODE_RESERVED_120 120U +#define MPC55XX_EMIOS_MODE_RESERVED_121 121U +#define MPC55XX_EMIOS_MODE_RESERVED_122 122U +#define MPC55XX_EMIOS_MODE_RESERVED_123 123U +#define MPC55XX_EMIOS_MODE_RESERVED_124 124U +#define MPC55XX_EMIOS_MODE_RESERVED_125 125U +#define MPC55XX_EMIOS_MODE_RESERVED_126 126U +#define MPC55XX_EMIOS_MODE_RESERVED_127 127U + +/** @} */ + +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + #define MPC55XX_EMIOS_CHANNEL_NUMBER 32U +#else + #define MPC55XX_EMIOS_CHANNEL_NUMBER 24U +#endif + +#define MPC55XX_EMIOS_VALUE_MAX 0x00ffffffU + +#define MPC55XX_EMIOS_IS_CHANNEL_VALID( c) \ + ((unsigned) (c) < MPC55XX_EMIOS_CHANNEL_NUMBER) + +#define MPC55XX_EMIOS_IS_CHANNEL_INVALID( c) \ + (!MPC55XX_EMIOS_IS_CHANNEL_VALID( c)) + +void mpc55xx_emios_initialize( unsigned prescaler); + +unsigned mpc55xx_emios_global_prescaler( void); + +void mpc55xx_emios_set_global_prescaler( unsigned prescaler); + +#endif /* MPC55XX_HAS_EMIOS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_EMIOS_H */ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc551x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc551x.h new file mode 100644 index 0000000000..dec0b4cf73 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc551x.h @@ -0,0 +1,4005 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5510.h COPYRIGHT (c) Freescale 2008 */ +/* REVISION: 2.2 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC5510. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +/*************************************************/ +/* Example register & bit field write: */ +/* */ +/* <MODULE>.<REGISTER>.B.<BIT> = 1; */ +/* <MODULE>.<REGISTER>.R = 0x10000000; */ +/* */ +/*************************************************/ + +#ifndef _MPC5510_H_ +#define _MPC5510_H_ + +#ifndef ASM + +#include <stdint.h> + +#include <mpc55xx/regs-edma.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : CRP */ +/****************************************************************************/ + struct CRP_tag { + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t IRC32KEN:1; + uint32_t XOSCEN:1; + uint32_t:1; + uint32_t OSC32KEN:1; + uint32_t TRIM32IRC:8; + uint32_t TRIMIRC:8; + } B; + } CLKSRC; /* Clock Source Register */ + + uint32_t crp_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t CNTEN:1; + uint32_t RTCIE:1; + uint32_t RTCF:1; + uint32_t ROVRF:1; + uint32_t RTCVAL:12; + uint32_t APIEN:1; + uint32_t APIIE:1; + uint32_t APIF:1; + uint32_t CLKSEL:2; + uint32_t ROVREN:1; + uint32_t APIVAL:10; + } B; + } RTCSC; /* RTC Status and Control Register */ + + union { + uint32_t R; + struct { + uint32_t RTCCNT:32; + } B; + } RTCCNT; /* RTC Counter Register */ + + uint32_t crp_reserved2[10]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t WKPSEL7:3; + uint32_t:1; + uint32_t WKPSEL6:3; + uint32_t:1; + uint32_t WKPSEL5:3; + uint32_t:1; + uint32_t WKPSEL4:3; + uint32_t:1; + uint32_t WKPSEL3:3; + uint32_t:1; + uint32_t WKPSEL2:3; + uint32_t:1; + uint32_t WKPSEL1:3; + uint32_t:1; + uint32_t WKPSEL0:3; + } B; + } WKPINSEL; /* Wakeup Pin Source Select Register */ + + union { + uint32_t R; + struct { + uint32_t WKPDET7:2; + uint32_t WKPDET6:2; + uint32_t WKPDET5:2; + uint32_t WKPDET4:2; + uint32_t WKPDET3:2; + uint32_t WKPDET2:2; + uint32_t WKPDET1:2; + uint32_t WKPDET0:2; + uint32_t:5; + uint32_t RTCOVREN:1; + uint32_t RTCWKEN:1; + uint32_t APIWKEN:1; + uint32_t:7; + uint32_t WKCLKSEL:1; + } B; + } WKSE; /* Wakeup Source Enable Register */ + + uint32_t crp_reserved3[2]; + + union { + uint32_t R; + struct { + uint32_t Z1VEC:30; + uint32_t Z1RST:1; + uint32_t VLE:1; + } B; + } Z1VEC; /* Z1 Reset Vector Register */ + + union { + uint32_t R; + struct { + uint32_t Z0VEC:30; + uint32_t Z0RST:1; + uint32_t:1; + } B; + } Z0VEC; /* Z0 Reset Vector Register */ + + union { + uint32_t R; + struct { + uint32_t RECPTR:30; + uint32_t FASTREC:1; + uint32_t:1; + } B; + } RECPTR; /* Reset Recovery Pointer Register */ + + uint32_t crp_reserved4; + + union { + uint32_t R; + struct { + uint32_t SLEEPF:1; + uint32_t STOPF:1; + uint32_t:3; + uint32_t WKRLLOVRF:1; + uint32_t WKAPIF:1; + uint32_t WKRTCF:1; + uint32_t PWKSCRF:8; + uint32_t SLEEP:1; + uint32_t STOP:1; + uint32_t:1; + uint32_t PKREL:1; + uint32_t SLP12EN:1; + uint32_t RAMSEL:3; + uint32_t PWKSRIE:8; + } B; + } PSCR; /* Power Status and Control Register */ + + uint32_t crp_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t LVI5IE:1; + uint32_t LVI5HIE:1; + uint32_t LVI5F:1; + uint32_t LVI5HF:1; + uint32_t LVI5LOCK:1; + uint32_t LVI5RE:1; + uint32_t:9; + uint32_t BYPDIS:1; + uint32_t:16; + } B; + } SOCSC; /* LVI Status and Control Register */ + + }; +/****************************************************************************/ +/* MODULE : DMAMUX */ +/****************************************************************************/ + struct DMAMUX_tag { + union { + uint8_t R; + struct { + uint8_t ENBL:1; + uint8_t TRIG:1; + uint8_t SOURCE:6; + } B; + } CHCONFIG[16]; /* DMA Channel Configuration Register */ + + }; +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t SPI_TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCF_RE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t TXSS:1; + uint32_t:2; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + +/* CS_tag instantiated within EBI_tag */ + struct EBI_CS_tag { + union { /* Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:3; + uint32_t AD_MUX:1; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:1; + uint32_t SETA:1; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_CAL_CS_tag { + uint32_t ebi_cal_cs_reserved [2]; + }; + + struct EBI_tag { + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ACGE:1; + uint32_t EXTM:1; + uint32_t EARB:1; + uint32_t:6; + uint32_t MDIS:1; + uint32_t:3; + uint32_t D16_31:1; + uint32_t AD_MUX:1; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + /* Roll in 3x CS registers */ + struct EBI_CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + struct EBI_CAL_CS_tag CAL_CS[4]; + }; +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t:1; + uint32_t GPREN:1; + uint32_t:10; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFG; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t UC23:1; + uint32_t UC22:1; + uint32_t UC21:1; + uint32_t UC20:1; + uint32_t UC19:1; + uint32_t UC18:1; + uint32_t UC17:1; + uint32_t UC16:1; + uint32_t UC15:1; + uint32_t UC14:1; + uint32_t UC13:1; + uint32_t UC12:1; + uint32_t UC11:1; + uint32_t UC10:1; + uint32_t UC9:1; + uint32_t UC8:1; + uint32_t UC7:1; + uint32_t UC6:1; + uint32_t UC5:1; + uint32_t UC4:1; + uint32_t UC3:1; + uint32_t UC2:1; + uint32_t UC1:1; + uint32_t UC0:1; + } B; + } UCDIS; /* Disable Channel Register */ + + uint32_t emios_reserved1[4]; + + struct EMIOS_CH_tag { + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t A:16; /* Channel A Data Register */ + } B; + } CADR; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t B:16; /* Channel B Data Register */ + } B; + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + struct { + uint32_t:16; + uint32_t C:16; /* Channel C Data Register */ + } B; + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + uint32_t R; /* Alternate Channel A Data Register */ + } ALTA; + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t eqadc_reserved0; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t CF_PUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RF_POP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t:4; + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union { + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union { + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t TC_CF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + uint32_t R; + struct { + uint32_t CFS0_T0:2; + uint32_t CFS1_T0:2; + uint32_t CFS2_T0:2; + uint32_t CFS3_T0:2; + uint32_t CFS4_T0:2; + uint32_t CFS5_T0:2; + uint32_t:5; + uint32_t LCFT0:4; + uint32_t TC_LCFT0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + uint32_t eqadc_reserved10[2]; + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11[20]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved12[12]; + + } CF[6]; + + uint32_t eqadc_reserved13[32]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved14[12]; + + } RF[6]; + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t TXDIR:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t:1; + uint16_t PMSK:1; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t R8:1; + uint16_t T8:1; + uint16_t:6; + uint8_t D; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:3; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:6; + uint32_t UREQ:1; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t LDBG:1; + uint32_t DSF:1; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:6; + uint32_t UQIE:1; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint32_t R; + } LTR; /* LIN Transmit Register */ + + union { + uint32_t R; + } LRR; /* LIN Recieve Register */ + + union { + uint32_t R; + } LPR; /* LIN CRC Polynom Register */ + + }; +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:3; + uint32_t SFS:1; + uint32_t SIZE:4; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t BBEPE:1; + uint32_t EPE:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + uint32_t:1; + uint32_t PRD:1; + uint32_t STOP:1; + uint32_t:1; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t:2; + uint32_t MLOCK:2; + uint32_t:6; + uint32_t LLOCK:10; + } B; + } LMLR; /* Legacy naming - refer to LML in Reference Manual */ + + union HLR_tag { /* High Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:23; + uint32_t HBLOCK:8; + } B; + } HLR; /* Legacy naming - refer to HBL in Reference Manual */ + + union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t:2; + uint32_t SMLOCK:2; + uint32_t:6; + uint32_t SLLOCK:10; + } B; + } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ + + union { /* Low/Mid Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MSEL:2; + uint32_t:6; + uint32_t LSEL:10; + } B; + } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ + + union { /* High Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t HBSEL:4; + } B; + } HSR; /* Legacy naming - refer to HBS in Reference Manual */ + + union { /* Address Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t ADDR:19; + uint32_t:3; + } B; + } AR; /* Legacy naming - refer to ADR in Reference Manual */ + + union { /* Platform Flash Configuration Register for Port 0 */ + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t ARB:1; + uint32_t PRI:1; + uint32_t:5; + uint32_t M4PFE:1; + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP0; + + union { /* Platform Flash Configuration Register for Port 1 */ + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t:7; + uint32_t M4PFE:1; + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP1; + + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t FEN:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t WAKMSK:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t SUPV:1; + uint32_t SLFWAK:1; + uint32_t WRNEN:1; + uint32_t LPMACK:1; + uint32_t WAKSRC:1; + uint32_t DOZE:1; + uint32_t SRXDIS:1; + uint32_t BCC:1; + uint32_t:2; + uint32_t LPRIO_EN:1; + uint32_t AEN:1; + uint32_t:2; + uint32_t IDAM:2; + uint32_t:2; + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CTRL; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMASK2; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMASK1; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFLAG2; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFLAG1; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t PRIO:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + uint32_t FLEXCAN_reserved3[256]; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + + uint32_t FMPLL_reserved0; + + union FMPLL_SYNSR_tag { /* Synthesiser Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + union FMPLL_ESYNCR1_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t CLKCFG:3; + uint32_t:8; + uint32_t EPREDIV:4; + uint32_t:8; + uint32_t EMFD:8; + } B; + } ESYNCR1; + + union FMPLL_ESYNCR2_tag { + uint32_t R; + struct { + uint32_t:8; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t:1; + uint32_t ERATE:2; + uint32_t:5; + uint32_t EDEPTH:3; + uint32_t:2; + uint32_t ERFD:6; + } B; + } ESYNCR2; + + }; +/****************************************************************************/ +/* MODULE : i2c */ +/****************************************************************************/ + struct I2C_tag { + union { + uint8_t R; + struct { + uint8_t AD:7; + uint8_t:1; + } B; + } IBAD; /* Module Bus Address Register */ + + union { + uint8_t R; + struct { + uint8_t MULT:2; + uint8_t ICR:6; + } B; + } IBFD; /* Module Bus Frequency Register */ + + union { + uint8_t R; + struct { + uint8_t MDIS:1; + uint8_t IBIE:1; + uint8_t MS:1; + uint8_t TX:1; + uint8_t NOACK:1; + uint8_t RSTA:1; + uint8_t DMAEN:1; + uint8_t:1; + } B; + } IBCR; /* Module Bus Control Register */ + + union { + uint8_t R; + struct { + uint8_t TCF:1; + uint8_t IAAS:1; + uint8_t IBB:1; + uint8_t IBAL:1; + uint8_t:1; + uint8_t SRW:1; + uint8_t IBIF:1; + uint8_t RXAK:1; + } B; + } IBSR; /* Module Status Register */ + + union { + uint8_t R; + struct { + uint8_t DATA:8; + } B; + } IBDR; /* Module Data Register */ + + union { + uint8_t R; + struct { + uint8_t BIIE:1; + uint8_t:7; + } B; + } IBIC; /* Module Interrupt Configuration Register */ + + }; +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:18; + uint32_t VTES_PRC1:1; + uint32_t:4; + uint32_t HVEN_PRC1:1; + uint32_t:2; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved1; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Processor 0 Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR_PRC1; /* Processor 1 Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Processor 0 Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA_PRC1:21; + uint32_t INTVEC_PRC1:9; + uint32_t:2; + } B; + } IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* Processor 0 End of Interrupt Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR_PRC1; /* Processor 1 End of Interrupt Register */ + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved2[6]; + + union { + uint8_t R; + struct { + uint8_t PRC_SEL:2; + uint8_t:2; + uint8_t PRI:4; + } B; + } PSR[294]; /* Software Set/Clear Interrupt Register */ + + }; +/****************************************************************************/ +/* MODULE : MCM */ +/****************************************************************************/ + struct MCM_tag { + + uint32_t mcm_reserved1[5]; + + uint16_t mcm_reserved2; + + union { + uint16_t R; + struct { + uint16_t RO:1; + uint16_t:6; + uint16_t SWRWH:1; + uint16_t SWE:1; + uint16_t SWRI:2; + uint16_t SWT:5; + } B; + } SWTCR; /* Software Watchdog Timer Control */ + + uint8_t mcm_reserved3[3]; + + union { + uint8_t R; + } SWTSR; /* SWT Service Register */ + + uint8_t mcm_reserved4[3]; + + union { + uint8_t R; + struct { + uint8_t:7; + uint8_t SWTIC:1; + } B; + } SWTIR; /* SWT Interrupt Register */ + + uint32_t mcm_reserved5[1]; + + union { + uint32_t R; + struct { + uint32_t PRI:1; + uint32_t:31; + } B; + } MUDCR; /* Misc. User Defined Control Register */ + + uint32_t mcm_reserved6[6]; + uint8_t mcm_reserved7[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t mcm_reserved8[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; /* ECC Status Register */ + + uint16_t mcm_reserved9; + + union { + uint16_t R; + struct { + uint16_t:6; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; /* ECC Error Generation Register */ + + uint32_t mcm_reserved10; + + union { + uint32_t R; + } FEAR; /* Flash ECC Address Register */ + + uint16_t mcm_reserved11; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; /* Flash ECC Master Register */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } FEAT; /* Flash ECC Attributes Register */ + + union { + uint32_t R; + } FEDRH; /* Flash ECC Data High Register */ + + union { + uint32_t R; + } FEDRL; /* Flash ECC Data Low Register */ + + union { + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; /* RAM ECC Address */ + + uint16_t mcm_reserved12; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; /* RAM ECC Master */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } REAT; /* RAM ECC Attributes Register */ + + union { + uint32_t R; + } REDRH; /* RAM ECC Data High Register */ + + union { + uint32_t R; + } REDRL; /* RAMECC Data Low Register */ + + }; +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + struct MPU_tag { + union { + uint32_t R; + struct { + uint32_t SPERR:8; + uint32_t:4; + uint32_t HRL:4; + uint32_t NSP:4; + uint32_t NGRD:4; + uint32_t:7; + uint32_t VLD:1; + } B; + } CESR; /* Module Control/Error Status Register */ + + uint32_t mpu_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR0; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR0; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR1; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR1; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR2; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR2; + + uint32_t mpu_reserved2[246]; + + struct { + union { + uint32_t R; + struct { + uint32_t SRTADDR:27; + uint32_t:5; + } B; + } WORD0; /* Region Descriptor n Word 0 */ + + union { + uint32_t R; + struct { + uint32_t ENDADDR:27; + uint32_t:5; + } B; + } WORD1; /* Region Descriptor n Word 1 */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t M4RE0:1; + uint32_t M4WE:1; + uint32_t M3PE:1; + uint32_t M3SM:2; + uint32_t M3UM:3; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } WORD2; /* Region Descriptor n Word 2 */ + + union { + uint32_t R; + struct { + uint32_t PID:8; + uint32_t PIDMASK:8; + uint32_t:15; + uint32_t VLD:1; + } B; + } WORD3; /* Region Descriptor n Word 3 */ + + } RGD[16]; + + uint32_t mpu_reserved3[192]; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t M3PE:1; + uint32_t M3SM:2; + uint32_t M3UM:3; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ + }; +/****************************************************************************/ +/* MODULE : pit */ +/****************************************************************************/ + struct PIT_tag { + union { + uint32_t R; + struct { + uint32_t TSV:32; + } B; + } TLVAL[9]; + + uint32_t pit_reserved1[23]; + + union { + uint32_t R; + struct { + uint32_t TVL:32; + } B; + } TVAL[9]; + + uint32_t pit_reserved2[23]; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t TIF8:1; + uint32_t TIF7:1; + uint32_t TIF6:1; + uint32_t TIF5:1; + uint32_t TIF4:1; + uint32_t TIF3:1; + uint32_t TIF2:1; + uint32_t TIF1:1; + uint32_t RTIF:1; + } B; + } PITFLG; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t TIE8:1; + uint32_t TIE7:1; + uint32_t TIE6:1; + uint32_t TIE5:1; + uint32_t TIE4:1; + uint32_t TIE3:1; + uint32_t TIE2:1; + uint32_t TIE1:1; + uint32_t RTIE:1; + } B; + } PITINTEN; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t ISEL8:1; + uint32_t ISEL7:1; + uint32_t ISEL6:1; + uint32_t ISEL5:1; + uint32_t ISEL4:1; + uint32_t ISEL3:1; + uint32_t ISEL2:1; + uint32_t ISEL1:1; + uint32_t:1; + } B; + } PITINTSEL; + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t PEN8:1; + uint32_t PEN7:1; + uint32_t PEN6:1; + uint32_t PEN5:1; + uint32_t PEN4:1; + uint32_t PEN3:1; + uint32_t PEN2:1; + uint32_t PEN1:1; + uint32_t PEN0:1; + } B; + } PITEN; + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t MDIS:1; + uint32_t:24; + } B; + } PITCTRL; + + }; +/****************************************************************************/ +/* MODULE : sem4 */ +/****************************************************************************/ + struct SEMA4_tag { + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t GTFSM:2; + } B; + } GATE[16]; /* Gate n Register */ + + uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP0INE; + + uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP1INE; + + uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP0NTF; + + uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP1NTF; + + uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */ + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTGSM:2; + uint16_t:1; + uint16_t RSTGMS:3; + uint16_t RSTGTN:8; + } B; + } RSTGT; + + uint16_t sema4_reserved6; + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTNSM:2; + uint16_t:1; + uint16_t RSTNMS:3; + uint16_t RSTNTN:8; + } B; + } RSTNTF; + }; +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + + int32_t SIU_reserved0; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t CSP:1; + uint32_t PKG:5; + uint32_t:2; + uint32_t MASKNUM_MAJOR:4; + uint32_t MASKNUM_MINOR:4; + } B; + } MIDR; + + int32_t SIU_reserved1; + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t:15; + uint32_t BOOTCFG:1; + uint32_t:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t:15; + uint32_t CRE0:1; + uint32_t CRE1:1; + uint32_t:6; + uint32_t SSRL:1; + uint32_t:7; + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t NMI0:1; + uint32_t NMI1:1; + uint32_t:14; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ + uint32_t R; + struct { + uint32_t:27; + uint32_t DIRS4:1; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t NREE0:1; + uint32_t NREE1:1; + uint32_t:14; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t NFEE0:1; + uint32_t NFEE1:1; + uint32_t:14; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + union { /* External IRQ Filtered Input Register */ + uint32_t R; + struct { + uint32_t FNMI0:1; + uint32_t FNMI1:1; + uint32_t:14; + uint32_t FI15:1; + uint32_t FI14:1; + uint32_t FI13:1; + uint32_t FI12:1; + uint32_t FI11:1; + uint32_t FI10:1; + uint32_t FI9:1; + uint32_t FI8:1; + uint32_t FI7:1; + uint32_t FI6:1; + uint32_t FI5:1; + uint32_t FI4:1; + uint32_t FI3:1; + uint32_t FI2:1; + uint32_t FI1:1; + uint32_t FI0:1; + } B; + } IFIR; + + int32_t SIU_reserved2[2]; + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:4; + uint16_t PA:2; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[146]; + + int32_t SIU_reserved3[295]; + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[146]; + + int32_t SIU_reserved4[91]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[146]; + + int32_t SIU_reserved5[27]; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t TSEL3:2; + uint32_t TSEL2:2; + uint32_t TSEL1:2; + uint32_t TSEL0:2; + uint32_t:24; + } B; + } ISEL0; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL1; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t SELEMIOS15:2; + uint32_t SELEMIOS14:2; + uint32_t SELEMIOS13:2; + uint32_t SELEMIOS12:2; + uint32_t SELEMIOS11:2; + uint32_t SELEMIOS10:2; + uint32_t SELEMIOS9:2; + uint32_t SELEMIOS8:2; + uint32_t SELEMIOS7:2; + uint32_t SELEMIOS6:2; + uint32_t SELEMIOS5:2; + uint32_t SELEMIOS4:2; + uint32_t SELEMIOS3:2; + uint32_t SELEMIOS2:2; + uint32_t SELEMIOS1:2; + uint32_t SELEMIOS0:2; + } B; + } ISEL2; + + int32_t SIU_reserved6[29]; + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t EBDF:2; + } B; + } ECCR; + + union { /* Compare A High Register */ + uint32_t R; + } CMPAH; + + union { /* Compare A Low Register */ + uint32_t R; + } CMPAL; + + union { /* Compare B High Register */ + uint32_t R; + } CMPBH; + + union { /* Compare B Low Register */ + uint32_t R; + } CMPBL; + + int32_t SIU_reserved7[2]; + + union { /* System CLock Register */ + uint32_t R; + struct { + uint32_t SYSCLKSEL:2; + uint32_t SYSCLKDIV:2; + uint32_t SWTCLKSEL:1; + uint32_t:11; + uint32_t LPCLKDIV7:2; + uint32_t LPCLKDIV6:2; + uint32_t LPCLKDIV5:2; + uint32_t LPCLKDIV4:2; + uint32_t LPCLKDIV3:2; + uint32_t LPCLKDIV2:2; + uint32_t LPCLKDIV1:2; + uint32_t LPCLKDIV0:2; + } B; + } SYSCLK; + + union { /* Halt Register */ + uint32_t R; + } HLT; + + union { /* Halt Acknowledge Register */ + uint32_t R; + } HLTACK; + + int32_t SIU_reserved8[149]; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t PB:16; + } B; + } PGPDO0; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDO1; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDO2; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDO3; + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t:16; + } B; + } PGPDO4; + + int32_t SIU_reserved9[11]; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PA:16; + uint32_t PB:16; + } B; + } PGPDI0; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDI1; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDI2; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDI3; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t PK:2; + uint32_t:14; + } B; + } PGPDI4; + + int32_t SIU_reserved10[12]; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PB_MASK:16; + uint32_t PB:16; + } B; + } MPGPDO1; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PC_MASK:16; + uint32_t PC:16; + } B; + } MPGPDO2; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PD_MASK:16; + uint32_t PD:16; + } B; + } MPGPDO3; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PE_MASK:16; + uint32_t PE:16; + } B; + } MPGPDO4; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PF_MASK:16; + uint32_t PF:16; + } B; + } MPGPDO5; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PG_MASK:16; + uint32_t PG:16; + } B; + } MPGPDO6; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PH_MASK:16; + uint32_t PH:16; + } B; + } MPGPDO7; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PJ_MASK:16; + uint32_t PJ:16; + } B; + } MPGPDO8; + + }; +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:2; + uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ + uint16_t:2; + uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:2; + uint16_t TBIVEC:6; /* transmit buffer interrupt vector */ + uint16_t:2; + uint16_t RBIVEC:6; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSYMATOR { + uint16_t R; + struct { + uint16_t:11; + uint16_t TIMEOUT:5; /* system memory time out value */ + } B; + } SYMATOR_t; + + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:5; + uint16_t RSBIDX:7; /* receive shadow buffer index */ + } B; + } RSBIR_t; + + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + + union { + uint16_t R; + struct { + uint16_t:9; + uint16_t MBIDX:7; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPADR { + uint16_t R; + } PADR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + uint16_t reserved0[1]; /*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved1[1]; /*10 */ + uint16_t reserved2[1]; /*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved3[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; +/****************************************************************************/ +/* MODULE : MLB */ +/****************************************************************************/ + struct MLB_tag { + + union { /* MLB Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t:15; + uint32_t MDATOBSE:1; + uint32_t MSIGOBS:1; + uint32_t MSLOTE:1; + uint32_t:2; + uint32_t MSVRQIE:1; + uint32_t MDATRQE:1; + uint32_t:2; + uint32_t MSVRQDL:3; + uint32_t MSVRQCIE:1; + uint32_t MIFSEL:1; + uint32_t MSBFEPOL:1; + uint32_t MDBFEPOL:1; + } B; + } MCR; + + union { /* MLB Blank Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t BLANK:1; + } B; + } MBR; + + union { /* MLB Status Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t MDATRQS:1; + uint32_t MSYSS:1; + uint32_t MSVRQS:1; + } B; + } MSR; + + union { /* RX Control Channel Address Register */ + uint32_t R; + struct { + uint32_t RXCCHA_ACEN:1; + uint32_t:25; + uint32_t RXCCHA:5; + uint32_t:1; + } B; + } RXCCHAR; + + union { /* RX Async Channel Address Register */ + uint32_t R; + struct { + uint32_t RXACHA_ACEN:1; + uint32_t:25; + uint32_t RXACHA:5; + uint32_t:1; + } B; + } RXACHAR; + + union { /* TX Control Channel Address Register */ + uint32_t R; + struct { + uint32_t TXCCHA_ACEN:1; + uint32_t:25; + uint32_t TXCCHA:5; + uint32_t:1; + } B; + } TXCCHAR; + + union { /* TX Async Channel Address Register */ + uint32_t R; + struct { + uint32_t TXACHA_ACEN:1; + uint32_t:25; + uint32_t TXACHA:5; + uint32_t:1; + } B; + } TXACHAR; + + union { /* TX Sync Channel Address Register */ + uint32_t R; + struct { + uint32_t TXSCHA_ACEN:1; + uint32_t:25; + uint32_t TXSCHA:5; + uint32_t:1; + } B; + } TXSCHAR; + + union { /* TX Sync Channel Address Mask Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t TXSCHAM:5; + uint32_t:1; + } B; + } TXSCHAMR; + + union { /* Clock Adjust Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t PDLY:16; + } B; + } CLKACR; + + union { /* RX Isochronous Channel Address Register */ + uint32_t R; + struct { + uint32_t RXICHA_ACEN:1; + uint32_t:25; + uint32_t RXICHA:5; + uint32_t:1; + } B; + } RXICHAR; + + union { /* TX Isochronous Channel Address Register */ + uint32_t R; + struct { + uint32_t TXICHA_ACEN:1; + uint32_t:25; + uint32_t TXICHA:5; + uint32_t:1; + } B; + } TXICHAR; + + }; + +/* Define memories */ + +#define SRAM_START 0x40000000UL +#define SRAM_SIZE 0x14000UL +#define SRAM_END 0x40013FFFUL + +#define FLASH_START 0x0UL +#define FLASH_SIZE 0x180000UL +#define FLASH_END 0x17FFFFUL + +/* Define instances of modules */ +#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL) +#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000UL) +#define MLB (*(volatile struct MLB_tag *) 0xFFF84000UL) +#define I2C (*(volatile struct I2C_tag *) 0xFFF88000UL) +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000UL) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000UL) +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL) +#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL) +#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL) +#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL) +#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL) +#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL) +#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL) +#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) +#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) +#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) +#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) +#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) +#define FR (*(volatile struct FR_tag *) 0xFFFD8000UL) +#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) +#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL) +#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL) +#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL) +#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL) +#define EBI (*(volatile struct EBI_tag *) 0xFFFF4000UL) +#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5510_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc555x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc555x.h new file mode 100644 index 0000000000..0dea1957cf --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc555x.h @@ -0,0 +1,3383 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */ +/* VERSION: 1.7 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC5554. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */ +/* Based on SoC version 0.7. */ +/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */ +/* defined. */ +/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/ +/* bugs and naming/formating issues. */ +/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/ +/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */ +/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */ +/* Updated many register names. */ +/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */ +/* register name updates. */ +/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */ +/* Updated for user manual 1.0 */ +/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */ +/* bit field names to match user's man. */ +/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */ +/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */ +/* manual, also some testing done. */ +/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */ +/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/ +/* changed eTPU memory defs to start with*/ +/* ETPU_ */ +/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */ +/* All code moved to CVS repository. */ +/* Updated copyright to Freescale. */ +/* Added new SCMOFFDATAR register to eTPU*/ +/* Fixed REDCR_A&B bit fields in eTPU. */ +/* Added new DBR bit in CTAR for DSPI. */ +/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */ +/* Added bit fields for FlexCAN buffer ID*/ +/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */ +/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */ +/* seperate new file. */ +/* Removed SIU variable the GPIO */ +/* routines do not need it. */ +/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */ +/* Joint generation with mpc5553.h */ +/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */ +/* expansion of PCR/GPDI/GPDO */ +/* Added #defines for memory sizes etc */ +/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */ +/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */ +/* XBAR MPR now generic */ +/* ECSM has FSBMCR on all integrations */ +/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */ +/* integration specific */ +/* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */ +/* process. No real change. */ +/* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */ +/* to DPB to align with documentation. */ +/* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */ +/* alternate configuration. INTC, */ +/* correction to the number of PSR */ +/* registers. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC5554_H_ +#define _MPC5554_H_ + +#ifndef ASM + +#include <stdint.h> + +#include <mpc55xx/regs-edma.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : PBRIDGE_A Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_A_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_a_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:28; + } B; + } PACR0; + + uint32_t pbridge_a_reserved3[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + + uint32_t BW0:1; /* EMIOS */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t:28; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR2; + + }; + +/****************************************************************************/ +/* MODULE : PBRIDGE_B Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_B_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_b_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t:24; + } B; + } PACR0; + + uint32_t pbridge_b_reserved3; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t:4; + + uint32_t:16; + + } B; + } PACR2; + + uint32_t pbridge_b_reserved4[5]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:12; + + uint32_t BW4:1; /* DSPI_A */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t BW5:1; /* DSPI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t BW6:1; + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t BW5:1; /* ESCI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t:8; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t BW1:1; /* CAN_B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t:4; + + uint32_t:4; + + uint32_t:12; + } B; + } OPACR2; + + union { + uint32_t R; + struct { + + uint32_t:4; + + uint32_t:24; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR3; + + }; +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union FMPLL_SYNCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t PREDIV:3; + uint32_t MFD:5; + uint32_t:1; + uint32_t RFD:3; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t DISCLK:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t RATE:1; + uint32_t DEPTH:2; + uint32_t EXP:10; + } B; + } SYNCR; + + union FMPLL_SYNSR_tag { + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + }; +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + struct EBI_CS_tag { + union { /* Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:4; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:2; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_CAL_CS_tag { + uint32_t ebi_cal_cs_reserved [2]; + }; + + struct EBI_tag { + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZEEN:1; + uint32_t SIZE:2; + uint32_t:8; + uint32_t ACGE:1; + uint32_t EXTM:1; + uint32_t EARB:1; + uint32_t EARP:2; + uint32_t:4; + uint32_t MDIS:1; + uint32_t:5; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + struct EBI_CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + struct EBI_CAL_CS_tag CAL_CS[4]; + }; +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:4; + uint32_t SIZE:4; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t BBEPE:1; + uint32_t EPE:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + + uint32_t:2; + + uint32_t STOP:1; + uint32_t:1; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* LML Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t MLOCK:4; + uint32_t LLOCK:16; + } B; + } LMLR; + + union HLR_tag { /* HL Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:3; + uint32_t HBLOCK:28; + } B; + } HLR; + + union SLMLR_tag { /* SLML Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t SMLOCK:4; + uint32_t SLLOCK:16; + } B; + } SLMLR; + + union { /* LMS Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t MSEL:4; + uint32_t LSEL:16; + } B; + } LMSR; + + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t HBSEL:28; + } B; + } HSR; + + union { + uint32_t R; + struct { + uint32_t:10; + uint32_t ADDR:19; + uint32_t:3; + } B; + } AR; + + union { + uint32_t R; + struct { + + uint32_t:11; + + uint32_t:1; + + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + + uint32_t DPFEN:2; + uint32_t IPFEN:2; + + uint32_t PFLIM:3; + uint32_t BFEN:1; + } B; + } BIUCR; + + union { + uint32_t R; + struct { + + uint32_t:22; + + uint32_t:2; + + uint32_t M3AP:2; + uint32_t M2AP:2; + uint32_t M1AP:2; + uint32_t M0AP:2; + } B; + } BIUAPR; + }; +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + int32_t SIU_reserved0; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t MASKNUM:16; + } B; + } MIDR; + int32_t SIU_reserved00; + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t SERF:1; + uint32_t WKPCFG:1; + uint32_t:12; + uint32_t BOOTCFG:2; + uint32_t RGF:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t SER:1; + uint32_t:14; + uint32_t CRE:1; + uint32_t:15; + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + int32_t SIU_reserved1[3]; + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t PA:3; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[512]; + + int16_t SIU_reserved_0[224]; + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[256]; + + int32_t SIU_reserved_3[64]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[256]; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t TSEL5:2; + uint32_t TSEL4:2; + uint32_t TSEL3:2; + uint32_t TSEL2:2; + uint32_t TSEL1:2; + uint32_t TSEL0:2; + uint32_t:20; + } B; + } ETISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } EIISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t SINSELA:2; + uint32_t SSSELA:2; + uint32_t SCKSELA:2; + uint32_t TRIGSELA:2; + uint32_t SINSELB:2; + uint32_t SSSELB:2; + uint32_t SCKSELB:2; + uint32_t TRIGSELB:2; + uint32_t SINSELC:2; + uint32_t SSSELC:2; + uint32_t SCKSELC:2; + uint32_t TRIGSELC:2; + uint32_t SINSELD:2; + uint32_t SSSELD:2; + uint32_t SCKSELD:2; + uint32_t TRIGSELD:2; + } B; + } DISR; + + int32_t SIU_reserved2[29]; + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t ENGDIV:6; + uint32_t:4; + uint32_t EBTS:1; + uint32_t:1; + uint32_t EBDF:2; + } B; + } ECCR; + + union { + uint32_t R; + } CARH; + + union { + uint32_t R; + } CARL; + + union { + uint32_t R; + } CBRH; + + union { + uint32_t R; + } CBRL; + + }; +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t ETB:1; + uint32_t GPREN:1; + uint32_t:6; + uint32_t SRV:4; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + uint32_t emios_reserved[5]; + + struct EMIOS_CH_tag { + union { + uint32_t R; /* Channel A Data Register */ + } CADR; + + union { + uint32_t R; /* Channel B Data Register */ + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + uint32_t emios_channel_reserved[3]; + + } CH[24]; + + }; +/****************************************************************************/ +/* MODULE :ETPU */ +/****************************************************************************/ + +/***************************Configuration Registers**************************/ + + struct ETPU_tag { + union { /* MODULE CONFIGURATION REGISTER */ + uint32_t R; + struct { + uint32_t GEC:1; /* Global Exception Clear */ + uint32_t:3; + uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ + + uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ + + uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ + + uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ + + uint32_t:3; + uint32_t SCMSIZE:5; /* Shared Code Memory size */ + uint32_t:5; + uint32_t SCMMISF:1; /* SCM MISC Flag */ + uint32_t SCMMISEN:1; /* SCM MISC Enable */ + uint32_t:2; + uint32_t VIS:1; /* SCM Visability */ + uint32_t:5; + uint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; + + union { /* COHERENT DUAL-PARAMETER CONTROL */ + uint32_t R; + struct { + uint32_t STS:1; /* Start Status bit */ + uint32_t CTBASE:5; /* Channel Transfer Base */ + uint32_t PBASE:10; /* Parameter Buffer Base Address */ + uint32_t PWIDTH:1; /* Parameter Width */ + uint32_t PARAM0:7; /* Channel Parameter 0 */ + uint32_t WR:1; + uint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; + + uint32_t etpu_reserved1; + + union { /* MISC Compare Register */ + uint32_t R; + } MISCCMPR; + + union { /* SCM off-range Date Register */ + uint32_t R; + } SCMOFFDATAR; + + union { /* ETPU_A Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:4; + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:9; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; + + union { /* ETPU_B Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:4; + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:9; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_B; + + uint32_t etpu_reserved4; + + union { /* ETPU_A Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t:1; + uint32_t AM:1; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t:6; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; + + union { /* ETPU_A TCR1 Visibility Register */ + uint32_t R; + } TB1R_A; + + union { /* ETPU_A TCR2 Visibility Register */ + uint32_t R; + } TB2R_A; + + union { /* ETPU_A STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; + + uint32_t etpu_reserved5[4]; + + union { /* ETPU_B Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t:1; + uint32_t AM:1; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t:6; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_B; + + union { /* ETPU_B TCR1 Visibility Register */ + uint32_t R; + } TB1R_B; + + union { /* ETPU_B TCR2 Visibility Register */ + uint32_t R; + } TB2R_B; + + union { /* ETPU_B STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_B; + + uint32_t etpu_reserved7[108]; + +/*****************************Status and Control Registers**************************/ + + union { /* ETPU_A Channel Interrut Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrut Status */ + uint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; + + union { /* ETPU_B Channel Interruput Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrupt Status */ + uint32_t CIS0:1; /* Channel 0 Interrupt Status */ + } B; + } CISR_B; + + uint32_t etpu_reserved9[2]; + + union { /* ETPU_A Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; + + union { /* ETPU_B Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_B; + + uint32_t etpu_reserved11[2]; + + union { /* ETPU_A Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; + + union { /* ETPU_B Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_B; + + uint32_t etpu_reserved13[2]; + + union { /* ETPU_A Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; + + union { /* ETPU_B Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_B; + + uint32_t etpu_reserved15[2]; + + union { /* ETPU_A Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; + + union { /* ETPU_B Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_B; + + uint32_t etpu_reserved17[2]; + + union { /* ETPU_A Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; + + union { /* ETPU_B Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_B; + + uint32_t etpu_reserved20[10]; + union { /* ETPU_A Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_A; + + union { /* ETPU_B Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_B; + + uint32_t etpu_reserved20a[2]; + + union { /* ETPU_A Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_A; + + union { /* ETPU_B Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_B; + + uint32_t etpu_reserved23[90]; + +/*****************************Channels********************************/ + + struct { + union { + uint32_t R; /* Channel Configuration Register */ + struct { + uint32_t CIE:1; /* Channel Interruput Enable */ + uint32_t DTRE:1; /* Data Transfer Request Enable */ + uint32_t CPR:2; /* Channel Priority */ + uint32_t:3; + uint32_t ETCS:1; /* Entry Table Condition Select */ + uint32_t:3; + uint32_t CFS:5; /* Channel Function Select */ + uint32_t ODIS:1; /* Output disable */ + uint32_t OPOL:1; /* output polarity */ + uint32_t:3; + uint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; + union { + uint32_t R; /* Channel Status Control Register */ + struct { + uint32_t CIS:1; /* Channel Interruput Status */ + uint32_t CIOS:1; /* Channel Interruput Overflow Status */ + uint32_t:6; + uint32_t DTRS:1; /* Data Transfer Status */ + uint32_t DTROS:1; /* Data Transfer Overflow Status */ + uint32_t:6; + uint32_t IPS:1; /* Input Pin State */ + uint32_t OPS:1; /* Output Pin State */ + uint32_t OBE:1; /* Output Buffer Enable */ + uint32_t:11; + uint32_t FM1:1; /* Function mode */ + uint32_t FM0:1; /* Function mode */ + } B; + } SCR; + union { + uint32_t R; /* Channel Host Service Request Register */ + struct { + uint32_t:29; /* Host Service Request */ + uint32_t HSR:3; + } B; + } HSRR; + uint32_t etpu_reserved23; + } CHAN[127]; + + }; +/****************************************************************************/ +/* MODULE : XBAR CrossBar */ +/****************************************************************************/ + struct XBAR_tag { + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR0; /* Master Priority Register for Slave Port 0 */ + + uint32_t xbar_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; /* General Purpose Control Register for Slave Port 0 */ + + uint32_t xbar_reserved2[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR1; /* Master Priority Register for Slave Port 1 */ + + uint32_t xbar_reserved3[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; /* General Purpose Control Register for Slave Port 1 */ + + uint32_t xbar_reserved4[123]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR3; /* Master Priority Register for Slave Port 3 */ + + uint32_t xbar_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR3; /* General Purpose Control Register for Slave Port 3 */ + uint32_t xbar_reserved6[187]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR6; /* Master Priority Register for Slave Port 6 */ + + uint32_t xbar_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; /* General Purpose Control Register for Slave Port 6 */ + + uint32_t xbar_reserved8[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR7; /* Master Priority Register for Slave Port 7 */ + + uint32_t xbar_reserved9[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ + + }; +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + + uint32_t ecsm_reserved1[5]; + + uint16_t ecsm_reserved2; + + union { + uint16_t R; + } SWTCR; //Software Watchdog Timer Control + + uint8_t ecsm_reserved3[3]; + + union { + uint8_t R; + } SWTSR; //SWT Service Register + + uint8_t ecsm_reserved4[3]; + + union { + uint8_t R; + } SWTIR; //SWT Interrupt Register + + uint32_t ecsm_reserved5a[1]; + uint32_t ecsm_reserved5b[1]; + + uint32_t ecsm_reserved5c[6]; + + uint8_t ecsm_reserved6[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; //ECC Configuration Register + + uint8_t mcm_reserved8[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; //ECC Status Register + + uint16_t ecsm_reserved9; + + union { + uint16_t R; + struct { + uint16_t:6; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; //ECC Error Generation Register + + uint32_t ecsm_reserved10; + + union { + uint32_t R; + struct { + uint32_t FEAR:32; + } B; + } FEAR; //Flash ECC Address Register + + uint16_t ecsm_reserved11; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; //Flash ECC Master Register + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } FEAT; //Flash ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t FEDH:32; + } B; + } FEDRH; //Flash ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t FEDL:32; + } B; + } FEDRL; //Flash ECC Data Low Register + + union { + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; //RAM ECC Address + + uint8_t ecsm_reserved12[2]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; //RAM ECC Master + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } REAT; // RAM ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t REDH:32; + } B; + } REDRH; //RAM ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t REDL:32; + } B; + } REDRL; //RAMECC Data Low Register + + }; +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:26; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Current Priority Register */ + + uint32_t intc_reserved1; + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Interrupt Acknowledge Register */ + + uint32_t intc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* End of Interrupt Register */ + + uint32_t intc_reserved3; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved4[6]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PRI:4; + } B; + } PSR[358]; /* Software Set/Clear Interrupt Register */ + + }; +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t ESSIE:2; + uint32_t:1; + uint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + int32_t EQADC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t CFPUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RFPOP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union EQADC_CFCR_tag { + uint16_t R; + struct { + uint16_t:5; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t:4; + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union EQADC_IDCR_tag { + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union EQADC_FISR_tag { + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t TCCF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB0:4; + uint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB1:4; + uint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:4; + uint32_t ECBNI:1; + uint32_t LCFTSSI:4; + uint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11; + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t MDT:3; + uint32_t:4; + uint32_t BR:4; + } B; + } SSICR; /* SSI Control Register */ + + union { + uint32_t R; + struct { + uint32_t RDV:1; + uint32_t:5; + uint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register */ + + uint32_t eqadc_reserved12[17]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved13[12]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; + +/* Message Formats for On-Chip ADC Operation + */ +union EQADC_CONVERSION_COMMAND_tag { + uint32_t R; + struct { + uint32_t EOQ:1; + uint32_t PAUSE:1; + uint32_t:3; + uint32_t EB:1; + uint32_t BN:1; + uint32_t CAL:1; + uint32_t MESSAGE_TAG:4; + uint32_t LST:2; + uint32_t TSR:1; + uint32_t FMT:1; + uint32_t CHANNEL_NUMBER:8; + uint32_t:8; + } B; +}; /* Conversion command */ + +union EQADC_WRITE_CONFIGURATION_COMMAND_tag { + uint32_t R; + struct { + uint32_t EOQ:1; + uint32_t PAUSE:1; + uint32_t:3; + uint32_t EB:1; + uint32_t BN:1; + uint32_t RW:1; + uint32_t VALUE:16; + uint32_t ADDR:8; + } B; +}; /* Write configuration command */ + +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t DOZE:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t MTOE:1; + uint32_t:1; + uint32_t MTOCNT:6; + uint32_t:4; + uint32_t TXSS:1; + uint32_t TPOL:1; + uint32_t TRRE:1; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t SCISDOZ:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t:2; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t R8:1; + uint16_t T8:1; + uint16_t:6; + uint8_t D; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:3; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:7; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t LDBG:1; + uint32_t DSF:1; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:7; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint32_t R; + } LTR; /* LIN Transmit Register */ + + union { + uint32_t R; + } LRR; /* LIN Recieve Register */ + + union { + uint32_t R; + } LPR; /* LIN CRC Polynom Register */ + + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN2_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t:1; + + uint32_t MDISACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t:12; + + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + + uint32_t:4; + + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + int32_t FLEXCAN_reserved00; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + + uint32_t:2; + + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t flexcan2_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + }; + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x10000 +#define SRAM_END 0x4000FFFF + +#define FLASH_START 0x0 +#define FLASH_SIZE 0x200000 +#define FLASH_END 0x1FFFFF + +/* Define instances of modules */ +#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*(volatile struct EBI_tag *) 0xC3F84000) +#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000) +#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC8BFC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000) +#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000) + +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000) + +#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5554_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h new file mode 100644 index 0000000000..41ad83729a --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc556x.h @@ -0,0 +1,4563 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */ +/* VERSION: 1.5 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC5567. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 1.0 G. Emerson 03/Jan/06 Initial version. */ +/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */ +/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */ +/* Add Flexcan bits WRNEN, SRXDIS, */ +/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */ +/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */ +/* to DPB to align with documentation. */ +/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */ +/* alternate configuration. */ +/* INTC, correction to the number of PSR */ +/* registers. */ +/* Updates to bitfield sizes in MBSSUTR, */ +/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */ +/* changed to SEL & RFRFCFR, FNUM changed */ +/* to SEL to align with documentation. */ +/* Various register/ bitfield updates to */ +/* correct errors (MCR, TMODE bit removed.*/ +/* PADR register removed. PIER1, DRDIE bit*/ +/* removed & PIFR1, DRDIF removed. PCR1, */ +/* Filter bypass bit removed). */ +/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */ +/* */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC5567_H_ +#define _MPC5567_H_ + +#ifndef ASM + +#include <stdint.h> + +#include <mpc55xx/regs-edma.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : PBRIDGE_A Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_A_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t MBW4:1; /* FEC */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + + uint32_t:4; + + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_a_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:28; + } B; + } PACR0; + + uint32_t pbridge_a_reserved3[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + + uint32_t BW0:1; /* EMIOS */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t:28; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:12; + } B; + } OPACR2; + + }; + +/****************************************************************************/ +/* MODULE : PBRIDGE_B Peripheral Bridge */ +/****************************************************************************/ + struct PBRIDGE_B_tag { + union { + uint32_t R; + struct { + uint32_t MBW0:1; + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + + uint32_t MBW4:1; /* FEC */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + + uint32_t:4; + + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + + uint32_t:4; + } B; + } MPCR; /* Master Privilege Control Register */ + + uint32_t pbridge_b_reserved2[7]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t:24; + } B; + } PACR0; + + uint32_t pbridge_b_reserved3; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t BW3:1; /* FEC */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + + uint32_t:16; + + } B; + } PACR2; + + uint32_t pbridge_b_reserved4[5]; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:12; + + uint32_t:4; + + uint32_t BW5:1; /* DSPI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t BW6:1; + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR0; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t BW4:1; + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t BW5:1; /* ESCI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + + uint32_t:8; + } B; + } OPACR1; + + union { + uint32_t R; + struct { + uint32_t BW0:1; + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t BW1:1; /* CAN_B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + + uint32_t BW2:1; + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + + uint32_t BW3:1; /* CAN_D */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + + uint32_t BW4:1; /* CAN_E */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + + uint32_t:12; + } B; + } OPACR2; + + union { + uint32_t R; + struct { + + uint32_t BW0:1; /* FLEXRAY */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + + uint32_t:24; + uint32_t BW7:1; + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR3; + + }; +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union FMPLL_SYNCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t PREDIV:3; + uint32_t MFD:5; + uint32_t:1; + uint32_t RFD:3; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t DISCLK:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t RATE:1; + uint32_t DEPTH:2; + uint32_t EXP:10; + } B; + } SYNCR; + + union FMPLL_SYNSR_tag { + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + }; +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + struct EBI_CS_tag { + union { /* Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:4; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:2; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_CAL_CS_tag { + union { /* Calibration Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:4; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:2; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Calibration Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_tag { + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZEEN:1; + uint32_t SIZE:2; + uint32_t:8; + uint32_t ACGE:1; + uint32_t EXTM:1; + uint32_t EARB:1; + uint32_t EARP:2; + uint32_t:4; + uint32_t MDIS:1; + uint32_t:5; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved1; + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + struct EBI_CS_tag CS[4]; + +/* Calibration registers */ + uint32_t EBI_reserved2[4]; + struct EBI_CAL_CS_tag CAL_CS[4]; + + }; +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:4; + uint32_t SIZE:4; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t BBEPE:1; + uint32_t EPE:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + + uint32_t:2; + + uint32_t STOP:1; + uint32_t:1; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* LML Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t MLOCK:4; + uint32_t LLOCK:16; + } B; + } LMLR; + + union HLR_tag { /* HL Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:3; + uint32_t HBLOCK:28; + } B; + } HLR; + + union SLMLR_tag { /* SLML Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t SMLOCK:4; + uint32_t SLLOCK:16; + } B; + } SLMLR; + + union { /* LMS Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t MSEL:4; + uint32_t LSEL:16; + } B; + } LMSR; + + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t HBSEL:28; + } B; + } HSR; + + union { + uint32_t R; + struct { + uint32_t:10; + uint32_t ADDR:19; + uint32_t:3; + } B; + } AR; + + union { + uint32_t R; + struct { + + uint32_t:9; + uint32_t M6PFE:1; /* Flexray */ + uint32_t:1; + + uint32_t M4PFE:1; /* FEC */ + + uint32_t M3PFE:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + + uint32_t DPFEN:2; + uint32_t IPFEN:2; + + uint32_t PFLIM:3; + uint32_t BFEN:1; + } B; + } BIUCR; + + union { + uint32_t R; + struct { + + uint32_t:18; + uint32_t M6AP:2; /* Flexray */ + uint32_t:2; + + uint32_t M4AP:2; /* FEC */ + + uint32_t M3AP:2; + uint32_t M2AP:2; + uint32_t M1AP:2; + uint32_t M0AP:2; + } B; + } BIUAPR; + }; +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + int32_t SIU_reserved0; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t MASKNUM:16; + } B; + } MIDR; + int32_t SIU_reserved00; + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t SERF:1; + uint32_t WKPCFG:1; + uint32_t:12; + uint32_t BOOTCFG:2; + uint32_t RGF:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t SER:1; + uint32_t:14; + uint32_t CRE:1; + uint32_t:15; + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + int32_t SIU_reserved1[3]; + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t PA:3; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[512]; + + int16_t SIU_reserved_0[224]; + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[256]; + + int32_t SIU_reserved_3[64]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[256]; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t TSEL5:2; + uint32_t TSEL4:2; + uint32_t TSEL3:2; + uint32_t TSEL2:2; + uint32_t TSEL1:2; + uint32_t TSEL0:2; + uint32_t:20; + } B; + } ETISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } EIISR; + + union { /* IMUX Register */ + uint32_t R; + struct { + uint32_t SINSELA:2; + uint32_t SSSELA:2; + uint32_t SCKSELA:2; + uint32_t TRIGSELA:2; + uint32_t SINSELB:2; + uint32_t SSSELB:2; + uint32_t SCKSELB:2; + uint32_t TRIGSELB:2; + uint32_t SINSELC:2; + uint32_t SSSELC:2; + uint32_t SCKSELC:2; + uint32_t TRIGSELC:2; + uint32_t SINSELD:2; + uint32_t SSSELD:2; + uint32_t SCKSELD:2; + uint32_t TRIGSELD:2; + } B; + } DISR; + + int32_t SIU_reserved2[29]; + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t ENGDIV:6; + uint32_t:4; + uint32_t EBTS:1; + uint32_t:1; + uint32_t EBDF:2; + } B; + } ECCR; + + union { + uint32_t R; + } CARH; + + union { + uint32_t R; + } CARL; + + union { + uint32_t R; + } CBRH; + + union { + uint32_t R; + } CBRL; + + }; +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t ETB:1; + uint32_t GPREN:1; + uint32_t:6; + uint32_t SRV:4; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t:8; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + uint32_t emios_reserved[5]; + + struct EMIOS_CH_tag { + union { + uint32_t R; /* Channel A Data Register */ + } CADR; + + union { + uint32_t R; /* Channel B Data Register */ + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + uint32_t R; /* Alternate Channel A Data Register */ + } ALTCADR; + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; +/****************************************************************************/ +/* MODULE :ETPU */ +/****************************************************************************/ + +/***************************Configuration Registers**************************/ + + struct ETPU_tag { + union { /* MODULE CONFIGURATION REGISTER */ + uint32_t R; + struct { + uint32_t GEC:1; /* Global Exception Clear */ + uint32_t:3; + uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ + + uint32_t:1; /* For single ETPU implementations */ + + uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ + + uint32_t:1; /* For single ETPU implementations */ + + uint32_t:3; + uint32_t SCMSIZE:5; /* Shared Code Memory size */ + uint32_t:5; + uint32_t SCMMISF:1; /* SCM MISC Flag */ + uint32_t SCMMISEN:1; /* SCM MISC Enable */ + uint32_t:2; + uint32_t VIS:1; /* SCM Visability */ + uint32_t:5; + uint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; + + union { /* COHERENT DUAL-PARAMETER CONTROL */ + uint32_t R; + struct { + uint32_t STS:1; /* Start Status bit */ + uint32_t CTBASE:5; /* Channel Transfer Base */ + uint32_t PBASE:10; /* Parameter Buffer Base Address */ + uint32_t PWIDTH:1; /* Parameter Width */ + uint32_t PARAM0:7; /* Channel Parameter 0 */ + uint32_t WR:1; + uint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; + + uint32_t etpu_reserved1; + + union { /* MISC Compare Register */ + uint32_t R; + } MISCCMPR; + + union { /* SCM off-range Date Register */ + uint32_t R; + } SCMOFFDATAR; + + union { /* ETPU_A Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:4; + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:9; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; + uint32_t etpu_reserved3; /* For single ETPU implementations */ + + uint32_t etpu_reserved4; + + union { /* ETPU_A Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t:1; + uint32_t AM:1; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t:6; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; + + union { /* ETPU_A TCR1 Visibility Register */ + uint32_t R; + } TB1R_A; + + union { /* ETPU_A TCR2 Visibility Register */ + uint32_t R; + } TB2R_A; + + union { /* ETPU_A STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; + + uint32_t etpu_reserved5[4]; + uint32_t etpu_reserved6[4]; /* For single ETPU implementations */ + + uint32_t etpu_reserved7[108]; + +/*****************************Status and Control Registers**************************/ + + union { /* ETPU_A Channel Interrut Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrut Status */ + uint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; + uint32_t etpu_reserved8; /* For single ETPU implementations */ + + uint32_t etpu_reserved9[2]; + + union { /* ETPU_A Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; + uint32_t etpu_reserved10; /* For single ETPU implementations */ + + uint32_t etpu_reserved11[2]; + + union { /* ETPU_A Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; + uint32_t etpu_reserved12; /* For single ETPU implementations */ + + uint32_t etpu_reserved13[2]; + + union { /* ETPU_A Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; + uint32_t etpu_reserved14; /* For single ETPU implementations */ + + uint32_t etpu_reserved15[2]; + + union { /* ETPU_A Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; + uint32_t etpu_reserved16; /* For single ETPU implementations */ + + uint32_t etpu_reserved17[2]; + + union { /* ETPU_A Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; + uint32_t etpu_reserved19; /* For single ETPU implementations */ + + uint32_t etpu_reserved20[10]; + union { /* ETPU_A Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_A; + uint32_t etpu_reserved22; /* For single ETPU implementations */ + + uint32_t etpu_reserved20a[2]; + + union { /* ETPU_A Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_A; + uint32_t etpu_reserved22a; /* For single ETPU implementations */ + + uint32_t etpu_reserved23[90]; + +/*****************************Channels********************************/ + + struct { + union { + uint32_t R; /* Channel Configuration Register */ + struct { + uint32_t CIE:1; /* Channel Interruput Enable */ + uint32_t DTRE:1; /* Data Transfer Request Enable */ + uint32_t CPR:2; /* Channel Priority */ + uint32_t:3; + uint32_t ETCS:1; /* Entry Table Condition Select */ + uint32_t:3; + uint32_t CFS:5; /* Channel Function Select */ + uint32_t ODIS:1; /* Output disable */ + uint32_t OPOL:1; /* output polarity */ + uint32_t:3; + uint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; + union { + uint32_t R; /* Channel Status Control Register */ + struct { + uint32_t CIS:1; /* Channel Interruput Status */ + uint32_t CIOS:1; /* Channel Interruput Overflow Status */ + uint32_t:6; + uint32_t DTRS:1; /* Data Transfer Status */ + uint32_t DTROS:1; /* Data Transfer Overflow Status */ + uint32_t:6; + uint32_t IPS:1; /* Input Pin State */ + uint32_t OPS:1; /* Output Pin State */ + uint32_t OBE:1; /* Output Buffer Enable */ + uint32_t:11; + uint32_t FM1:1; /* Function mode */ + uint32_t FM0:1; /* Function mode */ + } B; + } SCR; + union { + uint32_t R; /* Channel Host Service Request Register */ + struct { + uint32_t:29; /* Host Service Request */ + uint32_t HSR:3; + } B; + } HSRR; + uint32_t etpu_reserved23; + } CHAN[127]; + + }; +/****************************************************************************/ +/* MODULE : XBAR CrossBar */ +/****************************************************************************/ + struct XBAR_tag { + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR0; /* Master Priority Register for Slave Port 0 */ + + uint32_t xbar_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; /* General Purpose Control Register for Slave Port 0 */ + + uint32_t xbar_reserved2[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR1; /* Master Priority Register for Slave Port 1 */ + + uint32_t xbar_reserved3[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; /* General Purpose Control Register for Slave Port 1 */ + + uint32_t xbar_reserved4[123]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR3; /* Master Priority Register for Slave Port 3 */ + + uint32_t xbar_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR3; /* General Purpose Control Register for Slave Port 3 */ + uint32_t xbar_reserved6[187]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR6; /* Master Priority Register for Slave Port 6 */ + + uint32_t xbar_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; /* General Purpose Control Register for Slave Port 6 */ + + uint32_t xbar_reserved8[59]; + + union { + uint32_t R; + struct { + uint32_t:4; + + uint32_t:1; + uint32_t MSTR6:3; /* FLEXRAY */ + + uint32_t:4; + + uint32_t:4; + + uint32_t:1; + uint32_t MSTR3:3; /* FEC */ + + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:3; + } B; + } MPR7; /* Master Priority Register for Slave Port 7 */ + + uint32_t xbar_reserved9[3]; + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ + + }; +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + + uint32_t ecsm_reserved1[5]; + + uint16_t ecsm_reserved2; + + union { + uint16_t R; + } SWTCR; //Software Watchdog Timer Control + + uint8_t ecsm_reserved3[3]; + + union { + uint8_t R; + } SWTSR; //SWT Service Register + + uint8_t ecsm_reserved4[3]; + + union { + uint8_t R; + } SWTIR; //SWT Interrupt Register + + uint32_t ecsm_reserved5a[1]; + + union { + uint32_t R; + struct { + uint32_t FSBCR0:1; + uint32_t FSBCR1:1; + uint32_t FSBCR2:1; + uint32_t FSBCR3:1; + uint32_t FSBCR4:1; + uint32_t FSBCR5:1; + uint32_t FSBCR6:1; + uint32_t FSBCR7:1; + uint32_t RBEN:1; + uint32_t WBEN:1; + uint32_t ACCERR:1; + uint32_t:21; + } B; + } FSBMCR; /* FEC System Bus Master Control Register */ + + uint32_t ecsm_reserved5c[6]; + + uint8_t ecsm_reserved6[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; //ECC Configuration Register + + uint8_t mcm_reserved8[3]; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; //ECC Status Register + + uint16_t ecsm_reserved9; + + union { + uint16_t R; + struct { + uint16_t:6; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; //ECC Error Generation Register + + uint32_t ecsm_reserved10; + + union { + uint32_t R; + struct { + uint32_t FEAR:32; + } B; + } FEAR; //Flash ECC Address Register + + uint16_t ecsm_reserved11; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; //Flash ECC Master Register + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } FEAT; //Flash ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t FEDH:32; + } B; + } FEDRH; //Flash ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t FEDL:32; + } B; + } FEDRL; //Flash ECC Data Low Register + + union { + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; //RAM ECC Address + + uint8_t ecsm_reserved12[2]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; //RAM ECC Master + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } REAT; // RAM ECC Attributes Register + + union { + uint32_t R; + struct { + uint32_t REDH:32; + } B; + } REDRH; //RAM ECC Data High Register + + union { + uint32_t R; + struct { + uint32_t REDL:32; + } B; + } REDRL; //RAMECC Data Low Register + + }; +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:26; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Current Priority Register */ + + uint32_t intc_reserved1; + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Interrupt Acknowledge Register */ + + uint32_t intc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* End of Interrupt Register */ + + uint32_t intc_reserved3; + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved4[6]; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PRI:4; + } B; + } PSR[358]; /* Software Set/Clear Interrupt Register */ + + }; +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t ESSIE:2; + uint32_t:1; + uint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register */ + + int32_t EQADC_reserved00; + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t CFPUSH:32; + } B; + } CFPR[6]; /* CFIFO Push Registers */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RFPOP:16; + } B; + } RFPR[6]; /* Result FIFO Pop Registers */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t:4; + } B; + } CFCR[6]; /* CFIFO Control Registers */ + + uint32_t eqadc_reserved5; + + union { + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers */ + + uint32_t eqadc_reserved6; + + union { + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t TCCF:11; + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers */ + + uint32_t eqadc_reserved9; + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB0:4; + uint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:5; + uint32_t LCFTCB1:4; + uint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:4; + uint32_t ECBNI:1; + uint32_t LCFTSSI:4; + uint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 */ + + union { + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eqadc_reserved11; + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t MDT:3; + uint32_t:4; + uint32_t BR:4; + } B; + } SSICR; /* SSI Control Register */ + + union { + uint32_t R; + struct { + uint32_t RDV:1; + uint32_t:5; + uint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register */ + + uint32_t eqadc_reserved12[17]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved13[12]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } R[4]; + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t DOZE:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t MTOE:1; + uint32_t:1; + uint32_t MTOCNT:6; + uint32_t:4; + uint32_t TXSS:1; + uint32_t TPOL:1; + uint32_t TRRE:1; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; + } B; + } DDR; /* DSI deserialization Data Register */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t SCISDOZ:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t:2; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t R8:1; + uint16_t T8:1; + uint16_t:6; + uint8_t D; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:3; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:7; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t LDBG:1; + uint32_t DSF:1; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:7; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint32_t R; + } LTR; /* LIN Transmit Register */ + + union { + uint32_t R; + } LRR; /* LIN Recieve Register */ + + union { + uint32_t R; + } LPR; /* LIN CRC Polynom Register */ + + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN2_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t WRNEN:1; + + uint32_t MDISACK:1; + uint32_t:1; + uint32_t:1; + + uint32_t SRXDIS:1; + uint32_t MBFEN:1; + uint32_t:10; + + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CR; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + int32_t FLEXCAN_reserved00; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMRH; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMRL; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFRH; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFRL; /* Interruput Flag Register */ + + uint32_t flexcan2_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + uint32_t flexcan2_reserved3[256]; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t MI:29; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; +/****************************************************************************/ +/* MODULE : FEC */ +/****************************************************************************/ + struct FEC_tag { + + uint32_t fec_reserved_start[0x1]; + + union { + uint32_t R; + struct { + uint32_t HBERR:1; + uint32_t BABR:1; + uint32_t BABT:1; + uint32_t GRA:1; + uint32_t TXF:1; + uint32_t TXB:1; + uint32_t RXF:1; + uint32_t RXB:1; + uint32_t MII:1; + uint32_t EBERR:1; + uint32_t LC:1; + uint32_t RL:1; + uint32_t UN:1; + uint32_t:19; + } B; + } EIR; /* Interrupt Event Register */ + + union { + uint32_t R; + struct { + uint32_t HBERRM:1; + uint32_t BABRM:1; + uint32_t BABTM:1; + uint32_t GRAM:1; + uint32_t TXFM:1; + uint32_t TXBM:1; + uint32_t RXFM:1; + uint32_t RXBM:1; + uint32_t MIIM:1; + uint32_t EBERRM:1; + uint32_t LCM:1; + uint32_t RLM:1; + uint32_t UNM:1; + uint32_t:19; + } B; + } EIMR; /* Interrupt Mask Register */ + + uint32_t fec_reserved_eimr; + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t R_DES_ACTIVE:1; + uint32_t:24; + } B; + } RDAR; /* Receive Descriptor Active Register */ + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t X_DES_ACTIVE:1; + uint32_t:24; + } B; + } TDAR; /* Transmit Descriptor Active Register */ + + uint32_t fec_reserved_tdar[3]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t ETHER_EN:1; + uint32_t RESET:1; + } B; + } ECR; /* Ethernet Control Register */ + + uint32_t fec_reserved_ecr[6]; + + union { + uint32_t R; + struct { + uint32_t ST:2; + uint32_t CP:2; + uint32_t PA:5; + uint32_t RA:5; + uint32_t TA:2; + uint32_t DATA:16; + } B; + } MDATA; /* MII Data Register */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t DIS_PREAMBLE:1; + uint32_t MII_SPEED:6; + uint32_t:1; + } B; + } MSCR; /* MII Speed Control Register */ + + uint32_t fec_reserved_mscr[7]; + + union { + uint32_t R; + struct { + uint32_t MIB_DISABLE:1; + uint32_t MIB_IDLE:1; + uint32_t:30; + } B; + } MIBC; /* MIB Control Register */ + + uint32_t fec_reserved_mibc[7]; + + union { + uint32_t R; + struct { + uint32_t:5; + uint32_t MAX_FL:11; + uint32_t:10; + uint32_t FCE:1; + uint32_t BC_REJ:1; + uint32_t PROM:1; + uint32_t MII_MODE:1; + uint32_t DRT:1; + uint32_t LOOP:1; + } B; + } RCR; /* Receive Control Register */ + + uint32_t fec_reserved_rcr[15]; + + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t RFC_PAUSE:1; + uint32_t TFC_PAUSE:1; + uint32_t FDEN:1; + uint32_t HBC:1; + uint32_t GTS:1; + } B; + } TCR; /* Transmit Control Register */ + + uint32_t fec_reserved_tcr[7]; + + union { + uint32_t R; + struct { + uint32_t PADDR1:32; + } B; + } PALR; /* Physical Address Low Register */ + + union { + uint32_t R; + struct { + uint32_t PADDR2:16; + uint32_t TYPE:16; + } B; + } PAUR; /* Physical Address High + Type Register */ + + union { + uint32_t R; + struct { + uint32_t OPCODE:16; + uint32_t PAUSE_DUR:16; + } B; + } OPD; /* Opcode/Pause Duration Register */ + + uint32_t fec_reserved_opd[10]; + + union { + uint32_t R; + struct { + uint32_t IADDR1:32; + } B; + } IAUR; /* Descriptor Individual Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t IADDR2:32; + } B; + } IALR; /* Descriptor Individual Lower Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR1:32; + } B; + } GAUR; /* Descriptor Group Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR2:32; + } B; + } GALR; /* Descriptor Group Lower Address Register */ + + uint32_t fec_reserved_galr[7]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t X_WMRK:2; + } B; + } TFWR; /* FIFO Transmit FIFO Watermark Register */ + + uint32_t fec_reserved_tfwr; + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_BOUND:8; + uint32_t:2; + } B; + } FRBR; /* FIFO Receive Bound Register */ + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_FSTART:8; + uint32_t:2; + } B; + } FRSR; /* FIFO Receive Start Register */ + + uint32_t fec_reserved_frsr[11]; + + union { + uint32_t R; + struct { + uint32_t R_DES_START:30; + uint32_t:2; + } B; + } ERDSR; /* Receive Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t X_DES_START:30; + uint32_t:2; + } B; + } ETDSR; /* Transmit Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t R_BUF_SIZE:7; + uint32_t:4; + } B; + } EMRBR; /* Receive Buffer Size Register */ + + uint32_t fec_reserved_emrbr[29]; + + union { + uint32_t R; + } RMON_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_T_PACKETS; /* RMON Tx packet count */ + + union { + uint32_t R; + } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */ + + union { + uint32_t R; + } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */ + + union { + uint32_t R; + } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_COL; /* RMON Tx collision count */ + + union { + uint32_t R; + } RMON_T_P64; /* RMON Tx 64 byte packets */ + + union { + uint32_t R; + } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_T_OCTETS; /* RMON Tx Octets */ + + union { + uint32_t R; + } IEEE_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_T_FRAME_OK; /* Frames Transmitted OK */ + + union { + uint32_t R; + } IEEE_T_1COL; /* Frames Transmitted with Single Collision */ + + union { + uint32_t R; + } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */ + + union { + uint32_t R; + } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */ + + union { + uint32_t R; + } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */ + + union { + uint32_t R; + } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */ + + union { + uint32_t R; + } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */ + + union { + uint32_t R; + } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */ + + union { + uint32_t R; + } IEEE_T_SQE; /* Frames Transmitted with SQE Error */ + + union { + uint32_t R; + } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */ + + union { + uint32_t R; + } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */ + + uint32_t fec_reserved_rmon_t_octets_ok[2]; + + union { + uint32_t R; + } RMON_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_R_PACKETS; /* RMON Rx packet count */ + + union { + uint32_t R; + } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */ + + union { + uint32_t R; + } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */ + + union { + uint32_t R; + } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */ + + uint32_t fec_reserved_rmon_r_jab; + + union { + uint32_t R; + } RMON_R_P64; /* RMON Rx 64 byte packets */ + + union { + uint32_t R; + } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_R_OCTETS; /* RMON Rx Octets */ + + union { + uint32_t R; + } IEEE_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_R_FRAME_OK; /* Frames Received OK */ + + union { + uint32_t R; + } IEEE_R_CRC; /* Frames Received with CRC Error */ + + union { + uint32_t R; + } IEEE_R_ALIGN; /* Frames Received with Alignment Error */ + + union { + uint32_t R; + } IEEE_R_MACERR; /* Receive Fifo Overflow count */ + + union { + uint32_t R; + } IEEE_R_FDXFC; /* Flow Control Pause frames received */ + + union { + uint32_t R; + } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */ + + }; +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uSTBPCR { + uint16_t R; + struct { + uint16_t:12; + uint16_t STB3EN:1; /* strobe port enable */ + uint16_t STB2EN:1; /* strobe port enable */ + uint16_t STB1EN:1; /* strobe port enable */ + uint16_t STB0EN:1; /* strobe port enable */ + } B; + } STBPCR_t; + + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:1; + uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ + uint16_t:1; + uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:1; + uint16_t TBIVEC:7; /* transmit buffer interrupt vector */ + uint16_t:1; + uint16_t RBIVEC:7; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:4; + uint16_t RSBIDX:8; /* receive shadow buffer index */ + } B; + } RSBIR_t; + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + union { + uint16_t R; + struct { + uint16_t:8; + uint16_t MBIDX:8; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved3a[1]; /*10 */ + volatile PDAR_t PDAR; /*PE data register *//*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + uint16_t reserved3[1]; /*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved2[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x14000 +#define SRAM_END 0x40013FFF + +#define FLASH_START 0x0 +#define FLASH_SIZE 0x200000 +#define FLASH_END 0x1FFFFF + +/* Define instances of modules */ +#define PBRIDGE_A (*(volatile struct PBRIDGE_A_tag *) 0xC3F00000) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*(volatile struct EBI_tag *) 0xC3F84000) +#define FLASH (*(volatile struct FLASH_tag *) 0xC3F88000) +#define SIU (*(volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*(volatile struct EMIOS_tag *) 0xC3FA0000) +#define ETPU (*(volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC89FC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define PBRIDGE_B (*(volatile struct PBRIDGE_B_tag *) 0xFFF00000) +#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*(volatile struct EQADC_tag *) 0xFFF80000) + +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFB4000) + +#define CAN_A (*(volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*(volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*(volatile struct FLEXCAN2_tag *) 0xFFFC8000) +#define CAN_D (*(volatile struct FLEXCAN2_tag *) 0xFFFCC000) +#define CAN_E (*(volatile struct FLEXCAN2_tag *) 0xFFFD0000) + +#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000) + +#define FR (*(volatile struct FR_tag *) 0xFFFE0000) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5567_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h b/bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h new file mode 100644 index 0000000000..61217ac656 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc564xL.h @@ -0,0 +1,20666 @@ +/* + * Modifications of the original file provided by Freescale Semiconductor and + * ST Microelectronics are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/****************************************************************************\ + * PROJECT : MPC5643L + * FILE : mpc5643l.h + * + * DESCRIPTION : This is the header file describing the register + * set for the named projects. + * + * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics + * + * VERSION : 1.04 + * RELEASE DATE : Tue Dec 1 2009 + * CREATION DATE : Thu Oct 8 13:53:51 CEST 2009 + * AUTHOR : generated from IP-XACT database + * HISTORY : Preliminary release. +\****************************************************************************/ + +/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */ + +/****************************************************************************\ + * Example instantiation and use: + * + * <MODULE>.<REGISTER>.B.<BIT> = 1; + * <MODULE>.<REGISTER>.R = 0x10000000; + * +\****************************************************************************/ + +/* + * LICENSE: + * Copyright (c) 2006 Freescale Semiconductor + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice + * shall be included in all copies or substantial portions + * of the Software. + * + * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _leopard_H_ /* prevents multiple inclusions of this file */ +#define _leopard_H_ + +#ifndef ASM + +#include <stdint.h> + +#include <mpc55xx/regs-edma.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +//#define USE_FIELD_ALIASES_CFLASH +//#define USE_FIELD_ALIASES_SIUL +//#define USE_FIELD_ALIASES_SSCM +//#define USE_FIELD_ALIASES_ME +//#define USE_FIELD_ALIASES_RGM +//#define USE_FIELD_ALIASES_ADC +//#define USE_FIELD_ALIASES_CTU +//#define USE_FIELD_ALIASES_mcTIMER +//#define USE_FIELD_ALIASES_mcPWM +//#define USE_FIELD_ALIASES_LINFLEX +//#define USE_FIELD_ALIASES_SPP_MCM +#define USE_FIELD_ALIASES_INTC +#define USE_FIELD_ALIASES_DSPI +//#define USE_FIELD_ALIASES_FLEXCAN +//#define USE_FIELD_ALIASES_FR +//#define USE_FIELD_ALIASES_CMU +//#define USE_FIELD_ALIASES_PLLD +//#define USE_FIELD_ALIASES_SPP_DMA2 + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x20000 +#define SRAM_END 0x4001FFFF + +#define FLASH_START 0x0 +#define FLASH_SIZE 0xC0000 +#define FLASH_END 0xBFFFF + +/****************************************************************/ +/* */ +/* Global definitions and aliases */ +/* */ +/****************************************************************/ + +/* + Platform blocks that are only accessible by the second core (core 1) when + the device is in DPM mode. The block definition is equivalent to the one + for the first core (core 0) and reuses the related block structure. + + NOTE: the <block_name>_1 defines are the preferred method for programming + */ +#define PBRIDGE_1 (*(volatile PBRIDGE_tag*) 0x8FF00000UL) +#define MAX_1 (*(volatile MAX_tag*) 0x8FF04000UL) +#define MPU_1 (*(volatile MPU_tag*) 0x8FF10000UL) +#define SEMA4_1 (*(volatile SEMA4_tag*) 0x8FF24000UL) +#define SWT_1 (*(volatile SWT_tag*) 0x8FF38000UL) +#define STM_1 (*(volatile STM_tag*) 0x8FF3C000UL) +#define SPP_MCM_1 (*(volatile SPP_MCM_tag*) 0x8FF40000UL) +#define SPP_DMA2_1 (*(volatile SPP_DMA2_tag*) 0x8FF44000UL) +#define INTC_1 (*(volatile INTC_tag*) 0x8FF48000UL) + +/* + Platform blocks that are only accessible by the second core (core 1) when + the device is in DPM mode. The block definition is equivalent to the one + for the first core (core 0) and reuses the related block structure. + + NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for + programming the corresponding blocks for new code instead. + */ +#define PBRIDGE_DPM PBRIDGE_1 +#define MAX_DPM MAX_1 +#define MPU_DPM MPU_1 +#define SEMA4_DPM SEMA4_1 +#define SWT_DPM SWT_1 +#define STM_DPM STM_1 +#define SPP_MCM_DPM SPP_MCM_1 +#define SPP_DMA2_DPM SPP_DMA2_1 +#define INTC_DPM INTC_1 + +/* Aliases for Pictus Module names */ +#define CAN_0 FLEXCAN_A +#define CAN_1 FLEXCAN_B +#define CTU_0 CTU +#define DFLASH CRC +#define DMAMUX DMA_CH_MUX +#define DSPI_0 DSPI_A +#define DSPI_1 DSPI_B +#define DSPI_2 DSPI_C +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define ETIMER_0 mcTIMER0 +#define ETIMER_1 mcTIMER1 +#define FLEXPWM_0 mcPWM_A +#define FLEXPWM_1 mcPWM_B +#define LINFLEX_0 LINFLEX0 +#define LINFLEX_1 LINFLEX1 +#define MCM_ SPP_MCM +#define PIT PIT_RTI +#define SIU SIUL +#define WKUP WKPU +#define ADC_0 ADC0 +#define ADC_1 ADC1 + +/* Other Aliases */ +#define AIPS_DPM PBRIDGE_1 +#define AIPS_1 PBRIDGE_1 +#define AIPS PBRIDGE + +/****************************************************************/ +/* */ +/* Module: CFLASH_SHADOW */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers NVPWD... */ + + typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + uint32_t R; + struct { + uint32_t PWD:32; /* PassWorD */ + } B; + } CFLASH_SHADOW_NVPWD_32B_tag; + + + /* Register layout for all registers NVSCI... */ + + typedef union { /* NVSCI - Non Volatile System Censoring Information Register */ + uint32_t R; + struct { + uint32_t SC:16; /* Serial Censorship Control Word */ + uint32_t CW:16; /* Censorship Control Word */ + } B; + } CFLASH_SHADOW_NVSCI_32B_tag; + + typedef union { /* Non Volatile LML Default Value */ + uint32_t R; + } CFLASH_SHADOW_NVLML_32B_tag; + + typedef union { /* Non Volatile HBL Default Value */ + uint32_t R; + } CFLASH_SHADOW_NVHBL_32B_tag; + + typedef union { /* Non Volatile SLL Default Value */ + uint32_t R; + } CFLASH_SHADOW_NVSLL_32B_tag; + + + /* Register layout for all registers NVBIU... */ + + typedef union { /* Non Volatile Bus Interface Unit Register */ + uint32_t R; + struct { + uint32_t BI:32; /* Bus interface Unit */ + } B; + } CFLASH_SHADOW_NVBIU_32B_tag; + + typedef union { /* NVUSRO - Non Volatile USeR Options Register */ + uint32_t R; + struct { + uint32_t UO:32; /* User Options */ + } B; + } CFLASH_SHADOW_NVUSRO_32B_tag; + + + typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag { + + /* Non Volatile Bus Interface Unit Register */ + CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */ + int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4]; + + } CFLASH_SHADOW_BIU_DEFAULTS_tag; + + + typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */ + int8_t CFLASH_SHADOW_reserved_0000_C[15832]; + union { + /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */ + + struct { + /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */ + CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */ + }; + + }; + union { + /* NVSCI - Non Volatile System Censoring Information Register */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */ + + struct { + /* NVSCI - Non Volatile System Censoring Information Register */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */ + CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */ + }; + + }; + /* Non Volatile LML Default Value */ + CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DEC[4]; + /* Non Volatile HBL Default Value */ + CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DF4[4]; + /* Non Volatile SLL Default Value */ + CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3DFC_C[4]; + union { + /* Register set BIU_DEFAULTS */ + CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */ + + struct { + /* Non Volatile Bus Interface Unit Register */ + CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E04_I1[4]; + CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E0C_I1[4]; + CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */ + int8_t CFLASH_SHADOW_reserved_3E14_E1[4]; + }; + + }; + /* NVUSRO - Non Volatile USeR Options Register */ + CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */ + } CFLASH_SHADOW_tag; + + +#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL) + + + +/****************************************************************/ +/* */ +/* Module: CFLASH */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZE:3; /* Array Space Size */ + uint32_t:1; + uint32_t LAS:3; /* Low Address Space */ + uint32_t:3; + uint32_t MAS:1; /* Mid Address Space Configuration */ + uint32_t EER:1; /* ECC Event Error */ + uint32_t RWE:1; /* Read-while-Write Event Error */ + uint32_t SBC:1; /* Single Bit Correction */ + uint32_t:1; + uint32_t PEAS:1; /* Program/Erase Access Space */ + uint32_t DONE:1; /* modify operation DONE */ + uint32_t PEG:1; /* Program/Erase Good */ + uint32_t:4; + uint32_t PGM:1; /* Program Bit */ + uint32_t PSUS:1; /* Program Suspend */ + uint32_t ERS:1; /* Erase Bit */ + uint32_t ESUS:1; /* Erase Suspend */ + uint32_t EHV:1; /* Enable High Voltage */ + } B; + } CFLASH_MCR_32B_tag; + + typedef union { /* LML - Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t LME:1; /* Low/Mid Address Space Block Enable */ + uint32_t:10; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t SLOCK:1; /* Shadow Address Space Block Lock */ +#else + uint32_t TSLK:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t MLOCK:2; /* Mid Address Space Block Lock */ +#else + uint32_t MLK:2; /* deprecated name - please avoid */ +#endif + uint32_t:6; + uint32_t LLOCK:10; /* Low Address Space Block Lock */ + } B; + } CFLASH_LML_32B_tag; + + typedef union { /* HBL - High Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t HBE:1; /* High Address Space Block Enable */ + uint32_t:25; + uint32_t HLOCK:6; /* High Address Space Block Lock */ + } B; + } CFLASH_HBL_32B_tag; + + typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */ + uint32_t:10; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */ +#else + uint32_t STSLK:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */ +#else + uint32_t SMK:2; /* deprecated name - please avoid */ +#endif + uint32_t:6; + uint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */ + } B; + } CFLASH_SLL_32B_tag; + + typedef union { /* LMS - Low/Mid Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MSL:2; /* Mid Address Space Block Select */ + uint32_t:6; + uint32_t LSL:10; /* Low Address Space Block Select */ + } B; + } CFLASH_LMS_32B_tag; + + typedef union { /* HBS - High Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t HSL:6; /* High Address Space Block Select */ + } B; + } CFLASH_HBS_32B_tag; + + typedef union { /* ADR - Address Register */ + uint32_t R; + struct { + uint32_t SAD:1; /* Shadow Address */ + uint32_t:10; + uint32_t ADDR:18; /* Address */ + uint32_t:3; + } B; + } CFLASH_ADR_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */ +#else + uint32_t BK0_APC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */ +#else + uint32_t BK0_WWSC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */ +#else + uint32_t BK0_RWSC:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */ +#else + uint32_t BK0_RWWC2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */ +#else + uint32_t BK0_RWWC1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */ +#else + uint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */ +#else + uint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */ +#else + uint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */ +#else + uint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */ +#else + uint32_t B0_P1_BFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */ +#else + uint32_t BK0_RWWC0:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */ +#else + uint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */ +#else + uint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */ +#else + uint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */ +#else + uint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */ +#else + uint32_t B0_P0_BFE:1; /* deprecated name - please avoid */ +#endif + } B; + } CFLASH_PFCR0_32B_tag; + + + /* Register layout for all registers BIU... */ + + typedef union { /* Bus Interface Unit Register */ + uint32_t R; + } CFLASH_BIU_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */ + uint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */ + uint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */ + uint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */ + uint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */ + uint32_t:6; + uint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */ + uint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */ + uint32_t:6; + uint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */ +#else + uint32_t BK1_APC:5; + uint32_t BK1_WWSC:5; + uint32_t BK1_RWSC:5; + uint32_t BK1_RWWC2:1; + uint32_t BK1_RWWC1:1; + uint32_t:6; + uint32_t B0_P1_BFE:1; + uint32_t BK1_RWWC0:1; + uint32_t:6; + uint32_t B1_P0_BFE:1; +#endif + } B; + } CFLASH_PFCR1_32B_tag; + + typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t ARBM:2; /* Arbitration Mode */ + uint32_t M7PFD:1; /* Master x Prefetch Disable */ + uint32_t M6PFD:1; /* Master x Prefetch Disable */ + uint32_t M5PFD:1; /* Master x Prefetch Disable */ + uint32_t M4PFD:1; /* Master x Prefetch Disable */ + uint32_t M3PFD:1; /* Master x Prefetch Disable */ + uint32_t M2PFD:1; /* Master x Prefetch Disable */ + uint32_t M1PFD:1; /* Master x Prefetch Disable */ + uint32_t M0PFD:1; /* Master x Prefetch Disable */ + uint32_t M7AP:2; /* Master 7 Access Protection */ + uint32_t M6AP:2; /* Master 6 Access Protection */ + uint32_t M5AP:2; /* Master 5 Access Protection */ + uint32_t M4AP:2; /* Master 4 Access Protection */ + uint32_t M3AP:2; /* Master 3 Access Protection */ + uint32_t M2AP:2; /* Master 2 Access Protection */ + uint32_t M1AP:2; /* Master 1 Access Protection */ + uint32_t M0AP:2; /* Master 0 Access Protection */ + } B; + } CFLASH_PFAPR_32B_tag; + + typedef union { /* UT0 - User Test Register */ + uint32_t R; + struct { + uint32_t UTE:1; /* User Test Enable */ + uint32_t SBCE:1; /* Single Bit Correction Enable */ + uint32_t:6; + uint32_t DSI:8; /* Data Syndrome Input */ + uint32_t:10; + uint32_t MRE:1; /* Margin Read Enable */ + uint32_t MRV:1; /* Margin Read Value */ + uint32_t EIE:1; /* ECC Data Input Enable */ + uint32_t AIS:1; /* Array Integrity Sequence */ + uint32_t AIE:1; /* Array Integrity Enable */ + uint32_t AID:1; /* Array Integrity Done */ + } B; + } CFLASH_UT0_32B_tag; + + typedef union { /* UT1 - User Test Register */ + uint32_t R; + } CFLASH_UT1_32B_tag; + + typedef union { /* UT2 - User Test Register */ + uint32_t R; + } CFLASH_UT2_32B_tag; + + + /* Register layout for all registers UM... */ + + typedef union { /* UM - User Multiple Input Signature Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_CFLASH + uint32_t MISR:32; /* Multiple Input Signature */ +#else + uint32_t MS:32; /* deprecated - please avoid */ +#endif + } B; + } CFLASH_UM_32B_tag; + + + /* Register layout for generated register(s) UT... */ + + typedef union { /* */ + uint32_t R; + } CFLASH_UT_32B_tag; + + + /* Register layout for generated register(s) PFCR... */ + + typedef union { /* */ + uint32_t R; + } CFLASH_PFCR_32B_tag; + + + + typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */ + /* MCR - Module Configuration Register */ + CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + /* LML - Low/Mid Address Space Block Locking Register */ + CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */ + /* HBL - High Address Space Block Locking Register */ + CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */ + /* SLL - Secondary Low/Mid Address Space Block Locking Register */ + CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */ + /* LMS - Low/Mid Address Space Block Select Register */ + CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */ + /* HBS - High Address Space Block Select Register */ + CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */ + /* ADR - Address Register */ + CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */ + union { + struct { + /* */ + CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */ + int8_t CFLASH_reserved_0024_E0[12]; + }; + + /* Bus Interface Unit Register */ + CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */ + + struct { + /* Bus Interface Unit Register */ + CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */ + CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */ + CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */ + CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */ + CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */ + }; + + struct { + int8_t CFLASH_reserved_001C_I3[8]; + CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */ + int8_t CFLASH_reserved_0028_E3[8]; + }; + + struct { + /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */ + CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */ + /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */ + CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */ + /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */ + CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */ + int8_t CFLASH_reserved_0028_E4[8]; + }; + + }; + int8_t CFLASH_reserved_0030_C[12]; + union { + CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */ + + struct { + /* UT0 - User Test Register */ + CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */ + /* UT1 - User Test Register */ + CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */ + /* UT2 - User Test Register */ + CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */ + }; + + }; + union { + CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */ + + /* UM - User Multiple Input Signature Register */ + CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */ + + struct { + /* UM - User Multiple Input Signature Register */ + CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */ + CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */ + CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */ + CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */ + CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */ + }; + + }; + } CFLASH_tag; + + +#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL) + + + +/****************************************************************/ +/* */ +/* Module: SIUL */ +/* */ +/****************************************************************/ + + typedef union { /* MIDR1 - MCU ID Register #1 */ + uint32_t R; + struct { + uint32_t PARTNUM:16; /* MCU Part Number */ + uint32_t CSP:1; /* CSP Package */ + uint32_t PKG:5; /* Package Settings */ + uint32_t:2; +#ifndef USE_FIELD_ALIASES_SIUL + uint32_t MAJOR_MASK:4; /* Major Mask Revision */ +#else + uint32_t MAJORMASK:4; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SIUL + uint32_t MINOR_MASK:4; /* Minor Mask Revision */ +#else + uint32_t MINORMASK:4; /* deprecated name - please avoid */ +#endif + } B; + } SIUL_MIDR1_32B_tag; + + typedef union { /* MIDR2 - MCU ID Register #2 */ + uint32_t R; + struct { + uint32_t SF:1; /* Manufacturer */ + uint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */ + uint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */ + uint32_t:7; +#ifndef USE_FIELD_ALIASES_SIUL + uint32_t PARTNUM2:8; /* MCU Part Number */ +#else + uint32_t PARTNUM:8; /* deprecated name - please avoid */ +#endif + uint32_t TBD:1; /* Optional Bit */ + uint32_t:2; + uint32_t EE:1; /* Data Flash Present */ + uint32_t:3; + uint32_t FR:1; /* Flexray Present */ + } B; + } SIUL_MIDR2_32B_tag; + + typedef union { /* ISR - Interrupt Status Flag Register */ + uint32_t R; + struct { + uint32_t EIF31:1; /* External Interrupt Status Flag */ + uint32_t EIF30:1; /* External Interrupt Status Flag */ + uint32_t EIF29:1; /* External Interrupt Status Flag */ + uint32_t EIF28:1; /* External Interrupt Status Flag */ + uint32_t EIF27:1; /* External Interrupt Status Flag */ + uint32_t EIF26:1; /* External Interrupt Status Flag */ + uint32_t EIF25:1; /* External Interrupt Status Flag */ + uint32_t EIF24:1; /* External Interrupt Status Flag */ + uint32_t EIF23:1; /* External Interrupt Status Flag */ + uint32_t EIF22:1; /* External Interrupt Status Flag */ + uint32_t EIF21:1; /* External Interrupt Status Flag */ + uint32_t EIF20:1; /* External Interrupt Status Flag */ + uint32_t EIF19:1; /* External Interrupt Status Flag */ + uint32_t EIF18:1; /* External Interrupt Status Flag */ + uint32_t EIF17:1; /* External Interrupt Status Flag */ + uint32_t EIF16:1; /* External Interrupt Status Flag */ + uint32_t EIF15:1; /* External Interrupt Status Flag */ + uint32_t EIF14:1; /* External Interrupt Status Flag */ + uint32_t EIF13:1; /* External Interrupt Status Flag */ + uint32_t EIF12:1; /* External Interrupt Status Flag */ + uint32_t EIF11:1; /* External Interrupt Status Flag */ + uint32_t EIF10:1; /* External Interrupt Status Flag */ + uint32_t EIF9:1; /* External Interrupt Status Flag */ + uint32_t EIF8:1; /* External Interrupt Status Flag */ + uint32_t EIF7:1; /* External Interrupt Status Flag */ + uint32_t EIF6:1; /* External Interrupt Status Flag */ + uint32_t EIF5:1; /* External Interrupt Status Flag */ + uint32_t EIF4:1; /* External Interrupt Status Flag */ + uint32_t EIF3:1; /* External Interrupt Status Flag */ + uint32_t EIF2:1; /* External Interrupt Status Flag */ + uint32_t EIF1:1; /* External Interrupt Status Flag */ + uint32_t EIF0:1; /* External Interrupt Status Flag */ + } B; + } SIUL_ISR_32B_tag; + + typedef union { /* IRER - Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t EIRE31:1; /* Enable External Interrupt Requests */ + uint32_t EIRE30:1; /* Enable External Interrupt Requests */ + uint32_t EIRE29:1; /* Enable External Interrupt Requests */ + uint32_t EIRE28:1; /* Enable External Interrupt Requests */ + uint32_t EIRE27:1; /* Enable External Interrupt Requests */ + uint32_t EIRE26:1; /* Enable External Interrupt Requests */ + uint32_t EIRE25:1; /* Enable External Interrupt Requests */ + uint32_t EIRE24:1; /* Enable External Interrupt Requests */ + uint32_t EIRE23:1; /* Enable External Interrupt Requests */ + uint32_t EIRE22:1; /* Enable External Interrupt Requests */ + uint32_t EIRE21:1; /* Enable External Interrupt Requests */ + uint32_t EIRE20:1; /* Enable External Interrupt Requests */ + uint32_t EIRE19:1; /* Enable External Interrupt Requests */ + uint32_t EIRE18:1; /* Enable External Interrupt Requests */ + uint32_t EIRE17:1; /* Enable External Interrupt Requests */ + uint32_t EIRE16:1; /* Enable External Interrupt Requests */ + uint32_t EIRE15:1; /* Enable External Interrupt Requests */ + uint32_t EIRE14:1; /* Enable External Interrupt Requests */ + uint32_t EIRE13:1; /* Enable External Interrupt Requests */ + uint32_t EIRE12:1; /* Enable External Interrupt Requests */ + uint32_t EIRE11:1; /* Enable External Interrupt Requests */ + uint32_t EIRE10:1; /* Enable External Interrupt Requests */ + uint32_t EIRE9:1; /* Enable External Interrupt Requests */ + uint32_t EIRE8:1; /* Enable External Interrupt Requests */ + uint32_t EIRE7:1; /* Enable External Interrupt Requests */ + uint32_t EIRE6:1; /* Enable External Interrupt Requests */ + uint32_t EIRE5:1; /* Enable External Interrupt Requests */ + uint32_t EIRE4:1; /* Enable External Interrupt Requests */ + uint32_t EIRE3:1; /* Enable External Interrupt Requests */ + uint32_t EIRE2:1; /* Enable External Interrupt Requests */ + uint32_t EIRE1:1; /* Enable External Interrupt Requests */ + uint32_t EIRE0:1; /* Enable External Interrupt Requests */ + } B; + } SIUL_IRER_32B_tag; + + typedef union { /* IREER - Interrupt Rising Edge Event Enable */ + uint32_t R; + struct { + uint32_t IREE31:1; /* Enable rising-edge events */ + uint32_t IREE30:1; /* Enable rising-edge events */ + uint32_t IREE29:1; /* Enable rising-edge events */ + uint32_t IREE28:1; /* Enable rising-edge events */ + uint32_t IREE27:1; /* Enable rising-edge events */ + uint32_t IREE26:1; /* Enable rising-edge events */ + uint32_t IREE25:1; /* Enable rising-edge events */ + uint32_t IREE24:1; /* Enable rising-edge events */ + uint32_t IREE23:1; /* Enable rising-edge events */ + uint32_t IREE22:1; /* Enable rising-edge events */ + uint32_t IREE21:1; /* Enable rising-edge events */ + uint32_t IREE20:1; /* Enable rising-edge events */ + uint32_t IREE19:1; /* Enable rising-edge events */ + uint32_t IREE18:1; /* Enable rising-edge events */ + uint32_t IREE17:1; /* Enable rising-edge events */ + uint32_t IREE16:1; /* Enable rising-edge events */ + uint32_t IREE15:1; /* Enable rising-edge events */ + uint32_t IREE14:1; /* Enable rising-edge events */ + uint32_t IREE13:1; /* Enable rising-edge events */ + uint32_t IREE12:1; /* Enable rising-edge events */ + uint32_t IREE11:1; /* Enable rising-edge events */ + uint32_t IREE10:1; /* Enable rising-edge events */ + uint32_t IREE9:1; /* Enable rising-edge events */ + uint32_t IREE8:1; /* Enable rising-edge events */ + uint32_t IREE7:1; /* Enable rising-edge events */ + uint32_t IREE6:1; /* Enable rising-edge events */ + uint32_t IREE5:1; /* Enable rising-edge events */ + uint32_t IREE4:1; /* Enable rising-edge events */ + uint32_t IREE3:1; /* Enable rising-edge events */ + uint32_t IREE2:1; /* Enable rising-edge events */ + uint32_t IREE1:1; /* Enable rising-edge events */ + uint32_t IREE0:1; /* Enable rising-edge events */ + } B; + } SIUL_IREER_32B_tag; + + typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */ + uint32_t R; + struct { + uint32_t IFEE31:1; /* Enable Falling Edge Events */ + uint32_t IFEE30:1; /* Enable Falling Edge Events */ + uint32_t IFEE29:1; /* Enable Falling Edge Events */ + uint32_t IFEE28:1; /* Enable Falling Edge Events */ + uint32_t IFEE27:1; /* Enable Falling Edge Events */ + uint32_t IFEE26:1; /* Enable Falling Edge Events */ + uint32_t IFEE25:1; /* Enable Falling Edge Events */ + uint32_t IFEE24:1; /* Enable Falling Edge Events */ + uint32_t IFEE23:1; /* Enable Falling Edge Events */ + uint32_t IFEE22:1; /* Enable Falling Edge Events */ + uint32_t IFEE21:1; /* Enable Falling Edge Events */ + uint32_t IFEE20:1; /* Enable Falling Edge Events */ + uint32_t IFEE19:1; /* Enable Falling Edge Events */ + uint32_t IFEE18:1; /* Enable Falling Edge Events */ + uint32_t IFEE17:1; /* Enable Falling Edge Events */ + uint32_t IFEE16:1; /* Enable Falling Edge Events */ + uint32_t IFEE15:1; /* Enable Falling Edge Events */ + uint32_t IFEE14:1; /* Enable Falling Edge Events */ + uint32_t IFEE13:1; /* Enable Falling Edge Events */ + uint32_t IFEE12:1; /* Enable Falling Edge Events */ + uint32_t IFEE11:1; /* Enable Falling Edge Events */ + uint32_t IFEE10:1; /* Enable Falling Edge Events */ + uint32_t IFEE9:1; /* Enable Falling Edge Events */ + uint32_t IFEE8:1; /* Enable Falling Edge Events */ + uint32_t IFEE7:1; /* Enable Falling Edge Events */ + uint32_t IFEE6:1; /* Enable Falling Edge Events */ + uint32_t IFEE5:1; /* Enable Falling Edge Events */ + uint32_t IFEE4:1; /* Enable Falling Edge Events */ + uint32_t IFEE3:1; /* Enable Falling Edge Events */ + uint32_t IFEE2:1; /* Enable Falling Edge Events */ + uint32_t IFEE1:1; /* Enable Falling Edge Events */ + uint32_t IFEE0:1; /* Enable Falling Edge Events */ + } B; + } SIUL_IFEER_32B_tag; + + typedef union { /* IFER Interrupt Filter Enable Register */ + uint32_t R; + struct { + uint32_t IFE31:1; /* Enable Digital Glitch Filter */ + uint32_t IFE30:1; /* Enable Digital Glitch Filter */ + uint32_t IFE29:1; /* Enable Digital Glitch Filter */ + uint32_t IFE28:1; /* Enable Digital Glitch Filter */ + uint32_t IFE27:1; /* Enable Digital Glitch Filter */ + uint32_t IFE26:1; /* Enable Digital Glitch Filter */ + uint32_t IFE25:1; /* Enable Digital Glitch Filter */ + uint32_t IFE24:1; /* Enable Digital Glitch Filter */ + uint32_t IFE23:1; /* Enable Digital Glitch Filter */ + uint32_t IFE22:1; /* Enable Digital Glitch Filter */ + uint32_t IFE21:1; /* Enable Digital Glitch Filter */ + uint32_t IFE20:1; /* Enable Digital Glitch Filter */ + uint32_t IFE19:1; /* Enable Digital Glitch Filter */ + uint32_t IFE18:1; /* Enable Digital Glitch Filter */ + uint32_t IFE17:1; /* Enable Digital Glitch Filter */ + uint32_t IFE16:1; /* Enable Digital Glitch Filter */ + uint32_t IFE15:1; /* Enable Digital Glitch Filter */ + uint32_t IFE14:1; /* Enable Digital Glitch Filter */ + uint32_t IFE13:1; /* Enable Digital Glitch Filter */ + uint32_t IFE12:1; /* Enable Digital Glitch Filter */ + uint32_t IFE11:1; /* Enable Digital Glitch Filter */ + uint32_t IFE10:1; /* Enable Digital Glitch Filter */ + uint32_t IFE9:1; /* Enable Digital Glitch Filter */ + uint32_t IFE8:1; /* Enable Digital Glitch Filter */ + uint32_t IFE7:1; /* Enable Digital Glitch Filter */ + uint32_t IFE6:1; /* Enable Digital Glitch Filter */ + uint32_t IFE5:1; /* Enable Digital Glitch Filter */ + uint32_t IFE4:1; /* Enable Digital Glitch Filter */ + uint32_t IFE3:1; /* Enable Digital Glitch Filter */ + uint32_t IFE2:1; /* Enable Digital Glitch Filter */ + uint32_t IFE1:1; /* Enable Digital Glitch Filter */ + uint32_t IFE0:1; /* Enable Digital Glitch Filter */ + } B; + } SIUL_IFER_32B_tag; + + + /* Register layout for all registers PCR... */ + + typedef union SIU_PCR_tag { /* PCR - Pad Configuration Register */ + uint16_t R; + struct { + uint16_t:1; +#ifndef USE_FIELD_ALIASES_SIUL + uint16_t SMC:1; /* Safe Mode Control */ +#else + uint16_t SME:1; /* deprecated name - please avoid */ +#endif + uint16_t APC:1; /* Analog Pad Control */ + uint16_t:1; + uint16_t PA:2; /* Pad Output Assignment */ + uint16_t OBE:1; /* Output Buffer Enable */ + uint16_t IBE:1; /* Input Buffer Enable */ +#ifndef USE_FIELD_ALIASES_SIUL + uint16_t DSC:2; /* Drive Strength Control */ +#else + uint16_t DCS:2; /* deprecated name - please avoid */ +#endif + uint16_t ODE:1; /* Open Drain Output Enable */ + uint16_t HYS:1; /* Input Hysteresis */ + uint16_t SRC:2; /* Slew Rate Control */ + uint16_t WPE:1; /* Weak Pull Up/Down Enable */ + uint16_t WPS:1; /* Weak Pull Up/Down Select */ + } B; + } SIU_PCR_tag; + + + /* Register layout for all registers PSMI... */ + + typedef union SIUL_PSMI_8B_tag { /* PSMI - Pad Selection for Multiplexed Inputs */ + uint8_t R; + struct { + uint8_t:4; + uint8_t PADSEL:4; /* Pad selection for pin */ + } B; + } SIUL_PSMI_8B_tag; + + + /* Register layout for all registers PSMI... */ + + typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */ + uint32_t R; + struct { + uint32_t:4; + uint32_t PADSEL0:4; /* Pad selection for pin */ + uint32_t:4; + uint32_t PADSEL1:4; /* Pad selection for pin */ + uint32_t:4; + uint32_t PADSEL2:4; /* Pad selection for pin */ + uint32_t:4; + uint32_t PADSEL3:4; /* Pad selection for pin */ + } B; + } SIUL_PSMI_32B_tag; + + + /* Register layout for all registers GPDO... */ + + typedef union { /* GPDO - GPIO Pad Data Output Register */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; /* Pad Data Out */ + } B; + } SIUL_GPDO_8B_tag; + + + /* Register layout for all registers GPDO... */ + + typedef union { /* GPDO - GPIO Pad Data Output Register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t PDO0:1; /* Pad Data Out */ + uint32_t:7; + uint32_t PDO1:1; /* Pad Data Out */ + uint32_t:7; + uint32_t PDO2:1; /* Pad Data Out */ + uint32_t:7; + uint32_t PDO3:1; /* Pad Data Out */ + } B; + } SIUL_GPDO_32B_tag; + + + /* Register layout for all registers GPDI... */ + + typedef union { /* GPDI - GPIO Pad Data Input Register */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; /* Pad Data In */ + } B; + } SIUL_GPDI_8B_tag; + + + /* Register layout for all registers GPDI... */ + + typedef union { /* GPDI - GPIO Pad Data Input Register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t PDI0:1; /* Pad Data In */ + uint32_t:7; + uint32_t PDI1:1; /* Pad Data In */ + uint32_t:7; + uint32_t PDI2:1; /* Pad Data In */ + uint32_t:7; + uint32_t PDI3:1; /* Pad Data In */ + } B; + } SIUL_GPDI_32B_tag; + + + /* Register layout for all registers PGPDO... */ + + typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */ + uint16_t R; + } SIUL_PGPDO_16B_tag; + + + /* Register layout for all registers PGPDI... */ + + typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */ + uint16_t R; + } SIUL_PGPDI_16B_tag; + + + /* Register layout for all registers MPGPDO... */ + + typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + uint32_t R; + struct { + uint32_t MASK:16; /* Mask Field */ + uint32_t MPPDO:16; /* Masked Parallel Pad Data Out */ + } B; + } SIUL_MPGPDO_32B_tag; + + + /* Register layout for all registers IFMC... */ + + typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */ + } B; + } SIUL_IFMC_32B_tag; + + typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */ + } B; + } SIUL_IFCPR_32B_tag; + + + + typedef struct SIU_tag { /* start of SIUL_tag */ + int8_t SIUL_reserved_0000_C[4]; + union { + SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */ + + /* MIDR1 - MCU ID Register #1 */ + SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */ + + }; + /* MIDR2 - MCU ID Register #2 */ + SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */ + int8_t SIUL_reserved_000C[8]; + /* ISR - Interrupt Status Flag Register */ + SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */ + /* IRER - Interrupt Request Enable Register */ + SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ + int8_t SIUL_reserved_001C[12]; + /* IREER - Interrupt Rising Edge Event Enable */ + SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */ + /* IFEER - Interrupt Falling-Edge Event Enable */ + SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */ + /* IFER Interrupt Filter Enable Register */ + SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */ + int8_t SIUL_reserved_0034_C[12]; + union { + /* PCR - Pad Configuration Register */ + SIU_PCR_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */ + + struct { + /* PCR - Pad Configuration Register */ + SIU_PCR_tag PCR0; /* offset: 0x0040 size: 16 bit */ + SIU_PCR_tag PCR1; /* offset: 0x0042 size: 16 bit */ + SIU_PCR_tag PCR2; /* offset: 0x0044 size: 16 bit */ + SIU_PCR_tag PCR3; /* offset: 0x0046 size: 16 bit */ + SIU_PCR_tag PCR4; /* offset: 0x0048 size: 16 bit */ + SIU_PCR_tag PCR5; /* offset: 0x004A size: 16 bit */ + SIU_PCR_tag PCR6; /* offset: 0x004C size: 16 bit */ + SIU_PCR_tag PCR7; /* offset: 0x004E size: 16 bit */ + SIU_PCR_tag PCR8; /* offset: 0x0050 size: 16 bit */ + SIU_PCR_tag PCR9; /* offset: 0x0052 size: 16 bit */ + SIU_PCR_tag PCR10; /* offset: 0x0054 size: 16 bit */ + SIU_PCR_tag PCR11; /* offset: 0x0056 size: 16 bit */ + SIU_PCR_tag PCR12; /* offset: 0x0058 size: 16 bit */ + SIU_PCR_tag PCR13; /* offset: 0x005A size: 16 bit */ + SIU_PCR_tag PCR14; /* offset: 0x005C size: 16 bit */ + SIU_PCR_tag PCR15; /* offset: 0x005E size: 16 bit */ + SIU_PCR_tag PCR16; /* offset: 0x0060 size: 16 bit */ + SIU_PCR_tag PCR17; /* offset: 0x0062 size: 16 bit */ + SIU_PCR_tag PCR18; /* offset: 0x0064 size: 16 bit */ + SIU_PCR_tag PCR19; /* offset: 0x0066 size: 16 bit */ + SIU_PCR_tag PCR20; /* offset: 0x0068 size: 16 bit */ + SIU_PCR_tag PCR21; /* offset: 0x006A size: 16 bit */ + SIU_PCR_tag PCR22; /* offset: 0x006C size: 16 bit */ + SIU_PCR_tag PCR23; /* offset: 0x006E size: 16 bit */ + SIU_PCR_tag PCR24; /* offset: 0x0070 size: 16 bit */ + SIU_PCR_tag PCR25; /* offset: 0x0072 size: 16 bit */ + SIU_PCR_tag PCR26; /* offset: 0x0074 size: 16 bit */ + SIU_PCR_tag PCR27; /* offset: 0x0076 size: 16 bit */ + SIU_PCR_tag PCR28; /* offset: 0x0078 size: 16 bit */ + SIU_PCR_tag PCR29; /* offset: 0x007A size: 16 bit */ + SIU_PCR_tag PCR30; /* offset: 0x007C size: 16 bit */ + SIU_PCR_tag PCR31; /* offset: 0x007E size: 16 bit */ + SIU_PCR_tag PCR32; /* offset: 0x0080 size: 16 bit */ + SIU_PCR_tag PCR33; /* offset: 0x0082 size: 16 bit */ + SIU_PCR_tag PCR34; /* offset: 0x0084 size: 16 bit */ + SIU_PCR_tag PCR35; /* offset: 0x0086 size: 16 bit */ + SIU_PCR_tag PCR36; /* offset: 0x0088 size: 16 bit */ + SIU_PCR_tag PCR37; /* offset: 0x008A size: 16 bit */ + SIU_PCR_tag PCR38; /* offset: 0x008C size: 16 bit */ + SIU_PCR_tag PCR39; /* offset: 0x008E size: 16 bit */ + SIU_PCR_tag PCR40; /* offset: 0x0090 size: 16 bit */ + SIU_PCR_tag PCR41; /* offset: 0x0092 size: 16 bit */ + SIU_PCR_tag PCR42; /* offset: 0x0094 size: 16 bit */ + SIU_PCR_tag PCR43; /* offset: 0x0096 size: 16 bit */ + SIU_PCR_tag PCR44; /* offset: 0x0098 size: 16 bit */ + SIU_PCR_tag PCR45; /* offset: 0x009A size: 16 bit */ + SIU_PCR_tag PCR46; /* offset: 0x009C size: 16 bit */ + SIU_PCR_tag PCR47; /* offset: 0x009E size: 16 bit */ + SIU_PCR_tag PCR48; /* offset: 0x00A0 size: 16 bit */ + SIU_PCR_tag PCR49; /* offset: 0x00A2 size: 16 bit */ + SIU_PCR_tag PCR50; /* offset: 0x00A4 size: 16 bit */ + SIU_PCR_tag PCR51; /* offset: 0x00A6 size: 16 bit */ + SIU_PCR_tag PCR52; /* offset: 0x00A8 size: 16 bit */ + SIU_PCR_tag PCR53; /* offset: 0x00AA size: 16 bit */ + SIU_PCR_tag PCR54; /* offset: 0x00AC size: 16 bit */ + SIU_PCR_tag PCR55; /* offset: 0x00AE size: 16 bit */ + SIU_PCR_tag PCR56; /* offset: 0x00B0 size: 16 bit */ + SIU_PCR_tag PCR57; /* offset: 0x00B2 size: 16 bit */ + SIU_PCR_tag PCR58; /* offset: 0x00B4 size: 16 bit */ + SIU_PCR_tag PCR59; /* offset: 0x00B6 size: 16 bit */ + SIU_PCR_tag PCR60; /* offset: 0x00B8 size: 16 bit */ + SIU_PCR_tag PCR61; /* offset: 0x00BA size: 16 bit */ + SIU_PCR_tag PCR62; /* offset: 0x00BC size: 16 bit */ + SIU_PCR_tag PCR63; /* offset: 0x00BE size: 16 bit */ + SIU_PCR_tag PCR64; /* offset: 0x00C0 size: 16 bit */ + SIU_PCR_tag PCR65; /* offset: 0x00C2 size: 16 bit */ + SIU_PCR_tag PCR66; /* offset: 0x00C4 size: 16 bit */ + SIU_PCR_tag PCR67; /* offset: 0x00C6 size: 16 bit */ + SIU_PCR_tag PCR68; /* offset: 0x00C8 size: 16 bit */ + SIU_PCR_tag PCR69; /* offset: 0x00CA size: 16 bit */ + SIU_PCR_tag PCR70; /* offset: 0x00CC size: 16 bit */ + SIU_PCR_tag PCR71; /* offset: 0x00CE size: 16 bit */ + SIU_PCR_tag PCR72; /* offset: 0x00D0 size: 16 bit */ + SIU_PCR_tag PCR73; /* offset: 0x00D2 size: 16 bit */ + SIU_PCR_tag PCR74; /* offset: 0x00D4 size: 16 bit */ + SIU_PCR_tag PCR75; /* offset: 0x00D6 size: 16 bit */ + SIU_PCR_tag PCR76; /* offset: 0x00D8 size: 16 bit */ + SIU_PCR_tag PCR77; /* offset: 0x00DA size: 16 bit */ + SIU_PCR_tag PCR78; /* offset: 0x00DC size: 16 bit */ + SIU_PCR_tag PCR79; /* offset: 0x00DE size: 16 bit */ + SIU_PCR_tag PCR80; /* offset: 0x00E0 size: 16 bit */ + SIU_PCR_tag PCR81; /* offset: 0x00E2 size: 16 bit */ + SIU_PCR_tag PCR82; /* offset: 0x00E4 size: 16 bit */ + SIU_PCR_tag PCR83; /* offset: 0x00E6 size: 16 bit */ + SIU_PCR_tag PCR84; /* offset: 0x00E8 size: 16 bit */ + SIU_PCR_tag PCR85; /* offset: 0x00EA size: 16 bit */ + SIU_PCR_tag PCR86; /* offset: 0x00EC size: 16 bit */ + SIU_PCR_tag PCR87; /* offset: 0x00EE size: 16 bit */ + SIU_PCR_tag PCR88; /* offset: 0x00F0 size: 16 bit */ + SIU_PCR_tag PCR89; /* offset: 0x00F2 size: 16 bit */ + SIU_PCR_tag PCR90; /* offset: 0x00F4 size: 16 bit */ + SIU_PCR_tag PCR91; /* offset: 0x00F6 size: 16 bit */ + SIU_PCR_tag PCR92; /* offset: 0x00F8 size: 16 bit */ + SIU_PCR_tag PCR93; /* offset: 0x00FA size: 16 bit */ + SIU_PCR_tag PCR94; /* offset: 0x00FC size: 16 bit */ + SIU_PCR_tag PCR95; /* offset: 0x00FE size: 16 bit */ + SIU_PCR_tag PCR96; /* offset: 0x0100 size: 16 bit */ + SIU_PCR_tag PCR97; /* offset: 0x0102 size: 16 bit */ + SIU_PCR_tag PCR98; /* offset: 0x0104 size: 16 bit */ + SIU_PCR_tag PCR99; /* offset: 0x0106 size: 16 bit */ + SIU_PCR_tag PCR100; /* offset: 0x0108 size: 16 bit */ + SIU_PCR_tag PCR101; /* offset: 0x010A size: 16 bit */ + SIU_PCR_tag PCR102; /* offset: 0x010C size: 16 bit */ + SIU_PCR_tag PCR103; /* offset: 0x010E size: 16 bit */ + SIU_PCR_tag PCR104; /* offset: 0x0110 size: 16 bit */ + SIU_PCR_tag PCR105; /* offset: 0x0112 size: 16 bit */ + SIU_PCR_tag PCR106; /* offset: 0x0114 size: 16 bit */ + SIU_PCR_tag PCR107; /* offset: 0x0116 size: 16 bit */ + SIU_PCR_tag PCR108; /* offset: 0x0118 size: 16 bit */ + SIU_PCR_tag PCR109; /* offset: 0x011A size: 16 bit */ + SIU_PCR_tag PCR110; /* offset: 0x011C size: 16 bit */ + SIU_PCR_tag PCR111; /* offset: 0x011E size: 16 bit */ + SIU_PCR_tag PCR112; /* offset: 0x0120 size: 16 bit */ + SIU_PCR_tag PCR113; /* offset: 0x0122 size: 16 bit */ + SIU_PCR_tag PCR114; /* offset: 0x0124 size: 16 bit */ + SIU_PCR_tag PCR115; /* offset: 0x0126 size: 16 bit */ + SIU_PCR_tag PCR116; /* offset: 0x0128 size: 16 bit */ + SIU_PCR_tag PCR117; /* offset: 0x012A size: 16 bit */ + SIU_PCR_tag PCR118; /* offset: 0x012C size: 16 bit */ + SIU_PCR_tag PCR119; /* offset: 0x012E size: 16 bit */ + SIU_PCR_tag PCR120; /* offset: 0x0130 size: 16 bit */ + SIU_PCR_tag PCR121; /* offset: 0x0132 size: 16 bit */ + SIU_PCR_tag PCR122; /* offset: 0x0134 size: 16 bit */ + SIU_PCR_tag PCR123; /* offset: 0x0136 size: 16 bit */ + SIU_PCR_tag PCR124; /* offset: 0x0138 size: 16 bit */ + SIU_PCR_tag PCR125; /* offset: 0x013A size: 16 bit */ + SIU_PCR_tag PCR126; /* offset: 0x013C size: 16 bit */ + SIU_PCR_tag PCR127; /* offset: 0x013E size: 16 bit */ + SIU_PCR_tag PCR128; /* offset: 0x0140 size: 16 bit */ + SIU_PCR_tag PCR129; /* offset: 0x0142 size: 16 bit */ + SIU_PCR_tag PCR130; /* offset: 0x0144 size: 16 bit */ + SIU_PCR_tag PCR131; /* offset: 0x0146 size: 16 bit */ + SIU_PCR_tag PCR132; /* offset: 0x0148 size: 16 bit */ + SIU_PCR_tag PCR133; /* offset: 0x014A size: 16 bit */ + SIU_PCR_tag PCR134; /* offset: 0x014C size: 16 bit */ + SIU_PCR_tag PCR135; /* offset: 0x014E size: 16 bit */ + SIU_PCR_tag PCR136; /* offset: 0x0150 size: 16 bit */ + SIU_PCR_tag PCR137; /* offset: 0x0152 size: 16 bit */ + SIU_PCR_tag PCR138; /* offset: 0x0154 size: 16 bit */ + SIU_PCR_tag PCR139; /* offset: 0x0156 size: 16 bit */ + SIU_PCR_tag PCR140; /* offset: 0x0158 size: 16 bit */ + SIU_PCR_tag PCR141; /* offset: 0x015A size: 16 bit */ + SIU_PCR_tag PCR142; /* offset: 0x015C size: 16 bit */ + SIU_PCR_tag PCR143; /* offset: 0x015E size: 16 bit */ + SIU_PCR_tag PCR144; /* offset: 0x0160 size: 16 bit */ + SIU_PCR_tag PCR145; /* offset: 0x0162 size: 16 bit */ + SIU_PCR_tag PCR146; /* offset: 0x0164 size: 16 bit */ + SIU_PCR_tag PCR147; /* offset: 0x0166 size: 16 bit */ + SIU_PCR_tag PCR148; /* offset: 0x0168 size: 16 bit */ + SIU_PCR_tag PCR149; /* offset: 0x016A size: 16 bit */ + SIU_PCR_tag PCR150; /* offset: 0x016C size: 16 bit */ + SIU_PCR_tag PCR151; /* offset: 0x016E size: 16 bit */ + SIU_PCR_tag PCR152; /* offset: 0x0170 size: 16 bit */ + SIU_PCR_tag PCR153; /* offset: 0x0172 size: 16 bit */ + SIU_PCR_tag PCR154; /* offset: 0x0174 size: 16 bit */ + SIU_PCR_tag PCR155; /* offset: 0x0176 size: 16 bit */ + SIU_PCR_tag PCR156; /* offset: 0x0178 size: 16 bit */ + SIU_PCR_tag PCR157; /* offset: 0x017A size: 16 bit */ + SIU_PCR_tag PCR158; /* offset: 0x017C size: 16 bit */ + SIU_PCR_tag PCR159; /* offset: 0x017E size: 16 bit */ + SIU_PCR_tag PCR160; /* offset: 0x0180 size: 16 bit */ + SIU_PCR_tag PCR161; /* offset: 0x0182 size: 16 bit */ + SIU_PCR_tag PCR162; /* offset: 0x0184 size: 16 bit */ + SIU_PCR_tag PCR163; /* offset: 0x0186 size: 16 bit */ + SIU_PCR_tag PCR164; /* offset: 0x0188 size: 16 bit */ + SIU_PCR_tag PCR165; /* offset: 0x018A size: 16 bit */ + SIU_PCR_tag PCR166; /* offset: 0x018C size: 16 bit */ + SIU_PCR_tag PCR167; /* offset: 0x018E size: 16 bit */ + SIU_PCR_tag PCR168; /* offset: 0x0190 size: 16 bit */ + SIU_PCR_tag PCR169; /* offset: 0x0192 size: 16 bit */ + SIU_PCR_tag PCR170; /* offset: 0x0194 size: 16 bit */ + SIU_PCR_tag PCR171; /* offset: 0x0196 size: 16 bit */ + SIU_PCR_tag PCR172; /* offset: 0x0198 size: 16 bit */ + SIU_PCR_tag PCR173; /* offset: 0x019A size: 16 bit */ + SIU_PCR_tag PCR174; /* offset: 0x019C size: 16 bit */ + SIU_PCR_tag PCR175; /* offset: 0x019E size: 16 bit */ + SIU_PCR_tag PCR176; /* offset: 0x01A0 size: 16 bit */ + SIU_PCR_tag PCR177; /* offset: 0x01A2 size: 16 bit */ + SIU_PCR_tag PCR178; /* offset: 0x01A4 size: 16 bit */ + SIU_PCR_tag PCR179; /* offset: 0x01A6 size: 16 bit */ + SIU_PCR_tag PCR180; /* offset: 0x01A8 size: 16 bit */ + SIU_PCR_tag PCR181; /* offset: 0x01AA size: 16 bit */ + SIU_PCR_tag PCR182; /* offset: 0x01AC size: 16 bit */ + SIU_PCR_tag PCR183; /* offset: 0x01AE size: 16 bit */ + SIU_PCR_tag PCR184; /* offset: 0x01B0 size: 16 bit */ + SIU_PCR_tag PCR185; /* offset: 0x01B2 size: 16 bit */ + SIU_PCR_tag PCR186; /* offset: 0x01B4 size: 16 bit */ + SIU_PCR_tag PCR187; /* offset: 0x01B6 size: 16 bit */ + SIU_PCR_tag PCR188; /* offset: 0x01B8 size: 16 bit */ + SIU_PCR_tag PCR189; /* offset: 0x01BA size: 16 bit */ + SIU_PCR_tag PCR190; /* offset: 0x01BC size: 16 bit */ + SIU_PCR_tag PCR191; /* offset: 0x01BE size: 16 bit */ + SIU_PCR_tag PCR192; /* offset: 0x01C0 size: 16 bit */ + SIU_PCR_tag PCR193; /* offset: 0x01C2 size: 16 bit */ + SIU_PCR_tag PCR194; /* offset: 0x01C4 size: 16 bit */ + SIU_PCR_tag PCR195; /* offset: 0x01C6 size: 16 bit */ + SIU_PCR_tag PCR196; /* offset: 0x01C8 size: 16 bit */ + SIU_PCR_tag PCR197; /* offset: 0x01CA size: 16 bit */ + SIU_PCR_tag PCR198; /* offset: 0x01CC size: 16 bit */ + SIU_PCR_tag PCR199; /* offset: 0x01CE size: 16 bit */ + SIU_PCR_tag PCR200; /* offset: 0x01D0 size: 16 bit */ + SIU_PCR_tag PCR201; /* offset: 0x01D2 size: 16 bit */ + SIU_PCR_tag PCR202; /* offset: 0x01D4 size: 16 bit */ + SIU_PCR_tag PCR203; /* offset: 0x01D6 size: 16 bit */ + SIU_PCR_tag PCR204; /* offset: 0x01D8 size: 16 bit */ + SIU_PCR_tag PCR205; /* offset: 0x01DA size: 16 bit */ + SIU_PCR_tag PCR206; /* offset: 0x01DC size: 16 bit */ + SIU_PCR_tag PCR207; /* offset: 0x01DE size: 16 bit */ + SIU_PCR_tag PCR208; /* offset: 0x01E0 size: 16 bit */ + SIU_PCR_tag PCR209; /* offset: 0x01E2 size: 16 bit */ + SIU_PCR_tag PCR210; /* offset: 0x01E4 size: 16 bit */ + SIU_PCR_tag PCR211; /* offset: 0x01E6 size: 16 bit */ + SIU_PCR_tag PCR212; /* offset: 0x01E8 size: 16 bit */ + SIU_PCR_tag PCR213; /* offset: 0x01EA size: 16 bit */ + SIU_PCR_tag PCR214; /* offset: 0x01EC size: 16 bit */ + SIU_PCR_tag PCR215; /* offset: 0x01EE size: 16 bit */ + SIU_PCR_tag PCR216; /* offset: 0x01F0 size: 16 bit */ + SIU_PCR_tag PCR217; /* offset: 0x01F2 size: 16 bit */ + SIU_PCR_tag PCR218; /* offset: 0x01F4 size: 16 bit */ + SIU_PCR_tag PCR219; /* offset: 0x01F6 size: 16 bit */ + SIU_PCR_tag PCR220; /* offset: 0x01F8 size: 16 bit */ + SIU_PCR_tag PCR221; /* offset: 0x01FA size: 16 bit */ + SIU_PCR_tag PCR222; /* offset: 0x01FC size: 16 bit */ + SIU_PCR_tag PCR223; /* offset: 0x01FE size: 16 bit */ + SIU_PCR_tag PCR224; /* offset: 0x0200 size: 16 bit */ + SIU_PCR_tag PCR225; /* offset: 0x0202 size: 16 bit */ + SIU_PCR_tag PCR226; /* offset: 0x0204 size: 16 bit */ + SIU_PCR_tag PCR227; /* offset: 0x0206 size: 16 bit */ + SIU_PCR_tag PCR228; /* offset: 0x0208 size: 16 bit */ + SIU_PCR_tag PCR229; /* offset: 0x020A size: 16 bit */ + SIU_PCR_tag PCR230; /* offset: 0x020C size: 16 bit */ + SIU_PCR_tag PCR231; /* offset: 0x020E size: 16 bit */ + SIU_PCR_tag PCR232; /* offset: 0x0210 size: 16 bit */ + SIU_PCR_tag PCR233; /* offset: 0x0212 size: 16 bit */ + SIU_PCR_tag PCR234; /* offset: 0x0214 size: 16 bit */ + SIU_PCR_tag PCR235; /* offset: 0x0216 size: 16 bit */ + SIU_PCR_tag PCR236; /* offset: 0x0218 size: 16 bit */ + SIU_PCR_tag PCR237; /* offset: 0x021A size: 16 bit */ + SIU_PCR_tag PCR238; /* offset: 0x021C size: 16 bit */ + SIU_PCR_tag PCR239; /* offset: 0x021E size: 16 bit */ + SIU_PCR_tag PCR240; /* offset: 0x0220 size: 16 bit */ + SIU_PCR_tag PCR241; /* offset: 0x0222 size: 16 bit */ + SIU_PCR_tag PCR242; /* offset: 0x0224 size: 16 bit */ + SIU_PCR_tag PCR243; /* offset: 0x0226 size: 16 bit */ + SIU_PCR_tag PCR244; /* offset: 0x0228 size: 16 bit */ + SIU_PCR_tag PCR245; /* offset: 0x022A size: 16 bit */ + SIU_PCR_tag PCR246; /* offset: 0x022C size: 16 bit */ + SIU_PCR_tag PCR247; /* offset: 0x022E size: 16 bit */ + SIU_PCR_tag PCR248; /* offset: 0x0230 size: 16 bit */ + SIU_PCR_tag PCR249; /* offset: 0x0232 size: 16 bit */ + SIU_PCR_tag PCR250; /* offset: 0x0234 size: 16 bit */ + SIU_PCR_tag PCR251; /* offset: 0x0236 size: 16 bit */ + SIU_PCR_tag PCR252; /* offset: 0x0238 size: 16 bit */ + SIU_PCR_tag PCR253; /* offset: 0x023A size: 16 bit */ + SIU_PCR_tag PCR254; /* offset: 0x023C size: 16 bit */ + SIU_PCR_tag PCR255; /* offset: 0x023E size: 16 bit */ + SIU_PCR_tag PCR256; /* offset: 0x0240 size: 16 bit */ + SIU_PCR_tag PCR257; /* offset: 0x0242 size: 16 bit */ + SIU_PCR_tag PCR258; /* offset: 0x0244 size: 16 bit */ + SIU_PCR_tag PCR259; /* offset: 0x0246 size: 16 bit */ + SIU_PCR_tag PCR260; /* offset: 0x0248 size: 16 bit */ + SIU_PCR_tag PCR261; /* offset: 0x024A size: 16 bit */ + SIU_PCR_tag PCR262; /* offset: 0x024C size: 16 bit */ + SIU_PCR_tag PCR263; /* offset: 0x024E size: 16 bit */ + SIU_PCR_tag PCR264; /* offset: 0x0250 size: 16 bit */ + SIU_PCR_tag PCR265; /* offset: 0x0252 size: 16 bit */ + SIU_PCR_tag PCR266; /* offset: 0x0254 size: 16 bit */ + SIU_PCR_tag PCR267; /* offset: 0x0256 size: 16 bit */ + SIU_PCR_tag PCR268; /* offset: 0x0258 size: 16 bit */ + SIU_PCR_tag PCR269; /* offset: 0x025A size: 16 bit */ + SIU_PCR_tag PCR270; /* offset: 0x025C size: 16 bit */ + SIU_PCR_tag PCR271; /* offset: 0x025E size: 16 bit */ + SIU_PCR_tag PCR272; /* offset: 0x0260 size: 16 bit */ + SIU_PCR_tag PCR273; /* offset: 0x0262 size: 16 bit */ + SIU_PCR_tag PCR274; /* offset: 0x0264 size: 16 bit */ + SIU_PCR_tag PCR275; /* offset: 0x0266 size: 16 bit */ + SIU_PCR_tag PCR276; /* offset: 0x0268 size: 16 bit */ + SIU_PCR_tag PCR277; /* offset: 0x026A size: 16 bit */ + SIU_PCR_tag PCR278; /* offset: 0x026C size: 16 bit */ + SIU_PCR_tag PCR279; /* offset: 0x026E size: 16 bit */ + SIU_PCR_tag PCR280; /* offset: 0x0270 size: 16 bit */ + SIU_PCR_tag PCR281; /* offset: 0x0272 size: 16 bit */ + SIU_PCR_tag PCR282; /* offset: 0x0274 size: 16 bit */ + SIU_PCR_tag PCR283; /* offset: 0x0276 size: 16 bit */ + SIU_PCR_tag PCR284; /* offset: 0x0278 size: 16 bit */ + SIU_PCR_tag PCR285; /* offset: 0x027A size: 16 bit */ + SIU_PCR_tag PCR286; /* offset: 0x027C size: 16 bit */ + SIU_PCR_tag PCR287; /* offset: 0x027E size: 16 bit */ + SIU_PCR_tag PCR288; /* offset: 0x0280 size: 16 bit */ + SIU_PCR_tag PCR289; /* offset: 0x0282 size: 16 bit */ + SIU_PCR_tag PCR290; /* offset: 0x0284 size: 16 bit */ + SIU_PCR_tag PCR291; /* offset: 0x0286 size: 16 bit */ + SIU_PCR_tag PCR292; /* offset: 0x0288 size: 16 bit */ + SIU_PCR_tag PCR293; /* offset: 0x028A size: 16 bit */ + SIU_PCR_tag PCR294; /* offset: 0x028C size: 16 bit */ + SIU_PCR_tag PCR295; /* offset: 0x028E size: 16 bit */ + SIU_PCR_tag PCR296; /* offset: 0x0290 size: 16 bit */ + SIU_PCR_tag PCR297; /* offset: 0x0292 size: 16 bit */ + SIU_PCR_tag PCR298; /* offset: 0x0294 size: 16 bit */ + SIU_PCR_tag PCR299; /* offset: 0x0296 size: 16 bit */ + SIU_PCR_tag PCR300; /* offset: 0x0298 size: 16 bit */ + SIU_PCR_tag PCR301; /* offset: 0x029A size: 16 bit */ + SIU_PCR_tag PCR302; /* offset: 0x029C size: 16 bit */ + SIU_PCR_tag PCR303; /* offset: 0x029E size: 16 bit */ + SIU_PCR_tag PCR304; /* offset: 0x02A0 size: 16 bit */ + SIU_PCR_tag PCR305; /* offset: 0x02A2 size: 16 bit */ + SIU_PCR_tag PCR306; /* offset: 0x02A4 size: 16 bit */ + SIU_PCR_tag PCR307; /* offset: 0x02A6 size: 16 bit */ + SIU_PCR_tag PCR308; /* offset: 0x02A8 size: 16 bit */ + SIU_PCR_tag PCR309; /* offset: 0x02AA size: 16 bit */ + SIU_PCR_tag PCR310; /* offset: 0x02AC size: 16 bit */ + SIU_PCR_tag PCR311; /* offset: 0x02AE size: 16 bit */ + SIU_PCR_tag PCR312; /* offset: 0x02B0 size: 16 bit */ + SIU_PCR_tag PCR313; /* offset: 0x02B2 size: 16 bit */ + SIU_PCR_tag PCR314; /* offset: 0x02B4 size: 16 bit */ + SIU_PCR_tag PCR315; /* offset: 0x02B6 size: 16 bit */ + SIU_PCR_tag PCR316; /* offset: 0x02B8 size: 16 bit */ + SIU_PCR_tag PCR317; /* offset: 0x02BA size: 16 bit */ + SIU_PCR_tag PCR318; /* offset: 0x02BC size: 16 bit */ + SIU_PCR_tag PCR319; /* offset: 0x02BE size: 16 bit */ + SIU_PCR_tag PCR320; /* offset: 0x02C0 size: 16 bit */ + SIU_PCR_tag PCR321; /* offset: 0x02C2 size: 16 bit */ + SIU_PCR_tag PCR322; /* offset: 0x02C4 size: 16 bit */ + SIU_PCR_tag PCR323; /* offset: 0x02C6 size: 16 bit */ + SIU_PCR_tag PCR324; /* offset: 0x02C8 size: 16 bit */ + SIU_PCR_tag PCR325; /* offset: 0x02CA size: 16 bit */ + SIU_PCR_tag PCR326; /* offset: 0x02CC size: 16 bit */ + SIU_PCR_tag PCR327; /* offset: 0x02CE size: 16 bit */ + SIU_PCR_tag PCR328; /* offset: 0x02D0 size: 16 bit */ + SIU_PCR_tag PCR329; /* offset: 0x02D2 size: 16 bit */ + SIU_PCR_tag PCR330; /* offset: 0x02D4 size: 16 bit */ + SIU_PCR_tag PCR331; /* offset: 0x02D6 size: 16 bit */ + SIU_PCR_tag PCR332; /* offset: 0x02D8 size: 16 bit */ + SIU_PCR_tag PCR333; /* offset: 0x02DA size: 16 bit */ + SIU_PCR_tag PCR334; /* offset: 0x02DC size: 16 bit */ + SIU_PCR_tag PCR335; /* offset: 0x02DE size: 16 bit */ + SIU_PCR_tag PCR336; /* offset: 0x02E0 size: 16 bit */ + SIU_PCR_tag PCR337; /* offset: 0x02E2 size: 16 bit */ + SIU_PCR_tag PCR338; /* offset: 0x02E4 size: 16 bit */ + SIU_PCR_tag PCR339; /* offset: 0x02E6 size: 16 bit */ + SIU_PCR_tag PCR340; /* offset: 0x02E8 size: 16 bit */ + SIU_PCR_tag PCR341; /* offset: 0x02EA size: 16 bit */ + SIU_PCR_tag PCR342; /* offset: 0x02EC size: 16 bit */ + SIU_PCR_tag PCR343; /* offset: 0x02EE size: 16 bit */ + SIU_PCR_tag PCR344; /* offset: 0x02F0 size: 16 bit */ + SIU_PCR_tag PCR345; /* offset: 0x02F2 size: 16 bit */ + SIU_PCR_tag PCR346; /* offset: 0x02F4 size: 16 bit */ + SIU_PCR_tag PCR347; /* offset: 0x02F6 size: 16 bit */ + SIU_PCR_tag PCR348; /* offset: 0x02F8 size: 16 bit */ + SIU_PCR_tag PCR349; /* offset: 0x02FA size: 16 bit */ + SIU_PCR_tag PCR350; /* offset: 0x02FC size: 16 bit */ + SIU_PCR_tag PCR351; /* offset: 0x02FE size: 16 bit */ + SIU_PCR_tag PCR352; /* offset: 0x0300 size: 16 bit */ + SIU_PCR_tag PCR353; /* offset: 0x0302 size: 16 bit */ + SIU_PCR_tag PCR354; /* offset: 0x0304 size: 16 bit */ + SIU_PCR_tag PCR355; /* offset: 0x0306 size: 16 bit */ + SIU_PCR_tag PCR356; /* offset: 0x0308 size: 16 bit */ + SIU_PCR_tag PCR357; /* offset: 0x030A size: 16 bit */ + SIU_PCR_tag PCR358; /* offset: 0x030C size: 16 bit */ + SIU_PCR_tag PCR359; /* offset: 0x030E size: 16 bit */ + SIU_PCR_tag PCR360; /* offset: 0x0310 size: 16 bit */ + SIU_PCR_tag PCR361; /* offset: 0x0312 size: 16 bit */ + SIU_PCR_tag PCR362; /* offset: 0x0314 size: 16 bit */ + SIU_PCR_tag PCR363; /* offset: 0x0316 size: 16 bit */ + SIU_PCR_tag PCR364; /* offset: 0x0318 size: 16 bit */ + SIU_PCR_tag PCR365; /* offset: 0x031A size: 16 bit */ + SIU_PCR_tag PCR366; /* offset: 0x031C size: 16 bit */ + SIU_PCR_tag PCR367; /* offset: 0x031E size: 16 bit */ + SIU_PCR_tag PCR368; /* offset: 0x0320 size: 16 bit */ + SIU_PCR_tag PCR369; /* offset: 0x0322 size: 16 bit */ + SIU_PCR_tag PCR370; /* offset: 0x0324 size: 16 bit */ + SIU_PCR_tag PCR371; /* offset: 0x0326 size: 16 bit */ + SIU_PCR_tag PCR372; /* offset: 0x0328 size: 16 bit */ + SIU_PCR_tag PCR373; /* offset: 0x032A size: 16 bit */ + SIU_PCR_tag PCR374; /* offset: 0x032C size: 16 bit */ + SIU_PCR_tag PCR375; /* offset: 0x032E size: 16 bit */ + SIU_PCR_tag PCR376; /* offset: 0x0330 size: 16 bit */ + SIU_PCR_tag PCR377; /* offset: 0x0332 size: 16 bit */ + SIU_PCR_tag PCR378; /* offset: 0x0334 size: 16 bit */ + SIU_PCR_tag PCR379; /* offset: 0x0336 size: 16 bit */ + SIU_PCR_tag PCR380; /* offset: 0x0338 size: 16 bit */ + SIU_PCR_tag PCR381; /* offset: 0x033A size: 16 bit */ + SIU_PCR_tag PCR382; /* offset: 0x033C size: 16 bit */ + SIU_PCR_tag PCR383; /* offset: 0x033E size: 16 bit */ + SIU_PCR_tag PCR384; /* offset: 0x0340 size: 16 bit */ + SIU_PCR_tag PCR385; /* offset: 0x0342 size: 16 bit */ + SIU_PCR_tag PCR386; /* offset: 0x0344 size: 16 bit */ + SIU_PCR_tag PCR387; /* offset: 0x0346 size: 16 bit */ + SIU_PCR_tag PCR388; /* offset: 0x0348 size: 16 bit */ + SIU_PCR_tag PCR389; /* offset: 0x034A size: 16 bit */ + SIU_PCR_tag PCR390; /* offset: 0x034C size: 16 bit */ + SIU_PCR_tag PCR391; /* offset: 0x034E size: 16 bit */ + SIU_PCR_tag PCR392; /* offset: 0x0350 size: 16 bit */ + SIU_PCR_tag PCR393; /* offset: 0x0352 size: 16 bit */ + SIU_PCR_tag PCR394; /* offset: 0x0354 size: 16 bit */ + SIU_PCR_tag PCR395; /* offset: 0x0356 size: 16 bit */ + SIU_PCR_tag PCR396; /* offset: 0x0358 size: 16 bit */ + SIU_PCR_tag PCR397; /* offset: 0x035A size: 16 bit */ + SIU_PCR_tag PCR398; /* offset: 0x035C size: 16 bit */ + SIU_PCR_tag PCR399; /* offset: 0x035E size: 16 bit */ + SIU_PCR_tag PCR400; /* offset: 0x0360 size: 16 bit */ + SIU_PCR_tag PCR401; /* offset: 0x0362 size: 16 bit */ + SIU_PCR_tag PCR402; /* offset: 0x0364 size: 16 bit */ + SIU_PCR_tag PCR403; /* offset: 0x0366 size: 16 bit */ + SIU_PCR_tag PCR404; /* offset: 0x0368 size: 16 bit */ + SIU_PCR_tag PCR405; /* offset: 0x036A size: 16 bit */ + SIU_PCR_tag PCR406; /* offset: 0x036C size: 16 bit */ + SIU_PCR_tag PCR407; /* offset: 0x036E size: 16 bit */ + SIU_PCR_tag PCR408; /* offset: 0x0370 size: 16 bit */ + SIU_PCR_tag PCR409; /* offset: 0x0372 size: 16 bit */ + SIU_PCR_tag PCR410; /* offset: 0x0374 size: 16 bit */ + SIU_PCR_tag PCR411; /* offset: 0x0376 size: 16 bit */ + SIU_PCR_tag PCR412; /* offset: 0x0378 size: 16 bit */ + SIU_PCR_tag PCR413; /* offset: 0x037A size: 16 bit */ + SIU_PCR_tag PCR414; /* offset: 0x037C size: 16 bit */ + SIU_PCR_tag PCR415; /* offset: 0x037E size: 16 bit */ + SIU_PCR_tag PCR416; /* offset: 0x0380 size: 16 bit */ + SIU_PCR_tag PCR417; /* offset: 0x0382 size: 16 bit */ + SIU_PCR_tag PCR418; /* offset: 0x0384 size: 16 bit */ + SIU_PCR_tag PCR419; /* offset: 0x0386 size: 16 bit */ + SIU_PCR_tag PCR420; /* offset: 0x0388 size: 16 bit */ + SIU_PCR_tag PCR421; /* offset: 0x038A size: 16 bit */ + SIU_PCR_tag PCR422; /* offset: 0x038C size: 16 bit */ + SIU_PCR_tag PCR423; /* offset: 0x038E size: 16 bit */ + SIU_PCR_tag PCR424; /* offset: 0x0390 size: 16 bit */ + SIU_PCR_tag PCR425; /* offset: 0x0392 size: 16 bit */ + SIU_PCR_tag PCR426; /* offset: 0x0394 size: 16 bit */ + SIU_PCR_tag PCR427; /* offset: 0x0396 size: 16 bit */ + SIU_PCR_tag PCR428; /* offset: 0x0398 size: 16 bit */ + SIU_PCR_tag PCR429; /* offset: 0x039A size: 16 bit */ + SIU_PCR_tag PCR430; /* offset: 0x039C size: 16 bit */ + SIU_PCR_tag PCR431; /* offset: 0x039E size: 16 bit */ + SIU_PCR_tag PCR432; /* offset: 0x03A0 size: 16 bit */ + SIU_PCR_tag PCR433; /* offset: 0x03A2 size: 16 bit */ + SIU_PCR_tag PCR434; /* offset: 0x03A4 size: 16 bit */ + SIU_PCR_tag PCR435; /* offset: 0x03A6 size: 16 bit */ + SIU_PCR_tag PCR436; /* offset: 0x03A8 size: 16 bit */ + SIU_PCR_tag PCR437; /* offset: 0x03AA size: 16 bit */ + SIU_PCR_tag PCR438; /* offset: 0x03AC size: 16 bit */ + SIU_PCR_tag PCR439; /* offset: 0x03AE size: 16 bit */ + SIU_PCR_tag PCR440; /* offset: 0x03B0 size: 16 bit */ + SIU_PCR_tag PCR441; /* offset: 0x03B2 size: 16 bit */ + SIU_PCR_tag PCR442; /* offset: 0x03B4 size: 16 bit */ + SIU_PCR_tag PCR443; /* offset: 0x03B6 size: 16 bit */ + SIU_PCR_tag PCR444; /* offset: 0x03B8 size: 16 bit */ + SIU_PCR_tag PCR445; /* offset: 0x03BA size: 16 bit */ + SIU_PCR_tag PCR446; /* offset: 0x03BC size: 16 bit */ + SIU_PCR_tag PCR447; /* offset: 0x03BE size: 16 bit */ + SIU_PCR_tag PCR448; /* offset: 0x03C0 size: 16 bit */ + SIU_PCR_tag PCR449; /* offset: 0x03C2 size: 16 bit */ + SIU_PCR_tag PCR450; /* offset: 0x03C4 size: 16 bit */ + SIU_PCR_tag PCR451; /* offset: 0x03C6 size: 16 bit */ + SIU_PCR_tag PCR452; /* offset: 0x03C8 size: 16 bit */ + SIU_PCR_tag PCR453; /* offset: 0x03CA size: 16 bit */ + SIU_PCR_tag PCR454; /* offset: 0x03CC size: 16 bit */ + SIU_PCR_tag PCR455; /* offset: 0x03CE size: 16 bit */ + SIU_PCR_tag PCR456; /* offset: 0x03D0 size: 16 bit */ + SIU_PCR_tag PCR457; /* offset: 0x03D2 size: 16 bit */ + SIU_PCR_tag PCR458; /* offset: 0x03D4 size: 16 bit */ + SIU_PCR_tag PCR459; /* offset: 0x03D6 size: 16 bit */ + SIU_PCR_tag PCR460; /* offset: 0x03D8 size: 16 bit */ + SIU_PCR_tag PCR461; /* offset: 0x03DA size: 16 bit */ + SIU_PCR_tag PCR462; /* offset: 0x03DC size: 16 bit */ + SIU_PCR_tag PCR463; /* offset: 0x03DE size: 16 bit */ + SIU_PCR_tag PCR464; /* offset: 0x03E0 size: 16 bit */ + SIU_PCR_tag PCR465; /* offset: 0x03E2 size: 16 bit */ + SIU_PCR_tag PCR466; /* offset: 0x03E4 size: 16 bit */ + SIU_PCR_tag PCR467; /* offset: 0x03E6 size: 16 bit */ + SIU_PCR_tag PCR468; /* offset: 0x03E8 size: 16 bit */ + SIU_PCR_tag PCR469; /* offset: 0x03EA size: 16 bit */ + SIU_PCR_tag PCR470; /* offset: 0x03EC size: 16 bit */ + SIU_PCR_tag PCR471; /* offset: 0x03EE size: 16 bit */ + SIU_PCR_tag PCR472; /* offset: 0x03F0 size: 16 bit */ + SIU_PCR_tag PCR473; /* offset: 0x03F2 size: 16 bit */ + SIU_PCR_tag PCR474; /* offset: 0x03F4 size: 16 bit */ + SIU_PCR_tag PCR475; /* offset: 0x03F6 size: 16 bit */ + SIU_PCR_tag PCR476; /* offset: 0x03F8 size: 16 bit */ + SIU_PCR_tag PCR477; /* offset: 0x03FA size: 16 bit */ + SIU_PCR_tag PCR478; /* offset: 0x03FC size: 16 bit */ + SIU_PCR_tag PCR479; /* offset: 0x03FE size: 16 bit */ + SIU_PCR_tag PCR480; /* offset: 0x0400 size: 16 bit */ + SIU_PCR_tag PCR481; /* offset: 0x0402 size: 16 bit */ + SIU_PCR_tag PCR482; /* offset: 0x0404 size: 16 bit */ + SIU_PCR_tag PCR483; /* offset: 0x0406 size: 16 bit */ + SIU_PCR_tag PCR484; /* offset: 0x0408 size: 16 bit */ + SIU_PCR_tag PCR485; /* offset: 0x040A size: 16 bit */ + SIU_PCR_tag PCR486; /* offset: 0x040C size: 16 bit */ + SIU_PCR_tag PCR487; /* offset: 0x040E size: 16 bit */ + SIU_PCR_tag PCR488; /* offset: 0x0410 size: 16 bit */ + SIU_PCR_tag PCR489; /* offset: 0x0412 size: 16 bit */ + SIU_PCR_tag PCR490; /* offset: 0x0414 size: 16 bit */ + SIU_PCR_tag PCR491; /* offset: 0x0416 size: 16 bit */ + SIU_PCR_tag PCR492; /* offset: 0x0418 size: 16 bit */ + SIU_PCR_tag PCR493; /* offset: 0x041A size: 16 bit */ + SIU_PCR_tag PCR494; /* offset: 0x041C size: 16 bit */ + SIU_PCR_tag PCR495; /* offset: 0x041E size: 16 bit */ + SIU_PCR_tag PCR496; /* offset: 0x0420 size: 16 bit */ + SIU_PCR_tag PCR497; /* offset: 0x0422 size: 16 bit */ + SIU_PCR_tag PCR498; /* offset: 0x0424 size: 16 bit */ + SIU_PCR_tag PCR499; /* offset: 0x0426 size: 16 bit */ + SIU_PCR_tag PCR500; /* offset: 0x0428 size: 16 bit */ + SIU_PCR_tag PCR501; /* offset: 0x042A size: 16 bit */ + SIU_PCR_tag PCR502; /* offset: 0x042C size: 16 bit */ + SIU_PCR_tag PCR503; /* offset: 0x042E size: 16 bit */ + SIU_PCR_tag PCR504; /* offset: 0x0430 size: 16 bit */ + SIU_PCR_tag PCR505; /* offset: 0x0432 size: 16 bit */ + SIU_PCR_tag PCR506; /* offset: 0x0434 size: 16 bit */ + SIU_PCR_tag PCR507; /* offset: 0x0436 size: 16 bit */ + SIU_PCR_tag PCR508; /* offset: 0x0438 size: 16 bit */ + SIU_PCR_tag PCR509; /* offset: 0x043A size: 16 bit */ + SIU_PCR_tag PCR510; /* offset: 0x043C size: 16 bit */ + SIU_PCR_tag PCR511; /* offset: 0x043E size: 16 bit */ + }; + + }; + int8_t SIUL_reserved_0440_C[192]; + union { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */ + + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */ + + struct { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */ + SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */ + SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */ + SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */ + }; + + struct { + /* PSMI - Pad Selection for Multiplexed Inputs */ + SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */ + SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */ + SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */ + SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */ + SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */ + SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */ + SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */ + SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */ + SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */ + SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */ + SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */ + SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */ + SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */ + SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */ + SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */ + }; + + }; + union { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */ + + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */ + + struct { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */ + SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */ + SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */ + SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */ + }; + + struct { + /* GPDO - GPIO Pad Data Output Register */ + SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */ + SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */ + SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */ + SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */ + SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */ + SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */ + SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */ + SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */ + SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */ + SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */ + SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */ + SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */ + SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */ + SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */ + SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */ + SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */ + }; + + }; + union { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */ + + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */ + + struct { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */ + SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */ + SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */ + SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */ + }; + + struct { + /* GPDI - GPIO Pad Data Input Register */ + SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */ + SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */ + SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */ + SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */ + SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */ + SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */ + SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */ + SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */ + SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */ + SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */ + SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */ + SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */ + SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */ + SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */ + SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */ + SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */ + }; + + }; + int8_t SIUL_reserved_0A00_C[512]; + union { + /* PGPDO - Parallel GPIO Pad Data Out Register */ + SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */ + + struct { + /* PGPDO - Parallel GPIO Pad Data Out Register */ + SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */ + SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */ + }; + + }; + union { + /* PGPDI - Parallel GPIO Pad Data In Register */ + SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */ + + struct { + /* PGPDI - Parallel GPIO Pad Data In Register */ + SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */ + SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */ + }; + + }; + union { + /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */ + + struct { + /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */ + SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */ + SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */ + }; + + }; + int8_t SIUL_reserved_0D00_C[768]; + union { + /* IFMC - Interrupt Filter Maximum Counter Register */ + SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */ + + struct { + /* IFMC - Interrupt Filter Maximum Counter Register */ + SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */ + SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */ + SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */ + }; + + }; + /* IFCPR - Inerrupt Filter Clock Prescaler Register */ + SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */ + } SIU_tag; + + +#define SIUL (*(volatile SIU_tag *) 0xC3F90000UL) + + + +/****************************************************************/ +/* */ +/* Module: WKPU */ +/* */ +/****************************************************************/ + + typedef union { /* WKPU_NSR - NMI Status Flag Register */ + uint32_t R; + struct { + uint32_t NIF0:1; /* NMI Status Flag 0 */ + uint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */ + uint32_t:6; + uint32_t NIF1:1; /* NMI Status Flag 1 */ + uint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */ + uint32_t:6; + uint32_t NIF2:1; /* NMI Status Flag 2 */ + uint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */ + uint32_t:6; + uint32_t NIF3:1; /* NMI Status Flag 3 */ + uint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */ + uint32_t:6; + } B; + } WKPU_NSR_32B_tag; + + typedef union { /* WKPU_NCR - NMI Configuration Register */ + uint32_t R; + struct { + uint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */ + uint32_t NDSS0:2; /* NMI Desination Source Select 0 */ + uint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */ + uint32_t:1; + uint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */ + uint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */ + uint32_t NFE0:1; /* NMI Filter Enable 0 */ + uint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */ + uint32_t NDSS1:2; /* NMI Desination Source Select 1 */ + uint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */ + uint32_t:1; + uint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */ + uint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */ + uint32_t NFE1:1; /* NMI Filter Enable 1 */ + uint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */ + uint32_t NDSS2:2; /* NMI Desination Source Select 2 */ + uint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */ + uint32_t:1; + uint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */ + uint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */ + uint32_t NFE2:1; /* NMI Filter Enable 2 */ + uint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */ + uint32_t NDSS3:2; /* NMI Desination Source Select 3 */ + uint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */ + uint32_t:1; + uint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */ + uint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */ + uint32_t NFE3:1; /* NMI Filter Enable 3 */ + } B; + } WKPU_NCR_32B_tag; + + typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ + uint32_t R; + struct { + uint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */ + } B; + } WKPU_WISR_32B_tag; + + typedef union { /* WKPU_IRER - Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t EIRE:32; /* Enable External Interrupt Requests */ + } B; + } WKPU_IRER_32B_tag; + + typedef union { /* WKPU_WRER - Wakeup Request Enable Register */ + uint32_t R; + struct { + uint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */ + } B; + } WKPU_WRER_32B_tag; + + typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */ + } B; + } WKPU_WIREER_32B_tag; + + typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */ + } B; + } WKPU_WIFEER_32B_tag; + + typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ + uint32_t R; + struct { + uint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */ + } B; + } WKPU_WIFER_32B_tag; + + typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ + uint32_t R; + struct { + uint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */ + } B; + } WKPU_WIPUER_32B_tag; + + + + typedef struct WKPU_struct_tag { /* start of WKPU_tag */ + /* WKPU_NSR - NMI Status Flag Register */ + WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */ + int8_t WKPU_reserved_0004[4]; + /* WKPU_NCR - NMI Configuration Register */ + WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */ + int8_t WKPU_reserved_000C[8]; + /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */ + WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */ + /* WKPU_IRER - Interrupt Request Enable Register */ + WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */ + /* WKPU_WRER - Wakeup Request Enable Register */ + WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */ + int8_t WKPU_reserved_0020[8]; + /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */ + WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */ + /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */ + WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */ + /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */ + WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */ + /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */ + WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */ + } WKPU_tag; + + +#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL) + + + +/****************************************************************/ +/* */ +/* Module: SSCM */ +/* */ +/****************************************************************/ + + typedef union { /* SSCM_STATUS - System Status Register */ + uint16_t R; + struct { + uint16_t LSM:1; /* Lock Step Mode */ + uint16_t:2; + uint16_t NXEN1:1; /* Processor 1 Nexus enabled */ + uint16_t NXEN:1; /* Processor 0 Nexus enabled */ + uint16_t PUB:1; /* Public Serial Access Status */ + uint16_t SEC:1; /* Security Status */ + uint16_t:1; + uint16_t BMODE:3; /* Device Boot Mode */ + uint16_t VLE:1; /* Variable Length Instruction Mode */ + uint16_t ABD:1; /* Autobaud detection */ + uint16_t:3; + } B; + } SSCM_STATUS_16B_tag; + + typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */ + uint16_t R; + struct { + uint16_t JPIN:10; /* JTAG Part ID Number */ + uint16_t IVLD:1; /* Instruction Flash Valid */ + uint16_t MREV:4; /* Minor Mask Revision */ + uint16_t DVLD:1; /* Data Flash Valid */ + } B; + } SSCM_MEMCONFIG_16B_tag; + + typedef union { /* SSCM_ERROR - Error Configuration */ + uint16_t R; + struct { + uint16_t:14; + uint16_t PAE:1; /* Peripheral Bus Abort Enable */ + uint16_t RAE:1; /* Register Bus Abort Enable */ + } B; + } SSCM_ERROR_16B_tag; + + typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */ + uint16_t R; + struct { + uint16_t:13; + uint16_t DEBUG_MODE:3; /* Debug Status Port Mode */ + } B; + } SSCM_DEBUGPORT_16B_tag; + + typedef union { /* SSCM_PWCMPH - Password Comparison Register High */ + uint32_t R; + struct { + uint32_t PWD_HI:32; /* Password High */ + } B; + } SSCM_PWCMPH_32B_tag; + + typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */ + uint32_t R; + struct { + uint32_t PWD_LO:32; /* Password Low */ + } B; + } SSCM_PWCMPL_32B_tag; + + typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ + uint32_t R; + struct { + uint32_t P2BOOT:30; /* boot location 2nd processor */ + uint32_t DVLE:1; /* VLE mode for 2nd processor */ + uint32_t:1; + } B; + } SSCM_DPMBOOT_32B_tag; + + typedef union { /* SSCM_DPMKEY - Boot Key Register */ + uint32_t R; + struct { + uint32_t KEY:32; /* Boot Control Key */ + } B; + } SSCM_DPMKEY_32B_tag; + + typedef union { /* SSCM_UOPS - User Option Status Register */ + uint32_t R; + struct { + uint32_t UOPT:32; /* User Option Bits */ + } B; + } SSCM_UOPS_32B_tag; + + typedef union { /* SSCM_SCTR - SSCM Control Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t TFE:1; /* Test Flash Enable */ + uint32_t DSL:1; /* Disable Software-Controlled MBIST */ + uint32_t DSM:1; /* Disable Software-Controlled LBIST */ + } B; + } SSCM_SCTR_32B_tag; + + typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ + uint32_t R; + struct { + uint32_t TINFO0:32; /* General purpose TestFlash word 0 */ + } B; + } SSCM_TF_INFO0_32B_tag; + + typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ + uint32_t R; + struct { + uint32_t TINFO1:32; /* General purpose TestFlash word 1 */ + } B; + } SSCM_TF_INFO1_32B_tag; + + typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ + uint32_t R; + struct { + uint32_t TINFO2:32; /* General purpose TestFlash word 2 */ + } B; + } SSCM_TF_INFO2_32B_tag; + + typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ + uint32_t R; + struct { + uint32_t TINFO3:32; /* General purpose TestFlash word */ + } B; + } SSCM_TF_INFO3_32B_tag; + + + + typedef struct SSCM_struct_tag { /* start of SSCM_tag */ + /* SSCM_STATUS - System Status Register */ + SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */ + /* SSCM_MEMCONFIG - System Memory Configuration Register */ + SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */ + int8_t SSCM_reserved_0004[2]; + /* SSCM_ERROR - Error Configuration */ + SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */ + /* SSCM_DEBUGPORT - Debug Status Port Register */ + SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */ + int8_t SSCM_reserved_000A[2]; + /* SSCM_PWCMPH - Password Comparison Register High */ + SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */ + /* SSCM_PWCMPL - Password Comparison Register Low */ + SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */ + int8_t SSCM_reserved_0014[4]; + /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */ + SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */ + /* SSCM_DPMKEY - Boot Key Register */ + SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */ + /* SSCM_UOPS - User Option Status Register */ + SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */ + /* SSCM_SCTR - SSCM Control Register */ + SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */ + /* SSCM_TF_INFO0 - TestFlash Information Register 0 */ + SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */ + /* SSCM_TF_INFO1 - TestFlash Information Register 1 */ + SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */ + /* SSCM_TF_INFO2 - TestFlash Information Register 2 */ + SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */ + /* SSCM_TF_INFO3 - TestFlash Information Register 3 */ + SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */ + } SSCM_tag; + + +#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL) + + + +/****************************************************************/ +/* */ +/* Module: ME */ +/* */ +/****************************************************************/ + + typedef union { /* ME_GS - Global Status Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_CURRENT_MODE:4; /* Current device mode status */ +#else + uint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */ +#endif + uint32_t S_MTRANS:1; /* Mode transition status */ + uint32_t:3; + uint32_t S_PDO:1; /* Output power-down status */ + uint32_t:2; + uint32_t S_MVR:1; /* Main voltage regulator status */ + uint32_t:2; +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_FLA:2; /* Flash availability status */ +#else + uint32_t S_CFLA:2; /* deprecated name - please avoid */ +#endif + uint32_t:8; + uint32_t S_PLL1:1; /* Secondary PLL status */ + uint32_t S_PLL0:1; /* System PLL status */ +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_XOSC:1; /* System crystal oscillator status */ +#else + uint32_t S_OSC:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t S_IRCOSC:1; /* System RC oscillator status */ +#else + uint32_t S_RC:1; /* deprecated name - please avoid */ +#endif + uint32_t S_SYSCLK:4; /* System clock switch status */ + } B; + } ME_GS_32B_tag; + + typedef union { /* ME_MCTL - Mode Control Register */ + uint32_t R; + struct { + uint32_t TARGET_MODE:4; /* Target device mode */ + uint32_t:12; + uint32_t KEY:16; /* Control key */ + } B; + } ME_MCTL_32B_tag; + + typedef union { /* ME_MEN - Mode Enable Register */ + uint32_t R; + struct { + uint32_t:21; + uint32_t STOP0:1; /* STOP0 mode enable */ + uint32_t:1; + uint32_t HALT0:1; /* HALT0 mode enable */ + uint32_t RUN3:1; /* RUN3 mode enable */ + uint32_t RUN2:1; /* RUN2 mode enable */ + uint32_t RUN1:1; /* RUN1 mode enable */ + uint32_t RUN0:1; /* RUN0 mode enable */ + uint32_t DRUN:1; /* DRUN mode enable */ + uint32_t SAFE:1; /* SAFE mode enable */ + uint32_t:1; + uint32_t RESET:1; /* RESET mode enable */ + } B; + } ME_MEN_32B_tag; + + typedef union { /* ME_IS - Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:28; +#ifndef USE_FIELD_ALIASES_ME + uint32_t I_ICONF:1; /* Invalid mode config interrupt */ +#else + uint32_t I_CONF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t I_IMODE:1; /* Invalid mode interrupt */ +#else + uint32_t I_MODE:1; /* deprecated name - please avoid */ +#endif + uint32_t I_SAFE:1; /* SAFE mode interrupt */ +#ifndef USE_FIELD_ALIASES_ME + uint32_t I_MTC:1; /* Mode transition complete interrupt */ +#else + uint32_t I_TC:1; /* deprecated name - please avoid */ +#endif + } B; + } ME_IS_32B_tag; + + typedef union { /* ME_IM - Interrupt Mask Register */ + uint32_t R; + struct { + uint32_t:28; +#ifndef USE_FIELD_ALIASES_ME + uint32_t M_ICONF:1; /* Invalid mode config interrupt mask */ +#else + uint32_t M_CONF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t M_IMODE:1; /* Invalid mode interrupt mask */ +#else + uint32_t M_MODE:1; /* deprecated name - please avoid */ +#endif + uint32_t M_SAFE:1; /* SAFE mode interrupt mask */ +#ifndef USE_FIELD_ALIASES_ME + uint32_t M_MTC:1; /* Mode transition complete interrupt mask */ +#else + uint32_t M_TC:1; /* deprecated name - please avoid */ +#endif + } B; + } ME_IM_32B_tag; + + typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */ + uint32_t R; + struct { + uint32_t:27; + uint32_t S_MTI:1; /* Mode Transition Illegal status */ + uint32_t S_MRI:1; /* Mode Request Illegal status */ + uint32_t S_DMA:1; /* Disabled Mode Access status */ + uint32_t S_NMA:1; /* Non-existing Mode Access status */ + uint32_t S_SEA:1; /* Safe Event Active status */ + } B; + } ME_IMTS_32B_tag; + + typedef union { /* ME_DMTS - Debug Mode Transition Status Register */ + uint32_t R; + struct { + uint32_t PREVIOUS_MODE:4; /* Previous Device Mode */ + uint32_t:4; + uint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */ + uint32_t:2; + uint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */ + uint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */ + uint32_t:2; + uint32_t SMR:1; /* SAFE Mode Request */ + uint32_t:1; + uint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */ + uint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */ + uint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */ + uint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */ + uint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */ + uint32_t:1; + uint32_t FLASH_SC:1; /* FLASH State Change Indicator */ + uint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */ + uint32_t:4; + uint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */ + uint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */ + uint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */ + } B; + } ME_DMTS_32B_tag; + + typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_RESET_MC_32B_tag; + + typedef union { /* ME_SAFE_MC - Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_SAFE_MC_32B_tag; + + typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_DRUN_MC_32B_tag; + + + /* Register layout for all registers RUN_MC... */ + + typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_RUN_MC_32B_tag; + + typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_HALT0_MC_32B_tag; + + typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_STOP0_MC_32B_tag; + + typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t PDO:1; /* IOs output power-down control */ + uint32_t:2; + uint32_t MVRON:1; /* Main voltage regulator control */ + uint32_t:2; + uint32_t FLAON:2; /* Flash power-down control */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */ +#else + uint32_t PLL2ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t PLL0ON:1; /* System PLL control */ +#else + uint32_t PLL1ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t XOSCON:1; /* System crystal oscillator control */ +#else + uint32_t XOSC0ON:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ME + uint32_t IRCOSCON:1; /* System RC oscillator control */ +#else + uint32_t IRCON:1; /* deprecated name - please avoid */ +#endif + uint32_t SYSCLK:4; /* System clock switch control */ + } B; + } ME_STANDBY0_MC_32B_tag; + + typedef union { /* ME_PS0 - Peripheral Status Register 0 */ + uint32_t R; + struct { + uint32_t:7; + uint32_t S_FLEXRAY:1; /* FlexRay status */ + uint32_t:6; + uint32_t S_FLEXCAN1:1; /* FlexCAN1 status */ + uint32_t S_FLEXCAN0:1; /* FlexCAN0 status */ + uint32_t:9; + uint32_t S_DSPI2:1; /* DSPI2 status */ + uint32_t S_DSPI1:1; /* DSPI1 status */ + uint32_t S_DSPI0:1; /* DSPI0 status */ + uint32_t:4; + } B; + } ME_PS0_32B_tag; + + typedef union { /* ME_PS1 - Peripheral Status Register 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t S_SWG:1; /* SWG status */ + uint32_t:3; + uint32_t S_CRC:1; /* CRC status */ + uint32_t:8; + uint32_t S_LIN_FLEX1:1; /* LinFlex1 status */ + uint32_t S_LIN_FLEX0:1; /* LinFlex0 status */ + uint32_t:5; + uint32_t S_FLEXPWM1:1; /* FlexPWM1 status */ + uint32_t S_FLEXPWM0:1; /* FlexPWM0 status */ + uint32_t S_ETIMER2:1; /* eTimer2 status */ + uint32_t S_ETIMER1:1; /* eTimer1 status */ + uint32_t S_ETIMER0:1; /* eTimer0 status */ + uint32_t:2; + uint32_t S_CTU:1; /* CTU status */ + uint32_t:1; + uint32_t S_ADC1:1; /* ADC1 status */ + uint32_t S_ADC0:1; /* ADC0 status */ + } B; + } ME_PS1_32B_tag; + + typedef union { /* ME_PS2 - Peripheral Status Register 2 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t S_PIT:1; /* PIT status */ + uint32_t:28; + } B; + } ME_PS2_32B_tag; + + + /* Register layout for all registers RUN_PC... */ + + typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + uint32_t R; + struct { + uint32_t:24; + uint32_t RUN3:1; /* Peripheral control during RUN3 */ + uint32_t RUN2:1; /* Peripheral control during RUN2 */ + uint32_t RUN1:1; /* Peripheral control during RUN1 */ + uint32_t RUN0:1; /* Peripheral control during RUN0 */ + uint32_t DRUN:1; /* Peripheral control during DRUN */ + uint32_t SAFE:1; /* Peripheral control during SAFE */ + uint32_t TEST:1; /* Peripheral control during TEST */ + uint32_t RESET:1; /* Peripheral control during RESET */ + } B; + } ME_RUN_PC_32B_tag; + + + /* Register layout for all registers LP_PC... */ + + typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + uint32_t R; + struct { + uint32_t:21; + uint32_t STOP0:1; /* Peripheral control during STOP0 */ + uint32_t:1; + uint32_t HALT0:1; /* Peripheral control during HALT0 */ + uint32_t:8; + } B; + } ME_LP_PC_32B_tag; + + + /* Register layout for all registers PCTL... */ + + typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */ + uint8_t R; + struct { + uint8_t:1; + uint8_t DBG_F:1; /* Peripheral control in debug mode */ + uint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */ + uint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */ + } B; + } ME_PCTL_8B_tag; + + + + + /* Register layout for generated register(s) PS... */ + + typedef union { /* */ + uint32_t R; + } ME_PS_32B_tag; + + + + + + + typedef struct ME_struct_tag { /* start of ME_tag */ + /* ME_GS - Global Status Register */ + ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */ + /* ME_MCTL - Mode Control Register */ + ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */ + union { + ME_MEN_32B_tag MER; /* deprecated - please avoid */ + + /* ME_MEN - Mode Enable Register */ + ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */ + + }; + /* ME_IS - Interrupt Status Register */ + ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */ + /* ME_IM - Interrupt Mask Register */ + ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */ + /* ME_IMTS - Invalid Mode Transition Status Register */ + ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */ + /* ME_DMTS - Debug Mode Transition Status Register */ + ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */ + int8_t ME_reserved_001C_C[4]; + union { + /* ME_RESET_MC - RESET Mode Configuration Register */ + ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */ + + ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0024_C[4]; + union { + /* ME_SAFE_MC - Mode Configuration Register */ + ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */ + + ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */ + + }; + union { + /* ME_DRUN_MC - DRUN Mode Configuration Register */ + ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */ + + ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */ + + }; + union { + /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */ + + ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */ + + struct { + /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */ + ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */ + ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */ + ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */ + ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */ + }; + + }; + union { + /* ME_HALT0_MC - HALT0 Mode Configuration Register */ + ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */ + + ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0044_C[4]; + union { + /* ME_STOP0_MC - STOP0 Mode Configration Register */ + ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */ + + ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_004C_C[8]; + union { + /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */ + ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */ + + ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */ + + }; + int8_t ME_reserved_0058_C[8]; + union { + ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */ + + struct { + /* ME_PS0 - Peripheral Status Register 0 */ + ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */ + /* ME_PS1 - Peripheral Status Register 1 */ + ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */ + /* ME_PS2 - Peripheral Status Register 2 */ + ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */ + }; + + }; + int8_t ME_reserved_006C_C[20]; + union { + ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */ + + /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */ + + struct { + /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */ + ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */ + ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */ + }; + + }; + union { + ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + struct { + /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */ + ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */ + ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */ + ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */ + }; + + }; + union { + /* ME_PCTL[0...143] - Peripheral Control Registers */ + ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */ + + struct { + /* ME_PCTL[0...143] - Peripheral Control Registers */ + ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */ + ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */ + ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */ + ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */ + ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */ + ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */ + ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */ + ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */ + ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */ + ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */ + ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */ + ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */ + ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */ + ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */ + ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */ + ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */ + ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */ + ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */ + ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */ + ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */ + ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */ + ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */ + ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */ + ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */ + ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */ + ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */ + ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */ + ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */ + ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */ + ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */ + ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */ + ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */ + ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */ + ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */ + ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */ + ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */ + ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */ + ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */ + ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */ + ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */ + ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */ + ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */ + ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */ + ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */ + ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */ + ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */ + ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */ + ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */ + ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */ + ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */ + ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */ + ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */ + ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */ + ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */ + ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */ + ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */ + ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */ + ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */ + ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */ + ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */ + ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */ + ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */ + ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */ + ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */ + ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */ + ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */ + ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */ + ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */ + ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */ + ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */ + ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */ + ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */ + ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */ + ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */ + ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */ + ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */ + ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */ + ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */ + ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */ + ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */ + ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */ + ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */ + ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */ + ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */ + ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */ + ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */ + ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */ + ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */ + ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */ + ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */ + ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */ + ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */ + ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */ + ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */ + ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */ + ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */ + ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */ + ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */ + ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */ + ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */ + ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */ + ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */ + ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */ + ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */ + ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */ + ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */ + ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */ + ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */ + ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */ + ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */ + ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */ + ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */ + ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */ + ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */ + ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */ + ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */ + ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */ + ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */ + ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */ + ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */ + ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */ + ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */ + ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */ + ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */ + ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */ + ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */ + ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */ + ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */ + ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */ + ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */ + ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */ + ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */ + ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */ + ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */ + ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */ + ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */ + ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */ + ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */ + ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */ + ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */ + ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */ + ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */ + ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */ + ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */ + }; + + }; + } ME_tag; + + +#define ME (*(volatile ME_tag *) 0xC3FDC000UL) + + + +/****************************************************************/ +/* */ +/* Module: OSC */ +/* */ +/****************************************************************/ + + typedef union { /* OSC_CTL - Control Register */ + uint32_t R; + struct { + uint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */ + uint32_t:7; + uint32_t EOCV:8; /* End of Count Value */ + uint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */ + uint32_t:2; + uint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */ + uint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */ + uint32_t:5; + uint32_t S_OSC:1; + uint32_t OSCON:1; } B; + } OSC_CTL_32B_tag; + + + + typedef struct OSC_struct_tag { /* start of OSC_tag */ + /* OSC_CTL - Control Register */ + OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ + } OSC_tag; + + +#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL) + + + +/****************************************************************/ +/* */ +/* Module: RC */ +/* */ +/****************************************************************/ + + typedef union { /* RC_CTL - Control Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t RCTRIM:6; /* Main RC Trimming Bits */ + uint32_t:3; + uint32_t RCDIV:5; /* Main RC Clock Division Factor */ + uint32_t:2; + uint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */ + uint32_t:5; + } B; + } RC_CTL_32B_tag; + + + + typedef struct RC_struct_tag { /* start of RC_tag */ + /* RC_CTL - Control Register */ + RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */ + } RC_tag; + + +#define RC (*(volatile RC_tag *) 0xC3FE0060UL) + + + +/****************************************************************/ +/* */ +/* Module: PLLD */ +/* */ +/****************************************************************/ + + typedef union { /* PLLD_CR - Control Register */ + uint32_t R; + struct { + uint32_t:2; + uint32_t IDF:4; /* PLL Input Division Factor */ + uint32_t ODF:2; /* PLL Output Division Factor */ + uint32_t:1; + uint32_t NDIV:7; /* PLL Loop Division Factor */ + uint32_t:7; + uint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */ + uint32_t MODE:1; /* Activate 1:1 Mode */ + uint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */ + uint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */ + uint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */ + uint32_t S_LOCK:1; /* PLL has Aquired Lock */ + uint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */ + uint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */ + uint32_t PLL_ON:1; /* PLL ON Bit */ + } B; + } PLLD_CR_32B_tag; + + typedef union { /* PLLD_MR - PLLD Modulation Register */ + uint32_t R; + struct { + uint32_t STRB_BYPASS:1; /* Strobe Bypass */ + uint32_t:1; + uint32_t SPRD_SEL:1; /* Spread Type Selection */ + uint32_t MOD_PERIOD:13; /* Modulation Period */ +#ifndef USE_FIELD_ALIASES_PLLD + uint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */ +#else + uint32_t FM_EN:1; /* deprecated name - please avoid */ +#endif + uint32_t INC_STEP:15; /* Increment Step */ + } B; + } PLLD_MR_32B_tag; + + + + typedef struct PLLD_struct_tag { /* start of PLLD_tag */ + /* PLLD_CR - Control Register */ + PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + /* PLLD_MR - PLLD Modulation Register */ + PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */ + + uint32_t plld_reserved[6]; + } PLLD_tag; + + +#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL) +#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL) + + + +/****************************************************************/ +/* */ +/* Module: CMU */ +/* */ +/****************************************************************/ + + typedef union { /* CMU_CSR - Control Status Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t SFM:1; /* Start Frequency Measure */ + uint32_t:13; +#ifndef USE_FIELD_ALIASES_RGM + uint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */ +#else + uint32_t CLKSEL1:2; /* deprecated name - please avoid */ +#endif + uint32_t:5; + uint32_t RCDIV:2; /* RCfast Clock Division Factor */ + uint32_t CME_A:1; /* PLL_A Clock Monitor Enable */ + } B; + } CMU_CSR_32B_tag; + + typedef union { /* CMU_FDR - Frequency Display Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t FD:20; /* Measured Frequency Bits */ + } B; + } CMU_FDR_32B_tag; + + typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t HFREF_A:12; /* High Frequency Reference Value */ + } B; + } CMU_HFREFR_A_32B_tag; + + typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t LFREF_A:12; /* Low Frequency Reference Value */ + } B; + } CMU_LFREFR_A_32B_tag; + + typedef union { /* CMU_ISR - Interrupt Status Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */ +#ifndef USE_FIELD_ALIASES_RGM + uint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */ +#else + uint32_t FHHI_A:1; /* deprecated name - please avoid */ +#endif + uint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */ + uint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */ + } B; + } CMU_ISR_32B_tag; + + typedef union { /* CMU_IMR - Interrupt Mask Register */ + uint32_t R; + } CMU_IMR_32B_tag; + + typedef union { /* CMU_MDR - Measurement Duration Register */ + uint32_t R; + struct { + uint32_t:12; + uint32_t MD:20; /* Measurment Duration Bits */ + } B; + } CMU_MDR_32B_tag; + + + + typedef struct CMU_struct_tag { /* start of CMU_tag */ + /* CMU_CSR - Control Status Register */ + CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */ + /* CMU_FDR - Frequency Display Register */ + CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */ + /* CMU_HFREFR_A - High Frequency Reference Register */ + CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */ + /* CMU_LFREFR_A - Low Frequency Reference Register */ + CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */ + /* CMU_ISR - Interrupt Status Register */ + CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ + /* CMU_IMR - Interrupt Mask Register */ + CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */ + /* CMU_MDR - Measurement Duration Register */ + CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */ + } CMU_tag; + + +#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL) +#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL) +#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL) + + + +/****************************************************************/ +/* */ +/* Module: CGM */ +/* */ +/****************************************************************/ + + typedef union { /* Output Clock Enable Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:31; + uint32_t EN:1; /* Clock Enable Bit */ + } B; + } CGM_OC_EN_32B_tag; + + typedef union { /* Output Clock Division Select Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:2; + uint32_t SELDIV:2; /* Output Clock Division Select */ + uint32_t SELCTL:4; /* Output Clock Source Selection Control */ + uint32_t:24; + } B; + } CGM_OCDS_SC_32B_tag; + + typedef union { /* System Clock Select Status Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:4; + uint32_t SELSTAT:4; /* System Clock Source Selection Status */ + uint32_t:24; + } B; + } CGM_SC_SS_32B_tag; + + typedef union { /* System Clock Divider Configuration Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t DE0:1; /* Divider 0 Enable */ + uint32_t:3; + uint32_t DIV0:4; /* Divider 0 Value */ + uint32_t:24; + } B; + } CGM_SC_DC0_3_32B_tag; + + + /* Register layout for all registers SC_DC... */ + + typedef union { /* System Clock Divider Configuration Register */ + uint8_t R; + struct { + uint8_t DE:1; /* Divider Enable */ + uint8_t:3; + uint8_t DIV:4; /* Divider Division Value */ + } B; + } CGM_SC_DC_8B_tag; + + + /* Register layout for all registers AC_SC... */ + + typedef union { /* Auxiliary Clock Select Control Registers */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:4; + uint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */ + uint32_t:24; + } B; + } CGM_AC_SC_32B_tag; + + + /* Register layout for all registers AC_DC0_3... */ + + typedef union { /* Auxiliary Clock Divider Configuration Registers */ + uint32_t R; + struct { + uint32_t DE0:1; /* Divider 0 Enable */ + uint32_t:3; + uint32_t DIV0:4; /* Divider 0 Value */ + uint32_t DE1:1; /* Divider 1 Enable */ + uint32_t:3; + uint32_t DIV1:4; /* Divider 1 Value */ + uint32_t:16; + } B; + } CGM_AC_DC0_3_32B_tag; + + + typedef struct CGM_AUXCLK_struct_tag { + + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */ + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */ + + } CGM_AUXCLK_tag; + + + typedef struct CGM_struct_tag { /* start of CGM_tag */ + OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */ + int8_t CGM_reserved_0004[92]; + RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */ + int8_t CGM_reserved_0064[60]; + PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */ + int8_t CGM_reserved_00E0[32]; + CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */ + CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */ + CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */ + CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */ + CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */ + CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */ + CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */ + int8_t CGM_reserved_011C[4]; + CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */ + int8_t CGM_reserved_0124[4]; + CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */ + CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */ + CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */ + int8_t CGM_reserved_0134[572]; + union { + /* Output Clock Enable Register */ + CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */ + + CGM_OC_EN_32B_tag OCEN; /* deprecated - please avoid */ + + }; + union { + /* Output Clock Division Select Register */ + CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */ + + CGM_OCDS_SC_32B_tag OCDSSC; /* deprecated - please avoid */ + + }; + union { + /* Output Clock Division Select Register */ + CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */ + + CGM_SC_SS_32B_tag SCSS; /* deprecated - please avoid */ + + }; /* System Clock Select Status Register */ + union { + struct { + /* System Clock Divider Configuration Register */ + CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */ + int8_t CGM_reserved_037E_E0[2]; + }; + + struct { + /* System Clock Divider Configuration Register */ + CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */ + CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */ + int8_t CGM_reserved_037E_E1[2]; + }; + + /* System Clock Divider Configuration Register */ + union { + CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */ + CGM_SC_DC0_3_32B_tag SCDC; /* deprecated - please avoid */ + }; + }; + union { + /* Register set AUXCLK */ + CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */ + + struct { + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */ + + CGM_AC_SC_32B_tag AC0SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC0DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */ + + CGM_AC_SC_32B_tag AC1SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC1DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */ + + CGM_AC_SC_32B_tag AC2SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC2DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */ + + CGM_AC_SC_32B_tag AC3SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC3DC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */ + + CGM_AC_SC_32B_tag AC4SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC4DC; /* deprecated - please avoid */ + }; + union { + /* Auxiliary Clock Select Control Registers */ + CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */ + + CGM_AC_SC_32B_tag AC5SC; /* deprecated - please avoid */ + + }; + union { + /* Auxiliary Clock Divider Configuration Registers */ + CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */ + + CGM_AC_DC0_3_32B_tag AC5DC; /* deprecated - please avoid */ + + }; + }; + + }; + } CGM_tag; + + +#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL) + + + +/****************************************************************/ +/* */ +/* Module: RGM */ +/* */ +/****************************************************************/ + + typedef union { /* Functional Event Status Register */ + uint16_t R; + struct { + uint16_t F_EXR:1; /* Flag for External Reset */ + uint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */ + uint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */ + uint16_t F_ST_DONE:1; /* Flag for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */ +#else + uint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */ + uint16_t F_PLL1:1; /* Flag for PLL1 fail */ + uint16_t F_SWT:1; /* Flag for Software Watchdog Timer */ + uint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */ + uint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */ + uint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */ + uint16_t F_PLL0:1; /* Flag for PLL0 fail */ + uint16_t F_CWD:1; /* Flag for Core Watchdog Reset */ + uint16_t F_SOFT:1; /* Flag for software reset */ + uint16_t F_CORE:1; /* Flag for core reset */ + uint16_t F_JTAG:1; /* Flag for JTAG initiated reset */ + } B; + } RGM_FES_16B_tag; + + typedef union { /* Destructive Event Status Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_RGM + uint16_t F_POR:1; /* Flag for Power on Reset */ +#else + uint16_t POR:1; /* deprecated name - please avoid */ +#endif + uint16_t:7; + uint16_t F_COMP:1; /* Flag for comparator error */ + uint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */ + uint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */ + uint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */ + uint16_t:2; + uint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */ +#else + uint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */ +#endif + } B; + } RGM_DES_16B_tag; + + typedef union { /* Functional Event Reset Disable Register */ + uint16_t R; + struct { + uint16_t D_EXR:1; /* Disable External Pad Event Reset */ + uint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */ + uint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */ + uint16_t D_ST_DONE:1; /* Disable self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */ +#else + uint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */ + uint16_t D_PLL1:1; /* Disable PLL1 fail */ + uint16_t D_SWT:1; /* Disable Software Watchdog Timer */ + uint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */ + uint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */ + uint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */ + uint16_t D_PLL0:1; /* Disable PLL0 fail */ + uint16_t D_CWD:1; /* Disable Core Watchdog Reset */ + uint16_t D_SOFT:1; /* Disable software reset */ + uint16_t D_CORE:1; /* Disable core reset */ + uint16_t D_JTAG:1; /* Disable JTAG initiated reset */ + } B; + } RGM_FERD_16B_tag; + + typedef union { /* Destructive Event Reset Disable Register */ + uint16_t R; + struct { + uint16_t:8; + uint16_t D_COMP:1; /* Disable comparator error */ + uint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */ + uint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */ + uint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */ + uint16_t:2; + uint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */ +#else + uint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */ +#endif + } B; + } RGM_DERD_16B_tag; + + typedef union { /* Functional Event Alternate Request Register */ + uint16_t R; + struct { + uint16_t:4; +#ifndef USE_FIELD_ALIASES_RGM + uint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */ +#else + uint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t:1; + uint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */ + uint16_t:1; + uint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */ + uint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq. + too high/low */ + uint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */ + uint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */ + uint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */ + uint16_t:3; + } B; + } RGM_FEAR_16B_tag; + + typedef union { /* Functional Event Short Sequence Register */ + uint16_t R; + struct { + uint16_t SS_EXR:1; /* Short Sequence for External Reset */ + uint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */ + uint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */ + uint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */ +#else + uint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */ + uint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */ + uint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */ + uint16_t:1; + uint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */ + uint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */ + uint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */ + uint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */ + uint16_t SS_SOFT:1; /* Short Sequence for software reset */ + uint16_t SS_CORE:1; /* Short Sequence for core reset */ + uint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */ + } B; + } RGM_FESS_16B_tag; + + typedef union { /* Functional Bidirectional Reset Enable Register */ + uint16_t R; + struct { + uint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */ + uint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */ + uint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */ + uint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */ +#ifndef USE_FIELD_ALIASES_RGM + uint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */ +#else + uint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */ +#endif + uint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */ + uint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */ + uint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */ + uint16_t:1; + uint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */ + uint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */ + uint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */ + uint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */ + uint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */ + uint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */ + uint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */ + } B; + } RGM_FBRE_16B_tag; + + + + typedef struct RGM_struct_tag { /* start of RGM_tag */ + /* Functional Event Status Register */ + RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */ + /* Destructive Event Status Register */ + RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */ + /* Functional Event Reset Disable Register */ + RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */ + /* Destructive Event Reset Disable Register */ + RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */ + int8_t RGM_reserved_0008[8]; + /* Functional Event Alternate Request Register */ + RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */ + int8_t RGM_reserved_0012[6]; + /* Functional Event Short Sequence Register */ + RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */ + int8_t RGM_reserved_001A[2]; + /* Functional Bidirectional Reset Enable Register */ + RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */ + } RGM_tag; + + +#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL) + + + +/****************************************************************/ +/* */ +/* Module: PCU */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers PCONF... */ + + typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t STBY0:1; /* Power domain control during STBY0 */ + uint32_t:2; + uint32_t STOP0:1; /* Power domain control during STOP0 */ + uint32_t:1; + uint32_t HALT0:1; /* Power domain control during HALT0 */ + uint32_t RUN3:1; /* Power domain control during RUN3 */ + uint32_t RUN2:1; /* Power domain control during RUN2 */ + uint32_t RUN1:1; /* Power domain control during RUN1 */ + uint32_t RUN0:1; /* Power domain control during RUN0 */ + uint32_t DRUN:1; /* Power domain control during DRUN */ + uint32_t SAFE:1; /* Power domain control during SAFE */ + uint32_t TEST:1; /* Power domain control during TEST */ + uint32_t RST:1; /* Power domain control during RST */ + } B; + } PCU_PCONF_32B_tag; + + typedef union { /* PCU_PSTAT - Power Domain Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t PD15:1; /* Power Status for Power Domain 15 */ + uint32_t PD14:1; /* Power Status for Power Domain 14 */ + uint32_t PD13:1; /* Power Status for Power Domain 13 */ + uint32_t PD12:1; /* Power Status for Power Domain 12 */ + uint32_t PD11:1; /* Power Status for Power Domain 11 */ + uint32_t PD10:1; /* Power Status for Power Domain 10 */ + uint32_t PD9:1; /* Power Status for Power Domain 9 */ + uint32_t PD8:1; /* Power Status for Power Domain 8 */ + uint32_t PD7:1; /* Power Status for Power Domain 7 */ + uint32_t PD6:1; /* Power Status for Power Domain 6 */ + uint32_t PD5:1; /* Power Status for Power Domain 5 */ + uint32_t PD4:1; /* Power Status for Power Domain 4 */ + uint32_t PD3:1; /* Power Status for Power Domain 3 */ + uint32_t PD2:1; /* Power Status for Power Domain 2 */ + uint32_t PD1:1; /* Power Status for Power Domain 1 */ + uint32_t PD0:1; /* Power Status for Power Domain 0 */ + } B; + } PCU_PSTAT_32B_tag; + + + + typedef struct PCU_struct_tag { /* start of PCU_tag */ + union { + /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */ + + struct { + /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */ + PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */ + PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */ + PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */ + PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */ + PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */ + PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */ + PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */ + PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */ + PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */ + PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */ + PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */ + PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */ + PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */ + PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */ + PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */ + PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */ + }; + + }; + /* PCU_PSTAT - Power Domain Status Register */ + PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */ + } PCU_tag; + + +#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL) + + + +/****************************************************************/ +/* */ +/* Module: PMUCTRL */ +/* */ +/****************************************************************/ + + typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */ + uint32_t R; + struct { + uint32_t:11; + uint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */ + uint32_t:6; + uint32_t HVD_M:1; /* High Voltage Detector Main */ + uint32_t HVD_B:1; /* High Voltage Detector Backup */ + uint32_t:4; + uint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */ + } B; + } PMUCTRL_STATHVD_32B_tag; + + typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */ + uint32_t R; + struct { + uint32_t:11; + uint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */ + uint32_t:6; + uint32_t LVD_M:1; /* Ligh Voltage Detector Main */ + uint32_t LVD_B:1; /* Ligh Voltage Detector Backup */ + uint32_t:4; + uint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */ + } B; + } PMUCTRL_STATLVD_32B_tag; + + typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ + } B; + } PMUCTRL_STATIREG_32B_tag; + + typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */ + uint32_t R; + struct { + uint32_t:28; + uint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */ + } B; + } PMUCTRL_STATEREG_32B_tag; + + typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */ + uint32_t R; + struct { + uint32_t EBMM:1; /* External Ballast Management Mode */ + uint32_t AEBD:1; /* Automatic External Ballast Detection */ + uint32_t ENPN:1; /* External NPN status flag */ + uint32_t:13; + uint32_t CTB:2; /* Configuration Trace Bits */ + uint32_t:6; + uint32_t CBS:4; /* Current BIST Status */ + uint32_t CPCS:4; /* Current Pmu Configuration Status */ + } B; + } PMUCTRL_STATUS_32B_tag; + + typedef union { /* PMUCTRL_CTRL - PMU Control Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */ + } B; + } PMUCTRL_CTRL_32B_tag; + + typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */ + uint32_t R; + struct { + uint32_t MF_BB:4; /* Mask Fault Bypass Balast */ + uint32_t:28; + } B; + } PMUCTRL_MASKF_32B_tag; + + typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */ + uint32_t R; + struct { + uint32_t BB_LV:4; /* Bypass Ballast Low Voltage */ + uint32_t:9; + uint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */ + uint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */ + uint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */ + uint32_t:13; + uint32_t LHCF:1; /* Low High voltage detector Critical Fault */ + uint32_t LNCF:1; /* Low voltage detector Non Critical Fault */ + uint32_t HNCF:1; /* High voltage detector Non Critical Fault */ + } B; + } PMUCTRL_FAULT_32B_tag; + + typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */ + uint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */ + uint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */ + uint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */ + uint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */ + uint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */ + uint32_t:12; + uint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */ + uint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */ + uint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */ + uint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */ + } B; + } PMUCTRL_IRQS_32B_tag; + + typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */ + uint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */ + uint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */ + uint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */ + uint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */ + uint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */ + uint32_t:12; + uint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */ + uint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */ + uint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */ + uint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */ + } B; + } PMUCTRL_IRQE_32B_tag; + + + + typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */ + int8_t PMUCTRL_reserved_0000[4]; + /* PMUCTRL_STATHVD - PMU Status Register HVD */ + PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */ + /* PMUCTRL_STATLVD - PMU Status Register LVD */ + PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */ + int8_t PMUCTRL_reserved_000C[20]; + /* PMUCTRL_STATIREG - PMU Status Register IREG */ + PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */ + /* PMUCTRL_STATEREG - PMU Status Register EREG */ + PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */ + int8_t PMUCTRL_reserved_0028[24]; + /* PMUCTRL_STATUS - PMU Status Register STATUS */ + PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */ + /* PMUCTRL_CTRL - PMU Control Register */ + PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */ + int8_t PMUCTRL_reserved_0048[40]; + /* PMUCTRL_MASKF - PMU Mask Fault Register */ + PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */ + /* PMUCTRL_FAULT - PMU Fault Monitor Register */ + PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */ + /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */ + PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */ + /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */ + PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */ + } PMUCTRL_tag; + + +#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL) + + + +/****************************************************************/ +/* */ +/* Module: PIT_RTI */ +/* */ +/****************************************************************/ + + typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t MDIS:1; /* Module Disable. Disable the module clock */ + uint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */ + } B; + } PIT_RTI_PITMCR_32B_tag; + + + /* Register layout for all registers LDVAL... */ + + typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */ + uint32_t R; + struct { + uint32_t TSV:32; /* Time Start Value Bits */ + } B; + } PIT_RTI_LDVAL_32B_tag; + + + /* Register layout for all registers CVAL... */ + + typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */ + uint32_t R; + struct { + uint32_t TVL:32; /* Current Timer Value Bits */ + } B; + } PIT_RTI_CVAL_32B_tag; + + + /* Register layout for all registers TCTRL... */ + + typedef union { /* PIT_RTI_TCTRL - Timer Control Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; /* Timer Interrupt Enable Bit */ + uint32_t TEN:1; /* Timer Enable Bit */ + } B; + } PIT_RTI_TCTRL_32B_tag; + + + /* Register layout for all registers TFLG... */ + + typedef union { /* PIT_RTI_TFLG - Timer Flag Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; /* Timer Interrupt Flag Bit */ + } B; + } PIT_RTI_TFLG_32B_tag; + + + typedef struct PIT_RTI_CHANNEL_struct_tag { + + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */ + + } PIT_RTI_CHANNEL_tag; + + + typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */ + /* PIT_RTI_PITMCR - PIT Module Control Register */ + PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */ + int8_t PIT_RTI_reserved_0004_C[252]; + union { + /* Register set CHANNEL */ + PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */ + + PIT_RTI_CHANNEL_tag CH[4]; /* offset: 0x0100 (0x0010 x 4) */ + + struct { + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */ + /* PIT_RTI_LDVAL - Timer Load Value Register */ + PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */ + /* PIT_RTI_CVAL - Current Timer Value Register */ + PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */ + /* PIT_RTI_TCTRL - Timer Control Register */ + PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */ + /* PIT_RTI_TFLG - Timer Flag Register */ + PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */ + }; + + }; + } PIT_RTI_tag; + + +#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL) + + + +/****************************************************************/ +/* */ +/* Module: ADC */ +/* */ +/****************************************************************/ + + typedef union { /* module configuration register */ + uint32_t R; + struct { + uint32_t OWREN:1; /* Overwrite enable */ + uint32_t WLSIDE:1; /* Write Left/right Alligned */ + uint32_t MODE:1; /* One Shot/Scan Mode Selectiom */ + uint32_t EDGLEV:1; /* edge or level selection for external start trigger */ + uint32_t TRGEN:1; /* external trigger enable */ + uint32_t EDGE:1; /* start trigger egde /level detection */ + uint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */ + uint32_t NSTART:1; /* start normal conversion */ + uint32_t:1; + uint32_t JTRGEN:1; /* Injectin External Trigger Enable */ + uint32_t JEDGE:1; /* start trigger egde /level detection for injected */ + uint32_t JSTART:1; /* injected conversion start */ + uint32_t:2; + uint32_t CTUEN:1; /* CTU enabaled */ + uint32_t:8; + uint32_t ADCLKSEL:1; /* Select which clock for device */ + uint32_t ABORTCHAIN:1; /* abort chain conversion */ + uint32_t ABORT:1; /* abort current conversion */ +#ifndef USE_FIELD_ALIASES_ADC + uint32_t ACKO:1; /* Auto Clock Off Enable */ +#else + uint32_t ACK0:1; /* deprecated name - please avoid */ +#endif + uint32_t OFFREFRESH:1; /* offset phase selection */ + uint32_t OFFCANC:1; /* offset phase cancellation selection */ + uint32_t:2; + uint32_t PWDN:1; /* Power Down Enable */ + } B; + } ADC_MCR_32B_tag; + + typedef union { /* module status register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t NSTART:1; /* normal conversion status */ + uint32_t JABORT:1; /* Injection chain abort status */ + uint32_t:2; + uint32_t JSTART:1; /* Injection Start status */ + uint32_t:3; + uint32_t CTUSTART:1; /* ctu start status */ + uint32_t CHADDR:7; /* which address conv is goin on */ + uint32_t:3; +#ifndef USE_FIELD_ALIASES_ADC + uint32_t ACKO:1; /* Auto Clock Off Enable status */ +#else + uint32_t ACK0:1; /* deprecated name - please avoid */ +#endif + uint32_t OFFREFRESH:1; /* offset refresh status */ + uint32_t OFFCANC:1; /* offset phase cancellation status */ + uint32_t ADCSTATUS:3; /* status of ADC FSM */ + } B; + } ADC_MSR_32B_tag; + + typedef union { /* Interrupt status register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t OFFCANCOVR:1; /* Offset cancellation phase over */ + uint32_t EOFFSET:1; /* error in offset refresh */ + uint32_t EOCTU:1; /* end of CTU channel conversion */ + uint32_t JEOC:1; /* end of injected channel conversion */ + uint32_t JECH:1; /* end ofinjected chain conversion */ + uint32_t EOC:1; /* end of channel conversion */ + uint32_t ECH:1; /* end of chain conversion */ + } B; + } ADC_ISR_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 0 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH31:1; /* Channel 31 conversion over */ +#else + uint32_t EOC31:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH30:1; /* Channel 30 conversion over */ +#else + uint32_t EOC30:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH29:1; /* Channel 29 conversion over */ +#else + uint32_t EOC29:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH28:1; /* Channel 28 conversion over */ +#else + uint32_t EOC28:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH27:1; /* Channel 27 conversion over */ +#else + uint32_t EOC27:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH26:1; /* Channel 26 conversion over */ +#else + uint32_t EOC26:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH25:1; /* Channel 25 conversion over */ +#else + uint32_t EOC25:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH24:1; /* Channel 24 conversion over */ +#else + uint32_t EOC24:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH23:1; /* Channel 23 conversion over */ +#else + uint32_t EOC23:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH22:1; /* Channel 22 conversion over */ +#else + uint32_t EOC22:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH21:1; /* Channel 21 conversion over */ +#else + uint32_t EOC21:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH20:1; /* Channel 20 conversion over */ +#else + uint32_t EOC20:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH19:1; /* Channel 19 conversion over */ +#else + uint32_t EOC19:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH18:1; /* Channel 18 conversion over */ +#else + uint32_t EOC18:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH17:1; /* Channel 17 conversion over */ +#else + uint32_t EOC17:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH16:1; /* Channel 16 conversion over */ +#else + uint32_t EOC16:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH15:1; /* Channel 15 conversion over */ +#else + uint32_t EOC15:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH14:1; /* Channel 14 conversion over */ +#else + uint32_t EOC14:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH13:1; /* Channel 13 conversion over */ +#else + uint32_t EOC13:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH12:1; /* Channel 12 conversion over */ +#else + uint32_t EOC12:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH11:1; /* Channel 11 conversion over */ +#else + uint32_t EOC11:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH10:1; /* Channel 10 conversion over */ +#else + uint32_t EOC10:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH9:1; /* Channel 9 conversion over */ +#else + uint32_t EOC9:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH8:1; /* Channel 8 conversion over */ +#else + uint32_t EOC8:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH7:1; /* Channel 7 conversion over */ +#else + uint32_t EOC7:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH6:1; /* Channel 6 conversion over */ +#else + uint32_t EOC6:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH5:1; /* Channel 5 conversion over */ +#else + uint32_t EOC5:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH4:1; /* Channel 4 conversion over */ +#else + uint32_t EOC4:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH3:1; /* Channel 3 conversion over */ +#else + uint32_t EOC3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH2:1; /* Channel 2 conversion over */ +#else + uint32_t EOC2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH1:1; /* Channel 1 conversion over */ +#else + uint32_t EOC1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_ADC + uint32_t EOC_CH0:1; /* Channel 0 conversion over */ +#else + uint32_t EOC0:1; /* deprecated name - please avoid */ +#endif + } B; + } ADC_CEOCFR0_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 1 */ + uint32_t R; + struct { + uint32_t EOC_CH63:1; /* Channel 63 conversion over */ + uint32_t EOC_CH62:1; /* Channel 62 conversion over */ + uint32_t EOC_CH61:1; /* Channel 61 conversion over */ + uint32_t EOC_CH60:1; /* Channel 60 conversion over */ + uint32_t EOC_CH59:1; /* Channel 59 conversion over */ + uint32_t EOC_CH58:1; /* Channel 58 conversion over */ + uint32_t EOC_CH57:1; /* Channel 57 conversion over */ + uint32_t EOC_CH56:1; /* Channel 56 conversion over */ + uint32_t EOC_CH55:1; /* Channel 55 conversion over */ + uint32_t EOC_CH54:1; /* Channel 54 conversion over */ + uint32_t EOC_CH53:1; /* Channel 53 conversion over */ + uint32_t EOC_CH52:1; /* Channel 52 conversion over */ + uint32_t EOC_CH51:1; /* Channel 51 conversion over */ + uint32_t EOC_CH50:1; /* Channel 50 conversion over */ + uint32_t EOC_CH49:1; /* Channel 49 conversion over */ + uint32_t EOC_CH48:1; /* Channel 48 conversion over */ + uint32_t EOC_CH47:1; /* Channel 47 conversion over */ + uint32_t EOC_CH46:1; /* Channel 46 conversion over */ + uint32_t EOC_CH45:1; /* Channel 45 conversion over */ + uint32_t EOC_CH44:1; /* Channel 44 conversion over */ + uint32_t EOC_CH43:1; /* Channel 43 conversion over */ + uint32_t EOC_CH42:1; /* Channel 42 conversion over */ + uint32_t EOC_CH41:1; /* Channel 41 conversion over */ + uint32_t EOC_CH40:1; /* Channel 40 conversion over */ + uint32_t EOC_CH39:1; /* Channel 39 conversion over */ + uint32_t EOC_CH38:1; /* Channel 38 conversion over */ + uint32_t EOC_CH37:1; /* Channel 37 conversion over */ + uint32_t EOC_CH36:1; /* Channel 36 conversion over */ + uint32_t EOC_CH35:1; /* Channel 35 conversion over */ + uint32_t EOC_CH34:1; /* Channel 34 conversion over */ + uint32_t EOC_CH33:1; /* Channel 33 conversion over */ + uint32_t EOC_CH32:1; /* Channel 32 conversion over */ + } B; + } ADC_CEOCFR1_32B_tag; + + typedef union { /* CHANNEL PENDING REGISTER 2 */ + uint32_t R; + struct { + uint32_t EOC_CH95:1; /* Channel 95 conversion over */ + uint32_t EOC_CH94:1; /* Channel 94 conversion over */ + uint32_t EOC_CH93:1; /* Channel 93 conversion over */ + uint32_t EOC_CH92:1; /* Channel 92 conversion over */ + uint32_t EOC_CH91:1; /* Channel 91 conversion over */ + uint32_t EOC_CH90:1; /* Channel 90 conversion over */ + uint32_t EOC_CH89:1; /* Channel 89 conversion over */ + uint32_t EOC_CH88:1; /* Channel 88 conversion over */ + uint32_t EOC_CH87:1; /* Channel 87 conversion over */ + uint32_t EOC_CH86:1; /* Channel 86 conversion over */ + uint32_t EOC_CH85:1; /* Channel 85 conversion over */ + uint32_t EOC_CH84:1; /* Channel 84 conversion over */ + uint32_t EOC_CH83:1; /* Channel 83 conversion over */ + uint32_t EOC_CH82:1; /* Channel 82 conversion over */ + uint32_t EOC_CH81:1; /* Channel 81 conversion over */ + uint32_t EOC_CH80:1; /* Channel 80 conversion over */ + uint32_t EOC_CH79:1; /* Channel 79 conversion over */ + uint32_t EOC_CH78:1; /* Channel 78 conversion over */ + uint32_t EOC_CH77:1; /* Channel 77 conversion over */ + uint32_t EOC_CH76:1; /* Channel 76 conversion over */ + uint32_t EOC_CH75:1; /* Channel 75 conversion over */ + uint32_t EOC_CH74:1; /* Channel 74 conversion over */ + uint32_t EOC_CH73:1; /* Channel 73 conversion over */ + uint32_t EOC_CH72:1; /* Channel 72 conversion over */ + uint32_t EOC_CH71:1; /* Channel 71 conversion over */ + uint32_t EOC_CH70:1; /* Channel 70 conversion over */ + uint32_t EOC_CH69:1; /* Channel 69 conversion over */ + uint32_t EOC_CH68:1; /* Channel 68 conversion over */ + uint32_t EOC_CH67:1; /* Channel 67 conversion over */ + uint32_t EOC_CH66:1; /* Channel 66 conversion over */ + uint32_t EOC_CH65:1; /* Channel 65 conversion over */ + uint32_t EOC_CH64:1; /* Channel 64 conversion over */ + } B; + } ADC_CEOCFR2_32B_tag; + + typedef union { /* interrupt mask register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */ + uint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */ + uint32_t MSKEOCTU:1; /* mask bit for EOCTU */ + uint32_t MSKJEOC:1; /* mask bit for JEOC */ + uint32_t MSKJECH:1; /* mask bit for JECH */ + uint32_t MSKEOC:1; /* mask bit for EOC */ + uint32_t MSKECH:1; /* mask bit for ECH */ + } B; + } ADC_IMR_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */ + uint32_t R; + struct { + uint32_t CIM31:1; /* Channel 31 mask register */ + uint32_t CIM30:1; /* Channel 30 mask register */ + uint32_t CIM29:1; /* Channel 29 mask register */ + uint32_t CIM28:1; /* Channel 28 mask register */ + uint32_t CIM27:1; /* Channel 27 mask register */ + uint32_t CIM26:1; /* Channel 26 mask register */ + uint32_t CIM25:1; /* Channel 25 mask register */ + uint32_t CIM24:1; /* Channel 24 mask register */ + uint32_t CIM23:1; /* Channel 23 mask register */ + uint32_t CIM22:1; /* Channel 22 mask register */ + uint32_t CIM21:1; /* Channel 21 mask register */ + uint32_t CIM20:1; /* Channel 20 mask register */ + uint32_t CIM19:1; /* Channel 19 mask register */ + uint32_t CIM18:1; /* Channel 18 mask register */ + uint32_t CIM17:1; /* Channel 17 mask register */ + uint32_t CIM16:1; /* Channel 16 mask register */ + uint32_t CIM15:1; /* Channel 15 mask register */ + uint32_t CIM14:1; /* Channel 14 mask register */ + uint32_t CIM13:1; /* Channel 13 mask register */ + uint32_t CIM12:1; /* Channel 12 mask register */ + uint32_t CIM11:1; /* Channel 11 mask register */ + uint32_t CIM10:1; /* Channel 10 mask register */ + uint32_t CIM9:1; /* Channel 9 mask register */ + uint32_t CIM8:1; /* Channel 8 mask register */ + uint32_t CIM7:1; /* Channel 7 mask register */ + uint32_t CIM6:1; /* Channel 6 mask register */ + uint32_t CIM5:1; /* Channel 5 mask register */ + uint32_t CIM4:1; /* Channel 4 mask register */ + uint32_t CIM3:1; /* Channel 3 mask register */ + uint32_t CIM2:1; /* Channel 2 mask register */ + uint32_t CIM1:1; /* Channel 1 mask register */ + uint32_t CIM0:1; /* Channel 0 mask register */ + } B; + } ADC_CIMR0_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */ + uint32_t R; + struct { + uint32_t CIM63:1; /* Channel 63 mask register */ + uint32_t CIM62:1; /* Channel 62 mask register */ + uint32_t CIM61:1; /* Channel 61 mask register */ + uint32_t CIM60:1; /* Channel 60 mask register */ + uint32_t CIM59:1; /* Channel 59 mask register */ + uint32_t CIM58:1; /* Channel 58 mask register */ + uint32_t CIM57:1; /* Channel 57 mask register */ + uint32_t CIM56:1; /* Channel 56 mask register */ + uint32_t CIM55:1; /* Channel 55 mask register */ + uint32_t CIM54:1; /* Channel 54 mask register */ + uint32_t CIM53:1; /* Channel 53 mask register */ + uint32_t CIM52:1; /* Channel 52 mask register */ + uint32_t CIM51:1; /* Channel 51 mask register */ + uint32_t CIM50:1; /* Channel 50 mask register */ + uint32_t CIM49:1; /* Channel 49 mask register */ + uint32_t CIM48:1; /* Channel 48 mask register */ + uint32_t CIM47:1; /* Channel 47 mask register */ + uint32_t CIM46:1; /* Channel 46 mask register */ + uint32_t CIM45:1; /* Channel 45 mask register */ + uint32_t CIM44:1; /* Channel 44 mask register */ + uint32_t CIM43:1; /* Channel 43 mask register */ + uint32_t CIM42:1; /* Channel 42 mask register */ + uint32_t CIM41:1; /* Channel 41 mask register */ + uint32_t CIM40:1; /* Channel 40 mask register */ + uint32_t CIM39:1; /* Channel 39 mask register */ + uint32_t CIM38:1; /* Channel 38 mask register */ + uint32_t CIM37:1; /* Channel 37 mask register */ + uint32_t CIM36:1; /* Channel 36 mask register */ + uint32_t CIM35:1; /* Channel 35 mask register */ + uint32_t CIM34:1; /* Channel 34 mask register */ + uint32_t CIM33:1; /* Channel 33 mask register */ + uint32_t CIM32:1; /* Channel 32 mask register */ + } B; + } ADC_CIMR1_32B_tag; + + typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */ + uint32_t R; + struct { + uint32_t CIM95:1; /* Channel 95 mask register */ + uint32_t CIM94:1; /* Channel 94 mask register */ + uint32_t CIM93:1; /* Channel 93 mask register */ + uint32_t CIM92:1; /* Channel 92 mask register */ + uint32_t CIM91:1; /* Channel 91 mask register */ + uint32_t CIM90:1; /* Channel 90 mask register */ + uint32_t CIM89:1; /* Channel 89 mask register */ + uint32_t CIM88:1; /* Channel 88 mask register */ + uint32_t CIM87:1; /* Channel 87 mask register */ + uint32_t CIM86:1; /* Channel 86 mask register */ + uint32_t CIM85:1; /* Channel 85 mask register */ + uint32_t CIM84:1; /* Channel 84 mask register */ + uint32_t CIM83:1; /* Channel 83 mask register */ + uint32_t CIM82:1; /* Channel 82 mask register */ + uint32_t CIM81:1; /* Channel 81 mask register */ + uint32_t CIM80:1; /* Channel 80 mask register */ + uint32_t CIM79:1; /* Channel 79 mask register */ + uint32_t CIM78:1; /* Channel 78 mask register */ + uint32_t CIM77:1; /* Channel 77 mask register */ + uint32_t CIM76:1; /* Channel 76 mask register */ + uint32_t CIM75:1; /* Channel 75 mask register */ + uint32_t CIM74:1; /* Channel 74 mask register */ + uint32_t CIM73:1; /* Channel 73 mask register */ + uint32_t CIM72:1; /* Channel 72 mask register */ + uint32_t CIM71:1; /* Channel 71 mask register */ + uint32_t CIM70:1; /* Channel 70 mask register */ + uint32_t CIM69:1; /* Channel 69 mask register */ + uint32_t CIM68:1; /* Channel 68 mask register */ + uint32_t CIM67:1; /* Channel 67 mask register */ + uint32_t CIM66:1; /* Channel 66 mask register */ + uint32_t CIM65:1; /* Channel 65 mask register */ + uint32_t CIM64:1; /* Channel 64 mask register */ + } B; + } ADC_CIMR2_32B_tag; + + typedef union { /* Watchdog Threshold interrupt status register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */ + uint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */ + uint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */ + uint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */ + uint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */ + uint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */ + uint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */ + uint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */ + } B; + } ADC_WTISR_32B_tag; + + typedef union { /* Watchdog interrupt MASK register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */ + uint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */ + uint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */ + uint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */ + uint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */ + uint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */ + uint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */ + uint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */ + } B; + } ADC_WTIMR_32B_tag; + + typedef union { /* DMAE register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t DCLR:1; /* DMA clear sequence enable */ + uint32_t DMAEN:1; /* DMA global enable */ + } B; + } ADC_DMAE_32B_tag; + + typedef union { /* DMA REGISTER 0 */ + uint32_t R; + struct { + uint32_t DMA31:1; /* Channel 31 DMA Enable */ + uint32_t DMA30:1; /* Channel 30 DMA Enable */ + uint32_t DMA29:1; /* Channel 29 DMA Enable */ + uint32_t DMA28:1; /* Channel 28 DMA Enable */ + uint32_t DMA27:1; /* Channel 27 DMA Enable */ + uint32_t DMA26:1; /* Channel 26 DMA Enable */ + uint32_t DMA25:1; /* Channel 25 DMA Enable */ + uint32_t DMA24:1; /* Channel 24 DMA Enable */ + uint32_t DMA23:1; /* Channel 23 DMA Enable */ + uint32_t DMA22:1; /* Channel 22 DMA Enable */ + uint32_t DMA21:1; /* Channel 21 DMA Enable */ + uint32_t DMA20:1; /* Channel 20 DMA Enable */ + uint32_t DMA19:1; /* Channel 19 DMA Enable */ + uint32_t DMA18:1; /* Channel 18 DMA Enable */ + uint32_t DMA17:1; /* Channel 17 DMA Enable */ + uint32_t DMA16:1; /* Channel 16 DMA Enable */ + uint32_t DMA15:1; /* Channel 15 DMA Enable */ + uint32_t DMA14:1; /* Channel 14 DMA Enable */ + uint32_t DMA13:1; /* Channel 13 DMA Enable */ + uint32_t DMA12:1; /* Channel 12 DMA Enable */ + uint32_t DMA11:1; /* Channel 11 DMA Enable */ + uint32_t DMA10:1; /* Channel 10 DMA Enable */ + uint32_t DMA9:1; /* Channel 9 DMA Enable */ + uint32_t DMA8:1; /* Channel 8 DMA Enable */ + uint32_t DMA7:1; /* Channel 7 DMA Enable */ + uint32_t DMA6:1; /* Channel 6 DMA Enable */ + uint32_t DMA5:1; /* Channel 5 DMA Enable */ + uint32_t DMA4:1; /* Channel 4 DMA Enable */ + uint32_t DMA3:1; /* Channel 3 DMA Enable */ + uint32_t DMA2:1; /* Channel 2 DMA Enable */ + uint32_t DMA1:1; /* Channel 1 DMA Enable */ + uint32_t DMA0:1; /* Channel 0 DMA Enable */ + } B; + } ADC_DMAR0_32B_tag; + + typedef union { /* DMA REGISTER 1 */ + uint32_t R; + struct { + uint32_t DMA63:1; /* Channel 63 DMA Enable */ + uint32_t DMA62:1; /* Channel 62 DMA Enable */ + uint32_t DMA61:1; /* Channel 61 DMA Enable */ + uint32_t DMA60:1; /* Channel 60 DMA Enable */ + uint32_t DMA59:1; /* Channel 59 DMA Enable */ + uint32_t DMA58:1; /* Channel 58 DMA Enable */ + uint32_t DMA57:1; /* Channel 57 DMA Enable */ + uint32_t DMA56:1; /* Channel 56 DMA Enable */ + uint32_t DMA55:1; /* Channel 55 DMA Enable */ + uint32_t DMA54:1; /* Channel 54 DMA Enable */ + uint32_t DMA53:1; /* Channel 53 DMA Enable */ + uint32_t DMA52:1; /* Channel 52 DMA Enable */ + uint32_t DMA51:1; /* Channel 51 DMA Enable */ + uint32_t DMA50:1; /* Channel 50 DMA Enable */ + uint32_t DMA49:1; /* Channel 49 DMA Enable */ + uint32_t DMA48:1; /* Channel 48 DMA Enable */ + uint32_t DMA47:1; /* Channel 47 DMA Enable */ + uint32_t DMA46:1; /* Channel 46 DMA Enable */ + uint32_t DMA45:1; /* Channel 45 DMA Enable */ + uint32_t DMA44:1; /* Channel 44 DMA Enable */ + uint32_t DMA43:1; /* Channel 43 DMA Enable */ + uint32_t DMA42:1; /* Channel 42 DMA Enable */ + uint32_t DMA41:1; /* Channel 41 DMA Enable */ + uint32_t DMA40:1; /* Channel 40 DMA Enable */ + uint32_t DMA39:1; /* Channel 39 DMA Enable */ + uint32_t DMA38:1; /* Channel 38 DMA Enable */ + uint32_t DMA37:1; /* Channel 37 DMA Enable */ + uint32_t DMA36:1; /* Channel 36 DMA Enable */ + uint32_t DMA35:1; /* Channel 35 DMA Enable */ + uint32_t DMA34:1; /* Channel 34 DMA Enable */ + uint32_t DMA33:1; /* Channel 33 DMA Enable */ + uint32_t DMA32:1; /* Channel 32 DMA Enable */ + } B; + } ADC_DMAR1_32B_tag; + + typedef union { /* DMA REGISTER 2 */ + uint32_t R; + struct { + uint32_t DMA95:1; /* Channel 95 DMA Enable */ + uint32_t DMA94:1; /* Channel 94 DMA Enable */ + uint32_t DMA93:1; /* Channel 93 DMA Enable */ + uint32_t DMA92:1; /* Channel 92 DMA Enable */ + uint32_t DMA91:1; /* Channel 91 DMA Enable */ + uint32_t DMA90:1; /* Channel 90 DMA Enable */ + uint32_t DMA89:1; /* Channel 89 DMA Enable */ + uint32_t DMA88:1; /* Channel 88 DMA Enable */ + uint32_t DMA87:1; /* Channel 87 DMA Enable */ + uint32_t DMA86:1; /* Channel 86 DMA Enable */ + uint32_t DMA85:1; /* Channel 85 DMA Enable */ + uint32_t DMA84:1; /* Channel 84 DMA Enable */ + uint32_t DMA83:1; /* Channel 83 DMA Enable */ + uint32_t DMA82:1; /* Channel 82 DMA Enable */ + uint32_t DMA81:1; /* Channel 81 DMA Enable */ + uint32_t DMA80:1; /* Channel 80 DMA Enable */ + uint32_t DMA79:1; /* Channel 79 DMA Enable */ + uint32_t DMA78:1; /* Channel 78 DMA Enable */ + uint32_t DMA77:1; /* Channel 77 DMA Enable */ + uint32_t DMA76:1; /* Channel 76 DMA Enable */ + uint32_t DMA75:1; /* Channel 75 DMA Enable */ + uint32_t DMA74:1; /* Channel 74 DMA Enable */ + uint32_t DMA73:1; /* Channel 73 DMA Enable */ + uint32_t DMA72:1; /* Channel 72 DMA Enable */ + uint32_t DMA71:1; /* Channel 71 DMA Enable */ + uint32_t DMA70:1; /* Channel 70 DMA Enable */ + uint32_t DMA69:1; /* Channel 69 DMA Enable */ + uint32_t DMA68:1; /* Channel 68 DMA Enable */ + uint32_t DMA67:1; /* Channel 67 DMA Enable */ + uint32_t DMA66:1; /* Channel 66 DMA Enable */ + uint32_t DMA65:1; /* Channel 65 DMA Enable */ + uint32_t DMA64:1; /* Channel 64 DMA Enable */ + } B; + } ADC_DMAR2_32B_tag; + + + /* Register layout for all registers TRC... */ + + typedef union { /* Threshold Control register C */ + uint32_t R; + struct { + uint32_t:16; + uint32_t THREN:1; /* Threshold enable */ + uint32_t THRINV:1; /* invert the output pin */ + uint32_t THROP:1; /* output pin register */ + uint32_t:6; + uint32_t THRCH:7; /* Choose channel for threshold register */ + } B; + } ADC_TRC_32B_tag; + + + /* Register layout for all registers THRHLR... */ + + typedef union { /* Upper Threshold register */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR_32B_tag; + + + /* Register layout for all registers THRALT... */ + + typedef union { /* alternate Upper Threshold register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t THRH:10; /* high threshold value s */ + uint32_t:6; + uint32_t THRL:10; /* low threshold value s */ + } B; + } ADC_THRALT_32B_tag; + + typedef union { /* PRESAMPLING CONTROL REGISTER */ + uint32_t R; + struct { + uint32_t:25; + uint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */ + uint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */ + uint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */ +#ifndef USE_FIELD_ALIASES_ADC + uint32_t PRECONV:1; /* Presampled value */ +#else + uint32_t PREONCE:1; /* deprecated name - please avoid */ +#endif + } B; + } ADC_PSCR_32B_tag; + + typedef union { /* Presampling Register 0 */ + uint32_t R; + struct { + uint32_t PRES31:1; /* Channel 31 Presampling Enable */ + uint32_t PRES30:1; /* Channel 30 Presampling Enable */ + uint32_t PRES29:1; /* Channel 29 Presampling Enable */ + uint32_t PRES28:1; /* Channel 28 Presampling Enable */ + uint32_t PRES27:1; /* Channel 27 Presampling Enable */ + uint32_t PRES26:1; /* Channel 26 Presampling Enable */ + uint32_t PRES25:1; /* Channel 25 Presampling Enable */ + uint32_t PRES24:1; /* Channel 24 Presampling Enable */ + uint32_t PRES23:1; /* Channel 23 Presampling Enable */ + uint32_t PRES22:1; /* Channel 22 Presampling Enable */ + uint32_t PRES21:1; /* Channel 21 Presampling Enable */ + uint32_t PRES20:1; /* Channel 20 Presampling Enable */ + uint32_t PRES19:1; /* Channel 19 Presampling Enable */ + uint32_t PRES18:1; /* Channel 18 Presampling Enable */ + uint32_t PRES17:1; /* Channel 17 Presampling Enable */ + uint32_t PRES16:1; /* Channel 16 Presampling Enable */ + uint32_t PRES15:1; /* Channel 15 Presampling Enable */ + uint32_t PRES14:1; /* Channel 14 Presampling Enable */ + uint32_t PRES13:1; /* Channel 13 Presampling Enable */ + uint32_t PRES12:1; /* Channel 12 Presampling Enable */ + uint32_t PRES11:1; /* Channel 11 Presampling Enable */ + uint32_t PRES10:1; /* Channel 10 Presampling Enable */ + uint32_t PRES9:1; /* Channel 9 Presampling Enable */ + uint32_t PRES8:1; /* Channel 8 Presampling Enable */ + uint32_t PRES7:1; /* Channel 7 Presampling Enable */ + uint32_t PRES6:1; /* Channel 6 Presampling Enable */ + uint32_t PRES5:1; /* Channel 5 Presampling Enable */ + uint32_t PRES4:1; /* Channel 4 Presampling Enable */ + uint32_t PRES3:1; /* Channel 3 Presampling Enable */ + uint32_t PRES2:1; /* Channel 2 Presampling Enable */ + uint32_t PRES1:1; /* Channel 1presampling Enable */ + uint32_t PRES0:1; /* Channel 0 Presampling Enable */ + } B; + } ADC_PSR0_32B_tag; + + typedef union { /* Presampling REGISTER 1 */ + uint32_t R; + struct { + uint32_t PRES63:1; /* Channel 63 Presampling Enable */ + uint32_t PRES62:1; /* Channel 62 Presampling Enable */ + uint32_t PRES61:1; /* Channel 61 Presampling Enable */ + uint32_t PRES60:1; /* Channel 60 Presampling Enable */ + uint32_t PRES59:1; /* Channel 59 Presampling Enable */ + uint32_t PRES58:1; /* Channel 58 Presampling Enable */ + uint32_t PRES57:1; /* Channel 57 Presampling Enable */ + uint32_t PRES56:1; /* Channel 56 Presampling Enable */ + uint32_t PRES55:1; /* Channel 55 Presampling Enable */ + uint32_t PRES54:1; /* Channel 54 Presampling Enable */ + uint32_t PRES53:1; /* Channel 53 Presampling Enable */ + uint32_t PRES52:1; /* Channel 52 Presampling Enable */ + uint32_t PRES51:1; /* Channel 51 Presampling Enable */ + uint32_t PRES50:1; /* Channel 50 Presampling Enable */ + uint32_t PRES49:1; /* Channel 49 Presampling Enable */ + uint32_t PRES48:1; /* Channel 48 Presampling Enable */ + uint32_t PRES47:1; /* Channel 47 Presampling Enable */ + uint32_t PRES46:1; /* Channel 46 Presampling Enable */ + uint32_t PRES45:1; /* Channel 45 Presampling Enable */ + uint32_t PRES44:1; /* Channel 44 Presampling Enable */ + uint32_t PRES43:1; /* Channel 43 Presampling Enable */ + uint32_t PRES42:1; /* Channel 42 Presampling Enable */ + uint32_t PRES41:1; /* Channel 41 Presampling Enable */ + uint32_t PRES40:1; /* Channel 40 Presampling Enable */ + uint32_t PRES39:1; /* Channel 39 Presampling Enable */ + uint32_t PRES38:1; /* Channel 38 Presampling Enable */ + uint32_t PRES37:1; /* Channel 37 Presampling Enable */ + uint32_t PRES36:1; /* Channel 36 Presampling Enable */ + uint32_t PRES35:1; /* Channel 35 Presampling Enable */ + uint32_t PRES34:1; /* Channel 34 Presampling Enable */ + uint32_t PRES33:1; /* Channel 33 Presampling Enable */ + uint32_t PRES32:1; /* Channel 32 Presampling Enable */ + } B; + } ADC_PSR1_32B_tag; + + typedef union { /* Presampling REGISTER 2 */ + uint32_t R; + struct { + uint32_t PRES95:1; /* Channel 95 Presampling Enable */ + uint32_t PRES94:1; /* Channel 94 Presampling Enable */ + uint32_t PRES93:1; /* Channel 93 Presampling Enable */ + uint32_t PRES92:1; /* Channel 92 Presampling Enable */ + uint32_t PRES91:1; /* Channel 91 Presampling Enable */ + uint32_t PRES90:1; /* Channel 90 Presampling Enable */ + uint32_t PRES89:1; /* Channel 89 Presampling Enable */ + uint32_t PRES88:1; /* Channel 88 Presampling Enable */ + uint32_t PRES87:1; /* Channel 87 Presampling Enable */ + uint32_t PRES86:1; /* Channel 86 Presampling Enable */ + uint32_t PRES85:1; /* Channel 85 Presampling Enable */ + uint32_t PRES84:1; /* Channel 84 Presampling Enable */ + uint32_t PRES83:1; /* Channel 83 Presampling Enable */ + uint32_t PRES82:1; /* Channel 82 Presampling Enable */ + uint32_t PRES81:1; /* Channel 81 Presampling Enable */ + uint32_t PRES80:1; /* Channel 80 Presampling Enable */ + uint32_t PRES79:1; /* Channel 79 Presampling Enable */ + uint32_t PRES78:1; /* Channel 78 Presampling Enable */ + uint32_t PRES77:1; /* Channel 77 Presampling Enable */ + uint32_t PRES76:1; /* Channel 76 Presampling Enable */ + uint32_t PRES75:1; /* Channel 75 Presampling Enable */ + uint32_t PRES74:1; /* Channel 74 Presampling Enable */ + uint32_t PRES73:1; /* Channel 73 Presampling Enable */ + uint32_t PRES72:1; /* Channel 72 Presampling Enable */ + uint32_t PRES71:1; /* Channel 71 Presampling Enable */ + uint32_t PRES70:1; /* Channel 70 Presampling Enable */ + uint32_t PRES69:1; /* Channel 69 Presampling Enable */ + uint32_t PRES68:1; /* Channel 68 Presampling Enable */ + uint32_t PRES67:1; /* Channel 67 Presampling Enable */ + uint32_t PRES66:1; /* Channel 66 Presampling Enable */ + uint32_t PRES65:1; /* Channel 65 Presampling Enable */ + uint32_t PRES64:1; /* Channel 64 Presampling Enable */ + } B; + } ADC_PSR2_32B_tag; + + + /* Register layout for all registers CTR... */ + + typedef union { /* conversion timing register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */ + uint32_t:1; + uint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */ + uint32_t:1; + uint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */ + uint32_t:1; +#ifndef USE_FIELD_ALIASES_ADC + uint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */ +#else + uint32_t INPSAMP:8; +#endif + } B; + } ADC_CTR_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */ + uint32_t R; + struct { + uint32_t CH31:1; /* Channel 31 Normal Sampling Enable */ + uint32_t CH30:1; /* Channel 30 Normal Sampling Enable */ + uint32_t CH29:1; /* Channel 29 Normal Sampling Enable */ + uint32_t CH28:1; /* Channel 28 Normal Sampling Enable */ + uint32_t CH27:1; /* Channel 27 Normal Sampling Enable */ + uint32_t CH26:1; /* Channel 26 Normal Sampling Enable */ + uint32_t CH25:1; /* Channel 25 Normal Sampling Enable */ + uint32_t CH24:1; /* Channel 24 Normal Sampling Enable */ + uint32_t CH23:1; /* Channel 23 Normal Sampling Enable */ + uint32_t CH22:1; /* Channel 22 Normal Sampling Enable */ + uint32_t CH21:1; /* Channel 21 Normal Sampling Enable */ + uint32_t CH20:1; /* Channel 20 Normal Sampling Enable */ + uint32_t CH19:1; /* Channel 19 Normal Sampling Enable */ + uint32_t CH18:1; /* Channel 18 Normal Sampling Enable */ + uint32_t CH17:1; /* Channel 17 Normal Sampling Enable */ + uint32_t CH16:1; /* Channel 16 Normal Sampling Enable */ + uint32_t CH15:1; /* Channel 15 Normal Sampling Enable */ + uint32_t CH14:1; /* Channel 14 Normal Sampling Enable */ + uint32_t CH13:1; /* Channel 13 Normal Sampling Enable */ + uint32_t CH12:1; /* Channel 12 Normal Sampling Enable */ + uint32_t CH11:1; /* Channel 11 Normal Sampling Enable */ + uint32_t CH10:1; /* Channel 10 Normal Sampling Enable */ + uint32_t CH9:1; /* Channel 9 Normal Sampling Enable */ + uint32_t CH8:1; /* Channel 8 Normal Sampling Enable */ + uint32_t CH7:1; /* Channel 7 Normal Sampling Enable */ + uint32_t CH6:1; /* Channel 6 Normal Sampling Enable */ + uint32_t CH5:1; /* Channel 5 Normal Sampling Enable */ + uint32_t CH4:1; /* Channel 4 Normal Sampling Enable */ + uint32_t CH3:1; /* Channel 3 Normal Sampling Enable */ + uint32_t CH2:1; /* Channel 2 Normal Sampling Enable */ + uint32_t CH1:1; /* Channel 1 Normal Sampling Enable */ + uint32_t CH0:1; /* Channel 0 Normal Sampling Enable */ + } B; + } ADC_NCMR0_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */ + uint32_t R; + struct { + uint32_t CH63:1; /* Channel 63 Normal Sampling Enable */ + uint32_t CH62:1; /* Channel 62 Normal Sampling Enable */ + uint32_t CH61:1; /* Channel 61 Normal Sampling Enable */ + uint32_t CH60:1; /* Channel 60 Normal Sampling Enable */ + uint32_t CH59:1; /* Channel 59 Normal Sampling Enable */ + uint32_t CH58:1; /* Channel 58 Normal Sampling Enable */ + uint32_t CH57:1; /* Channel 57 Normal Sampling Enable */ + uint32_t CH56:1; /* Channel 56 Normal Sampling Enable */ + uint32_t CH55:1; /* Channel 55 Normal Sampling Enable */ + uint32_t CH54:1; /* Channel 54 Normal Sampling Enable */ + uint32_t CH53:1; /* Channel 53 Normal Sampling Enable */ + uint32_t CH52:1; /* Channel 52 Normal Sampling Enable */ + uint32_t CH51:1; /* Channel 51 Normal Sampling Enable */ + uint32_t CH50:1; /* Channel 50 Normal Sampling Enable */ + uint32_t CH49:1; /* Channel 49 Normal Sampling Enable */ + uint32_t CH48:1; /* Channel 48 Normal Sampling Enable */ + uint32_t CH47:1; /* Channel 47 Normal Sampling Enable */ + uint32_t CH46:1; /* Channel 46 Normal Sampling Enable */ + uint32_t CH45:1; /* Channel 45 Normal Sampling Enable */ + uint32_t CH44:1; /* Channel 44 Normal Sampling Enable */ + uint32_t CH43:1; /* Channel 43 Normal Sampling Enable */ + uint32_t CH42:1; /* Channel 42 Normal Sampling Enable */ + uint32_t CH41:1; /* Channel 41 Normal Sampling Enable */ + uint32_t CH40:1; /* Channel 40 Normal Sampling Enable */ + uint32_t CH39:1; /* Channel 39 Normal Sampling Enable */ + uint32_t CH38:1; /* Channel 38 Normal Sampling Enable */ + uint32_t CH37:1; /* Channel 37 Normal Sampling Enable */ + uint32_t CH36:1; /* Channel 36 Normal Sampling Enable */ + uint32_t CH35:1; /* Channel 35 Normal Sampling Enable */ + uint32_t CH34:1; /* Channel 34 Normal Sampling Enable */ + uint32_t CH33:1; /* Channel 33 Normal Sampling Enable */ + uint32_t CH32:1; /* Channel 32 Normal Sampling Enable */ + } B; + } ADC_NCMR1_32B_tag; + + typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */ + uint32_t R; + struct { + uint32_t CH95:1; /* Channel 95 Normal Sampling Enable */ + uint32_t CH94:1; /* Channel 94 Normal Sampling Enable */ + uint32_t CH93:1; /* Channel 93 Normal Sampling Enable */ + uint32_t CH92:1; /* Channel 92 Normal Sampling Enable */ + uint32_t CH91:1; /* Channel 91 Normal Sampling Enable */ + uint32_t CH90:1; /* Channel 90 Normal Sampling Enable */ + uint32_t CH89:1; /* Channel 89 Normal Sampling Enable */ + uint32_t CH88:1; /* Channel 88 Normal Sampling Enable */ + uint32_t CH87:1; /* Channel 87 Normal Sampling Enable */ + uint32_t CH86:1; /* Channel 86 Normal Sampling Enable */ + uint32_t CH85:1; /* Channel 85 Normal Sampling Enable */ + uint32_t CH84:1; /* Channel 84 Normal Sampling Enable */ + uint32_t CH83:1; /* Channel 83 Normal Sampling Enable */ + uint32_t CH82:1; /* Channel 82 Normal Sampling Enable */ + uint32_t CH81:1; /* Channel 81 Normal Sampling Enable */ + uint32_t CH80:1; /* Channel 80 Normal Sampling Enable */ + uint32_t CH79:1; /* Channel 79 Normal Sampling Enable */ + uint32_t CH78:1; /* Channel 78 Normal Sampling Enable */ + uint32_t CH77:1; /* Channel 77 Normal Sampling Enable */ + uint32_t CH76:1; /* Channel 76 Normal Sampling Enable */ + uint32_t CH75:1; /* Channel 75 Normal Sampling Enable */ + uint32_t CH74:1; /* Channel 74 Normal Sampling Enable */ + uint32_t CH73:1; /* Channel 73 Normal Sampling Enable */ + uint32_t CH72:1; /* Channel 72 Normal Sampling Enable */ + uint32_t CH71:1; /* Channel 71 Normal Sampling Enable */ + uint32_t CH70:1; /* Channel 70 Normal Sampling Enable */ + uint32_t CH69:1; /* Channel 69 Normal Sampling Enable */ + uint32_t CH68:1; /* Channel 68 Normal Sampling Enable */ + uint32_t CH67:1; /* Channel 67 Normal Sampling Enable */ + uint32_t CH66:1; /* Channel 66 Normal Sampling Enable */ + uint32_t CH65:1; /* Channel 65 Normal Sampling Enable */ + uint32_t CH64:1; /* Channel 64 Normal Sampling Enable */ + } B; + } ADC_NCMR2_32B_tag; + + typedef union { /* Injected Conversion Mask Register 0 */ + uint32_t R; + struct { + uint32_t CH31:1; /* Channel 31 Injected Sampling Enable */ + uint32_t CH30:1; /* Channel 30 Injected Sampling Enable */ + uint32_t CH29:1; /* Channel 29 Injected Sampling Enable */ + uint32_t CH28:1; /* Channel 28 Injected Sampling Enable */ + uint32_t CH27:1; /* Channel 27 Injected Sampling Enable */ + uint32_t CH26:1; /* Channel 26 Injected Sampling Enable */ + uint32_t CH25:1; /* Channel 25 Injected Sampling Enable */ + uint32_t CH24:1; /* Channel 24 Injected Sampling Enable */ + uint32_t CH23:1; /* Channel 23 Injected Sampling Enable */ + uint32_t CH22:1; /* Channel 22 Injected Sampling Enable */ + uint32_t CH21:1; /* Channel 21 Injected Sampling Enable */ + uint32_t CH20:1; /* Channel 20 Injected Sampling Enable */ + uint32_t CH19:1; /* Channel 19 Injected Sampling Enable */ + uint32_t CH18:1; /* Channel 18 Injected Sampling Enable */ + uint32_t CH17:1; /* Channel 17 Injected Sampling Enable */ + uint32_t CH16:1; /* Channel 16 Injected Sampling Enable */ + uint32_t CH15:1; /* Channel 15 Injected Sampling Enable */ + uint32_t CH14:1; /* Channel 14 Injected Sampling Enable */ + uint32_t CH13:1; /* Channel 13 Injected Sampling Enable */ + uint32_t CH12:1; /* Channel 12 Injected Sampling Enable */ + uint32_t CH11:1; /* Channel 11 Injected Sampling Enable */ + uint32_t CH10:1; /* Channel 10 Injected Sampling Enable */ + uint32_t CH9:1; /* Channel 9 Injected Sampling Enable */ + uint32_t CH8:1; /* Channel 8 Injected Sampling Enable */ + uint32_t CH7:1; /* Channel 7 Injected Sampling Enable */ + uint32_t CH6:1; /* Channel 6 Injected Sampling Enable */ + uint32_t CH5:1; /* Channel 5 Injected Sampling Enable */ + uint32_t CH4:1; /* Channel 4 Injected Sampling Enable */ + uint32_t CH3:1; /* Channel 3 Injected Sampling Enable */ + uint32_t CH2:1; /* Channel 2 Injected Sampling Enable */ + uint32_t CH1:1; /* Channel 1 injected Sampling Enable */ + uint32_t CH0:1; /* Channel 0 injected Sampling Enable */ + } B; + } ADC_JCMR0_32B_tag; + + typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */ + uint32_t R; + struct { + uint32_t CH63:1; /* Channel 63 Injected Sampling Enable */ + uint32_t CH62:1; /* Channel 62 Injected Sampling Enable */ + uint32_t CH61:1; /* Channel 61 Injected Sampling Enable */ + uint32_t CH60:1; /* Channel 60 Injected Sampling Enable */ + uint32_t CH59:1; /* Channel 59 Injected Sampling Enable */ + uint32_t CH58:1; /* Channel 58 Injected Sampling Enable */ + uint32_t CH57:1; /* Channel 57 Injected Sampling Enable */ + uint32_t CH56:1; /* Channel 56 Injected Sampling Enable */ + uint32_t CH55:1; /* Channel 55 Injected Sampling Enable */ + uint32_t CH54:1; /* Channel 54 Injected Sampling Enable */ + uint32_t CH53:1; /* Channel 53 Injected Sampling Enable */ + uint32_t CH52:1; /* Channel 52 Injected Sampling Enable */ + uint32_t CH51:1; /* Channel 51 Injected Sampling Enable */ + uint32_t CH50:1; /* Channel 50 Injected Sampling Enable */ + uint32_t CH49:1; /* Channel 49 Injected Sampling Enable */ + uint32_t CH48:1; /* Channel 48 Injected Sampling Enable */ + uint32_t CH47:1; /* Channel 47 Injected Sampling Enable */ + uint32_t CH46:1; /* Channel 46 Injected Sampling Enable */ + uint32_t CH45:1; /* Channel 45 Injected Sampling Enable */ + uint32_t CH44:1; /* Channel 44 Injected Sampling Enable */ + uint32_t CH43:1; /* Channel 43 Injected Sampling Enable */ + uint32_t CH42:1; /* Channel 42 Injected Sampling Enable */ + uint32_t CH41:1; /* Channel 41 Injected Sampling Enable */ + uint32_t CH40:1; /* Channel 40 Injected Sampling Enable */ + uint32_t CH39:1; /* Channel 39 Injected Sampling Enable */ + uint32_t CH38:1; /* Channel 38 Injected Sampling Enable */ + uint32_t CH37:1; /* Channel 37 Injected Sampling Enable */ + uint32_t CH36:1; /* Channel 36 Injected Sampling Enable */ + uint32_t CH35:1; /* Channel 35 Injected Sampling Enable */ + uint32_t CH34:1; /* Channel 34 Injected Sampling Enable */ + uint32_t CH33:1; /* Channel 33 Injected Sampling Enable */ + uint32_t CH32:1; /* Channel 32 Injected Sampling Enable */ + } B; + } ADC_JCMR1_32B_tag; + + typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */ + uint32_t R; + struct { + uint32_t CH95:1; /* Channel 95 Injected Sampling Enable */ + uint32_t CH94:1; /* Channel 94 Injected Sampling Enable */ + uint32_t CH93:1; /* Channel 93 Injected Sampling Enable */ + uint32_t CH92:1; /* Channel 92 Injected Sampling Enable */ + uint32_t CH91:1; /* Channel 91 Injected Sampling Enable */ + uint32_t CH90:1; /* Channel 90 Injected Sampling Enable */ + uint32_t CH89:1; /* Channel 89 Injected Sampling Enable */ + uint32_t CH88:1; /* Channel 88 Injected Sampling Enable */ + uint32_t CH87:1; /* Channel 87 Injected Sampling Enable */ + uint32_t CH86:1; /* Channel 86 Injected Sampling Enable */ + uint32_t CH85:1; /* Channel 85 Injected Sampling Enable */ + uint32_t CH84:1; /* Channel 84 Injected Sampling Enable */ + uint32_t CH83:1; /* Channel 83 Injected Sampling Enable */ + uint32_t CH82:1; /* Channel 82 Injected Sampling Enable */ + uint32_t CH81:1; /* Channel 81 Injected Sampling Enable */ + uint32_t CH80:1; /* Channel 80 Injected Sampling Enable */ + uint32_t CH79:1; /* Channel 79 Injected Sampling Enable */ + uint32_t CH78:1; /* Channel 78 Injected Sampling Enable */ + uint32_t CH77:1; /* Channel 77 Injected Sampling Enable */ + uint32_t CH76:1; /* Channel 76 Injected Sampling Enable */ + uint32_t CH75:1; /* Channel 75 Injected Sampling Enable */ + uint32_t CH74:1; /* Channel 74 Injected Sampling Enable */ + uint32_t CH73:1; /* Channel 73 Injected Sampling Enable */ + uint32_t CH72:1; /* Channel 72 Injected Sampling Enable */ + uint32_t CH71:1; /* Channel 71 Injected Sampling Enable */ + uint32_t CH70:1; /* Channel 70 Injected Sampling Enable */ + uint32_t CH69:1; /* Channel 69 Injected Sampling Enable */ + uint32_t CH68:1; /* Channel 68 Injected Sampling Enable */ + uint32_t CH67:1; /* Channel 67 Injected Sampling Enable */ + uint32_t CH66:1; /* Channel 66 Injected Sampling Enable */ + uint32_t CH65:1; /* Channel 65 Injected Sampling Enable */ + uint32_t CH64:1; /* Channel 64 Injected Sampling Enable */ + } B; + } ADC_JCMR2_32B_tag; + + typedef union { /* Offset Word Regsiter */ + uint32_t R; + struct { + uint32_t:15; + uint32_t OFFSETLOAD:1; /* load_offset */ + uint32_t:8; +#ifndef USE_FIELD_ALIASES_ADC + uint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */ +#else + uint32_t OFFSETWORD:8; +#endif + } B; + } ADC_OFFWR_32B_tag; + + typedef union { /* Decode Signal Delay Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t DSD:8; /* take into account the settling time of the external mux */ + } B; + } ADC_DSDR_32B_tag; + + typedef union { /* Power Down Dealy Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */ + } B; + } ADC_PDEDR_32B_tag; + + + /* Register layout for all registers CDR... */ + + typedef union { /* CHANNEL DATA REGS */ + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; /* validity of data */ + uint32_t OVERW:1; /* overwrite data */ + uint32_t RESULT:2; /* reflects mode conversion */ + uint32_t:6; + uint32_t CDATA:10; /* Channel 0 converted data */ + } B; + } ADC_CDR_32B_tag; + + typedef union { /* Upper Threshold register 4 is not contiguous to 3 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR4_32B_tag; + + typedef union { /* Upper Threshold register 5 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR5_32B_tag; + + typedef union { /* Upper Threshold register 6 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR6_32B_tag; + + typedef union { /* Upper Threshold register 7 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR7_32B_tag; + + typedef union { /* Upper Threshold register 8 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR8_32B_tag; + + typedef union { /* Upper Threshold register 9 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR9_32B_tag; + + typedef union { /* Upper Threshold register 10 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR10_32B_tag; + + typedef union { /* Upper Threshold register 11 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR11_32B_tag; + + typedef union { /* Upper Threshold register 12 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR12_32B_tag; + + typedef union { /* Upper Threshold register 13 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR13_32B_tag; + + typedef union { /* Upper Threshold register 14 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR14_32B_tag; + + typedef union { /* Upper Threshold register 15 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* high threshold value s */ + uint32_t:4; + uint32_t THRL:12; /* low threshold value s */ + } B; + } ADC_THRHLR15_32B_tag; + + + /* Register layout for all registers CWSELR... */ + + typedef union { /* Channel Watchdog Select register */ + uint32_t R; + struct { + uint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */ + uint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */ + uint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */ + uint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */ + uint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */ + uint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */ + uint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */ + uint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */ + } B; + } ADC_CWSELR_32B_tag; + + + /* Register layout for all registers CWENR... */ + + typedef union { /* Channel Watchdog Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + uint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */ + } B; + } ADC_CWENR_32B_tag; + + + /* Register layout for all registers AWORR... */ + + typedef union { /* Analog Watchdog Out of Range Register */ + uint32_t R; + struct { + uint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */ + uint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */ + uint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */ + uint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */ + uint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */ + uint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */ + uint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */ + uint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */ + uint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */ + uint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */ + uint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */ + uint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */ + uint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */ + uint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */ + uint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */ + uint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */ + uint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */ + uint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */ + uint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */ + uint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */ + uint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */ + uint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */ + uint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */ + uint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */ + uint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */ + uint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */ + uint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */ + uint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */ + uint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */ + uint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */ + uint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */ + uint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */ + } B; + } ADC_AWORR_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */ + uint32_t R; + struct { + uint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */ + uint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */ + uint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */ + uint32_t:5; + uint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */ + uint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */ + } B; + } ADC_STCR1_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SERR:1; /* Error fault injection bit (write only) */ + uint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */ + uint32_t:1; + uint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */ + uint32_t:4; + uint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */ + uint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */ + uint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */ + uint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */ + uint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */ + uint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */ + uint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */ + uint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */ + uint32_t:3; + uint32_t EN:1; /* Self testing channel enable */ + uint32_t:4; + uint32_t FMA_C:1; /* Fault mapping for the algorithm C */ + uint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */ + uint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */ + } B; + } ADC_STCR2_32B_tag; + + typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */ + uint32_t R; + struct { + uint32_t:22; + uint32_t ALG:2; /* Algorithm scheduling */ + uint32_t:8; + } B; + } ADC_STCR3_32B_tag; + + typedef union { /* SELF TEST BAUD RATE REGISTER */ + uint32_t R; + struct { + uint32_t:13; + uint32_t WDT:3; /* Watchdog timer value */ + uint32_t:8; + uint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */ + } B; + } ADC_STBRR_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 1 */ + uint32_t R; + struct { + uint32_t:6; + uint32_t WDTERR:1; /* Watchdog timer error */ + uint32_t OVERWR:1; /* Overwrite error */ + uint32_t ST_EOC:1; /* Self test EOC bit */ + uint32_t:4; + uint32_t WDG_EOA_C:1; /* Algorithm C completed without error */ + uint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */ + uint32_t WDG_EOA_S:1; /* Algorithm S completed without error */ + uint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */ + uint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */ + uint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */ + uint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */ + uint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */ + uint32_t:1; + uint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */ + uint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */ + } B; + } ADC_STSR1_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 2 */ + uint32_t R; + struct { + uint32_t OVFL:1; /* Overflow bit */ + uint32_t:3; + uint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */ + uint32_t:4; + uint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */ + } B; + } ADC_STSR2_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 3 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */ + uint32_t:4; + uint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */ + } B; + } ADC_STSR3_32B_tag; + + typedef union { /* SELF TEST STATUS REGISTER 4 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */ + uint32_t:4; + uint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */ + } B; + } ADC_STSR4_32B_tag; + + typedef union { /* SELF TEST DATA REGISTER 1 */ + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; /* Valid data */ + uint32_t OVERWR:1; /* Overwrite data */ + uint32_t:6; + uint32_t TCDATA:12; /* Test channel converted data */ + } B; + } ADC_STDR1_32B_tag; + + typedef union { /* SELF TEST DATA REGISTER 2 */ + uint32_t R; + struct { + uint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */ + uint32_t VALID:1; /* Valid data */ + uint32_t OVERWR:1; /* Overwrite data */ + uint32_t:6; + uint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */ + } B; + } ADC_STDR2_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */ + uint32_t:2; + uint32_t THRH:12; /* High threshold value for channel 0 */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for channel 0 */ + } B; + } ADC_STAW0R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + uint32_t:3; + uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ + } B; + } ADC_STAW1AR_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* High threshold value for test channel - algorithm S */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */ + } B; + } ADC_STAW1BR_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */ + uint32_t:19; + uint32_t THRL:12; /* Low threshold value for channel */ + } B; + } ADC_STAW2R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */ + uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */ + uint32_t:2; + uint32_t THRH:12; /* High threshold value for channel 3 */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for channel 3 */ + } B; + } ADC_STAW3R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ + uint32_t R; + struct { + uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */ + uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */ + uint32_t:2; + uint32_t THRH:12; /* High threshold value for channel 4 */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for channel 4 */ + } B; + } ADC_STAW4R_32B_tag; + + typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ + uint32_t R; + struct { + uint32_t:4; + uint32_t THRH:12; /* High threshold value for algorithm C */ + uint32_t:4; + uint32_t THRL:12; /* Low threshold value for algorithm C */ + } B; + } ADC_STAW5R_32B_tag; + + + + typedef struct ADC_struct_tag { /* start of ADC_tag */ + /* module configuration register */ + ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + /* module status register */ + ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */ + int8_t ADC_reserved_0008[8]; + /* Interrupt status register */ + ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */ + union { + ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */ + + struct { + /* CHANNEL PENDING REGISTER 0 */ + ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */ + /* CHANNEL PENDING REGISTER 1 */ + ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */ + /* CHANNEL PENDING REGISTER 2 */ + ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */ + }; + + }; + /* interrupt mask register */ + ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */ + union { + ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */ + + struct { + /* CHANNEL INTERRUPT MASK REGISTER 0 */ + ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */ + /* CHANNEL INTERRUPT MASK REGISTER 1 */ + ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */ + /* CHANNEL INTERRUPT MASK REGISTER 2 */ + ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */ + }; + + }; + /* Watchdog Threshold interrupt status register */ + ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */ + /* Watchdog interrupt MASK register */ + ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */ + int8_t ADC_reserved_0038[8]; + /* DMAE register */ + ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */ + union { + ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */ + + struct { + /* DMA REGISTER 0 */ + ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */ + /* DMA REGISTER 1 */ + ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */ + /* DMA REGISTER 2 */ + ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */ + }; + + }; + union { + /* Threshold Control register C */ + ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */ + + struct { + /* Threshold Control register C */ + ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */ + ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */ + ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */ + ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */ + }; + + }; + union { + /* Upper Threshold register */ + ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */ + + struct { + /* Upper Threshold register */ + ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */ + ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */ + }; + + }; + union { + /* alternate Upper Threshold register */ + ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */ + + struct { + /* alternate Upper Threshold register */ + ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */ + ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */ + ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */ + ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */ + }; + + }; + /* PRESAMPLING CONTROL REGISTER */ + ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */ + union { + ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */ + + struct { + /* Presampling Register 0 */ + ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */ + /* Presampling REGISTER 1 */ + ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */ + /* Presampling REGISTER 2 */ + ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */ + }; + + }; + int8_t ADC_reserved_0090_C[4]; + union { + /* conversion timing register */ + ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */ + + struct { + /* conversion timing register */ + ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */ + ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */ + ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */ + }; + + }; + int8_t ADC_reserved_00A0_C[4]; + union { + ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */ + + struct { + /* NORMAL CONVERSION MASK REGISTER 0 */ + ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */ + /* NORMAL CONVERSION MASK REGISTER 1 */ + ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */ + /* NORMAL CONVERSION MASK REGISTER 2 */ + ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */ + }; + + }; + int8_t ADC_reserved_00B0_C[4]; + union { + ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */ + + struct { + /* Injected Conversion Mask Register 0 */ + ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */ + /* INJECTED CONVERSION MASK REGISTER 1 */ + ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */ + /* INJECTED CONVERSION MASK REGISTER 2 */ + ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */ + }; + + }; + /* Offset Word Regsiter */ + ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */ + /* Decode Signal Delay Register */ + ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */ + /* Power Down Dealy Register */ + ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */ + int8_t ADC_reserved_00CC_C[52]; + union { + /* CHANNEL DATA REGS */ + ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */ + + struct { + /* CHANNEL DATA REGS */ + ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */ + ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */ + ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */ + ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */ + ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */ + ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */ + ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */ + ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */ + ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */ + ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */ + ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */ + ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */ + ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */ + ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */ + ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */ + ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */ + ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */ + ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */ + ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */ + ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */ + ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */ + ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */ + ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */ + ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */ + ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */ + ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */ + ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */ + ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */ + ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */ + ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */ + ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */ + ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */ + ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */ + ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */ + ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */ + ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */ + ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */ + ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */ + ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */ + ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */ + ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */ + ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */ + ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */ + ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */ + ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */ + ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */ + ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */ + ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */ + ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */ + ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */ + ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */ + ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */ + ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */ + ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */ + ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */ + ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */ + ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */ + ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */ + ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */ + ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */ + ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */ + ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */ + ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */ + ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */ + ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */ + ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */ + ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */ + ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */ + ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */ + ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */ + ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */ + ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */ + ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */ + ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */ + ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */ + ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */ + ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */ + ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */ + ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */ + ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */ + ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */ + ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */ + ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */ + ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */ + ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */ + ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */ + ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */ + ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */ + ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */ + ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */ + ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */ + ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */ + ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */ + ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */ + ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */ + ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */ + }; + + }; + /* Upper Threshold register 4 is not contiguous to 3 */ + ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */ + /* Upper Threshold register 5 */ + ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */ + /* Upper Threshold register 6 */ + ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */ + /* Upper Threshold register 7 */ + ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */ + /* Upper Threshold register 8 */ + ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */ + /* Upper Threshold register 9 */ + ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */ + /* Upper Threshold register 10 */ + ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */ + /* Upper Threshold register 11 */ + ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */ + /* Upper Threshold register 12 */ + ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */ + /* Upper Threshold register 13 */ + ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */ + /* Upper Threshold register 14 */ + ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */ + /* Upper Threshold register 15 */ + ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */ + union { + /* Channel Watchdog Select register */ + ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */ + + struct { + /* Channel Watchdog Select register */ + ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */ + ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */ + }; + + }; + union { + /* Channel Watchdog Enable Register */ + ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */ + + struct { + /* Channel Watchdog Enable Register */ + ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */ + ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */ + ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */ + }; + + }; + int8_t ADC_reserved_02EC_C[4]; + union { + /* Analog Watchdog Out of Range Register */ + ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */ + + struct { + /* Analog Watchdog Out of Range Register */ + ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */ + ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */ + ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */ + }; + + }; + int8_t ADC_reserved_02FC[68]; + /* SELF TEST CONFIGURATION REGISTER 1 */ + ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */ + /* SELF TEST CONFIGURATION REGISTER 2 */ + ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */ + /* SELF TEST CONFIGURATION REGISTER 3 */ + ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */ + /* SELF TEST BAUD RATE REGISTER */ + ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */ + /* SELF TEST STATUS REGISTER 1 */ + ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */ + /* SELF TEST STATUS REGISTER 2 */ + ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */ + /* SELF TEST STATUS REGISTER 3 */ + ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */ + /* SELF TEST STATUS REGISTER 4 */ + ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */ + int8_t ADC_reserved_0360[16]; + /* SELF TEST DATA REGISTER 1 */ + ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */ + /* SELF TEST DATA REGISTER 2 */ + ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */ + int8_t ADC_reserved_0378[8]; + /* SELF TEST ANALOG WATCHDOG REGISTER 0 */ + ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 1A */ + ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 1B */ + ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 2 */ + ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 3 */ + ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 4 */ + ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */ + /* SELF TEST ANALOG WATCHDOG REGISTER 5 */ + ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */ + } ADC_tag; + + +#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL) +#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL) + + + +/****************************************************************/ +/* */ +/* Module: CTU */ +/* */ +/****************************************************************/ + + typedef union { /* Trigger Generator Subunit Input Selection register */ + uint32_t R; + struct { + uint32_t I15_FE:1; /* ext_signal Falling Edge */ + uint32_t I15_RE:1; /* ext_signal Rising Edge */ + uint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */ + uint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */ + uint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */ + uint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */ + uint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */ + uint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */ + uint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */ + uint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */ + uint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */ + uint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */ + uint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */ + uint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */ + uint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */ + uint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */ + uint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */ + uint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */ + uint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */ + uint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */ + uint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */ + uint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */ + uint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */ + uint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */ + uint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */ + uint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */ + uint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */ + uint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */ + uint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */ + uint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */ + uint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */ + uint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */ + } B; + } CTU_TGSISR_32B_tag; + + typedef union { /* Trigger Generator Subunit Control Register */ + uint16_t R; + struct { + uint16_t:7; +#ifndef USE_FIELD_ALIASES_CTU + uint16_t ET_TM:1; /* Toggle Mode Enable */ +#else + uint16_t ETTM:1; /* deprecated name - please avoid */ +#endif + uint16_t PRES:2; /* TGS Prescaler Selection */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */ +#else + uint16_t MRSSM:5; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t TGS_M:1; /* Trigger Generator Subunit Mode */ +#else + uint16_t TGSM:1; /* deprecated name - please avoid */ +#endif + } B; + } CTU_TGSCR_16B_tag; + + typedef union { /* */ + uint16_t R; + } CTU_TCR_16B_tag; + + typedef union { /* TGS Counter Compare Register */ + uint16_t R; +#ifndef USE_FIELD_ALIASES_CTU + struct { + uint16_t TGSCCV:16; /* deprecated field -- do not use */ + } B; +#endif + } CTU_TGSCCR_16B_tag; + + typedef union { /* TGS Counter Reload Register */ + uint16_t R; +#ifndef USE_FIELD_ALIASES_CTU + struct { + uint16_t TGSCRV:16; /* deprecated field -- do not use */ + } B; +#endif + } CTU_TGSCRR_16B_tag; + + typedef union { /* Commands List Control Register 1 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t T3INDEX:5; /* Trigger 3 First Command address */ + uint32_t:3; + uint32_t T2INDEX:5; /* Trigger 2 First Command address */ + uint32_t:3; + uint32_t T1INDEX:5; /* Trigger 1 First Command address */ + uint32_t:3; + uint32_t T0INDEX:5; /* Trigger 0 First Command address */ + } B; + } CTU_CLCR1_32B_tag; + + typedef union { /* Commands List Control Register 2 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t T7INDEX:5; /* Trigger 7 First Command address */ + uint32_t:3; + uint32_t T6INDEX:5; /* Trigger 6 First Command address */ + uint32_t:3; + uint32_t T5INDEX:5; /* Trigger 5 First Command address */ + uint32_t:3; + uint32_t T4INDEX:5; /* Trigger 4 First Command address */ + } B; + } CTU_CLCR2_32B_tag; + + typedef union { /* Trigger Handler Control Register 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t T3_E:1; /* Trigger 3 enable */ + uint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */ + uint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */ + uint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */ + uint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */ + uint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */ + uint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */ + uint32_t:1; + uint32_t T2_E:1; /* Trigger 2 enable */ + uint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */ + uint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */ + uint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */ + uint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */ + uint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */ + uint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */ + uint32_t:1; + uint32_t T1_E:1; /* Trigger 1 enable */ + uint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */ + uint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */ + uint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */ + uint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */ + uint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */ + uint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */ + uint32_t:1; + uint32_t T0_E:1; /* Trigger 0 enable */ + uint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */ + uint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */ + uint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */ + uint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */ + uint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */ + uint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */ + } B; + } CTU_THCR1_32B_tag; + + typedef union { /* Trigger Handler Control Register 2 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t T7_E:1; /* Trigger 7 enable */ + uint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */ + uint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */ + uint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */ + uint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */ + uint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */ + uint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */ + uint32_t:1; + uint32_t T6_E:1; /* Trigger 6 enable */ + uint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */ + uint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */ + uint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */ + uint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */ + uint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */ + uint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */ + uint32_t:1; + uint32_t T5_E:1; /* Trigger 5 enable */ + uint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */ + uint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */ + uint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */ + uint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */ + uint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */ + uint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */ + uint32_t:1; + uint32_t T4_E:1; /* Trigger 4 enable */ + uint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */ + uint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */ + uint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */ + uint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */ + uint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */ + uint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */ + } B; + } CTU_THCR2_32B_tag; + + + /* Register layout for all registers CLR_DCM... */ + + typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + uint16_t R; + struct { + uint16_t CIR:1; /* Command Interrupt Request */ + uint16_t LC:1; /* Last Command */ + uint16_t CMS:1; /* Conversion Mode Selection */ + uint16_t FIFO:3; /* FIFO for ADC A/B */ + uint16_t:1; + uint16_t CHB:4; /* ADC unit B channel number */ + uint16_t:1; + uint16_t CHA:4; /* ADC unit A channel number */ + } B; + } CTU_CLR_DCM_16B_tag; + + + /* Register layout for all registers CLR_SCM... */ + + typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + uint16_t R; + struct { + uint16_t CIR:1; /* Command Interrupt Request */ + uint16_t LC:1; /* Last Command */ + uint16_t CMS:1; /* Conversion Mode Selection */ + uint16_t FIFO:3; /* FIFO for ADC A/B */ + uint16_t:4; + uint16_t SU:1; /* Selection ADC Unit */ + uint16_t:1; + uint16_t CH:4; /* ADC unit channel number */ + } B; + } CTU_CLR_SCM_16B_tag; + + + /* Register layout for all registers CLR... */ + + + typedef union { /* Control Register */ + uint16_t R; + struct { + uint16_t EMPTY_CLR7:1; /* Empty Clear 7 */ + uint16_t EMPTY_CLR6:1; /* Empty Clear 6 */ + uint16_t EMPTY_CLR5:1; /* Empty Clear 5 */ + uint16_t EMPTY_CLR4:1; /* Empty Clear 4 */ + uint16_t EMPTY_CLR3:1; /* Empty Clear 3 */ + uint16_t EMPTY_CLR2:1; /* Empty Clear 2 */ + uint16_t EMPTY_CLR1:1; /* Empty Clear 1 */ + uint16_t EMPTY_CLR0:1; /* Empty Clear 0 */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */ +#else + uint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */ +#else + uint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */ +#else + uint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */ +#else + uint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */ +#else + uint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */ +#else + uint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */ +#else + uint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */ +#else + uint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */ +#endif + } B; + } CTU_CR_16B_tag; + + typedef union { /* Control Register FIFO */ + uint32_t R; + struct { + uint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */ + uint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */ + uint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */ + uint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */ + uint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */ + } B; + } CTU_FCR_32B_tag; + + typedef union { /* Threshold 1 Register */ + uint32_t R; + struct { + uint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */ + uint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */ + uint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */ + uint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */ + } B; + } CTU_TH1_32B_tag; + + typedef union { /* Threshold 2 Register */ + uint32_t R; + struct { + uint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */ + uint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */ + uint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */ + uint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */ + } B; + } CTU_TH2_32B_tag; + + typedef union { /* Status Register */ + uint32_t R; + struct { + uint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */ + uint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */ + uint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */ + uint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */ + uint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */ + uint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */ + uint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */ + uint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */ + uint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */ + uint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */ + uint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */ + uint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */ + uint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */ + uint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */ + uint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */ + uint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */ + uint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */ + uint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */ + uint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */ + uint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */ + uint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */ + uint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */ + uint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */ + uint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */ + uint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */ + } B; + } CTU_STS_32B_tag; + + + /* Register layout for all registers FR... */ + + typedef union { /* FIFO Right Aligned register */ + uint32_t R; + struct { + uint32_t:11; + uint32_t ADC:1; /* ADC Unit */ + uint32_t N_CH:4; /* Number Channel */ + uint32_t:4; + uint32_t DATA:12; /* Data Fifo */ + } B; + } CTU_FR_32B_tag; + + + /* Register layout for all registers FL... */ + + typedef union { /* FIFO Left Aligned register */ + uint32_t R; + struct { + uint32_t:11; + uint32_t ADC:1; /* ADC Unit */ + uint32_t N_CH:4; /* Number Channel */ + uint32_t:1; + uint32_t DATA:12; /* Data Fifo */ + uint32_t:3; + } B; + } CTU_FL_32B_tag; + + typedef union { /* CTU Error Flag Register */ + uint16_t R; + struct { + uint16_t:3; + uint16_t CS:1; /* Counter Status */ + uint16_t ET_OE:1; /* ExtTrigger Generation Overrun */ + uint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */ + uint16_t T4_OE:1; /* Timer4 Generation Overrun */ + uint16_t T3_OE:1; /* Timer3 Generation Overrun */ + uint16_t T2_OE:1; /* Timer2 Generation Overrun */ + uint16_t T1_OE:1; /* Timer1 Generation Overrun */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t ADC_OE:1; /* ADC Command Generation Overrun */ +#else + uint16_t ADCOE:1; /* ADC Command Generation Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t TGS_OSM:1; /* TGS Overrun */ +#else + uint16_t TGSOSM:1; /* TGS Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_O:1; /* MRS Overrun */ +#else + uint16_t MRSO:1; /* TGS Overrun */ +#endif + uint16_t ICE:1; /* Invalid Command Error */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t SM_TO:1; /* Trigger Overrun */ +#else + uint16_t SMTO:1; /* Trigger Overrun */ +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_RE:1; /* MRS Reload Error */ +#else + uint16_t MRSRE:1; /* MRS Reload Error */ +#endif + } B; + } CTU_CTUEFR_16B_tag; + + typedef union { /* CTU Interrupt Flag Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t S_E_B:1; /* Slice time OK */ + uint16_t S_E_A:1; /* Slice time OK */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t ADC_I:1; /* ADC Command Interrupt Flag */ +#else + uint16_t ADC:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T7_I:1; /* Trigger 7 Interrupt Flag */ +#else + uint16_t T7:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T6_I:1; /* Trigger 6 Interrupt Flag */ +#else + uint16_t T6:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T5_I:1; /* Trigger 5 Interrupt Flag */ +#else + uint16_t T5:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T4_I:1; /* Trigger 4 Interrupt Flag */ +#else + uint16_t T4:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T3_I:1; /* Trigger 3 Interrupt Flag */ +#else + uint16_t T3:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T2_I:1; /* Trigger 2 Interrupt Flag */ +#else + uint16_t T2:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T1_I:1; /* Trigger 1 Interrupt Flag */ +#else + uint16_t T1:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T0_I:1; /* Trigger 0 Interrupt Flag */ +#else + uint16_t T0:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_I:1; /* MRS Interrupt Flag */ +#else + uint16_t MRS:1; +#endif + } B; + } CTU_CTUIFR_16B_tag; + + typedef union { /* CTU Interrupt/DMA Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T7_I:1; /* Trigger 7 Interrupt Enable */ +#else + uint16_t T7IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T6_I:1; /* Trigger 6 Interrupt Enable */ +#else + uint16_t T6IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T5_I:1; /* Trigger 5 Interrupt Enable */ +#else + uint16_t T5IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T4_I:1; /* Trigger 4 Interrupt Enable */ +#else + uint16_t T4IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T3_I:1; /* Trigger 3 Interrupt Enable */ +#else + uint16_t T3IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T2_I:1; /* Trigger 2 Interrupt Enable */ +#else + uint16_t T2IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T1_I:1; /* Trigger 1 Interrupt Enable */ +#else + uint16_t T1IE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T0_I:1; /* Trigger 0 Interrupt Enable */ +#else + uint16_t T0IE:1; +#endif + uint16_t:2; + uint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */ + uint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */ + uint16_t DMA_DE:1; /* DMA and gre bit */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_DMAE:1; /* DMA Transfer Enable */ +#else + uint16_t MRSDMAE:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_IE:1; /* MRS Interrupt Enable */ +#else + uint16_t MRSIE:1; +#endif + uint16_t IEE:1; /* Interrupt Error Enable */ + } B; + } CTU_CTUIR_16B_tag; + + typedef union { /* Control On-Time Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_CTU + uint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */ +#else + uint16_t COTR:8; +#endif + } B; + } CTU_COTR_16B_tag; + + typedef union { /* CTU Control Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T7_SG:1; /* Trigger 7 Software Generated */ +#else + uint16_t T7SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T6_SG:1; /* Trigger 6 Software Generated */ +#else + uint16_t T6SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T5_SG:1; /* Trigger 5 Software Generated */ +#else + uint16_t T5SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T4_SG:1; /* Trigger 4 Software Generated */ +#else + uint16_t T4SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T3_SG:1; /* Trigger 3 Software Generated */ +#else + uint16_t T3SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T2_SG:1; /* Trigger 2 Software Generated */ +#else + uint16_t T2SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T1_SG:1; /* Trigger 1 Software Generated */ +#else + uint16_t T1SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t T0_SG:1; /* Trigger 0 Software Generated */ +#else + uint16_t T0SG:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */ +#else + uint16_t CTUADCRESET:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t CTU_ODIS:1; /* CTU Output Disable */ +#else + uint16_t CTUODIS:1; +#endif +#ifndef USE_FIELD_ALIASES_CTU + uint16_t FILTER_EN:1; /* Synchronize Filter Register value */ +#else + uint16_t FILTERENABLE:1; +#endif + uint16_t CGRE:1; /* Clear GRE */ + uint16_t FGRE:1; /* GRE Flag */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t MRS_SG:1; /* MRS Software Generated */ +#else + uint16_t MRSSG:1; +#endif + uint16_t GRE:1; /* General Reload Enable */ +#ifndef USE_FIELD_ALIASES_CTU + uint16_t TGSISR_RE:1; /* TGSISR Reload Enable */ +#else + uint16_t TGSISRRE:1; +#endif + } B; + } CTU_CTUCR_16B_tag; + + typedef union { /* CTU Digital Filter Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_CTU + uint16_t FILTER_VALUE:8; /* Filter Value */ +#else + uint16_t FILTERVALUE:8; /* deprecated name - please avoid */ +#endif + } B; + } CTU_FILTER_16B_tag; + + typedef union { /* CTU Expected A Value Register */ + uint16_t R; + struct { + uint16_t EXPECTED_A_VALUE:16; /* Expected A Value */ + } B; + } CTU_EXPECTED_A_16B_tag; + + typedef union { /* CTU Expected B Value Register */ + uint16_t R; + struct { + uint16_t EXPECTED_B_VALUE:16; /* Expected B Value */ + } B; + } CTU_EXPECTED_B_16B_tag; + + typedef union { /* CTU Counter Range Register */ + uint16_t R; + struct { + uint16_t:8; + uint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */ + } B; + } CTU_CNT_RANGE_16B_tag; + + + /* Register layout for generated register(s) FRA... */ + + typedef union { /* */ + uint32_t R; + } CTU_FRA_32B_tag; + + + /* Register layout for generated register(s) FLA... */ + + typedef union { /* */ + uint32_t R; + } CTU_FLA_32B_tag; + + + + typedef struct CTU_struct_tag { /* start of CTU_tag */ + /* Trigger Generator Subunit Input Selection register */ + CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */ + /* Trigger Generator Subunit Control Register */ + CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */ + union { + CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */ + + struct { + CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */ + CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */ + CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */ + CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */ + CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */ + CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */ + CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */ + CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */ + }; + + }; + /* TGS Counter Compare Register */ + CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */ + /* TGS Counter Reload Register */ + CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */ + int8_t CTU_reserved_001A[2]; + /* Commands List Control Register 1 */ + CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */ + /* Commands List Control Register 2 */ + CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */ + /* Trigger Handler Control Register 1 */ + CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */ + /* Trigger Handler Control Register 2 */ + CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */ + union { + /* Command List Register. View: BIT13, BIT9 */ + CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */ + + /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */ + + /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */ + + struct { + /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */ + CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */ + CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */ + }; + + struct { + /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */ + CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */ + CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */ + }; + + }; + int8_t CTU_reserved_005C[16]; + /* Control Register */ + CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */ + int8_t CTU_reserved_006E[2]; + /* Control Register FIFO */ + CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */ + /* Threshold 1 Register */ + CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */ + /* Threshold 2 Register */ + CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */ + union { + /* Status Register */ + CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */ + + CTU_STS_32B_tag STATUS; /* deprecated - please avoid */ + + }; + union { + CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */ + + /* FIFO Right Aligned register */ + CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */ + + struct { + /* FIFO Right Aligned register */ + CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */ + CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */ + CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */ + CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */ + CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */ + CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */ + CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */ + CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */ + }; + + }; + union { + CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + /* FIFO Left Aligned register */ + CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */ + + struct { + /* FIFO Left Aligned register */ + CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */ + CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */ + CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */ + CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */ + CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */ + CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */ + CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */ + CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */ + }; + + }; + /* CTU Error Flag Register */ + CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */ + /* CTU Interrupt Flag Register */ + CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */ + /* CTU Interrupt/DMA Register */ + CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */ + /* Control On-Time Register */ + CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */ + /* CTU Control Register */ + CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */ + union { + /* CTU Digital Filter Register */ + CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */ + + CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */ + + }; + /* CTU Expected A Value Register */ + CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */ + + /* CTU Expected B Value Register */ + CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */ + /* CTU Counter Range Register */ + CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */ + } CTU_tag; + + +#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL) + + + +/****************************************************************/ +/* */ +/* Module: mcTIMER */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers COMP1... */ + + typedef union { /* Compare Register 1 */ + uint16_t R; + struct { + uint16_t COMP1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_COMP1_16B_tag; + + + /* Register layout for all registers COMP2... */ + + typedef union { /* Compare Register 2 */ + uint16_t R; + struct { + uint16_t COMP2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_COMP2_16B_tag; + + + /* Register layout for all registers CAPT1... */ + + typedef union { /* Capture Register 1 */ + uint16_t R; + struct { + uint16_t CAPT1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CAPT1_16B_tag; + + + /* Register layout for all registers CAPT2... */ + + typedef union { /* Capture Register 2 */ + uint16_t R; + struct { + uint16_t CAPT2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CAPT2_16B_tag; + + + /* Register layout for all registers LOAD... */ + + typedef union { /* Load Register */ + uint16_t R; + struct { + uint16_t LOAD:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_LOAD_16B_tag; + + + /* Register layout for all registers HOLD... */ + + typedef union { /* Hold Register */ + uint16_t R; + struct { + uint16_t HOLD:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_HOLD_16B_tag; + + + /* Register layout for all registers CNTR... */ + + typedef union { /* Counter Register */ + uint16_t R; + struct { + uint16_t CNTR:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CNTR_16B_tag; + + + /* Register layout for all registers CTRL1... */ + + typedef union { /* Control Register */ + uint16_t R; + struct { + uint16_t CNTMODE:3; /* Count Mode */ + uint16_t PRISRC:5; /* Primary Count Source */ + uint16_t ONCE:1; /* Count Once */ + uint16_t LENGTH:1; /* Count Length */ + uint16_t DIR:1; /* Count Direction */ + uint16_t SECSRC:5; /* Secondary Count Source */ + } B; + } mcTIMER_CTRL1_16B_tag; + + + /* Register layout for all registers CTRL2... */ + + typedef union { /* Control Register 2 */ + uint16_t R; + struct { + uint16_t OEN:1; /* Output Enable */ + uint16_t RDNT:1; /* Redundant Channel Enable */ + uint16_t INPUT:1; /* External Input Signal */ + uint16_t VAL:1; /* Forced OFLAG Value */ + uint16_t FORCE:1; /* Force the OFLAG output */ + uint16_t COFRC:1; /* Co-channel OFLAG Force */ + uint16_t COINIT:2; /* Co-channel Initialization */ + uint16_t SIPS:1; /* Secondary Source Input Polarity Select */ + uint16_t PIPS:1; /* Primary Source Input Polarity Select */ + uint16_t OPS:1; /* Output Polarity Select */ + uint16_t MSTR:1; /* Master Mode */ + uint16_t OUTMODE:4; /* Output Mode */ + } B; + } mcTIMER_CTRL2_16B_tag; + + + /* Register layout for all registers CTRL3... */ + + typedef union { /* Control Register 3 */ + uint16_t R; + struct { + uint16_t STPEN:1; /* Stop Action Enable */ + uint16_t ROC:2; /* Reload On Capture */ + uint16_t FMODE:1; /* Fault Safing Mode */ + uint16_t FDIS:4; /* Fault Disable Mask */ + uint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */ + uint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */ + uint16_t DBGEN:2; /* Debug Actions Enable */ + } B; + } mcTIMER_CTRL3_16B_tag; + + + /* Register layout for all registers STS... */ + + typedef union { /* Status Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t WDF:1; /* Watchdog Time-out Flag */ + uint16_t RCF:1; /* Redundant Channel Flag */ + uint16_t ICF2:1; /* Input Capture 2 Flag */ + uint16_t ICF1:1; /* Input Capture 1 Flag */ + uint16_t IEHF:1; /* Input Edge High Flag */ + uint16_t IELF:1; /* Input Edge Low Flag */ + uint16_t TOF:1; /* Timer Overflow Flag */ + uint16_t TCF2:1; /* Timer Compare 2 Flag */ + uint16_t TCF1:1; /* Timer Compare 1 Flag */ + uint16_t TCF:1; /* Timer Compare Flag */ + } B; + } mcTIMER_STS_16B_tag; + + + /* Register layout for all registers INTDMA... */ + + typedef union { /* Interrupt and DMA Enable Register */ + uint16_t R; + struct { + uint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */ + uint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */ + uint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */ + uint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */ + uint16_t:2; + uint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */ + uint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */ + uint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */ + uint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */ + uint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */ + uint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */ + uint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */ + uint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */ + uint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */ + uint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */ + } B; + } mcTIMER_INTDMA_16B_tag; + + + /* Register layout for all registers CMPLD1... */ + + typedef union { /* Comparator Load Register 1 */ + uint16_t R; + struct { + uint16_t CMPLD1:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CMPLD1_16B_tag; + + + /* Register layout for all registers CMPLD2... */ + + typedef union { /* Comparator Load Register 2 */ + uint16_t R; + struct { + uint16_t CMPLD2:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_CMPLD2_16B_tag; + + + /* Register layout for all registers CCCTRL... */ + + typedef union { /* Compare and Capture Control Register */ + uint16_t R; + struct { + uint16_t CLC2:3; /* Compare Load Control 2 */ + uint16_t CLC1:3; /* Compare Load Control 1 */ + uint16_t CMPMODE:2; /* Compare Mode */ + uint16_t CPT2MODE:2; /* Capture 2 Mode Control */ + uint16_t CPT1MODE:2; /* Capture 1 Mode Control */ + uint16_t CFWM:2; /* Capture FIFO Water Mark */ + uint16_t ONESHOT:1; /* One Shot Capture Mode */ + uint16_t ARM:1; /* Arm Capture */ + } B; + } mcTIMER_CCCTRL_16B_tag; + + + /* Register layout for all registers FILT... */ + + typedef union { /* Input Filter Register */ + uint16_t R; + struct { + uint16_t:5; +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FILT_CNT:3; /* Input Filter Sample Count */ +#else + uint16_t FILTCNT:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FILT_PER:8; /* Input Filter Sample Period */ +#else + uint16_t FILTPER:8; /* deprecated name - please avoid */ +#endif + } B; + } mcTIMER_FILT_16B_tag; + + typedef union { /* Watchdog Time-out Register */ + uint16_t R; + struct { + uint16_t WDTOL:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_WDTOL_16B_tag; + + typedef union { /* Watchdog Time-out Register */ + uint16_t R; + struct { + uint16_t WDTOH:16; /* deprecated definition -- do not use */ + } B; + } mcTIMER_WDTOH_16B_tag; + + typedef union { /* Fault Control Register */ + uint16_t R; + struct { + uint16_t:3; + uint16_t FTEST:1; /* Fault Test */ + uint16_t FIE:4; /* Fault Interrupt Enable */ + uint16_t:4; + uint16_t FLVL:4; /* Fault Active Logic Level */ + } B; + } mcTIMER_FCTRL_16B_tag; + + typedef union { /* Fault Status Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t FFPIN:4; /* Filtered Fault Pin */ + uint16_t:4; + uint16_t FFLAG:4; /* Fault Flag */ + } B; + } mcTIMER_FSTS_16B_tag; + + typedef union { /* Fault Filter Registers */ + uint16_t R; + struct { + uint16_t:5; +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FFPIN:3; /* Fault Filter Sample Count */ +#else + uint16_t FFILTCNT:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcTIMER + uint16_t FFILT_PER:8; /* Fault Filter Sample Period */ +#else + uint16_t FFILTPER:8; /* deprecated name - please avoid */ +#endif + } B; + } mcTIMER_FFILT_16B_tag; + + typedef union { /* Channel Enable Registers */ + uint16_t R; + struct { + uint16_t:8; + uint16_t ENBL:8; /* Timer Channel Enable */ + } B; + } mcTIMER_ENBL_16B_tag; + + typedef union { /* DMA Request 0 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ0V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ0_16B_tag; + + typedef union { /* DMA Request 1 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ1V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ1_16B_tag; + + typedef union { /* DMA Request 2 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ2V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ2_16B_tag; + + typedef union { /* DMA Request 3 Select Registers */ + uint16_t R; + struct { + uint16_t:11; + uint16_t DREQ3V:5; /* DMA Request Select */ + } B; + } mcTIMER_DREQ3_16B_tag; + + + /* Register layout for generated register(s) DREQ... */ + + typedef union { /* */ + uint16_t R; + } mcTIMER_DREQ_16B_tag; + + + typedef struct mcTIMER_CHANNEL_struct_tag { + + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */ + union { + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */ + mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ + }; + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */ + /* Status Register */ + mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */ + + } mcTIMER_CHANNEL_tag; + + + typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */ + union { + /* Register set CHANNEL */ + mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */ + + struct { + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */ + /* Compare Register 1 */ + mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */ + /* Compare Register 2 */ + mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */ + /* Capture Register 1 */ + mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */ + /* Capture Register 2 */ + mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */ + /* Load Register */ + mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */ + /* Hold Register */ + mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */ + /* Counter Register */ + mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */ + /* Control Register */ + mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */ + /* Control Register 2 */ + mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */ + /* Control Register 3 */ + mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */ + /* Status Register */ + mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */ + /* Interrupt and DMA Enable Register */ + mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */ + /* Comparator Load Register 1 */ + mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */ + /* Comparator Load Register 2 */ + mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */ + /* Compare and Capture Control Register */ + mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */ + /* Input Filter Register */ + mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */ + }; + + }; + int8_t mcTIMER_reserved_00C0[64]; + /* Watchdog Time-out Register */ + mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */ + /* Watchdog Time-out Register */ + mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */ + /* Fault Control Register */ + mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */ + /* Fault Status Register */ + mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */ + /* Fault Filter Registers */ + mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */ + int8_t mcTIMER_reserved_010A[2]; + /* Channel Enable Registers */ + mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */ + int8_t mcTIMER_reserved_010E_C[2]; + union { + mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */ + + struct { + /* DMA Request 0 Select Registers */ + mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */ + /* DMA Request 1 Select Registers */ + mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */ + /* DMA Request 2 Select Registers */ + mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */ + /* DMA Request 3 Select Registers */ + mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */ + }; + + }; + } mcTIMER_tag; + + +#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL) +#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL) +#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL) + + + +/****************************************************************/ +/* */ +/* Module: mcPWM */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CNT... */ + + typedef union { /* Counter Register */ + uint16_t R; + } mcPWM_CNT_16B_tag; + + + /* Register layout for all registers INIT... */ + + typedef union { /* Initial Counter Register */ + uint16_t R; + } mcPWM_INIT_16B_tag; + + + /* Register layout for all registers CTRL2... */ + + typedef union { /* Control 2 Register */ + uint16_t R; + struct { + uint16_t DBGEN:1; /* Debug Enable */ + uint16_t WAITEN:1; /* Wait Enable */ + uint16_t INDEP:1; /* Independent or Complementary Pair Operation */ +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t PWM23_INIT:1; /* PWM23 Initial Value */ +#else + uint16_t PWMA_INIT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t PWM45_INIT:1; /* PWM23 Initial Value */ +#else + uint16_t PWMB_INIT:1; /* deprecated name - please avoid */ +#endif + uint16_t PWMX_INIT:1; /* PWMX Initial Value */ + uint16_t INIT_SEL:2; /* Initialization Control Select */ + uint16_t FRCEN:1; /* Force Initialization enable */ + uint16_t FORCE:1; /* Force Initialization */ + uint16_t FORCE_SEL:3; /* Force Source Select */ + uint16_t RELOAD_SEL:1; /* Reload Source Select */ + uint16_t CLK_SEL:2; /* Clock Source Select */ + } B; + } mcPWM_CTRL2_16B_tag; + + + /* Register layout for all registers CTRL1... */ + + typedef union { /* Control Register */ + uint16_t R; + struct { + uint16_t LDFQ:4; /* Load Frequency */ + uint16_t HALF:1; /* Half Cycle Reload */ + uint16_t FULL:1; /* Full Cycle Reload */ + uint16_t DT:2; /* Deadtime */ + uint16_t:1; + uint16_t PRSC:3; /* Prescaler */ + uint16_t:1; + uint16_t LDMOD:1; /* Load Mode Select */ + uint16_t:1; +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t DBL_EN:1; /* Double Switching Enable */ +#else + uint16_t DBLEN:1; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_CTRL1_16B_tag; + + + /* Register layout for all registers VAL_0... */ + + typedef union { /* Value Register 0 */ + uint16_t R; + } mcPWM_VAL_0_16B_tag; + + + /* Register layout for all registers VAL_1... */ + + typedef union { /* Value Register 1 */ + uint16_t R; + } mcPWM_VAL_1_16B_tag; + + + /* Register layout for all registers VAL_2... */ + + typedef union { /* Value Register 2 */ + uint16_t R; + } mcPWM_VAL_2_16B_tag; + + + /* Register layout for all registers VAL_3... */ + + typedef union { /* Value Register 3 */ + uint16_t R; + } mcPWM_VAL_3_16B_tag; + + + /* Register layout for all registers VAL_4... */ + + typedef union { /* Value Register 4 */ + uint16_t R; + } mcPWM_VAL_4_16B_tag; + + + /* Register layout for all registers VAL_5... */ + + typedef union { /* Value Register 5 */ + uint16_t R; + } mcPWM_VAL_5_16B_tag; + + /* Register layout for all registers OCTRL... */ + + typedef union { /* Output Control Register */ + uint16_t R; + struct { + uint16_t PWMA_IN:1; /* PWMA Input */ + uint16_t PWMB_IN:1; /* PWMB Input */ + uint16_t PWMX_IN:1; /* PWMX Input */ + uint16_t:2; + uint16_t POLA:1; /* PWMA Output Polarity */ + uint16_t POLB:1; /* PWMB Output Polarity */ + uint16_t POLX:1; /* PWMX Output Polarity */ + uint16_t:2; + uint16_t PWMAFS:2; /* PWMA Fault State */ + uint16_t PWMBFS:2; /* PWMB Fault State */ + uint16_t PWMXFS:2; /* PWMX Fault State */ + } B; + } mcPWM_OCTRL_16B_tag; + + + /* Register layout for all registers STS... */ + + typedef union { /* Status Register */ + uint16_t R; + struct { + uint16_t:1; + uint16_t RUF:1; /* Registers Updated Flag */ + uint16_t REF:1; /* Reload Error Flag */ + uint16_t RF:1; /* Reload Flag */ + uint16_t CFA1:1; /* Capture Flag A1 */ + uint16_t CFA0:1; /* Capture Flag A0 */ + uint16_t CFB1:1; /* Capture Flag B1 */ + uint16_t CFB0:1; /* Capture Flag B0 */ + uint16_t CFX1:1; /* Capture Flag X1 */ + uint16_t CFX0:1; /* Capture Flag X0 */ + uint16_t CMPF:6; /* Compare Flags */ + } B; + } mcPWM_STS_16B_tag; + + + /* Register layout for all registers INTEN... */ + + typedef union { /* Interrupt Enable Registers */ + uint16_t R; + struct { + uint16_t:2; + uint16_t REIE:1; /* Reload Error Interrupt Enable */ + uint16_t RIE:1; /* Reload Interrupt Enable */ + uint16_t CA1IE:1; /* Capture A1 Interrupt Enable */ + uint16_t CA0IE:1; /* Capture A0 Interrupt Enable */ + uint16_t CB1IE:1; /* Capture B1 Interrupt Enable */ + uint16_t CB0IE:1; /* Capture B0 Interrupt Enable */ + uint16_t CX1IE:1; /* Capture X1 Interrupt Enable */ + uint16_t CX0IE:1; /* Capture X0 Interrupt Enable */ + uint16_t CMPIE:6; /* Compare Interrupt Enables */ + } B; + } mcPWM_INTEN_16B_tag; + + + /* Register layout for all registers DMAEN... */ + + typedef union { /* DMA Enable Registers */ + uint16_t R; + struct { + uint16_t:6; + uint16_t VALDE:1; /* Value Register DMA Enable */ + uint16_t FAND:1; /* FIFO Watermark AND Control */ + uint16_t CAPTDE:2; /* Capture DMA Enable Source Select */ + uint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */ + uint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */ + uint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */ + uint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */ + uint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */ + uint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */ + } B; + } mcPWM_DMAEN_16B_tag; + + + /* Register layout for all registers TCTRL... */ + + typedef union { /* Output Trigger Control Registers */ + uint16_t R; + struct { + uint16_t:10; + uint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */ + } B; + } mcPWM_TCTRL_16B_tag; + + + /* Register layout for all registers DISMAP... */ + + typedef union { /* Fault Disable Mapping Registers */ + uint16_t R; + struct { + uint16_t:4; + uint16_t DISX:4; /* PWMX Fault Disable Mask */ + uint16_t DISB:4; /* PWMB Fault Disable Mask */ + uint16_t DISA:4; /* PWMA Fault Disable Mask */ + } B; + } mcPWM_DISMAP_16B_tag; + + + /* Register layout for all registers DTCNT0... */ + + typedef union { /* Deadtime Count Register 0 */ + uint16_t R; + struct { + uint16_t:5; + uint16_t DTCNT0:11; /* Deadtime Count Register 0 */ + } B; + } mcPWM_DTCNT0_16B_tag; + + + /* Register layout for all registers DTCNT1... */ + + typedef union { /* Deadtime Count Register 1 */ + uint16_t R; + struct { + uint16_t:5; + uint16_t DTCNT1:11; /* Deadtime Count Register 1 */ + } B; + } mcPWM_DTCNT1_16B_tag; + + /* Register layout for all registers CAPTCTRLX... */ + + typedef union { /* Capture Control X Register */ + uint16_t R; + struct { + uint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */ + uint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */ + uint16_t CFXWM:2; /* Capture X FIFOs Water Mark */ +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t EDGCNTXEN:1; /* Edge Counter X Enable */ +#else + uint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t INPSELX:1; /* Input Select X */ +#else + uint16_t INP_SELX:1; /* deprecated name - please avoid */ +#endif + uint16_t EDGX1:2; /* Edge X 1 */ + uint16_t EDGX0:2; /* Edge X 0 */ + uint16_t ONESHOTX:1; /* One Shot Mode X */ + uint16_t ARMX:1; /* Arm X */ + } B; + } mcPWM_CAPTCTRLX_16B_tag; + + + /* Register layout for all registers CAPTCMPX... */ + + typedef union { /* Capture Compare X Register */ + uint16_t R; + struct { + uint16_t EDGCNTX:8; /* Edge Counter X */ + uint16_t EDGCMPX:8; /* Edge Compare X */ + } B; + } mcPWM_CAPTCMPX_16B_tag; + + + /* Register layout for all registers CVAL0... */ + + typedef union { /* Capture Value 0 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL0:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL0_16B_tag; + + + /* Register layout for all registers CVAL0CYC... */ + + typedef union { /* Capture Value 0 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */ + } B; + } mcPWM_CVAL0CYC_16B_tag; + + + /* Register layout for all registers CVAL1... */ + + typedef union { /* Capture Value 1 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL1:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL1_16B_tag; + + + /* Register layout for all registers CVAL1CYC... */ + + typedef union { /* Capture Value 1 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */ + } B; + } mcPWM_CVAL1CYC_16B_tag; + + + /* Register layout for all registers CVAL3... */ + + typedef union { /* Capture Value 3 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL3:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL3_16B_tag; + + + /* Register layout for all registers CVAL3CYC... */ + + typedef union { /* Capture Value 3 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */ + } B; + } mcPWM_CVAL3CYC_16B_tag; + + + /* Register layout for all registers CVAL4... */ + + typedef union { /* Capture Value 4 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL4:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL4_16B_tag; + + + /* Register layout for all registers CVAL4CYC... */ + + typedef union { /* Capture Value 4 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */ + } B; + } mcPWM_CVAL4CYC_16B_tag; + + + /* Register layout for all registers CVAL5... */ + + typedef union { /* Capture Value 5 Register */ + uint16_t R; + struct { + uint16_t CAPTVAL5:16; /* Captured value from submodule counter */ + } B; + } mcPWM_CVAL5_16B_tag; + + + /* Register layout for all registers CVAL5CYC... */ + + typedef union { /* Capture Value 5 Cycle Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */ + } B; + } mcPWM_CVAL5CYC_16B_tag; + + typedef union { /* Output Enable Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t PWMA_EN:4; /* PWMA Output Enables */ + uint16_t PWMB_EN:4; /* PWMB Output Enables */ + uint16_t PWMX_EN:4; /* PWMX Output Enables */ + } B; + } mcPWM_OUTEN_16B_tag; + + typedef union { /* Mask Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t MASKA:4; /* PWMA Masks */ + uint16_t MASKB:4; /* PWMB Masks */ + uint16_t MASKX:4; /* PWMX Masks */ + } B; + } mcPWM_MASK_16B_tag; + + typedef union { /* Software Controlled Output Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_3:1; /* Software Controlled Output 23_3 */ +#else + uint16_t OUTA_3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_3:1; /* Software Controlled Output 45_3 */ +#else + uint16_t OUTB_3:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_2:1; /* Software Controlled Output 23_2 */ +#else + uint16_t OUTA_2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_2:1; /* Software Controlled Output 45_2 */ +#else + uint16_t OUTB_2:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_1:1; /* Software Controlled Output 23_1 */ +#else + uint16_t OUTA_1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_1:1; /* Software Controlled Output 45_1 */ +#else + uint16_t OUTB_1:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT23_0:1; /* Software Controlled Output 23_0 */ +#else + uint16_t OUTA_0:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t OUT45_0:1; /* Software Controlled Output 45_0 */ +#else + uint16_t OUTB_0:1; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_SWCOUT_16B_tag; + + typedef union { /* Deadtime Source Select Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_3:2; /* PWM23_3 Control Select */ +#else + uint16_t SELA_3:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_3:2; /* PWM45_3 Control Select */ +#else + uint16_t SELB_3:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_2:2; /* PWM23_2 Control Select */ +#else + uint16_t SELA_2:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_2:2; /* PWM45_2 Control Select */ +#else + uint16_t SELB_2:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_1:2; /* PWM23_1 Control Select */ +#else + uint16_t SELA_1:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_1:2; /* PWM45_1 Control Select */ +#else + uint16_t SELB_1:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL23_0:2; /* PWM23_0 Control Select */ +#else + uint16_t SELA_0:2; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t SEL45_0:2; /* PWM45_0 Control Select */ +#else + uint16_t SELB_0:2; /* deprecated name - please avoid */ +#endif + } B; + } mcPWM_DTSRCSEL_16B_tag; + + typedef union { /* Master Control Register */ + uint16_t R; + struct { + uint16_t IPOL:4; /* Current Polarity */ + uint16_t RUN:4; /* Run */ +#ifndef USE_FIELD_ALIASES_mcPWM + uint16_t CLOK:4; /* Clear Load Okay */ +#else + uint16_t CLDOK:4; /* deprecated name - please avoid */ +#endif + uint16_t LDOK:4; /* Load Okay */ + } B; + } mcPWM_MCTRL_16B_tag; + + typedef union { /* Fault Control Register */ + uint16_t R; + struct { + uint16_t FLVL:4; /* Fault Level */ + uint16_t FAUTO:4; /* Automatic Fault Clearing */ + uint16_t FSAFE:4; /* Fault Safety Mode */ + uint16_t FIE:4; /* Fault Interrupt Enables */ + } B; + } mcPWM_FCTRL_16B_tag; + + typedef union { /* Fault Status Register */ + uint16_t R; + struct { + uint16_t:3; + uint16_t FTEST:1; /* Fault Test */ + uint16_t FFPIN:4; /* Filtered Fault Pins */ + uint16_t:4; + uint16_t FFLAG:4; /* Fault Flags */ + } B; + } mcPWM_FSTS_16B_tag; + + typedef union { /* Fault Filter Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FILT_CNT:3; /* Fault Filter Count */ + uint16_t FILT_PER:8; /* Fault Filter Period */ + } B; + } mcPWM_FFILT_16B_tag; + + + /* Register layout for generated register(s) VAL... */ + + typedef union { /* */ + uint16_t R; + } mcPWM_VAL_16B_tag; + + + typedef struct mcPWM_SUBMOD_struct_tag { + + /* Counter Register */ + mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */ + union { + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */ + mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */ + }; + /* Value Register 0 */ + + union { + + struct { + + mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */ + + }; + + mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */ + + }; + int8_t mcPWM_reserved_0014[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */ + /* Status Register */ + mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_0028[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */ + union { + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */ + mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */ + }; + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */ + union { + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */ + mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */ + }; + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */ + union { + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */ + mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */ + }; + /* Capture Value 2 Register */ + int8_t mcPWM_SUBMOD_reserved_003C[16]; + int8_t mcPWM_SUBMOD_reserved_004C[4]; + + } mcPWM_SUBMOD_tag; + + + typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */ + union { + /* Register set SUBMOD */ + mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */ + + mcPWM_SUBMOD_tag SUB[4]; /* offset: 0x0000 (0x0050 x 4) */ + + struct { + /* Counter Register */ + mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */ + int8_t mcPWM_reserved_0014[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */ + int8_t mcPWM_reserved_0028[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */ + int8_t mcPWM_reserved_003c[16]; + int8_t mcPWM_reserved_004C_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */ + int8_t mcPWM_reserved_0064[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_0078[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */ + int8_t mcPWM_reserved_008c[16]; + int8_t mcPWM_reserved_009C_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */ + int8_t mcPWM_reserved_00b4[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_00c8[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */ + int8_t mcPWM_reserved_00dc[16]; + int8_t mcPWM_reserved_00EC_I2[4]; + /* Counter Register */ + mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */ + /* Initial Counter Register */ + mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */ + /* Control 2 Register */ + mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */ + /* Control Register */ + mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */ + /* Value Register 0 */ + mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */ + /* Value Register 1 */ + mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */ + /* Value Register 2 */ + mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */ + /* Value Register 3 */ + mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */ + /* Value Register 4 */ + mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */ + /* Value Register 5 */ + mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */ + int8_t mcPWM_reserved_00104[4]; + /* Output Control Register */ + mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */ + /* Status Register */ + mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */ + /* Interrupt Enable Registers */ + mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */ + /* DMA Enable Registers */ + mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */ + /* Output Trigger Control Registers */ + mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */ + /* Fault Disable Mapping Registers */ + mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */ + /* Deadtime Count Register 0 */ + mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */ + /* Deadtime Count Register 1 */ + mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */ + /* Capture Control A Register */ + int8_t mcPWM_reserved_00118[8]; + /* Capture Control X Register */ + mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */ + /* Capture Compare X Register */ + mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */ + /* Capture Value 0 Register */ + mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */ + /* Capture Value 0 Cycle Register */ + mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */ + /* Capture Value 1 Register */ + mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */ + /* Capture Value 1 Cycle Register */ + mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */ + int8_t mcPWM_reserved_0012c[16]; + int8_t mcPWM_reserved_013C_E2[4]; + }; + + }; + /* Output Enable Register */ + mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */ + /* Mask Register */ + mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */ + /* Software Controlled Output Register */ + mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */ + /* Deadtime Source Select Register */ + mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */ + /* Master Control Register */ + mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */ + int8_t mcPWM_reserved_014A[2]; + /* Fault Control Register */ + mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */ + /* Fault Status Register */ + mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */ + /* Fault Filter Register */ + mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */ + } mcPWM_tag; + + +#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL) +#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL) + + + +/****************************************************************/ +/* */ +/* Module: LINFLEX */ +/* */ +/****************************************************************/ + + typedef union { /* LIN Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t CCD:1; /* Checksum Calculation Disable */ + uint32_t CFD:1; /* Checksum Field Disable */ + uint32_t LASE:1; /* LIN Auto Synchronization Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t AUTOWU:1; /* Auto Wake Up */ +#else + uint32_t AWUM:1; /* deprecated name - please avoid */ +#endif + uint32_t MBL:4; /* Master Break Length */ + uint32_t BF:1; /* By-Pass Filter */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t SLFM:1; /* Selftest Mode */ +#else + uint32_t SFTM:1; /* deprecated name - please avoid */ +#endif + uint32_t LBKM:1; /* Loopback Mode */ + uint32_t MME:1; /* Master Mode Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t SSBL:1; /* Slave Mode Synch Break Length */ +#else + uint32_t SSDT:1; /* deprecated name - please avoid */ +#endif + uint32_t RBLM:1; /* Receiver Buffer Locked Mode */ + uint32_t SLEEP:1; /* Sleep Mode Request */ + uint32_t INIT:1; /* Initialization Mode Request */ + } B; + } LINFLEX_LINCR1_32B_tag; + + typedef union { /* LIN Interrupt Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */ + uint32_t OCIE:1; /* Output Compare Interrupt Enable */ + uint32_t BEIE:1; /* Bit Error Interrupt Enable */ + uint32_t CEIE:1; /* Checksum Error Interrupt Enable */ + uint32_t HEIE:1; /* Header Error Interrupt Enable */ + uint32_t:2; + uint32_t FEIE:1; /* Frame Error Interrupt Enable */ + uint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */ + uint32_t LSIE:1; /* LIN State Interrupt Enable */ + uint32_t WUIE:1; /* Wakeup Interrupt Enable */ + uint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */ +#else + uint32_t DBEIE:1; /* deprecated name - please avoid */ +#endif + uint32_t DRIE:1; /* Data Reception complete Interrupt Enable */ + uint32_t DTIE:1; /* Data Transmitted Interrupt Enable */ + uint32_t HRIE:1; /* Header Received Interrupt Enable */ + } B; + } LINFLEX_LINIER_32B_tag; + + typedef union { /* LIN Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t LINS:4; /* LIN State */ + uint32_t:2; + uint32_t RMB:1; /* Release Message Buffer */ + uint32_t:1; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t RXBUSY:1; /* Receiver Busy Flag */ +#else + uint32_t RBSY:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t RDI:1; /* LIN Receive Signal */ +#else + uint32_t RPS:1; /* deprecated name - please avoid */ +#endif + uint32_t WUF:1; /* Wake Up Flag */ + uint32_t DBFF:1; /* Data Buffer Full Flag */ + uint32_t DBEF:1; /* Data Buffer Empty Flag */ + uint32_t DRF:1; /* Data Reception Completed Flag */ + uint32_t DTF:1; /* Data Transmission Completed Flag */ + uint32_t HRF:1; /* Header Received Flag */ + } B; + } LINFLEX_LINSR_32B_tag; + + typedef union { /* LIN Error Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SZF:1; /* Stuck at Zero Flag */ + uint32_t OCF:1; /* Output Compare Flag */ + uint32_t BEF:1; /* Bit Error Flag */ + uint32_t CEF:1; /* Checksum Error Flag */ + uint32_t SFEF:1; /* Sync Field Error Flag */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t SDEF:1; /* Sync Delimiter Error Flag */ +#else + uint32_t BDEF:1; /* deprecated name - please avoid */ +#endif + uint32_t IDPEF:1; /* ID Parity Error Flag */ + uint32_t FEF:1; /* Framing Error Flag */ + uint32_t BOF:1; /* Buffer Overrun Flag */ + uint32_t:6; + uint32_t NF:1; /* Noise Flag */ + } B; + } LINFLEX_LINESR_32B_tag; + + typedef union { /* UART Mode Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */ + uint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */ + uint32_t RFBM:1; /* RX FIFO/ Buffer Mode */ + uint32_t TFBM:1; /* TX FIFO/ Buffer Mode */ + uint32_t WL1:1; /* Word Length in UART mode - bit 1 */ + uint32_t PC1:1; /* Parity Check - bit 1 */ + uint32_t RXEN:1; /* Receiver Enable */ + uint32_t TXEN:1; /* Transmitter Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t PC0:1; /* Parity Check - bit 0 */ +#else + uint32_t OP:1; /* deprecated name - please avoid */ +#endif + uint32_t PCE:1; /* Parity Control Enable */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t WL0:1; /* Word Length in UART Mode - bit 0 */ +#else + uint32_t WL:1; /* deprecated name - please avoid */ +#endif + uint32_t UART:1; /* UART Mode */ + } B; + } LINFLEX_UARTCR_32B_tag; + + typedef union { /* UART Mode Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SZF:1; /* Stuck at Zero Flag */ + uint32_t OCF:1; /* Output Compare Flag */ + uint32_t PE:4; /* Parity Error Flag */ + uint32_t RMB:1; /* Release Message Buffer */ + uint32_t FEF:1; /* Framing Error Flag */ + uint32_t BOF:1; /* Buffer Overrun Flag */ + uint32_t RDI:1; /* Receiver Data Input Signal */ + uint32_t WUF:1; /* Wakeup Flag */ + uint32_t:1; + uint32_t TO:1; /* Time Out */ +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */ +#else + uint32_t DRF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */ +#else + uint32_t DTF:1; /* deprecated name - please avoid */ +#endif + uint32_t NF:1; /* Noise Flag */ + } B; + } LINFLEX_UARTSR_32B_tag; + + typedef union { /* LIN Time-Out Control Status Register */ + uint32_t R; + struct { + uint32_t:21; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t MODE:1; /* Time-out Counter Mode */ +#else + uint32_t LTOM:1; /* deprecated name - please avoid */ +#endif + uint32_t IOT:1; /* Idle on Timeout */ + uint32_t TOCE:1; /* Time-Out Counter Enable */ + uint32_t CNT:8; /* Counter Value */ + } B; + } LINFLEX_LINTCSR_32B_tag; + + typedef union { /* LIN Output Compare Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OC2:8; /* Output Compare Value 2 */ + uint32_t OC1:8; /* Output Compare Value 1 */ + } B; + } LINFLEX_LINOCR_32B_tag; + + typedef union { /* LIN Time-Out Control Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t RTO:4; /* Response Time-Out Value */ + uint32_t:1; + uint32_t HTO:7; /* Header Time-Out Value */ + } B; + } LINFLEX_LINTOCR_32B_tag; + + typedef union { /* LIN Fractional Baud Rate Register */ + uint32_t R; + struct { + uint32_t:28; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t FBR:4; /* Fractional Baud Rates */ +#else + uint32_t DIV_F:4; /* deprecated name - please avoid */ +#endif + } B; + } LINFLEX_LINFBRR_32B_tag; + + typedef union { /* LIN Integer Baud Rate Register */ + uint32_t R; + struct { + uint32_t:13; +#ifndef USE_FIELD_ALIASES_LINFLEX + uint32_t IBR:19; /* Integer Baud Rates */ +#else + uint32_t DIV_M:19; /* deprecated name - please avoid */ +#endif + } B; + } LINFLEX_LINIBRR_32B_tag; + + typedef union { /* LIN Checksum Field Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t CF:8; /* Checksum Bits */ + } B; + } LINFLEX_LINCFR_32B_tag; + + typedef union { /* LIN Control Register 2 */ + uint32_t R; + struct { + uint32_t:17; + uint32_t IOBE:1; /* Idle on Bit Error */ + uint32_t IOPE:1; /* Idle on Identifier Parity Error */ + uint32_t WURQ:1; /* Wakeup Generate Request */ + uint32_t DDRQ:1; /* Data Discard Request */ + uint32_t DTRQ:1; /* Data Transmission Request */ + uint32_t ABRQ:1; /* Abort Request */ + uint32_t HTRQ:1; /* Header Transmission Request */ + uint32_t:8; + } B; + } LINFLEX_LINCR2_32B_tag; + + typedef union { /* Buffer Identifier Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t DFL:6; /* Data Field Length */ + uint32_t DIR:1; /* Direction */ + uint32_t CCS:1; /* Classic Checksum */ + uint32_t:2; + uint32_t ID:6; /* Identifier */ + } B; + } LINFLEX_BIDR_32B_tag; + + typedef union { /* Buffer Data Register Least Significant */ + uint32_t R; + struct { + uint32_t DATA3:8; /* Data3 */ + uint32_t DATA2:8; /* Data2 */ + uint32_t DATA1:8; /* Data1 */ + uint32_t DATA0:8; /* Data0 */ + } B; + } LINFLEX_BDRL_32B_tag; + + typedef union { /* Buffer Data Register Most Significant */ + uint32_t R; + struct { + uint32_t DATA7:8; /* Data7 */ + uint32_t DATA6:8; /* Data6 */ + uint32_t DATA5:8; /* Data5 */ + uint32_t DATA4:8; /* Data4 */ + } B; + } LINFLEX_BDRM_32B_tag; + + typedef union { /* Identifier Filter Enable Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t FACT:8; /* Filter Active */ + } B; + } LINFLEX_IFER_32B_tag; + + typedef union { /* Identifier Filter Match Index */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IFMI_IFMI:4; /* Filter Match Index */ + } B; + } LINFLEX_IFMI_32B_tag; + + typedef union { /* Identifier Filter Mode Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t IFM:4; /* Filter Mode */ + } B; + } LINFLEX_IFMR_32B_tag; + + + /* Register layout for all registers IFCR... */ + + typedef union { /* Identifier Filter Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t DFL:6; /* Data Field Length */ + uint32_t DIR:1; /* Direction */ + uint32_t CCS:1; /* Classic Checksum */ + uint32_t:2; + uint32_t ID:6; /* Identifier */ + } B; + } LINFLEX_IFCR_32B_tag; + + typedef union { /* Global Control Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t TDFBM:1; /* Transmit Data First Bit MSB */ + uint32_t RDFBM:1; /* Received Data First Bit MSB */ + uint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */ + uint32_t RDLIS:1; /* Received Data Level Inversion Selection */ + uint32_t STOP:1; /* 1/2 stop bit configuration */ + uint32_t SR:1; /* Soft Reset */ + } B; + } LINFLEX_GCR_32B_tag; + + typedef union { /* UART Preset Time Out Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t PTO:12; /* Preset Time Out */ + } B; + } LINFLEX_UARTPTO_32B_tag; + + typedef union { /* UART Current Time Out Register */ + uint32_t R; + struct { + uint32_t:20; + uint32_t CTO:12; /* Current Time Out */ + } B; + } LINFLEX_UARTCTO_32B_tag; + + typedef union { /* DMA TX Enable Register */ + uint32_t R; + struct { + uint32_t:17; + uint32_t DTE:15; /* DMA Tx channel Enable */ + } B; + } LINFLEX_DMATXE_32B_tag; + + typedef union { /* DMA RX Enable Register */ + uint32_t R; + struct { + uint32_t:17; + uint32_t DRE:15; /* DMA Rx channel Enable */ + } B; + } LINFLEX_DMARXE_32B_tag; + + + + typedef struct LINFLEX_struct_tag { /* start of LINFLEX_tag */ + /* LIN Control Register */ + LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */ + /* LIN Interrupt Enable Register */ + LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */ + /* LIN Status Register */ + LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */ + /* LIN Error Status Register */ + LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */ + /* UART Mode Control Register */ + LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */ + /* UART Mode Status Register */ + LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */ + /* LIN Time-Out Control Status Register */ + LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */ + /* LIN Output Compare Register */ + LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */ + /* LIN Time-Out Control Register */ + LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */ + /* LIN Fractional Baud Rate Register */ + LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */ + /* LIN Integer Baud Rate Register */ + LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */ + /* LIN Checksum Field Register */ + LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */ + /* LIN Control Register 2 */ + LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */ + /* Buffer Identifier Register */ + LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */ + /* Buffer Data Register Least Significant */ + LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */ + /* Buffer Data Register Most Significant */ + LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */ + /* Identifier Filter Enable Register */ + LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */ + /* Identifier Filter Match Index */ + LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */ + /* Identifier Filter Mode Register */ + LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */ + union { + /* Identifier Filter Control Register */ + LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */ + + struct { + /* Identifier Filter Control Register */ + LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */ + LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */ + }; + + }; + int8_t LINFLEX_reserved_006C[32]; + /* Global Control Register */ + LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */ + /* UART Preset Time Out Register */ + LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */ + /* UART Current Time Out Register */ + LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */ + /* DMA TX Enable Register */ + LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */ + /* DMA RX Enable Register */ + LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */ + } LINFLEX_tag; + + +#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL) +#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL) + + + +/****************************************************************/ +/* */ +/* Module: CRC */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CFG... */ + + typedef union { /* CRC_CFG - CRC Configuration register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + struct { + uint32_t:29; + uint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */ + uint32_t SWAP:1; /* SWAP selection */ + uint32_t INV:1; /* INV selection */ + } B; + } CRC_CFG_32B_tag; + + + /* Register layout for all registers INP... */ + + typedef union { /* CRC_INP - CRC Input register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } CRC_INP_32B_tag; + + + /* Register layout for all registers CSTAT... */ + + typedef union { /* CRC_STATUS - CRC Status register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } CRC_CSTAT_32B_tag; + + + /* Register layout for all registers OUTP... */ + + typedef union { /* CRC_STATUS - CRC OUTPUT register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint16_t HALF[2]; /* individual halfwords can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } CRC_OUTP_32B_tag; + + + typedef struct CRC_CNTX_struct_tag { + + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP; /* relative offset: 0x0004 */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */ + + } CRC_CNTX_tag; + + + typedef struct CRC_struct_tag { /* start of CRC_tag */ + union { + /* Register set CNTX */ + CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */ + + struct { + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */ + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */ + /* CRC_CFG - CRC Configuration register */ + CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */ + /* CRC_INP - CRC Input register */ + CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */ + /* CRC_STATUS - CRC Status register */ + CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */ + /* CRC_STATUS - CRC OUTPUT register */ + CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */ + }; + + }; + } CRC_tag; + + +#define CRC (*(volatile CRC_tag *) 0xFFE68000UL) + + + +/****************************************************************/ +/* */ +/* Module: FCCU */ +/* */ +/****************************************************************/ + + typedef union { /* FCCU Control Register */ + uint32_t R; + struct { + uint32_t:23; + uint32_t NVML:1; /* NVM configuration loaded */ + uint32_t OPS:2; /* Operation status */ + uint32_t:1; + uint32_t OPR:5; /* Operation run */ + } B; + } FCCU_CTRL_32B_tag; + + typedef union { /* FCCU CTRL Key Register */ + uint32_t R; + } FCCU_CTRLK_32B_tag; + + typedef union { /* FCCU Configuration Register */ + uint32_t R; + struct { + uint32_t:10; + uint32_t RCCE1:1; /* RCC1 enable */ + uint32_t RCCE0:1; /* RCC0 enable */ + uint32_t SMRT:4; /* Safe Mode Request Timer */ + uint32_t:4; + uint32_t CM:1; /* Config mode */ + uint32_t SM:1; /* Switching mode */ + uint32_t PS:1; /* Polarity Selection */ + uint32_t FOM:3; /* Fault Output Mode Selection */ + uint32_t FOP:6; /* Fault Output Prescaler */ + } B; + } FCCU_CFG_32B_tag; + + typedef union { /* FCCU CF Configuration Register 0 */ + uint32_t R; + struct { + uint32_t CFC31:1; /* CF 31 configuration */ + uint32_t CFC30:1; /* CF 30 configuration */ + uint32_t CFC29:1; /* CF 29 configuration */ + uint32_t CFC28:1; /* CF 28 configuration */ + uint32_t CFC27:1; /* CF 27 configuration */ + uint32_t CFC26:1; /* CF 26 configuration */ + uint32_t CFC25:1; /* CF 25 configuration */ + uint32_t CFC24:1; /* CF 24 configuration */ + uint32_t CFC23:1; /* CF 23 configuration */ + uint32_t CFC22:1; /* CF 22 configuration */ + uint32_t CFC21:1; /* CF 21 configuration */ + uint32_t CFC20:1; /* CF 20 configuration */ + uint32_t CFC19:1; /* CF 19 configuration */ + uint32_t CFC18:1; /* CF 18 configuration */ + uint32_t CFC17:1; /* CF 17 configuration */ + uint32_t CFC16:1; /* CF 16 configuration */ + uint32_t CFC15:1; /* CF 15 configuration */ + uint32_t CFC14:1; /* CF 14 configuration */ + uint32_t CFC13:1; /* CF 13 configuration */ + uint32_t CFC12:1; /* CF 12 configuration */ + uint32_t CFC11:1; /* CF 11 configuration */ + uint32_t CFC10:1; /* CF 10 configuration */ + uint32_t CFC9:1; /* CF 9 configuration */ + uint32_t CFC8:1; /* CF 8 configuration */ + uint32_t CFC7:1; /* CF 7 configuration */ + uint32_t CFC6:1; /* CF 6 configuration */ + uint32_t CFC5:1; /* CF 5 configuration */ + uint32_t CFC4:1; /* CF 4 configuration */ + uint32_t CFC3:1; /* CF 3 configuration */ + uint32_t CFC2:1; /* CF 2 configuration */ + uint32_t CFC1:1; /* CF 1 configuration */ + uint32_t CFC0:1; /* CF 0 configuration */ + } B; + } FCCU_CF_CFG0_32B_tag; + + typedef union { /* FCCU CF Configuration Register 1 */ + uint32_t R; + struct { + uint32_t CFC63:1; /* CF 63 configuration */ + uint32_t CFC62:1; /* CF 62 configuration */ + uint32_t CFC61:1; /* CF 61 configuration */ + uint32_t CFC60:1; /* CF 60 configuration */ + uint32_t CFC59:1; /* CF 59 configuration */ + uint32_t CFC58:1; /* CF 58 configuration */ + uint32_t CFC57:1; /* CF 57 configuration */ + uint32_t CFC56:1; /* CF 56 configuration */ + uint32_t CFC55:1; /* CF 55 configuration */ + uint32_t CFC54:1; /* CF 54 configuration */ + uint32_t CFC53:1; /* CF 53 configuration */ + uint32_t CFC52:1; /* CF 52 configuration */ + uint32_t CFC51:1; /* CF 51 configuration */ + uint32_t CFC50:1; /* CF 50 configuration */ + uint32_t CFC49:1; /* CF 49 configuration */ + uint32_t CFC48:1; /* CF 48 configuration */ + uint32_t CFC47:1; /* CF 47 configuration */ + uint32_t CFC46:1; /* CF 46 configuration */ + uint32_t CFC45:1; /* CF 45 configuration */ + uint32_t CFC44:1; /* CF 44 configuration */ + uint32_t CFC43:1; /* CF 43 configuration */ + uint32_t CFC42:1; /* CF 42 configuration */ + uint32_t CFC41:1; /* CF 41 configuration */ + uint32_t CFC40:1; /* CF 40 configuration */ + uint32_t CFC39:1; /* CF 39 configuration */ + uint32_t CFC38:1; /* CF 38 configuration */ + uint32_t CFC37:1; /* CF 37 configuration */ + uint32_t CFC36:1; /* CF 36 configuration */ + uint32_t CFC35:1; /* CF 35 configuration */ + uint32_t CFC34:1; /* CF 34 configuration */ + uint32_t CFC33:1; /* CF 33 configuration */ + uint32_t CFC32:1; /* CF 32 configuration */ + } B; + } FCCU_CF_CFG1_32B_tag; + + typedef union { /* FCCU CF Configuration Register 2 */ + uint32_t R; + struct { + uint32_t CFC95:1; /* CF 95 configuration */ + uint32_t CFC94:1; /* CF 94 configuration */ + uint32_t CFC93:1; /* CF 93 configuration */ + uint32_t CFC92:1; /* CF 92 configuration */ + uint32_t CFC91:1; /* CF 91 configuration */ + uint32_t CFC90:1; /* CF 90 configuration */ + uint32_t CFC89:1; /* CF 89 configuration */ + uint32_t CFC88:1; /* CF 88 configuration */ + uint32_t CFC87:1; /* CF 87 configuration */ + uint32_t CFC86:1; /* CF 86 configuration */ + uint32_t CFC85:1; /* CF 85 configuration */ + uint32_t CFC84:1; /* CF 84 configuration */ + uint32_t CFC83:1; /* CF 83 configuration */ + uint32_t CFC82:1; /* CF 82 configuration */ + uint32_t CFC81:1; /* CF 81 configuration */ + uint32_t CFC80:1; /* CF 80 configuration */ + uint32_t CFC79:1; /* CF 79 configuration */ + uint32_t CFC78:1; /* CF 78 configuration */ + uint32_t CFC77:1; /* CF 77 configuration */ + uint32_t CFC76:1; /* CF 76 configuration */ + uint32_t CFC75:1; /* CF 75 configuration */ + uint32_t CFC74:1; /* CF 74 configuration */ + uint32_t CFC73:1; /* CF 73 configuration */ + uint32_t CFC72:1; /* CF 72 configuration */ + uint32_t CFC71:1; /* CF 71 configuration */ + uint32_t CFC70:1; /* CF 70 configuration */ + uint32_t CFC69:1; /* CF 69 configuration */ + uint32_t CFC68:1; /* CF 68 configuration */ + uint32_t CFC67:1; /* CF 67 configuration */ + uint32_t CFC66:1; /* CF 66 configuration */ + uint32_t CFC65:1; /* CF 65 configuration */ + uint32_t CFC64:1; /* CF 64 configuration */ + } B; + } FCCU_CF_CFG2_32B_tag; + + typedef union { /* FCCU CF Configuration Register 3 */ + uint32_t R; + struct { + uint32_t CFC127:1; /* CF 127 configuration */ + uint32_t CFC126:1; /* CF 126 configuration */ + uint32_t CFC125:1; /* CF 125 configuration */ + uint32_t CFC124:1; /* CF 124 configuration */ + uint32_t CFC123:1; /* CF 123 configuration */ + uint32_t CFC122:1; /* CF 122 configuration */ + uint32_t CFC121:1; /* CF 121 configuration */ + uint32_t CFC120:1; /* CF 120 configuration */ + uint32_t CFC119:1; /* CF 119 configuration */ + uint32_t CFC118:1; /* CF 118 configuration */ + uint32_t CFC117:1; /* CF 117 configuration */ + uint32_t CFC116:1; /* CF 116 configuration */ + uint32_t CFC115:1; /* CF 115 configuration */ + uint32_t CFC114:1; /* CF 114 configuration */ + uint32_t CFC113:1; /* CF 113 configuration */ + uint32_t CFC112:1; /* CF 112 configuration */ + uint32_t CFC111:1; /* CF 111 configuration */ + uint32_t CFC110:1; /* CF 110 configuration */ + uint32_t CFC109:1; /* CF 109 configuration */ + uint32_t CFC108:1; /* CF 108 configuration */ + uint32_t CFC107:1; /* CF 107 configuration */ + uint32_t CFC106:1; /* CF 106 configuration */ + uint32_t CFC105:1; /* CF 105 configuration */ + uint32_t CFC104:1; /* CF 104 configuration */ + uint32_t CFC103:1; /* CF 103 configuration */ + uint32_t CFC102:1; /* CF 102 configuration */ + uint32_t CFC101:1; /* CF 101 configuration */ + uint32_t CFC100:1; /* CF 100 configuration */ + uint32_t CFC99:1; /* CF 99 configuration */ + uint32_t CFC98:1; /* CF 98 configuration */ + uint32_t CFC97:1; /* CF 97 configuration */ + uint32_t CFC96:1; /* CF 96 configuration */ + } B; + } FCCU_CF_CFG3_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 0 */ + uint32_t R; + struct { + uint32_t NCFC31:1; /* NCF 31 configuration */ + uint32_t NCFC30:1; /* NCF 30 configuration */ + uint32_t NCFC29:1; /* NCF 29 configuration */ + uint32_t NCFC28:1; /* NCF 28 configuration */ + uint32_t NCFC27:1; /* NCF 27 configuration */ + uint32_t NCFC26:1; /* NCF 26 configuration */ + uint32_t NCFC25:1; /* NCF 25 configuration */ + uint32_t NCFC24:1; /* NCF 24 configuration */ + uint32_t NCFC23:1; /* NCF 23 configuration */ + uint32_t NCFC22:1; /* NCF 22 configuration */ + uint32_t NCFC21:1; /* NCF 21 configuration */ + uint32_t NCFC20:1; /* NCF 20 configuration */ + uint32_t NCFC19:1; /* NCF 19 configuration */ + uint32_t NCFC18:1; /* NCF 18 configuration */ + uint32_t NCFC17:1; /* NCF 17 configuration */ + uint32_t NCFC16:1; /* NCF 16 configuration */ + uint32_t NCFC15:1; /* NCF 15 configuration */ + uint32_t NCFC14:1; /* NCF 14 configuration */ + uint32_t NCFC13:1; /* NCF 13 configuration */ + uint32_t NCFC12:1; /* NCF 12 configuration */ + uint32_t NCFC11:1; /* NCF 11 configuration */ + uint32_t NCFC10:1; /* NCF 10 configuration */ + uint32_t NCFC9:1; /* NCF 9 configuration */ + uint32_t NCFC8:1; /* NCF 8 configuration */ + uint32_t NCFC7:1; /* NCF 7 configuration */ + uint32_t NCFC6:1; /* NCF 6 configuration */ + uint32_t NCFC5:1; /* NCF 5 configuration */ + uint32_t NCFC4:1; /* NCF 4 configuration */ + uint32_t NCFC3:1; /* NCF 3 configuration */ + uint32_t NCFC2:1; /* NCF 2 configuration */ + uint32_t NCFC1:1; /* NCF 1 configuration */ + uint32_t NCFC0:1; /* NCF 0 configuration */ + } B; + } FCCU_NCF_CFG0_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 1 */ + uint32_t R; + struct { + uint32_t NCFC63:1; /* NCF 63 configuration */ + uint32_t NCFC62:1; /* NCF 62 configuration */ + uint32_t NCFC61:1; /* NCF 61 configuration */ + uint32_t NCFC60:1; /* NCF 60 configuration */ + uint32_t NCFC59:1; /* NCF 59 configuration */ + uint32_t NCFC58:1; /* NCF 58 configuration */ + uint32_t NCFC57:1; /* NCF 57 configuration */ + uint32_t NCFC56:1; /* NCF 56 configuration */ + uint32_t NCFC55:1; /* NCF 55 configuration */ + uint32_t NCFC54:1; /* NCF 54 configuration */ + uint32_t NCFC53:1; /* NCF 53 configuration */ + uint32_t NCFC52:1; /* NCF 52 configuration */ + uint32_t NCFC51:1; /* NCF 51 configuration */ + uint32_t NCFC50:1; /* NCF 50 configuration */ + uint32_t NCFC49:1; /* NCF 49 configuration */ + uint32_t NCFC48:1; /* NCF 48 configuration */ + uint32_t NCFC47:1; /* NCF 47 configuration */ + uint32_t NCFC46:1; /* NCF 46 configuration */ + uint32_t NCFC45:1; /* NCF 45 configuration */ + uint32_t NCFC44:1; /* NCF 44 configuration */ + uint32_t NCFC43:1; /* NCF 43 configuration */ + uint32_t NCFC42:1; /* NCF 42 configuration */ + uint32_t NCFC41:1; /* NCF 41 configuration */ + uint32_t NCFC40:1; /* NCF 40 configuration */ + uint32_t NCFC39:1; /* NCF 39 configuration */ + uint32_t NCFC38:1; /* NCF 38 configuration */ + uint32_t NCFC37:1; /* NCF 37 configuration */ + uint32_t NCFC36:1; /* NCF 36 configuration */ + uint32_t NCFC35:1; /* NCF 35 configuration */ + uint32_t NCFC34:1; /* NCF 34 configuration */ + uint32_t NCFC33:1; /* NCF 33 configuration */ + uint32_t NCFC32:1; /* NCF 32 configuration */ + } B; + } FCCU_NCF_CFG1_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 2 */ + uint32_t R; + struct { + uint32_t NCFC95:1; /* NCF 95 configuration */ + uint32_t NCFC94:1; /* NCF 94 configuration */ + uint32_t NCFC93:1; /* NCF 93 configuration */ + uint32_t NCFC92:1; /* NCF 92 configuration */ + uint32_t NCFC91:1; /* NCF 91 configuration */ + uint32_t NCFC90:1; /* NCF 90 configuration */ + uint32_t NCFC89:1; /* NCF 89 configuration */ + uint32_t NCFC88:1; /* NCF 88 configuration */ + uint32_t NCFC87:1; /* NCF 87 configuration */ + uint32_t NCFC86:1; /* NCF 86 configuration */ + uint32_t NCFC85:1; /* NCF 85 configuration */ + uint32_t NCFC84:1; /* NCF 84 configuration */ + uint32_t NCFC83:1; /* NCF 83 configuration */ + uint32_t NCFC82:1; /* NCF 82 configuration */ + uint32_t NCFC81:1; /* NCF 81 configuration */ + uint32_t NCFC80:1; /* NCF 80 configuration */ + uint32_t NCFC79:1; /* NCF 79 configuration */ + uint32_t NCFC78:1; /* NCF 78 configuration */ + uint32_t NCFC77:1; /* NCF 77 configuration */ + uint32_t NCFC76:1; /* NCF 76 configuration */ + uint32_t NCFC75:1; /* NCF 75 configuration */ + uint32_t NCFC74:1; /* NCF 74 configuration */ + uint32_t NCFC73:1; /* NCF 73 configuration */ + uint32_t NCFC72:1; /* NCF 72 configuration */ + uint32_t NCFC71:1; /* NCF 71 configuration */ + uint32_t NCFC70:1; /* NCF 70 configuration */ + uint32_t NCFC69:1; /* NCF 69 configuration */ + uint32_t NCFC68:1; /* NCF 68 configuration */ + uint32_t NCFC67:1; /* NCF 67 configuration */ + uint32_t NCFC66:1; /* NCF 66 configuration */ + uint32_t NCFC65:1; /* NCF 65 configuration */ + uint32_t NCFC64:1; /* NCF 64 configuration */ + } B; + } FCCU_NCF_CFG2_32B_tag; + + typedef union { /* FCCU NCF Configuration Register 3 */ + uint32_t R; + struct { + uint32_t NCFC127:1; /* NCF 127 configuration */ + uint32_t NCFC126:1; /* NCF 126 configuration */ + uint32_t NCFC125:1; /* NCF 125 configuration */ + uint32_t NCFC124:1; /* NCF 124 configuration */ + uint32_t NCFC123:1; /* NCF 123 configuration */ + uint32_t NCFC122:1; /* NCF 122 configuration */ + uint32_t NCFC121:1; /* NCF 121 configuration */ + uint32_t NCFC120:1; /* NCF 120 configuration */ + uint32_t NCFC119:1; /* NCF 119 configuration */ + uint32_t NCFC118:1; /* NCF 118 configuration */ + uint32_t NCFC117:1; /* NCF 117 configuration */ + uint32_t NCFC116:1; /* NCF 116 configuration */ + uint32_t NCFC115:1; /* NCF 115 configuration */ + uint32_t NCFC114:1; /* NCF 114 configuration */ + uint32_t NCFC113:1; /* NCF 113 configuration */ + uint32_t NCFC112:1; /* NCF 112 configuration */ + uint32_t NCFC111:1; /* NCF 111 configuration */ + uint32_t NCFC110:1; /* NCF 110 configuration */ + uint32_t NCFC109:1; /* NCF 109 configuration */ + uint32_t NCFC108:1; /* NCF 108 configuration */ + uint32_t NCFC107:1; /* NCF 107 configuration */ + uint32_t NCFC106:1; /* NCF 106 configuration */ + uint32_t NCFC105:1; /* NCF 105 configuration */ + uint32_t NCFC104:1; /* NCF 104 configuration */ + uint32_t NCFC103:1; /* NCF 103 configuration */ + uint32_t NCFC102:1; /* NCF 102 configuration */ + uint32_t NCFC101:1; /* NCF 101 configuration */ + uint32_t NCFC100:1; /* NCF 100 configuration */ + uint32_t NCFC99:1; /* NCF 99 configuration */ + uint32_t NCFC98:1; /* NCF 98 configuration */ + uint32_t NCFC97:1; /* NCF 97 configuration */ + uint32_t NCFC96:1; /* NCF 96 configuration */ + } B; + } FCCU_NCF_CFG3_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 0 */ + uint32_t R; + struct { + uint32_t CFSC15:2; /* CF 15 state configuration */ + uint32_t CFSC14:2; /* CF 14 state configuration */ + uint32_t CFSC13:2; /* CF 13 state configuration */ + uint32_t CFSC12:2; /* CF 12 state configuration */ + uint32_t CFSC11:2; /* CF 11 state configuration */ + uint32_t CFSC10:2; /* CF 10 state configuration */ + uint32_t CFSC9:2; /* CF 9 state configuration */ + uint32_t CFSC8:2; /* CF 8 state configuration */ + uint32_t CFSC7:2; /* CF 7 state configuration */ + uint32_t CFSC6:2; /* CF 6 state configuration */ + uint32_t CFSC5:2; /* CF 5 state configuration */ + uint32_t CFSC4:2; /* CF 4 state configuration */ + uint32_t CFSC3:2; /* CF 3 state configuration */ + uint32_t CFSC2:2; /* CF 2 state configuration */ + uint32_t CFSC1:2; /* CF 1 state configuration */ + uint32_t CFSC0:2; /* CF 0 state configuration */ + } B; + } FCCU_CFS_CFG0_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 1 */ + uint32_t R; + struct { + uint32_t CFSC31:2; /* CF 31 state configuration */ + uint32_t CFSC30:2; /* CF 30 state configuration */ + uint32_t CFSC29:2; /* CF 29 state configuration */ + uint32_t CFSC28:2; /* CF 28 state configuration */ + uint32_t CFSC27:2; /* CF 27 state configuration */ + uint32_t CFSC26:2; /* CF 26 state configuration */ + uint32_t CFSC25:2; /* CF 25 state configuration */ + uint32_t CFSC24:2; /* CF 24 state configuration */ + uint32_t CFSC23:2; /* CF 23 state configuration */ + uint32_t CFSC22:2; /* CF 22 state configuration */ + uint32_t CFSC21:2; /* CF 21 state configuration */ + uint32_t CFSC20:2; /* CF 20 state configuration */ + uint32_t CFSC19:2; /* CF 19 state configuration */ + uint32_t CFSC18:2; /* CF 18 state configuration */ + uint32_t CFSC17:2; /* CF 17 state configuration */ + uint32_t CFSC16:2; /* CF 16 state configuration */ + } B; + } FCCU_CFS_CFG1_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 2 */ + uint32_t R; + struct { + uint32_t CFSC47:2; /* CF 47 state configuration */ + uint32_t CFSC46:2; /* CF 46 state configuration */ + uint32_t CFSC45:2; /* CF 45 state configuration */ + uint32_t CFSC44:2; /* CF 44 state configuration */ + uint32_t CFSC43:2; /* CF 43 state configuration */ + uint32_t CFSC42:2; /* CF 42 state configuration */ + uint32_t CFSC41:2; /* CF 41 state configuration */ + uint32_t CFSC40:2; /* CF 40 state configuration */ + uint32_t CFSC39:2; /* CF 39 state configuration */ + uint32_t CFSC38:2; /* CF 38 state configuration */ + uint32_t CFSC37:2; /* CF 37 state configuration */ + uint32_t CFSC36:2; /* CF 36 state configuration */ + uint32_t CFSC35:2; /* CF 35 state configuration */ + uint32_t CFSC34:2; /* CF 34 state configuration */ + uint32_t CFSC33:2; /* CF 33 state configuration */ + uint32_t CFSC32:2; /* CF 32 state configuration */ + } B; + } FCCU_CFS_CFG2_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 3 */ + uint32_t R; + struct { + uint32_t CFSC63:2; /* CF 63 state configuration */ + uint32_t CFSC62:2; /* CF 62 state configuration */ + uint32_t CFSC61:2; /* CF 61 state configuration */ + uint32_t CFSC60:2; /* CF 60 state configuration */ + uint32_t CFSC59:2; /* CF 59 state configuration */ + uint32_t CFSC58:2; /* CF 58 state configuration */ + uint32_t CFSC57:2; /* CF 57 state configuration */ + uint32_t CFSC56:2; /* CF 56 state configuration */ + uint32_t CFSC55:2; /* CF 55 state configuration */ + uint32_t CFSC54:2; /* CF 54 state configuration */ + uint32_t CFSC53:2; /* CF 53 state configuration */ + uint32_t CFSC52:2; /* CF 52 state configuration */ + uint32_t CFSC51:2; /* CF 51 state configuration */ + uint32_t CFSC50:2; /* CF 50 state configuration */ + uint32_t CFSC49:2; /* CF 49 state configuration */ + uint32_t CFSC48:2; /* CF 48 state configuration */ + } B; + } FCCU_CFS_CFG3_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 4 */ + uint32_t R; + struct { + uint32_t CFSC79:2; /* CF 79 state configuration */ + uint32_t CFSC78:2; /* CF 78 state configuration */ + uint32_t CFSC77:2; /* CF 77 state configuration */ + uint32_t CFSC76:2; /* CF 76 state configuration */ + uint32_t CFSC75:2; /* CF 75 state configuration */ + uint32_t CFSC74:2; /* CF 74 state configuration */ + uint32_t CFSC73:2; /* CF 73 state configuration */ + uint32_t CFSC72:2; /* CF 72 state configuration */ + uint32_t CFSC71:2; /* CF 71 state configuration */ + uint32_t CFSC70:2; /* CF 70 state configuration */ + uint32_t CFSC69:2; /* CF 69 state configuration */ + uint32_t CFSC68:2; /* CF 68 state configuration */ + uint32_t CFSC67:2; /* CF 67 state configuration */ + uint32_t CFSC66:2; /* CF 66 state configuration */ + uint32_t CFSC65:2; /* CF 65 state configuration */ + uint32_t CFSC64:2; /* CF 64 state configuration */ + } B; + } FCCU_CFS_CFG4_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 5 */ + uint32_t R; + struct { + uint32_t CFSC95:2; /* CF 95 state configuration */ + uint32_t CFSC94:2; /* CF 94 state configuration */ + uint32_t CFSC93:2; /* CF 93 state configuration */ + uint32_t CFSC92:2; /* CF 92 state configuration */ + uint32_t CFSC91:2; /* CF 91 state configuration */ + uint32_t CFSC90:2; /* CF 90 state configuration */ + uint32_t CFSC89:2; /* CF 89 state configuration */ + uint32_t CFSC88:2; /* CF 88 state configuration */ + uint32_t CFSC87:2; /* CF 87 state configuration */ + uint32_t CFSC86:2; /* CF 86 state configuration */ + uint32_t CFSC85:2; /* CF 85 state configuration */ + uint32_t CFSC84:2; /* CF 84 state configuration */ + uint32_t CFSC83:2; /* CF 83 state configuration */ + uint32_t CFSC82:2; /* CF 82 state configuration */ + uint32_t CFSC81:2; /* CF 81 state configuration */ + uint32_t CFSC80:2; /* CF 80 state configuration */ + } B; + } FCCU_CFS_CFG5_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 6 */ + uint32_t R; + struct { + uint32_t CFSC111:2; /* CF 111 state configuration */ + uint32_t CFSC110:2; /* CF 110 state configuration */ + uint32_t CFSC109:2; /* CF 109 state configuration */ + uint32_t CFSC108:2; /* CF 108 state configuration */ + uint32_t CFSC107:2; /* CF 107 state configuration */ + uint32_t CFSC106:2; /* CF 106 state configuration */ + uint32_t CFSC105:2; /* CF 105 state configuration */ + uint32_t CFSC104:2; /* CF 104 state configuration */ + uint32_t CFSC103:2; /* CF 103 state configuration */ + uint32_t CFSC102:2; /* CF 102 state configuration */ + uint32_t CFSC101:2; /* CF 101 state configuration */ + uint32_t CFSC100:2; /* CF 100 state configuration */ + uint32_t CFSC99:2; /* CF 99 state configuration */ + uint32_t CFSC98:2; /* CF 98 state configuration */ + uint32_t CFSC97:2; /* CF 97 state configuration */ + uint32_t CFSC96:2; /* CF 96 state configuration */ + } B; + } FCCU_CFS_CFG6_32B_tag; + + typedef union { /* FCCU CFS Configuration Register 7 */ + uint32_t R; + struct { + uint32_t CFSC127:2; /* CF 127 state configuration */ + uint32_t CFSC126:2; /* CF 126 state configuration */ + uint32_t CFSC125:2; /* CF 125 state configuration */ + uint32_t CFSC124:2; /* CF 124 state configuration */ + uint32_t CFSC123:2; /* CF 123 state configuration */ + uint32_t CFSC122:2; /* CF 122 state configuration */ + uint32_t CFSC121:2; /* CF 121 state configuration */ + uint32_t CFSC120:2; /* CF 120 state configuration */ + uint32_t CFSC119:2; /* CF 119 state configuration */ + uint32_t CFSC118:2; /* CF 118 state configuration */ + uint32_t CFSC117:2; /* CF 117 state configuration */ + uint32_t CFSC116:2; /* CF 116 state configuration */ + uint32_t CFSC115:2; /* CF 115 state configuration */ + uint32_t CFSC114:2; /* CF 114 state configuration */ + uint32_t CFSC113:2; /* CF 113 state configuration */ + uint32_t CFSC112:2; /* CF 112 state configuration */ + } B; + } FCCU_CFS_CFG7_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 0 */ + uint32_t R; + struct { + uint32_t NCFSC15:2; /* NCF 15 state configuration */ + uint32_t NCFSC14:2; /* NCF 14 state configuration */ + uint32_t NCFSC13:2; /* NCF 13 state configuration */ + uint32_t NCFSC12:2; /* NCF 12 state configuration */ + uint32_t NCFSC11:2; /* NCF 11 state configuration */ + uint32_t NCFSC10:2; /* NCF 10 state configuration */ + uint32_t NCFSC9:2; /* NCF 9 state configuration */ + uint32_t NCFSC8:2; /* NCF 8 state configuration */ + uint32_t NCFSC7:2; /* NCF 7 state configuration */ + uint32_t NCFSC6:2; /* NCF 6 state configuration */ + uint32_t NCFSC5:2; /* NCF 5 state configuration */ + uint32_t NCFSC4:2; /* NCF 4 state configuration */ + uint32_t NCFSC3:2; /* NCF 3 state configuration */ + uint32_t NCFSC2:2; /* NCF 2 state configuration */ + uint32_t NCFSC1:2; /* NCF 1 state configuration */ + uint32_t NCFSC0:2; /* NCF 0 state configuration */ + } B; + } FCCU_NCFS_CFG0_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 1 */ + uint32_t R; + struct { + uint32_t NCFSC31:2; /* NCF 31 state configuration */ + uint32_t NCFSC30:2; /* NCF 30 state configuration */ + uint32_t NCFSC29:2; /* NCF 29 state configuration */ + uint32_t NCFSC28:2; /* NCF 28 state configuration */ + uint32_t NCFSC27:2; /* NCF 27 state configuration */ + uint32_t NCFSC26:2; /* NCF 26 state configuration */ + uint32_t NCFSC25:2; /* NCF 25 state configuration */ + uint32_t NCFSC24:2; /* NCF 24 state configuration */ + uint32_t NCFSC23:2; /* NCF 23 state configuration */ + uint32_t NCFSC22:2; /* NCF 22 state configuration */ + uint32_t NCFSC21:2; /* NCF 21 state configuration */ + uint32_t NCFSC20:2; /* NCF 20 state configuration */ + uint32_t NCFSC19:2; /* NCF 19 state configuration */ + uint32_t NCFSC18:2; /* NCF 18 state configuration */ + uint32_t NCFSC17:2; /* NCF 17 state configuration */ + uint32_t NCFSC16:2; /* NCF 16 state configuration */ + } B; + } FCCU_NCFS_CFG1_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 2 */ + uint32_t R; + struct { + uint32_t NCFSC47:2; /* NCF 47 state configuration */ + uint32_t NCFSC46:2; /* NCF 46 state configuration */ + uint32_t NCFSC45:2; /* NCF 45 state configuration */ + uint32_t NCFSC44:2; /* NCF 44 state configuration */ + uint32_t NCFSC43:2; /* NCF 43 state configuration */ + uint32_t NCFSC42:2; /* NCF 42 state configuration */ + uint32_t NCFSC41:2; /* NCF 41 state configuration */ + uint32_t NCFSC40:2; /* NCF 40 state configuration */ + uint32_t NCFSC39:2; /* NCF 39 state configuration */ + uint32_t NCFSC38:2; /* NCF 38 state configuration */ + uint32_t NCFSC37:2; /* NCF 37 state configuration */ + uint32_t NCFSC36:2; /* NCF 36 state configuration */ + uint32_t NCFSC35:2; /* NCF 35 state configuration */ + uint32_t NCFSC34:2; /* NCF 34 state configuration */ + uint32_t NCFSC33:2; /* NCF 33 state configuration */ + uint32_t NCFSC32:2; /* NCF 32 state configuration */ + } B; + } FCCU_NCFS_CFG2_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 3 */ + uint32_t R; + struct { + uint32_t NCFSC63:2; /* NCF 63 state configuration */ + uint32_t NCFSC62:2; /* NCF 62 state configuration */ + uint32_t NCFSC61:2; /* NCF 61 state configuration */ + uint32_t NCFSC60:2; /* NCF 60 state configuration */ + uint32_t NCFSC59:2; /* NCF 59 state configuration */ + uint32_t NCFSC58:2; /* NCF 58 state configuration */ + uint32_t NCFSC57:2; /* NCF 57 state configuration */ + uint32_t NCFSC56:2; /* NCF 56 state configuration */ + uint32_t NCFSC55:2; /* NCF 55 state configuration */ + uint32_t NCFSC54:2; /* NCF 54 state configuration */ + uint32_t NCFSC53:2; /* NCF 53 state configuration */ + uint32_t NCFSC52:2; /* NCF 52 state configuration */ + uint32_t NCFSC51:2; /* NCF 51 state configuration */ + uint32_t NCFSC50:2; /* NCF 50 state configuration */ + uint32_t NCFSC49:2; /* NCF 49 state configuration */ + uint32_t NCFSC48:2; /* NCF 48 state configuration */ + } B; + } FCCU_NCFS_CFG3_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 4 */ + uint32_t R; + struct { + uint32_t NCFSC79:2; /* NCF 79 state configuration */ + uint32_t NCFSC78:2; /* NCF 78 state configuration */ + uint32_t NCFSC77:2; /* NCF 77 state configuration */ + uint32_t NCFSC76:2; /* NCF 76 state configuration */ + uint32_t NCFSC75:2; /* NCF 75 state configuration */ + uint32_t NCFSC74:2; /* NCF 74 state configuration */ + uint32_t NCFSC73:2; /* NCF 73 state configuration */ + uint32_t NCFSC72:2; /* NCF 72 state configuration */ + uint32_t NCFSC71:2; /* NCF 71 state configuration */ + uint32_t NCFSC70:2; /* NCF 70 state configuration */ + uint32_t NCFSC69:2; /* NCF 69 state configuration */ + uint32_t NCFSC68:2; /* NCF 68 state configuration */ + uint32_t NCFSC67:2; /* NCF 67 state configuration */ + uint32_t NCFSC66:2; /* NCF 66 state configuration */ + uint32_t NCFSC65:2; /* NCF 65 state configuration */ + uint32_t NCFSC64:2; /* NCF 64 state configuration */ + } B; + } FCCU_NCFS_CFG4_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 5 */ + uint32_t R; + struct { + uint32_t NCFSC95:2; /* NCF 95 state configuration */ + uint32_t NCFSC94:2; /* NCF 94 state configuration */ + uint32_t NCFSC93:2; /* NCF 93 state configuration */ + uint32_t NCFSC92:2; /* NCF 92 state configuration */ + uint32_t NCFSC91:2; /* NCF 91 state configuration */ + uint32_t NCFSC90:2; /* NCF 90 state configuration */ + uint32_t NCFSC89:2; /* NCF 89 state configuration */ + uint32_t NCFSC88:2; /* NCF 88 state configuration */ + uint32_t NCFSC87:2; /* NCF 87 state configuration */ + uint32_t NCFSC86:2; /* NCF 86 state configuration */ + uint32_t NCFSC85:2; /* NCF 85 state configuration */ + uint32_t NCFSC84:2; /* NCF 84 state configuration */ + uint32_t NCFSC83:2; /* NCF 83 state configuration */ + uint32_t NCFSC82:2; /* NCF 82 state configuration */ + uint32_t NCFSC81:2; /* NCF 81 state configuration */ + uint32_t NCFSC80:2; /* NCF 80 state configuration */ + } B; + } FCCU_NCFS_CFG5_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 6 */ + uint32_t R; + struct { + uint32_t NCFSC111:2; /* NCF 111 state configuration */ + uint32_t NCFSC110:2; /* NCF 110 state configuration */ + uint32_t NCFSC109:2; /* NCF 109 state configuration */ + uint32_t NCFSC108:2; /* NCF 108 state configuration */ + uint32_t NCFSC107:2; /* NCF 107 state configuration */ + uint32_t NCFSC106:2; /* NCF 106 state configuration */ + uint32_t NCFSC105:2; /* NCF 105 state configuration */ + uint32_t NCFSC104:2; /* NCF 104 state configuration */ + uint32_t NCFSC103:2; /* NCF 103 state configuration */ + uint32_t NCFSC102:2; /* NCF 102 state configuration */ + uint32_t NCFSC101:2; /* NCF 101 state configuration */ + uint32_t NCFSC100:2; /* NCF 100 state configuration */ + uint32_t NCFSC99:2; /* NCF 99 state configuration */ + uint32_t NCFSC98:2; /* NCF 98 state configuration */ + uint32_t NCFSC97:2; /* NCF 97 state configuration */ + uint32_t NCFSC96:2; /* NCF 96 state configuration */ + } B; + } FCCU_NCFS_CFG6_32B_tag; + + typedef union { /* FCCU NCFS Configuration Register 7 */ + uint32_t R; + struct { + uint32_t NCFSC127:2; /* NCF 127 state configuration */ + uint32_t NCFSC126:2; /* NCF 126 state configuration */ + uint32_t NCFSC125:2; /* NCF 125 state configuration */ + uint32_t NCFSC124:2; /* NCF 124 state configuration */ + uint32_t NCFSC123:2; /* NCF 123 state configuration */ + uint32_t NCFSC122:2; /* NCF 122 state configuration */ + uint32_t NCFSC121:2; /* NCF 121 state configuration */ + uint32_t NCFSC120:2; /* NCF 120 state configuration */ + uint32_t NCFSC119:2; /* NCF 119 state configuration */ + uint32_t NCFSC118:2; /* NCF 118 state configuration */ + uint32_t NCFSC117:2; /* NCF 117 state configuration */ + uint32_t NCFSC116:2; /* NCF 116 state configuration */ + uint32_t NCFSC115:2; /* NCF 115 state configuration */ + uint32_t NCFSC114:2; /* NCF 114 state configuration */ + uint32_t NCFSC113:2; /* NCF 113 state configuration */ + uint32_t NCFSC112:2; /* NCF 112 state configuration */ + } B; + } FCCU_NCFS_CFG7_32B_tag; + + typedef union { /* FCCU CF Status Register 0 */ + uint32_t R; + struct { + uint32_t CFS31:1; /* CF 31 status */ + uint32_t CFS30:1; /* CF 30 status */ + uint32_t CFS29:1; /* CF 29 status */ + uint32_t CFS28:1; /* CF 28 status */ + uint32_t CFS27:1; /* CF 27 status */ + uint32_t CFS26:1; /* CF 26 status */ + uint32_t CFS25:1; /* CF 25 status */ + uint32_t CFS24:1; /* CF 24 status */ + uint32_t CFS23:1; /* CF 23 status */ + uint32_t CFS22:1; /* CF 22 status */ + uint32_t CFS21:1; /* CF 21 status */ + uint32_t CFS20:1; /* CF 20 status */ + uint32_t CFS19:1; /* CF 19 status */ + uint32_t CFS18:1; /* CF 18 status */ + uint32_t CFS17:1; /* CF 17 status */ + uint32_t CFS16:1; /* CF 16 status */ + uint32_t CFS15:1; /* CF 15 status */ + uint32_t CFS14:1; /* CF 14 status */ + uint32_t CFS13:1; /* CF 13 status */ + uint32_t CFS12:1; /* CF 12 status */ + uint32_t CFS11:1; /* CF 11 status */ + uint32_t CFS10:1; /* CF 10 status */ + uint32_t CFS9:1; /* CF 9 status */ + uint32_t CFS8:1; /* CF 8 status */ + uint32_t CFS7:1; /* CF 7 status */ + uint32_t CFS6:1; /* CF 6 status */ + uint32_t CFS5:1; /* CF 5 status */ + uint32_t CFS4:1; /* CF 4 status */ + uint32_t CFS3:1; /* CF 3 status */ + uint32_t CFS2:1; /* CF 2 status */ + uint32_t CFS1:1; /* CF 1 status */ + uint32_t CFS0:1; /* CF 0 status */ + } B; + } FCCU_CFS0_32B_tag; + + typedef union { /* FCCU CF Status Register 1 */ + uint32_t R; + struct { + uint32_t CFS63:1; /* CF 63 status */ + uint32_t CFS62:1; /* CF 62 status */ + uint32_t CFS61:1; /* CF 61 status */ + uint32_t CFS60:1; /* CF 60 status */ + uint32_t CFS59:1; /* CF 59 status */ + uint32_t CFS58:1; /* CF 58 status */ + uint32_t CFS57:1; /* CF 57 status */ + uint32_t CFS56:1; /* CF 56 status */ + uint32_t CFS55:1; /* CF 55 status */ + uint32_t CFS54:1; /* CF 54 status */ + uint32_t CFS53:1; /* CF 53 status */ + uint32_t CFS52:1; /* CF 52 status */ + uint32_t CFS51:1; /* CF 51 status */ + uint32_t CFS50:1; /* CF 50 status */ + uint32_t CFS49:1; /* CF 49 status */ + uint32_t CFS48:1; /* CF 48 status */ + uint32_t CFS47:1; /* CF 47 status */ + uint32_t CFS46:1; /* CF 46 status */ + uint32_t CFS45:1; /* CF 45 status */ + uint32_t CFS44:1; /* CF 44 status */ + uint32_t CFS43:1; /* CF 43 status */ + uint32_t CFS42:1; /* CF 42 status */ + uint32_t CFS41:1; /* CF 41 status */ + uint32_t CFS40:1; /* CF 40 status */ + uint32_t CFS39:1; /* CF 39 status */ + uint32_t CFS38:1; /* CF 38 status */ + uint32_t CFS37:1; /* CF 37 status */ + uint32_t CFS36:1; /* CF 36 status */ + uint32_t CFS35:1; /* CF 35 status */ + uint32_t CFS34:1; /* CF 34 status */ + uint32_t CFS33:1; /* CF 33 status */ + uint32_t CFS32:1; /* CF 32 status */ + } B; + } FCCU_CFS1_32B_tag; + + typedef union { /* FCCU CF Status Register 2 */ + uint32_t R; + struct { + uint32_t CFS95:1; /* CF 95 status */ + uint32_t CFS94:1; /* CF 94 status */ + uint32_t CFS93:1; /* CF 93 status */ + uint32_t CFS92:1; /* CF 92 status */ + uint32_t CFS91:1; /* CF 91 status */ + uint32_t CFS90:1; /* CF 90 status */ + uint32_t CFS89:1; /* CF 89 status */ + uint32_t CFS88:1; /* CF 88 status */ + uint32_t CFS87:1; /* CF 87 status */ + uint32_t CFS86:1; /* CF 86 status */ + uint32_t CFS85:1; /* CF 85 status */ + uint32_t CFS84:1; /* CF 84 status */ + uint32_t CFS83:1; /* CF 83 status */ + uint32_t CFS82:1; /* CF 82 status */ + uint32_t CFS81:1; /* CF 81 status */ + uint32_t CFS80:1; /* CF 80 status */ + uint32_t CFS79:1; /* CF 79 status */ + uint32_t CFS78:1; /* CF 78 status */ + uint32_t CFS77:1; /* CF 77 status */ + uint32_t CFS76:1; /* CF 76 status */ + uint32_t CFS75:1; /* CF 75 status */ + uint32_t CFS74:1; /* CF 74 status */ + uint32_t CFS73:1; /* CF 73 status */ + uint32_t CFS72:1; /* CF 72 status */ + uint32_t CFS71:1; /* CF 71 status */ + uint32_t CFS70:1; /* CF 70 status */ + uint32_t CFS69:1; /* CF 69 status */ + uint32_t CFS68:1; /* CF 68 status */ + uint32_t CFS67:1; /* CF 67 status */ + uint32_t CFS66:1; /* CF 66 status */ + uint32_t CFS65:1; /* CF 65 status */ + uint32_t CFS64:1; /* CF 64 status */ + } B; + } FCCU_CFS2_32B_tag; + + typedef union { /* FCCU CF Status Register 3 */ + uint32_t R; + struct { + uint32_t CFS127:1; /* CF 127 status */ + uint32_t CFS126:1; /* CF 126 status */ + uint32_t CFS125:1; /* CF 125 status */ + uint32_t CFS124:1; /* CF 124 status */ + uint32_t CFS123:1; /* CF 123 status */ + uint32_t CFS122:1; /* CF 122 status */ + uint32_t CFS121:1; /* CF 121 status */ + uint32_t CFS120:1; /* CF 120 status */ + uint32_t CFS119:1; /* CF 119 status */ + uint32_t CFS118:1; /* CF 118 status */ + uint32_t CFS117:1; /* CF 117 status */ + uint32_t CFS116:1; /* CF 116 status */ + uint32_t CFS115:1; /* CF 115 status */ + uint32_t CFS114:1; /* CF 114 status */ + uint32_t CFS113:1; /* CF 113 status */ + uint32_t CFS112:1; /* CF 112 status */ + uint32_t CFS111:1; /* CF 111 status */ + uint32_t CFS110:1; /* CF 110 status */ + uint32_t CFS109:1; /* CF 109 status */ + uint32_t CFS108:1; /* CF 108 status */ + uint32_t CFS107:1; /* CF 107 status */ + uint32_t CFS106:1; /* CF 106 status */ + uint32_t CFS105:1; /* CF 105 status */ + uint32_t CFS104:1; /* CF 104 status */ + uint32_t CFS103:1; /* CF 103 status */ + uint32_t CFS102:1; /* CF 102 status */ + uint32_t CFS101:1; /* CF 101 status */ + uint32_t CFS100:1; /* CF 100 status */ + uint32_t CFS99:1; /* CF 99 status */ + uint32_t CFS98:1; /* CF 98 status */ + uint32_t CFS97:1; /* CF 97 status */ + uint32_t CFS96:1; /* CF 96 status */ + } B; + } FCCU_CFS3_32B_tag; + + typedef union { /* FCCU_CFK - FCCU CF Key Register */ + uint32_t R; + } FCCU_CFK_32B_tag; + + typedef union { /* FCCU NCF Status Register 0 */ + uint32_t R; + struct { + uint32_t NCFS31:1; /* NCF 31 status */ + uint32_t NCFS30:1; /* NCF 30 status */ + uint32_t NCFS29:1; /* NCF 29 status */ + uint32_t NCFS28:1; /* NCF 28 status */ + uint32_t NCFS27:1; /* NCF 27 status */ + uint32_t NCFS26:1; /* NCF 26 status */ + uint32_t NCFS25:1; /* NCF 25 status */ + uint32_t NCFS24:1; /* NCF 24 status */ + uint32_t NCFS23:1; /* NCF 23 status */ + uint32_t NCFS22:1; /* NCF 22 status */ + uint32_t NCFS21:1; /* NCF 21 status */ + uint32_t NCFS20:1; /* NCF 20 status */ + uint32_t NCFS19:1; /* NCF 19 status */ + uint32_t NCFS18:1; /* NCF 18 status */ + uint32_t NCFS17:1; /* NCF 17 status */ + uint32_t NCFS16:1; /* NCF 16 status */ + uint32_t NCFS15:1; /* NCF 15 status */ + uint32_t NCFS14:1; /* NCF 14 status */ + uint32_t NCFS13:1; /* NCF 13 status */ + uint32_t NCFS12:1; /* NCF 12 status */ + uint32_t NCFS11:1; /* NCF 11 status */ + uint32_t NCFS10:1; /* NCF 10 status */ + uint32_t NCFS9:1; /* NCF 9 status */ + uint32_t NCFS8:1; /* NCF 8 status */ + uint32_t NCFS7:1; /* NCF 7 status */ + uint32_t NCFS6:1; /* NCF 6 status */ + uint32_t NCFS5:1; /* NCF 5 status */ + uint32_t NCFS4:1; /* NCF 4 status */ + uint32_t NCFS3:1; /* NCF 3 status */ + uint32_t NCFS2:1; /* NCF 2 status */ + uint32_t NCFS1:1; /* NCF 1 status */ + uint32_t NCFS0:1; /* NCF 0 status */ + } B; + } FCCU_NCFS0_32B_tag; + + typedef union { /* FCCU NCF Status Register 1 */ + uint32_t R; + struct { + uint32_t NCFS63:1; /* NCF 63 status */ + uint32_t NCFS62:1; /* NCF 62 status */ + uint32_t NCFS61:1; /* NCF 61 status */ + uint32_t NCFS60:1; /* NCF 60 status */ + uint32_t NCFS59:1; /* NCF 59 status */ + uint32_t NCFS58:1; /* NCF 58 status */ + uint32_t NCFS57:1; /* NCF 57 status */ + uint32_t NCFS56:1; /* NCF 56 status */ + uint32_t NCFS55:1; /* NCF 55 status */ + uint32_t NCFS54:1; /* NCF 54 status */ + uint32_t NCFS53:1; /* NCF 53 status */ + uint32_t NCFS52:1; /* NCF 52 status */ + uint32_t NCFS51:1; /* NCF 51 status */ + uint32_t NCFS50:1; /* NCF 50 status */ + uint32_t NCFS49:1; /* NCF 49 status */ + uint32_t NCFS48:1; /* NCF 48 status */ + uint32_t NCFS47:1; /* NCF 47 status */ + uint32_t NCFS46:1; /* NCF 46 status */ + uint32_t NCFS45:1; /* NCF 45 status */ + uint32_t NCFS44:1; /* NCF 44 status */ + uint32_t NCFS43:1; /* NCF 43 status */ + uint32_t NCFS42:1; /* NCF 42 status */ + uint32_t NCFS41:1; /* NCF 41 status */ + uint32_t NCFS40:1; /* NCF 40 status */ + uint32_t NCFS39:1; /* NCF 39 status */ + uint32_t NCFS38:1; /* NCF 38 status */ + uint32_t NCFS37:1; /* NCF 37 status */ + uint32_t NCFS36:1; /* NCF 36 status */ + uint32_t NCFS35:1; /* NCF 35 status */ + uint32_t NCFS34:1; /* NCF 34 status */ + uint32_t NCFS33:1; /* NCF 33 status */ + uint32_t NCFS32:1; /* NCF 32 status */ + } B; + } FCCU_NCFS1_32B_tag; + + typedef union { /* FCCU NCF Status Register 2 */ + uint32_t R; + struct { + uint32_t NCFS95:1; /* NCF 95 status */ + uint32_t NCFS94:1; /* NCF 94 status */ + uint32_t NCFS93:1; /* NCF 93 status */ + uint32_t NCFS92:1; /* NCF 92 status */ + uint32_t NCFS91:1; /* NCF 91 status */ + uint32_t NCFS90:1; /* NCF 90 status */ + uint32_t NCFS89:1; /* NCF 89 status */ + uint32_t NCFS88:1; /* NCF 88 status */ + uint32_t NCFS87:1; /* NCF 87 status */ + uint32_t NCFS86:1; /* NCF 86 status */ + uint32_t NCFS85:1; /* NCF 85 status */ + uint32_t NCFS84:1; /* NCF 84 status */ + uint32_t NCFS83:1; /* NCF 83 status */ + uint32_t NCFS82:1; /* NCF 82 status */ + uint32_t NCFS81:1; /* NCF 81 status */ + uint32_t NCFS80:1; /* NCF 80 status */ + uint32_t NCFS79:1; /* NCF 79 status */ + uint32_t NCFS78:1; /* NCF 78 status */ + uint32_t NCFS77:1; /* NCF 77 status */ + uint32_t NCFS76:1; /* NCF 76 status */ + uint32_t NCFS75:1; /* NCF 75 status */ + uint32_t NCFS74:1; /* NCF 74 status */ + uint32_t NCFS73:1; /* NCF 73 status */ + uint32_t NCFS72:1; /* NCF 72 status */ + uint32_t NCFS71:1; /* NCF 71 status */ + uint32_t NCFS70:1; /* NCF 70 status */ + uint32_t NCFS69:1; /* NCF 69 status */ + uint32_t NCFS68:1; /* NCF 68 status */ + uint32_t NCFS67:1; /* NCF 67 status */ + uint32_t NCFS66:1; /* NCF 66 status */ + uint32_t NCFS65:1; /* NCF 65 status */ + uint32_t NCFS64:1; /* NCF 64 status */ + } B; + } FCCU_NCFS2_32B_tag; + + typedef union { /* FCCU NCF Status Register 3 */ + uint32_t R; + struct { + uint32_t NCFS127:1; /* NCF 127 status */ + uint32_t NCFS126:1; /* NCF 126 status */ + uint32_t NCFS125:1; /* NCF 125 status */ + uint32_t NCFS124:1; /* NCF 124 status */ + uint32_t NCFS123:1; /* NCF 123 status */ + uint32_t NCFS122:1; /* NCF 122 status */ + uint32_t NCFS121:1; /* NCF 121 status */ + uint32_t NCFS120:1; /* NCF 120 status */ + uint32_t NCFS119:1; /* NCF 119 status */ + uint32_t NCFS118:1; /* NCF 118 status */ + uint32_t NCFS117:1; /* NCF 117 status */ + uint32_t NCFS116:1; /* NCF 116 status */ + uint32_t NCFS115:1; /* NCF 115 status */ + uint32_t NCFS114:1; /* NCF 114 status */ + uint32_t NCFS113:1; /* NCF 113 status */ + uint32_t NCFS112:1; /* NCF 112 status */ + uint32_t NCFS111:1; /* NCF 111 status */ + uint32_t NCFS110:1; /* NCF 110 status */ + uint32_t NCFS109:1; /* NCF 109 status */ + uint32_t NCFS108:1; /* NCF 108 status */ + uint32_t NCFS107:1; /* NCF 107 status */ + uint32_t NCFS106:1; /* NCF 106 status */ + uint32_t NCFS105:1; /* NCF 105 status */ + uint32_t NCFS104:1; /* NCF 104 status */ + uint32_t NCFS103:1; /* NCF 103 status */ + uint32_t NCFS102:1; /* NCF 102 status */ + uint32_t NCFS101:1; /* NCF 101 status */ + uint32_t NCFS100:1; /* NCF 100 status */ + uint32_t NCFS99:1; /* NCF 99 status */ + uint32_t NCFS98:1; /* NCF 98 status */ + uint32_t NCFS97:1; /* NCF 97 status */ + uint32_t NCFS96:1; /* NCF 96 status */ + } B; + } FCCU_NCFS3_32B_tag; + + typedef union { /* FCCU_NCFK - FCCU NCF Key Register */ + uint32_t R; + } FCCU_NCFK_32B_tag; + + typedef union { /* FCCU NCF Enable Register 0 */ + uint32_t R; + struct { + uint32_t NCFE31:1; /* NCF 31 enable */ + uint32_t NCFE30:1; /* NCF 30 enable */ + uint32_t NCFE29:1; /* NCF 29 enable */ + uint32_t NCFE28:1; /* NCF 28 enable */ + uint32_t NCFE27:1; /* NCF 27 enable */ + uint32_t NCFE26:1; /* NCF 26 enable */ + uint32_t NCFE25:1; /* NCF 25 enable */ + uint32_t NCFE24:1; /* NCF 24 enable */ + uint32_t NCFE23:1; /* NCF 23 enable */ + uint32_t NCFE22:1; /* NCF 22 enable */ + uint32_t NCFE21:1; /* NCF 21 enable */ + uint32_t NCFE20:1; /* NCF 20 enable */ + uint32_t NCFE19:1; /* NCF 19 enable */ + uint32_t NCFE18:1; /* NCF 18 enable */ + uint32_t NCFE17:1; /* NCF 17 enable */ + uint32_t NCFE16:1; /* NCF 16 enable */ + uint32_t NCFE15:1; /* NCF 15 enable */ + uint32_t NCFE14:1; /* NCF 14 enable */ + uint32_t NCFE13:1; /* NCF 13 enable */ + uint32_t NCFE12:1; /* NCF 12 enable */ + uint32_t NCFE11:1; /* NCF 11 enable */ + uint32_t NCFE10:1; /* NCF 10 enable */ + uint32_t NCFE9:1; /* NCF 9 enable */ + uint32_t NCFE8:1; /* NCF 8 enable */ + uint32_t NCFE7:1; /* NCF 7 enable */ + uint32_t NCFE6:1; /* NCF 6 enable */ + uint32_t NCFE5:1; /* NCF 5 enable */ + uint32_t NCFE4:1; /* NCF 4 enable */ + uint32_t NCFE3:1; /* NCF 3 enable */ + uint32_t NCFE2:1; /* NCF 2 enable */ + uint32_t NCFE1:1; /* NCF 1 enable */ + uint32_t NCFE0:1; /* NCF 0 enable */ + } B; + } FCCU_NCFE0_32B_tag; + + typedef union { /* FCCU NCF Enable Register 1 */ + uint32_t R; + struct { + uint32_t NCFE63:1; /* NCF 63 enable */ + uint32_t NCFE62:1; /* NCF 62 enable */ + uint32_t NCFE61:1; /* NCF 61 enable */ + uint32_t NCFE60:1; /* NCF 60 enable */ + uint32_t NCFE59:1; /* NCF 59 enable */ + uint32_t NCFE58:1; /* NCF 58 enable */ + uint32_t NCFE57:1; /* NCF 57 enable */ + uint32_t NCFE56:1; /* NCF 56 enable */ + uint32_t NCFE55:1; /* NCF 55 enable */ + uint32_t NCFE54:1; /* NCF 54 enable */ + uint32_t NCFE53:1; /* NCF 53 enable */ + uint32_t NCFE52:1; /* NCF 52 enable */ + uint32_t NCFE51:1; /* NCF 51 enable */ + uint32_t NCFE50:1; /* NCF 50 enable */ + uint32_t NCFE49:1; /* NCF 49 enable */ + uint32_t NCFE48:1; /* NCF 48 enable */ + uint32_t NCFE47:1; /* NCF 47 enable */ + uint32_t NCFE46:1; /* NCF 46 enable */ + uint32_t NCFE45:1; /* NCF 45 enable */ + uint32_t NCFE44:1; /* NCF 44 enable */ + uint32_t NCFE43:1; /* NCF 43 enable */ + uint32_t NCFE42:1; /* NCF 42 enable */ + uint32_t NCFE41:1; /* NCF 41 enable */ + uint32_t NCFE40:1; /* NCF 40 enable */ + uint32_t NCFE39:1; /* NCF 39 enable */ + uint32_t NCFE38:1; /* NCF 38 enable */ + uint32_t NCFE37:1; /* NCF 37 enable */ + uint32_t NCFE36:1; /* NCF 36 enable */ + uint32_t NCFE35:1; /* NCF 35 enable */ + uint32_t NCFE34:1; /* NCF 34 enable */ + uint32_t NCFE33:1; /* NCF 33 enable */ + uint32_t NCFE32:1; /* NCF 32 enable */ + } B; + } FCCU_NCFE1_32B_tag; + + typedef union { /* FCCU NCF Enable Register 2 */ + uint32_t R; + struct { + uint32_t NCFE95:1; /* NCF 95 enable */ + uint32_t NCFE94:1; /* NCF 94 enable */ + uint32_t NCFE93:1; /* NCF 93 enable */ + uint32_t NCFE92:1; /* NCF 92 enable */ + uint32_t NCFE91:1; /* NCF 91 enable */ + uint32_t NCFE90:1; /* NCF 90 enable */ + uint32_t NCFE89:1; /* NCF 89 enable */ + uint32_t NCFE88:1; /* NCF 88 enable */ + uint32_t NCFE87:1; /* NCF 87 enable */ + uint32_t NCFE86:1; /* NCF 86 enable */ + uint32_t NCFE85:1; /* NCF 85 enable */ + uint32_t NCFE84:1; /* NCF 84 enable */ + uint32_t NCFE83:1; /* NCF 83 enable */ + uint32_t NCFE82:1; /* NCF 82 enable */ + uint32_t NCFE81:1; /* NCF 81 enable */ + uint32_t NCFE80:1; /* NCF 80 enable */ + uint32_t NCFE79:1; /* NCF 79 enable */ + uint32_t NCFE78:1; /* NCF 78 enable */ + uint32_t NCFE77:1; /* NCF 77 enable */ + uint32_t NCFE76:1; /* NCF 76 enable */ + uint32_t NCFE75:1; /* NCF 75 enable */ + uint32_t NCFE74:1; /* NCF 74 enable */ + uint32_t NCFE73:1; /* NCF 73 enable */ + uint32_t NCFE72:1; /* NCF 72 enable */ + uint32_t NCFE71:1; /* NCF 71 enable */ + uint32_t NCFE70:1; /* NCF 70 enable */ + uint32_t NCFE69:1; /* NCF 69 enable */ + uint32_t NCFE68:1; /* NCF 68 enable */ + uint32_t NCFE67:1; /* NCF 67 enable */ + uint32_t NCFE66:1; /* NCF 66 enable */ + uint32_t NCFE65:1; /* NCF 65 enable */ + uint32_t NCFE64:1; /* NCF 64 enable */ + } B; + } FCCU_NCFE2_32B_tag; + + typedef union { /* FCCU NCF Enable Register 3 */ + uint32_t R; + struct { + uint32_t NCFE127:1; /* NCF 127 enable */ + uint32_t NCFE126:1; /* NCF 126 enable */ + uint32_t NCFE125:1; /* NCF 125 enable */ + uint32_t NCFE124:1; /* NCF 124 enable */ + uint32_t NCFE123:1; /* NCF 123 enable */ + uint32_t NCFE122:1; /* NCF 122 enable */ + uint32_t NCFE121:1; /* NCF 121 enable */ + uint32_t NCFE120:1; /* NCF 120 enable */ + uint32_t NCFE119:1; /* NCF 119 enable */ + uint32_t NCFE118:1; /* NCF 118 enable */ + uint32_t NCFE117:1; /* NCF 117 enable */ + uint32_t NCFE116:1; /* NCF 116 enable */ + uint32_t NCFE115:1; /* NCF 115 enable */ + uint32_t NCFE114:1; /* NCF 114 enable */ + uint32_t NCFE113:1; /* NCF 113 enable */ + uint32_t NCFE112:1; /* NCF 112 enable */ + uint32_t NCFE111:1; /* NCF 111 enable */ + uint32_t NCFE110:1; /* NCF 110 enable */ + uint32_t NCFE109:1; /* NCF 109 enable */ + uint32_t NCFE108:1; /* NCF 108 enable */ + uint32_t NCFE107:1; /* NCF 107 enable */ + uint32_t NCFE106:1; /* NCF 106 enable */ + uint32_t NCFE105:1; /* NCF 105 enable */ + uint32_t NCFE104:1; /* NCF 104 enable */ + uint32_t NCFE103:1; /* NCF 103 enable */ + uint32_t NCFE102:1; /* NCF 102 enable */ + uint32_t NCFE101:1; /* NCF 101 enable */ + uint32_t NCFE100:1; /* NCF 100 enable */ + uint32_t NCFE99:1; /* NCF 99 enable */ + uint32_t NCFE98:1; /* NCF 98 enable */ + uint32_t NCFE97:1; /* NCF 97 enable */ + uint32_t NCFE96:1; /* NCF 96 enable */ + } B; + } FCCU_NCFE3_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 0 */ + uint32_t R; + struct { + uint32_t NCFTOE31:1; /* NCF 31 time-out enable */ + uint32_t NCFTOE30:1; /* NCF 30 time-out enable */ + uint32_t NCFTOE29:1; /* NCF 29 time-out enable */ + uint32_t NCFTOE28:1; /* NCF 28 time-out enable */ + uint32_t NCFTOE27:1; /* NCF 27 time-out enable */ + uint32_t NCFTOE26:1; /* NCF 26 time-out enable */ + uint32_t NCFTOE25:1; /* NCF 25 time-out enable */ + uint32_t NCFTOE24:1; /* NCF 24 time-out enable */ + uint32_t NCFTOE23:1; /* NCF 23 time-out enable */ + uint32_t NCFTOE22:1; /* NCF 22 time-out enable */ + uint32_t NCFTOE21:1; /* NCF 21 time-out enable */ + uint32_t NCFTOE20:1; /* NCF 20 time-out enable */ + uint32_t NCFTOE19:1; /* NCF 19 time-out enable */ + uint32_t NCFTOE18:1; /* NCF 18 time-out enable */ + uint32_t NCFTOE17:1; /* NCF 17 time-out enable */ + uint32_t NCFTOE16:1; /* NCF 16 time-out enable */ + uint32_t NCFTOE15:1; /* NCF 15 time-out enable */ + uint32_t NCFTOE14:1; /* NCF 14 time-out enable */ + uint32_t NCFTOE13:1; /* NCF 13 time-out enable */ + uint32_t NCFTOE12:1; /* NCF 12 time-out enable */ + uint32_t NCFTOE11:1; /* NCF 11 time-out enable */ + uint32_t NCFTOE10:1; /* NCF 10 time-out enable */ + uint32_t NCFTOE9:1; /* NCF 9 time-out enable */ + uint32_t NCFTOE8:1; /* NCF 8 time-out enable */ + uint32_t NCFTOE7:1; /* NCF 7 time-out enable */ + uint32_t NCFTOE6:1; /* NCF 6 time-out enable */ + uint32_t NCFTOE5:1; /* NCF 5 time-out enable */ + uint32_t NCFTOE4:1; /* NCF 4 time-out enable */ + uint32_t NCFTOE3:1; /* NCF 3 time-out enable */ + uint32_t NCFTOE2:1; /* NCF 2 time-out enable */ + uint32_t NCFTOE1:1; /* NCF 1 time-out enable */ + uint32_t NCFTOE0:1; /* NCF 0 time-out enable */ + } B; + } FCCU_NCF_TOE0_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 1 */ + uint32_t R; + struct { + uint32_t NCFTOE63:1; /* NCF 63 time-out enable */ + uint32_t NCFTOE62:1; /* NCF 62 time-out enable */ + uint32_t NCFTOE61:1; /* NCF 61 time-out enable */ + uint32_t NCFTOE60:1; /* NCF 60 time-out enable */ + uint32_t NCFTOE59:1; /* NCF 59 time-out enable */ + uint32_t NCFTOE58:1; /* NCF 58 time-out enable */ + uint32_t NCFTOE57:1; /* NCF 57 time-out enable */ + uint32_t NCFTOE56:1; /* NCF 56 time-out enable */ + uint32_t NCFTOE55:1; /* NCF 55 time-out enable */ + uint32_t NCFTOE54:1; /* NCF 54 time-out enable */ + uint32_t NCFTOE53:1; /* NCF 53 time-out enable */ + uint32_t NCFTOE52:1; /* NCF 52 time-out enable */ + uint32_t NCFTOE51:1; /* NCF 51 time-out enable */ + uint32_t NCFTOE50:1; /* NCF 50 time-out enable */ + uint32_t NCFTOE49:1; /* NCF 49 time-out enable */ + uint32_t NCFTOE48:1; /* NCF 48 time-out enable */ + uint32_t NCFTOE47:1; /* NCF 47 time-out enable */ + uint32_t NCFTOE46:1; /* NCF 46 time-out enable */ + uint32_t NCFTOE45:1; /* NCF 45 time-out enable */ + uint32_t NCFTOE44:1; /* NCF 44 time-out enable */ + uint32_t NCFTOE43:1; /* NCF 43 time-out enable */ + uint32_t NCFTOE42:1; /* NCF 42 time-out enable */ + uint32_t NCFTOE41:1; /* NCF 41 time-out enable */ + uint32_t NCFTOE40:1; /* NCF 40 time-out enable */ + uint32_t NCFTOE39:1; /* NCF 39 time-out enable */ + uint32_t NCFTOE38:1; /* NCF 38 time-out enable */ + uint32_t NCFTOE37:1; /* NCF 37 time-out enable */ + uint32_t NCFTOE36:1; /* NCF 36 time-out enable */ + uint32_t NCFTOE35:1; /* NCF 35 time-out enable */ + uint32_t NCFTOE34:1; /* NCF 34 time-out enable */ + uint32_t NCFTOE33:1; /* NCF 33 time-out enable */ + uint32_t NCFTOE32:1; /* NCF 32 time-out enable */ + } B; + } FCCU_NCF_TOE1_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 2 */ + uint32_t R; + struct { + uint32_t NCFTOE95:1; /* NCF 95 time-out enable */ + uint32_t NCFTOE94:1; /* NCF 94 time-out enable */ + uint32_t NCFTOE93:1; /* NCF 93 time-out enable */ + uint32_t NCFTOE92:1; /* NCF 92 time-out enable */ + uint32_t NCFTOE91:1; /* NCF 91 time-out enable */ + uint32_t NCFTOE90:1; /* NCF 90 time-out enable */ + uint32_t NCFTOE89:1; /* NCF 89 time-out enable */ + uint32_t NCFTOE88:1; /* NCF 88 time-out enable */ + uint32_t NCFTOE87:1; /* NCF 87 time-out enable */ + uint32_t NCFTOE86:1; /* NCF 86 time-out enable */ + uint32_t NCFTOE85:1; /* NCF 85 time-out enable */ + uint32_t NCFTOE84:1; /* NCF 84 time-out enable */ + uint32_t NCFTOE83:1; /* NCF 83 time-out enable */ + uint32_t NCFTOE82:1; /* NCF 82 time-out enable */ + uint32_t NCFTOE81:1; /* NCF 81 time-out enable */ + uint32_t NCFTOE80:1; /* NCF 80 time-out enable */ + uint32_t NCFTOE79:1; /* NCF 79 time-out enable */ + uint32_t NCFTOE78:1; /* NCF 78 time-out enable */ + uint32_t NCFTOE77:1; /* NCF 77 time-out enable */ + uint32_t NCFTOE76:1; /* NCF 76 time-out enable */ + uint32_t NCFTOE75:1; /* NCF 75 time-out enable */ + uint32_t NCFTOE74:1; /* NCF 74 time-out enable */ + uint32_t NCFTOE73:1; /* NCF 73 time-out enable */ + uint32_t NCFTOE72:1; /* NCF 72 time-out enable */ + uint32_t NCFTOE71:1; /* NCF 71 time-out enable */ + uint32_t NCFTOE70:1; /* NCF 70 time-out enable */ + uint32_t NCFTOE69:1; /* NCF 69 time-out enable */ + uint32_t NCFTOE68:1; /* NCF 68 time-out enable */ + uint32_t NCFTOE67:1; /* NCF 67 time-out enable */ + uint32_t NCFTOE66:1; /* NCF 66 time-out enable */ + uint32_t NCFTOE65:1; /* NCF 65 time-out enable */ + uint32_t NCFTOE64:1; /* NCF 64 time-out enable */ + } B; + } FCCU_NCF_TOE2_32B_tag; + + typedef union { /* FCCU NCF Time-out Enable Register 3 */ + uint32_t R; + struct { + uint32_t NCFTOE127:1; /* NCF 127 time-out enable */ + uint32_t NCFTOE126:1; /* NCF 126 time-out enable */ + uint32_t NCFTOE125:1; /* NCF 125 time-out enable */ + uint32_t NCFTOE124:1; /* NCF 124 time-out enable */ + uint32_t NCFTOE123:1; /* NCF 123 time-out enable */ + uint32_t NCFTOE122:1; /* NCF 122 time-out enable */ + uint32_t NCFTOE121:1; /* NCF 121 time-out enable */ + uint32_t NCFTOE120:1; /* NCF 120 time-out enable */ + uint32_t NCFTOE119:1; /* NCF 119 time-out enable */ + uint32_t NCFTOE118:1; /* NCF 118 time-out enable */ + uint32_t NCFTOE117:1; /* NCF 117 time-out enable */ + uint32_t NCFTOE116:1; /* NCF 116 time-out enable */ + uint32_t NCFTOE115:1; /* NCF 115 time-out enable */ + uint32_t NCFTOE114:1; /* NCF 114 time-out enable */ + uint32_t NCFTOE113:1; /* NCF 113 time-out enable */ + uint32_t NCFTOE112:1; /* NCF 112 time-out enable */ + uint32_t NCFTOE111:1; /* NCF 111 time-out enable */ + uint32_t NCFTOE110:1; /* NCF 110 time-out enable */ + uint32_t NCFTOE109:1; /* NCF 109 time-out enable */ + uint32_t NCFTOE108:1; /* NCF 108 time-out enable */ + uint32_t NCFTOE107:1; /* NCF 107 time-out enable */ + uint32_t NCFTOE106:1; /* NCF 106 time-out enable */ + uint32_t NCFTOE105:1; /* NCF 105 time-out enable */ + uint32_t NCFTOE104:1; /* NCF 104 time-out enable */ + uint32_t NCFTOE103:1; /* NCF 103 time-out enable */ + uint32_t NCFTOE102:1; /* NCF 102 time-out enable */ + uint32_t NCFTOE101:1; /* NCF 101 time-out enable */ + uint32_t NCFTOE100:1; /* NCF 100 time-out enable */ + uint32_t NCFTOE99:1; /* NCF 99 time-out enable */ + uint32_t NCFTOE98:1; /* NCF 98 time-out enable */ + uint32_t NCFTOE97:1; /* NCF 97 time-out enable */ + uint32_t NCFTOE96:1; /* NCF 96 time-out enable */ + } B; + } FCCU_NCF_TOE3_32B_tag; + + typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */ + uint32_t R; + } FCCU_NCF_TO_32B_tag; + + typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t TO:3; /* Configuration time-out */ + } B; + } FCCU_CFG_TO_32B_tag; + + typedef union { /* FCCU_EINOUT - FCCU IO Control Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t EIN1:1; /* Error input 1 */ + uint32_t EIN0:1; /* Error input 0 */ + uint32_t:2; + uint32_t EOUT1:1; /* Error out 1 */ + uint32_t EOUT0:1; /* Error out 0 */ + } B; + } FCCU_EINOUT_32B_tag; + + typedef union { /* FCCU_STAT - FCCU Status Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t STATUS:3; /* FCCU status */ + } B; + } FCCU_STAT_32B_tag; + + typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */ + } B; + } FCCU_NAFS_32B_tag; + + typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t AFFS_SRC:2; /* Fault source */ + uint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */ + } B; + } FCCU_AFFS_32B_tag; + + typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t NFFS_SRC:2; /* Fault source */ + uint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */ + } B; + } FCCU_NFFS_32B_tag; + + typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */ + } B; + } FCCU_FAFS_32B_tag; + + typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t RCCS1:1; /* RCC1 Status */ + uint32_t RCCS0:1; /* RCC0 Status */ + } B; + } FCCU_SCFS_32B_tag; + + typedef union { /* FCCU_CFF - FCCU CF Fake Register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t FCFC:7; /* Fake critical fault code */ + } B; + } FCCU_CFF_32B_tag; + + typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */ + uint32_t R; + struct { + uint32_t:25; + uint32_t FNCFC:7; /* Fake non-critical fault code */ + } B; + } FCCU_NCFF_32B_tag; + + typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t NMI_STAT:1; /* NMI Interrupt Status */ + uint32_t ALRM_STAT:1; /* Alarm Interrupt Status */ + uint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */ + } B; + } FCCU_IRQ_STAT_32B_tag; + + typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */ + } B; + } FCCU_IRQ_EN_32B_tag; + + typedef union { /* FCCU_XTMR - FCCU XTMR Register */ + uint32_t R; + struct { + uint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */ + } B; + } FCCU_XTMR_32B_tag; + + typedef union { /* FCCU_MCS - FCCU MCS Register */ + uint32_t R; + struct { + uint32_t VL3:1; /* Valid */ + uint32_t FS3:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS3:4; /* Magic Carpet oldest state */ + uint32_t VL2:1; /* Valid */ + uint32_t FS2:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS2:4; /* Magic Carpet previous-previous state */ + uint32_t VL1:1; /* Valid */ + uint32_t FS1:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS1:4; /* Magic Carpet previous state */ + uint32_t VL0:1; /* Valid */ + uint32_t FS0:1; /* Fault Status */ + uint32_t:2; + uint32_t MCS0:4; /* Magic Carpet latest state */ + } B; + } FCCU_MCS_32B_tag; + + + /* Register layout for generated register(s) CF_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_CF_CFG_32B_tag; + + + /* Register layout for generated register(s) NCF_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCF_CFG_32B_tag; + + + /* Register layout for generated register(s) CFS_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_CFS_CFG_32B_tag; + + + /* Register layout for generated register(s) NCFS_CFG... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCFS_CFG_32B_tag; + + + /* Register layout for generated register(s) CFS... */ + + typedef union { /* */ + uint32_t R; + } FCCU_CFS_32B_tag; + + + /* Register layout for generated register(s) NCFS... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCFS_32B_tag; + + + /* Register layout for generated register(s) NCFE... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCFE_32B_tag; + + + /* Register layout for generated register(s) NCF_TOE... */ + + typedef union { /* */ + uint32_t R; + } FCCU_NCF_TOE_32B_tag; + + + + typedef struct FCCU_struct_tag { /* start of FCCU_tag */ + /* FCCU Control Register */ + FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ + /* FCCU CTRL Key Register */ + FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */ + /* FCCU Configuration Register */ + FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */ + union { + FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */ + + struct { + /* FCCU CF Configuration Register 0 */ + FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */ + /* FCCU CF Configuration Register 1 */ + FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */ + /* FCCU CF Configuration Register 2 */ + FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */ + /* FCCU CF Configuration Register 3 */ + FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */ + }; + + }; + union { + FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */ + + struct { + /* FCCU NCF Configuration Register 0 */ + FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */ + /* FCCU NCF Configuration Register 1 */ + FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */ + /* FCCU NCF Configuration Register 2 */ + FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */ + /* FCCU NCF Configuration Register 3 */ + FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */ + }; + + }; + union { + FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */ + + struct { + /* FCCU CFS Configuration Register 0 */ + FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */ + /* FCCU CFS Configuration Register 1 */ + FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */ + /* FCCU CFS Configuration Register 2 */ + FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */ + /* FCCU CFS Configuration Register 3 */ + FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */ + /* FCCU CFS Configuration Register 4 */ + FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */ + /* FCCU CFS Configuration Register 5 */ + FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */ + /* FCCU CFS Configuration Register 6 */ + FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */ + /* FCCU CFS Configuration Register 7 */ + FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */ + }; + + }; + union { + FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */ + + struct { + /* FCCU NCFS Configuration Register 0 */ + FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */ + /* FCCU NCFS Configuration Register 1 */ + FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */ + /* FCCU NCFS Configuration Register 2 */ + FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */ + /* FCCU NCFS Configuration Register 3 */ + FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */ + /* FCCU NCFS Configuration Register 4 */ + FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */ + /* FCCU NCFS Configuration Register 5 */ + FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */ + /* FCCU NCFS Configuration Register 6 */ + FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */ + /* FCCU NCFS Configuration Register 7 */ + FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */ + }; + + }; + union { + FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */ + + struct { + /* FCCU CF Status Register 0 */ + FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */ + /* FCCU CF Status Register 1 */ + FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */ + /* FCCU CF Status Register 2 */ + FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */ + /* FCCU CF Status Register 3 */ + FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */ + }; + + }; + /* FCCU_CFK - FCCU CF Key Register */ + FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */ + union { + FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */ + + struct { + /* FCCU NCF Status Register 0 */ + FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */ + /* FCCU NCF Status Register 1 */ + FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */ + /* FCCU NCF Status Register 2 */ + FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */ + /* FCCU NCF Status Register 3 */ + FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */ + }; + + }; + /* FCCU_NCFK - FCCU NCF Key Register */ + FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */ + union { + FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */ + + struct { + /* FCCU NCF Enable Register 0 */ + FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */ + /* FCCU NCF Enable Register 1 */ + FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */ + /* FCCU NCF Enable Register 2 */ + FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */ + /* FCCU NCF Enable Register 3 */ + FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */ + }; + + }; + union { + FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */ + + struct { + /* FCCU NCF Time-out Enable Register 0 */ + FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */ + /* FCCU NCF Time-out Enable Register 1 */ + FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */ + /* FCCU NCF Time-out Enable Register 2 */ + FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */ + /* FCCU NCF Time-out Enable Register 3 */ + FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */ + }; + + }; + /* FCCU_NCF_TO - FCCU NCF Time-out Register */ + FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */ + /* FCCU_CFG_TO - FCCU CFG Timeout Register */ + FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */ + /* FCCU_EINOUT - FCCU IO Control Register */ + FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */ + /* FCCU_STAT - FCCU Status Register */ + FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */ + /* FCCU_NAFS - FCCU NA Freeze Status Register */ + FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */ + /* FCCU_AFFS - FCCU AF Freeze Status Register */ + FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */ + /* FCCU_NFFS - FCCU NF Freeze Status Register */ + FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */ + /* FCCU_FAFS - FCCU FA Freeze Status Register */ + FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */ + /* FCCU_SCFS - FCCU SC Freeze Status Register */ + FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */ + /* FCCU_CFF - FCCU CF Fake Register */ + FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */ + /* FCCU_NCFF - FCCU NCF Fake Register */ + FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */ + /* FCCU_IRQ_STAT - FCCU IRQ Status Register */ + FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */ + /* FCCU_IRQ_EN - FCCU IRQ Enable Register */ + FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */ + /* FCCU_XTMR - FCCU XTMR Register */ + FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */ + /* FCCU_MCS - FCCU MCS Register */ + FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */ + } FCCU_tag; + + +#define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL) + + + +/****************************************************************/ +/* */ +/* Module: SGENDIG */ +/* */ +/****************************************************************/ + + typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */ + uint32_t R; + struct { + uint32_t LDOS:1; /* Operation Status */ + uint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */ + uint32_t:2; + uint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */ + uint32_t:5; + uint32_t S0H1:1; /* Operation Status */ + uint32_t PDS:1; /* Operation Status */ + uint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */ + } B; + } SGENDIG_CTRL_32B_tag; + + typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t SERR:1; /* Sine wave generator Error bit */ + uint32_t:3; + uint32_t FERR:1; /* Sine wave generator Force Error bit */ + uint32_t:19; + } B; + } SGENDIG_IRQE_32B_tag; + + + + typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */ + /* SGENDIG_CTRL - SGENDIG Control Register */ + SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */ + /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */ + SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */ + } SGENDIG_tag; + + +#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL) + + + +/****************************************************************/ +/* */ +/* Module: PBRIDGE */ +/* */ +/****************************************************************/ + + typedef union { /* MPROT - Master Privilege Registers */ + uint32_t R; + struct { + uint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */ + uint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */ + uint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */ + uint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */ + uint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */ + uint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */ + uint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */ + uint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */ + uint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */ + uint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */ + uint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */ + uint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */ + uint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */ + uint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */ + uint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */ + uint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */ + uint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */ + uint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */ + uint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */ + uint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */ + uint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */ + uint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */ + uint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */ + uint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */ + uint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */ + uint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */ + uint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */ + uint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */ + uint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */ + uint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */ + uint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */ + uint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */ + } B; + } PBRIDGE_MPROT_32B_tag; + + typedef union { /* PACR0_7 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR0_BW:1; /* Buffer Writes */ + uint32_t PACR0_SP:1; /* Supervisor Protect */ + uint32_t PACR0_WP:1; /* Write Protect */ + uint32_t PACR0_TP:1; /* Trusted Protect */ + uint32_t PACR1_BW:1; /* Buffer Writes */ + uint32_t PACR1_SP:1; /* Supervisor Protect */ + uint32_t PACR1_WP:1; /* Write Protect */ + uint32_t PACR1_TP:1; /* Trusted Protect */ + uint32_t PACR2_BW:1; /* Buffer Writes */ + uint32_t PACR2_SP:1; /* Supervisor Protect */ + uint32_t PACR2_WP:1; /* Write Protect */ + uint32_t PACR2_TP:1; /* Trusted Protect */ + uint32_t PACR3_BW:1; /* Buffer Writes */ + uint32_t PACR3_SP:1; /* Supervisor Protect */ + uint32_t PACR3_WP:1; /* Write Protect */ + uint32_t PACR3_TP:1; /* Trusted Protect */ + uint32_t PACR4_BW:1; /* Buffer Writes */ + uint32_t PACR4_SP:1; /* Supervisor Protect */ + uint32_t PACR4_WP:1; /* Write Protect */ + uint32_t PACR4_TP:1; /* Trusted Protect */ + uint32_t PACR5_BW:1; /* Buffer Writes */ + uint32_t PACR5_SP:1; /* Supervisor Protect */ + uint32_t PACR5_WP:1; /* Write Protect */ + uint32_t PACR5_TP:1; /* Trusted Protect */ + uint32_t PACR6_BW:1; /* Buffer Writes */ + uint32_t PACR6_SP:1; /* Supervisor Protect */ + uint32_t PACR6_WP:1; /* Write Protect */ + uint32_t PACR6_TP:1; /* Trusted Protect */ + uint32_t PACR7_BW:1; /* Buffer Writes */ + uint32_t PACR7_SP:1; /* Supervisor Protect */ + uint32_t PACR7_WP:1; /* Write Protect */ + uint32_t PACR7_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR0_7_32B_tag; + + typedef union { /* PACR8_15 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR8_BW:1; /* Buffer Writes */ + uint32_t PACR8_SP:1; /* Supervisor Protect */ + uint32_t PACR8_WP:1; /* Write Protect */ + uint32_t PACR8_TP:1; /* Trusted Protect */ + uint32_t PACR9_BW:1; /* Buffer Writes */ + uint32_t PACR9_SP:1; /* Supervisor Protect */ + uint32_t PACR9_WP:1; /* Write Protect */ + uint32_t PACR9_TP:1; /* Trusted Protect */ + uint32_t PACR10_BW:1; /* Buffer Writes */ + uint32_t PACR10_SP:1; /* Supervisor Protect */ + uint32_t PACR10_WP:1; /* Write Protect */ + uint32_t PACR10_TP:1; /* Trusted Protect */ + uint32_t PACR11_BW:1; /* Buffer Writes */ + uint32_t PACR11_SP:1; /* Supervisor Protect */ + uint32_t PACR11_WP:1; /* Write Protect */ + uint32_t PACR11_TP:1; /* Trusted Protect */ + uint32_t PACR12_BW:1; /* Buffer Writes */ + uint32_t PACR12_SP:1; /* Supervisor Protect */ + uint32_t PACR12_WP:1; /* Write Protect */ + uint32_t PACR12_TP:1; /* Trusted Protect */ + uint32_t PACR13_BW:1; /* Buffer Writes */ + uint32_t PACR13_SP:1; /* Supervisor Protect */ + uint32_t PACR13_WP:1; /* Write Protect */ + uint32_t PACR13_TP:1; /* Trusted Protect */ + uint32_t PACR14_BW:1; /* Buffer Writes */ + uint32_t PACR14_SP:1; /* Supervisor Protect */ + uint32_t PACR14_WP:1; /* Write Protect */ + uint32_t PACR14_TP:1; /* Trusted Protect */ + uint32_t PACR15_BW:1; /* Buffer Writes */ + uint32_t PACR15_SP:1; /* Supervisor Protect */ + uint32_t PACR15_WP:1; /* Write Protect */ + uint32_t PACR15_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR8_15_32B_tag; + + typedef union { /* PACR16_23 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR16_BW:1; /* Buffer Writes */ + uint32_t PACR16_SP:1; /* Supervisor Protect */ + uint32_t PACR16_WP:1; /* Write Protect */ + uint32_t PACR16_TP:1; /* Trusted Protect */ + uint32_t PACR17_BW:1; /* Buffer Writes */ + uint32_t PACR17_SP:1; /* Supervisor Protect */ + uint32_t PACR17_WP:1; /* Write Protect */ + uint32_t PACR17_TP:1; /* Trusted Protect */ + uint32_t PACR18_BW:1; /* Buffer Writes */ + uint32_t PACR18_SP:1; /* Supervisor Protect */ + uint32_t PACR18_WP:1; /* Write Protect */ + uint32_t PACR18_TP:1; /* Trusted Protect */ + uint32_t PACR19_BW:1; /* Buffer Writes */ + uint32_t PACR19_SP:1; /* Supervisor Protect */ + uint32_t PACR19_WP:1; /* Write Protect */ + uint32_t PACR19_TP:1; /* Trusted Protect */ + uint32_t PACR20_BW:1; /* Buffer Writes */ + uint32_t PACR20_SP:1; /* Supervisor Protect */ + uint32_t PACR20_WP:1; /* Write Protect */ + uint32_t PACR20_TP:1; /* Trusted Protect */ + uint32_t PACR21_BW:1; /* Buffer Writes */ + uint32_t PACR21_SP:1; /* Supervisor Protect */ + uint32_t PACR21_WP:1; /* Write Protect */ + uint32_t PACR21_TP:1; /* Trusted Protect */ + uint32_t PACR22_BW:1; /* Buffer Writes */ + uint32_t PACR22_SP:1; /* Supervisor Protect */ + uint32_t PACR22_WP:1; /* Write Protect */ + uint32_t PACR22_TP:1; /* Trusted Protect */ + uint32_t PACR23_BW:1; /* Buffer Writes */ + uint32_t PACR23_SP:1; /* Supervisor Protect */ + uint32_t PACR23_WP:1; /* Write Protect */ + uint32_t PACR23_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR16_23_32B_tag; + + typedef union { /* PACR24_31 - Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t PACR24_BW:1; /* Buffer Writes */ + uint32_t PACR24_SP:1; /* Supervisor Protect */ + uint32_t PACR24_WP:1; /* Write Protect */ + uint32_t PACR24_TP:1; /* Trusted Protect */ + uint32_t PACR25_BW:1; /* Buffer Writes */ + uint32_t PACR25_SP:1; /* Supervisor Protect */ + uint32_t PACR25_WP:1; /* Write Protect */ + uint32_t PACR25_TP:1; /* Trusted Protect */ + uint32_t PACR26_BW:1; /* Buffer Writes */ + uint32_t PACR26_SP:1; /* Supervisor Protect */ + uint32_t PACR26_WP:1; /* Write Protect */ + uint32_t PACR26_TP:1; /* Trusted Protect */ + uint32_t PACR27_BW:1; /* Buffer Writes */ + uint32_t PACR27_SP:1; /* Supervisor Protect */ + uint32_t PACR27_WP:1; /* Write Protect */ + uint32_t PACR27_TP:1; /* Trusted Protect */ + uint32_t PACR28_BW:1; /* Buffer Writes */ + uint32_t PACR28_SP:1; /* Supervisor Protect */ + uint32_t PACR28_WP:1; /* Write Protect */ + uint32_t PACR28_TP:1; /* Trusted Protect */ + uint32_t PACR29_BW:1; /* Buffer Writes */ + uint32_t PACR29_SP:1; /* Supervisor Protect */ + uint32_t PACR29_WP:1; /* Write Protect */ + uint32_t PACR29_TP:1; /* Trusted Protect */ + uint32_t PACR30_BW:1; /* Buffer Writes */ + uint32_t PACR30_SP:1; /* Supervisor Protect */ + uint32_t PACR30_WP:1; /* Write Protect */ + uint32_t PACR30_TP:1; /* Trusted Protect */ + uint32_t PACR31_BW:1; /* Buffer Writes */ + uint32_t PACR31_SP:1; /* Supervisor Protect */ + uint32_t PACR31_WP:1; /* Write Protect */ + uint32_t PACR31_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_PACR24_31_32B_tag; + + typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR0_BW:1; /* Buffer Writes */ + uint32_t OPACR0_SP:1; /* Supervisor Protect */ + uint32_t OPACR0_WP:1; /* Write Protect */ + uint32_t OPACR0_TP:1; /* Trusted Protect */ + uint32_t OPACR1_BW:1; /* Buffer Writes */ + uint32_t OPACR1_SP:1; /* Supervisor Protect */ + uint32_t OPACR1_WP:1; /* Write Protect */ + uint32_t OPACR1_TP:1; /* Trusted Protect */ + uint32_t OPACR2_BW:1; /* Buffer Writes */ + uint32_t OPACR2_SP:1; /* Supervisor Protect */ + uint32_t OPACR2_WP:1; /* Write Protect */ + uint32_t OPACR2_TP:1; /* Trusted Protect */ + uint32_t OPACR3_BW:1; /* Buffer Writes */ + uint32_t OPACR3_SP:1; /* Supervisor Protect */ + uint32_t OPACR3_WP:1; /* Write Protect */ + uint32_t OPACR3_TP:1; /* Trusted Protect */ + uint32_t OPACR4_BW:1; /* Buffer Writes */ + uint32_t OPACR4_SP:1; /* Supervisor Protect */ + uint32_t OPACR4_WP:1; /* Write Protect */ + uint32_t OPACR4_TP:1; /* Trusted Protect */ + uint32_t OPACR5_BW:1; /* Buffer Writes */ + uint32_t OPACR5_SP:1; /* Supervisor Protect */ + uint32_t OPACR5_WP:1; /* Write Protect */ + uint32_t OPACR5_TP:1; /* Trusted Protect */ + uint32_t OPACR6_BW:1; /* Buffer Writes */ + uint32_t OPACR6_SP:1; /* Supervisor Protect */ + uint32_t OPACR6_WP:1; /* Write Protect */ + uint32_t OPACR6_TP:1; /* Trusted Protect */ + uint32_t OPACR7_BW:1; /* Buffer Writes */ + uint32_t OPACR7_SP:1; /* Supervisor Protect */ + uint32_t OPACR7_WP:1; /* Write Protect */ + uint32_t OPACR7_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR0_7_32B_tag; + + typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR8_BW:1; /* Buffer Writes */ + uint32_t OPACR8_SP:1; /* Supervisor Protect */ + uint32_t OPACR8_WP:1; /* Write Protect */ + uint32_t OPACR8_TP:1; /* Trusted Protect */ + uint32_t OPACR9_BW:1; /* Buffer Writes */ + uint32_t OPACR9_SP:1; /* Supervisor Protect */ + uint32_t OPACR9_WP:1; /* Write Protect */ + uint32_t OPACR9_TP:1; /* Trusted Protect */ + uint32_t OPACR10_BW:1; /* Buffer Writes */ + uint32_t OPACR10_SP:1; /* Supervisor Protect */ + uint32_t OPACR10_WP:1; /* Write Protect */ + uint32_t OPACR10_TP:1; /* Trusted Protect */ + uint32_t OPACR11_BW:1; /* Buffer Writes */ + uint32_t OPACR11_SP:1; /* Supervisor Protect */ + uint32_t OPACR11_WP:1; /* Write Protect */ + uint32_t OPACR11_TP:1; /* Trusted Protect */ + uint32_t OPACR12_BW:1; /* Buffer Writes */ + uint32_t OPACR12_SP:1; /* Supervisor Protect */ + uint32_t OPACR12_WP:1; /* Write Protect */ + uint32_t OPACR12_TP:1; /* Trusted Protect */ + uint32_t OPACR13_BW:1; /* Buffer Writes */ + uint32_t OPACR13_SP:1; /* Supervisor Protect */ + uint32_t OPACR13_WP:1; /* Write Protect */ + uint32_t OPACR13_TP:1; /* Trusted Protect */ + uint32_t OPACR14_BW:1; /* Buffer Writes */ + uint32_t OPACR14_SP:1; /* Supervisor Protect */ + uint32_t OPACR14_WP:1; /* Write Protect */ + uint32_t OPACR14_TP:1; /* Trusted Protect */ + uint32_t OPACR15_BW:1; /* Buffer Writes */ + uint32_t OPACR15_SP:1; /* Supervisor Protect */ + uint32_t OPACR15_WP:1; /* Write Protect */ + uint32_t OPACR15_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR8_15_32B_tag; + + typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR16_BW:1; /* Buffer Writes */ + uint32_t OPACR16_SP:1; /* Supervisor Protect */ + uint32_t OPACR16_WP:1; /* Write Protect */ + uint32_t OPACR16_TP:1; /* Trusted Protect */ + uint32_t OPACR17_BW:1; /* Buffer Writes */ + uint32_t OPACR17_SP:1; /* Supervisor Protect */ + uint32_t OPACR17_WP:1; /* Write Protect */ + uint32_t OPACR17_TP:1; /* Trusted Protect */ + uint32_t OPACR18_BW:1; /* Buffer Writes */ + uint32_t OPACR18_SP:1; /* Supervisor Protect */ + uint32_t OPACR18_WP:1; /* Write Protect */ + uint32_t OPACR18_TP:1; /* Trusted Protect */ + uint32_t OPACR19_BW:1; /* Buffer Writes */ + uint32_t OPACR19_SP:1; /* Supervisor Protect */ + uint32_t OPACR19_WP:1; /* Write Protect */ + uint32_t OPACR19_TP:1; /* Trusted Protect */ + uint32_t OPACR20_BW:1; /* Buffer Writes */ + uint32_t OPACR20_SP:1; /* Supervisor Protect */ + uint32_t OPACR20_WP:1; /* Write Protect */ + uint32_t OPACR20_TP:1; /* Trusted Protect */ + uint32_t OPACR21_BW:1; /* Buffer Writes */ + uint32_t OPACR21_SP:1; /* Supervisor Protect */ + uint32_t OPACR21_WP:1; /* Write Protect */ + uint32_t OPACR21_TP:1; /* Trusted Protect */ + uint32_t OPACR22_BW:1; /* Buffer Writes */ + uint32_t OPACR22_SP:1; /* Supervisor Protect */ + uint32_t OPACR22_WP:1; /* Write Protect */ + uint32_t OPACR22_TP:1; /* Trusted Protect */ + uint32_t OPACR23_BW:1; /* Buffer Writes */ + uint32_t OPACR23_SP:1; /* Supervisor Protect */ + uint32_t OPACR23_WP:1; /* Write Protect */ + uint32_t OPACR23_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR16_23_32B_tag; + + typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR24_BW:1; /* Buffer Writes */ + uint32_t OPACR24_SP:1; /* Supervisor Protect */ + uint32_t OPACR24_WP:1; /* Write Protect */ + uint32_t OPACR24_TP:1; /* Trusted Protect */ + uint32_t OPACR25_BW:1; /* Buffer Writes */ + uint32_t OPACR25_SP:1; /* Supervisor Protect */ + uint32_t OPACR25_WP:1; /* Write Protect */ + uint32_t OPACR25_TP:1; /* Trusted Protect */ + uint32_t OPACR26_BW:1; /* Buffer Writes */ + uint32_t OPACR26_SP:1; /* Supervisor Protect */ + uint32_t OPACR26_WP:1; /* Write Protect */ + uint32_t OPACR26_TP:1; /* Trusted Protect */ + uint32_t OPACR27_BW:1; /* Buffer Writes */ + uint32_t OPACR27_SP:1; /* Supervisor Protect */ + uint32_t OPACR27_WP:1; /* Write Protect */ + uint32_t OPACR27_TP:1; /* Trusted Protect */ + uint32_t OPACR28_BW:1; /* Buffer Writes */ + uint32_t OPACR28_SP:1; /* Supervisor Protect */ + uint32_t OPACR28_WP:1; /* Write Protect */ + uint32_t OPACR28_TP:1; /* Trusted Protect */ + uint32_t OPACR29_BW:1; /* Buffer Writes */ + uint32_t OPACR29_SP:1; /* Supervisor Protect */ + uint32_t OPACR29_WP:1; /* Write Protect */ + uint32_t OPACR29_TP:1; /* Trusted Protect */ + uint32_t OPACR30_BW:1; /* Buffer Writes */ + uint32_t OPACR30_SP:1; /* Supervisor Protect */ + uint32_t OPACR30_WP:1; /* Write Protect */ + uint32_t OPACR30_TP:1; /* Trusted Protect */ + uint32_t OPACR31_BW:1; /* Buffer Writes */ + uint32_t OPACR31_SP:1; /* Supervisor Protect */ + uint32_t OPACR31_WP:1; /* Write Protect */ + uint32_t OPACR31_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR24_31_32B_tag; + + typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR32_BW:1; /* Buffer Writes */ + uint32_t OPACR32_SP:1; /* Supervisor Protect */ + uint32_t OPACR32_WP:1; /* Write Protect */ + uint32_t OPACR32_TP:1; /* Trusted Protect */ + uint32_t OPACR33_BW:1; /* Buffer Writes */ + uint32_t OPACR33_SP:1; /* Supervisor Protect */ + uint32_t OPACR33_WP:1; /* Write Protect */ + uint32_t OPACR33_TP:1; /* Trusted Protect */ + uint32_t OPACR34_BW:1; /* Buffer Writes */ + uint32_t OPACR34_SP:1; /* Supervisor Protect */ + uint32_t OPACR34_WP:1; /* Write Protect */ + uint32_t OPACR34_TP:1; /* Trusted Protect */ + uint32_t OPACR35_BW:1; /* Buffer Writes */ + uint32_t OPACR35_SP:1; /* Supervisor Protect */ + uint32_t OPACR35_WP:1; /* Write Protect */ + uint32_t OPACR35_TP:1; /* Trusted Protect */ + uint32_t OPACR36_BW:1; /* Buffer Writes */ + uint32_t OPACR36_SP:1; /* Supervisor Protect */ + uint32_t OPACR36_WP:1; /* Write Protect */ + uint32_t OPACR36_TP:1; /* Trusted Protect */ + uint32_t OPACR37_BW:1; /* Buffer Writes */ + uint32_t OPACR37_SP:1; /* Supervisor Protect */ + uint32_t OPACR37_WP:1; /* Write Protect */ + uint32_t OPACR37_TP:1; /* Trusted Protect */ + uint32_t OPACR38_BW:1; /* Buffer Writes */ + uint32_t OPACR38_SP:1; /* Supervisor Protect */ + uint32_t OPACR38_WP:1; /* Write Protect */ + uint32_t OPACR38_TP:1; /* Trusted Protect */ + uint32_t OPACR39_BW:1; /* Buffer Writes */ + uint32_t OPACR39_SP:1; /* Supervisor Protect */ + uint32_t OPACR39_WP:1; /* Write Protect */ + uint32_t OPACR39_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR32_39_32B_tag; + + typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR40_BW:1; /* Buffer Writes */ + uint32_t OPACR40_SP:1; /* Supervisor Protect */ + uint32_t OPACR40_WP:1; /* Write Protect */ + uint32_t OPACR40_TP:1; /* Trusted Protect */ + uint32_t OPACR41_BW:1; /* Buffer Writes */ + uint32_t OPACR41_SP:1; /* Supervisor Protect */ + uint32_t OPACR41_WP:1; /* Write Protect */ + uint32_t OPACR41_TP:1; /* Trusted Protect */ + uint32_t OPACR42_BW:1; /* Buffer Writes */ + uint32_t OPACR42_SP:1; /* Supervisor Protect */ + uint32_t OPACR42_WP:1; /* Write Protect */ + uint32_t OPACR42_TP:1; /* Trusted Protect */ + uint32_t OPACR43_BW:1; /* Buffer Writes */ + uint32_t OPACR43_SP:1; /* Supervisor Protect */ + uint32_t OPACR43_WP:1; /* Write Protect */ + uint32_t OPACR43_TP:1; /* Trusted Protect */ + uint32_t OPACR44_BW:1; /* Buffer Writes */ + uint32_t OPACR44_SP:1; /* Supervisor Protect */ + uint32_t OPACR44_WP:1; /* Write Protect */ + uint32_t OPACR44_TP:1; /* Trusted Protect */ + uint32_t OPACR45_BW:1; /* Buffer Writes */ + uint32_t OPACR45_SP:1; /* Supervisor Protect */ + uint32_t OPACR45_WP:1; /* Write Protect */ + uint32_t OPACR45_TP:1; /* Trusted Protect */ + uint32_t OPACR46_BW:1; /* Buffer Writes */ + uint32_t OPACR46_SP:1; /* Supervisor Protect */ + uint32_t OPACR46_WP:1; /* Write Protect */ + uint32_t OPACR46_TP:1; /* Trusted Protect */ + uint32_t OPACR47_BW:1; /* Buffer Writes */ + uint32_t OPACR47_SP:1; /* Supervisor Protect */ + uint32_t OPACR47_WP:1; /* Write Protect */ + uint32_t OPACR47_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR40_47_32B_tag; + + typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR48_BW:1; /* Buffer Writes */ + uint32_t OPACR48_SP:1; /* Supervisor Protect */ + uint32_t OPACR48_WP:1; /* Write Protect */ + uint32_t OPACR48_TP:1; /* Trusted Protect */ + uint32_t OPACR49_BW:1; /* Buffer Writes */ + uint32_t OPACR49_SP:1; /* Supervisor Protect */ + uint32_t OPACR49_WP:1; /* Write Protect */ + uint32_t OPACR49_TP:1; /* Trusted Protect */ + uint32_t OPACR50_BW:1; /* Buffer Writes */ + uint32_t OPACR50_SP:1; /* Supervisor Protect */ + uint32_t OPACR50_WP:1; /* Write Protect */ + uint32_t OPACR50_TP:1; /* Trusted Protect */ + uint32_t OPACR51_BW:1; /* Buffer Writes */ + uint32_t OPACR51_SP:1; /* Supervisor Protect */ + uint32_t OPACR51_WP:1; /* Write Protect */ + uint32_t OPACR51_TP:1; /* Trusted Protect */ + uint32_t OPACR52_BW:1; /* Buffer Writes */ + uint32_t OPACR52_SP:1; /* Supervisor Protect */ + uint32_t OPACR52_WP:1; /* Write Protect */ + uint32_t OPACR52_TP:1; /* Trusted Protect */ + uint32_t OPACR53_BW:1; /* Buffer Writes */ + uint32_t OPACR53_SP:1; /* Supervisor Protect */ + uint32_t OPACR53_WP:1; /* Write Protect */ + uint32_t OPACR53_TP:1; /* Trusted Protect */ + uint32_t OPACR54_BW:1; /* Buffer Writes */ + uint32_t OPACR54_SP:1; /* Supervisor Protect */ + uint32_t OPACR54_WP:1; /* Write Protect */ + uint32_t OPACR54_TP:1; /* Trusted Protect */ + uint32_t OPACR55_BW:1; /* Buffer Writes */ + uint32_t OPACR55_SP:1; /* Supervisor Protect */ + uint32_t OPACR55_WP:1; /* Write Protect */ + uint32_t OPACR55_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR48_55_32B_tag; + + typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR56_BW:1; /* Buffer Writes */ + uint32_t OPACR56_SP:1; /* Supervisor Protect */ + uint32_t OPACR56_WP:1; /* Write Protect */ + uint32_t OPACR56_TP:1; /* Trusted Protect */ + uint32_t OPACR57_BW:1; /* Buffer Writes */ + uint32_t OPACR57_SP:1; /* Supervisor Protect */ + uint32_t OPACR57_WP:1; /* Write Protect */ + uint32_t OPACR57_TP:1; /* Trusted Protect */ + uint32_t OPACR58_BW:1; /* Buffer Writes */ + uint32_t OPACR58_SP:1; /* Supervisor Protect */ + uint32_t OPACR58_WP:1; /* Write Protect */ + uint32_t OPACR58_TP:1; /* Trusted Protect */ + uint32_t OPACR59_BW:1; /* Buffer Writes */ + uint32_t OPACR59_SP:1; /* Supervisor Protect */ + uint32_t OPACR59_WP:1; /* Write Protect */ + uint32_t OPACR59_TP:1; /* Trusted Protect */ + uint32_t OPACR60_BW:1; /* Buffer Writes */ + uint32_t OPACR60_SP:1; /* Supervisor Protect */ + uint32_t OPACR60_WP:1; /* Write Protect */ + uint32_t OPACR60_TP:1; /* Trusted Protect */ + uint32_t OPACR61_BW:1; /* Buffer Writes */ + uint32_t OPACR61_SP:1; /* Supervisor Protect */ + uint32_t OPACR61_WP:1; /* Write Protect */ + uint32_t OPACR61_TP:1; /* Trusted Protect */ + uint32_t OPACR62_BW:1; /* Buffer Writes */ + uint32_t OPACR62_SP:1; /* Supervisor Protect */ + uint32_t OPACR62_WP:1; /* Write Protect */ + uint32_t OPACR62_TP:1; /* Trusted Protect */ + uint32_t OPACR63_BW:1; /* Buffer Writes */ + uint32_t OPACR63_SP:1; /* Supervisor Protect */ + uint32_t OPACR63_WP:1; /* Write Protect */ + uint32_t OPACR63_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR56_63_32B_tag; + + typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR64_BW:1; /* Buffer Writes */ + uint32_t OPACR64_SP:1; /* Supervisor Protect */ + uint32_t OPACR64_WP:1; /* Write Protect */ + uint32_t OPACR64_TP:1; /* Trusted Protect */ + uint32_t OPACR65_BW:1; /* Buffer Writes */ + uint32_t OPACR65_SP:1; /* Supervisor Protect */ + uint32_t OPACR65_WP:1; /* Write Protect */ + uint32_t OPACR65_TP:1; /* Trusted Protect */ + uint32_t OPACR66_BW:1; /* Buffer Writes */ + uint32_t OPACR66_SP:1; /* Supervisor Protect */ + uint32_t OPACR66_WP:1; /* Write Protect */ + uint32_t OPACR66_TP:1; /* Trusted Protect */ + uint32_t OPACR67_BW:1; /* Buffer Writes */ + uint32_t OPACR67_SP:1; /* Supervisor Protect */ + uint32_t OPACR67_WP:1; /* Write Protect */ + uint32_t OPACR67_TP:1; /* Trusted Protect */ + uint32_t OPACR68_BW:1; /* Buffer Writes */ + uint32_t OPACR68_SP:1; /* Supervisor Protect */ + uint32_t OPACR68_WP:1; /* Write Protect */ + uint32_t OPACR68_TP:1; /* Trusted Protect */ + uint32_t OPACR69_BW:1; /* Buffer Writes */ + uint32_t OPACR69_SP:1; /* Supervisor Protect */ + uint32_t OPACR69_WP:1; /* Write Protect */ + uint32_t OPACR69_TP:1; /* Trusted Protect */ + uint32_t OPACR70_BW:1; /* Buffer Writes */ + uint32_t OPACR70_SP:1; /* Supervisor Protect */ + uint32_t OPACR70_WP:1; /* Write Protect */ + uint32_t OPACR70_TP:1; /* Trusted Protect */ + uint32_t OPACR71_BW:1; /* Buffer Writes */ + uint32_t OPACR71_SP:1; /* Supervisor Protect */ + uint32_t OPACR71_WP:1; /* Write Protect */ + uint32_t OPACR71_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR64_71_32B_tag; + + typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR72_BW:1; /* Buffer Writes */ + uint32_t OPACR72_SP:1; /* Supervisor Protect */ + uint32_t OPACR72_WP:1; /* Write Protect */ + uint32_t OPACR72_TP:1; /* Trusted Protect */ + uint32_t OPACR73_BW:1; /* Buffer Writes */ + uint32_t OPACR73_SP:1; /* Supervisor Protect */ + uint32_t OPACR73_WP:1; /* Write Protect */ + uint32_t OPACR73_TP:1; /* Trusted Protect */ + uint32_t OPACR74_BW:1; /* Buffer Writes */ + uint32_t OPACR74_SP:1; /* Supervisor Protect */ + uint32_t OPACR74_WP:1; /* Write Protect */ + uint32_t OPACR74_TP:1; /* Trusted Protect */ + uint32_t OPACR75_BW:1; /* Buffer Writes */ + uint32_t OPACR75_SP:1; /* Supervisor Protect */ + uint32_t OPACR75_WP:1; /* Write Protect */ + uint32_t OPACR75_TP:1; /* Trusted Protect */ + uint32_t OPACR76_BW:1; /* Buffer Writes */ + uint32_t OPACR76_SP:1; /* Supervisor Protect */ + uint32_t OPACR76_WP:1; /* Write Protect */ + uint32_t OPACR76_TP:1; /* Trusted Protect */ + uint32_t OPACR77_BW:1; /* Buffer Writes */ + uint32_t OPACR77_SP:1; /* Supervisor Protect */ + uint32_t OPACR77_WP:1; /* Write Protect */ + uint32_t OPACR77_TP:1; /* Trusted Protect */ + uint32_t OPACR78_BW:1; /* Buffer Writes */ + uint32_t OPACR78_SP:1; /* Supervisor Protect */ + uint32_t OPACR78_WP:1; /* Write Protect */ + uint32_t OPACR78_TP:1; /* Trusted Protect */ + uint32_t OPACR79_BW:1; /* Buffer Writes */ + uint32_t OPACR79_SP:1; /* Supervisor Protect */ + uint32_t OPACR79_WP:1; /* Write Protect */ + uint32_t OPACR79_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR72_79_32B_tag; + + typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR80_BW:1; /* Buffer Writes */ + uint32_t OPACR80_SP:1; /* Supervisor Protect */ + uint32_t OPACR80_WP:1; /* Write Protect */ + uint32_t OPACR80_TP:1; /* Trusted Protect */ + uint32_t OPACR81_BW:1; /* Buffer Writes */ + uint32_t OPACR81_SP:1; /* Supervisor Protect */ + uint32_t OPACR81_WP:1; /* Write Protect */ + uint32_t OPACR81_TP:1; /* Trusted Protect */ + uint32_t OPACR82_BW:1; /* Buffer Writes */ + uint32_t OPACR82_SP:1; /* Supervisor Protect */ + uint32_t OPACR82_WP:1; /* Write Protect */ + uint32_t OPACR82_TP:1; /* Trusted Protect */ + uint32_t OPACR83_BW:1; /* Buffer Writes */ + uint32_t OPACR83_SP:1; /* Supervisor Protect */ + uint32_t OPACR83_WP:1; /* Write Protect */ + uint32_t OPACR83_TP:1; /* Trusted Protect */ + uint32_t OPACR84_BW:1; /* Buffer Writes */ + uint32_t OPACR84_SP:1; /* Supervisor Protect */ + uint32_t OPACR84_WP:1; /* Write Protect */ + uint32_t OPACR84_TP:1; /* Trusted Protect */ + uint32_t OPACR85_BW:1; /* Buffer Writes */ + uint32_t OPACR85_SP:1; /* Supervisor Protect */ + uint32_t OPACR85_WP:1; /* Write Protect */ + uint32_t OPACR85_TP:1; /* Trusted Protect */ + uint32_t OPACR86_BW:1; /* Buffer Writes */ + uint32_t OPACR86_SP:1; /* Supervisor Protect */ + uint32_t OPACR86_WP:1; /* Write Protect */ + uint32_t OPACR86_TP:1; /* Trusted Protect */ + uint32_t OPACR87_BW:1; /* Buffer Writes */ + uint32_t OPACR87_SP:1; /* Supervisor Protect */ + uint32_t OPACR87_WP:1; /* Write Protect */ + uint32_t OPACR87_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR80_87_32B_tag; + + typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ + uint32_t R; + struct { + uint32_t OPACR88_BW:1; /* Buffer Writes */ + uint32_t OPACR88_SP:1; /* Supervisor Protect */ + uint32_t OPACR88_WP:1; /* Write Protect */ + uint32_t OPACR88_TP:1; /* Trusted Protect */ + uint32_t OPACR89_BW:1; /* Buffer Writes */ + uint32_t OPACR89_SP:1; /* Supervisor Protect */ + uint32_t OPACR89_WP:1; /* Write Protect */ + uint32_t OPACR89_TP:1; /* Trusted Protect */ + uint32_t OPACR90_BW:1; /* Buffer Writes */ + uint32_t OPACR90_SP:1; /* Supervisor Protect */ + uint32_t OPACR90_WP:1; /* Write Protect */ + uint32_t OPACR90_TP:1; /* Trusted Protect */ + uint32_t OPACR91_BW:1; /* Buffer Writes */ + uint32_t OPACR91_SP:1; /* Supervisor Protect */ + uint32_t OPACR91_WP:1; /* Write Protect */ + uint32_t OPACR91_TP:1; /* Trusted Protect */ + uint32_t OPACR92_BW:1; /* Buffer Writes */ + uint32_t OPACR92_SP:1; /* Supervisor Protect */ + uint32_t OPACR92_WP:1; /* Write Protect */ + uint32_t OPACR92_TP:1; /* Trusted Protect */ + uint32_t OPACR93_BW:1; /* Buffer Writes */ + uint32_t OPACR93_SP:1; /* Supervisor Protect */ + uint32_t OPACR93_WP:1; /* Write Protect */ + uint32_t OPACR93_TP:1; /* Trusted Protect */ + uint32_t OPACR94_BW:1; /* Buffer Writes */ + uint32_t OPACR94_SP:1; /* Supervisor Protect */ + uint32_t OPACR94_WP:1; /* Write Protect */ + uint32_t OPACR94_TP:1; /* Trusted Protect */ + uint32_t OPACR95_BW:1; /* Buffer Writes */ + uint32_t OPACR95_SP:1; /* Supervisor Protect */ + uint32_t OPACR95_WP:1; /* Write Protect */ + uint32_t OPACR95_TP:1; /* Trusted Protect */ + } B; + } PBRIDGE_OPACR88_95_32B_tag; + + + + typedef struct PBRIDGE_struct_tag { /* start of PBRIDGE_tag */ + /* MPROT - Master Privilege Registers */ + PBRIDGE_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */ + int8_t PBRIDGE_reserved_0004[28]; + /* PACR0_7 - Peripheral Access Control Registers */ + PBRIDGE_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */ + /* PACR8_15 - Peripheral Access Control Registers */ + PBRIDGE_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */ + /* PACR16_23 - Peripheral Access Control Registers */ + PBRIDGE_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */ + /* PACR24_31 - Peripheral Access Control Registers */ + PBRIDGE_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */ + int8_t PBRIDGE_reserved_0030[16]; + /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */ + /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */ + /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */ + /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */ + /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */ + /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */ + /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */ + /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */ + /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */ + /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */ + /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */ + /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */ + PBRIDGE_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */ + } PBRIDGE_tag; + + +#define PBRIDGE (*(volatile PBRIDGE_tag *) 0xFFF00000UL) + + + +/****************************************************************/ +/* */ +/* Module: MAX */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers MPR... */ + + typedef union { /* Master Priority Register for slave port n */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR_7:3; /* Master 7 Priority */ + uint32_t:1; + uint32_t MSTR_6:3; /* Master 6 Priority */ + uint32_t:1; + uint32_t MSTR_5:3; /* Master 5 Priority */ + uint32_t:1; + uint32_t MSTR_4:3; /* Master 4 Priority */ + uint32_t:1; + uint32_t MSTR_3:3; /* Master 3 Priority */ + uint32_t:1; + uint32_t MSTR_2:3; /* Master 2 Priority */ + uint32_t:1; + uint32_t MSTR_1:3; /* Master 1 Priority */ + uint32_t:1; + uint32_t MSTR_0:3; /* Master 0 Priority */ + } B; + } MAX_MPR_32B_tag; + + + /* Register layout for all registers AMPR matches xxx */ + + + /* Register layout for all registers SGPCR... */ + + typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + uint32_t R; + struct { + uint32_t RO:1; /* Read Only */ + uint32_t HLP:1; /* Halt Low Priority */ + uint32_t:6; + uint32_t HPE7:1; /* High Priority Enable */ + uint32_t HPE6:1; /* High Priority Enable */ + uint32_t HPE5:1; /* High Priority Enable */ + uint32_t HPE4:1; /* High Priority Enable */ + uint32_t HPE3:1; /* High Priority Enable */ + uint32_t HPE2:1; /* High Priority Enable */ + uint32_t HPE1:1; /* High Priority Enable */ + uint32_t HPE0:1; /* High Priority Enable */ + uint32_t:6; + uint32_t ARB:2; /* Arbitration Mode */ + uint32_t:2; + uint32_t PCTL:2; /* Parking Control */ + uint32_t:1; + uint32_t PARK:3; /* Park */ + } B; + } MAX_SGPCR_32B_tag; + + + /* Register layout for all registers ASGPCR... */ + + typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + uint32_t R; + struct { + uint32_t:1; + uint32_t HLP:1; /* Halt Low Priority */ + uint32_t:6; + uint32_t HPE7:1; /* High Priority Enable */ + uint32_t HPE6:1; /* High Priority Enable */ + uint32_t HPE5:1; /* High Priority Enable */ + uint32_t HPE4:1; /* High Priority Enable */ + uint32_t HPE3:1; /* High Priority Enable */ + uint32_t HPE2:1; /* High Priority Enable */ + uint32_t HPE1:1; /* High Priority Enable */ + uint32_t HPE0:1; /* High Priority Enable */ + uint32_t:6; + uint32_t ARB:2; /* Arbitration Mode */ + uint32_t:2; + uint32_t PCTL:2; /* Parking Control */ + uint32_t:1; + uint32_t PARK:3; /* Park */ + } B; + } MAX_ASGPCR_32B_tag; + + + /* Register layout for all registers MGPCR... */ + + typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */ + uint32_t R; + struct { + uint32_t:29; + uint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MAX_MGPCR_32B_tag; + + + typedef struct MAX_SLAVE_PORT_struct_tag { + + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */ + int8_t MAX_SLAVE_PORT_reserved_0008[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */ + int8_t MAX_SLAVE_PORT_reserved_0018[232]; + + } MAX_SLAVE_PORT_tag; + + typedef struct MAX_MASTER_PORT_struct_tag { + + /* MAX_MGPCRn - Master General Purpose Control Register n */ + MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */ + int8_t MAX_MASTER_PORT_reserved_0004[252]; + + } MAX_MASTER_PORT_tag; + + + typedef struct MAX_struct_tag { /* start of MAX_tag */ + union { + /* Register set SLAVE_PORT */ + MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */ + + struct { + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */ + int8_t MAX_reserved_0008_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */ + int8_t MAX_reserved_0018_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */ + int8_t MAX_reserved_0108_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */ + int8_t MAX_reserved_0118_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */ + int8_t MAX_reserved_0208_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */ + int8_t MAX_reserved_0218_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */ + int8_t MAX_reserved_0308_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */ + int8_t MAX_reserved_0318_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */ + int8_t MAX_reserved_0408_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */ + int8_t MAX_reserved_0418_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */ + int8_t MAX_reserved_0508_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */ + int8_t MAX_reserved_0518_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */ + int8_t MAX_reserved_0608_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */ + int8_t MAX_reserved_0618_I1[232]; + /* Master Priority Register for slave port n */ + MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */ + /* Alternate Master Priority Register for slave port n */ + MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */ + int8_t MAX_reserved_0708_I1[8]; + /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */ + MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */ + /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */ + MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */ + int8_t MAX_reserved_0718_E1[232]; + }; + + }; + union { + /* Register set MASTER_PORT */ + MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */ + + struct { + /* MAX_MGPCRn - Master General Purpose Control Register n */ + MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */ + int8_t MAX_reserved_0804_I1[252]; + MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */ + int8_t MAX_reserved_0904_I1[252]; + MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */ + int8_t MAX_reserved_0A04_I1[252]; + MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */ + int8_t MAX_reserved_0B04_I1[252]; + MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */ + int8_t MAX_reserved_0C04_I1[252]; + MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */ + int8_t MAX_reserved_0D04_I1[252]; + MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */ + int8_t MAX_reserved_0E04_I1[252]; + MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */ + int8_t MAX_reserved_0F04_E1[252]; + }; + + }; + } MAX_tag; + + +#define MAX (*(volatile MAX_tag *) 0xFFF04000UL) + + + +/****************************************************************/ +/* */ +/* Module: MPU */ +/* */ +/****************************************************************/ + + typedef union { /* MPU_CESR - MPU Control/Error Status Register */ + uint32_t R; + struct { + uint32_t SPERR:8; /* Slave Port n Error */ + uint32_t:4; + uint32_t HRL:4; /* Hardware Revision Level */ + uint32_t NSP:4; /* Number of Slave Ports */ + uint32_t NRGD:4; /* Number of Region Descriptors */ + uint32_t:7; + uint32_t VLD:1; /* Valid bit */ + } B; + } MPU_CESR_32B_tag; + + + /* Register layout for all registers EAR... */ + + typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */ + uint32_t R; + struct { + uint32_t EADDR:32; /* Error Address */ + } B; + } MPU_EAR_32B_tag; + + + /* Register layout for all registers EDR... */ + + typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + uint32_t R; + struct { + uint32_t EACD:16; /* Error Access Control Detail */ + uint32_t EPID:8; /* Error Process Identification */ + uint32_t EMN:4; /* Error Master Number */ + uint32_t EATTR:3; /* Error Attributes */ + uint32_t ERW:1; /* Error Read/Write */ + } B; + } MPU_EDR_32B_tag; + + + /* Register layout for all registers RGD_WORD0... */ + + typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t SRTADDR:27; /* Start Address */ + uint32_t:5; + } B; + } MPU_RGD_WORD0_32B_tag; + + + /* Register layout for all registers RGD_WORD1... */ + + typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t ENDADDR:27; /* End Address */ + uint32_t:5; + } B; + } MPU_RGD_WORD1_32B_tag; + + + /* Register layout for all registers RGD_WORD2... */ + + typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t M7RE:1; /* Bus Master 7 Read Enable */ + uint32_t M7WE:1; /* Bus Master 7 Write Enable */ + uint32_t M6RE:1; /* Bus Master 6 Read Enable */ + uint32_t M6WE:1; /* Bus Master 7 Write Enable */ + uint32_t M5RE:1; /* Bus Master 5 Read Enable */ + uint32_t M5WE:1; /* Bus Master 5 Write Enable */ + uint32_t M4RE:1; /* Bus Master 4 Read Enable */ + uint32_t M4WE:1; /* Bus Master 4 Write Enable */ + uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ + uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ + uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ + uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ + uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ + uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ + uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ + uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ + uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ + uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ + uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ + uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ + } B; + } MPU_RGD_WORD2_32B_tag; + + + /* Register layout for all registers RGD_WORD3... */ + + typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */ + uint32_t R; + struct { + uint32_t PID:8; /* Process Identifier */ + uint32_t PIDMASK:8; /* Process Identifier Mask */ + uint32_t:15; + uint32_t VLD:1; /* Valid */ + } B; + } MPU_RGD_WORD3_32B_tag; + + + /* Register layout for all registers RGDAAC... */ + + typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + uint32_t R; + struct { + uint32_t M7RE:1; /* Bus Master 7 Read Enable */ + uint32_t M7WE:1; /* Bus Master 7 Write Enable */ + uint32_t M6RE:1; /* Bus Master 6 Read Enable */ + uint32_t M6WE:1; /* Bus Master 7 Write Enable */ + uint32_t M5RE:1; /* Bus Master 5 Read Enable */ + uint32_t M5WE:1; /* Bus Master 5 Write Enable */ + uint32_t M4RE:1; /* Bus Master 4 Read Enable */ + uint32_t M4WE:1; /* Bus Master 4 Write Enable */ + uint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */ + uint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */ + uint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */ + uint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */ + uint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */ + uint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */ + uint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */ + uint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */ + uint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */ + uint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */ + uint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */ + uint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */ + } B; + } MPU_RGDAAC_32B_tag; + + + typedef struct MPU_SLAVE_PORT_struct_tag { + + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */ + + } MPU_SLAVE_PORT_tag; + + typedef struct MPU_REGION_struct_tag { + + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */ + + } MPU_REGION_tag; + + + typedef struct MPU_struct_tag { /* start of MPU_tag */ + /* MPU_CESR - MPU Control/Error Status Register */ + MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */ + int8_t MPU_reserved_0004_C[12]; + union { + /* Register set SLAVE_PORT */ + MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */ + + struct { + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */ + /* MPU_EARn - MPU Error Address Register, Slave Port n */ + MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */ + /* MPU_EDRn - MPU Error Detail Register, Slave Port n */ + MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */ + }; + + }; + int8_t MPU_reserved_0030_C[976]; + union { + /* Register set REGION */ + MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */ + + struct { + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */ + /* MPU_RGDn_Word0 - MPU Region Descriptor */ + MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */ + /* MPU_RGDn_Word1 - MPU Region Descriptor */ + MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */ + /* MPU_RGDn_Word2 - MPU Region Descriptor */ + MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */ + /* MPU_RGDn_Word3 - MPU Region Descriptor */ + MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */ + }; + + }; + int8_t MPU_reserved_0500_C[768]; + union { + /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */ + + struct { + /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */ + MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */ + MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */ + }; + + }; + } MPU_tag; + + +#define MPU (*(volatile MPU_tag *) 0xFFF10000UL) + + + +/****************************************************************/ +/* */ +/* Module: SEMA4 */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers GATE... */ + + typedef union { /* SEMA4_GATEn - Semephores Gate Register */ + uint8_t R; + struct { + uint8_t:6; + uint8_t GTFSM:2; /* Gate Finite State machine */ + } B; + } SEMA4_GATE_8B_tag; + + typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ + uint16_t R; + struct { + uint16_t INE:16; /* Interrupt Request Notification Enable */ + } B; + } SEMA4_CP0INE_16B_tag; + + typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ + uint16_t R; + struct { + uint16_t INE:16; /* Interrupt Request Notification Enable */ + } B; + } SEMA4_CP1INE_16B_tag; + + typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ + uint16_t R; + struct { + uint16_t GN:16; /* Gate 0 Notification */ + } B; + } SEMA4_CP0NTF_16B_tag; + + typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ + uint16_t R; + struct { + uint16_t GN:16; /* Gate 1 Notification */ + } B; + } SEMA4_CP1NTF_16B_tag; + + typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */ + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTGSM:2; /* Reset Gate Finite State Machine */ + uint16_t RSTGDP:7; /* Reset Gate Data Pattern */ + uint16_t RSTGMS:3; /* Reset Gate Bus Master */ + uint16_t RSTGTN:8; /* Reset Gate Number */ + } B; + } SEMA4_RSTGT_16B_tag; + + typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTNSM:2; /* Reset Gate Finite State Machine */ + uint16_t RSTNDP:7; /* Reset Gate Data Pattern */ + uint16_t RSTNMS:3; /* Reset Gate Bus Master */ + uint16_t RSTNTN:8; /* Reset Gate Number */ + } B; + } SEMA4_RSTNTF_16B_tag; + + + + typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */ + union { + /* SEMA4_GATEn - Semephores Gate Register */ + SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */ + + struct { + /* SEMA4_GATEn - Semephores Gate Register */ + SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */ + SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */ + SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */ + SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */ + SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */ + SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */ + SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */ + SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */ + SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */ + SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */ + SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */ + SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */ + SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */ + SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */ + SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */ + SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */ + }; + + }; + int8_t SEMA4_reserved_0010[48]; + /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */ + SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */ + int8_t SEMA4_reserved_0042[6]; + /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */ + SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */ + int8_t SEMA4_reserved_004A[54]; + /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */ + SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */ + int8_t SEMA4_reserved_0082[6]; + /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */ + SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */ + int8_t SEMA4_reserved_008A[118]; + /* SEMA4_RSTGT - Semaphores Reset Gate */ + SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */ + int8_t SEMA4_reserved_0102[2]; + /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */ + SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */ + } SEMA4_tag; + + +#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL) + + + +/****************************************************************/ +/* */ +/* Module: SWT */ +/* */ +/****************************************************************/ + + typedef union { /* SWT_CR - Control Register */ + uint32_t R; + struct { + uint32_t MAP0:1; /* Master Acces Protection for Master 0 */ + uint32_t MAP1:1; /* Master Acces Protection for Master 1 */ + uint32_t MAP2:1; /* Master Acces Protection for Master 2 */ + uint32_t MAP3:1; /* Master Acces Protection for Master 3 */ + uint32_t MAP4:1; /* Master Acces Protection for Master 4 */ + uint32_t MAP5:1; /* Master Acces Protection for Master 5 */ + uint32_t MAP6:1; /* Master Acces Protection for Master 6 */ + uint32_t MAP7:1; /* Master Acces Protection for Master 7 */ + uint32_t:14; + uint32_t KEY:1; /* Keyed Service Mode */ + uint32_t RIA:1; /* Reset on Invalid Access */ + uint32_t WND:1; /* Window Mode */ + uint32_t ITR:1; /* Interrupt Then Reset */ + uint32_t HLK:1; /* Hard Lock */ + uint32_t SLK:1; /* Soft Lock */ + uint32_t:1; + uint32_t STP:1; /* Stop Mode Control */ + uint32_t FRZ:1; /* Debug Mode Control */ + uint32_t WEN:1; /* Watchdog Enabled */ + } B; + } SWT_CR_32B_tag; + + typedef union { /* SWT_IR - SWT Interrupt Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; /* Time Out Interrupt Flag */ + } B; + } SWT_IR_32B_tag; + + typedef union { /* SWT_TO - SWT Time-Out Register */ + uint32_t R; + struct { + uint32_t WTO:32; /* Watchdog Time Out Period */ + } B; + } SWT_TO_32B_tag; + + typedef union { /* SWT_WN - SWT Window Register */ + uint32_t R; + struct { + uint32_t WST:32; /* Watchdog Time Out Period */ + } B; + } SWT_WN_32B_tag; + + typedef union { /* SWT_SR - SWT Service Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t WSC:16; /* Watchdog Service Code */ + } B; + } SWT_SR_32B_tag; + + typedef union { /* SWT_CO - SWT Counter Output Register */ + uint32_t R; + struct { + uint32_t CNT:32; /* Watchdog Count */ + } B; + } SWT_CO_32B_tag; + + typedef union { /* SWT_SK - SWT Service Key Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SERVICEKEY:16; /* Service Key */ + } B; + } SWT_SK_32B_tag; + + + + typedef struct SWT_struct_tag { /* start of SWT_tag */ + /* SWT_CR - Control Register */ + SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + /* SWT_IR - SWT Interrupt Register */ + SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */ + /* SWT_TO - SWT Time-Out Register */ + SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */ + /* SWT_WN - SWT Window Register */ + SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */ + /* SWT_SR - SWT Service Register */ + SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */ + /* SWT_CO - SWT Counter Output Register */ + SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */ + /* SWT_SK - SWT Service Key Register */ + SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */ + } SWT_tag; + + +#define SWT (*(volatile SWT_tag *) 0xFFF38000UL) + + + +/****************************************************************/ +/* */ +/* Module: STM */ +/* */ +/****************************************************************/ + + typedef union { /* STM_CR - Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t CPS:8; /* Counter Prescaler */ + uint32_t:6; + uint32_t FRZ:1; /* Freeze Control */ + uint32_t TEN:1; /* Timer Counter Enabled */ + } B; + } STM_CR_32B_tag; + + typedef union { /* STM_CNT - STM Count Register */ + uint32_t R; + } STM_CNT_32B_tag; + + + /* Register layout for all registers CCR... */ + + typedef union { /* STM_CCRn - STM Channel Control Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; /* Channel Enable */ + } B; + } STM_CCR_32B_tag; + + + /* Register layout for all registers CIR... */ + + typedef union { /* STM_CIRn - STM Channel Interrupt Register */ + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; /* Channel Interrupt Flag */ + } B; + } STM_CIR_32B_tag; + + + /* Register layout for all registers CMP... */ + + typedef union { /* STM_CMPn - STM Channel Compare Register */ + uint32_t R; + } STM_CMP_32B_tag; + + + typedef struct STM_CHANNEL_struct_tag { + + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */ + int8_t STM_CHANNEL_reserved_000C[4]; + + } STM_CHANNEL_tag; + + + typedef struct STM_struct_tag { /* start of STM_tag */ + union { + STM_CR_32B_tag CR0; /* deprecated - please avoid */ + + /* STM_CR - Control Register */ + STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */ + + }; + union { + STM_CNT_32B_tag CNT0; /* deprecated - please avoid */ + + /* STM_CNT - STM Count Register */ + STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */ + + }; + int8_t STM_reserved_0008_C[8]; + union { + /* Register set CHANNEL */ + STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */ + + struct { + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */ + int8_t STM_reserved_001C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */ + int8_t STM_reserved_002C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */ + int8_t STM_reserved_003C_I1[4]; + /* STM_CCRn - STM Channel Control Register */ + STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */ + /* STM_CIRn - STM Channel Interrupt Register */ + STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */ + /* STM_CMPn - STM Channel Compare Register */ + STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */ + int8_t STM_reserved_004C_E1[4]; + }; + + }; + } STM_tag; + + +#define STM (*(volatile STM_tag *) 0xFFF3C000UL) + + + +/****************************************************************/ +/* */ +/* Module: SPP_MCM */ +/* */ +/****************************************************************/ + + typedef union { /* SPP_MCM_PCT - Processor Core Type */ + uint16_t R; + struct { + uint16_t PCTYPE:16; /* Processor Core Type */ + } B; + } SPP_MCM_PCT_16B_tag; + + typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ + uint16_t R; + struct { + uint16_t PLREVISION:16; /* Platform Revision */ + } B; + } SPP_MCM_PLREV_16B_tag; + + typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ + uint32_t R; + struct { + uint32_t PMC:32; /* IPS Module Configuration */ + } B; + } SPP_MCM_IOPMC_32B_tag; + + typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ + uint8_t R; + struct { + uint8_t POR:1; /* Power on Reset */ +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t OFPLR:1; /* Off-Platform Reset */ +#else + uint8_t DIR:1; /* deprecated name - please avoid */ +#endif + uint8_t:6; + } B; + } SPP_MCM_MRSR_8B_tag; + + typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ + uint8_t R; + struct { + uint8_t ENBWCR:1; /* Enable WCR */ + uint8_t:3; + uint8_t PRILVL:4; /* Interrupt Priority Level */ + } B; + } SPP_MCM_MWCR_8B_tag; + + typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ + uint8_t R; + struct { + uint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */ + uint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */ + uint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */ + uint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */ + uint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */ + uint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */ + uint8_t:2; + } B; + } SPP_MCM_MIR_8B_tag; + + typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ + uint32_t R; + struct { + uint32_t MUSERDCR:32; /* User Defined Control Register */ + } B; + } SPP_MCM_MUDCR_32B_tag; + + typedef union { /* SPP_MCM_ECR - ECC Configuration Register */ + uint8_t R; + struct { + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */ +#else + uint8_t ER1BR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */ +#else + uint8_t EF1BR:1; /* deprecated name - please avoid */ +#endif + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */ +#else + uint8_t ERNCR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */ +#else + uint8_t EFNCR:1; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_ECR_8B_tag; + + typedef union { /* SPP_MCM_ESR - ECC Status Register */ + uint8_t R; + struct { + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PR1BC:1; /* Platform RAM 1-bit Correction */ +#else + uint8_t R1BC:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */ +#else + uint8_t F1BC:1; /* deprecated name - please avoid */ +#endif + uint8_t:2; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */ +#else + uint8_t RNCE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */ +#else + uint8_t FNCE:1; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_ESR_8B_tag; + + typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */ + uint16_t R; + struct { + uint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */ + uint16_t:1; + uint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */ + uint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */ + uint16_t:2; + uint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */ + uint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */ + uint16_t:1; + uint16_t ERRBIT:7; /* Error Bit Position */ + } B; + } SPP_MCM_EEGR_16B_tag; + + typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ + uint32_t R; + } SPP_MCM_PFEAR_32B_tag; + + typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ + uint8_t R; + } SPP_MCM_PFEMR_8B_tag; + + typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ + uint8_t R; + struct { +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t F_WRITE:1; /* AMBA-AHBH Write */ +#else + uint8_t WRITE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t F_SIZE:3; /* AMBA-AHBH Size */ +#else + uint8_t SIZE:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t F_PROTECT:4; /* AMBA-AHBH PROT */ +#else + uint8_t PROTECTION:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PFEAT_8B_tag; + + typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ + uint32_t R; + } SPP_MCM_PFEDRH_32B_tag; + + typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ + uint32_t R; + } SPP_MCM_PFEDR_32B_tag; + + typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ + uint32_t R; + } SPP_MCM_PREAR_32B_tag; + + typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ + uint8_t R; + } SPP_MCM_PRESR_8B_tag; + + typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ + uint8_t R; + struct { + uint8_t:4; +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t PR_EMR:4; /* Platform RAM ECC Master Number */ +#else + uint8_t REMR:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PREMR_8B_tag; + + typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ + uint8_t R; + struct { +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t R_WRITE:1; /* AMBA-AHBH Write */ +#else + uint8_t WRITE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t R_SIZE:3; /* AMBA-AHBH Size */ +#else + uint8_t SIZE:3; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_SPP_MCM + uint8_t R_PROTECT:4; /* AMBA-AHBH PROT */ +#else + uint8_t PROTECTION:4; /* deprecated name - please avoid */ +#endif + } B; + } SPP_MCM_PREAT_8B_tag; + + typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ + uint32_t R; + } SPP_MCM_PREDRH_32B_tag; + + typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ + uint32_t R; + } SPP_MCM_PREDR_32B_tag; + + + + typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */ + /* SPP_MCM_PCT - Processor Core Type */ + SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */ + union { + SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */ + + /* SPP_MCM_PLREV - SOC-Defined Platform Revision */ + SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */ + + }; + int8_t SPP_MCM_reserved_0004_C[4]; + union { + SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */ + + /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */ + SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */ + + }; + int8_t SPP_MCM_reserved_000C[3]; + /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */ + SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */ + int8_t SPP_MCM_reserved_0010[3]; + /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */ + SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */ + int8_t SPP_MCM_reserved_0014[11]; + /* SPP_MCM_MIR - Miscellaneous Interrupt Register */ + SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */ + int8_t SPP_MCM_reserved_0020[4]; + /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */ + SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */ + int8_t SPP_MCM_reserved_0028[27]; + /* SPP_MCM_ECR - ECC Configuration Register */ + SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */ + int8_t SPP_MCM_reserved_0044[3]; + /* SPP_MCM_ESR - ECC Status Register */ + SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */ + int8_t SPP_MCM_reserved_0048[2]; + /* SPP_MCM_EEGR - ECC Error Generation Register */ + SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */ + int8_t SPP_MCM_reserved_004C_C[4]; + union { + /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */ + SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */ + + SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */ + + }; + int8_t SPP_MCM_reserved_0054_C[2]; + union { + /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */ + SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */ + + SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */ + + }; + union { + /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */ + SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */ + + SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */ + + }; + /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */ + SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */ + union { + /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */ + SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */ + + SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */ + + }; + union { + SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */ + + /* SPP_MCM_PREAR - Platform RAM ECC Address Register */ + SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */ + + }; + int8_t SPP_MCM_reserved_0064_C; + union { + SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */ + + /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */ + SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */ + + }; + union { + SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */ + + /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */ + SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */ + + }; + union { + SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */ + + /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */ + SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */ + + }; + /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */ + SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */ + union { + SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */ + + /* SPP_MCM_PREDR - Platform RAM ECC Data Register */ + SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */ + + }; + } SPP_MCM_tag; + + +#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL) + + + +/****************************************************************/ +/* */ +/* Module: SPP_DMA2 */ +/* */ +/****************************************************************/ + + typedef union { /* SPP_DMA2_DMACR - DMA Control Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t CX:1; /* Cancel Transfer */ + uint32_t ECX:1; /* Error Cancel Transfer */ + uint32_t GRP3PRI:2; /* Channel Group 3 Priority */ + uint32_t GRP2PRI:2; /* Channel Group 2 Priority */ + uint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + uint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + uint32_t EMLM:1; /* Enable Minor Loop Mapping */ + uint32_t CLM:1; /* Continuous Link Mode */ + uint32_t HALT:1; /* Halt DMA Operations */ + uint32_t HOE:1; /* Halt on Error */ + uint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + uint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + uint32_t EDBG:1; /* Enable Debug */ + uint32_t EBW:1; /* Enable Buffered Writes */ + } B; + } SPP_DMA2_DMACR_32B_tag; + + typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */ + uint32_t R; + struct { + uint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */ + uint32_t:14; + uint32_t ECX:1; /* Transfer Cancelled */ + uint32_t GPE:1; /* Group Priority Error */ + uint32_t CPE:1; /* Channel Priority Error */ + uint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */ + uint32_t SAE:1; /* Source Address Error */ + uint32_t SOE:1; /* Source Offset Error */ + uint32_t DAE:1; /* Destination Address Error */ + uint32_t DOE:1; /* Destination Offset Error */ + uint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + uint32_t SGE:1; /* Scatter/Gather Configuration Error */ + uint32_t SBE:1; /* Source Bus Error */ + uint32_t DBE:1; /* Destination Bus Error */ + } B; + } SPP_DMA2_DMAES_32B_tag; + + typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ + uint32_t R; + struct { + uint32_t ERQ:32; /* DMA Enable Request */ + } B; + } SPP_DMA2_DMAERQH_32B_tag; + + typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ + uint32_t R; + struct { + uint32_t ERQ:32; /* DMA Enable Request */ + } B; + } SPP_DMA2_DMAERQL_32B_tag; + + typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ + uint32_t R; + struct { + uint32_t EEI:32; /* DMA Enable Error Interrupt */ + } B; + } SPP_DMA2_DMAEEIH_32B_tag; + + typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ + uint32_t R; + struct { + uint32_t EEI:32; /* DMA Enable Error Interrupt */ + } B; + } SPP_DMA2_DMAEEIL_32B_tag; + + typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t SERQ:7; /* Set Enable Request */ + } B; + } SPP_DMA2_DMASERQ_8B_tag; + + typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CERQ:7; /* Clear Enable Request */ + } B; + } SPP_DMA2_DMACERQ_8B_tag; + + typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t SEEI:7; /* Set Enable Error Interrupt */ + } B; + } SPP_DMA2_DMASEEI_8B_tag; + + typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CEEI:7; /* Clear Enable Error Interrupt */ + } B; + } SPP_DMA2_DMACEEI_8B_tag; + + typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CINT:7; /* Clear Interrupt Request */ + } B; + } SPP_DMA2_DMACINT_8B_tag; + + typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CERR:7; /* Clear Error Indicator */ + } B; + } SPP_DMA2_DMACERR_8B_tag; + + typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */ + uint8_t R; + struct { + uint8_t:1; + uint8_t SSRT:7; /* Set START Bit */ + } B; + } SPP_DMA2_DMASSRT_8B_tag; + + typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ + uint8_t R; + struct { + uint8_t:1; + uint8_t CDNE:7; /* Clear DONE Status Bit */ + } B; + } SPP_DMA2_DMACDNE_8B_tag; + + typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ + uint32_t R; + struct { + uint32_t INT:32; /* DMA Interrupt Request */ + } B; + } SPP_DMA2_DMAINTH_32B_tag; + + typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ + uint32_t R; + struct { + uint32_t INT:32; /* DMA Interrupt Request */ + } B; + } SPP_DMA2_DMAINTL_32B_tag; + + typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */ + uint32_t R; + struct { + uint32_t ERR:32; /* DMA Error n */ + } B; + } SPP_DMA2_DMAERRH_32B_tag; + + typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */ + uint32_t R; + struct { + uint32_t ERR:32; /* DMA Error n */ + } B; + } SPP_DMA2_DMAERRL_32B_tag; + + typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ + uint32_t R; + struct { + uint32_t HRS:32; /* DMA Hardware Request Status */ + } B; + } SPP_DMA2_DMAHRSH_32B_tag; + + typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ + uint32_t R; + struct { + uint32_t HRS:32; /* DMA Hardware Request Status */ + } B; + } SPP_DMA2_DMAHRSL_32B_tag; + + typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ + uint32_t R; + struct { + uint32_t GPOR:32; /* DMA General Purpose Output */ + } B; + } SPP_DMA2_DMAGPOR_32B_tag; + + + /* Register layout for all registers DCHPRI... */ + + typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + uint8_t R; + struct { + uint8_t ECP:1; /* Enable Channel Preemption */ + uint8_t DPA:1; /* Disable Preempt Ability */ + uint8_t GRPPRI:2; /* Channel n Current Group Priority */ + uint8_t CHPRI:4; /* Channel n Arbitration Priority */ + } B; + } SPP_DMA2_DCHPRI_8B_tag; + + + /* Register layout for all registers TCDWORD0_... */ + + typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */ + uint32_t R; + struct { + uint32_t SADDR:32; /* Source Address */ + } B; + } SPP_DMA2_TCDWORD0__32B_tag; + + + /* Register layout for all registers TCDWORD4_... */ + + typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + uint32_t R; + struct { + uint32_t SMOD:5; /* Source Address Modulo */ + uint32_t SSIZE:3; /* Source Data Transfer Size */ + uint32_t DMOD:5; /* Destination Address Module */ + uint32_t DSIZE:3; /* Destination Data Transfer Size */ + uint32_t SOFF:16; /* Source Address Signed Offset */ + } B; + } SPP_DMA2_TCDWORD4__32B_tag; + + + /* Register layout for all registers TCDWORD8_... */ + + typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */ + uint32_t R; + struct { + uint32_t SMLOE:1; /* Source Minor Loop Offset Enable */ + uint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */ + uint32_t MLOFF:20; /* Minor Loop Offset */ + uint32_t NBYTES:10; /* Inner Minor byte transfer Count */ + } B; + } SPP_DMA2_TCDWORD8__32B_tag; + + + /* Register layout for all registers TCDWORD12_... */ + + typedef union { /* SPP_DMA2_TCDn Word3 - slast */ + uint32_t R; + struct { + uint32_t SLAST:32; /* Last Source Address Adjustment */ + } B; + } SPP_DMA2_TCDWORD12__32B_tag; + + + /* Register layout for all registers TCDWORD16_... */ + + typedef union { /* SPP_DMA2_TCDn Word4 - daddr */ + uint32_t R; + struct { + uint32_t DADDR:32; /* Destination Address */ + } B; + } SPP_DMA2_TCDWORD16__32B_tag; + + + /* Register layout for all registers TCDWORD20_... */ + + typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + uint32_t R; + struct { + uint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */ + uint32_t CITER_LINKCH:6; /* Link Channel Number */ + uint32_t CITER:9; /* Current Major Iteration Count */ + uint32_t DOFF:16; /* Destination Address Signed Offset */ + } B; + } SPP_DMA2_TCDWORD20__32B_tag; + + + /* Register layout for all registers TCDWORD24_... */ + + typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */ + uint32_t R; + struct { + uint32_t DLAST_SGA:32; /* Last destination address adjustment */ + } B; + } SPP_DMA2_TCDWORD24__32B_tag; + + + /* Register layout for all registers TCDWORD28_... */ + + typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */ + uint32_t R; + struct { + +#ifndef USE_FIELD_ALIASES_SPP_DMA2 + uint32_t BITER_E_LINK:1; /* beginning ("major") iteration count */ +#else + uint32_t BITERE_LINK:1; /* deprecated name - please avoid */ +#endif + uint32_t BITER:15; /* Enable Channel to Channel linking on minor loop complete */ + uint32_t BWC:2; /* Bandwidth Control */ + uint32_t MAJOR_LINKCH:6; /* Link Channel Number */ + uint32_t DONE:1; /* channel done */ + uint32_t ACTIVE:1; /* Channel Active */ + uint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */ + uint32_t E_SG:1; /* Enable Scatter/Gather Processing */ + uint32_t D_REQ:1; /* Disable Request */ + uint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */ + uint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */ + uint32_t START:1; /* Channel Start */ + } B; + } SPP_DMA2_TCDWORD28__32B_tag; + + + typedef struct SPP_DMA2_CHANNEL_struct_tag { + + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */ + + } SPP_DMA2_CHANNEL_tag; + + + typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */ + /* SPP_DMA2_DMACR - DMA Control Register */ + SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */ + /* SPP_DMA2_DMAES - DMA Error Status Register */ + SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */ + /* SPP_DMA2_DMAERQH - DMA Enable Request Register */ + SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */ + /* SPP_DMA2_DMAERQL - DMA Enable Request Register */ + SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */ + /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */ + SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */ + /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */ + SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */ + /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */ + SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */ + /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */ + SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */ + /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */ + SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */ + /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */ + SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */ + /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */ + SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */ + /* SPP_DMA2_DMACERR - DMA Clear Error */ + SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */ + /* SPP_DMA2_DMASSRT - DMA Set START Bit */ + SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */ + /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */ + SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */ + /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */ + SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */ + /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */ + SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */ + /* SPP_DMA2_DMAERRH - DMA Error Register */ + SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */ + /* SPP_DMA2_DMAERRL - DMA Error Register */ + SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */ + /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */ + SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */ + /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */ + SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */ + /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */ + SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */ + int8_t SPP_DMA2_reserved_003C_C[196]; + union { + /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */ + + struct { + /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */ + SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */ + }; + + }; + int8_t SPP_DMA2_reserved_0140_C[3776]; + union { + /* Register set CHANNEL */ + SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */ + + struct { + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */ + /* SPP_DMA2_TCDn Word0 - Source Address */ + SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */ + /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */ + SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */ + /* SPP_DMA2_TCDn Word2 - nbytes */ + SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */ + /* SPP_DMA2_TCDn Word3 - slast */ + SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */ + /* SPP_DMA2_TCDn Word4 - daddr */ + SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */ + /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */ + SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */ + /* SPP_DMA2_TCDn Word6 - dlast_sga */ + SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */ + /* SPP_DMA2_TCDn Word7 - biter, etc. */ + SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */ + }; + + }; + } SPP_DMA2_tag; + + +#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL) + + + +/****************************************************************/ +/* */ +/* Module: INTC */ +/* */ +/****************************************************************/ + + typedef union { /* BCR - Block Configuration Register */ + uint32_t R; + struct { + uint32_t:18; + uint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */ + uint32_t:4; + uint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */ + uint32_t:2; +#ifndef USE_FIELD_ALIASES_INTC + uint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */ +#else + uint32_t VTES:1; /* deprecated name - please avoid */ +#endif + uint32_t:4; +#ifndef USE_FIELD_ALIASES_INTC + uint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */ +#else + uint32_t HVEN:1; /* deprecated name - please avoid */ +#endif + } B; + } INTC_BCR_32B_tag; + + typedef union { /* CPR - Current Priority Register - Processor 0 */ + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; /* Priority Bits */ + } B; + } INTC_CPR_PRC0_32B_tag; + + typedef union { /* CPR - Current Priority Register - Processor 1 */ + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; /* Priority Bits */ + } B; + } INTC_CPR_PRC1_32B_tag; + + typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_INTC + uint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */ +#else + uint32_t VTBA:21; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_INTC + uint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */ +#else + uint32_t INTVEC:9; /* deprecated name - please avoid */ +#endif + uint32_t:2; + } B; + } INTC_IACKR_PRC0_32B_tag; + + typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */ + uint32_t R; + struct { + uint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */ + uint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */ + uint32_t:2; + } B; + } INTC_IACKR_PRC1_32B_tag; + + typedef union { /* EOIR- End of Interrupt Register - Processor 0 */ + uint32_t R; + } INTC_EOIR_PRC0_32B_tag; + + typedef union { /* EOIR- End of Interrupt Register - Processor 1 */ + uint32_t R; + } INTC_EOIR_PRC1_32B_tag; + + + /* Register layout for all registers SSCIR... */ + + typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; /* Set Flag bit */ + uint8_t CLR:1; /* Clear Flag bit */ + } B; + } INTC_SSCIR_8B_tag; + + typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ + uint32_t R; + struct { + uint32_t:6; + uint32_t SET0:1; /* Set Flag 0 bit */ + uint32_t CLR0:1; /* Clear Flag 0 bit */ + uint32_t:6; + uint32_t SET1:1; /* Set Flag 1 bit */ + uint32_t CLR1:1; /* Clear Flag 1 bit */ + uint32_t:6; + uint32_t SET2:1; /* Set Flag 2 bit */ + uint32_t CLR2:1; /* Clear Flag 2 bit */ + uint32_t:6; + uint32_t SET3:1; /* Set Flag 3 bit */ + uint32_t CLR3:1; /* Clear Flag 3 bit */ + } B; + } INTC_SSCIR0_3_32B_tag; + + typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ + uint32_t R; + struct { + uint32_t:6; + uint32_t SET4:1; /* Set Flag 4 bit */ + uint32_t CLR4:1; /* Clear Flag 4 bit */ + uint32_t:6; + uint32_t SET5:1; /* Set Flag 5 bit */ + uint32_t CLR5:1; /* Clear Flag 5 bit */ + uint32_t:6; + uint32_t SET6:1; /* Set Flag 6 bit */ + uint32_t CLR6:1; /* Clear Flag 6 bit */ + uint32_t:6; + uint32_t SET7:1; /* Set Flag 7 bit */ + uint32_t CLR7:1; /* Clear Flag 7 bit */ + } B; + } INTC_SSCIR4_7_32B_tag; + + + /* Register layout for all registers PSR... */ + + typedef union { /* PSR0-511 - Priority Select Registers */ + uint8_t R; + struct { + uint8_t PRC_SEL:2; /* Processor Select */ + uint8_t:2; + uint8_t PRI:4; /* Priority Select */ + } B; + } INTC_PSR_8B_tag; + + + /* Register layout for all registers PSR... */ + + typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */ + uint32_t R; + struct { + uint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */ + uint32_t:2; + uint32_t PRI0:4; /* Priority Select - Entry 0 */ + uint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */ + uint32_t:2; + uint32_t PRI1:4; /* Priority Select - Entry 1 */ + uint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */ + uint32_t:2; + uint32_t PRI2:4; /* Priority Select - Entry 2 */ + uint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */ + uint32_t:2; + uint32_t PRI3:4; /* Priority Select - Entry 3 */ + } B; + } INTC_PSR_32B_tag; + + + + typedef struct INTC_struct_tag { /* start of INTC_tag */ + union { + INTC_BCR_32B_tag MCR; /* deprecated - please avoid */ + + /* BCR - Block Configuration Register */ + INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */ + + }; + int8_t INTC_reserved_0004_C[4]; + union { + /* CPR - Current Priority Register - Processor 0 */ + INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */ + + INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */ + + }; + /* CPR - Current Priority Register - Processor 1 */ + INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */ + union { + /* IACKR- Interrupt Acknowledge Register - Processor 0 */ + INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */ + + INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */ + + }; + /* IACKR- Interrupt Acknowledge Register - Processor 1 */ + INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */ + union { + /* EOIR- End of Interrupt Register - Processor 0 */ + INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */ + + INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */ + + }; + /* EOIR- End of Interrupt Register - Processor 1 */ + INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */ + union { + /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */ + + struct { + /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */ + INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */ + INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */ + }; + + struct { + /* SSCIR0_3 - Software Set/Clear Interrupt Registers */ + INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */ + /* SSCIR4_7 - Software Set/Clear Interrupt Registers */ + INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */ + }; + + }; + int8_t INTC_reserved_0028_C[24]; + union { + /* PSR0_3 - 508_511 - Priority Select Registers */ + INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */ + + /* PSR0-511 - Priority Select Registers */ + INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */ + + struct { + /* PSR0_3 - 508_511 - Priority Select Registers */ + INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */ + INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */ + INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */ + INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */ + INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */ + INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */ + INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */ + INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */ + INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */ + INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */ + INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */ + INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */ + INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */ + INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */ + INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */ + INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */ + INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */ + INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */ + INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */ + INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */ + INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */ + INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */ + INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */ + INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */ + INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */ + INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */ + INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */ + INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */ + INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */ + INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */ + INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */ + INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */ + INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */ + INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */ + INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */ + INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */ + INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */ + INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */ + INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */ + INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */ + INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */ + INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */ + INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */ + INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */ + INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */ + INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */ + INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */ + INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */ + INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */ + INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */ + INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */ + INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */ + INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */ + INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */ + INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */ + INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */ + INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */ + INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */ + INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */ + INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */ + INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */ + INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */ + INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */ + INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */ + INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */ + INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */ + INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */ + INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */ + INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */ + INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */ + INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */ + INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */ + INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */ + INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */ + INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */ + INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */ + INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */ + INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */ + INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */ + INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */ + INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */ + INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */ + INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */ + INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */ + INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */ + INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */ + INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */ + INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */ + INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */ + INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */ + INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */ + INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */ + INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */ + INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */ + INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */ + INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */ + INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */ + INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */ + INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */ + INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */ + INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */ + INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */ + INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */ + INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */ + INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */ + INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */ + INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */ + INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */ + INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */ + INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */ + INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */ + INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */ + INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */ + INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */ + INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */ + INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */ + INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */ + INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */ + INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */ + INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */ + INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */ + INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */ + INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */ + INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */ + INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */ + INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */ + INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */ + INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */ + }; + + struct { + /* PSR0-511 - Priority Select Registers */ + INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */ + INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */ + INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */ + INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */ + INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */ + INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */ + INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */ + INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */ + INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */ + INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */ + INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */ + INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */ + INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */ + INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */ + INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */ + INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */ + INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */ + INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */ + INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */ + INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */ + INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */ + INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */ + INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */ + INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */ + INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */ + INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */ + INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */ + INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */ + INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */ + INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */ + INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */ + INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */ + INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */ + INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */ + INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */ + INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */ + INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */ + INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */ + INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */ + INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */ + INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */ + INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */ + INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */ + INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */ + INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */ + INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */ + INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */ + INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */ + INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */ + INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */ + INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */ + INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */ + INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */ + INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */ + INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */ + INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */ + INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */ + INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */ + INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */ + INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */ + INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */ + INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */ + INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */ + INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */ + INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */ + INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */ + INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */ + INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */ + INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */ + INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */ + INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */ + INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */ + INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */ + INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */ + INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */ + INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */ + INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */ + INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */ + INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */ + INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */ + INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */ + INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */ + INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */ + INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */ + INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */ + INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */ + INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */ + INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */ + INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */ + INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */ + INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */ + INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */ + INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */ + INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */ + INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */ + INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */ + INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */ + INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */ + INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */ + INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */ + INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */ + INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */ + INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */ + INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */ + INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */ + INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */ + INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */ + INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */ + INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */ + INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */ + INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */ + INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */ + INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */ + INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */ + INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */ + INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */ + INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */ + INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */ + INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */ + INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */ + INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */ + INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */ + INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */ + INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */ + INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */ + INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */ + INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */ + INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */ + INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */ + INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */ + INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */ + INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */ + INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */ + INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */ + INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */ + INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */ + INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */ + INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */ + INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */ + INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */ + INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */ + INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */ + INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */ + INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */ + INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */ + INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */ + INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */ + INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */ + INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */ + INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */ + INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */ + INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */ + INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */ + INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */ + INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */ + INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */ + INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */ + INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */ + INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */ + INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */ + INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */ + INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */ + INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */ + INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */ + INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */ + INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */ + INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */ + INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */ + INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */ + INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */ + INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */ + INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */ + INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */ + INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */ + INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */ + INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */ + INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */ + INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */ + INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */ + INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */ + INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */ + INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */ + INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */ + INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */ + INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */ + INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */ + INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */ + INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */ + INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */ + INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */ + INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */ + INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */ + INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */ + INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */ + INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */ + INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */ + INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */ + INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */ + INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */ + INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */ + INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */ + INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */ + INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */ + INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */ + INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */ + INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */ + INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */ + INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */ + INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */ + INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */ + INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */ + INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */ + INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */ + INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */ + INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */ + INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */ + INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */ + INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */ + INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */ + INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */ + INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */ + INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */ + INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */ + INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */ + INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */ + INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */ + INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */ + INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */ + INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */ + INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */ + INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */ + INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */ + INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */ + INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */ + INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */ + INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */ + INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */ + INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */ + INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */ + INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */ + INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */ + INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */ + INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */ + INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */ + INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */ + INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */ + INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */ + INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */ + INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */ + INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */ + INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */ + INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */ + INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */ + INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */ + INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */ + INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */ + INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */ + INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */ + INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */ + INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */ + INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */ + INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */ + INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */ + INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */ + INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */ + INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */ + INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */ + INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */ + INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */ + INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */ + INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */ + INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */ + INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */ + INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */ + INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */ + INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */ + INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */ + INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */ + INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */ + INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */ + INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */ + INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */ + INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */ + INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */ + INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */ + INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */ + INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */ + INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */ + INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */ + INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */ + INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */ + INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */ + INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */ + INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */ + INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */ + INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */ + INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */ + INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */ + INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */ + INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */ + INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */ + INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */ + INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */ + INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */ + INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */ + INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */ + INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */ + INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */ + INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */ + INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */ + INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */ + INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */ + INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */ + INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */ + INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */ + INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */ + INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */ + INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */ + INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */ + INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */ + INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */ + INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */ + INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */ + INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */ + INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */ + INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */ + INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */ + INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */ + INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */ + INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */ + INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */ + INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */ + INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */ + INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */ + INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */ + INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */ + INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */ + INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */ + INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */ + INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */ + INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */ + INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */ + INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */ + INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */ + INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */ + INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */ + INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */ + INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */ + INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */ + INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */ + INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */ + INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */ + INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */ + INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */ + INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */ + INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */ + INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */ + INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */ + INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */ + INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */ + INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */ + INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */ + INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */ + INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */ + INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */ + INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */ + INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */ + INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */ + INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */ + INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */ + INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */ + INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */ + INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */ + INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */ + INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */ + INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */ + INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */ + INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */ + INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */ + INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */ + INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */ + INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */ + INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */ + INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */ + INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */ + INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */ + INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */ + INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */ + INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */ + INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */ + INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */ + INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */ + INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */ + INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */ + INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */ + INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */ + INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */ + INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */ + INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */ + INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */ + INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */ + INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */ + INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */ + INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */ + INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */ + INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */ + INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */ + INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */ + INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */ + INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */ + INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */ + INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */ + INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */ + INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */ + INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */ + INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */ + INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */ + INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */ + INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */ + INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */ + INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */ + INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */ + INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */ + INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */ + INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */ + INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */ + INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */ + INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */ + INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */ + INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */ + INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */ + INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */ + INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */ + INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */ + INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */ + INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */ + INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */ + INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */ + INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */ + INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */ + INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */ + INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */ + INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */ + INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */ + INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */ + INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */ + INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */ + INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */ + INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */ + INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */ + INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */ + INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */ + INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */ + INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */ + INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */ + INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */ + INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */ + INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */ + INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */ + INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */ + INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */ + INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */ + INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */ + INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */ + INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */ + INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */ + INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */ + INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */ + INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */ + INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */ + INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */ + INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */ + INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */ + INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */ + INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */ + INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */ + INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */ + INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */ + INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */ + INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */ + INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */ + INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */ + INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */ + INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */ + INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */ + INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */ + INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */ + INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */ + INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */ + INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */ + INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */ + INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */ + INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */ + INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */ + INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */ + INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */ + INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */ + INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */ + INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */ + INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */ + INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */ + INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */ + INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */ + INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */ + INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */ + INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */ + INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */ + INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */ + INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */ + INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */ + INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */ + INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */ + }; + + }; + } INTC_tag; + + +#define INTC (*(volatile INTC_tag *) 0xFFF48000UL) + + + +/****************************************************************/ +/* */ +/* Module: DSPI */ +/* */ +/****************************************************************/ + + typedef union DSPI_MCR_tag { /* MCR - Module Configuration Register */ + uint32_t R; + struct { + uint32_t MSTR:1; /* Master/Slave mode select */ + uint32_t CONT_SCKE:1; /* Continuous SCK Enable */ + uint32_t DCONF:2; /* DSPI Configuration */ + uint32_t FRZ:1; /* Freeze */ + uint32_t MTFE:1; /* Modified Timing Format Enable */ + uint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */ + uint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */ + uint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */ + uint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */ + uint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */ + uint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */ + uint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */ + uint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */ + uint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */ + uint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */ + uint32_t DOZE:1; /* Doze Enable */ + uint32_t MDIS:1; /* Module Disable */ + uint32_t DIS_TXF:1; /* Disable Transmit FIFO */ + uint32_t DIS_RXF:1; /* Disable Receive FIFO */ + uint32_t CLR_TXF:1; /* Clear TX FIFO */ + uint32_t CLR_RXF:1; /* Clear RX FIFO */ + uint32_t SMPL_PT:2; /* Sample Point */ + uint32_t:7; + uint32_t HALT:1; /* Halt */ + } B; + } DSPI_MCR_32B_tag; + + typedef union { /* TCR - Transfer Count Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t SPI_TCNT:16; /* SPI Transfer Counter */ +#else + uint32_t TCNT:16; /* deprecated name - please avoid */ +#endif + uint32_t:16; + } B; + } DSPI_TCR_32B_tag; + + + /* Register layout for all registers CTAR... */ + + typedef union DSPI_CTAR_tag { /* CTAR0-7 - Clock and Transfer Attribute Registers */ + uint32_t R; + struct { + uint32_t DBR:1; /* Double Baud Rate */ + uint32_t FMSZ:4; /* Frame Size */ + uint32_t CPOL:1; /* Clock Polarity */ + uint32_t CPHA:1; /* Clock Phase */ + uint32_t LSBFE:1; /* LSB First Enable */ + uint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */ + uint32_t PASC:2; /* After SCK Delay Prescaler */ + uint32_t PDT:2; /* Delay after Transfer Prescaler */ + uint32_t PBR:2; /* Baud Rate Prescaler */ + uint32_t CSSCK:4; /* PCS to SCK Delay Scaler */ + uint32_t ASC:4; /* After SCK Delay Scaler */ + uint32_t DT:4; /* Delay after Transfer Scaler */ + uint32_t BR:4; /* Baud Rate Scaler */ + } B; + } DSPI_CTAR_32B_tag; + + typedef union DSPI_SR_tag { /* SR - Status Register */ + uint32_t R; + struct { + uint32_t TCF:1; /* Transfer Complete Flag */ + uint32_t TXRXS:1; /* TX & RX Status */ + uint32_t:1; + uint32_t EOQF:1; /* End of queue Flag */ + uint32_t TFUF:1; /* Transmit FIFO Underflow Flag */ + uint32_t:1; + uint32_t TFFF:1; /* Transmit FIFO FIll Flag */ + uint32_t:5; + uint32_t RFOF:1; /* Receive FIFO Overflow Flag */ + uint32_t:1; + uint32_t RFDF:1; /* Receive FIFO Drain Flag */ + uint32_t:1; + uint32_t TXCTR:4; /* TX FIFO Counter */ + uint32_t TXNXTPTR:4; /* Transmit Next Pointer */ + uint32_t RXCTR:4; /* RX FIFO Counter */ + uint32_t POPNXTPTR:4; /* Pop Next Pointer */ + } B; + } DSPI_SR_32B_tag; + + typedef union DSPI_RSER_tag { /* RSER - DMA/Interrupt Request Register */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TCF_RE:1; /* Transmission Complete Request Enable */ +#else + uint32_t TCFRE:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t EOQF_RE:1; /* DSPI Finished Request Enable */ +#else + uint32_t EOQFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */ +#else + uint32_t TFUFRE:1; /* deprecated name - please avoid */ +#endif + uint32_t:1; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */ +#else + uint32_t TFFFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */ +#else + uint32_t TFFFDIRS:1; /* deprecated name - please avoid */ +#endif + uint32_t:4; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */ +#else + uint32_t RFOFRE:1; /* deprecated name - please avoid */ +#endif + uint32_t:1; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */ +#else + uint32_t RFDFRE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */ +#else + uint32_t RFDFDIRS:1; /* deprecated name - please avoid */ +#endif + uint32_t:16; + } B; + } DSPI_RSER_32B_tag; + + typedef union DSPI_PUSHR_tag { /* PUSHR - PUSH TX FIFO Register */ + uint32_t R; + struct { + uint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */ + uint32_t CTAS:3; /* Clock and Transfer Attributes Select */ + uint32_t EOQ:1; /* End of Queue */ + uint32_t CTCNT:1; /* Clear SPI_TCNT */ + uint32_t:2; + uint32_t PCS7:1; /* Peripheral Chip Select 7 */ + uint32_t PCS6:1; /* Peripheral Chip Select 6 */ + uint32_t PCS5:1; /* Peripheral Chip Select 5 */ + uint32_t PCS4:1; /* Peripheral Chip Select 4 */ + uint32_t PCS3:1; /* Peripheral Chip Select 3 */ + uint32_t PCS2:1; /* Peripheral Chip Select 2 */ + uint32_t PCS1:1; /* Peripheral Chip Select 1 */ + uint32_t PCS0:1; /* Peripheral Chip Select 0 */ + uint32_t TXDATA:16; /* Transmit Data */ + } B; + } DSPI_PUSHR_32B_tag; + + typedef union DSPI_POPR_tag { /* POPR - POP RX FIFO Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; /* Receive Data */ + } B; + } DSPI_POPR_32B_tag; + + + /* Register layout for all registers TXFR... */ + + typedef union { /* Transmit FIFO Registers */ + uint32_t R; + struct { +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t FIFO_TXCMD:16; /* Transmit Command */ +#else + uint32_t TXCMD:16; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t FIFO_TXDATA:16; /* Transmit Data */ +#else + uint32_t TXDATA:16; /* deprecated name - please avoid */ +#endif + } B; + } DSPI_TXFR_32B_tag; + + + /* Register layout for all registers RXFR... */ + + typedef union { /* Receive FIFO Registers */ + uint32_t R; + struct { + uint32_t:16; +#ifndef USE_FIELD_ALIASES_DSPI + uint32_t FIFO_RXDATA:16; /* Transmit Data */ +#else + uint32_t RXDATA:16; /* deprecated name - please avoid */ +#endif + } B; + } DSPI_RXFR_32B_tag; + + typedef union { /* DSICR - DSI Configuration Register */ + uint32_t R; + struct { + uint32_t MTOE:1; /* Multiple Transfer Operation Enable */ + uint32_t:1; + uint32_t MTOCNT:6; /* Multiple Transfer Operation Count */ + uint32_t:4; + uint32_t TXSS:1; /* Transmit Data Source Select */ + uint32_t TPOL:1; /* Trigger Polarity */ + uint32_t TRRE:1; /* Trigger Reception Enable */ + uint32_t CID:1; /* Change in Data Transfer Enable */ + uint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */ + uint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */ + uint32_t:4; + uint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */ + uint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */ + uint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */ + uint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */ + uint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */ + uint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */ + uint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */ + uint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */ + } B; + } DSPI_DSICR_32B_tag; + + typedef union { /* SDR - DSI Serialization Data Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SER_DATA:16; /* Serialized Data */ + } B; + } DSPI_SDR_32B_tag; + + typedef union { /* ASDR - DSI Alternate Serialization Data Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ASER_DATA:16; /* Alternate Serialized Data */ + } B; + } DSPI_ASDR_32B_tag; + + typedef union { /* COMPR - DSI Transmit Comparison Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t COMP_DATA:16; /* Compare Data */ + } B; + } DSPI_COMPR_32B_tag; + + typedef union { /* DDR - DSI Deserialization Data Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t DESER_DATA:16; /* Deserialized Data */ + } B; + } DSPI_DDR_32B_tag; + + typedef union { /* DSICR1 - DSI Configuration Register 1 */ + uint32_t R; + } DSPI_DSICR1_32B_tag; + + + + typedef struct DSPI_tag { /* start of DSPI_tag */ + /* MCR - Module Configuration Register */ + DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + int8_t DSPI_reserved_0004[4]; + /* TCR - Transfer Count Register */ + DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */ + union { + /* CTAR0-7 - Clock and Transfer Attribute Registers */ + DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */ + + struct { + /* CTAR0-7 - Clock and Transfer Attribute Registers */ + DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */ + DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */ + DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */ + DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */ + }; + + }; + /* SR - Status Register */ + DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */ + /* RSER - DMA/Interrupt Request Register */ + DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */ + /* PUSHR - PUSH TX FIFO Register */ + DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */ + /* POPR - POP RX FIFO Register */ + DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */ + union { + /* Transmit FIFO Registers */ + DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */ + + struct { + /* Transmit FIFO Registers */ + DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */ + DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */ + DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */ + }; + + }; + int8_t DSPI_reserved_0050_C[44]; + union { + /* Receive FIFO Registers */ + DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */ + + struct { + /* Receive FIFO Registers */ + DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */ + DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */ + DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */ + }; + + }; + int8_t DSPI_reserved_0090[44]; + /* DSICR - DSI Configuration Register */ + DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */ + /* SDR - DSI Serialization Data Register */ + DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */ + /* ASDR - DSI Alternate Serialization Data Register */ + DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */ + /* COMPR - DSI Transmit Comparison Register */ + DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */ + /* DDR - DSI Deserialization Data Register */ + DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */ + /* DSICR1 - DSI Configuration Register 1 */ + DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */ + } DSPI_tag; + + +#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL) +#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL) + + + +/****************************************************************/ +/* */ +/* Module: FLEXCAN */ +/* */ +/****************************************************************/ + + typedef union { /* MCR - Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; /* Module Disable */ + uint32_t FRZ:1; /* Freeze Enable */ + uint32_t FEN:1; /* FIFO Enable */ + uint32_t HALT:1; /* Halt Flexcan */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t NOT_RDY:1; /* Flexcan Not Ready */ +#else + uint32_t NOTRDY:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */ +#else + uint32_t WAKMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t SOFT_RST:1; /* Soft Reset */ +#else + uint32_t SOFTRST:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */ +#else + uint32_t FRZACK:1; /* deprecated name - please avoid */ +#endif + uint32_t SUPV:1; /* Supervisor Mode */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t SLF_WAK:1; /* Self Wake Up */ +#else + uint32_t SLFWAK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WRN_EN:1; /* Warning Interrupt Enable */ +#else + uint32_t WRNEN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */ +#else + uint32_t LPMACK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WAK_SRC:1; /* Wake Up Source */ +#else + uint32_t WAKSRC:1; /* deprecated name - please avoid */ +#endif + uint32_t DOZE:1; /* Doze Mode Enable */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t SRX_DIS:1; /* Self Reception Disable */ +#else + uint32_t SRXDIS:1; /* deprecated name - please avoid */ +#endif + uint32_t BCC:1; /* Backwards Compatibility Configuration */ + uint32_t:2; + uint32_t LPRIO_EN:1; /* Local Priority Enable */ + uint32_t AEN:1; /* Abort Enable */ + uint32_t:2; + uint32_t IDAM:2; /* ID Acceptance Mode */ + uint32_t:2; + uint32_t MAXMB:6; /* Maximum Number of Message Buffers */ + } B; + } FLEXCAN_MCR_32B_tag; + + typedef union { /* CTRL - Control Register */ + uint32_t R; + struct { + uint32_t PRESDIV:8; /* Prescaler Divsion Factor */ + uint32_t RJW:2; /* Resync Jump Width */ + uint32_t PSEG1:3; /* Phase Segment 1 */ + uint32_t PSEG2:3; /* Phase Segment 2 */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BOFF_MSK:1; /* Bus Off Mask */ +#else + uint32_t BOFFMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t ERR_MSK:1; /* Error Mask */ +#else + uint32_t ERRMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t CLK_SRC:1; /* CAN Engine Clock Source */ +#else + uint32_t CLKSRC:1; /* deprecated name - please avoid */ +#endif + uint32_t LPB:1; /* Loop Back */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */ +#else + uint32_t TWRNMSK:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */ +#else + uint32_t RWRNMSK:1; /* deprecated name - please avoid */ +#endif + uint32_t:2; + uint32_t SMP:1; /* Sampling Mode */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BOFF_REC:1; /* Bus Off Recovery Mode */ +#else + uint32_t BOFFREC:1; /* deprecated name - please avoid */ +#endif + uint32_t TSYN:1; /* Timer Sync Mode */ + uint32_t LBUF:1; /* Lowest Buffer Transmitted First */ + uint32_t LOM:1; /* Listen-Only Mode */ + uint32_t PROPSEG:3; /* Propagation Segment */ + } B; + } FLEXCAN_CTRL_32B_tag; + + typedef union { /* TIMER - Free Running Timer */ + uint32_t R; + } FLEXCAN_TIMER_32B_tag; + + typedef union { /* RXGMASK - Rx Global Mask Register */ + uint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + uint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RXGMASK_32B_tag; + + typedef union { /* RX14MASK - Rx 14 Mask Register */ + uint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + uint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RX14MASK_32B_tag; + + typedef union { /* RX15MASK - Rx 15 Mask Register */ + uint32_t R; +#ifndef USE_FIELD_ALIASES_FLEXCAN + struct { + uint32_t MI:32; /* deprecated field -- do not use */ + } B; +#endif + } FLEXCAN_RX15MASK_32B_tag; + + typedef union { /* ECR - Error Counter Register */ + uint32_t R; + struct { + uint32_t:16; +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */ +#else + uint32_t RXECNT:8; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */ +#else + uint32_t TXECNT:8; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_ECR_32B_tag; + + typedef union { /* ESR - Error and Status Register */ + uint32_t R; + struct { + uint32_t:14; +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */ +#else + uint32_t TWRNINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */ +#else + uint32_t RWRNINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BIT1_ERR:1; /* Bit 1 Error */ +#else + uint32_t BIT1ERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BIT0_ERR:1; /* Bit 0 Error */ +#else + uint32_t BIT0ERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t ACK_ERR:1; /* Acknowledge Error */ +#else + uint32_t ACKERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */ +#else + uint32_t CRCERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t FRM_ERR:1; /* Form Error */ +#else + uint32_t FRMERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t STF_ERR:1; /* Stuffing Error */ +#else + uint32_t STFERR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t TX_WRN:1; /* Tx Error Counter */ +#else + uint32_t TXWRN:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t RX_WRN:1; /* Rx Error Counter */ +#else + uint32_t RXWRN:1; /* deprecated name - please avoid */ +#endif + uint32_t IDLE:1; /* CAN bus Idle State */ + uint32_t TXRX:1; /* Current Flexcan Status */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t FLT_CONF:2; /* Fault Confinement State */ +#else + uint32_t FLTCONF:2; /* deprecated name - please avoid */ +#endif + uint32_t:1; +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BOFF_INT:1; /* Bus Off Interrupt */ +#else + uint32_t BOFFINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t ERR_INT:1; /* Error Interrupt */ +#else + uint32_t ERRINT:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t WAK_INT:1; /* Wake-Up Interrupt */ +#else + uint32_t WAKINT:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_ESR_32B_tag; + + typedef union { /* IMASK2 - Interrupt Masks 2 Register */ + uint32_t R; + struct { + uint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */ + uint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */ + uint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */ + uint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */ + uint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */ + uint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */ + uint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */ + uint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */ + uint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */ + uint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */ + uint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */ + uint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */ + uint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */ + uint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */ + uint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */ + uint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */ + uint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */ + uint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */ + uint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */ + uint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */ + uint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */ + uint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */ + uint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */ + uint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */ + uint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */ + uint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */ + uint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */ + uint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */ + uint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */ + uint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */ + uint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */ + uint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */ + } B; + } FLEXCAN_IMASK2_32B_tag; + + typedef union { /* IMASK1 - Interrupt Masks 1 Register */ + uint32_t R; + struct { + uint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */ + uint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */ + uint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */ + uint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */ + uint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */ + uint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */ + uint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */ + uint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */ + uint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */ + uint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */ + uint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */ + uint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */ + uint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */ + uint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */ + uint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */ + uint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */ + uint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */ + uint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */ + uint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */ + uint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */ + uint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */ + uint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */ +#else + uint32_t BUF09M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */ +#else + uint32_t BUF08M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */ +#else + uint32_t BUF07M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */ +#else + uint32_t BUF06M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */ +#else + uint32_t BUF05M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */ +#else + uint32_t BUF04M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */ +#else + uint32_t BUF03M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */ +#else + uint32_t BUF02M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */ +#else + uint32_t BUF01M:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */ +#else + uint32_t BUF00M:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_IMASK1_32B_tag; + + typedef union { /* IFLAG2 - Interrupt Flags 2 Register */ + uint32_t R; + struct { + uint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */ + uint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */ + uint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */ + uint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */ + uint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */ + uint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */ + uint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */ + uint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */ + uint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */ + uint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */ + uint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */ + uint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */ + uint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */ + uint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */ + uint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */ + uint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */ + uint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */ + uint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */ + uint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */ + uint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */ + uint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */ + uint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */ + uint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */ + uint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */ + uint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */ + uint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */ + uint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */ + uint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */ + uint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */ + uint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */ + uint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */ + uint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */ + } B; + } FLEXCAN_IFLAG2_32B_tag; + + typedef union { /* IFLAG1 - Interrupt Flags 1 Register */ + uint32_t R; + struct { + uint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */ + uint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */ + uint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */ + uint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */ + uint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */ + uint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */ + uint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */ + uint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */ + uint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */ + uint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */ + uint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */ + uint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */ + uint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */ + uint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */ + uint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */ + uint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */ + uint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */ + uint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */ + uint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */ + uint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */ + uint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */ + uint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */ +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */ +#else + uint32_t BUF09I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */ +#else + uint32_t BUF08I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */ +#else + uint32_t BUF07I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */ +#else + uint32_t BUF06I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */ +#else + uint32_t BUF05I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */ +#else + uint32_t BUF04I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */ +#else + uint32_t BUF03I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */ +#else + uint32_t BUF02I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */ +#else + uint32_t BUF01I:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FLEXCAN + uint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */ +#else + uint32_t BUF00I:1; /* deprecated name - please avoid */ +#endif + } B; + } FLEXCAN_IFLAG1_32B_tag; + + + /* Register layout for all registers MSG_CS... */ + + typedef union { /* Message Buffer Control and Status */ + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; /* Message Buffer Code */ + uint32_t:1; + uint32_t SRR:1; /* Substitute Remote Request */ + uint32_t IDE:1; /* ID Extended Bit */ + uint32_t RTR:1; /* Remote Transmission Request */ + uint32_t LENGTH:4; /* Length of Data in Bytes */ + uint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */ + } B; + } FLEXCAN_MSG_CS_32B_tag; + + + /* Register layout for all registers MSG_ID... */ + + typedef union { /* Message Buffer Identifier Field */ + uint32_t R; + struct { + uint32_t PRIO:3; /* Local Priority */ + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } FLEXCAN_MSG_ID_32B_tag; + + + /* Register layout for all registers MSG_BYTE0_3... */ + + typedef union { /* Message Buffer Data Register */ + uint32_t R; + uint8_t BYTE[4]; /* individual bytes can be accessed */ + uint32_t WORD; /* individual words can be accessed */ + } FLEXCAN_MSG_DATA_32B_tag; + + typedef union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } FLEXCAN_MSG_DATA2_32B_tag; + + /* Register layout for all registers MSG_BYTE4_7 matches xxx */ + + + /* Register layout for all registers RXIMR... */ + + typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + uint32_t R; + } FLEXCAN_RXIMR_32B_tag; + + + typedef struct FLEXCAN_MB_struct_tag { + + union { + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */ + FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */ + }; + union { + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */ + FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */ + }; + union { /* Message Buffer Data Register */ + + struct { + FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */ + }; + + FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */ + + }; + + } FLEXCAN_MB_tag; + + + typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */ + /* MCR - Module Configuration Register */ + FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */ + union { + /* CTRL - Control Register */ + FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */ + + FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */ + + }; + /* TIMER - Free Running Timer */ + FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */ + int8_t FLEXCAN_reserved_000C[4]; + /* RXGMASK - Rx Global Mask Register */ + FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */ + /* RX14MASK - Rx 14 Mask Register */ + FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */ + /* RX15MASK - Rx 15 Mask Register */ + FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */ + /* ECR - Error Counter Register */ + FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */ + /* ESR - Error and Status Register */ + FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */ + union { + FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */ + + /* IMASK2 - Interrupt Masks 2 Register */ + FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */ + + }; + union { + FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */ + + /* IMASK1 - Interrupt Masks 1 Register */ + FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */ + + }; + union { + FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */ + + /* IFLAG2 - Interrupt Flags 2 Register */ + FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */ + + }; + union { + FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */ + + /* IFLAG1 - Interrupt Flags 1 Register */ + FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */ + + }; + int8_t FLEXCAN_reserved_0034_C[76]; + union { + /* Register set MB */ + FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */ + + /* Alias name for MB */ + FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */ + + struct { + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */ + /* Message Buffer Control and Status */ + FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */ + /* Message Buffer Identifier Field */ + FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */ + /* Message Buffer Data Register */ + FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */ + }; + + }; + int8_t FLEXCAN_reserved_0480_C[1024]; + union { + /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */ + + struct { + /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */ + FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */ + FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */ + }; + + }; + } FLEXCAN_tag; + + +#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL) +#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL) + + + +/****************************************************************/ +/* */ +/* Module: DMA_CH_MUX */ +/* */ +/****************************************************************/ + + + /* Register layout for all registers CHCONFIG... */ + + typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */ + uint8_t R; + struct { + uint8_t ENBL:1; /* DMA Channel Enable */ + uint8_t TRIG:1; /* DMA Channel Trigger Enable */ + uint8_t SOURCE:6; /* DMA Channel Source */ + } B; + } DMA_CH_MUX_CHCONFIG_8B_tag; + + + + typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */ + union { + /* CHCONFIG[0-15] - Channel Configuration Registers */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */ + + struct { + /* CHCONFIG[0-15] - Channel Configuration Registers */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */ + DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */ + }; + + }; + } DMA_CH_MUX_tag; + + +#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL) + + + +/****************************************************************/ +/* */ +/* Module: FR */ +/* */ +/****************************************************************/ + + typedef union { /* Module Version Number */ + uint16_t R; + struct { + uint16_t CHIVER:8; /* VERSION NUMBER OF CHI */ + uint16_t PEVER:8; /* VERSION NUMBER OF PE */ + } B; + } FR_MVR_16B_tag; + + typedef union { /* Module Configuration Register */ + uint16_t R; + struct { + uint16_t MEN:1; /* Module Enable */ + uint16_t SBFF:1; /* System Bus Failure Freeze */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t SCM:1; /* single channel device mode */ +#else + uint16_t SCMD:1; /* deprecated name - please avoid */ +#endif + uint16_t CHB:1; /* Channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* Sync. frame filter Enable */ + uint16_t ECCE:1; /* ECC Functionlity Enable */ + uint16_t TMODER:1; /* Functional Test mode */ + uint16_t FUM:1; /* FIFO Update Mode */ + uint16_t FAM:1; /* FIFO Address Mode */ + uint16_t:1; + uint16_t CLKSEL:1; /* Protocol Engine clock source select */ + uint16_t BITRATE:3; /* Bus bit rate */ + uint16_t:1; + } B; + } FR_MCR_16B_tag; + + typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */ + uint16_t R; + struct { + uint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */ + } B; + } FR_SYMBADHR_16B_tag; + + typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */ + uint16_t R; + struct { + uint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */ + uint16_t:4; + } B; + } FR_SYMBADLR_16B_tag; + + typedef union { /* STROBE SIGNAL CONTROL REGISTER */ + uint16_t R; + struct { + uint16_t WMD:1; /* DEFINES WRITE MODE OF REG */ + uint16_t:3; + uint16_t SEL:4; /* STROBE SIGNSL SELECT */ + uint16_t:3; + uint16_t ENB:1; /* STROBE SIGNAL ENABLE */ + uint16_t:2; + uint16_t STBPSEL:2; /* STROBE PORT SELECT */ + } B; + } FR_STBSCR_16B_tag; + + typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */ + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */ + } B; + } FR_MBDSR_16B_tag; + + typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ + uint16_t R; + struct { + uint16_t:2; + uint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */ + uint16_t:2; + uint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */ + } B; + } FR_MBSSUTR_16B_tag; + + typedef union { /* PE DRAM ACCESS REGISTER */ + uint16_t R; + struct { + uint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */ + uint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */ + uint16_t DAD:1; /* PE DRAM ACCESS DONE */ + } B; + } FR_PEDRAR_16B_tag; + + typedef union { /* PE DRAM DATA REGISTER */ + uint16_t R; + struct { + uint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */ + } B; + } FR_PEDRDR_16B_tag; + + typedef union { /* PROTOCOL OPERATION CONTROL REG */ + uint16_t R; + struct { + uint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */ + uint16_t:3; + uint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */ + uint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */ + uint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */ + uint16_t:3; + uint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */ + } B; + } FR_POCR_16B_tag; + + typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */ + uint16_t R; + struct { + uint16_t MIF:1; /* MODULE INTERRUPT FLAG */ + uint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */ + uint16_t CHIF:1; /* CHI INTERRUPT FLAG */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */ +#else + uint16_t WKUPIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */ +#else + uint16_t FNEBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */ +#else + uint16_t FNEAIF:1; /* deprecated name - please avoid */ +#endif + uint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */ + uint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */ + uint16_t MIE:1; /* MODULE INTERRUPT ENABLE */ + uint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */ + uint16_t CHIE:1; /* CHI INTERRUPT ENABLE */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */ +#else + uint16_t WKUPIE:1; /* deprecated name - please avoid */ +#endif + uint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */ + uint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */ + uint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */ + uint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */ + } B; + } FR_GIFER_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */ +#else + uint16_t FATLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */ +#else + uint16_t INTLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */ +#else + uint16_t ILCFIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */ +#else + uint16_t CSAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */ +#else + uint16_t MRCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */ +#else + uint16_t MOCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */ +#else + uint16_t CCLIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */ +#else + uint16_t MXSIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */ +#else + uint16_t MTXIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */ +#else + uint16_t LTXBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */ +#else + uint16_t LTXAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */ +#else + uint16_t TBVBIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */ +#else + uint16_t TBVAIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */ +#else + uint16_t TI2IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */ +#else + uint16_t TI1IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */ +#else + uint16_t CYSIF:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_PIFR0_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */ +#else + uint16_t EMCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */ +#else + uint16_t IPCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */ +#else + uint16_t PECFIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */ +#else + uint16_t PSCIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI3IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI2IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI1IF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */ +#else + uint16_t SSI0IF:1; /* deprecated name - please avoid */ +#endif + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */ +#else + uint16_t EVTIF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */ +#else + uint16_t ODTIF:1; /* deprecated name - please avoid */ +#endif + uint16_t:4; + } B; + } FR_PIFR1_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */ +#else + uint16_t FATLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */ +#else + uint16_t INTLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */ +#else + uint16_t ILCFIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */ +#else + uint16_t CSAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */ +#else + uint16_t MRCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */ +#else + uint16_t MOCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */ +#else + uint16_t CCLIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */ +#else + uint16_t MXSIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */ +#else + uint16_t MTXIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */ +#else + uint16_t LTXBIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */ +#else + uint16_t LTXAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */ +#else + uint16_t TBVBIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */ +#else + uint16_t TBVAIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */ +#else + uint16_t TI2IE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */ +#else + uint16_t TI1IE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */ +#else + uint16_t CYSIE:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_PIER0_16B_tag; + + typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */ +#else + uint16_t EMCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */ +#else + uint16_t IPCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */ +#else + uint16_t PECFIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */ +#else + uint16_t PSCIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */ +#else + uint16_t SSI3IE:1; + uint16_t SSI2IE:1; + uint16_t SSI1IE:1; + uint16_t SSI0IE:1; +#endif + + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */ +#else + uint16_t EVTIE:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */ +#else + uint16_t ODTIE:1; /* deprecated name - please avoid */ +#endif + uint16_t:4; + } B; + } FR_PIER1_16B_tag; + + typedef union { /* CHI ERROR FLAG REGISTER */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */ +#else + uint16_t FRLBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */ +#else + uint16_t FRLAEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */ +#else + uint16_t PCMIEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */ +#else + uint16_t FOVBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */ +#else + uint16_t FOVAEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */ +#else + uint16_t MSBEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */ +#else + uint16_t MBUEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t LCK_EF:1; /* LOCK ERROR FLAG */ +#else + uint16_t LCKEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */ +#else + uint16_t DBLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */ +#else + uint16_t SBCFEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FID_EF:1; /* FRAME ID ERROR FLAG */ +#else + uint16_t FIDEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */ +#else + uint16_t DPLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */ +#else + uint16_t SPLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */ +#else + uint16_t NMLEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */ +#else + uint16_t NMFEF:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */ +#else + uint16_t ILSAEF:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_CHIERFR_16B_tag; + + typedef union { /* Message Buffer Interrupt Vector Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */ + uint16_t:2; + uint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */ + } B; + } FR_MBIVEC_16B_tag; + + typedef union { /* Channel A Status Error Counter Register */ + uint16_t R; + struct { + uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ + } B; + } FR_CASERCR_16B_tag; + + typedef union { /* Channel B Status Error Counter Register */ + uint16_t R; + struct { + uint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */ + } B; + } FR_CBSERCR_16B_tag; + + typedef union { /* Protocol Status Register 0 */ + uint16_t R; + struct { + uint16_t ERRMODE:2; /* Error Mode */ + uint16_t SLOTMODE:2; /* Slot Mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* Protocol State */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t STARTUPSTATE:4; /* Startup State */ +#else + uint16_t SUBSTATE:4; /* deprecated name - please avoid */ +#endif + uint16_t WAKEUPSTATE:4; /* Wakeup Status */ + } B; + } FR_PSR0_16B_tag; + + typedef union { /* Protocol Status Register 1 */ + uint16_t R; + struct { + uint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */ + uint16_t CSP:1; /* Leading Coldstart Path */ + uint16_t:1; + uint16_t REMCSAT:5; /* Remaining Coldstart Attempts */ + uint16_t CPN:1; /* Leading Coldstart Path Noise */ + uint16_t HHR:1; /* Host Halt Request Pending */ + uint16_t FRZ:1; /* Freeze Occurred */ + uint16_t APTAC:5; /* Allow Passive to Active Counter */ + } B; + } FR_PSR1_16B_tag; + + typedef union { /* Protocol Status Register 2 */ + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT Boundary Violation on Channel B */ + uint16_t NSEB:1; /* NIT Syntax Error on Channel B */ + uint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */ +#else + uint16_t SBVB:1; /* deprecated name - please avoid */ +#endif + uint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */ + uint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */ + uint16_t NBVA:1; /* NIT Boundary Violation on Channel A */ + uint16_t NSEA:1; /* NIT Syntax Error on Channel A */ + uint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */ + uint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */ + uint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */ + uint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */ + uint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */ + } B; + } FR_PSR2_16B_tag; + + typedef union { /* Protocol Status Register 3 */ + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* Wakeup Symbol Received on Channel B */ + uint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */ + uint16_t AACB:1; /* Aggregated Additional Communication on Channel B */ + uint16_t ACEB:1; /* Aggregated Content Error on Channel B */ + uint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */ + uint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */ + uint16_t:2; + uint16_t WUA:1; /* Wakeup Symbol Received on Channel A */ + uint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */ + uint16_t AACA:1; /* Aggregated Additional Communication on Channel A */ + uint16_t ACEA:1; /* Aggregated Content Error on Channel A */ + uint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */ + uint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */ + } B; + } FR_PSR3_16B_tag; + + typedef union { /* Macrotick Counter Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t MTCT:14; /* Macrotick Counter */ + } B; + } FR_MTCTR_16B_tag; + + typedef union { /* Cycle Counter Register */ + uint16_t R; + struct { + uint16_t:10; + uint16_t CYCCNT:6; /* Cycle Counter */ + } B; + } FR_CYCTR_16B_tag; + + typedef union { /* Slot Counter Channel A Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */ + } B; + } FR_SLTCTAR_16B_tag; + + typedef union { /* Slot Counter Channel B Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */ + } B; + } FR_SLTCTBR_16B_tag; + + typedef union { /* Rate Correction Value Register */ + uint16_t R; + struct { + uint16_t RATECORR:16; /* Rate Correction Value */ + } B; + } FR_RTCORVR_16B_tag; + + typedef union { /* Offset Correction Value Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t OFFSETCORR:10; /* Offset Correction Value */ + } B; + } FR_OFCORVR_16B_tag; + + typedef union { /* Combined Interrupt Flag Register */ + uint16_t R; + struct { + uint16_t:8; +#ifndef USE_FIELD_ALIASES_FR + uint16_t MIF:1; /* Module Interrupt Flag */ +#else + uint16_t MIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t PRIF:1; /* Protocol Interrupt Flag */ +#else + uint16_t PRIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CHIF:1; /* CHI Interrupt Flag */ +#else + uint16_t CHIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t WUPIF:1; /* Wakeup Interrupt Flag */ +#else + uint16_t WUPIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */ +#else + uint16_t FNEBIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */ +#else + uint16_t FNEAIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */ +#else + uint16_t RBIFR:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */ +#else + uint16_t TBIFR:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_CIFR_16B_tag; + + typedef union { /* System Memory Access Time-Out Register */ + uint16_t R; + struct { + uint16_t:8; + uint16_t TIMEOUT:8; /* Time-Out */ + } B; + } FR_SYMATOR_16B_tag; + + typedef union { /* Sync Frame Counter Register */ + uint16_t R; + struct { + uint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */ + uint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */ + uint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */ + uint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */ + } B; + } FR_SFCNTR_16B_tag; + + typedef union { /* Sync Frame Table Offset Register */ + uint16_t R; + struct { + uint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */ + uint16_t:1; + } B; + } FR_SFTOR_16B_tag; + + typedef union { /* Sync Frame Table Configuration, Control, Status Register */ + uint16_t R; + struct { + uint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */ + uint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */ + uint16_t CYCNUM:6; /* Cycle Number */ + uint16_t ELKS:1; /* Even Cycle Tables Lock Status */ + uint16_t OLKS:1; /* Odd Cycle Tables Lock Status */ + uint16_t EVAL:1; /* Even Cycle Tables Valid */ + uint16_t OVAL:1; /* Odd Cycle Tables Valid */ + uint16_t:1; + uint16_t OPT:1; /* One Pair Trigger */ + uint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t SIVEN:1; /* Sync Frame ID Table Enable */ +#else + uint16_t SIDEN:1; /* deprecated name - please avoid */ +#endif + } B; + } FR_SFTCCSR_16B_tag; + + typedef union { /* Sync Frame ID Rejection Filter */ + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* Sync Frame Rejection ID */ + } B; + } FR_SFIDRFR_16B_tag; + + typedef union { /* Sync Frame ID Acceptance Filter Value Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t FVAL:10; /* Filter Value */ + } B; + } FR_SFIDAFVR_16B_tag; + + typedef union { /* Sync Frame ID Acceptance Filter Mask Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t FMSK:10; /* Filter Mask */ + } B; + } FR_SFIDAFMR_16B_tag; + + typedef union { /* Network Management Vector Register0 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR0_16B_tag; + + typedef union { /* Network Management Vector Register1 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR1_16B_tag; + + typedef union { /* Network Management Vector Register2 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR2_16B_tag; + + typedef union { /* Network Management Vector Register3 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR3_16B_tag; + + typedef union { /* Network Management Vector Register4 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR4_16B_tag; + + typedef union { /* Network Management Vector Register5 */ + uint16_t R; + struct { + uint16_t NMVP_15_8:8; /* Network Management Vector Part */ + uint16_t NMVP_7_0:8; /* Network Management Vector Part */ + } B; + } FR_NMVR5_16B_tag; + + typedef union { /* Network Management Vector Length Register */ + uint16_t R; + struct { + uint16_t:12; + uint16_t NMVL:4; /* Network Management Vector Length */ + } B; + } FR_NMVLR_16B_tag; + + typedef union { /* Timer Configuration and Control Register */ + uint16_t R; + struct { + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T2_CFG:1; /* Timer T2 Configuration */ +#else + uint16_t T2CFG:1; /* Timer T2 Configuration */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t T2_REP:1; /* Timer T2 Repetitive Mode */ +#else + uint16_t T2REP:1; /* Timer T2 Configuration */ +#endif + uint16_t:1; + uint16_t T2SP:1; /* Timer T2 Stop */ + uint16_t T2TR:1; /* Timer T2 Trigger */ + uint16_t T2ST:1; /* Timer T2 State */ + uint16_t:3; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T1_REP:1; /* Timer T1 Repetitive Mode */ +#else + uint16_t T1REP:1; +#endif + uint16_t:1; + uint16_t T1SP:1; /* Timer T1 Stop */ + uint16_t T1TR:1; /* Timer T1 Trigger */ + uint16_t T1ST:1; /* Timer T1 State */ + } B; + } FR_TICCR_16B_tag; + + typedef union { /* Timer 1 Cycle Set Register */ + uint16_t R; + struct { + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */ +#else + uint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */ +#endif + uint16_t:2; +#ifndef USE_FIELD_ALIASES_FR + uint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */ +#else + uint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */ +#endif + } B; + } FR_TI1CYSR_16B_tag; + + typedef union { /* Timer 1 Macrotick Offset Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */ + } B; + } FR_TI1MTOR_16B_tag; + + typedef union { /* Timer 2 Configuration Register 0 */ + uint16_t R; + struct { + uint16_t:2; + uint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */ + uint16_t:2; + uint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */ + } B; + } FR_TI2CR0_16B_tag; + + typedef union { /* Timer 2 Configuration Register 1 */ + uint16_t R; + struct { + uint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */ + } B; + } FR_TI2CR1_16B_tag; + + typedef union { /* Slot Status Selection Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t:1; + uint16_t SEL:2; /* Selector */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* Slot Number */ + } B; + } FR_SSSR_16B_tag; + + typedef union { /* Slot Status Counter Condition Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t:1; + uint16_t SEL:2; /* Selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* Counter Configuration */ + uint16_t MCY:1; /* Multi Cycle Selection */ + uint16_t VFR:1; /* Valid Frame Restriction */ + uint16_t SYF:1; /* Sync Frame Restriction */ + uint16_t NUF:1; /* Null Frame Restriction */ + uint16_t SUF:1; /* Startup Frame Restriction */ + uint16_t STATUSMASK:4; /* Slot Status Mask */ + } B; + } FR_SSCCR_16B_tag; + + typedef union { /* Slot Status Register0 */ + uint16_t R; + struct { + uint16_t VFB:1; /* Valid Frame on Channel B */ + uint16_t SYB:1; /* Sync Frame Indicator Channel B */ + uint16_t NFB:1; /* Null Frame Indicator Channel B */ + uint16_t SUB:1; /* Startup Frame Indicator Channel B */ + uint16_t SEB:1; /* Syntax Error on Channel B */ + uint16_t CEB:1; /* Content Error on Channel B */ + uint16_t BVB:1; /* Boundary Violation on Channel B */ + uint16_t TCB:1; /* Transmission Conflict on Channel B */ + uint16_t VFA:1; /* Valid Frame on Channel A */ + uint16_t SYA:1; /* Sync Frame Indicator Channel A */ + uint16_t NFA:1; /* Null Frame Indicator Channel A */ + uint16_t SUA:1; /* Startup Frame Indicator Channel A */ + uint16_t SEA:1; /* Syntax Error on Channel A */ + uint16_t CEA:1; /* Content Error on Channel A */ + uint16_t BVA:1; /* Boundary Violation on Channel A */ + uint16_t TCA:1; /* Transmission Conflict on Channel A */ + } B; + } FR_SSR_16B_tag; + + + + typedef union { /* Slot Status Counter Register0 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR0_16B_tag; + + typedef union { /* Slot Status Counter Register1 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR1_16B_tag; + + typedef union { /* Slot Status Counter Register2 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR2_16B_tag; + + typedef union { /* Slot Status Counter Register3 */ + uint16_t R; + struct { + uint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */ + } B; + } FR_SSCR3_16B_tag; + + typedef union { /* MTS A Configuration Register */ + uint16_t R; + struct { + uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ + } B; + } FR_MTSACFR_16B_tag; + + typedef union { /* MTS B Configuration Register */ + uint16_t R; + struct { + uint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* Cycle Counter Mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* Cycle Counter Value */ + } B; + } FR_MTSBCFR_16B_tag; + + typedef union { /* Receive Shadow Buffer Index Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t:1; + uint16_t SEL:2; /* Selector */ + uint16_t:5; + uint16_t RSBIDX:7; /* Receive Shadow Buffer Index */ + } B; + } FR_RSBIR_16B_tag; + + typedef union { /* Receive FIFO Watermark and Selection Register */ + uint16_t R; + struct { + uint16_t WM:8; /* Watermark Value */ + uint16_t:7; + uint16_t SEL:1; /* Select */ + } B; + } FR_RFWMSR_16B_tag; + + typedef union { /* Receive FIFO Start Index Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t SIDX:10; /* Start Index */ + } B; + } FR_RF_RFSIR_16B_tag; + + typedef union { /* Receive FIFO Depth and Size Register */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t FIFO_DEPTH:8; /* FIFO Depth */ +#else + uint16_t FIFODEPTH:8; /* deprecated name - please avoid */ +#endif + uint16_t:1; +#ifndef USE_FIELD_ALIASES_FR + uint16_t ENTRY_SIZE:7; /* Entry Size */ +#else + uint16_t ENTRYSIZE:7; /* deprecated name - please avoid */ +#endif + } B; + } FR_RFDSR_16B_tag; + + typedef union { /* Receive FIFO A Read Index Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t RDIDX:10; /* Read Index */ + } B; + } FR_RFARIR_16B_tag; + + typedef union { /* Receive FIFO B Read Index Register */ + uint16_t R; + struct { + uint16_t:6; + uint16_t RDIDX:10; /* Read Index */ + } B; + } FR_RFBRIR_16B_tag; + + typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */ + uint16_t R; + struct { + uint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */ + } B; + } FR_RFMIDAFVR_16B_tag; + + typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */ + uint16_t R; + struct { + uint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */ + } B; + } FR_RFMIDAFMR_16B_tag; + + typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */ + } B; + } FR_RFFIDRFVR_16B_tag; + + typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */ + } B; + } FR_RFFIDRFMR_16B_tag; + + typedef union { /* Receive FIFO Range Filter Configuration Register */ + uint16_t R; + struct { + uint16_t WMD:1; /* Write Mode */ + uint16_t IBD:1; /* Interval Boundary */ + uint16_t SEL:2; /* Filter Selector */ + uint16_t:1; + uint16_t SID:11; /* Slot ID */ + } B; + } FR_RFRFCFR_16B_tag; + + typedef union { /* Receive FIFO Range Filter Control Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* Range Filter 3 Mode */ + uint16_t F2MD:1; /* Range Filter 2 Mode */ + uint16_t F1MD:1; /* Range Filter 1 Mode */ + uint16_t F0MD:1; /* Range Filter 0 Mode */ + uint16_t:4; + uint16_t F3EN:1; /* Range Filter 3 Enable */ + uint16_t F2EN:1; /* Range Filter 2 Enable */ + uint16_t F1EN:1; /* Range Filter 1 Enable */ + uint16_t F0EN:1; /* Range Filter 0 Enable */ + } B; + } FR_RFRFCTR_16B_tag; + + typedef union { /* Last Dynamic Transmit Slot Channel A Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */ + } B; + } FR_LDTXSLAR_16B_tag; + + typedef union { /* Last Dynamic Transmit Slot Channel B Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */ + } B; + } FR_LDTXSLBR_16B_tag; + + typedef union { /* Protocol Configuration Register 0 */ + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */ + uint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */ + } B; + } FR_PCR0_16B_tag; + + typedef union { /* Protocol Configuration Register 1 */ + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */ + } B; + } FR_PCR1_16B_tag; + + typedef union { /* Protocol Configuration Register 2 */ + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */ + uint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */ + } B; + } FR_PCR2_16B_tag; + + typedef union { /* Protocol Configuration Register 3 */ + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */ +#else + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */ +#endif + uint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */ + } B; + } FR_PCR3_16B_tag; + + typedef union { /* Protocol Configuration Register 4 */ + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */ + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */ + } B; + } FR_PCR4_16B_tag; + + typedef union { /* Protocol Configuration Register 5 */ + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */ + uint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */ + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */ + } B; + } FR_PCR5_16B_tag; + + typedef union { /* Protocol Configuration Register 6 */ + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */ + uint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */ + } B; + } FR_PCR6_16B_tag; + + typedef union { /* Protocol Configuration Register 7 */ + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */ + uint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */ + } B; + } FR_PCR7_16B_tag; + + typedef union { /* Protocol Configuration Register 8 */ + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */ + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */ + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */ + } B; + } FR_PCR8_16B_tag; + + typedef union { /* Protocol Configuration Register 9 */ + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */ + uint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */ + uint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */ + } B; + } FR_PCR9_16B_tag; + + typedef union { /* Protocol Configuration Register 10 */ + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */ + uint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */ + uint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */ + } B; + } FR_PCR10_16B_tag; + + typedef union { /* Protocol Configuration Register 11 */ + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */ + uint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */ + uint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */ + } B; + } FR_PCR11_16B_tag; + + typedef union { /* Protocol Configuration Register 12 */ + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */ + uint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */ + } B; + } FR_PCR12_16B_tag; + + typedef union { /* Protocol Configuration Register 13 */ + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */ + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */ + } B; + } FR_PCR13_16B_tag; + + typedef union { /* Protocol Configuration Register 14 */ + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */ +#else + uint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR14_16B_tag; + + typedef union { /* Protocol Configuration Register 15 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */ +#else + uint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR15_16B_tag; + + typedef union { /* Protocol Configuration Register 16 */ + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */ +#else + uint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR16_16B_tag; + + typedef union { /* Protocol Configuration Register 17 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */ +#else + uint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR17_16B_tag; + + typedef union { /* Protocol Configuration Register 18 */ + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */ + uint16_t KEY_SLOT_ID:10; /* pKeySlotId */ + } B; + } FR_PCR18_16B_tag; + + typedef union { /* Protocol Configuration Register 19 */ + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */ + uint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */ + } B; + } FR_PCR19_16B_tag; + + typedef union { /* Protocol Configuration Register 20 */ + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */ + uint16_t MICRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */ + } B; + } FR_PCR20_16B_tag; + + typedef union { /* Protocol Configuration Register 21 */ + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */ + uint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */ + } B; + } FR_PCR21_16B_tag; + + typedef union { /* Protocol Configuration Register 22 */ + uint16_t R; + struct { + uint16_t R:1; /* Reserved bit */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */ +#else + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */ +#else + uint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR22_16B_tag; + + typedef union { /* Protocol Configuration Register 23 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */ +#else + uint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR23_16B_tag; + + typedef union { /* Protocol Configuration Register 24 */ + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */ + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR24_16B_tag; + + typedef union { /* Protocol Configuration Register 25 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR25_16B_tag; + + typedef union { /* Protocol Configuration Register 26 */ + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */ + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR26_16B_tag; + + typedef union { /* Protocol Configuration Register 27 */ + uint16_t R; + struct { +#ifndef USE_FIELD_ALIASES_FR + uint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */ +#else + uint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */ +#endif + } B; + } FR_PCR27_16B_tag; + + typedef union { /* Protocol Configuration Register 28 */ + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */ + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */ + } B; + } FR_PCR28_16B_tag; + + typedef union { /* Protocol Configuration Register 29 */ + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */ + uint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */ + } B; + } FR_PCR29_16B_tag; + + typedef union { /* Protocol Configuration Register 30 */ + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */ + } B; + } FR_PCR30_16B_tag; + + typedef union { /* Receive FIFO System Memory Base Address High Register */ + uint16_t R; + struct { + uint16_t SMBA_31_16:16; /* System Memory Base Address */ + } B; + } FR_RFSYMBHADR_16B_tag; + + typedef union { /* Receive FIFO System Memory Base Address Low Register */ + uint16_t R; + struct { + uint16_t:4; + uint16_t SMBA_15_4:12; /* System Memory Base Address */ + } B; + } FR_RFSYMBLADR_16B_tag; + + typedef union { /* Receive FIFO Periodic Timer Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t PTD:14; /* Periodic Timer Duration */ + } B; + } FR_RFPTR_16B_tag; + + typedef union { /* Receive FIFO Fill Level and Pop Count Register */ + uint16_t R; + struct { + uint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */ + uint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */ + } B; + } FR_RFFLPCR_16B_tag; + + typedef union { /* ECC Error Interrupt Flag and Enable Register */ + uint16_t R; + struct { + uint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */ + uint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */ + uint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */ + uint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */ + uint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */ + uint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */ + uint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */ + uint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */ + uint16_t:4; + uint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */ + uint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */ + uint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */ + uint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */ + } B; + } FR_EEIFER_16B_tag; + + typedef union { /* ECC Error Report and Injection Control Register */ + uint16_t R; + struct { + uint16_t BSY:1; /* Register Update Busy */ + uint16_t:5; + uint16_t ERS:2; /* Error Report Select */ + uint16_t:3; + uint16_t ERM:1; /* Error Report Mode */ + uint16_t:2; + uint16_t EIM:1; /* Error Injection Mode */ + uint16_t EIE:1; /* Error Injection Enable */ + } B; + } FR_EERICR_16B_tag; + + typedef union { /* ECC Error Report Adress Register */ + uint16_t R; + struct { + uint16_t MID:1; /* Memory Identifier */ + uint16_t BANK:3; /* Memory Bank */ + uint16_t ADDR:12; /* Memory Address */ + } B; + } FR_EERAR_16B_tag; + + typedef union { /* ECC Error Report Data Register */ + uint16_t R; + struct { + uint16_t DATA:16; /* Data */ + } B; + } FR_EERDR_16B_tag; + + typedef union { /* ECC Error Report Code Register */ + uint16_t R; + struct { + uint16_t:11; + uint16_t CODE:5; /* Code */ + } B; + } FR_EERCR_16B_tag; + + typedef union { /* ECC Error Injection Address Register */ + uint16_t R; + struct { + uint16_t MID:1; /* Memory Identifier */ + uint16_t BANK:3; /* Memory Bank */ + uint16_t ADDR:12; /* Memory Address */ + } B; + } FR_EEIAR_16B_tag; + + typedef union { /* ECC Error Injection Data Register */ + uint16_t R; + struct { + uint16_t DATA:16; /* Data */ + } B; + } FR_EEIDR_16B_tag; + + typedef union { /* ECC Error Injection Code Register */ + uint16_t R; + struct { + uint16_t:11; + uint16_t CODE:5; /* Code */ + } B; + } FR_EEICR_16B_tag; + + + /* Register layout for all registers MBCCSR... */ + + typedef union { /* Message Buffer Configuration Control Status Register */ + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* Message Buffer Commit Mode */ + uint16_t MBT:1; /* Message Buffer Type */ + uint16_t MTD:1; /* Message Buffer Transfer Direction */ + uint16_t CMT:1; /* Commit for Transmission */ + uint16_t EDT:1; /* Enable/Disable Trigger */ + uint16_t LCKT:1; /* Lock/Unlock Trigger */ + uint16_t MBIE:1; /* Message Buffer Interrupt Enable */ + uint16_t:3; + uint16_t DUP:1; /* Data Updated */ + uint16_t DVAL:1; /* DataValid */ + uint16_t EDS:1; /* Enable/Disable Status */ + uint16_t LCKS:1; /* LockStatus */ + uint16_t MBIF:1; /* Message Buffer Interrupt Flag */ + } B; + } FR_MBCCSR_16B_tag; + + + /* Register layout for all registers MBCCFR... */ + + typedef union { /* Message Buffer Cycle Counter Filter Register */ + uint16_t R; + struct { + uint16_t MTM:1; /* Message Buffer Transmission Mode */ +#ifndef USE_FIELD_ALIASES_FR + uint16_t CHA:1; /* Channel Assignment */ +#else + uint16_t CHNLA:1; /* deprecated name - please avoid */ +#endif +#ifndef USE_FIELD_ALIASES_FR + uint16_t CHB:1; /* Channel Assignment */ +#else + uint16_t CHNLB:1; /* deprecated name - please avoid */ +#endif + uint16_t CCFE:1; /* Cycle Counter Filtering Enable */ + uint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */ + uint16_t CCFVAL:6; /* Cycle Counter Filtering Value */ + } B; + } FR_MBCCFR_16B_tag; + + + /* Register layout for all registers MBFIDR... */ + + typedef union { /* Message Buffer Frame ID Register */ + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* Frame ID */ + } B; + } FR_MBFIDR_16B_tag; + + + /* Register layout for all registers MBIDXR... */ + + typedef union { /* Message Buffer Index Register */ + uint16_t R; + struct { + uint16_t:9; + uint16_t MBIDX:7; /* Message Buffer Index */ + } B; + } FR_MBIDXR_16B_tag; + + + /* Register layout for generated register(s) NMVR... */ + + typedef union { /* */ + uint16_t R; + } FR_NMVR_16B_tag; + + + + + /* Register layout for generated register(s) SSCR... */ + + typedef union { /* */ + uint16_t R; + } FR_SSCR_16B_tag; + + + typedef struct FR_MB_struct_tag { + + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */ + + } FR_MB_tag; + + + typedef struct FR_struct_tag { /* start of FR_tag */ + /* Module Version Number */ + FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */ + /* Module Configuration Register */ + FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */ + union { + FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */ + + /* SYSTEM MEMORY BASE ADD HIGH REG */ + FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */ + + }; + union { + FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */ + + /* SYSTEM MEMORY BASE ADD LOW REG */ + FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */ + + }; + /* STROBE SIGNAL CONTROL REGISTER */ + FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */ + int8_t FR_reserved_000A[2]; + /* MESSAGE BUFFER DATA SIZE REGISTER */ + FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */ + /* MESS. BUFFER SEG. SIZE & UTILISATION REG */ + FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */ + union { + /* PE DRAM ACCESS REGISTER */ + FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */ + + FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */ + + }; + union { + /* PE DRAM DATA REGISTER */ + FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */ + + FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */ + + }; + /* PROTOCOL OPERATION CONTROL REG */ + FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */ + /* GLOBAL INTERRUPT FLAG & ENABLE REG */ + FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */ + /* PROTOCOL INTERRUPT FLAG REGISTER 0 */ + FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */ + /* PROTOCOL INTERRUPT FLAG REGISTER 1 */ + FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */ + /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */ + FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */ + /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */ + FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */ + /* CHI ERROR FLAG REGISTER */ + FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */ + /* Message Buffer Interrupt Vector Register */ + FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */ + /* Channel A Status Error Counter Register */ + FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */ + /* Channel B Status Error Counter Register */ + FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */ + /* Protocol Status Register 0 */ + FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */ + /* Protocol Status Register 1 */ + FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */ + /* Protocol Status Register 2 */ + FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */ + /* Protocol Status Register 3 */ + FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */ + /* Macrotick Counter Register */ + FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */ + /* Cycle Counter Register */ + FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */ + /* Slot Counter Channel A Register */ + FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */ + /* Slot Counter Channel B Register */ + FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */ + /* Rate Correction Value Register */ + FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */ + /* Offset Correction Value Register */ + FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */ + union { + FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */ + + /* Combined Interrupt Flag Register */ + FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */ + + }; + /* System Memory Access Time-Out Register */ + FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */ + /* Sync Frame Counter Register */ + FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */ + /* Sync Frame Table Offset Register */ + FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */ + /* Sync Frame Table Configuration, Control, Status Register */ + FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */ + /* Sync Frame ID Rejection Filter */ + FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */ + /* Sync Frame ID Acceptance Filter Value Register */ + FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */ + /* Sync Frame ID Acceptance Filter Mask Register */ + FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */ + union { + FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */ + + struct { + /* Network Management Vector Register0 */ + FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */ + /* Network Management Vector Register1 */ + FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */ + /* Network Management Vector Register2 */ + FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */ + /* Network Management Vector Register3 */ + FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */ + /* Network Management Vector Register4 */ + FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */ + /* Network Management Vector Register5 */ + FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */ + }; + + }; + /* Network Management Vector Length Register */ + FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */ + /* Timer Configuration and Control Register */ + FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */ + /* Timer 1 Cycle Set Register */ + FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */ + union { + /* Timer 1 Macrotick Offset Register */ + FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */ + + FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */ + + }; + /* Timer 2 Configuration Register 0 */ + FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */ + /* Timer 2 Configuration Register 1 */ + FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */ + /* Slot Status Selection Register */ + FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */ + /* Slot Status Counter Condition Register */ + FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */ + union { + FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */ + + struct { + /* Slot Status Register0 */ + FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */ + /* Slot Status Register1 */ + FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */ + /* Slot Status Register2 */ + FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */ + /* Slot Status Register3 */ + FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */ + /* Slot Status Register4 */ + FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */ + /* Slot Status Register5 */ + FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */ + /* Slot Status Register6 */ + FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */ + /* Slot Status Register7 */ + FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */ + }; + + }; + union { + FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */ + + struct { + /* Slot Status Counter Register0 */ + FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */ + /* Slot Status Counter Register1 */ + FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */ + /* Slot Status Counter Register2 */ + FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */ + /* Slot Status Counter Register3 */ + FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */ + }; + + }; + /* MTS A Configuration Register */ + FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */ + /* MTS B Configuration Register */ + FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */ + /* Receive Shadow Buffer Index Register */ + FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */ + union { + /* Receive FIFO Watermark and Selection Register */ + FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */ + + FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */ + + }; + union { + FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */ + + /* Receive FIFO Start Index Register */ + FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */ + + }; + /* Receive FIFO Depth and Size Register */ + FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */ + /* Receive FIFO A Read Index Register */ + FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */ + /* Receive FIFO B Read Index Register */ + FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */ + /* Receive FIFO Message ID Acceptance Filter Value Register */ + FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */ + union { + /* Receive FIFO Message ID Acceptance Filter Mask Register */ + FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */ + + FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */ + + }; + /* Receive FIFO Frame ID Rejection Filter Value Register */ + FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */ + /* Receive FIFO Frame ID Rejection Filter Mask Register */ + FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */ + /* Receive FIFO Range Filter Configuration Register */ + FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */ + /* Receive FIFO Range Filter Control Register */ + FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */ + /* Last Dynamic Transmit Slot Channel A Register */ + FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */ + /* Last Dynamic Transmit Slot Channel B Register */ + FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */ + /* Protocol Configuration Register 0 */ + FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */ + /* Protocol Configuration Register 1 */ + FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */ + /* Protocol Configuration Register 2 */ + FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */ + /* Protocol Configuration Register 3 */ + FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */ + /* Protocol Configuration Register 4 */ + FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */ + /* Protocol Configuration Register 5 */ + FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */ + /* Protocol Configuration Register 6 */ + FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */ + /* Protocol Configuration Register 7 */ + FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */ + /* Protocol Configuration Register 8 */ + FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */ + /* Protocol Configuration Register 9 */ + FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */ + /* Protocol Configuration Register 10 */ + FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */ + /* Protocol Configuration Register 11 */ + FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */ + /* Protocol Configuration Register 12 */ + FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */ + /* Protocol Configuration Register 13 */ + FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */ + /* Protocol Configuration Register 14 */ + FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */ + /* Protocol Configuration Register 15 */ + FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */ + /* Protocol Configuration Register 16 */ + FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */ + /* Protocol Configuration Register 17 */ + FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */ + /* Protocol Configuration Register 18 */ + FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */ + /* Protocol Configuration Register 19 */ + FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */ + /* Protocol Configuration Register 20 */ + FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */ + /* Protocol Configuration Register 21 */ + FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */ + /* Protocol Configuration Register 22 */ + FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */ + /* Protocol Configuration Register 23 */ + FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */ + /* Protocol Configuration Register 24 */ + FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */ + /* Protocol Configuration Register 25 */ + FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */ + /* Protocol Configuration Register 26 */ + FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */ + /* Protocol Configuration Register 27 */ + FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */ + /* Protocol Configuration Register 28 */ + FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */ + /* Protocol Configuration Register 29 */ + FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */ + /* Protocol Configuration Register 30 */ + FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */ + int8_t FR_reserved_00DE[10]; + /* Receive FIFO System Memory Base Address High Register */ + FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */ + /* Receive FIFO System Memory Base Address Low Register */ + FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */ + /* Receive FIFO Periodic Timer Register */ + FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */ + /* Receive FIFO Fill Level and Pop Count Register */ + FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */ + /* ECC Error Interrupt Flag and Enable Register */ + FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */ + /* ECC Error Report and Injection Control Register */ + FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */ + /* ECC Error Report Adress Register */ + FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */ + /* ECC Error Report Data Register */ + FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */ + /* ECC Error Report Code Register */ + FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */ + /* ECC Error Injection Address Register */ + FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */ + /* ECC Error Injection Data Register */ + FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */ + /* ECC Error Injection Code Register */ + FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */ + union { + /* Register set MB */ + FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */ + + FR_MB_tag MBCCS[64]; /* offset: 0x0100 (0x0008 x 64) */ + + struct { + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */ + /* Message Buffer Configuration Control Status Register */ + FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */ + /* Message Buffer Cycle Counter Filter Register */ + FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */ + /* Message Buffer Frame ID Register */ + FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */ + /* Message Buffer Index Register */ + FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */ + }; + + }; + } FR_tag; + + +#define FR (*(volatile FR_tag *) 0xFFFE0000UL) + + + + + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* _leopard_H_*/ + +/* End of file */ + diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc5668.h b/bsps/powerpc/include/mpc55xx/fsl-mpc5668.h new file mode 100644 index 0000000000..b7a1793dca --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc5668.h @@ -0,0 +1,6721 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/************************************************************************** + * FILE NAME: mpc5668.h COPYRIGHT (c) Freescale 2009 * + * REVISION: 1.1 All Rights Reserved * + * * + * DESCRIPTION: * + * This file contain all of the register and bit field definitions for * + * MPC5668. * + **************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +/************************************************************************** + * Example register & bit field write: * + * * + * <MODULE>.<REGISTER>.B.<BIT> = 1; * + * <MODULE>.<REGISTER>.R = 0x10000000; * + * * + **************************************************************************/ + +#ifndef _MPC5668_H_ +#define _MPC5668_H_ + +#ifndef ASM + +#include <stdint.h> + +#include <mpc55xx/regs-edma.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/*************************************************************************/ +/* MODULE : ADC */ +/*************************************************************************/ + struct ADC_tag { + + union { + uint32_t R; + struct { + uint32_t OWREN:1; + uint32_t WLSIDE:1; + uint32_t MODE:1; + uint32_t EDGLEV:1; + uint32_t TRGEN:1; + uint32_t EDGE:1; + uint32_t XSTRTEN:1; + uint32_t NSTART:1; + uint32_t:1; + uint32_t JTRGEN:1; + uint32_t JEDGE:1; + uint32_t JSTART:1; + uint32_t:2; + uint32_t CTUEN:1; + uint32_t:8; + uint32_t ADCLKSEL:1; + uint32_t ABORTCHAIN:1; + uint32_t ABORT:1; + uint32_t ACKO:1; + uint32_t OFFREFRESH:1; + uint32_t OFFCANC:1; + uint32_t:2; + uint32_t PWDN:1; + } B; + } MCR; /* MAIN CONFIGURATION REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t NSTART:1; + uint32_t JABORT:1; + uint32_t:2; + uint32_t JSTART:1; + uint32_t:3; + uint32_t CTUSTART:1; + uint32_t CHADDR:7; + uint32_t:3; + uint32_t ACKO:1; + uint32_t OFFREFRESH:1; + uint32_t OFFCANC:1; + uint32_t ADCSTATUS:3; + } B; + } MSR; /* MAIN STATUS REGISTER */ + + uint32_t adc_reserved1[2]; + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t OFFCANCOVR:1; + uint32_t EOFFSET:1; + uint32_t EOCTU:1; + uint32_t JEOC:1; + uint32_t JECH:1; + uint32_t EOC:1; + uint32_t ECH:1; + } B; + } ISR; /* INTERRUPT STATUS REGISTER */ + + union { + uint32_t R; + struct { + uint32_t EOCCH31:1; + uint32_t EOCCH30:1; + uint32_t EOCCH29:1; + uint32_t EOCCH28:1; + uint32_t EOCCH27:1; + uint32_t EOCCH26:1; + uint32_t EOCCH25:1; + uint32_t EOCCH24:1; + uint32_t EOCCH23:1; + uint32_t EOCCH22:1; + uint32_t EOCCH21:1; + uint32_t EOCCH20:1; + uint32_t EOCCH19:1; + uint32_t EOCCH18:1; + uint32_t EOCCH17:1; + uint32_t EOCCH16:1; + uint32_t EOCCH15:1; + uint32_t EOCCH14:1; + uint32_t EOCCH13:1; + uint32_t EOCCH12:1; + uint32_t EOCCH11:1; + uint32_t EOCCH10:1; + uint32_t EOCCH9:1; + uint32_t EOCCH8:1; + uint32_t EOCCH7:1; + uint32_t EOCCH6:1; + uint32_t EOCCH5:1; + uint32_t EOCCH4:1; + uint32_t EOCCH3:1; + uint32_t EOCCH2:1; + uint32_t EOCCH1:1; + uint32_t EOCCH0:1; + } B; + } CEOCFR0; /* CHANNEL PENDING REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t EOCCH63:1; + uint32_t EOCCH62:1; + uint32_t EOCCH61:1; + uint32_t EOCCH60:1; + uint32_t EOCCH59:1; + uint32_t EOCCH58:1; + uint32_t EOCCH57:1; + uint32_t EOCCH56:1; + uint32_t EOCCH55:1; + uint32_t EOCCH54:1; + uint32_t EOCCH53:1; + uint32_t EOCCH52:1; + uint32_t EOCCH51:1; + uint32_t EOCCH50:1; + uint32_t EOCCH49:1; + uint32_t EOCCH48:1; + uint32_t EOCCH47:1; + uint32_t EOCCH46:1; + uint32_t EOCCH45:1; + uint32_t EOCCH44:1; + uint32_t EOCCH43:1; + uint32_t EOCCH42:1; + uint32_t EOCCH41:1; + uint32_t EOCCH40:1; + uint32_t EOCCH39:1; + uint32_t EOCCH38:1; + uint32_t EOCCH37:1; + uint32_t EOCCH36:1; + uint32_t EOCCH35:1; + uint32_t EOCCH34:1; + uint32_t EOCCH33:1; + uint32_t EOCCH32:1; + } B; + } CEOCFR1; /* CHANNEL PENDING REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t EOCCH95:1; + uint32_t EOCCH94:1; + uint32_t EOCCH93:1; + uint32_t EOCCH92:1; + uint32_t EOCCH91:1; + uint32_t EOCCH90:1; + uint32_t EOCCH89:1; + uint32_t EOCCH88:1; + uint32_t EOCCH87:1; + uint32_t EOCCH86:1; + uint32_t EOCCH85:1; + uint32_t EOCCH84:1; + uint32_t EOCCH83:1; + uint32_t EOCCH82:1; + uint32_t EOCCH81:1; + uint32_t EOCCH80:1; + uint32_t EOCCH79:1; + uint32_t EOCCH78:1; + uint32_t EOCCH77:1; + uint32_t EOCCH76:1; + uint32_t EOCCH75:1; + uint32_t EOCCH74:1; + uint32_t EOCCH73:1; + uint32_t EOCCH72:1; + uint32_t EOCCH71:1; + uint32_t EOCCH70:1; + uint32_t EOCCH69:1; + uint32_t EOCCH68:1; + uint32_t EOCCH67:1; + uint32_t EOCCH66:1; + uint32_t EOCCH65:1; + uint32_t EOCCH64:1; + } B; + } CEOCFR2; /* CHANNEL PENDING REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t MSKOFFCANCOVR:1; + uint32_t MSKEOFFSET:1; + uint32_t MSKEOCTU:1; + uint32_t MSKJEOC:1; + uint32_t MSKJECH:1; + uint32_t MSKEOC:1; + uint32_t MSKECH:1; + } B; + } IMR; /* INTERRUPT MASK REGISTER */ + + union { + uint32_t R; + struct { + uint32_t CIM31:1; + uint32_t CIM30:1; + uint32_t CIM29:1; + uint32_t CIM28:1; + uint32_t CIM27:1; + uint32_t CIM26:1; + uint32_t CIM25:1; + uint32_t CIM24:1; + uint32_t CIM23:1; + uint32_t CIM22:1; + uint32_t CIM21:1; + uint32_t CIM20:1; + uint32_t CIM19:1; + uint32_t CIM18:1; + uint32_t CIM17:1; + uint32_t CIM16:1; + uint32_t CIM15:1; + uint32_t CIM14:1; + uint32_t CIM13:1; + uint32_t CIM12:1; + uint32_t CIM11:1; + uint32_t CIM10:1; + uint32_t CIM9:1; + uint32_t CIM8:1; + uint32_t CIM7:1; + uint32_t CIM6:1; + uint32_t CIM5:1; + uint32_t CIM4:1; + uint32_t CIM3:1; + uint32_t CIM2:1; + uint32_t CIM1:1; + uint32_t CIM0:1; + } B; + } CIMR0; /* CHANNEL INTERRUPT MASK REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t CIM63:1; + uint32_t CIM62:1; + uint32_t CIM61:1; + uint32_t CIM60:1; + uint32_t CIM59:1; + uint32_t CIM58:1; + uint32_t CIM57:1; + uint32_t CIM56:1; + uint32_t CIM55:1; + uint32_t CIM54:1; + uint32_t CIM53:1; + uint32_t CIM52:1; + uint32_t CIM51:1; + uint32_t CIM50:1; + uint32_t CIM49:1; + uint32_t CIM48:1; + uint32_t CIM47:1; + uint32_t CIM46:1; + uint32_t CIM45:1; + uint32_t CIM44:1; + uint32_t CIM43:1; + uint32_t CIM42:1; + uint32_t CIM41:1; + uint32_t CIM40:1; + uint32_t CIM39:1; + uint32_t CIM38:1; + uint32_t CIM37:1; + uint32_t CIM36:1; + uint32_t CIM35:1; + uint32_t CIM34:1; + uint32_t CIM33:1; + uint32_t CIM32:1; + } B; + } CIMR1; /* CHANNEL INTERRUPT MASK REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t CIM63:1; + uint32_t CIM62:1; + uint32_t CIM61:1; + uint32_t CIM60:1; + uint32_t CIM59:1; + uint32_t CIM58:1; + uint32_t CIM57:1; + uint32_t CIM56:1; + uint32_t CIM55:1; + uint32_t CIM54:1; + uint32_t CIM53:1; + uint32_t CIM52:1; + uint32_t CIM51:1; + uint32_t CIM50:1; + uint32_t CIM49:1; + uint32_t CIM48:1; + uint32_t CIM47:1; + uint32_t CIM46:1; + uint32_t CIM45:1; + uint32_t CIM44:1; + uint32_t CIM43:1; + uint32_t CIM42:1; + uint32_t CIM41:1; + uint32_t CIM40:1; + uint32_t CIM39:1; + uint32_t CIM38:1; + uint32_t CIM37:1; + uint32_t CIM36:1; + uint32_t CIM35:1; + uint32_t CIM34:1; + uint32_t CIM33:1; + uint32_t CIM32:1; + } B; + } CIMR2; /* CHANNEL INTERRUPT MASK REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t WDG3H:1; + uint32_t WDG2H:1; + uint32_t WDG1H:1; + uint32_t WDG0H:1; + uint32_t WDG3L:1; + uint32_t WDG2L:1; + uint32_t WDG1L:1; + uint32_t WDG0L:1; + } B; + } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t MSKWDG3H:1; + uint32_t MSKWDG2H:1; + uint32_t MSKWDG1H:1; + uint32_t MSKWDG0H:1; + uint32_t MSKWDG3L:1; + uint32_t MSKWDG2L:1; + uint32_t MSKWDG1L:1; + uint32_t MSKWDG0L:1; + } B; + } WTIMR; /* WATCHDOG INTERRUPT THRESHOLD MASK REGISTER */ + + uint32_t adc_reserved2[2]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t DCLR:1; + uint32_t DMAEN:1; + } B; + } DMAE; /* DMA ENABLE REGISTER */ + + union { + uint32_t R; + struct { + uint32_t DMA31:1; + uint32_t DMA30:1; + uint32_t DMA29:1; + uint32_t DMA28:1; + uint32_t DMA27:1; + uint32_t DMA26:1; + uint32_t DMA25:1; + uint32_t DMA24:1; + uint32_t DMA23:1; + uint32_t DMA22:1; + uint32_t DMA21:1; + uint32_t DMA20:1; + uint32_t DMA19:1; + uint32_t DMA18:1; + uint32_t DMA17:1; + uint32_t DMA16:1; + uint32_t DMA15:1; + uint32_t DMA14:1; + uint32_t DMA13:1; + uint32_t DMA12:1; + uint32_t DMA11:1; + uint32_t DMA10:1; + uint32_t DMA9:1; + uint32_t DMA8:1; + uint32_t DMA7:1; + uint32_t DMA6:1; + uint32_t DMA5:1; + uint32_t DMA4:1; + uint32_t DMA3:1; + uint32_t DMA2:1; + uint32_t DMA1:1; + uint32_t DMA0:1; + } B; + } DMAR0; /* DMA CHANNEL SELECT REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t DMA63:1; + uint32_t DMA62:1; + uint32_t DMA61:1; + uint32_t DMA60:1; + uint32_t DMA59:1; + uint32_t DMA58:1; + uint32_t DMA57:1; + uint32_t DMA56:1; + uint32_t DMA55:1; + uint32_t DMA54:1; + uint32_t DMA53:1; + uint32_t DMA52:1; + uint32_t DMA51:1; + uint32_t DMA50:1; + uint32_t DMA49:1; + uint32_t DMA48:1; + uint32_t DMA47:1; + uint32_t DMA46:1; + uint32_t DMA45:1; + uint32_t DMA44:1; + uint32_t DMA43:1; + uint32_t DMA42:1; + uint32_t DMA41:1; + uint32_t DMA40:1; + uint32_t DMA39:1; + uint32_t DMA38:1; + uint32_t DMA37:1; + uint32_t DMA36:1; + uint32_t DMA35:1; + uint32_t DMA34:1; + uint32_t DMA33:1; + uint32_t DMA32:1; + } B; + } DMAR1; /* DMA CHANNEL SELECT REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t DMA95:1; + uint32_t DMA94:1; + uint32_t DMA93:1; + uint32_t DMA92:1; + uint32_t DMA91:1; + uint32_t DMA90:1; + uint32_t DMA89:1; + uint32_t DMA88:1; + uint32_t DMA87:1; + uint32_t DMA86:1; + uint32_t DMA85:1; + uint32_t DMA84:1; + uint32_t DMA83:1; + uint32_t DMA82:1; + uint32_t DMA81:1; + uint32_t DMA80:1; + uint32_t DMA79:1; + uint32_t DMA78:1; + uint32_t DMA77:1; + uint32_t DMA76:1; + uint32_t DMA75:1; + uint32_t DMA74:1; + uint32_t DMA73:1; + uint32_t DMA72:1; + uint32_t DMA71:1; + uint32_t DMA70:1; + uint32_t DMA69:1; + uint32_t DMA68:1; + uint32_t DMA67:1; + uint32_t DMA66:1; + uint32_t DMA65:1; + uint32_t DMA64:1; + } B; + } DMAR2; /* DMA CHANNEL SELECT REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t THREN:1; + uint32_t THRINV:1; + uint32_t THROP:1; + uint32_t:6; + uint32_t THRCH:7; + } B; + } TRC[4]; /* THRESHOLD CONTROL REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t THRH:10; + uint32_t:6; + uint32_t THRL:10; + } B; + } THRHLR[4]; /* THRESHOLD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t THRH:10; + uint32_t:6; + uint32_t THRL:10; + } B; + } THRALT[4]; /* ALTERNATE THRESHOLD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t PREVAL2:2; + uint32_t PREVAL1:2; + uint32_t PREVAL0:2; + uint32_t PRECONV:1; + } B; + } PSCR; /* PRESAMPLING CONTROL REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PSR31:1; + uint32_t PSR30:1; + uint32_t PSR29:1; + uint32_t PSR28:1; + uint32_t PSR27:1; + uint32_t PSR26:1; + uint32_t PSR25:1; + uint32_t PSR24:1; + uint32_t PSR23:1; + uint32_t PSR22:1; + uint32_t PSR21:1; + uint32_t PSR20:1; + uint32_t PSR19:1; + uint32_t PSR18:1; + uint32_t PSR17:1; + uint32_t PSR16:1; + uint32_t PSR15:1; + uint32_t PSR14:1; + uint32_t PSR13:1; + uint32_t PSR12:1; + uint32_t PSR11:1; + uint32_t PSR10:1; + uint32_t PSR9:1; + uint32_t PSR8:1; + uint32_t PSR7:1; + uint32_t PSR6:1; + uint32_t PSR5:1; + uint32_t PSR4:1; + uint32_t PSR3:1; + uint32_t PSR2:1; + uint32_t PSR1:1; + uint32_t PSR0:1; + } B; + } PSR0; /* PRESAMPLING REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t PSR63:1; + uint32_t PSR62:1; + uint32_t PSR61:1; + uint32_t PSR60:1; + uint32_t PSR59:1; + uint32_t PSR58:1; + uint32_t PSR57:1; + uint32_t PSR56:1; + uint32_t PSR55:1; + uint32_t PSR54:1; + uint32_t PSR53:1; + uint32_t PSR52:1; + uint32_t PSR51:1; + uint32_t PSR50:1; + uint32_t PSR49:1; + uint32_t PSR48:1; + uint32_t PSR47:1; + uint32_t PSR46:1; + uint32_t PSR45:1; + uint32_t PSR44:1; + uint32_t PSR43:1; + uint32_t PSR42:1; + uint32_t PSR41:1; + uint32_t PSR40:1; + uint32_t PSR39:1; + uint32_t PSR38:1; + uint32_t PSR37:1; + uint32_t PSR36:1; + uint32_t PSR35:1; + uint32_t PSR34:1; + uint32_t PSR33:1; + uint32_t PSR32:1; + } B; + } PSR1; /* PRESAMPLING REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t PSR95:1; + uint32_t PSR94:1; + uint32_t PSR93:1; + uint32_t PSR92:1; + uint32_t PSR91:1; + uint32_t PSR90:1; + uint32_t PSR89:1; + uint32_t PSR88:1; + uint32_t PSR87:1; + uint32_t PSR86:1; + uint32_t PSR85:1; + uint32_t PSR84:1; + uint32_t PSR83:1; + uint32_t PSR82:1; + uint32_t PSR81:1; + uint32_t PSR80:1; + uint32_t PSR79:1; + uint32_t PSR78:1; + uint32_t PSR77:1; + uint32_t PSR76:1; + uint32_t PSR75:1; + uint32_t PSR74:1; + uint32_t PSR73:1; + uint32_t PSR72:1; + uint32_t PSR71:1; + uint32_t PSR70:1; + uint32_t PSR69:1; + uint32_t PSR68:1; + uint32_t PSR67:1; + uint32_t PSR66:1; + uint32_t PSR65:1; + uint32_t PSR64:1; + } B; + } PSR2; /* PRESAMPLING REGISTER 2 */ + + uint32_t adc_reserved3; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; + uint32_t:1; + uint32_t OFFSHIFT:2; + uint32_t:1; + uint32_t INPCMP:2; + uint32_t:1; + uint32_t INPSAMP:8; + } B; + } CTR0; /* CONVERSION TIMING REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; + uint32_t:4; + uint32_t INPCMP:2; + uint32_t:1; + uint32_t INPSAMP:8; + } B; + } CTR1; /* CONVERSION TIMING REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t INPLATCH:1; + uint32_t:4; + uint32_t INPCMP:2; + uint32_t:1; + uint32_t INPSAMP:8; + } B; + } CTR2; /* CONVERSION TIMING REGISTER 2 */ + + uint32_t adc_reserved4; + + union { + uint32_t R; + struct { + uint32_t CH31:1; + uint32_t CH30:1; + uint32_t CH29:1; + uint32_t CH28:1; + uint32_t CH27:1; + uint32_t CH26:1; + uint32_t CH25:1; + uint32_t CH24:1; + uint32_t CH23:1; + uint32_t CH22:1; + uint32_t CH21:1; + uint32_t CH20:1; + uint32_t CH19:1; + uint32_t CH18:1; + uint32_t CH17:1; + uint32_t CH16:1; + uint32_t CH15:1; + uint32_t CH14:1; + uint32_t CH13:1; + uint32_t CH12:1; + uint32_t CH11:1; + uint32_t CH10:1; + uint32_t CH9:1; + uint32_t CH8:1; + uint32_t CH7:1; + uint32_t CH6:1; + uint32_t CH5:1; + uint32_t CH4:1; + uint32_t CH3:1; + uint32_t CH2:1; + uint32_t CH1:1; + uint32_t CH0:1; + } B; + } NCMR0; /* NORMAL CONVERSION MASK REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t CH63:1; + uint32_t CH62:1; + uint32_t CH61:1; + uint32_t CH60:1; + uint32_t CH59:1; + uint32_t CH58:1; + uint32_t CH57:1; + uint32_t CH56:1; + uint32_t CH55:1; + uint32_t CH54:1; + uint32_t CH53:1; + uint32_t CH52:1; + uint32_t CH51:1; + uint32_t CH50:1; + uint32_t CH49:1; + uint32_t CH48:1; + uint32_t CH47:1; + uint32_t CH46:1; + uint32_t CH45:1; + uint32_t CH44:1; + uint32_t CH43:1; + uint32_t CH42:1; + uint32_t CH41:1; + uint32_t CH40:1; + uint32_t CH39:1; + uint32_t CH38:1; + uint32_t CH37:1; + uint32_t CH36:1; + uint32_t CH35:1; + uint32_t CH34:1; + uint32_t CH33:1; + uint32_t CH32:1; + } B; + } NCMR1; /* NORMAL CONVERSION MASK REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t PSR95:1; + uint32_t PSR94:1; + uint32_t PSR93:1; + uint32_t PSR92:1; + uint32_t PSR91:1; + uint32_t PSR90:1; + uint32_t PSR89:1; + uint32_t PSR88:1; + uint32_t PSR87:1; + uint32_t PSR86:1; + uint32_t PSR85:1; + uint32_t PSR84:1; + uint32_t PSR83:1; + uint32_t PSR82:1; + uint32_t PSR81:1; + uint32_t PSR80:1; + uint32_t PSR79:1; + uint32_t PSR78:1; + uint32_t PSR77:1; + uint32_t PSR76:1; + uint32_t PSR75:1; + uint32_t PSR74:1; + uint32_t PSR73:1; + uint32_t PSR72:1; + uint32_t PSR71:1; + uint32_t PSR70:1; + uint32_t PSR69:1; + uint32_t PSR68:1; + uint32_t PSR67:1; + uint32_t PSR66:1; + uint32_t PSR65:1; + uint32_t PSR64:1; + } B; + } NCMR2; /* NORMAL CONVERSION MASK REGISTER 2 */ + + uint32_t adc_reserved5; + + union { + uint32_t R; + struct { + uint32_t CH31:1; + uint32_t CH30:1; + uint32_t CH29:1; + uint32_t CH28:1; + uint32_t CH27:1; + uint32_t CH26:1; + uint32_t CH25:1; + uint32_t CH24:1; + uint32_t CH23:1; + uint32_t CH22:1; + uint32_t CH21:1; + uint32_t CH20:1; + uint32_t CH19:1; + uint32_t CH18:1; + uint32_t CH17:1; + uint32_t CH16:1; + uint32_t CH15:1; + uint32_t CH14:1; + uint32_t CH13:1; + uint32_t CH12:1; + uint32_t CH11:1; + uint32_t CH10:1; + uint32_t CH9:1; + uint32_t CH8:1; + uint32_t CH7:1; + uint32_t CH6:1; + uint32_t CH5:1; + uint32_t CH4:1; + uint32_t CH3:1; + uint32_t CH2:1; + uint32_t CH1:1; + uint32_t CH0:1; + } B; + } JCMR0; /* INJECTED CONVERSION MASK REGISTER 0 */ + + union { + uint32_t R; + struct { + uint32_t CH63:1; + uint32_t CH62:1; + uint32_t CH61:1; + uint32_t CH60:1; + uint32_t CH59:1; + uint32_t CH58:1; + uint32_t CH57:1; + uint32_t CH56:1; + uint32_t CH55:1; + uint32_t CH54:1; + uint32_t CH53:1; + uint32_t CH52:1; + uint32_t CH51:1; + uint32_t CH50:1; + uint32_t CH49:1; + uint32_t CH48:1; + uint32_t CH47:1; + uint32_t CH46:1; + uint32_t CH45:1; + uint32_t CH44:1; + uint32_t CH43:1; + uint32_t CH42:1; + uint32_t CH41:1; + uint32_t CH40:1; + uint32_t CH39:1; + uint32_t CH38:1; + uint32_t CH37:1; + uint32_t CH36:1; + uint32_t CH35:1; + uint32_t CH34:1; + uint32_t CH33:1; + uint32_t CH32:1; + } B; + } JCMR1; /* INJECTED CONVERSION MASK REGISTER 1 */ + + union { + uint32_t R; + struct { + uint32_t PSR95:1; + uint32_t PSR94:1; + uint32_t PSR93:1; + uint32_t PSR92:1; + uint32_t PSR91:1; + uint32_t PSR90:1; + uint32_t PSR89:1; + uint32_t PSR88:1; + uint32_t PSR87:1; + uint32_t PSR86:1; + uint32_t PSR85:1; + uint32_t PSR84:1; + uint32_t PSR83:1; + uint32_t PSR82:1; + uint32_t PSR81:1; + uint32_t PSR80:1; + uint32_t PSR79:1; + uint32_t PSR78:1; + uint32_t PSR77:1; + uint32_t PSR76:1; + uint32_t PSR75:1; + uint32_t PSR74:1; + uint32_t PSR73:1; + uint32_t PSR72:1; + uint32_t PSR71:1; + uint32_t PSR70:1; + uint32_t PSR69:1; + uint32_t PSR68:1; + uint32_t PSR67:1; + uint32_t PSR66:1; + uint32_t PSR65:1; + uint32_t PSR64:1; + } B; + } JCMR2; /* INJECTED CONVERSION MASK REGISTER 2 */ + + union { + uint32_t R; + struct { + uint32_t:15; + uint32_t OFFSETLOAD:1; + uint32_t:8; + uint32_t OFFSET_WORD:8; + } B; + } OFFWR; /* OFFSET WORD REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t DSD:8; + } B; + } DSDR; /* DECODE SIGNALS DELAY REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t PDED:8; + } B; + } PDEDR; /* DECODE SIGNALS DELAY REGISTER */ + + uint32_t adc_reserved6[9]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t TEST_CTL:16; + } B; + } TCTLR; /* TEST CONTROL REGISTER */ + + uint32_t adc_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; + uint32_t OVERW:1; + uint32_t RESULT:2; + uint32_t:6; + uint32_t CDATA:10; + } B; + } PRECDATAREG[32]; /* PRESISION DATA REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; + uint32_t OVERW:1; + uint32_t RESULT:2; + uint32_t:6; + uint32_t CDATA:10; + } B; + } INTDATAREG[32]; /* PRESISION DATA REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:12; + uint32_t VALID:1; + uint32_t OVERW:1; + uint32_t RESULT:2; + uint32_t:6; + uint32_t CDATA:10; + } B; + } EXTDATAREG[32]; /* PRESISION DATA REGISTER */ + + }; /* end of ADC_tag */ +/**************************************************************************/ +/* MODULE : AXBS Crossbar Switch (XBAR) */ +/**************************************************************************/ + struct XBAR_tag { + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR0; /* Master Priority Register 0 */ + + uint32_t xbar_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; /* Master Priority Register 0 */ + + uint32_t xbar_reserved2[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR1; /* Master Priority Register 1 */ + + uint32_t xbar_reserved3[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; /* Master Priority Register 1 */ + + uint32_t xbar_reserved4[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR2; /* Master Priority Register 2 */ + + uint32_t xbar_reserved5[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR2; /* Master Priority Register 2 */ + + uint32_t xbar_reserved6[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR3; /* Master Priority Register 3 */ + + uint32_t xbar_reserved7[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR3; /* Master Priority Register 3 */ + + uint32_t xbar_reserved8[186]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR6; /* Master Priority Register 6 */ + + uint32_t xbar_reserved9[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; /* Master Priority Register 6 */ + + uint32_t xbar_reserved10[58]; + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; + uint32_t:1; + uint32_t MSTR6:3; + uint32_t:9; + uint32_t MSTR5:3; + uint32_t:1; + uint32_t MSTR3:3; + uint32_t:1; + uint32_t MSTR2:3; + uint32_t:1; + uint32_t MSTR1:3; + uint32_t:1; + uint32_t MSTR0:1; + } B; + } MPR7; /* Master Priority Register 7 */ + + uint32_t xbar_reserved11[3]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* Master Priority Register 7 */ + + uint32_t xbar_reserved12[506]; + + union { + uint32_t R; + struct { + uint32_t R0:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } MGPCR7; /* Master General Purpose Register 7 */ + + }; +/*************************************************************************/ +/* MODULE : CRP */ +/*************************************************************************/ + struct CRP_tag { + + union { + uint32_t R; + struct { + uint32_t IRCTRIMEN:1; + uint32_t:4; + uint32_t PREDIV:3; + uint32_t:4; + uint32_t EN128KIRC:1; + uint32_t EN32KOSC:1; + uint32_t ENLPOSC:1; + uint32_t EN40MOSC:1; + uint32_t:3; + uint32_t TRIM128IRC:5; + uint32_t:2; + uint32_t TRIM16IRC:6; + } B; + } CLKSRC; /* CLOCK SOURCE REGISTER */ + + uint32_t crp_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t CNTEN:1; + uint32_t RTCIE:1; + uint32_t FRZEN:1; + uint32_t ROVREN:1; + uint32_t RTCVAL:12; + uint32_t APIEN:1; + uint32_t APIIE:1; + uint32_t CLKSEL:2; + uint32_t DIV512EN:1; + uint32_t DIV32EN:1; + uint32_t APIVAL:10; + } B; + } RTCC; /* RTC CONTROL REGISTER */ + + union { + uint32_t R; + struct { + uint32_t:2; + uint32_t RTCF:1; + uint32_t:15; + uint32_t APIF:1; + uint32_t:2; + uint32_t ROVRF:1; + uint32_t:10; + } B; + } RTSC; /* RTC STATUS REGISTER */ + + union { + uint32_t R; + struct { + uint32_t RTCCNT:32; + } B; + } RTCCNT; /* RTC Counter Register */ + + uint32_t crp_reserved2[9]; + + union { + uint32_t R; + struct { + uint32_t PWK31:2; + uint32_t PWK30:2; + uint32_t PWK29:2; + uint32_t PWK28:2; + uint32_t PWK27:2; + uint32_t PWK26:2; + uint32_t PWK25:2; + uint32_t PWK24:2; + uint32_t PWK23:2; + uint32_t PWK22:2; + uint32_t PWK21:2; + uint32_t PWK20:2; + uint32_t PWK19:2; + uint32_t PWK18:2; + uint32_t PWK17:2; + uint32_t PWK16:2; + } B; + } PWKENH; /* PIN WAKEUP ENABLE HIGH REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PWK15:2; + uint32_t PWK14:2; + uint32_t PWK13:2; + uint32_t PWK12:2; + uint32_t PWK11:2; + uint32_t PWK10:2; + uint32_t PWK9:2; + uint32_t PWK8:2; + uint32_t PWK7:2; + uint32_t PWK6:2; + uint32_t PWK5:2; + uint32_t PWK4:2; + uint32_t PWK3:2; + uint32_t PWK2:2; + uint32_t PWK1:2; + uint32_t PWK0:2; + } B; + } PWKENL; /* PIN WAKEUP ENABLE LOW REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PWKSRCIE31:1; + uint32_t PWKSRCIE30:1; + uint32_t PWKSRCIE29:1; + uint32_t PWKSRCIE28:1; + uint32_t PWKSRCIE27:1; + uint32_t PWKSRCIE26:1; + uint32_t PWKSRCIE25:1; + uint32_t PWKSRCIE24:1; + uint32_t PWKSRCIE23:1; + uint32_t PWKSRCIE22:1; + uint32_t PWKSRCIE21:1; + uint32_t PWKSRCIE20:1; + uint32_t PWKSRCIE19:1; + uint32_t PWKSRCIE18:1; + uint32_t PWKSRCIE17:1; + uint32_t PWKSRCIE16:1; + uint32_t PWKSRCIE15:1; + uint32_t PWKSRCIE14:1; + uint32_t PWKSRCIE13:1; + uint32_t PWKSRCIE12:1; + uint32_t PWKSRCIE11:1; + uint32_t PWKSRCIE10:1; + uint32_t PWKSRCIE9:1; + uint32_t PWKSRCIE8:1; + uint32_t PWKSRCIE7:1; + uint32_t PWKSRCIE6:1; + uint32_t PWKSRCIE5:1; + uint32_t PWKSRCIE4:1; + uint32_t PWKSRCIE3:1; + uint32_t PWKSRCIE2:1; + uint32_t PWKSRCIE1:1; + uint32_t PWKSRCIE0:1; + } B; + } PWKSRCIE; /* PIN WAKEUP SOURCE INTERRUPT ENABLE REGISTER */ + + union { + uint32_t R; + struct { + uint32_t PWKSRCIE31:1; + uint32_t PWKSRCIE30:1; + uint32_t PWKSRCIE29:1; + uint32_t PWKSRCIE28:1; + uint32_t PWKSRCIE27:1; + uint32_t PWKSRCIE26:1; + uint32_t PWKSRCIE25:1; + uint32_t PWKSRCIE24:1; + uint32_t PWKSRCIE23:1; + uint32_t PWKSRCIE22:1; + uint32_t PWKSRCIE21:1; + uint32_t PWKSRCIE20:1; + uint32_t PWKSRCIE19:1; + uint32_t PWKSRCIE18:1; + uint32_t PWKSRCIE17:1; + uint32_t PWKSRCIE16:1; + uint32_t PWKSRCIE15:1; + uint32_t PWKSRCIE14:1; + uint32_t PWKSRCIE13:1; + uint32_t PWKSRCIE12:1; + uint32_t PWKSRCIE11:1; + uint32_t PWKSRCIE10:1; + uint32_t PWKSRCIE9:1; + uint32_t PWKSRCIE8:1; + uint32_t PWKSRCIE7:1; + uint32_t PWKSRCIE6:1; + uint32_t PWKSRCIE5:1; + uint32_t PWKSRCIE4:1; + uint32_t PWKSRCIE3:1; + uint32_t PWKSRCIE2:1; + uint32_t PWKSRCIE1:1; + uint32_t PWKSRCIE0:1; + } B; + } PWKSRCF; /* PIN WAKEUP SOURCE FLAG REGISTER */ + + union { + uint32_t R; + struct { + uint32_t Z6VECB:20; + uint32_t:10; + uint32_t Z6RST:1; + uint32_t VLE:1; + } B; + } Z6VEC; /* Z6 RESET VECTOR REGISTER */ + + union { + uint32_t R; + struct { + uint32_t Z0VECB:30; + uint32_t Z0RST:1; + uint32_t:1; + } B; + } Z0VEC; /* Z0 RESET VECTOR REGISTER */ + + union { + uint32_t R; + struct { + uint32_t RECPTR:30; + uint32_t FASTREC:1; + uint32_t:1; + } B; + } RECPTR; /* RESET RECOVERY POINTER REGISTER */ + + uint32_t crp_reserved3; + + union { + uint32_t R; + struct { + uint32_t SLEEPF:1; + uint32_t:12; + uint32_t RTCOVRWKF:1; + uint32_t RTCWKF:1; + uint32_t APIWKF:1; + uint32_t SLEEP:1; + uint32_t:4; + uint32_t RAMSEL:3; + uint32_t:4; + uint32_t WKCLKSEL:1; + uint32_t RTCOVRWKEN:1; + uint32_t RTCWKEN:1; + uint32_t APIWKEN:1; + } B; + } PSCR; /* POWER STATUS AND CONTROL REGISTER */ + + uint32_t crp_reserved4[3]; + + union { + uint32_t R; + struct { + uint32_t LVI5LOCK:1; + uint32_t LVI5RE:1; + uint32_t:7; + uint32_t LVI5HIE:1; + uint32_t LVI5NIE:1; + uint32_t LVI5IE:1; + uint32_t:2; + uint32_t FRIE:1; + uint32_t FDIS:1; + uint32_t:9; + uint32_t LVI5HIF:1; + uint32_t LVI5NF:1; + uint32_t LVI5F:1; + uint32_t:2; + uint32_t FRF:1; + uint32_t FRDY:1; + } B; + } SOCSC; /* LVI Status and Control Register */ + + }; /* end of CRP_tag */ +/*************************************************************************/ +/* MODULE : CTU */ +/*************************************************************************/ + struct CTU_tag { + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t TRGIEN:1; + uint32_t TRGI:1; + uint32_t:2; + uint32_t PRESC_CONF:4; + } B; + } CSR; /* Control Status Register */ + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t SV:9; + } B; + } SVR[7]; /* Start Value Register */ + + union { + uint32_t R; + struct { + uint32_t:23; + uint32_t CV:9; + } B; + } CVR[4]; /* Current Value Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t TM:1; + uint32_t:1; + uint32_t COUNT_GROUP:2; + uint32_t:1; + uint32_t DELAY_INDEX:3; + uint32_t CLR_FG:1; + uint32_t:1; + uint32_t CHANNEL_VALUE:6; + } B; + } EVTCFGR[33]; /* Event Configuration Register */ + + }; /* end of CTU_tag */ +/*************************************************************************/ +/* MODULE : DMAMUX */ +/*************************************************************************/ + struct DMAMUX_tag { + union { + uint8_t R; + struct { + uint8_t ENBL:1; + uint8_t TRIG:1; + uint8_t SOURCE:6; + } B; + } CHCONFIG[32]; /* DMA Channel Configuration Register */ + + }; /* end of DMAMUX_tag */ +/*************************************************************************/ +/* MODULE : DSPI */ +/*************************************************************************/ + struct DSPI_tag { + union DSPI_MCR_tag { + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t:2; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register */ + + uint32_t dspi_reserved1; + + union { + uint32_t R; + struct { + uint32_t SPI_TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag { + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers */ + + union DSPI_SR_tag { + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register */ + + union DSPI_RSER_tag { + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register */ + + union DSPI_PUSHR_tag { + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:4; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register */ + + union DSPI_POPR_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register */ + + union { + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_txf[12]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers */ + + uint32_t DSPI_reserved_rxf[12]; + + union { + uint32_t R; + struct { + uint32_t:11; + uint32_t TSBC:1; + uint32_t TXSS:1; + uint32_t:2; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:6; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t SER_DATA:32; + } B; + } SDR; /* DSI Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t ASER_DATA:32; + } B; + } ASDR; /* DSI Alternate Serialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t COMP_DATA:32; + } B; + } COMPR; /* DSI Transmit Comparison Register */ + + union { + uint32_t R; + struct { + uint32_t DESER_DATA:32; + } B; + } DDR; /* DSI deserialization Data Register */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t TSBCNT:5; + uint32_t:16; + uint32_t DPCS1_7:1; + uint32_t DPCS1_6:1; + uint32_t DPCS1_5:1; + uint32_t DPCS1_4:1; + uint32_t DPCS1_3:1; + uint32_t DPCS1_2:1; + uint32_t DPCS1_1:1; + uint32_t DPCS1_0:1; + } B; + } DSICR1; /* DSI Configuration Register 1 */ + + }; /* end of DSPI_tag */ +/*************************************************************************/ +/* MODULE : ECSM */ +/*************************************************************************/ + struct ECSM_tag { + + uint32_t ecsm_reserved1[9]; + + union { + uint32_t R; + struct { + uint32_t FXSBE0:1; + uint32_t FXSBE1:1; + uint32_t FXSBE2:1; + uint32_t FXSBE3:1; + uint32_t:2; + uint32_t FXSBE6:1; + uint32_t FXSBE7:1; + uint32_t RBEN:1; + uint32_t WBEN:1; + uint32_t ACCERR:1; + uint32_t:21; + } B; + } FBOMCR; /* FEC Burst Optimisation Master Control Register */ + + uint8_t ecsm_reserved2[27]; + + union { + uint8_t R; + struct { + uint8_t:2; + uint8_t EPR1BR:1; + uint8_t EPF1BR:1; + uint8_t:2; + uint8_t EPRNCR:1; + uint8_t EPFNCR:1; + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t ecsm_reserved3[3]; + + union { + uint8_t R; + struct { + uint8_t:2; + uint8_t PR1BC:1; + uint8_t PF1BC:1; + uint8_t:2; + uint8_t PRNCE:1; + uint8_t PFNCE:1; + } B; + } ESR; /* ECC Status Register */ + + uint16_t ecsm_reserved4; + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t FRC1BI:1; + uint16_t FR11BI:1; + uint16_t:2; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t PREI_SEL:1; + uint16_t ERRBIT:7; + } B; + } EEGR; /* ECC Error Generation Register */ + + uint32_t ecsm_reserved5; + + union { + uint32_t R; + struct { + uint32_t PFEAR:32; + } B; + } PFEAR; /* Platform Flash ECC Address Register */ + + uint16_t ecsm_reserved6; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PFEMR:4; + } B; + } PFEMR; /* Platform Flash ECC Address Register */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } PFEAT; /* Flash ECC Attributes Register */ + + union { + uint32_t R; + struct { + uint32_t PFEDRH:32; + } B; + } PFEDRH; /* Flash ECC Data High Register */ + + union { + uint32_t R; + struct { + uint32_t PFEDRL:32; + } B; + } PFEDRL; /* Flash ECC Data Low Register */ + + union { + uint32_t R; + struct { + uint32_t PREAR:32; + } B; + } PREAR; /* Platform RAM ECC Address Register */ + + uint16_t ecsm_reserved8; + + union { + uint8_t R; + struct { + uint8_t:4; + uint8_t PREMR:4; + } B; + } PREMR; /* RAM ECC Attributes Register */ + + union { + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROTECTION:4; + } B; + } PREAT; /* Platform RAM ECC Attributes Register */ + + union { + uint32_t R; + struct { + uint32_t PREDR:32; + } B; + } PREDRH; /* Platform RAM ECC Data Low Register High */ + + union { + uint32_t R; + struct { + uint32_t PREDR:32; + } B; + } PREDRL; /* Platform RAM ECC Data Low Register Low */ + + }; /* end of ECSM_tag */ +/*************************************************************************/ +/* MODULE : EMIOS */ +/*************************************************************************/ + struct EMIOS_tag { + union EMIOS_MCR_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t:1; + uint32_t GPREN:1; + uint32_t:10; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t F31:1; + uint32_t F30:1; + uint32_t F29:1; + uint32_t F28:1; + uint32_t F27:1; + uint32_t F26:1; + uint32_t F25:1; + uint32_t F24:1; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; /* Global FLAG Register */ + + union { + uint32_t R; + struct { + uint32_t OU31:1; + uint32_t OU30:1; + uint32_t OU29:1; + uint32_t OU28:1; + uint32_t OU27:1; + uint32_t OU26:1; + uint32_t OU25:1; + uint32_t OU24:1; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register */ + + union { + uint32_t R; + struct { + uint32_t UC31:1; + uint32_t UC30:1; + uint32_t UC29:1; + uint32_t UC28:1; + uint32_t UC27:1; + uint32_t UC26:1; + uint32_t UC25:1; + uint32_t UC24:1; + uint32_t UC23:1; + uint32_t UC22:1; + uint32_t UC21:1; + uint32_t UC20:1; + uint32_t UC19:1; + uint32_t UC18:1; + uint32_t UC17:1; + uint32_t UC16:1; + uint32_t UC15:1; + uint32_t UC14:1; + uint32_t UC13:1; + uint32_t UC12:1; + uint32_t UC11:1; + uint32_t UC10:1; + uint32_t UC9:1; + uint32_t UC8:1; + uint32_t UC7:1; + uint32_t UC6:1; + uint32_t UC5:1; + uint32_t UC4:1; + uint32_t UC3:1; + uint32_t UC2:1; + uint32_t UC1:1; + uint32_t UC0:1; + } B; + } UCDIS; /* Disable Channel Register */ + + uint32_t emios_reserved1[4]; + + struct EMIOS_CH_tag { + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t A:16; /* Channel A Data Register */ + } B; + } CADR; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t B:16; /* Channel B Data Register */ + } B; + } CBDR; + + union { + uint32_t R; /* Channel Counter Register */ + struct { + uint32_t:16; + uint32_t C:16; /* Channel C Data Register */ + } B; + } CCNTR; + + union EMIOS_CCR_tag { + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; /* Channel Control Register */ + + union EMIOS_CSR_tag { + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register */ + + union { + uint32_t R; /* Alternate Channel A Data Register */ + } ALTA; + + uint32_t emios_channel_reserved[2]; + + } CH[32]; + + }; /* end of EMIOS_tag */ +/*************************************************************************/ +/* MODULE : eSCI */ +/*************************************************************************/ + struct ESCI_tag { + union ESCI_CR1_tag { + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; /* Control Register 1 */ + + union ESCI_CR2_tag { + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t TXDIR:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t RXPOL:1; + uint16_t PMSK:1; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 */ + + union ESCI_DR_tag { + uint16_t R; + struct { + uint16_t RN:1; + uint16_t TN:1; + uint16_t ERR:1; + uint16_t:1; + uint16_t RD_11:4; + uint16_t D:8; + } B; + } DR; /* Data Register */ + + union ESCI_SR_tag { + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:2; + uint32_t TACT:1; + uint32_t RACT:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:6; + uint32_t UREQ:1; + uint32_t OVFL:1; + } B; + } SR; /* Status Register */ + + union { + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t:2; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:6; + uint32_t UQIE:1; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; /* LIN Control Register */ + + union { + uint8_t R; + } LTR; /* LIN Transmit Register */ + + uint8_t eSCI_reserved1[3]; + + union { + uint8_t R; + } LRR; /* LIN Recieve Register */ + + uint8_t eSCI_reserved2[3]; + + union { + uint16_t R; + } LPR; /* LIN CRC Polynom Register */ + + union { + uint8_t R; + struct { + uint8_t:3; + uint8_t SYNM:1; + uint8_t EROE:1; + uint8_t ERFE:1; + uint8_t ERPE:1; + uint8_t M2:1; + } B; + } CR3; /* Control Register 3 */ + + uint8_t eSCI_reserved3[5]; + }; /* end of ESCI_tag */ +/*************************************************************************/ +/* MODULE : FEC */ +/*************************************************************************/ + struct FEC_tag { + + uint32_t fec_reserved_start; + + union { + uint32_t R; + struct { + uint32_t HBERR:1; + uint32_t BABR:1; + uint32_t BABT:1; + uint32_t GRA:1; + uint32_t TXF:1; + uint32_t TXB:1; + uint32_t RXF:1; + uint32_t RXB:1; + uint32_t MII:1; + uint32_t EBERR:1; + uint32_t LC:1; + uint32_t RL:1; + uint32_t UN:1; + uint32_t:19; + } B; + } EIR; /* Interrupt Event Register */ + + union { + uint32_t R; + struct { + uint32_t HBERR:1; + uint32_t BABR:1; + uint32_t BABT:1; + uint32_t GRA:1; + uint32_t TXF:1; + uint32_t TXB:1; + uint32_t RXF:1; + uint32_t RXB:1; + uint32_t MII:1; + uint32_t EBERR:1; + uint32_t LC:1; + uint32_t RL:1; + uint32_t UN:1; + uint32_t:19; + } B; + } EIMR; /* Interrupt Mask Register */ + + uint32_t fec_reserved_eimr; + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t R_DES_ACTIVE:1; + uint32_t:24; + } B; + } RDAR; /* Receive Descriptor Active Register */ + + union { + uint32_t R; + struct { + uint32_t:7; + uint32_t X_DES_ACTIVE:1; + uint32_t:24; + } B; + } TDAR; /* Transmit Descriptor Active Register */ + + uint32_t fec_reserved_tdar[3]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t ETHER_EN:1; + uint32_t RESET:1; + } B; + } ECR; /* Ethernet Control Register */ + + uint32_t fec_reserved_ecr[6]; + + union { + uint32_t R; + struct { + uint32_t ST:2; + uint32_t OP:2; + uint32_t PA:5; + uint32_t RA:5; + uint32_t TA:2; + uint32_t DATA:16; + } B; + } MMFR; /* MII Data Register */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t DIS_PREAMBLE:1; + uint32_t MII_SPEED:6; + uint32_t:1; + } B; + } MSCR; /* MII Speed Control Register */ + + uint32_t fec_reserved_mscr[7]; + + union { + uint32_t R; + struct { + uint32_t MIB_DISABLE:1; + uint32_t MIB_IDLE:1; + uint32_t:30; + } B; + } MIBC; /* MIB Control Register */ + + uint32_t fec_reserved_mibc[7]; + + union { + uint32_t R; + struct { + uint32_t:5; + uint32_t MAX_FL:11; + uint32_t:10; + uint32_t FCE:1; + uint32_t BC_REJ:1; + uint32_t PROM:1; + uint32_t MII_MODE:1; + uint32_t DRT:1; + uint32_t LOOP:1; + } B; + } RCR; /* Receive Control Register */ + + uint32_t fec_reserved_rcr[15]; + + union { + uint32_t R; + struct { + uint32_t:27; + uint32_t RFC_PAUSE:1; + uint32_t TFC_PAUSE:1; + uint32_t FDEN:1; + uint32_t HBC:1; + uint32_t GTS:1; + } B; + } TCR; /* Transmit Control Register */ + + uint32_t fec_reserved_tcr[7]; + + union { + uint32_t R; + struct { + uint32_t PADDR1:32; + } B; + } PALR; /* Physical Address Low Register */ + + union { + uint32_t R; + struct { + uint32_t PADDR2:16; + uint32_t TYPE:16; + } B; + } PAUR; /* Physical Address High + Type Register */ + + union { + uint32_t R; + struct { + uint32_t OPCODE:16; + uint32_t PAUSE_DUR:16; + } B; + } OPD; /* Opcode/Pause Duration Register */ + + uint32_t fec_reserved_opd[10]; + + union { + uint32_t R; + struct { + uint32_t IADDR1:32; + } B; + } IAUR; /* Descriptor Individual Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t IADDR2:32; + } B; + } IALR; /* Descriptor Individual Lower Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR1:32; + } B; + } GAUR; /* Descriptor Group Upper Address Register */ + + union { + uint32_t R; + struct { + uint32_t GADDR2:32; + } B; + } GALR; /* Descriptor Group Lower Address Register */ + + uint32_t fec_reserved_galr[7]; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t X_WMRK:2; + } B; + } TFWR; /* FIFO Transmit FIFO Watermark Register */ + + uint32_t fec_reserved_tfwr; + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_BOUND:8; + uint32_t:2; + } B; + } FRBR; /* FIFO Receive Bound Register */ + + union { + uint32_t R; + struct { + uint32_t:22; + uint32_t R_FSTART:8; + uint32_t:2; + } B; + } FRSR; /* FIFO Receive Start Register */ + + uint32_t fec_reserved_frsr[11]; + + union { + uint32_t R; + struct { + uint32_t R_DES_START:30; + uint32_t:2; + } B; + } ERDSR; /* Receive Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t X_DES_START:30; + uint32_t:2; + } B; + } ETDSR; /* Transmit Descriptor Ring Start Register */ + + union { + uint32_t R; + struct { + uint32_t:21; + uint32_t R_BUF_SIZE:7; + uint32_t:4; + } B; + } EMRBR; /* Receive Buffer Size Register */ + + uint32_t fec_reserved_emrbr[29]; + + union { + uint32_t R; + } RMON_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_T_PACKETS; /* RMON Tx packet count */ + + union { + uint32_t R; + } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */ + + union { + uint32_t R; + } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */ + + union { + uint32_t R; + } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */ + + union { + uint32_t R; + } RMON_T_COL; /* RMON Tx collision count */ + + union { + uint32_t R; + } RMON_T_P64; /* RMON Tx 64 byte packets */ + + union { + uint32_t R; + } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_T_OCTETS; /* RMON Tx Octets */ + + union { + uint32_t R; + } IEEE_T_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_T_FRAME_OK; /* Frames Transmitted OK */ + + union { + uint32_t R; + } IEEE_T_1COL; /* Frames Transmitted with Single Collision */ + + union { + uint32_t R; + } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */ + + union { + uint32_t R; + } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */ + + union { + uint32_t R; + } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */ + + union { + uint32_t R; + } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */ + + union { + uint32_t R; + } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */ + + union { + uint32_t R; + } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */ + + union { + uint32_t R; + } IEEE_T_SQE; /* Frames Transmitted with SQE Error */ + + union { + uint32_t R; + } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */ + + union { + uint32_t R; + } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */ + + uint32_t fec_reserved_rmon_t_octets_ok[2]; + + union { + uint32_t R; + } RMON_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } RMON_R_PACKETS; /* RMON Rx packet count */ + + union { + uint32_t R; + } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */ + + union { + uint32_t R; + } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */ + + union { + uint32_t R; + } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */ + + union { + uint32_t R; + } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */ + + union { + uint32_t R; + } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */ + + union { + uint32_t R; + } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */ + + union { + uint32_t R; + } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */ + + uint32_t fec_reserved_rmon_r_jab; + + union { + uint32_t R; + } RMON_R_P64; /* RMON Rx 64 byte packets */ + + union { + uint32_t R; + } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */ + + union { + uint32_t R; + } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */ + + union { + uint32_t R; + } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */ + + union { + uint32_t R; + } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */ + + union { + uint32_t R; + } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */ + + union { + uint32_t R; + } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */ + + union { + uint32_t R; + } RMON_R_OCTETS; /* RMON Rx Octets */ + + union { + uint32_t R; + } IEEE_R_DROP; /* Count of frames not counted correctly */ + + union { + uint32_t R; + } IEEE_R_FRAME_OK; /* Frames Received OK */ + + union { + uint32_t R; + } IEEE_R_CRC; /* Frames Received with CRC Error */ + + union { + uint32_t R; + } IEEE_R_ALIGN; /* Frames Received with Alignment Error */ + + union { + uint32_t R; + } IEEE_R_MACERR; /* Receive Fifo Overflow count */ + + union { + uint32_t R; + } IEEE_R_FDXFC; /* Flow Control Pause frames received */ + + union { + uint32_t R; + } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */ + + }; /* end of FEC_tag */ +/*************************************************************************/ +/* MODULE : FLASH */ +/*************************************************************************/ + struct FLASH_tag { + union { + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZE:3; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t SBC:1; + uint32_t:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + uint32_t:4; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t:2; + uint32_t MLOCK:2; + uint32_t:6; + uint32_t LLOCK:10; + } B; + } LML; /* Low/Mid-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:25; + uint32_t HBLOCK:6; + } B; + } HBL; /* High-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t:2; + uint32_t SMLOCK:2; + uint32_t:6; + uint32_t SLLOCK:10; + } B; + } SLL; /* Secondary low/mid-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t MSEL:2; + uint32_t:6; + uint32_t LSEL:10; + } B; + } LMS; /* Low/Mid-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t:26; + uint32_t HBSEL:6; + } B; + } HBS; /* High-address space block locking Register */ + + union { + uint32_t R; + struct { + uint32_t SAD:1; + uint32_t:10; + uint32_t ADDR:18; + uint32_t:3; + } B; + } ADR; /* Address Register */ + + union { + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t ARB:1; + uint32_t PRI:1; + uint32_t:1; + uint32_t M8PFE:1; + uint32_t:1; + uint32_t M6PFE:1; + uint32_t M5PFE:1; + uint32_t M4PFE:1; + uint32_t:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP0; /* Platform Flash Configuration Register for Port 0 */ + + union { + uint32_t R; + struct { + uint32_t LBCFG:4; + uint32_t:3; + uint32_t M8PFE:1; + uint32_t:1; + uint32_t M6PFE:1; + uint32_t M5PFE:1; + uint32_t M4PFE:1; + uint32_t:1; + uint32_t M2PFE:1; + uint32_t M1PFE:1; + uint32_t M0PFE:1; + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } PFCRP1; /* Platform Flash Configuration Register for Port 1 */ + + union { + uint32_t R; + struct { + uint32_t M7AP:2; + uint32_t M6AP:2; + uint32_t M5AP:2; + uint32_t M4AP:2; + uint32_t M3AP:2; + uint32_t M2AP:2; + uint32_t M1AP:2; + uint32_t M0AP:2; + uint32_t SHSACC:4; + uint32_t:4; + uint32_t SHDACC:4; + uint32_t:4; + } B; + } PFAPR; /* Platform Flash access protection Register */ + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t SACC:31; + } B; + } PFSACC; /* PFlash Supervisor Access Control Register */ + + union { + uint32_t R; + struct { + uint32_t:1; + uint32_t DACC:31; + } B; + } PFDACC; /* PFlash Data Access Control Register */ + + uint32_t FLASH_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t UTE:1; + uint32_t SCBE:1; + uint32_t:6; + uint32_t DSI:8; + uint32_t:10; + uint32_t MRE:1; + uint32_t MRV:1; + uint32_t EIE:1; + uint32_t AIS:1; + uint32_t AIE:1; + uint32_t AID:1; + } B; + } UT0; /* User Test Register 0 */ + + union { + uint32_t R; + struct { + uint32_t DAI:32; + } B; + } UT1; /* User Test Register 1 */ + + union { + uint32_t R; + struct { + uint32_t DAI:32; + } B; + } UT2; /* User Test Register 2 */ + + union { + uint32_t R; + struct { + uint32_t MISR:32; + } B; + } MISR[5]; /* Multiple Input Signature Register */ + + }; /* end of FLASH_tag */ +/*************************************************************************/ +/* MODULE : FlexCAN */ +/*************************************************************************/ + struct FLEXCAN_tag { + union { + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t FEN:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t WAKMSK:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t SUPV:1; + uint32_t SLFWAK:1; + uint32_t WRNEN:1; + uint32_t LPMACK:1; + uint32_t WAKSRC:1; + uint32_t DOZE:1; + uint32_t SRXDIS:1; + uint32_t BCC:1; + uint32_t:2; + uint32_t LPRIO_EN:1; + uint32_t AEN:1; + uint32_t:2; + uint32_t IDAM:2; + uint32_t:2; + uint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CTRL; /* Control Register */ + + union { + uint32_t R; + } TIMER; /* Free Running Timer */ + + uint32_t FLEXCAN_reserved1; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t WAKINT:1; + } B; + } ESR; /* Error and Status Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMASK2; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMASK1; /* Interruput Masks Register */ + + union { + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFLAG2; /* Interruput Flag Register */ + + union { + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFLAG1; /* Interruput Flag Register */ + + uint32_t FLEXCAN_reserved2[19]; + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t PRIO:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + /* uint8_t B[8]; Data buffer in Bytes (8 bits) */ + /* uint16_t H[4]; Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + /* uint32_t R[2]; Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + uint32_t FLEXCAN_reserved3[256]; + + union { + uint32_t R; + struct { + uint32_t MI:32; + } B; + } RXIMR[64]; /* RX Individual Mask Registers */ + + }; /* end of CTU_tag */ +/**************************************************************************/ +/* MODULE : FlexRay */ +/**************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:2; + uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */ + uint16_t:2; + uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:2; + uint16_t TBIVEC:6; /* transmit buffer interrupt vector */ + uint16_t:2; + uint16_t RBIVEC:6; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSYMATOR { + uint16_t R; + struct { + uint16_t:11; + uint16_t TIMEOUT:5; /* system memory time out value */ + } B; + } SYMATOR_t; + + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:5; + uint16_t RSBIDX:7; /* receive shadow buffer index */ + } B; + } RSBIR_t; + + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + + union { + uint16_t R; + struct { + uint16_t:9; + uint16_t MBIDX:7; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPADR { + uint16_t R; + } PADR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + uint16_t reserved0[1]; /*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved1[1]; /*10 */ + uint16_t reserved2[1]; /*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved3[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; +/**************************************************************************/ +/* MODULE : FMPLL */ +/**************************************************************************/ + struct FMPLL_tag { + + uint32_t FMPLL_reserved0; + + union FMPLL_SYNSR_tag { /* Synthesiser Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + union FMPLL_ESYNCR1_tag { + uint32_t R; + struct { + uint32_t:1; + uint32_t CLKCFG:3; + uint32_t:8; + uint32_t EPREDIV:4; + uint32_t:8; + uint32_t EMFD:8; + } B; + } ESYNCR1; + + union FMPLL_ESYNCR2_tag { + uint32_t R; + struct { + uint32_t:8; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t:1; + uint32_t ERATE:2; + uint32_t:5; + uint32_t EDEPTH:3; + uint32_t:2; + uint32_t ERFD:6; + } B; + } ESYNCR2; + + }; +/*************************************************************************/ +/* MODULE : i2c */ +/*************************************************************************/ + struct I2C_tag { + union { + uint8_t R; + struct { + uint8_t AD:7; + uint8_t:1; + } B; + } IBAD; /* Module Bus Address Register */ + + union { + uint8_t R; + struct { + uint8_t MULT:2; + uint8_t ICR:6; + } B; + } IBFD; /* Module Bus Frequency Register */ + + union { + uint8_t R; + struct { + uint8_t MDIS:1; + uint8_t IBIE:1; + uint8_t MS:1; + uint8_t TX:1; + uint8_t NOACK:1; + uint8_t RSTA:1; + uint8_t DMAEN:1; + uint8_t:1; + } B; + } IBCR; /* Module Bus Control Register */ + + union { + uint8_t R; + struct { + uint8_t TCF:1; + uint8_t IAAS:1; + uint8_t IBB:1; + uint8_t IBAL:1; + uint8_t:1; + uint8_t SRW:1; + uint8_t IBIF:1; + uint8_t RXAK:1; + } B; + } IBSR; /* Module Status Register */ + + union { + uint8_t R; + struct { + uint8_t DATA:8; + } B; + } IBDR; /* Module Data Register */ + + union { + uint8_t R; + struct { + uint8_t BIIE:1; + uint8_t:7; + } B; + } IBIC; /* Module Interrupt Configuration Register */ + + }; /* end of i2c_tag */ +/*************************************************************************/ +/* MODULE : INTC */ +/*************************************************************************/ + struct INTC_tag { + union { + uint32_t R; + struct { + uint32_t:18; + uint32_t VTES_PRC1:1; + uint32_t:4; + uint32_t HVEN_PRC1:1; + uint32_t:2; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; /* Module Configuration Register */ + + int32_t INTC_reserved1; + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; /* Processor 0 (Z6) Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR_PRC1; /* Processor 1 (Z0) Current Priority Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; /* Processor 0 (Z6) Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t VTBA_PRC1:21; + uint32_t INTVEC_PRC1:9; + uint32_t:2; + } B; + } IACKR_PRC1; /* Processor 1 (Z0) Interrupt Acknowledge Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR; /* Processor 0 End of Interrupt Register */ + + union { + uint32_t R; + struct { + uint32_t:32; + } B; + } EOIR_PRC1; /* Processor 1 End of Interrupt Register */ + + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; /* Software Set/Clear Interruput Register */ + + uint32_t intc_reserved2[6]; + + union { + uint8_t R; + struct { + uint8_t PRC_SEL:2; + uint8_t:2; + uint8_t PRI:4; + } B; + } PSR[316]; /* Software Set/Clear Interrupt Register */ + + }; /* end of INTC_tag */ +/*************************************************************************/ +/* MODULE : MLB */ +/*************************************************************************/ + struct MLB_tag { + + union { + uint32_t R; + struct { + uint32_t MDE:1; + uint32_t LBM:1; + uint32_t MCS:2; + uint32_t:1; + uint32_t MLK:1; + uint32_t MLE:1; + uint32_t MHRE:1; + uint32_t MRS:1; + uint32_t:15; + uint32_t MDA:8; + } B; + } DCCR; /* Device Control Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t:24; + uint32_t SSRE:1; + uint32_t SDMU:1; + uint32_t SDML:1; + uint32_t SDSC:1; + uint32_t SDCS:1; + uint32_t SDNU:1; + uint32_t SDNL:1; + uint32_t SDR:1; + } B; + } SSCR; /* MLB Blank Register */ + + union { + uint32_t R; + struct { + uint32_t MSD:32; + } B; + } SDCR; /* MLB Status Register */ + + union { + uint32_t R; + struct { + uint32_t:25; + uint32_t SMMU:1; + uint32_t SMML:1; + uint32_t SMSC:1; + uint32_t SMCS:1; + uint32_t SMNU:1; + uint32_t SMNL:1; + uint32_t SMR:1; + } B; + } SMCR; /* RX Control Channel Address Register */ + + uint32_t MLB_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t UMA:8; + uint32_t UMI:8; + uint32_t MMA:8; + uint32_t MMI:8; + } B; + } VCCR; /* Version Control Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t SRBA:16; + uint32_t STBA:16; + } B; + } SBCR; /* Sync Base Address Config Register */ + + union { + uint32_t R; + struct { + uint32_t ARBA:16; + uint32_t ATBA:16; + } B; + } ABCR; /* Async Base Address Channel Config Register */ + + union { + uint32_t R; + struct { + uint32_t CRBA:16; + uint32_t CTBA:16; + } B; + } CBCR; /* Control Base Address Config Register */ + + union { + uint32_t R; + struct { + uint32_t IRBA:16; + uint32_t ITBA:16; + } B; + } IBCR; /* Isochronous Base Address Config Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t CSU:16; + } B; + } CICR; /* Channel Interrupt Config Register */ + + uint32_t MLB_reserved2[3]; + + struct mlbch_t { + + union { + uint32_t R; + struct { + uint32_t CE:1; + uint32_t TR:1; + uint32_t CT:2; + uint32_t FSE_FCE:1; + uint32_t MDS:2; + uint32_t:2; + uint32_t MLFS:1; + uint32_t:1; + uint32_t MBE:1; + uint32_t MBS:1; + uint32_t MBD:1; + uint32_t MDB:1; + uint32_t MPE:1; + uint32_t FSCD_IPL:1; + uint32_t IPL:2; + uint32_t FSPC_IPL:5; + uint32_t CA:8; + } B; + } CECR; /* Channel Entry Config Register */ + + union { + uint32_t R; + struct { + uint32_t BM:1; + uint32_t BF:1; + uint32_t:10; + uint32_t IVB:2; + uint32_t GIRB_GB:1; + uint32_t RDY:1; + uint32_t:4; + uint32_t PBS:1; + uint32_t PBD:1; + uint32_t PBDB:1; + uint32_t PBPE:1; + uint32_t:1; + uint32_t LFS:1; + uint32_t HBE:1; + uint32_t BE:1; + uint32_t CBS:1; + uint32_t CBD:1; + uint32_t CBDB:1; + uint32_t CBPE:1; + } B; + } CSCR; /* Channel Status Config Register */ + + union { + uint32_t R; + struct { + uint32_t BCA:16; + uint32_t BFA:16; + } B; + } CCBCR; /* Channel Current Buffer Config Register */ + + union { + uint32_t R; + struct { + uint32_t BSA:16; + uint32_t BEA:16; + } B; + } CNBCR; /* Channel Next Buffer Config Register */ + + } CH[16]; + + uint32_t MLB_reserved3[80]; + + union { + uint32_t R; + struct { + uint32_t BSA:16; + uint32_t BEA:16; + } B; + } LCBCR[16]; /* Local Channel Buffer Config Register */ + + }; /* end of MLB_tag */ +/*************************************************************************/ +/* MODULE : MPU */ +/*************************************************************************/ + struct MPU_tag { + union { + uint32_t R; + struct { + uint32_t MPERR:8; + uint32_t:4; + uint32_t HRL:4; + uint32_t NSP:4; + uint32_t NGRD:4; + uint32_t:7; + uint32_t VLD:1; + } B; + } CESR; /* Module Control/Error Status Register */ + + uint32_t mpu_reserved1[3]; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR0; /* Error Address Register */ + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR0; /* Error Detail Register */ + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR1; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR1; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR2; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR3; + + union { + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR3; + + union { + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR2; + + uint32_t mpu_reserved2[244]; + + struct { + union { + uint32_t R; + struct { + uint32_t SRTADDR:27; + uint32_t:5; + } B; + } WORD0; /* Region Descriptor n Word 0 */ + + union { + uint32_t R; + struct { + uint32_t ENDADDR:27; + uint32_t:5; + } B; + } WORD1; /* Region Descriptor n Word 1 */ + + union { + uint32_t R; + struct { + uint32_t:2; + uint32_t M6RE:1; + uint32_t M6WE:1; + uint32_t M5RE:1; + uint32_t M5WE:1; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t:6; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } WORD2; /* Region Descriptor n Word 2 */ + + union { + uint32_t R; + struct { + uint32_t PID:8; + uint32_t PIDMASK:8; + uint32_t:15; + uint32_t VLD:1; + } B; + } WORD3; /* Region Descriptor n Word 3 */ + + } RGD[16]; + + uint32_t mpu_reserved3[192]; + + union { + uint32_t R; + struct { + uint32_t:2; + uint32_t M6RE:1; + uint32_t M6WE:1; + uint32_t M5RE:1; + uint32_t M5WE:1; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t:6; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */ + }; +/**************************************************************************/ +/* MODULE : pit */ +/**************************************************************************/ + struct PIT_tag { + + union PIT_MCR_tag { + uint32_t R; + struct { + uint32_t:30; + uint32_t MDIS:1; + uint32_t FRZ:1; + } B; + } PITMCR; + + uint32_t pit_reserved1[59]; + + struct PIT_CHANNEL_tag { + union { + uint32_t R; + struct { + uint32_t TSV:32; + } B; + } LDVAL; + + union { + uint32_t R; + struct { + uint32_t TVL:32; + } B; + } CVAL; + + union PIT_TCTRL_tag { + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; + uint32_t TEN:1; + } B; + } TCTRL; + + union PIT_TFLG_tag { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } TFLG; + } CHANNEL[9]; + }; + + /* Compatibility with MPC5643L */ + typedef struct PIT_CHANNEL_tag PIT_RTI_CHANNEL_tag; + typedef union PIT_MCR_tag PIT_RTI_PITMCR_32B_tag; + typedef union PIT_TCTRL_tag PIT_RTI_TCTRL_32B_tag; + typedef union PIT_TFLG_tag PIT_RTI_TFLG_32B_tag; +/**************************************************************************/ +/* MODULE : sem4 */ +/**************************************************************************/ + struct SEMA4_tag { + union { + uint8_t R; + struct { + uint8_t:6; + uint8_t GTFSM:2; + } B; + } GATE[16]; /* Gate n Register */ + + uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP0INE; + + uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t INE0:1; + uint16_t INE1:1; + uint16_t INE2:1; + uint16_t INE3:1; + uint16_t INE4:1; + uint16_t INE5:1; + uint16_t INE6:1; + uint16_t INE7:1; + uint16_t INE8:1; + uint16_t INE9:1; + uint16_t INE10:1; + uint16_t INE11:1; + uint16_t INE12:1; + uint16_t INE13:1; + uint16_t INE14:1; + uint16_t INE15:1; + } B; + } CP1INE; + + uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP0NTF; + + uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */ + + union { + uint16_t R; + struct { + uint16_t GN0:1; + uint16_t GN1:1; + uint16_t GN2:1; + uint16_t GN3:1; + uint16_t GN4:1; + uint16_t GN5:1; + uint16_t GN6:1; + uint16_t GN7:1; + uint16_t GN8:1; + uint16_t GN9:1; + uint16_t GN10:1; + uint16_t GN11:1; + uint16_t GN12:1; + uint16_t GN13:1; + uint16_t GN14:1; + uint16_t GN15:1; + } B; + } CP1NTF; + + uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */ + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTGSM:2; + uint16_t:1; + uint16_t RSTGMS:3; + uint16_t RSTGTN:8; + } B; + } RSTGT; + + uint16_t sema4_reserved6; + + union { + uint16_t R; + struct { + uint16_t:2; + uint16_t RSTNSM:2; + uint16_t:1; + uint16_t RSTNMS:3; + uint16_t RSTNTN:8; + } B; + } RSTNTF; + }; +/*************************************************************************/ +/* MODULE : SIU */ +/*************************************************************************/ + struct SIU_tag { + + int32_t SIU_reserved0; + + union { + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t CSP:1; + uint32_t PKG:5; + uint32_t:2; + uint32_t MASKNUM_MAJOR:4; + uint32_t MASKNUM_MINOR:4; + } B; + } MIDR; /* MCU ID Register */ + + int32_t SIU_reserved1; + + union { + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t:8; + uint32_t SSRS:1; + uint32_t:15; + uint32_t BOOTCFG:1; + uint32_t:1; + } B; + } RSR; /* Reset Status Register */ + + union { + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t:15; + uint32_t CRE0:1; + uint32_t CRE1:1; + uint32_t:6; + uint32_t SSRL:1; + uint32_t:7; + } B; + } SRCR; /* System Reset Control Register */ + + union { + uint32_t R; + struct { + uint32_t NMI0:1; + uint32_t NMI1:1; + uint32_t:14; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; /* External Interrupt Status Register */ + + union SIU_DIRER_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; /* DMA/Interrupt Request Enable Register */ + + union SIU_DIRSR_tag { + uint32_t R; + struct { + uint32_t:30; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; /* DMA/Interrupt Select Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; /* Overrun Status Register */ + + union SIU_ORER_tag { + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; /* Overrun Request Enable Register */ + + union SIU_IREER_tag { + uint32_t R; + struct { + uint32_t NREE0:1; + uint32_t NREE1:1; + uint32_t:14; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; /* External IRQ Rising-Edge Event Enable Register */ + + union SIU_IFEER_tag { + uint32_t R; + struct { + uint32_t NFEE0:1; + uint32_t NFEE1:1; + uint32_t:14; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; /* External IRQ Falling-Edge Event Enable Register */ + + union SIU_IDFR_tag { + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; /* External IRQ Digital Filter Register */ + + union { + uint32_t R; + struct { + uint32_t FNMI0:1; + uint32_t FNMI1:1; + uint32_t:14; + uint32_t FI15:1; + uint32_t FI14:1; + uint32_t FI13:1; + uint32_t FI12:1; + uint32_t FI11:1; + uint32_t FI10:1; + uint32_t FI9:1; + uint32_t FI8:1; + uint32_t FI7:1; + uint32_t FI6:1; + uint32_t FI5:1; + uint32_t FI4:1; + uint32_t FI3:1; + uint32_t FI2:1; + uint32_t FI1:1; + uint32_t FI0:1; + } B; + } IFIR; /* External IRQ Filtered Input Register */ + + int32_t SIU_reserved2[2]; + + union SIU_PCR_tag { + uint16_t R; + struct { + uint16_t:4; + uint16_t PA:2; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[155]; /* Pad Configuration Registers */ + + int32_t SIU_reserved3[290]; + + union { + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[155]; /* GPIO Pin Data Output Registers */ + + int8_t SIU_reserved4[357]; + + union { + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[155]; /* GPIO Pin Data Input Registers */ + + int32_t SIU_reserved5[26]; + + union { + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL1; /* IMUX Register */ + + union { + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL2; /* IMUX Register */ + + int32_t SIU_reserved6; + + union { + uint32_t R; + struct { + uint32_t:17; + uint32_t TSEL1:7; + uint32_t:1; + uint32_t TSEL0:7; + } B; + } ISEL4; /* IMUX Register */ + + int32_t SIU_reserved7[27]; + + union { + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:8; + uint32_t TESTLOCK:1; + uint32_t:7; + } B; + } CCR; /* Chip Configuration Register Register */ + + union { + uint32_t R; + struct { + uint32_t:28; + uint32_t ECEN:1; + uint32_t:1; + uint32_t ECDF:2; + } B; + } ECCR; /* External Clock Configuration Register Register */ + + union { + uint32_t R; + } GPR0; /* General Purpose Register 0 */ + + union { + uint32_t R; + } GPR1; /* General Purpose Register 1 */ + + union { + uint32_t R; + } GPR2; /* General Purpose Register 2 */ + + union { + uint32_t R; + } GPR3; /* General Purpose Register 3 */ + + int32_t SIU_reserved8[2]; + + union { + uint32_t R; + struct { + uint32_t SYSCLKSEL:2; + uint32_t SYSCLKDIV:3; + uint32_t:19; + uint32_t LPCLKDIV3:2; + uint32_t LPCLKDIV2:2; + uint32_t LPCLKDIV1:2; + uint32_t LPCLKDIV0:2; + } B; + } SYSCLK; /* System CLock Register */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t HLT6:1; + uint32_t HLT7:1; + uint32_t:1; + uint32_t HLT9:1; + uint32_t HLT10:1; + uint32_t HLT11:1; + uint32_t HLT12:1; + uint32_t HLT13:1; + uint32_t HLT14:1; + uint32_t HLT15:1; + uint32_t HLT16:1; + uint32_t HLT17:1; + uint32_t HLT18:1; + uint32_t HLT19:1; + uint32_t HLT20:1; + uint32_t HLT21:1; + uint32_t HLT22:1; + uint32_t HLT23:1; + uint32_t:2; + uint32_t HLT26:1; + uint32_t HLT27:1; + uint32_t HLT28:1; + uint32_t HLT29:1; + uint32_t:1; + uint32_t HLT31:1; + } B; + } HLT0; /* Halt Register 0 */ + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t HLT3:1; + uint32_t HLT4:1; + uint32_t:15; + uint32_t HLT20:1; + uint32_t HLT21:1; + uint32_t HLT22:1; + uint32_t HLT23:1; + uint32_t:2; + uint32_t HLT26:1; + uint32_t HLT27:1; + uint32_t HLT28:1; + uint32_t HLT29:1; + uint32_t:2; + } B; + } HLT1; /* Halt Register 1 */ + + union { + uint32_t R; + struct { + uint32_t:6; + uint32_t HLTACK6:1; + uint32_t HLTACK7:1; + uint32_t:1; + uint32_t HLTACK9:1; + uint32_t HLTACK10:1; + uint32_t HLTACK11:1; + uint32_t HLTACK12:1; + uint32_t HLTACK13:1; + uint32_t HLTACK14:1; + uint32_t HLTACK15:1; + uint32_t HLTACK16:1; + uint32_t HLTACK17:1; + uint32_t HLTACK18:1; + uint32_t HLTACK19:1; + uint32_t HLTACK20:1; + uint32_t HLTACK21:1; + uint32_t HLTACK22:1; + uint32_t HLTACK23:1; + uint32_t:2; + uint32_t HLTACK26:1; + uint32_t HLTACK27:1; + uint32_t HLTACK28:1; + uint32_t HLTACK29:1; + uint32_t:1; + uint32_t HLTACK31:1; + } B; + } HLTACK0; /* Halt Acknowledge Register 0 */ + + union { + uint32_t R; + struct { + uint32_t HLTACK0:1; + uint32_t HLTACK1:1; + uint32_t:1; + uint32_t HLTACK3:1; + uint32_t HLTACK4:1; + uint32_t:11; + uint32_t HLTACK20:1; + uint32_t HLTACK21:1; + uint32_t HLTACK22:1; + uint32_t HLTACK23:1; + uint32_t:2; + uint32_t HLTACK26:1; + uint32_t HLTACK27:1; + uint32_t HLTACK28:1; + uint32_t HLTACK29:1; + uint32_t:2; + } B; + } HLTACK1; /* Halt Acknowledge Register 0 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL31:4; + uint32_t EMIOSSEL30:4; + uint32_t EMIOSSEL29:4; + uint32_t EMIOSSEL28:4; + uint32_t EMIOSSEL27:4; + uint32_t EMIOSSEL26:4; + uint32_t EMIOSSEL25:4; + uint32_t EMIOSSEL24:4; + } B; + } EMIOS_SEL0; /* eMIOS Select Register 0 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL23:4; + uint32_t EMIOSSEL22:4; + uint32_t EMIOSSEL21:4; + uint32_t EMIOSSEL20:4; + uint32_t EMIOSSEL19:4; + uint32_t EMIOSSEL18:4; + uint32_t EMIOSSEL17:4; + uint32_t EMIOSSEL16:4; + } B; + } EMIOS_SEL1; /* eMIOS Select Register 1 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL15:4; + uint32_t EMIOSSEL14:4; + uint32_t EMIOSSEL13:4; + uint32_t EMIOSSEL12:4; + uint32_t EMIOSSEL11:4; + uint32_t EMIOSSEL10:4; + uint32_t EMIOSSEL9:4; + uint32_t EMIOSSEL8:4; + } B; + } EMIOS_SEL2; /* eMIOS Select Register 2 */ + + union { + uint32_t R; + struct { + uint32_t EMIOSSEL7:4; + uint32_t EMIOSSEL6:4; + uint32_t EMIOSSEL5:4; + uint32_t EMIOSSEL4:4; + uint32_t EMIOSSEL3:4; + uint32_t EMIOSSEL2:4; + uint32_t EMIOSSEL1:4; + uint32_t EMIOSSEL0:4; + } B; + } EMIOS_SEL3; /* eMIOS Select Register 3 */ + + union { + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } ISEL2A; /* External Interrupt Select Register 2A */ + + int32_t SIU_reserved9[142]; + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t PB:16; + } B; + } PGPDO0; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDO1; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDO2; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDO3; /* Parallel GPIO Pin Data Output Register */ + + union { + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t PK:11; + uint32_t:5; + } B; + } PGPDO4; /* Parallel GPIO Pin Data Output Register */ + + int32_t SIU_reserved10[11]; + + union { + uint32_t R; + struct { + uint32_t PA:16; + uint32_t PB:16; + } B; + } PGPDI0; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PC:16; + uint32_t PD:16; + } B; + } PGPDI1; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PE:16; + uint32_t PF:16; + } B; + } PGPDI2; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PG:16; + uint32_t PH:16; + } B; + } PGPDI3; /* Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PJ:16; + uint32_t PK:11; + uint32_t:5; + } B; + } PGPDI4; /* Parallel GPIO Pin Data Input Register */ + + int32_t SIU_reserved11[12]; + + union { + uint32_t R; + struct { + uint32_t PB_MASK:16; + uint32_t PB:16; + } B; + } MPGPDO1; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PC_MASK:16; + uint32_t PC:16; + } B; + } MPGPDO2; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PD_MASK:16; + uint32_t PD:16; + } B; + } MPGPDO3; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PE_MASK:16; + uint32_t PE:16; + } B; + } MPGPDO4; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PF_MASK:16; + uint32_t PF:16; + } B; + } MPGPDO5; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PG_MASK:16; + uint32_t PG:16; + } B; + } MPGPDO6; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PH_MASK:16; + uint32_t PH:16; + } B; + } MPGPDO7; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PJ_MASK:16; + uint32_t PJ:16; + } B; + } MPGPDO8; /* Masked Parallel GPIO Pin Data Input Register */ + + union { + uint32_t R; + struct { + uint32_t PK_MASK:11; + uint32_t:5; + uint32_t PK:11; + uint32_t:5; + } B; + } MPGPDO9; /* Masked Parallel GPIO Pin Data Input Register */ + + int32_t SIU_reserved12[22]; + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPIAH; /* Masked Serial GPO for DSPI_A High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPIAL; /* Masked Serial GPO for DSPI_A Low Register */ + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPIBH; /* Masked Serial GPO for DSPI_B High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPIBL; /* Masked Serial GPO for DSPI_B Low Register */ + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPICH; /* Masked Serial GPO for DSPI_C High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPICL; /* Masked Serial GPO for DSPI_C Low Register */ + + union { + uint32_t R; + struct { + uint32_t MASK31:1; + uint32_t MASK30:1; + uint32_t MASK29:1; + uint32_t MASK28:1; + uint32_t MASK27:1; + uint32_t MASK26:1; + uint32_t MASK25:1; + uint32_t MASK24:1; + uint32_t MASK23:1; + uint32_t MASK22:1; + uint32_t MASK21:1; + uint32_t MASK20:1; + uint32_t MASK19:1; + uint32_t MASK18:1; + uint32_t MASK17:1; + uint32_t MASK16:1; + uint32_t DATA31:1; + uint32_t DATA30:1; + uint32_t DATA29:1; + uint32_t DATA28:1; + uint32_t DATA27:1; + uint32_t DATA26:1; + uint32_t DATA25:1; + uint32_t DATA24:1; + uint32_t DATA23:1; + uint32_t DATA22:1; + uint32_t DATA21:1; + uint32_t DATA20:1; + uint32_t DATA19:1; + uint32_t DATA18:1; + uint32_t DATA17:1; + uint32_t DATA16:1; + } B; + } DSPIDH; /* Masked Serial GPO for DSPI_D High Register */ + + union { + uint32_t R; + struct { + uint32_t MASK15:1; + uint32_t MASK14:1; + uint32_t MASK13:1; + uint32_t MASK12:1; + uint32_t MASK11:1; + uint32_t MASK10:1; + uint32_t MASK9:1; + uint32_t MASK8:1; + uint32_t MASK7:1; + uint32_t MASK6:1; + uint32_t MASK5:1; + uint32_t MASK4:1; + uint32_t MASK3:1; + uint32_t MASK2:1; + uint32_t MASK1:1; + uint32_t MASK0:1; + uint32_t DATA15:1; + uint32_t DATA14:1; + uint32_t DATA13:1; + uint32_t DATA12:1; + uint32_t DATA11:1; + uint32_t DATA10:1; + uint32_t DATA9:1; + uint32_t DATA8:1; + uint32_t DATA7:1; + uint32_t DATA6:1; + uint32_t DATA5:1; + uint32_t DATA4:1; + uint32_t DATA3:1; + uint32_t DATA2:1; + uint32_t DATA1:1; + uint32_t DATA0:1; + } B; + } DSPIDL; /* Masked Serial GPO for DSPI_D Low Register */ + + int32_t SIU_reserved13[9]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSA; /* EMIOS A Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPIAH31:1; + uint32_t DSPIAH30:1; + uint32_t DSPIAH29:1; + uint32_t DSPIAH28:1; + uint32_t DSPIAH27:1; + uint32_t DSPIAH26:1; + uint32_t DSPIAH25:1; + uint32_t DSPIAH24:1; + uint32_t DSPIAH23:1; + uint32_t DSPIAH22:1; + uint32_t DSPIAH21:1; + uint32_t DSPIAH20:1; + uint32_t DSPIAH19:1; + uint32_t DSPIAH18:1; + uint32_t DSPIAH17:1; + uint32_t DSPIAH16:1; + uint32_t DSPIAL15:1; + uint32_t DSPIAL14:1; + uint32_t DSPIAL13:1; + uint32_t DSPIAL12:1; + uint32_t DSPIAL11:1; + uint32_t DSPIAL10:1; + uint32_t DSPIAL9:1; + uint32_t DSPIAL8:1; + uint32_t DSPIAL7:1; + uint32_t DSPIAL6:1; + uint32_t DSPIAL5:1; + uint32_t DSPIAL4:1; + uint32_t DSPIAL3:1; + uint32_t DSPIAL2:1; + uint32_t DSPIAL1:1; + uint32_t DSPIAL0:1; + } B; + } DSPIAHLA; /* DSPIAH/L Select Register for DSPI A */ + + int32_t SIU_reserved14[2]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSB; /* EMIOS B Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPIBH31:1; + uint32_t DSPIBH30:1; + uint32_t DSPIBH29:1; + uint32_t DSPIBH28:1; + uint32_t DSPIBH27:1; + uint32_t DSPIBH26:1; + uint32_t DSPIBH25:1; + uint32_t DSPIBH24:1; + uint32_t DSPIBH23:1; + uint32_t DSPIBH22:1; + uint32_t DSPIBH21:1; + uint32_t DSPIBH20:1; + uint32_t DSPIBH19:1; + uint32_t DSPIBH18:1; + uint32_t DSPIBH17:1; + uint32_t DSPIBH16:1; + uint32_t DSPIBL15:1; + uint32_t DSPIBL14:1; + uint32_t DSPIBL13:1; + uint32_t DSPIBL12:1; + uint32_t DSPIBL11:1; + uint32_t DSPIBL10:1; + uint32_t DSPIBL9:1; + uint32_t DSPIBL8:1; + uint32_t DSPIBL7:1; + uint32_t DSPIBL6:1; + uint32_t DSPIBL5:1; + uint32_t DSPIBL4:1; + uint32_t DSPIBL3:1; + uint32_t DSPIBL2:1; + uint32_t DSPIBL1:1; + uint32_t DSPIBL0:1; + } B; + } DSPIBHLB; /* DSPIBH/L Select Register for DSPI B */ + + int32_t SIU_reserved115[2]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSC; /* EMIOS C Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPICH31:1; + uint32_t DSPICH30:1; + uint32_t DSPICH29:1; + uint32_t DSPICH28:1; + uint32_t DSPICH27:1; + uint32_t DSPICH26:1; + uint32_t DSPICH25:1; + uint32_t DSPICH24:1; + uint32_t DSPICH23:1; + uint32_t DSPICH22:1; + uint32_t DSPICH21:1; + uint32_t DSPICH20:1; + uint32_t DSPICH19:1; + uint32_t DSPICH18:1; + uint32_t DSPICH17:1; + uint32_t DSPICH16:1; + uint32_t DSPICL15:1; + uint32_t DSPICL14:1; + uint32_t DSPICL13:1; + uint32_t DSPICL12:1; + uint32_t DSPICL11:1; + uint32_t DSPICL10:1; + uint32_t DSPICL9:1; + uint32_t DSPICL8:1; + uint32_t DSPICL7:1; + uint32_t DSPICL6:1; + uint32_t DSPICL5:1; + uint32_t DSPICL4:1; + uint32_t DSPICL3:1; + uint32_t DSPICL2:1; + uint32_t DSPICL1:1; + uint32_t DSPICL0:1; + } B; + } DSPICHLC; /* DSPIAH/L Select Register for DSPI C */ + + int32_t SIU_reserved16[2]; + + union { + uint32_t R; + struct { + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + } B; + } EMIOSD; /* EMIOS D Select Register */ + + union { + uint32_t R; + struct { + uint32_t DSPIDH31:1; + uint32_t DSPIDH30:1; + uint32_t DSPIDH29:1; + uint32_t DSPIDH28:1; + uint32_t DSPIDH27:1; + uint32_t DSPIDH26:1; + uint32_t DSPIDH25:1; + uint32_t DSPIDH24:1; + uint32_t DSPIDH23:1; + uint32_t DSPIDH22:1; + uint32_t DSPIDH21:1; + uint32_t DSPIDH20:1; + uint32_t DSPIDH19:1; + uint32_t DSPIDH18:1; + uint32_t DSPIDH17:1; + uint32_t DSPIDH16:1; + uint32_t DSPIDL15:1; + uint32_t DSPIDL14:1; + uint32_t DSPIDL13:1; + uint32_t DSPIDL12:1; + uint32_t DSPIDL11:1; + uint32_t DSPIDL10:1; + uint32_t DSPIDL9:1; + uint32_t DSPIDL8:1; + uint32_t DSPIDL7:1; + uint32_t DSPIDL6:1; + uint32_t DSPIDL5:1; + uint32_t DSPIDL4:1; + uint32_t DSPIDL3:1; + uint32_t DSPIDL2:1; + uint32_t DSPIDL1:1; + uint32_t DSPIDL0:1; + } B; + } DSPIDHLD; /* DSPIAH/L Select Register for DSPI D */ + + }; /* end of SIU_tag */ +/**************************************************************************/ +/* MODULE : STM */ +/**************************************************************************/ + struct STM_tag { + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t CPS:8; + uint32_t:6; + uint32_t FRZ:1; + uint32_t TEN:1; + } B; + } CR; /* STM Control Register */ + + union { + uint32_t R; + } CNT; /* STM Count Register */ + + int32_t STM_reserved[2]; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register 0 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register 0 */ + + union { + uint32_t R; + } CMP0; /* STM Channel Compare Register 0 */ + + int32_t STM_reserved1; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register 1 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register 1 */ + + union { + uint32_t R; + } CMP1; /* STM Channel Compare Register 1 */ + + int32_t STM_reserved2; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register 2 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register 2 */ + + union { + uint32_t R; + } CMP2; /* STM Channel Compare Register 2 */ + + int32_t STM_reserved3; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register 3 */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register 3 */ + + union { + uint32_t R; + } CMP3; /* STM Channel Compare Register 3 */ + + }; /* end of STM_tag */ +/**************************************************************************/ +/* MODULE : SWT */ +/**************************************************************************/ + struct SWT_tag { + union { + uint32_t R; + struct { + uint32_t MAP0:1; + uint32_t MAP1:1; + uint32_t MAP2:1; + uint32_t MAP3:1; + uint32_t MAP4:1; + uint32_t MAP5:1; + uint32_t MAP6:1; + uint32_t MAP7:1; + uint32_t:14; + uint32_t KEY:1; + uint32_t RIA:1; + uint32_t WND:1; + uint32_t ITR:1; + uint32_t HLK:1; + uint32_t SLK:1; + uint32_t:2; + uint32_t FRZ:1; + uint32_t WEN:1; + } B; + } CR; /* SWT Control Register */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } IR; /* SWT Interrupt Register */ + + union { + uint32_t R; + struct { + uint32_t WTO:32; + } B; + } TO; /* SWT Time-Out Register */ + + union { + uint32_t R; + struct { + uint32_t WST:32; + } B; + } WN; /* SWT Window Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t WSC:16; + } B; + } SR; /* SWT Service Register */ + + union { + uint32_t R; + struct { + uint32_t CNT:32; + } B; + } CO; /* SWT Counter Output Register */ + + union { + uint32_t R; + struct { + uint32_t:16; + uint32_t SK:16; + } B; + } SK; /* SWT Service Key Register */ + + }; /* end of SWT_tag */ + +/* Define memories */ + +#define SRAM0_START 0x40000000UL +#define SRAM0_SIZE 0x80000UL +#define SRAM0_END 0x4007FFFFUL + +#define SRAM1_START 0x40080000UL +#define SRAM1_SIZE 0x14000UL +#define SRAM1_END 0x40093FFFUL + +#define FLASH_START 0x0UL +#define FLASH_SIZE 0x200000UL +#define FLASH_END 0x1FFFFFUL + +/* Define instances of modules AIPS_A */ +#define MLB (*(volatile struct MLB_tag *) 0xC3F84000UL) +#define I2C_C (*(volatile struct I2C_tag *) 0xC3F88000UL) +#define I2C_D (*(volatile struct I2C_tag *) 0xC3F8C000UL) +#define DSPI_C (*(volatile struct DSPI_tag *) 0xC3F90000UL) +#define DSPI_D (*(volatile struct DSPI_tag *) 0xC3F94000UL) +#define ESCI_J (*(volatile struct ESCI_tag *) 0xC3FA0000UL) +#define ESCI_K (*(volatile struct ESCI_tag *) 0xC3FA4000UL) +#define ESCI_L (*(volatile struct ESCI_tag *) 0xC3FA8000UL) +#define ESCI_M (*(volatile struct ESCI_tag *) 0xC3FAC000UL) +#define FR (*(volatile struct FR_tag *) 0xC3FDC000UL) + +/* Define instances of modules AIPS_B */ +#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL) +#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL) +#define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL) +#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL) +#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL) +#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL) +#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL) +#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL) +#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL) +#define ADC (*(volatile struct ADC_tag *) 0xFFF80000UL) +#define I2C_A (*(volatile struct I2C_tag *) 0xFFF88000UL) +#define I2C_B (*(volatile struct I2C_tag *) 0xFFF8C000UL) +#define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL) +#define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL) +#define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL) +#define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL) +#define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL) +#define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL) +#define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL) +#define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL) +#define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL) +#define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL) +#define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL) +#define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL) +#define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL) +#define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL) +#define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL) +#define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL) +#define CTU (*(volatile struct CTU_tag *) 0xFFFD8000UL) +#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL) +#define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL) +#define PIT_RTI (*(volatile struct PIT_tag *) 0xFFFE0000UL) +#define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL) +#define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL) +#define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL) +#define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL) +#define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5668_H */ diff --git a/bsps/powerpc/include/mpc55xx/fsl-mpc567x.h b/bsps/powerpc/include/mpc55xx/fsl-mpc567x.h new file mode 100644 index 0000000000..31a132a096 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/fsl-mpc567x.h @@ -0,0 +1,6630 @@ +/* + * Modifications of the original file provided by Freescale are: + * + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************/ +/* FILE NAME: mpc5674f.h COPYRIGHT (c) Freescale 2009 */ +/* VERSION: 1.04 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contains all of the register and bit field definitions for */ +/* MPC5674F. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* NOTE: Branch pulled at version 0.87 for mpc5674_c.h version 1.00 */ +/* 1.00 B. Terry Corrected DECFILT addresses and added */ +/* 4 additional filters for Rev. 2 */ +/* 1.01 B. Terry 16/Nov/09 Corrected bit definitions in SIUDIV */ +/* register. */ +/* 1.02 B. Terry 19/Nov/09 Added ISEL8, ISEL9, ISEL10, and ISEL11 */ +/* regs to SIU tag. (Mamba 2 features) */ +/* 1.03 B. Terry 19/Nov/09 Renamed ISEL10 and ISEL11 to DECFIL1 */ +/* and DECFIL2 to match RM. */ +/* 1.04 B. Terry 22/Jan/10 Updated bitfields of MPU RGDx Word2 */ +/* register to reflect Mamba 2. Added */ +/* MXCR and MXSR registers to DecFilt. */ +/* Removed pre-release rev history. */ +/**************************************************************************/ + +#ifndef _MPC5674F_H_ +#define _MPC5674F_H_ + +#ifndef ASM + +#include <stdint.h> + +#include <mpc55xx/regs-edma.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif + +/****************************************************************************/ +/* MODULE : PBRIDGE_A Peripheral Bridge */ +/****************************************************************************/ + + struct PBRIDGE_A_tag { + + union { /* Master Privilege Control Register 0*/ + uint32_t R; + struct { + uint32_t MBW0:1; /* z7 Core */ + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; /* Nexus */ + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; /* Reserved */ + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; /* Reserved */ + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + uint32_t MBW4:1; /* eDMA A */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + uint32_t MBW5:1; /* eDMA B */ + uint32_t MTR5:1; + uint32_t MTW5:1; + uint32_t MPL5:1; + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + uint32_t MBW7:1; /* EBI */ + uint32_t MTR7:1; + uint32_t MTW7:1; + uint32_t MPL7:1; + } B; + } MPCR; + + union { /* Master Privilege Control Register 1 */ + uint32_t R; + struct { + uint32_t:32; /* reserved */ + } B; + } MPCR1; + + uint32_t PBRIDGE_A_reserved0008[6]; /* 0x0008-0x001F */ + + union { /* Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* PBRIDGE_A */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } PACR0; + + uint32_t PBRIDGE_A_reserved0024[7]; /* 0x0024-0x003F */ + + union { /* Off-Platform Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* FMPLL */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* EBI control */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* Flash A control */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; /* Flash B control */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; /* SIU */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR0; + + union { /* Off-Platform Peripheral Access Control Register 1 */ + uint32_t R; + struct { + uint32_t BW0:1; /* EMIOS */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW7:1; /* PMC */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR1; + + union { /* Off-Platform Peripheral Access Control Register 2 */ + uint32_t R; + struct { + uint32_t BW0:1; /* eTPU */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t BW2:1; /* eTPU PRAM */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; /* eTPU PRAM mirror */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t BW4:1; /* eTPU SCM */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t BW5:1; /* eTPU SCM */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR2; + + union { /* Off-Platform Peripheral Access Control Register 3 */ + uint32_t R; + struct { + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* PIT/RTI */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR3; + + uint32_t PBRIDGE_A_reserved0050[4076]; /* 0x0050-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : PBRIDGE_B Peripheral Bridge */ +/****************************************************************************/ + + struct PBRIDGE_B_tag { + + union { /* Master Privilege Control Register 0 */ + uint32_t R; + struct { + uint32_t MBW0:1; /* z7 Core */ + uint32_t MTR0:1; + uint32_t MTW0:1; + uint32_t MPL0:1; + uint32_t MBW1:1; /* Nexus */ + uint32_t MTR1:1; + uint32_t MTW1:1; + uint32_t MPL1:1; + uint32_t MBW2:1; /* Reserved */ + uint32_t MTR2:1; + uint32_t MTW2:1; + uint32_t MPL2:1; + uint32_t MBW3:1; /* Reserved */ + uint32_t MTR3:1; + uint32_t MTW3:1; + uint32_t MPL3:1; + uint32_t MBW4:1; /* eDMA A */ + uint32_t MTR4:1; + uint32_t MTW4:1; + uint32_t MPL4:1; + uint32_t MBW5:1; /* eDMA B */ + uint32_t MTR5:1; + uint32_t MTW5:1; + uint32_t MPL5:1; + uint32_t MBW6:1; /* FLEXRAY */ + uint32_t MTR6:1; + uint32_t MTW6:1; + uint32_t MPL6:1; + uint32_t MBW7:1; /* EBI */ + uint32_t MTR7:1; + uint32_t MTW7:1; + uint32_t MPL7:1; + } B; + } MPCR; + + union { /* Master Privilege Control Register 1 */ + uint32_t R; + struct { + uint32_t:32; /* Reserved */ + + } B; + } MPCR1; + + uint32_t PBRIDGE_B_reserved0008[6]; /* 0x0008-0x001F */ + + union { /* Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* PBRIDGE B */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* XBAR */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* MPU */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } PACR0; + + union { /* Peripheral Access Control Register 1 */ + uint32_t R; + struct { + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW6:1; /* SWT */ + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; /* STM */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } PACR1; + + union { /* Peripheral Access Control Register 2 */ + uint32_t R; + struct { + uint32_t BW0:1; /* ECSM */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* eDMA A */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* INTC */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW5:1; /* eDMA B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } PACR2; + + uint32_t PBRIDGE_B_reserved002C[5]; /* 0x002C-0x003F */ + + union { /* Off-Platform Peripheral Access Control Register 0 */ + uint32_t R; + struct { + uint32_t BW0:1; /* eQADC A */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* eQADC B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* Decimation Filters A, B, C, D */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* DSPI_A */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t BW5:1; /* DSPI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t BW6:1; /* DSPI_C */ + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t BW7:1; /* DSPI_D */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR0; + + union { /* Off-Platform Peripheral Access Control Register 1 */ + uint32_t R; + struct { + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW4:1; /* ESCI_A */ + uint32_t SP4:1; + uint32_t WP4:1; + uint32_t TP4:1; + uint32_t BW5:1; /* ESCI_B */ + uint32_t SP5:1; + uint32_t WP5:1; + uint32_t TP5:1; + uint32_t BW6:1; /* ESCI_C */ + uint32_t SP6:1; + uint32_t WP6:1; + uint32_t TP6:1; + uint32_t:4; /* Reserved */ + } B; + } OPACR1; + + union { /* Off-Platform Peripheral Access Control Register 2 */ + uint32_t R; + struct { + uint32_t BW0:1; /* FlexCAN_A */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t BW1:1; /* FlexCAN_B */ + uint32_t SP1:1; + uint32_t WP1:1; + uint32_t TP1:1; + uint32_t BW2:1; /* FlexCAN_C */ + uint32_t SP2:1; + uint32_t WP2:1; + uint32_t TP2:1; + uint32_t BW3:1; /* FlexCAN_D */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + } B; + } OPACR2; + + union { /* Off-Platform Peripheral Access Control Register 3 */ + uint32_t R; + struct { + uint32_t BW0:1; /* FlexRAY */ + uint32_t SP0:1; + uint32_t WP0:1; + uint32_t TP0:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW3:1; /* Temp Sensor */ + uint32_t SP3:1; + uint32_t WP3:1; + uint32_t TP3:1; + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t:4; /* Reserved */ + uint32_t BW7:1; /* BAM */ + uint32_t SP7:1; + uint32_t WP7:1; + uint32_t TP7:1; + } B; + } OPACR3; + + uint32_t PBRIDGE_B_reserved0050[4076]; /* 0x0050-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + + struct FMPLL_tag { + + uint32_t FMPLL_reserved0000; /* 0x0000-0x0003 */ + + union FMPLL_SYNSR_tag { /* FMPLL Synthesizer Status Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t LOLF:1; + uint32_t LOC:1; + uint32_t MODE:1; + uint32_t PLLSEL:1; + uint32_t PLLREF:1; + uint32_t LOCKS:1; + uint32_t LOCK:1; + uint32_t LOCF:1; + uint32_t CALDONE:1; + uint32_t CALPASS:1; + } B; + } SYNSR; + + union FMPLL_ESYNCR1_tag {/* FMPLL Enhanced Synthesizer Control Register 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CLKCFG:3; + uint32_t:8; + uint32_t EPREDIV:4; + uint32_t :8; + uint32_t EMFD:8; + } B; + } ESYNCR1; + + union FMPLL_ESYNCR2_tag {/* FMPLL Enhanced Synthesizer Control Register 2 */ + uint32_t R; + struct { + uint32_t:8; + uint32_t LOCEN:1; + uint32_t LOLRE:1; + uint32_t LOCRE:1; + uint32_t LOLIRQ:1; + uint32_t LOCIRQ:1; + uint32_t:1; + uint32_t ERATE:2; + uint32_t CLKCFG_DIS:1; + uint32_t:4; + uint32_t EDEPTH:3; + uint32_t:2; + uint32_t ERFD:6; + } B; + } ESYNCR2; + + uint32_t FMPLL_reserved0010[4092]; /* 0x0010-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : External Bus Interface (EBI) */ +/****************************************************************************/ + + struct EBI_CS_tag { + uint32_t ebi_cs_reserved [2]; + }; + + struct EBI_CAL_CS_tag { + union { /* Calibration Base Register Bank */ + uint32_t R; + struct { + uint32_t BA:17; + uint32_t:3; + uint32_t PS:1; + uint32_t:3; + uint32_t AD_MUX:1; + uint32_t BL:1; + uint32_t WEBS:1; + uint32_t TBDIP:1; + uint32_t:1; + uint32_t SETA:1; + uint32_t BI:1; + uint32_t V:1; + } B; + } BR; + + union { /* Calibration Option Register Bank */ + uint32_t R; + struct { + uint32_t AM:17; + uint32_t:7; + uint32_t SCY:4; + uint32_t:1; + uint32_t BSCY:2; + uint32_t:1; + } B; + } OR; + }; + + struct EBI_tag { + + union EBI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ACGE:1; + uint32_t:8; + uint32_t MDIS:1; + uint32_t:3; + uint32_t D16_31:1; + uint32_t AD_MUX:1; + uint32_t DBM:1; + } B; + } MCR; + + uint32_t EBI_reserved0004; /* 0x0004-0x0007 */ + + union { /* Transfer Error Status Register */ + uint32_t R; + struct { + uint32_t:30; + uint32_t TEAF:1; + uint32_t BMTF:1; + } B; + } TESR; + + union { /* Bus Monitor Control Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t BMT:8; + uint32_t BME:1; + uint32_t:7; + } B; + } BMCR; + + /* Base/Option registers */ + struct EBI_CS_tag CS[4]; + + uint32_t EBI_reserved0030[4]; /* 0x0030-0x003F */ + + /* Calibration registers */ + struct EBI_CAL_CS_tag CAL_CS[4]; + + uint32_t EBI_reserved0060[4000]; /* 0x0060-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ + + struct FLASH_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:5; + uint32_t SIZE:3; + uint32_t:1; + uint32_t LAS:3; + uint32_t:3; + uint32_t MAS:1; + uint32_t EER:1; + uint32_t RWE:1; + uint32_t SBC:1; + uint32_t:1; + uint32_t PEAS:1; + uint32_t DONE:1; + uint32_t PEG:1; + uint32_t:4; + uint32_t PGM:1; + uint32_t PSUS:1; + uint32_t ERS:1; + uint32_t ESUS:1; + uint32_t EHV:1; + } B; + } MCR; + + union LMLR_tag { /* Low/Mid Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t LME:1; + uint32_t:10; + uint32_t SLOCK:1; + uint32_t:2; + uint32_t MLOCK:2; + uint32_t:6; + uint32_t LLOCK:10; + } B; + } LMLR; /* Legacy naming - refer to LML in Reference Manual */ + + union HLR_tag { /* High Address Space Block Locking Register */ + uint32_t R; + struct { + uint32_t HBE:1; + uint32_t:25; + uint32_t HBLOCK:6; /* Legacy naming - refer to HLOCK in Reference Manual */ + } B; + } HLR; /* Legacy naming - refer to HBL in Reference Manual */ + + union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */ + uint32_t R; + struct { + uint32_t SLE:1; + uint32_t:10; + uint32_t SSLOCK:1; + uint32_t:2; + uint32_t SMLOCK:2; + uint32_t:6; + uint32_t SLLOCK:10; + } B; + } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */ + + union { /* Low/Mid Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MSEL:2; + uint32_t:6; + uint32_t LSEL:10; + } B; + } LMSR; /* Legacy naming - refer to LMS in Reference Manual */ + + union { /* High Address Space Block Select Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t HBSEL:6; /* Legacy naming - refer to HSEL in Reference Manual */ + } B; + } HSR; /* Legacy naming - refer to HBS in Reference Manual */ + + union { /* Address Register */ + uint32_t R; + struct { + uint32_t SAD:1; + uint32_t:13; + uint32_t ADDR:15; + uint32_t:3; + } B; + } AR; /* Legacy naming - refer to ADR in Reference Manual */ + + union { /* Platform Flash Configuration Register 1 */ + uint32_t R; + struct { + uint32_t:7; + uint32_t M8PFE:1; /* z7 Nexus */ + uint32_t:1; /* EBI Testing - Reserved */ + uint32_t M6PFE:1; /* FlexRay */ + uint32_t M5PFE:1; /* eDMA_B */ + uint32_t M4PFE:1; /* eDMA_A */ + uint32_t:1; /* Reserved */ + uint32_t:1; /* Reserved */ + uint32_t:1; /* Reserved */ + uint32_t M0PFE:1; /* z7 Core */ + uint32_t APC:3; + uint32_t WWSC:2; + uint32_t RWSC:3; + uint32_t:1; + uint32_t DPFEN:1; + uint32_t:1; + uint32_t IPFEN:1; + uint32_t:1; + uint32_t PFLIM:2; + uint32_t BFEN:1; + } B; + } BIUCR; /* Legacy naming - PFCR1 */ + + union { /*Platform Flash Access Protection Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t M8AP:2; /* z7 Nexus */ + uint32_t:2; /* EBI Testing - Reserved */ + uint32_t M6AP:2; /* FlexRay */ + uint32_t M5AP:2; /* eDMA_B */ + uint32_t M4AP:2; /* eDMA_A */ + uint32_t:2; /* Reserved */ + uint32_t:2; /* Reserved */ + uint32_t:2; /* Reserved */ + uint32_t M0AP:2; /* z7 Core */ + } B; + } BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */ + + union { /* Platform Flash Configuration Register 2 */ + uint32_t R; + struct { + uint32_t LBCFG:2; + uint32_t:30; + } B; + } BIUCR2; + + uint32_t FLASH_reserved0028[4086]; /* 0x0028-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + int32_t SIU_reserved0000 /* 0x0000-0x0003 */; + + union { /* MCU ID Register */ + uint32_t R; + struct { + uint32_t PARTNUM:16; + uint32_t PKG:4; + uint32_t:4; + uint32_t MAJOR_REV:4; + uint32_t MINOR_REV:4; + } B; + } MIDR; + + int32_t SIU_reserved0008; /* 0x0008-0x000B */ + + union { /* Reset Status Register */ + uint32_t R; + struct { + uint32_t PORS:1; + uint32_t ERS:1; + uint32_t LLRS:1; + uint32_t LCRS:1; + uint32_t WDRS:1; + uint32_t CRS:1; + uint32_t SWTRS:1; + uint32_t:7; + uint32_t SSRS:1; + uint32_t SERF:1; + uint32_t WKPCFG:1; + uint32_t:11; + uint32_t ABR:1; + uint32_t BOOTCFG:2; + uint32_t RGF:1; + } B; + } RSR; + + union { /* System Reset Control Register */ + uint32_t R; + struct { + uint32_t SSR:1; + uint32_t SER:1; + uint32_t:30; // Removed CRE bit + } B; + } SRCR; + + union SIU_EISR_tag { /* External Interrupt Status Register */ + uint32_t R; + struct { + uint32_t NMI:1; + uint32_t:15; + uint32_t EIF15:1; + uint32_t EIF14:1; + uint32_t EIF13:1; + uint32_t EIF12:1; + uint32_t EIF11:1; + uint32_t EIF10:1; + uint32_t EIF9:1; + uint32_t EIF8:1; + uint32_t EIF7:1; + uint32_t EIF6:1; + uint32_t EIF5:1; + uint32_t EIF4:1; + uint32_t EIF3:1; + uint32_t EIF2:1; + uint32_t EIF1:1; + uint32_t EIF0:1; + } B; + } EISR; + + union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */ + uint32_t R; + struct { + uint32_t NMISEL8:1; + uint32_t:7; + uint32_t NMISEL0:1; + uint32_t:7; + uint32_t EIRE15:1; + uint32_t EIRE14:1; + uint32_t EIRE13:1; + uint32_t EIRE12:1; + uint32_t EIRE11:1; + uint32_t EIRE10:1; + uint32_t EIRE9:1; + uint32_t EIRE8:1; + uint32_t EIRE7:1; + uint32_t EIRE6:1; + uint32_t EIRE5:1; + uint32_t EIRE4:1; + uint32_t EIRE3:1; + uint32_t EIRE2:1; + uint32_t EIRE1:1; + uint32_t EIRE0:1; + } B; + } DIRER; + + union SIU_DIRSR_tag { /* DMA/Interrupt Request Select Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DIRS3:1; + uint32_t DIRS2:1; + uint32_t DIRS1:1; + uint32_t DIRS0:1; + } B; + } DIRSR; + + union { /* Overrun Status Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t OVF15:1; + uint32_t OVF14:1; + uint32_t OVF13:1; + uint32_t OVF12:1; + uint32_t OVF11:1; + uint32_t OVF10:1; + uint32_t OVF9:1; + uint32_t OVF8:1; + uint32_t OVF7:1; + uint32_t OVF6:1; + uint32_t OVF5:1; + uint32_t OVF4:1; + uint32_t OVF3:1; + uint32_t OVF2:1; + uint32_t OVF1:1; + uint32_t OVF0:1; + } B; + } OSR; + + union SIU_ORER_tag { /* Overrun Request Enable Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ORE15:1; + uint32_t ORE14:1; + uint32_t ORE13:1; + uint32_t ORE12:1; + uint32_t ORE11:1; + uint32_t ORE10:1; + uint32_t ORE9:1; + uint32_t ORE8:1; + uint32_t ORE7:1; + uint32_t ORE6:1; + uint32_t ORE5:1; + uint32_t ORE4:1; + uint32_t ORE3:1; + uint32_t ORE2:1; + uint32_t ORE1:1; + uint32_t ORE0:1; + } B; + } ORER; + + union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IREE_NMI8:1; + uint32_t:7; + uint32_t IREE_NMI0:1; + uint32_t:7; + uint32_t IREE15:1; + uint32_t IREE14:1; + uint32_t IREE13:1; + uint32_t IREE12:1; + uint32_t IREE11:1; + uint32_t IREE10:1; + uint32_t IREE9:1; + uint32_t IREE8:1; + uint32_t IREE7:1; + uint32_t IREE6:1; + uint32_t IREE5:1; + uint32_t IREE4:1; + uint32_t IREE3:1; + uint32_t IREE2:1; + uint32_t IREE1:1; + uint32_t IREE0:1; + } B; + } IREER; + + union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */ + uint32_t R; + struct { + uint32_t IFEE_NMI8:1; + uint32_t:7; + uint32_t IFEE_NMI0:1; + uint32_t:7; + uint32_t IFEE15:1; + uint32_t IFEE14:1; + uint32_t IFEE13:1; + uint32_t IFEE12:1; + uint32_t IFEE11:1; + uint32_t IFEE10:1; + uint32_t IFEE9:1; + uint32_t IFEE8:1; + uint32_t IFEE7:1; + uint32_t IFEE6:1; + uint32_t IFEE5:1; + uint32_t IFEE4:1; + uint32_t IFEE3:1; + uint32_t IFEE2:1; + uint32_t IFEE1:1; + uint32_t IFEE0:1; + } B; + } IFEER; + + union SIU_IDFR_tag { /* External IRQ Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } IDFR; + + union { /* External IRQ Filtered Input Register */ + uint32_t R; + struct { + uint32_t FI31:1; + uint32_t FI30:1; + uint32_t FI29:1; + uint32_t FI28:1; + uint32_t FI27:1; + uint32_t FI26:1; + uint32_t FI25:1; + uint32_t FI24:1; + uint32_t FI23:1; + uint32_t FI22:1; + uint32_t FI21:1; + uint32_t FI20:1; + uint32_t FI19:1; + uint32_t FI18:1; + uint32_t FI17:1; + uint32_t FI16:1; + uint32_t FI15:1; + uint32_t FI14:1; + uint32_t FI13:1; + uint32_t FI12:1; + uint32_t FI11:1; + uint32_t FI10:1; + uint32_t FI9:1; + uint32_t FI8:1; + uint32_t FI7:1; + uint32_t FI6:1; + uint32_t FI5:1; + uint32_t FI4:1; + uint32_t FI3:1; + uint32_t FI2:1; + uint32_t FI1:1; + uint32_t FI0:1; + } B; + } IFIR; + + int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */ + + union SIU_PCR_tag { /* Pad Configuration Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t PA:3; + uint16_t OBE:1; + uint16_t IBE:1; + uint16_t DSC:2; + uint16_t ODE:1; + uint16_t HYS:1; + uint16_t SRC:2; + uint16_t WPE:1; + uint16_t WPS:1; + } B; + } PCR[512]; + + int16_t SIU_reserved0440[224]; /* 0x0440-0x05FF */ + + union { /* GPIO Pin Data Output Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDO:1; + } B; + } GPDO[512]; + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI[256]; + + uint32_t SIU_reserved0900; /* 0x0900-0x0903 */ + + union { /* External IRQ Input Select Register */ + uint32_t R; + struct { + uint32_t ESEL15:2; + uint32_t ESEL14:2; + uint32_t ESEL13:2; + uint32_t ESEL12:2; + uint32_t ESEL11:2; + uint32_t ESEL10:2; + uint32_t ESEL9:2; + uint32_t ESEL8:2; + uint32_t ESEL7:2; + uint32_t ESEL6:2; + uint32_t ESEL5:2; + uint32_t ESEL4:2; + uint32_t ESEL3:2; + uint32_t ESEL2:2; + uint32_t ESEL1:2; + uint32_t ESEL0:2; + } B; + } EIISR; + + union { /* DSPI Input Select Register */ + uint32_t R; + struct { + uint32_t SINSELA:2; + uint32_t SSSELA:2; + uint32_t SCKSELA:2; + uint32_t TRIGSELA:2; + uint32_t SINSELB:2; + uint32_t SSSELB:2; + uint32_t SCKSELB:2; + uint32_t TRIGSELB:2; + uint32_t SINSELC:2; + uint32_t SSSELC:2; + uint32_t SCKSELC:2; + uint32_t TRIGSELC:2; + uint32_t SINSELD:2; + uint32_t SSSELD:2; + uint32_t SCKSELD:2; + uint32_t TRIGSELD:2; + } B; + } DISR; + + int32_t SIU_reserved090C; /* 0x090C-0x090F */ + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL5_0:7; + uint32_t:1; + uint32_t CTSEL4_0:7; + uint32_t:1; + uint32_t CTSEL3_0:7; + uint32_t:1; + uint32_t CTSEL2_0:7; + } B; + } ISEL4; + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL1_0:7; + uint32_t:1; + uint32_t CTSEL0_0:7; + uint32_t:16; + } B; + } ISEL5; + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL5_1:7; + uint32_t:1; + uint32_t CTSEL4_1:7; + uint32_t:1; + uint32_t CTSEL3_1:7; + uint32_t:1; + uint32_t CTSEL2_1:7; + } B; + } ISEL6; + + union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */ + uint32_t R; + struct { + uint32_t:1; + uint32_t CTSEL1_1:7; + uint32_t:1; + uint32_t CTSEL0_1:7; + uint32_t:16; + } B; + } ISEL7; + + union { /* eTPU Input Select Register */ + uint32_t R; + struct { + uint32_t:11; + uint32_t ETPU29:1; + uint32_t:3; + uint32_t ETPU28:1; + uint32_t:3; + uint32_t ETPU27:1; + uint32_t:3; + uint32_t ETPU26:1; + uint32_t:3; + uint32_t ETPU25:1; + uint32_t:3; + uint32_t ETPU24:1; + } B; + } ISEL8; + + union { /* eQADC Advanced Trigger Select */ + uint32_t R; + struct { + uint32_t:27; + uint32_t ETSEL0A:5; + } B; + } ISEL9; + + union { /* DecFilter Integrator Control */ + uint32_t R; + struct { + uint32_t ZSELA:4; + uint32_t HSELA:4; + uint32_t ZSELB:4; + uint32_t HSELB:4; + uint32_t ZSELC:4; + uint32_t HSELC:4; + uint32_t ZSELD:4; + uint32_t HSELD:4; + } B; + } DECFIL1; + + union { /* DecFilter Integrator Control */ + uint32_t R; + struct { + uint32_t ZSELE:4; + uint32_t HSELE:4; + uint32_t ZSELF:4; + uint32_t HSELF:4; + uint32_t ZSELG:4; + uint32_t HSELG:4; + uint32_t ZSELH:4; + uint32_t HSELH:4; + } B; + } DECFIL2; + + + int32_t SIU_reserved0920[20]; /* 0x0930-0x097F */ + + union { /* Chip Configuration Register Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t MATCH:1; + uint32_t DISNEX:1; + uint32_t:16; + } B; + } CCR; + + union { /* External Clock Configuration Register Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t ENGDIV:8; + uint32_t ECSS:1; + uint32_t:3; + uint32_t EBTS:1; + uint32_t:1; + uint32_t EBDF:2; + } B; + } ECCR; + + union { /* Compare A Register High */ + uint32_t R; + struct { + uint32_t CMPAH:32; + } B; + } CARH; + + union { /* Compare A Register Low */ + uint32_t R; + struct { + uint32_t CMPAL:32; + } B; + } CARL; + + union { /* Compare B Register High */ + uint32_t R; + struct { + uint32_t CMPBH:32; + } B; + } CBRH; + + union { /* Compare B Register Low */ + uint32_t R; + struct { + uint32_t CMPBL:32; + } B; + } CBRL; + + int32_t SIU_reserved0998[2]; /* 0x0998-0x099F */ + + union { /* System Clock Register */ + uint32_t R; + struct { + uint32_t:22; + uint32_t IPCLKDIV:2; + uint32_t:3; + uint32_t BYPASS:1; + uint32_t SYSCLKDIV:2; + uint32_t:2; + } B; + } SYSDIV; + + union { /* Halt Register */ + uint32_t R; + struct { + uint32_t CPUSTP:1; /* CPU and Platform stop request */ + uint32_t:4; /* Reserved */ + uint32_t TPUSTP:1; /* eTPU_A stop request */ + uint32_t NPCSTP:1; /* Nexus stop request */ + uint32_t EBISTP:1; /* EBI stop request*/ + uint32_t ADCSTP:1; /* eQADC stop request */ + uint32_t:1; /* Reserved */ + uint32_t MIOSSTP:1; /* eMIOS stop request */ + uint32_t DFILSTP:1; /* Decimation filter stop request */ + uint32_t:1; /* Reserved */ + uint32_t PITSTP:1; /* PIT stop request */ + uint32_t:2; /* Reserved */ + uint32_t CNDSTP:1; /* FlexCAN D stop request */ + uint32_t CNCSTP:1; /* FlexCAN C stop request */ + uint32_t CNBSTP:1; /* FlexCAN B stop request */ + uint32_t CNASTP:1; /* FlexCAN A stop request */ + uint32_t SPIDSTP:1; /* DSPI D stop request */ + uint32_t SPICSTP:1; /* DSPI C stop request */ + uint32_t SPIBSTP:1; /* DSPI B stop request */ + uint32_t SPIASTP:1; /* DSPI C stop request */ + uint32_t:5; /* Reserved */ + uint32_t SCICSTP:1; /* eSCI C stop request */ + uint32_t SCIBSTP:1; /* eSCI B stop request */ + uint32_t SCIASTP:1; /* eSCI A stop request */ + } B; + } HLT; + + union { /* Halt Acknowledge Register */ + uint32_t R; + struct { + uint32_t CPUACK:1; /* CPU and Platform stop acknowledge */ + uint32_t:4; /* Reserved */ + uint32_t TPUACK:1; /* eTPU_A stop acknowledge */ + uint32_t NPCACK:1; /* Nexus stop acknowledge */ + uint32_t EBIACK:1; /* EBI stop acknowledge*/ + uint32_t ADCACK:1; /* eQADC stop acknowledge */ + uint32_t:1; /* Reserved */ + uint32_t MIOSACK:1; /* eMIOS stop acknowledge */ + uint32_t DFILACK:1; /* Decimation filter stop acknowledge */ + uint32_t:1; /* Reserved */ + uint32_t PITACK:1; /* PIT stop acknowledge */ + uint32_t:2; /* Reserved */ + uint32_t CNDACK:1; /* FlexCAN D stop acknowledge */ + uint32_t CNCACK:1; /* FlexCAN C stop acknowledge */ + uint32_t CNBACK:1; /* FlexCAN B stop acknowledge */ + uint32_t CNAACK:1; /* FlexCAN A stop acknowledge */ + uint32_t SPIDACK:1; /* DSPI D stop acknowledge */ + uint32_t SPICACK:1; /* DSPI C stop acknowledge */ + uint32_t SPIBACK:1; /* DSPI B stop acknowledge */ + uint32_t SPIAACK:1; /* DSPI C stop acknowledge */ + uint32_t:5; /* Reserved */ + uint32_t SCICACK:1; /* eSCI C stop acknowledge */ + uint32_t SCIBACK:1; /* eSCI B stop acknowledge */ + uint32_t SCIAACK:1; /* eSCI A stop acknowledge */ + } B; + } HLTACK; + + int32_t SIU_reserved09AC[21]; /* 0x09AC-0x09FF */ + + int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */ + + union { /* Parallel GPIO Pin Data Output Register */ + uint32_t R; + struct { + uint32_t PGPDO0:1; + uint32_t PGPDO1:1; + uint32_t PGPDO2:1; + uint32_t PGPDO3:1; + uint32_t PGPDO4:1; + uint32_t PGPDO5:1; + uint32_t PGPDO6:1; + uint32_t PGPDO7:1; + uint32_t PGPDO8:1; + uint32_t PGPDO9:1; + uint32_t PGPDO10:1; + uint32_t PGPDO11:1; + uint32_t PGPDO12:1; + uint32_t PGPDO13:1; + uint32_t PGPDO14:1; + uint32_t PGPDO15:1; + uint32_t PGPDO16:1; + uint32_t PGPDO17:1; + uint32_t PGPDO18:1; + uint32_t PGPDO19:1; + uint32_t PGPDO20:1; + uint32_t PGPDO21:1; + uint32_t PGPDO22:1; + uint32_t PGPDO23:1; + uint32_t PGPDO24:1; + uint32_t PGPDO25:1; + uint32_t PGPDO26:1; + uint32_t PGPDO27:1; + uint32_t PGPDO28:1; + uint32_t PGPDO29:1; + uint32_t PGPDO30:1; + uint32_t PGPDO31:1; + } B; + } PGPDO[16]; + + union { /* Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t PGPDI0:1; + uint32_t PGPDI1:1; + uint32_t PGPDI2:1; + uint32_t PGPDI3:1; + uint32_t PGPDI4:1; + uint32_t PGPDI5:1; + uint32_t PGPDI6:1; + uint32_t PGPDI7:1; + uint32_t PGPDI8:1; + uint32_t PGPDI9:1; + uint32_t PGPDI10:1; + uint32_t PGPDI11:1; + uint32_t PGPDI12:1; + uint32_t PGPDI13:1; + uint32_t PGPDI14:1; + uint32_t PGPDI15:1; + uint32_t PGPDI16:1; + uint32_t PGPDI17:1; + uint32_t PGPDI18:1; + uint32_t PGPDI19:1; + uint32_t PGPDI20:1; + uint32_t PGPDI21:1; + uint32_t PGPDI22:1; + uint32_t PGPDI23:1; + uint32_t PGPDI24:1; + uint32_t PGPDI25:1; + uint32_t PGPDI26:1; + uint32_t PGPDI27:1; + uint32_t PGPDI28:1; + uint32_t PGPDI29:1; + uint32_t PGPDI30:1; + uint32_t PGPDI31:1; + } B; + } PGPDI[16]; + + union { /* Masked Parallel GPIO Pin Data Input Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } MPGPDO[32]; + + union { /* DSPI_A Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPIAH; + + union { /* DSPI_A Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPIAL; + + union { /* DSPI_B Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPIBH; + + union { /* DSPI_B Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPIBL; + + union { /* DSPI_C Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPICH; + + union { /* DSPI_C Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPICL; + + union { /* DSPI_D Mask Output High Register */ + uint32_t R; + struct { + uint32_t MASK0:1; + uint32_t MASK1:1; + uint32_t MASK2:1; + uint32_t MASK3:1; + uint32_t MASK4:1; + uint32_t MASK5:1; + uint32_t MASK6:1; + uint32_t MASK7:1; + uint32_t MASK8:1; + uint32_t MASK9:1; + uint32_t MASK10:1; + uint32_t MASK11:1; + uint32_t MASK12:1; + uint32_t MASK13:1; + uint32_t MASK14:1; + uint32_t MASK15:1; + uint32_t DATA0:1; + uint32_t DATA1:1; + uint32_t DATA2:1; + uint32_t DATA3:1; + uint32_t DATA4:1; + uint32_t DATA5:1; + uint32_t DATA6:1; + uint32_t DATA7:1; + uint32_t DATA8:1; + uint32_t DATA9:1; + uint32_t DATA10:1; + uint32_t DATA11:1; + uint32_t DATA12:1; + uint32_t DATA13:1; + uint32_t DATA14:1; + uint32_t DATA15:1; + } B; + } DSPIDH; + + union { /* DSPI_D Mask Output Low Register */ + uint32_t R; + struct { + uint32_t MASK16:1; + uint32_t MASK17:1; + uint32_t MASK18:1; + uint32_t MASK19:1; + uint32_t MASK20:1; + uint32_t MASK21:1; + uint32_t MASK22:1; + uint32_t MASK23:1; + uint32_t MASK24:1; + uint32_t MASK25:1; + uint32_t MASK26:1; + uint32_t MASK27:1; + uint32_t MASK28:1; + uint32_t MASK29:1; + uint32_t MASK30:1; + uint32_t MASK31:1; + uint32_t DATA16:1; + uint32_t DATA17:1; + uint32_t DATA18:1; + uint32_t DATA19:1; + uint32_t DATA20:1; + uint32_t DATA21:1; + uint32_t DATA22:1; + uint32_t DATA23:1; + uint32_t DATA24:1; + uint32_t DATA25:1; + uint32_t DATA26:1; + uint32_t DATA27:1; + uint32_t DATA28:1; + uint32_t DATA29:1; + uint32_t DATA30:1; + uint32_t DATA31:1; + } B; + } DSPIDL; + + int32_t SIU_reserved0D20[8]; /* 0x0D20-0x0D3F */ + + union { /* ETPU B Select Register */ + uint32_t R; + struct { + uint32_t ETPUB15:1; + uint32_t ETPUB14:1; + uint32_t ETPUB13:1; + uint32_t ETPUB12:1; + uint32_t ETPUB11:1; + uint32_t ETPUB10:1; + uint32_t ETPUB9:1; + uint32_t ETPUB8:1; + uint32_t ETPUB7:1; + uint32_t ETPUB6:1; + uint32_t ETPUB5:1; + uint32_t ETPUB4:1; + uint32_t ETPUB3:1; + uint32_t ETPUB2:1; + uint32_t ETPUB1:1; + uint32_t ETPUB0:1; + uint32_t ETPUB31:1; + uint32_t ETPUB30:1; + uint32_t ETPUB29:1; + uint32_t ETPUB28:1; + uint32_t ETPUB27:1; + uint32_t ETPUB26:1; + uint32_t ETPUB25:1; + uint32_t ETPUB24:1; + uint32_t ETPUB23:1; + uint32_t ETPUB22:1; + uint32_t ETPUB21:1; + uint32_t ETPUB20:1; + uint32_t ETPUB19:1; + uint32_t ETPUB18:1; + uint32_t ETPUB17:1; + uint32_t ETPUB16:1; + } B ; + } ETPUBA; + + union { /* EMIOS A Select Register */ + uint32_t R; + struct { + uint32_t EMIOS7:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + uint32_t EMIOS8:1; + uint32_t EMIOS9:1; + uint32_t EMIOS10:1; + uint32_t EMIOS11:1; + uint32_t EMIOS12:1; + uint32_t EMIOS13:1; + uint32_t EMIOS14:1; + uint32_t EMIOS15:1; + uint32_t EMIOS16:1; + uint32_t EMIOS17:1; + uint32_t EMIOS18:1; + uint32_t EMIOS19:1; + uint32_t EMIOS20:1; + uint32_t EMIOS21:1; + uint32_t EMIOS22:1; + uint32_t EMIOS23:1; + uint32_t EMIOS0_0:1; + uint32_t EMIOS1_1:1; + uint32_t EMIOS2_2:1; + uint32_t EMIOS3_3:1; + uint32_t EMIOS4_4:1; + uint32_t EMIOS5_5:1; + uint32_t EMIOS6_6:1; + uint32_t EMIOS7_7:1; + } B; + } EMIOSA; + + union { /* DSPIAH/L Select Register for DSPI A */ + uint32_t R; + struct { + uint32_t DSPIAH0:1; + uint32_t DSPIAH1:1; + uint32_t DSPIAH2:1; + uint32_t DSPIAH3:1; + uint32_t DSPIAH4:1; + uint32_t DSPIAH5:1; + uint32_t DSPIAH6:1; + uint32_t DSPIAH7:1; + uint32_t DSPIAH8:1; + uint32_t DSPIAH9:1; + uint32_t DSPIAH10:1; + uint32_t DSPIAH11:1; + uint32_t DSPIAH12:1; + uint32_t DSPIAH13:1; + uint32_t DSPIAH14:1; + uint32_t DSPIAH15:1; + uint32_t DSPIAL16:1; + uint32_t DSPIAL17:1; + uint32_t DSPIAL18:1; + uint32_t DSPIAL19:1; + uint32_t DSPIAL20:1; + uint32_t DSPIAL21:1; + uint32_t DSPIAL22:1; + uint32_t DSPIAL23:1; + uint32_t DSPIAL24:1; + uint32_t DSPIAL25:1; + uint32_t DSPIAL26:1; + uint32_t DSPIAL27:1; + uint32_t DSPIAL28:1; + uint32_t DSPIAL29:1; + uint32_t DSPIAL30:1; + uint32_t DSPIAL31:1; + } B; + } DSPIAHLA; + + int32_t SIU_reserved0D4C; /* 0x0D4C-0x0D4F */ + + union { /* ETPU A Select Register */ + uint32_t R; + struct { + uint32_t ETPUA23:1; + uint32_t ETPUA22:1; + uint32_t ETPUA21:1; + uint32_t ETPUA20:1; + uint32_t ETPUA19:1; + uint32_t ETPUA18:1; + uint32_t ETPUA17:1; + uint32_t ETPUA16:1; + uint32_t ETPUA29:1; + uint32_t ETPUA28:1; + uint32_t ETPUA27:1; + uint32_t ETPUA26:1; + uint32_t ETPUA25:1; + uint32_t ETPUA24:1; + uint32_t ETPUA31:1; + uint32_t ETPUA30:1; + uint32_t ETPUA12:1; + uint32_t ETPUA13:1; + uint32_t ETPUA14:1; + uint32_t ETPUA15:1; + uint32_t ETPUA0:1; + uint32_t ETPUA1:1; + uint32_t ETPUA2:1; + uint32_t ETPUA3:1; + uint32_t ETPUA4:1; + uint32_t ETPUA5:1; + uint32_t ETPUA6:1; + uint32_t ETPUA7:1; + uint32_t ETPUA8:1; + uint32_t ETPUA9:1; + uint32_t ETPUA10:1; + uint32_t ETPUA11:1; + } B ; + } ETPUAB; + + union { /* EMIOS B Select Register */ + uint32_t R; + struct { + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS9:1; + uint32_t EMIOS8:1; + uint32_t EMIOS6:1; + uint32_t EMIOS5:1; + uint32_t EMIOS4:1; + uint32_t EMIOS3:1; + uint32_t EMIOS2:1; + uint32_t EMIOS1:1; + uint32_t EMIOS0:1; + uint32_t EMIOS23:1; + uint32_t EMIOS15:1; + uint32_t EMIOS14:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t EMIOS23_23:1; + uint32_t EMIOS15_15:1; + uint32_t EMIOS14_14:1; + uint32_t EMIOS13_13:1; + uint32_t EMIOS12_12:1; + uint32_t EMIOS11_11:1; + uint32_t EMIOS10_10:1; + uint32_t EMIOS9_9:1; + uint32_t EMIOS8_8:1; + uint32_t EMIOS6_6:1; + uint32_t EMIOS5_5:1; + uint32_t EMIOS4_4:1; + uint32_t EMIOS3_3:1; + uint32_t EMIOS2_2:1; + uint32_t EMIOS1_1:1; + uint32_t EMIOS0_0:1; + } B; + } EMIOSB; + + union { /* DSPIBH/L Select Register for DSPI B */ + uint32_t R; + struct { + uint32_t DSPIBH0:1; + uint32_t DSPIBH1:1; + uint32_t DSPIBH2:1; + uint32_t DSPIBH3:1; + uint32_t DSPIBH4:1; + uint32_t DSPIBH5:1; + uint32_t DSPIBH6:1; + uint32_t DSPIBH7:1; + uint32_t DSPIBH8:1; + uint32_t DSPIBH9:1; + uint32_t DSPIBH10:1; + uint32_t DSPIBH11:1; + uint32_t DSPIBH12:1; + uint32_t DSPIBH13:1; + uint32_t DSPIBH14:1; + uint32_t DSPIBH15:1; + uint32_t DSPIBL16:1; + uint32_t DSPIBL17:1; + uint32_t DSPIBL18:1; + uint32_t DSPIBL19:1; + uint32_t DSPIBL20:1; + uint32_t DSPIBL21:1; + uint32_t DSPIBL22:1; + uint32_t DSPIBL23:1; + uint32_t DSPIBL24:1; + uint32_t DSPIBL25:1; + uint32_t DSPIBL26:1; + uint32_t DSPIBL27:1; + uint32_t DSPIBL28:1; + uint32_t DSPIBL29:1; + uint32_t DSPIBL30:1; + uint32_t DSPIBL31:1; + } B; + } DSPIBHLB; + + int32_t SIU_reserved0D5C; /* 0x0D5C-0x0D5F */ + + union { /* ETPU A Select Register */ + uint32_t R; + struct { + uint32_t ETPUA12:1; + uint32_t ETPUA13:1; + uint32_t ETPUA14:1; + uint32_t ETPUA15:1; + uint32_t ETPUA0:1; + uint32_t ETPUA1:1; + uint32_t ETPUA2:1; + uint32_t ETPUA3:1; + uint32_t ETPUA4:1; + uint32_t ETPUA5:1; + uint32_t ETPUA6:1; + uint32_t ETPUA7:1; + uint32_t ETPUA8:1; + uint32_t ETPUA9:1; + uint32_t ETPUA10:1; + uint32_t ETPUA11:1; + uint32_t ETPUA23:1; + uint32_t ETPUA22:1; + uint32_t ETPUA21:1; + uint32_t ETPUA20:1; + uint32_t ETPUA19:1; + uint32_t ETPUA18:1; + uint32_t ETPUA17:1; + uint32_t ETPUA16:1; + uint32_t ETPUA29:1; + uint32_t ETPUA28:1; + uint32_t ETPUA27:1; + uint32_t ETPUA26:1; + uint32_t ETPUA25:1; + uint32_t ETPUA24:1; + uint32_t ETPUA31:1; + uint32_t ETPUA30:1; + } B ; + } ETPUAC; + + union { /* EMIOS C Select Register */ + uint32_t R; + struct { + uint32_t EMIOS12:1; + uint32_t EMIOS13:1; + uint32_t EMIOS14:1; + uint32_t EMIOS15:1; + uint32_t EMIOS23:1; + uint32_t EMIOS0:1; + uint32_t EMIOS1:1; + uint32_t EMIOS2:1; + uint32_t EMIOS3:1; + uint32_t EMIOS4:1; + uint32_t EMIOS5:1; + uint32_t EMIOS6:1; + uint32_t EMIOS8:1; + uint32_t EMIOS9:1; + uint32_t EMIOS10:1; + uint32_t EMIOS11:1; + uint32_t EMIOS23_23:1; + uint32_t EMIOS22:1; + uint32_t EMIOS21:1; + uint32_t EMIOS20:1; + uint32_t EMIOS19:1; + uint32_t EMIOS18:1; + uint32_t EMIOS17:1; + uint32_t EMIOS16:1; + uint32_t EMIOS29:1; + uint32_t EMIOS28:1; + uint32_t EMIOS27:1; + uint32_t EMIOS26:1; + uint32_t EMIOS25:1; + uint32_t EMIOS24:1; + uint32_t EMIOS31:1; + uint32_t EMIOS30:1; + } B; + } EMIOSC; + + union { /* DSPICH/L Select Register for DSPI C */ + uint32_t R; + struct { + uint32_t DSPICH0:1; + uint32_t DSPICH1:1; + uint32_t DSPICH2:1; + uint32_t DSPICH3:1; + uint32_t DSPICH4:1; + uint32_t DSPICH5:1; + uint32_t DSPICH6:1; + uint32_t DSPICH7:1; + uint32_t DSPICH8:1; + uint32_t DSPICH9:1; + uint32_t DSPICH10:1; + uint32_t DSPICH11:1; + uint32_t DSPICH12:1; + uint32_t DSPICH13:1; + uint32_t DSPICH14:1; + uint32_t DSPICH15:1; + uint32_t DSPICL16:1; + uint32_t DSPICL17:1; + uint32_t DSPICL18:1; + uint32_t DSPICL19:1; + uint32_t DSPICL20:1; + uint32_t DSPICL21:1; + uint32_t DSPICL22:1; + uint32_t DSPICL23:1; + uint32_t DSPICL24:1; + uint32_t DSPICL25:1; + uint32_t DSPICL26:1; + uint32_t DSPICL27:1; + uint32_t DSPICL28:1; + uint32_t DSPICL29:1; + uint32_t DSPICL30:1; + uint32_t DSPICL31:1; + } B; + } DSPICHLC; + + int32_t SIU_reserved0D6C; /* 0x0D6C-0x0D6F */ + + union { /* ETPU B Select Register */ + uint32_t R; + struct { + uint32_t ETPUB21:1; + uint32_t ETPUB20:1; + uint32_t ETPUB19:1; + uint32_t ETPUB18:1; + uint32_t ETPUB17:1; + uint32_t ETPUB16:1; + uint32_t:4; + uint32_t ETPUB29:1; + uint32_t ETPUB28:1; + uint32_t ETPUB27:1; + uint32_t ETPUB26:1; + uint32_t ETPUB25:1; + uint32_t ETPUB24:1; + uint32_t:16; + } B ; + } ETPUBD; + + union { /* EMIOS D Select Register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t EMIOS11:1; + uint32_t EMIOS10:1; + uint32_t EMIOS13:1; + uint32_t EMIOS12:1; + uint32_t:22; + } B; + } EMIOSD; + + union { /* DSPIDH/L Select Register for DSPI D */ + uint32_t R; + struct { + uint32_t:32; + } B; + } DSPIDHLD; + + int32_t SIU_reserved0D7C; /* 0x0D7C-0x0D7F */ + + int32_t SIU_reserved0D80[32]; /* 0x0D80-0x0DFF */ + + union { /* GPIO Pin Data Input Registers */ + uint8_t R; + struct { + uint8_t:7; + uint8_t PDI:1; + } B; + } GPDI0_511[512]; + + uint32_t SIU_reserved1000[3072]; /* 0x1000-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + + struct EMIOS_tag { + + union EMIOS_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t GTBE:1; + uint32_t ETB:1; + uint32_t GPREN:1; + uint32_t:6; + uint32_t SRV:4; + uint32_t GPRE:8; + uint32_t:8; + } B; + } MCR; + + union { /* Global FLAG Register */ + uint32_t R; + struct { + uint32_t F31:1; + uint32_t F30:1; + uint32_t F29:1; + uint32_t F28:1; + uint32_t F27:1; + uint32_t F26:1; + uint32_t F25:1; + uint32_t F24:1; + uint32_t F23:1; + uint32_t F22:1; + uint32_t F21:1; + uint32_t F20:1; + uint32_t F19:1; + uint32_t F18:1; + uint32_t F17:1; + uint32_t F16:1; + uint32_t F15:1; + uint32_t F14:1; + uint32_t F13:1; + uint32_t F12:1; + uint32_t F11:1; + uint32_t F10:1; + uint32_t F9:1; + uint32_t F8:1; + uint32_t F7:1; + uint32_t F6:1; + uint32_t F5:1; + uint32_t F4:1; + uint32_t F3:1; + uint32_t F2:1; + uint32_t F1:1; + uint32_t F0:1; + } B; + } GFR; + + union { /* Output Update Disable Register */ + uint32_t R; + struct { + uint32_t OU31:1; + uint32_t OU30:1; + uint32_t OU29:1; + uint32_t OU28:1; + uint32_t OU27:1; + uint32_t OU26:1; + uint32_t OU25:1; + uint32_t OU24:1; + uint32_t OU23:1; + uint32_t OU22:1; + uint32_t OU21:1; + uint32_t OU20:1; + uint32_t OU19:1; + uint32_t OU18:1; + uint32_t OU17:1; + uint32_t OU16:1; + uint32_t OU15:1; + uint32_t OU14:1; + uint32_t OU13:1; + uint32_t OU12:1; + uint32_t OU11:1; + uint32_t OU10:1; + uint32_t OU9:1; + uint32_t OU8:1; + uint32_t OU7:1; + uint32_t OU6:1; + uint32_t OU5:1; + uint32_t OU4:1; + uint32_t OU3:1; + uint32_t OU2:1; + uint32_t OU1:1; + uint32_t OU0:1; + } B; + } OUDR; + + uint32_t eMIOS_reserved000C[5]; /* 0x000C-0x001F */ + + struct EMIOS_CH_tag { + union { /* Channel A Data Register */ + uint32_t R; + } CADR; + + union { /* Channel B Data Register */ + uint32_t R; + } CBDR; + + union { /* Channel Counter Register */ + uint32_t R; + } CCNTR; + + union EMIOS_CCR_tag {/* Channel Control Register */ + uint32_t R; + struct { + uint32_t FREN:1; + uint32_t ODIS:1; + uint32_t ODISSL:2; + uint32_t UCPRE:2; + uint32_t UCPREN:1; + uint32_t DMA:1; + uint32_t:1; + uint32_t IF:4; + uint32_t FCK:1; + uint32_t FEN:1; + uint32_t:3; + uint32_t FORCMA:1; + uint32_t FORCMB:1; + uint32_t:1; + uint32_t BSL:2; + uint32_t EDSEL:1; + uint32_t EDPOL:1; + uint32_t MODE:7; + } B; + } CCR; + + union EMIOS_CSR_tag {/* Channel Status Register */ + uint32_t R; + struct { + uint32_t OVR:1; + uint32_t:15; + uint32_t OVFL:1; + uint32_t:12; + uint32_t UCIN:1; + uint32_t UCOUT:1; + uint32_t FLAG:1; + } B; + } CSR; + + union { /* Alternate Channel A Data Register */ + uint32_t R; + } ALTA; + + uint32_t eMIOS_channel_reserved0018[2]; /* 0x0018-0x001F */ + + } CH[32]; + + uint32_t eMIOS_reserved0420[3832]; /* 0x0420-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : PMC */ +/****************************************************************************/ + + struct PMC_tag { + + union { + uint32_t R; + struct { + uint32_t LVRER:1; + uint32_t LVREH:1; + uint32_t LVRE50:1; + uint32_t LVRE33:1; + uint32_t LVREC:1; + uint32_t LVREA:1; + uint32_t:1; + uint32_t:1; + uint32_t LVIER:1; + uint32_t LVIEH:1; + uint32_t LVIE50:1; + uint32_t LVIE33:1; + uint32_t LVIEC:1; + uint32_t LVIEA:1; + uint32_t:1; + uint32_t TLK:1; + uint32_t:16; + } B; + } MCR; /* Module Configuration Register */ + + union { + uint32_t R; + struct { + uint32_t :8; + uint32_t LVDATRIM:4; + uint32_t LVDREGTRIM:4; + uint32_t VDD33TRIM:4; + uint32_t LVD33TRIM:4; + uint32_t VDDCTRIM:4; + uint32_t LVDCTRIM:4; + } B; + } TRIMR; /* Trimming register */ + + union { + uint32_t R; + struct { + uint32_t :5; + uint32_t LVFSTBY:1; + uint32_t BGRDY:1; + uint32_t BGTS:1; + uint32_t :5; + uint32_t LVFCSTBY:1; + uint32_t :2; + uint32_t LVFCR:1; + uint32_t LVFCH:1; + uint32_t LVFC50:1; + uint32_t LVFC33:1; + uint32_t LVFCC:1; + uint32_t LVFCA:1; + uint32_t :2; + uint32_t LVFR:1; + uint32_t LVFH:1; + uint32_t LVF50:1; + uint32_t LVF33:1; + uint32_t LVFC:1; + uint32_t LVFA:1; + uint32_t :2; + } B; + } SR; /* status register */ + + uint32_t PMC_reserved000C[4093]; /* 0x000C-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE :ETPU */ +/****************************************************************************/ + +/***************************Configuration Registers**************************/ + + struct ETPU_tag { + union { /* MODULE CONFIGURATION REGISTER */ + uint32_t R; + struct { + uint32_t GEC:1; /* Global Exception Clear */ + uint32_t SDMERR:1; /* SDM Read Error */ + uint32_t WDTOA:1; /* Watchdog Timeout-eTPU_A */ + uint32_t WDTOB:1; /* Watchdog Timeout-eTPU_B */ + uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ + uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ + uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ + uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ + uint32_t:3; + uint32_t SCMSIZE:5; /* Shared Code Memory size */ + uint32_t:4; + uint32_t SCMMISC:1; /* SCM MISC Complete/Clear */ + uint32_t SCMMISF:1; /* SCM MISC Flag */ + uint32_t SCMMISEN:1; /* SCM MISC Enable */ + uint32_t:2; + uint32_t VIS:1; /* SCM Visability */ + uint32_t:5; + uint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; + + union { /* COHERENT DUAL-PARAMETER CONTROL */ + uint32_t R; + struct { + uint32_t STS:1; /* Start Status bit */ + uint32_t CTBASE:5; /* Channel Transfer Base */ + uint32_t PBASE:10; /* Parameter Buffer Base Address */ + uint32_t PWIDTH:1; /* Parameter Width */ + uint32_t PARAM0:7; /* Channel Parameter 0 */ + uint32_t WR:1; /* Read/Write selection */ + uint32_t PARAM1:7; /* Channel Parameter 1 */ + } B; + } CDCR; + + uint32_t eTPU_reserved0008; /* 0x0008-0x000B */ + + union { /* MISC Compare Register */ + uint32_t R; + struct { + uint32_t ETPUMISCCMP:32; + } B; + } MISCCMPR; + + union { /* SCM off-range Date Register */ + uint32_t R; + struct { + uint32_t ETPUSCMOFFDATA:32; + } B; + } SCMOFFDATAR; + + union { /* ETPU_A Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:3; + uint32_t FCSS:1; /* Filter Clock Source Select */ + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:1; + uint32_t ERBA:5; /* Engine Relative Base Address */ + uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ + uint32_t:2; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; + + union { /* ETPU_B Configuration Register */ + uint32_t R; + struct { + uint32_t FEND:1; /* Force END */ + uint32_t MDIS:1; /* Low power Stop */ + uint32_t:1; + uint32_t STF:1; /* Stop Flag */ + uint32_t:4; + uint32_t HLTF:1; /* Halt Mode Flag */ + uint32_t:3; + uint32_t FCSS:1; /* Filter Clock Source Select */ + uint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + uint32_t CDFC:2; + uint32_t:1; + uint32_t ERBA:5; /* Engine Relative Base Address */ + uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */ + uint32_t:2; + uint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_B; + + uint32_t eTPU_reserved001C; /* 0x001C-0x001F */ + + union { /* ETPU_A Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t AM:2; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t TCR1CS:1; /* TCR1 Clock Source */ + uint32_t:5; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; + + union { /* ETPU_A TCR1 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR1:24; + } B; + } TB1R_A; + + union { /* ETPU_A TCR2 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR2:24; + } B; + } TB2R_A; + + union { /* ETPU_A STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; /* TCR1 Server ID */ + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; /* TCR2 Server ID */ + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; + + uint32_t eTPU_reserved0030[4]; /* 0x0030-0x003F */ + + union { /* ETPU_B Timebase Configuration Register */ + uint32_t R; + struct { + uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + uint32_t AM:2; /* Angle Mode */ + uint32_t:3; + uint32_t TCR2P:6; /* TCR2 Prescaler Control */ + uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + uint32_t TCR1CS:1; /* TCR1 Clock Source */ + uint32_t:5; + uint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_B; + + union { /* ETPU_B TCR1 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR1:24; + } B; + } TB1R_B; + + union { /* ETPU_B TCR2 Visibility Register */ + uint32_t R; + struct { + uint32_t:8; + uint32_t TCR2:24; + } B; + } TB2R_B; + + union { /* ETPU_B STAC Configuration Register */ + uint32_t R; + struct { + uint32_t REN1:1; /* Resource Enable TCR1 */ + uint32_t RSC1:1; /* Resource Control TCR1 */ + uint32_t:2; + uint32_t SERVER_ID1:4; /* TCR1 Server ID */ + uint32_t:4; + uint32_t SRV1:4; /* Resource Server Slot */ + uint32_t REN2:1; /* Resource Enable TCR2 */ + uint32_t RSC2:1; /* Resource Control TCR2 */ + uint32_t:2; + uint32_t SERVER_ID2:4; /* TCR2 Server ID */ + uint32_t:4; + uint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_B; + + uint32_t eTPU_reserved0050[4]; /* 0x0050-0x005F */ + + union { /* Watchdog Timer Register A */ + uint32_t R; + struct { + uint32_t WDM:2; /* Watchdog Mode */ + uint32_t:14; + uint32_t WDCNT:16; /* Watchdog Count */ + } B; + } WDTR_A; + + uint32_t eTPU_reserved0064; /* 0x0064-0x0067 */ + + union { /* Idle Counter Register A*/ + uint32_t R; + struct { + uint32_t IDLE_CNT:31; + uint32_t ICLR:1; /* Idle Clear */ + } B; + + } IDLE_A; + + uint32_t eTPU_reserved006C; /* 0x006C-0x006F */ + + union { /* Watchdog Timer Register B */ + uint32_t R; + struct { + uint32_t WDM:2; /* Watchdog Mode */ + uint32_t:14; + uint32_t WDCNT:16; /* Watchdog Count */ + } B; + } WDTR_B; + + uint32_t eTPU_reserved0074; /* 0x0074-0x0077 */ + + union { /* Idle Counter Register B*/ + uint32_t R; + struct { + uint32_t IDLE_CNT:31; + uint32_t ICLR:1; /* Idle Clear */ + } B; + } IDLE_B; + + uint32_t eTPU_reserved007C; /* 0x007C-0x007F */ + + uint32_t eTPU_reserved0080[96]; /* 0x0080-0x01FF */ + +/*****************************Status and Control Registers**************************/ + + union { /* ETPU_A Channel Interrut Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrut Status */ + uint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; + + union { /* ETPU_B Channel Interruput Status */ + uint32_t R; + struct { + uint32_t CIS31:1; /* Channel 31 Interrut Status */ + uint32_t CIS30:1; /* Channel 30 Interrut Status */ + uint32_t CIS29:1; /* Channel 29 Interrut Status */ + uint32_t CIS28:1; /* Channel 28 Interrut Status */ + uint32_t CIS27:1; /* Channel 27 Interrut Status */ + uint32_t CIS26:1; /* Channel 26 Interrut Status */ + uint32_t CIS25:1; /* Channel 25 Interrut Status */ + uint32_t CIS24:1; /* Channel 24 Interrut Status */ + uint32_t CIS23:1; /* Channel 23 Interrut Status */ + uint32_t CIS22:1; /* Channel 22 Interrut Status */ + uint32_t CIS21:1; /* Channel 21 Interrut Status */ + uint32_t CIS20:1; /* Channel 20 Interrut Status */ + uint32_t CIS19:1; /* Channel 19 Interrut Status */ + uint32_t CIS18:1; /* Channel 18 Interrut Status */ + uint32_t CIS17:1; /* Channel 17 Interrut Status */ + uint32_t CIS16:1; /* Channel 16 Interrut Status */ + uint32_t CIS15:1; /* Channel 15 Interrut Status */ + uint32_t CIS14:1; /* Channel 14 Interrut Status */ + uint32_t CIS13:1; /* Channel 13 Interrut Status */ + uint32_t CIS12:1; /* Channel 12 Interrut Status */ + uint32_t CIS11:1; /* Channel 11 Interrut Status */ + uint32_t CIS10:1; /* Channel 10 Interrut Status */ + uint32_t CIS9:1; /* Channel 9 Interrut Status */ + uint32_t CIS8:1; /* Channel 8 Interrut Status */ + uint32_t CIS7:1; /* Channel 7 Interrut Status */ + uint32_t CIS6:1; /* Channel 6 Interrut Status */ + uint32_t CIS5:1; /* Channel 5 Interrut Status */ + uint32_t CIS4:1; /* Channel 4 Interrut Status */ + uint32_t CIS3:1; /* Channel 3 Interrut Status */ + uint32_t CIS2:1; /* Channel 2 Interrut Status */ + uint32_t CIS1:1; /* Channel 1 Interrupt Status */ + uint32_t CIS0:1; /* Channel 0 Interrupt Status */ + } B; + } CISR_B; + + uint32_t eTPU_reserved0208[2]; /* 0x0208-0x020F */ + + union { /* ETPU_A Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; + + union { /* ETPU_B Data Transfer Request Status */ + uint32_t R; + struct { + uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_B; + + uint32_t eTPU_reserved0218[2]; /* 0x0218-0x021F */ + + union { /* ETPU_A Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; + + union { /* ETPU_B Interruput Overflow Status */ + uint32_t R; + struct { + uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_B; + + uint32_t eTPU_reserved0228[2]; /* 0x0228-0x022F */ + + union { /* ETPU_A Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; + + union { /* ETPU_B Data Transfer Overflow Status */ + uint32_t R; + struct { + uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_B; + + uint32_t eTPU_reserved0238[2]; /* 0x0238-0x023F */ + + union { /* ETPU_A Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; + + union { /* ETPU_B Channel Interruput Enable */ + uint32_t R; + struct { + uint32_t CIE31:1; /* Channel 31 Interruput Enable */ + uint32_t CIE30:1; /* Channel 30 Interruput Enable */ + uint32_t CIE29:1; /* Channel 29 Interruput Enable */ + uint32_t CIE28:1; /* Channel 28 Interruput Enable */ + uint32_t CIE27:1; /* Channel 27 Interruput Enable */ + uint32_t CIE26:1; /* Channel 26 Interruput Enable */ + uint32_t CIE25:1; /* Channel 25 Interruput Enable */ + uint32_t CIE24:1; /* Channel 24 Interruput Enable */ + uint32_t CIE23:1; /* Channel 23 Interruput Enable */ + uint32_t CIE22:1; /* Channel 22 Interruput Enable */ + uint32_t CIE21:1; /* Channel 21 Interruput Enable */ + uint32_t CIE20:1; /* Channel 20 Interruput Enable */ + uint32_t CIE19:1; /* Channel 19 Interruput Enable */ + uint32_t CIE18:1; /* Channel 18 Interruput Enable */ + uint32_t CIE17:1; /* Channel 17 Interruput Enable */ + uint32_t CIE16:1; /* Channel 16 Interruput Enable */ + uint32_t CIE15:1; /* Channel 15 Interruput Enable */ + uint32_t CIE14:1; /* Channel 14 Interruput Enable */ + uint32_t CIE13:1; /* Channel 13 Interruput Enable */ + uint32_t CIE12:1; /* Channel 12 Interruput Enable */ + uint32_t CIE11:1; /* Channel 11 Interruput Enable */ + uint32_t CIE10:1; /* Channel 10 Interruput Enable */ + uint32_t CIE9:1; /* Channel 9 Interruput Enable */ + uint32_t CIE8:1; /* Channel 8 Interruput Enable */ + uint32_t CIE7:1; /* Channel 7 Interruput Enable */ + uint32_t CIE6:1; /* Channel 6 Interruput Enable */ + uint32_t CIE5:1; /* Channel 5 Interruput Enable */ + uint32_t CIE4:1; /* Channel 4 Interruput Enable */ + uint32_t CIE3:1; /* Channel 3 Interruput Enable */ + uint32_t CIE2:1; /* Channel 2 Interruput Enable */ + uint32_t CIE1:1; /* Channel 1 Interruput Enable */ + uint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_B; + + uint32_t eTPU_reserved0248[2]; /* 0x0248-0x024F */ + + union { /* ETPU_A Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; + + union { /* ETPU_B Channel Data Transfer Request Enable */ + uint32_t R; + struct { + uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_B; + + uint32_t eTPU_reserved0258[2]; /* 0x0258-0x025F */ + + union { /* Watchdog Status Register A */ + uint32_t R; + struct { + uint32_t WDS31:1; + uint32_t WDS30:1; + uint32_t WDS29:1; + uint32_t WDS28:1; + uint32_t WDS27:1; + uint32_t WDS26:1; + uint32_t WDS25:1; + uint32_t WDS24:1; + uint32_t WDS23:1; + uint32_t WDS22:1; + uint32_t WDS21:1; + uint32_t WDS20:1; + uint32_t WDS19:1; + uint32_t WDS18:1; + uint32_t WDS17:1; + uint32_t WDS16:1; + uint32_t WDS15:1; + uint32_t WDS14:1; + uint32_t WDS13:1; + uint32_t WDS12:1; + uint32_t WDS11:1; + uint32_t WDS10:1; + uint32_t WDS9:1; + uint32_t WDS8:1; + uint32_t WDS7:1; + uint32_t WDS6:1; + uint32_t WDS5:1; + uint32_t WDS4:1; + uint32_t WDS3:1; + uint32_t WDS2:1; + uint32_t WDS1:1; + uint32_t WDS0:1; + } B; + } WDSR_A; + + union { /* Watchdog Status Register B */ + uint32_t R; + struct { + uint32_t WDS31:1; + uint32_t WDS30:1; + uint32_t WDS29:1; + uint32_t WDS28:1; + uint32_t WDS27:1; + uint32_t WDS26:1; + uint32_t WDS25:1; + uint32_t WDS24:1; + uint32_t WDS23:1; + uint32_t WDS22:1; + uint32_t WDS21:1; + uint32_t WDS20:1; + uint32_t WDS19:1; + uint32_t WDS18:1; + uint32_t WDS17:1; + uint32_t WDS16:1; + uint32_t WDS15:1; + uint32_t WDS14:1; + uint32_t WDS13:1; + uint32_t WDS12:1; + uint32_t WDS11:1; + uint32_t WDS10:1; + uint32_t WDS9:1; + uint32_t WDS8:1; + uint32_t WDS7:1; + uint32_t WDS6:1; + uint32_t WDS5:1; + uint32_t WDS4:1; + uint32_t WDS3:1; + uint32_t WDS2:1; + uint32_t WDS1:1; + uint32_t WDS0:1; + } B; + } WDSR_B; + + uint32_t eTPU_reserved0268[6]; /* 0x0268-0x027F */ + + union { /* ETPU_A Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_A; + + union { /* ETPU_B Channel Pending Service Status */ + uint32_t R; + struct { + uint32_t SR31:1; /* Channel 31 Pending Service Status */ + uint32_t SR30:1; /* Channel 30 Pending Service Status */ + uint32_t SR29:1; /* Channel 29 Pending Service Status */ + uint32_t SR28:1; /* Channel 28 Pending Service Status */ + uint32_t SR27:1; /* Channel 27 Pending Service Status */ + uint32_t SR26:1; /* Channel 26 Pending Service Status */ + uint32_t SR25:1; /* Channel 25 Pending Service Status */ + uint32_t SR24:1; /* Channel 24 Pending Service Status */ + uint32_t SR23:1; /* Channel 23 Pending Service Status */ + uint32_t SR22:1; /* Channel 22 Pending Service Status */ + uint32_t SR21:1; /* Channel 21 Pending Service Status */ + uint32_t SR20:1; /* Channel 20 Pending Service Status */ + uint32_t SR19:1; /* Channel 19 Pending Service Status */ + uint32_t SR18:1; /* Channel 18 Pending Service Status */ + uint32_t SR17:1; /* Channel 17 Pending Service Status */ + uint32_t SR16:1; /* Channel 16 Pending Service Status */ + uint32_t SR15:1; /* Channel 15 Pending Service Status */ + uint32_t SR14:1; /* Channel 14 Pending Service Status */ + uint32_t SR13:1; /* Channel 13 Pending Service Status */ + uint32_t SR12:1; /* Channel 12 Pending Service Status */ + uint32_t SR11:1; /* Channel 11 Pending Service Status */ + uint32_t SR10:1; /* Channel 10 Pending Service Status */ + uint32_t SR9:1; /* Channel 9 Pending Service Status */ + uint32_t SR8:1; /* Channel 8 Pending Service Status */ + uint32_t SR7:1; /* Channel 7 Pending Service Status */ + uint32_t SR6:1; /* Channel 6 Pending Service Status */ + uint32_t SR5:1; /* Channel 5 Pending Service Status */ + uint32_t SR4:1; /* Channel 4 Pending Service Status */ + uint32_t SR3:1; /* Channel 3 Pending Service Status */ + uint32_t SR2:1; /* Channel 2 Pending Service Status */ + uint32_t SR1:1; /* Channel 1 Pending Service Status */ + uint32_t SR0:1; /* Channel 0 Pending Service Status */ + } B; + } CPSSR_B; + + uint32_t eTPU_reserved0288[2]; /* 0x0288-0x028F */ + + union { /* ETPU_A Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_A; + + union { /* ETPU_B Channel Service Status */ + uint32_t R; + struct { + uint32_t SS31:1; /* Channel 31 Service Status */ + uint32_t SS30:1; /* Channel 30 Service Status */ + uint32_t SS29:1; /* Channel 29 Service Status */ + uint32_t SS28:1; /* Channel 28 Service Status */ + uint32_t SS27:1; /* Channel 27 Service Status */ + uint32_t SS26:1; /* Channel 26 Service Status */ + uint32_t SS25:1; /* Channel 25 Service Status */ + uint32_t SS24:1; /* Channel 24 Service Status */ + uint32_t SS23:1; /* Channel 23 Service Status */ + uint32_t SS22:1; /* Channel 22 Service Status */ + uint32_t SS21:1; /* Channel 21 Service Status */ + uint32_t SS20:1; /* Channel 20 Service Status */ + uint32_t SS19:1; /* Channel 19 Service Status */ + uint32_t SS18:1; /* Channel 18 Service Status */ + uint32_t SS17:1; /* Channel 17 Service Status */ + uint32_t SS16:1; /* Channel 16 Service Status */ + uint32_t SS15:1; /* Channel 15 Service Status */ + uint32_t SS14:1; /* Channel 14 Service Status */ + uint32_t SS13:1; /* Channel 13 Service Status */ + uint32_t SS12:1; /* Channel 12 Service Status */ + uint32_t SS11:1; /* Channel 11 Service Status */ + uint32_t SS10:1; /* Channel 10 Service Status */ + uint32_t SS9:1; /* Channel 9 Service Status */ + uint32_t SS8:1; /* Channel 8 Service Status */ + uint32_t SS7:1; /* Channel 7 Service Status */ + uint32_t SS6:1; /* Channel 6 Service Status */ + uint32_t SS5:1; /* Channel 5 Service Status */ + uint32_t SS4:1; /* Channel 4 Service Status */ + uint32_t SS3:1; /* Channel 3 Service Status */ + uint32_t SS2:1; /* Channel 2 Service Status */ + uint32_t SS1:1; /* Channel 1 Service Status */ + uint32_t SS0:1; /* Channel 0 Service Status */ + } B; + } CSSR_B; + + uint32_t eTPU_reserved0298[2]; /* 0x0298-0x029F */ + + uint32_t eTPU_reserved02A0[88]; /* 0x02A0-0x03FF */ + +/*****************************Channels********************************/ + + struct { + union { /* Channel Configuration Register */ + uint32_t R; + struct { + uint32_t CIE:1; /* Channel Interruput Enable */ + uint32_t DTRE:1; /* Data Transfer Request Enable */ + uint32_t CPR:2; /* Channel Priority */ + uint32_t:2; + uint32_t ETPD:1; + uint32_t ETCS:1; /* Entry Table Condition Select */ + uint32_t:3; + uint32_t CFS:5; /* Channel Function Select */ + uint32_t ODIS:1; /* Output disable */ + uint32_t OPOL:1; /* output polarity */ + uint32_t:3; + uint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; + + union { /* Channel Status Control Register */ + uint32_t R; + struct { + uint32_t CIS:1; /* Channel Interruput Status */ + uint32_t CIOS:1; /* Channel Interruput Overflow Status */ + uint32_t:6; + uint32_t DTRS:1; /* Data Transfer Status */ + uint32_t DTROS:1; /* Data Transfer Overflow Status */ + uint32_t:6; + uint32_t IPS:1; /* Input Pin State */ + uint32_t OPS:1; /* Output Pin State */ + uint32_t OBE:1; /* Output Buffer Enable */ + uint32_t:11; + uint32_t FM1:1; /* Function mode */ + uint32_t FM0:1; /* Function mode */ + } B; + } SCR; + + union { /* Channel Host Service Request Register */ + uint32_t R; + struct { + uint32_t:29; /* Host Service Request */ + uint32_t HSR:3; + } B; + } HSRR; + + uint32_t eTPU_ch_reserved00C; /* channel offset 0x00C-0x00F */ + + } CHAN[127]; + + uint32_t eTPU_reserved1000[7168]; /* 0x1000-0x7FFF */ + + }; + +/****************************************************************************/ +/* MODULE : PIT / RTI */ +/****************************************************************************/ + + struct PIT_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:29; + uint32_t MDIS_RTI:1; + uint32_t MDIS:1; + uint32_t FRZ:1; + } B; + } MCR; + + uint32_t PIT_reserved0004[59]; /* 0x0004-0x00EF */ + + struct { + union { + uint32_t R; /* <URM>TSVn</URM> */ + } LDVAL; /* Timer Load Value Register */ + + union { + uint32_t R; /* <URM>TVLn</URM> */ + } CVAL; /* Current Timer Value Register */ + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; + uint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } RTI; /* RTI Channel */ + + struct { + union { + uint32_t R; + struct { + uint32_t TSV:32; + } B; + } LDVAL; + + union { + uint32_t R; + struct { + uint32_t TVL:32; + } B; + } CVAL; + + union { + uint32_t R; + struct { + uint32_t:30; + uint32_t TIE:1; + uint32_t TEN:1; + } B; + } TCTRL; + + union { + uint32_t R; + struct { + uint32_t:31; + uint32_t TIF:1; + } B; + } TFLG; + } CH[4]; + + uint32_t PIT_reserved00140[4016]; /* 0x0140-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : XBAR CrossBar */ +/****************************************************************************/ + + struct XBAR_tag { + + union { /* Master Priority Register for Slave Port 0 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR0; + + uint32_t XBAR_reserved0004[3]; /* 0x0004-0x000F */ + + union { /* General Purpose Control Register for Slave Port 0 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR0; + + uint32_t XBAR_reserved0014[59]; /* 0x0014-0x00FF */ + + union { /* Master Priority Register for Slave Port 1 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR1; + + uint32_t XBAR_reserved0104[3]; /* 0x0104-0x010F */ + + union { /* General Purpose Control Register for Slave Port 1 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR1; + + uint32_t XBAR_reserved0114[59]; /* 0x0114-0x01FF */ + + union { /* Master Priority Register for Slave Port 2 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR2; + + uint32_t XBAR_reserved0204[3]; /* 0x0204-0x020F */ + + union { /* General Purpose Control Register for Slave Port 2 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR2; + + uint32_t XBAR_reserved0214[59]; /* 0x0214-0x02FF */ + + uint32_t XBAR_reserved0300[64]; /* 0x0300-0x03FF */ + + uint32_t XBAR_reserved0400[64]; /* 0x0400-0x04FF */ + + uint32_t XBAR_reserved0500[64]; /* 0x0500-0x05FF */ + + union { /* Master Priority Register for Slave Port 6 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR6; + + uint32_t XBAR_reserved604[3]; /* 0x0604-0x060F */ + + union { /* General Purpose Control Register for Slave Port 6 */ + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR6; + + uint32_t XBAR_reserved0614[59]; /* 0x0614-0x06FF */ + + union { /* Master Priority Register for Slave Port 7 */ + uint32_t R; + struct { + uint32_t:1; + uint32_t MSTR7:3; /* EBI (development bus) */ + uint32_t:1; + uint32_t MSTR6:3; /* FlexRay */ + uint32_t:1; + uint32_t MSTR5:3; /* eDMA_B */ + uint32_t:1; + uint32_t MSTR4:3; /* eDMA_A */ + uint32_t:1; + uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */ + uint32_t:1; + uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */ + uint32_t:1; + uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */ + uint32_t:1; + uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */ + } B; + } MPR7; + + uint32_t XBAR_reserved704[3]; /* 0x0704-0x070F */ + + union { + uint32_t R; + struct { + uint32_t RO:1; + uint32_t:21; + uint32_t ARB:2; + uint32_t:2; + uint32_t PCTL:2; + uint32_t:1; + uint32_t PARK:3; + } B; + } SGPCR7; /* General Purpose Control Register for Slave Port 7 */ + + uint32_t XBAR_reserved0714[59]; /* 0x0714-0x07FF */ + + uint32_t XBAR_reserved0800[3584]; /* 0x0800-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : MPU */ +/****************************************************************************/ + + struct MPU_tag { + + union { /* Module Control/Error Status Register */ + uint32_t R; + struct { + uint32_t SPERR:8; + uint32_t:4; + uint32_t HRL:4; + uint32_t NSP:4; + uint32_t NRGD:4; + uint32_t:7; + uint32_t VLD:1; + } B; + } CESR; + + uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */ + + struct { + union { /* MPU Error Address Registers */ + uint32_t R; + struct { + uint32_t EADDR:32; + } B; + } EAR; + + union { /* MPU Error Detail Registers */ + uint32_t R; + struct { + uint32_t EACD:16; + uint32_t EPID:8; + uint32_t EMN:4; + uint32_t EATTR:3; + uint32_t ERW:1; + } B; + } EDR; + } PORT[3]; + + uint32_t MPU_reserved0028[246]; /* 0x0028-0x03FF */ + + struct { + union { /* Region Descriptor n Word 0 */ + uint32_t R; + struct { + uint32_t SRTADDR:27; + uint32_t:5; + } B; + } WORD0; + + union { /* Region Descriptor n Word 1 */ + uint32_t R; + struct { + uint32_t ENDADDR:27; + uint32_t:5; + } B; + } WORD1; + + union { /* Region Descriptor n Word 2 */ + uint32_t R; + struct { + uint32_t M7RE:1; + uint32_t M7WE:1; + uint32_t M6RE:1; + uint32_t M6WE:1; + uint32_t M5RE:1; + uint32_t M5WE:1; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t: 18; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } WORD2; + + union { /* Region Descriptor n Word 3 */ + uint32_t R; + struct { + uint32_t PID:8; + uint32_t PIDMASK:8; + uint32_t:15; + uint32_t VLD:1; + } B; + } WORD3; + } RGD[16]; + + uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */ + + union { /* Region Descriptor Alternate Access Control n */ + uint32_t R; + struct { + uint32_t:6; + uint32_t M4RE:1; + uint32_t M4WE:1; + uint32_t M3PE:1; + uint32_t M3SM:2; + uint32_t M3UM:3; + uint32_t M2PE:1; + uint32_t M2SM:2; + uint32_t M2UM:3; + uint32_t M1PE:1; + uint32_t M1SM:2; + uint32_t M1UM:3; + uint32_t M0PE:1; + uint32_t M0SM:2; + uint32_t M0UM:3; + } B; + } RGDAAC[16]; + + uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + + struct SWT_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MAP0:1; + uint32_t MAP1:1; + uint32_t:1; + uint32_t:1; + uint32_t MAP4:1; + uint32_t MAP5:1; + uint32_t MAP6:1; + uint32_t MAP7:1; + uint32_t:14; + uint32_t KEY:1; + uint32_t RIA:1; + uint32_t WND:1; + uint32_t ITR:1; + uint32_t HLK:1; + uint32_t SLK:1; + uint32_t CSL:1; + uint32_t STP:1; + uint32_t FRZ:1; + uint32_t WEN:1; + } B; + } MCR; + + union { /* Interrupt register */ + uint32_t R; + struct { + uint32_t :31; + uint32_t TIF:1; + } B; + } IR; + + union { /* Timeout register */ + uint32_t R; + struct { + uint32_t WTO:32; + } B; + } TO; + + union { /* Window register */ + uint32_t R; + struct { + uint32_t WST:32; + } B; + } WN; + + union { /* Service register */ + uint32_t R; + struct { + uint32_t :16; + uint32_t WSC:16; + } B; + } SR; + + union { /* Counter output register */ + uint32_t R; + struct { + uint32_t CNT:32; + } B; + } CO; + + union { /* Service key register */ + uint32_t R; + struct { + uint32_t :16; + uint32_t SK:16; + } B; + } SK; + + uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : STM */ +/****************************************************************************/ + + struct STM_tag { + + union { /* Control Register */ + uint32_t R; + struct { + uint32_t :16; + uint32_t CPS:8; + uint32_t :6; + uint32_t FRZ:1; + uint32_t TEN:1; + } B; + } CR; + + union { /* STM Counter */ + uint32_t R; + } CNT; + + uint32_t STM_reserved0008[2]; /* 0x0008-0x000F */ + + /* channel 0 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR0; /* Chan 0 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR0; /* Chan 0 Interrupt Register */ + + union { + uint32_t R; + } CMP0; /* Chan 0 Compare Register */ + + uint32_t STM_reserved2[1]; + +/* channel 1 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR1; /* Chan 1 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR1; /* Chan 1 Interrupt Register */ + + union { + uint32_t R; + } CMP1; /* Chan 1 Compare Register */ + + uint32_t STM_reserved3[1]; + +/* channel 2 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR2; /* Chan 2 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR2; /* Chan 2 Interrupt Register */ + + union { + uint32_t R; + } CMP2; /* Chan 2 Compare Register */ + + uint32_t STM_reserved4[1]; + +/* channel 3 registers */ + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CEN:1; + } B; + } CCR3; /* Chan 3 Control Register */ + + union { + uint32_t R; + struct { + uint32_t :31; + uint32_t CIF:1; + } B; + } CIR3; /* Chan 3 Interrupt Register */ + + union { + uint32_t R; + } CMP3; /* Chan 3 Compare Register */ + + uint32_t STM_reserved0050[4076]; /* 0x0050-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + + struct ECSM_tag { + + union { /* Processor core type */ + uint16_t R; + } PCT; + + union { /* Platform revision */ + uint16_t R; + } REV; + + uint32_t ECSM_reserved0004; /* 0x0004-0x0007 */ + + union { /* IPS Module Configuration */ + uint32_t R; + } IMC; + + uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */ + + union { /* Miscellaneous Reset Status Register */ + uint8_t R; + struct { + uint8_t POR:1; + uint8_t DIR:1; + uint8_t SWTR:1; + uint8_t:5; + } B; + } MRSR; + + uint8_t ECSM_reserved0010[51]; /* 0x0010-0x0042 */ + + union { /* ECC Configuration Register */ + uint8_t R; + struct { + uint8_t:2; + uint8_t ER1BR:1; + uint8_t EF1BR:1; + uint8_t:2; + uint8_t ERNCR:1; + uint8_t EFNCR:1; + } B; + } ECR; + + uint8_t ECSM_reserved0044[3]; /* 0x0044-0x0046 */ + + union { /* ECC Status Register */ + uint8_t R; + struct { + uint8_t:2; + uint8_t R1BC:1; + uint8_t F1BC:1; + uint8_t:2; + uint8_t RNCE:1; + uint8_t FNCE:1; + } B; + } ESR; + + uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */ + + union { /* ECC Error Generation Register */ + uint16_t R; + struct { + uint16_t:2; + uint16_t FRC1BI:1; + uint16_t FR11BI:1; + uint16_t:2; + uint16_t FRCNCI:1; + uint16_t FR1NCI:1; + uint16_t:1; + uint16_t ERRBIT:7; + } B; + } EEGR; + + uint32_t ECSM_reserved004C; /* 0x004C-0x004F */ + + union { /* Flash ECC Address Register */ + uint32_t R; + struct { + uint32_t FEAR:32; + } B; + } FEAR; + + uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */ + + union { /* Flash ECC Master Number Register */ + uint8_t R; + struct { + uint8_t:4; + uint8_t FEMR:4; + } B; + } FEMR; + + union { /* Flash ECC Attributes Register */ + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } FEAT; + + union { /* Flash ECC Data Register High */ + uint32_t R; + struct { + uint32_t FEDH:32; + } B; + } FEDRH; + + union { /* Flash ECC Data Register Low */ + uint32_t R; + struct { + uint32_t FEDL:32; + } B; + } FEDRL; + + union { /* RAM ECC Address Register */ + uint32_t R; + struct { + uint32_t REAR:32; + } B; + } REAR; + + uint16_t ECSM_reserved0064; /* 0x0064-0x0065 */ + + union { /* RAM ECC Master Number Register */ + uint8_t R; + struct { + uint8_t:4; + uint8_t REMR:4; + } B; + } REMR; + + union { /* RAM ECC Attributes Register */ + uint8_t R; + struct { + uint8_t WRITE:1; + uint8_t SIZE:3; + uint8_t PROT0:1; + uint8_t PROT1:1; + uint8_t PROT2:1; + uint8_t PROT3:1; + } B; + } REAT; + + union { /* RAM ECC Data Register */ + uint32_t R; + struct { + uint32_t REDH:32; + } B; + } REDRH; + + union { /* RAM ECC Data Register */ + uint32_t R; + struct { + uint32_t REDL:32; + } B; + } REDRL; + + uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + + struct INTC_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:26; + uint32_t VTES:1; + uint32_t:4; + uint32_t HVEN:1; + } B; + } MCR; + + uint32_t INTC_reserved0004; /* 0x0004-0x0007 */ + + union { /* Current Priority Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t PRI:4; + } B; + } CPR; + + uint32_t INTC_reserved000C; /* 0x000C-0x000F */ + + union { /* Interrupt Acknowledge Register */ + uint32_t R; + struct { + uint32_t VTBA:21; + uint32_t INTVEC:9; + uint32_t:2; + } B; + } IACKR; + + uint32_t INTC_reserved0014; /* 0x0014-0x0017 */ + + union { /* End of Interrupt Register */ + uint32_t R; + struct { + uint32_t EOIR:32; + } B; + } EOIR; + + uint32_t INTC_reserved001C; /* 0x001C-0x001F */ + + union { /* Software Set/Clear Interruput Register */ + uint8_t R; + struct { + uint8_t:6; + uint8_t SET:1; + uint8_t CLR:1; + } B; + } SSCIR[8]; + + uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */ + + union { /* Software Set/Clear Interrupt Register */ + uint8_t R; + struct { + uint8_t:4; + uint8_t PRI:4; + } B; + } PSR[480]; + + uint16_t INTC_reserved0220[7920]; /* 0x0220-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + + struct EQADC_tag { + + union EQADC_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t:24; + uint32_t ICEA0:1; + uint32_t ICEA1:1; + uint32_t:1; + uint32_t ESSIE:2; + uint32_t:1; + uint32_t DBG:2; + } B; + } MCR; + + uint32_t eQADC_reserved0004; /* 0x0004-0x0007 */ + + union EQADC_NMSFR_tag { /* Null Message Send Format Register */ + uint32_t R; + struct { + uint32_t:6; + uint32_t NMF:26; + } B; + } NMSFR; + + union EQADC_ETDFR_tag { /* External Trigger Digital Filter Register */ + uint32_t R; + struct { + uint32_t:28; + uint32_t DFL:4; + } B; + } ETDFR; + + union EQADC_CFPR_tag { /* CFIFO Push Registers */ + uint32_t R; + struct { + uint32_t CFPUSH:32; + } B; + } CFPR[6]; + + uint32_t eQADC_reserved0028[2]; /* 0x0028-0x002F */ + + union EQADC_RFPR_tag { /* Result FIFO Pop Registers */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RFPOP:16; + } B; + } RFPR[6]; + + uint32_t eQADC_reserved0048[2]; /* 0x0048-0x004F */ + + union EQADC_CFCR_tag { /* CFIFO Control Registers */ + uint16_t R; + struct { + uint16_t:3; + uint16_t CFEEE0:1; + uint16_t STRME0:1; + uint16_t SSE:1; + uint16_t CFINV:1; + uint16_t:1; + uint16_t MODE:4; + uint16_t AMODE0:4; + } B; + } CFCR[6]; + + uint32_t eQADC_reserved005C; /* 0x005C-0x005F */ + + union EQADC_IDCR_tag { /* Interrupt and DMA Control Registers */ + uint16_t R; + struct { + uint16_t NCIE:1; + uint16_t TORIE:1; + uint16_t PIE:1; + uint16_t EOQIE:1; + uint16_t CFUIE:1; + uint16_t:1; + uint16_t CFFE:1; + uint16_t CFFS:1; + uint16_t:4; + uint16_t RFOIE:1; + uint16_t:1; + uint16_t RFDE:1; + uint16_t RFDS:1; + } B; + } IDCR[6]; + + uint32_t eQADC_reserved006C; /* 0x006C-0x006F */ + + union { /* FIFO and Interrupt Status Registers */ + uint32_t R; + struct { + uint32_t NCF:1; + uint32_t TORF:1; + uint32_t PF:1; + uint32_t EOQF:1; + uint32_t CFUF:1; + uint32_t SSS:1; + uint32_t CFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t CFCTR:4; + uint32_t TNXTPTR:4; + uint32_t RFCTR:4; + uint32_t POPNXTPTR:4; + } B; + } FISR[6]; + + uint32_t eQADC_reserved0088[2]; /* 0x0088-0x008F */ + + union { /* CFIFO Transfer Counter Registers */ + uint16_t R; + struct { + uint16_t:5; + uint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */ + } B; + } CFTCR[6]; + + uint32_t eQADC_reserved009C[1]; /* 0x009F */ + + union { /* CFIFO Status Register 0 */ + uint32_t R; + struct { + uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */ + uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */ + uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */ + uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */ + uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */ + uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */ + uint32_t:5; + uint32_t LCFTCB0:4; + uint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; + + union { /* CFIFO Status Register 1 */ + uint32_t R; + struct { + uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */ + uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */ + uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */ + uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */ + uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */ + uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */ + uint32_t:5; + uint32_t LCFTCB1:4; + uint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; + + union { /* CFIFO Status Register 2 */ + uint32_t R; + struct { + uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TSSI in Reference Manual */ + uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TSSI in Reference Manual */ + uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TSSI in Reference Manual */ + uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TSSI in Reference Manual */ + uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TSSI in Reference Manual */ + uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TSSI in Reference Manual */ + uint32_t:4; + uint32_t ECBNI:1; + uint32_t LCFTSSI:4; + uint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; + + union { /* CFIFO Status Register */ + uint32_t R; + struct { + uint32_t CFS0:2; + uint32_t CFS1:2; + uint32_t CFS2:2; + uint32_t CFS3:2; + uint32_t CFS4:2; + uint32_t CFS5:2; + uint32_t:20; + } B; + } CFSR; + + uint32_t eQADC_reserved00B0; /* 0x00B0-0x00B3 */ + + union EQADC_SSICR_tag { /* SSI Control Register */ + uint32_t R; + struct { + uint32_t:21; + uint32_t MDT:3; + uint32_t:4; + uint32_t BR:4; + } B; + } SSICR; + + union { /* SSI Recieve Data Register */ + uint32_t R; + struct { + uint32_t RDV:1; + uint32_t:5; + uint32_t RDATA:26; + } B; + } SSIRDR; + + uint32_t eQADC_reserved00BC[17]; /* 0x00BC-0x00FF */ + + struct { + union { + uint32_t R; + struct { + uint32_t CFIFO_DATA:32; + } B; + } R[4]; + + uint32_t eQADC_cf_reserved010[12]; /* CFIFO offset 0x010-0x03F */ + + } CF[6]; + + uint32_t eQADC_reserved0280[32]; /* 0x0280-0x02FF */ + + struct { + union { + uint32_t R; + struct { + uint32_t RFIFO_DATA:32; + } B; + } R[4]; + + uint32_t eQADC_rf_reserved010[12]; /* RFIFO offset 0x010-0x03F */ + + } RF[6]; + + uint32_t eQADC_reserved0480[3808]; /* 0x0480-0x3FFF */ + }; + +/****************************************************************************/ +/* MODULE : Decimation Filter */ +/****************************************************************************/ + + struct DECFIL_tag { + + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FREN:1; + uint32_t :1; + uint32_t FRZ:1; + uint32_t SRES:1; + uint32_t CASCD:2; + uint32_t IDEN:1; + uint32_t ODEN:1; + uint32_t ERREN:1; + uint32_t :1; + uint32_t FTYPE:2; + uint32_t :1; + uint32_t SCAL:2; + uint32_t :1; + uint32_t SAT:1; + uint32_t ISEL:1; + uint32_t :1; + uint32_t DEC_RATE:4; + uint32_t :1; + uint32_t DSEL:1; + uint32_t IBIE:1; + uint32_t OBIE:1; + uint32_t EDME:1; + uint32_t TORE:1; + uint32_t TRFE:1; + uint32_t :1; + } B; + } MCR; + + union { /* Module Status Register */ + uint32_t R; + struct { + uint32_t BSY:1; + uint32_t:1; + uint32_t DEC_COUNTER:4; + uint32_t IDFC:1; + uint32_t ODFC:1; + uint32_t:1; + uint32_t IBIC:1; + uint32_t OBIC:1; + uint32_t:1; + uint32_t DIVRC:1; + uint32_t OVFC:1; + uint32_t OVRC:1; + uint32_t IVRC:1; + uint32_t:6; + uint32_t IDF:1; + uint32_t ODF:1; + uint32_t:1; + uint32_t IBIF:1; + uint32_t OBIF:1; + uint32_t:1; + uint32_t DIVR:1; + uint32_t OVF:1; + uint32_t OVR:1; + uint32_t IVR:1; + } B; + } SR; + + union { /* Module Extended Config Register */ + uint32_t R; + struct { + uint32_t SDMAE:1; + uint32_t SSIG:1; + uint32_t SSAT:1; + uint32_t SCSAT:1; + uint32_t:10; + uint32_t SRQ:1; + uint32_t SZR0:1; + uint32_t:1; + uint32_t SISEL:1; + uint32_t SZROSEL:2; + uint32_t:2; + uint32_t SHLTSEL:2; + uint32_t:1; + uint32_t SRQSEL:3; + uint32_t:2; + uint32_t SENSEL:2; + } B; + } MXCR; + + union { /* Module Extended Status Register */ + uint32_t R; + struct { + uint32_t:7; + uint32_t SDFC:1; + uint32_t:2; + uint32_t SSEC:1; + uint32_t SCEC:1; + uint32_t:1; + uint32_t SSOVFC:1; + uint32_t SCOVFC:1; + uint32_t SVRC:1; + uint32_t:7; + uint32_t SDF:1; + uint32_t:2; + uint32_t SSE:1; + uint32_t SCE:1; + uint32_t:1; + uint32_t SSOVF:1; + uint32_t SCOVF:1; + uint32_t SVR:1; + } B; + } MXSR; + + union { /* Interface Input Buffer Register */ + uint32_t R; + struct { + uint32_t:14; + uint32_t PREFILL:1; + uint32_t FLUSH:1; + uint32_t INPBUF:16; + } B; + } IB; + + union { /* Interface Output Buffer Register */ + uint32_t R; + struct { + uint32_t:9; + uint32_t TSI:1; + uint32_t:2; + uint32_t OUTTAG:4; + uint32_t OUTBUF:16; + } B; + } OB; + + uint32_t DFILT_reserved0018[2]; /* 0x0018-0x001F */ + + union { /* Coefficient n Register */ + int32_t R; + struct { + int32_t:8; + int32_t COEF:24; + } B; + } COEF[9]; + + uint32_t DFILT_reserved0044[13]; /* 0x0044-0x0077 */ + + union { /* TAP n Register */ + int32_t R; + struct { + int32_t:8; + int32_t TAP:24; + } B; + } TAP[8]; + + uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */ + + union { /* EDID Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t SAMP_DATA:16; + } B; + } EDID; + + uint32_t DFILT_reserved00D4[459]; /* 0x00D4-0x07FF */ + + }; + +/****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + + struct DSPI_tag { + + union DSPI_MCR_tag { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MSTR:1; + uint32_t CONT_SCKE:1; + uint32_t DCONF:2; + uint32_t FRZ:1; + uint32_t MTFE:1; + uint32_t PCSSE:1; + uint32_t ROOE:1; + uint32_t PCSIS7:1; + uint32_t PCSIS6:1; + uint32_t PCSIS5:1; + uint32_t PCSIS4:1; + uint32_t PCSIS3:1; + uint32_t PCSIS2:1; + uint32_t PCSIS1:1; + uint32_t PCSIS0:1; + uint32_t DOZE:1; + uint32_t MDIS:1; + uint32_t DIS_TXF:1; + uint32_t DIS_RXF:1; + uint32_t CLR_TXF:1; + uint32_t CLR_RXF:1; + uint32_t SMPL_PT:2; + uint32_t:7; + uint32_t HALT:1; + } B; + } MCR; + + uint32_t DSPI_reserved0004; /* 0x0004-0x0007 */ + + union { /* Transfer Count Register */ + uint32_t R; + struct { + uint32_t TCNT:16; + uint32_t:16; + } B; + } TCR; + + union DSPI_CTAR_tag {/* Clock and Transfer Attributes Registers */ + uint32_t R; + struct { + uint32_t DBR:1; + uint32_t FMSZ:4; + uint32_t CPOL:1; + uint32_t CPHA:1; + uint32_t LSBFE:1; + uint32_t PCSSCK:2; + uint32_t PASC:2; + uint32_t PDT:2; + uint32_t PBR:2; + uint32_t CSSCK:4; + uint32_t ASC:4; + uint32_t DT:4; + uint32_t BR:4; + } B; + } CTAR[8]; + + union DSPI_SR_tag { /* Status Register */ + uint32_t R; + struct { + uint32_t TCF:1; + uint32_t TXRXS:1; + uint32_t:1; + uint32_t EOQF:1; + uint32_t TFUF:1; + uint32_t:1; + uint32_t TFFF:1; + uint32_t:5; + uint32_t RFOF:1; + uint32_t:1; + uint32_t RFDF:1; + uint32_t:1; + uint32_t TXCTR:4; + uint32_t TXNXTPTR:4; + uint32_t RXCTR:4; + uint32_t POPNXTPTR:4; + } B; + } SR; + + union DSPI_RSER_tag { /* DMA/Interrupt Request Select and Enable Register */ + uint32_t R; + struct { + uint32_t TCFRE:1; + uint32_t:2; + uint32_t EOQFRE:1; + uint32_t TFUFRE:1; + uint32_t:1; + uint32_t TFFFRE:1; + uint32_t TFFFDIRS:1; + uint32_t:4; + uint32_t RFOFRE:1; + uint32_t:1; + uint32_t RFDFRE:1; + uint32_t RFDFDIRS:1; + uint32_t:16; + } B; + } RSER; + + union DSPI_PUSHR_tag { /* PUSH TX FIFO Register */ + uint32_t R; + struct { + uint32_t CONT:1; + uint32_t CTAS:3; + uint32_t EOQ:1; + uint32_t CTCNT:1; + uint32_t:2; + uint32_t PCS7:1; + uint32_t PCS6:1; + uint32_t PCS5:1; + uint32_t PCS4:1; + uint32_t PCS3:1; + uint32_t PCS2:1; + uint32_t PCS1:1; + uint32_t PCS0:1; + uint32_t TXDATA:16; + } B; + } PUSHR; + + union DSPI_POPR_tag { /* POP RX FIFO Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } POPR; + + union { /* Transmit FIFO Registers */ + uint32_t R; + struct { + uint32_t TXCMD:16; + uint32_t TXDATA:16; + } B; + } TXFR[4]; + + uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */ + + union { /* Transmit FIFO Registers */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXDATA:16; + } B; + } RXFR[4]; + + uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */ + + union { /* DSI Configuration Register */ + uint32_t R; + struct { + uint32_t MTOE:1; + uint32_t:1; + uint32_t MTOCNT:6; + uint32_t:3; + uint32_t TSBC:1; + uint32_t TXSS:1; + uint32_t TPOL:1; + uint32_t TRRE:1; + uint32_t CID:1; + uint32_t DCONT:1; + uint32_t DSICTAS:3; + uint32_t:4; + uint32_t DPCS7:1; + uint32_t DPCS6:1; + uint32_t DPCS5:1; + uint32_t DPCS4:1; + uint32_t DPCS3:1; + uint32_t DPCS2:1; + uint32_t DPCS1:1; + uint32_t DPCS0:1; + } B; + } DSICR; + + union { /* DSI Serialization Data Register */ + uint32_t R; + struct { + uint32_t SER_DATA:32; + } B; + } SDR; + + union { /* DSI Alternate Serialization Data Register */ + uint32_t R; + struct { + uint32_t ASER_DATA:32; + } B; + } ASDR; + + union { /* DSI Transmit Comparison Register */ + uint32_t R; + struct { + uint32_t COMP_DATA:32; + } B; + } COMPR; + + union { /* DSI deserialization Data Register */ + uint32_t R; + struct { + uint32_t DESER_DATA:32; + } B; + } DDR; + + union { + uint32_t R; + struct { + uint32_t:3; + uint32_t TSBCNT:5; + uint32_t:16; + uint32_t DPCS1_7:1; + uint32_t DPCS1_6:1; + uint32_t DPCS1_5:1; + uint32_t DPCS1_4:1; + uint32_t DPCS1_3:1; + uint32_t DPCS1_2:1; + uint32_t DPCS1_1:1; + uint32_t DPCS1_0:1; + } B; + } DSICR1; + uint32_t DSPI_reserved00D4[4043]; /* 0x00D4-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + + struct ESCI_tag { + union ESCI_CR1_tag { /* Control Register 1 */ + uint32_t R; + struct { + uint32_t:3; + uint32_t SBR:13; + uint32_t LOOPS:1; + uint32_t:1; + uint32_t RSRC:1; + uint32_t M:1; + uint32_t WAKE:1; + uint32_t ILT:1; + uint32_t PE:1; + uint32_t PT:1; + uint32_t TIE:1; + uint32_t TCIE:1; + uint32_t RIE:1; + uint32_t ILIE:1; + uint32_t TE:1; + uint32_t RE:1; + uint32_t RWU:1; + uint32_t SBK:1; + } B; + } CR1; + + union ESCI_CR2_tag { /* Control Register 2 */ + uint16_t R; + struct { + uint16_t MDIS:1; + uint16_t FBR:1; + uint16_t BSTP:1; + uint16_t IEBERR:1; + uint16_t RXDMA:1; + uint16_t TXDMA:1; + uint16_t BRK13:1; + uint16_t TXDIR:1; + uint16_t BESM13:1; + uint16_t SBSTP:1; + uint16_t RXPOL:1; + uint16_t PMSK:1; + uint16_t ORIE:1; + uint16_t NFIE:1; + uint16_t FEIE:1; + uint16_t PFIE:1; + } B; + } CR2; + + union ESCI_DR_tag { /* Data Register */ + uint16_t R; + + struct { + uint16_t RN:1; + uint16_t TN:1; + uint16_t ERR:1; + uint16_t:1; + uint16_t RD_11:4; + uint16_t D:8; + } B; + } DR; /* Legacy naming - refer to SDR in Reference Manual */ + + union ESCI_SR_tag { /* Status Register */ + uint32_t R; + struct { + uint32_t TDRE:1; + uint32_t TC:1; + uint32_t RDRF:1; + uint32_t IDLE:1; + uint32_t OR:1; + uint32_t NF:1; + uint32_t FE:1; + uint32_t PF:1; + uint32_t:3; + uint32_t BERR:1; + uint32_t:2; + uint32_t TACT:1; + uint32_t RAF:1; + uint32_t RXRDY:1; + uint32_t TXRDY:1; + uint32_t LWAKE:1; + uint32_t STO:1; + uint32_t PBERR:1; + uint32_t CERR:1; + uint32_t CKERR:1; + uint32_t FRC:1; + uint32_t:6; + uint32_t UREQ:1; + uint32_t OVFL:1; + } B; + } SR; + + union { /* LIN Control Register */ + uint32_t R; + struct { + uint32_t LRES:1; + uint32_t WU:1; + uint32_t WUD0:1; + uint32_t WUD1:1; + uint32_t :2; + uint32_t PRTY:1; + uint32_t LIN:1; + uint32_t RXIE:1; + uint32_t TXIE:1; + uint32_t WUIE:1; + uint32_t STIE:1; + uint32_t PBIE:1; + uint32_t CIE:1; + uint32_t CKIE:1; + uint32_t FCIE:1; + uint32_t:6; + uint32_t UQIE:1; + uint32_t OFIE:1; + uint32_t:8; + } B; + } LCR; + + union { /* LIN Transmit Register */ + uint8_t R; + } LTR; + + uint8_t eSCI_reserved0011[3]; /* 0x0011-0x0013 */ + + union { /* LIN Recieve Register */ + uint8_t R; + struct { + uint8_t D:8; + } B; + } LRR; + + uint8_t eSCI_reserved0015[3]; /* 0x0015-0x0017 */ + + union { /* LIN CRC Polynom Register */ + uint16_t R; + struct { + uint16_t P:16; + } B; + } LPR; + + union { /* Control Register 3 */ + uint16_t R; + struct { + uint16_t:3; + uint16_t SYNM:1; + uint16_t EROE:1; + uint16_t ERFE:1; + uint16_t ERPE:1; + uint16_t M2:1; + uint16_t:8; + } B; + } CR3; + + uint32_t eSCI_reserved001C; /* 0x001C-0x001F */ + + uint32_t eSCI_reserved0020[4088]; /* 0x0020-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + + struct FLEXCAN2_tag { + union { /* Module Configuration Register */ + uint32_t R; + struct { + uint32_t MDIS:1; + uint32_t FRZ:1; + uint32_t FEN:1; + uint32_t HALT:1; + uint32_t NOTRDY:1; + uint32_t WAK_MSK:1; + uint32_t SOFTRST:1; + uint32_t FRZACK:1; + uint32_t SUPV:1; + uint32_t SLF_WAK:1; + uint32_t WRNEN:1; + uint32_t MDISACK:1; + uint32_t WAK_SRC:1; + uint32_t DOZE:1; + uint32_t SRXDIS:1; + uint32_t BCC:1; + uint32_t:2; + uint32_t LPRIO_EN:1; + uint32_t AEN:1; + uint32_t:2; + uint32_t IDAM:2; + uint32_t:2; + uint32_t MAXMB:6; + } B; + } MCR; + + union { /* Control Register */ + uint32_t R; + struct { + uint32_t PRESDIV:8; + uint32_t RJW:2; + uint32_t PSEG1:3; + uint32_t PSEG2:3; + uint32_t BOFFMSK:1; + uint32_t ERRMSK:1; + uint32_t CLKSRC:1; + uint32_t LPB:1; + uint32_t TWRNMSK:1; + uint32_t RWRNMSK:1; + uint32_t:2; + uint32_t SMP:1; + uint32_t BOFFREC:1; + uint32_t TSYN:1; + uint32_t LBUF:1; + uint32_t LOM:1; + uint32_t PROPSEG:3; + } B; + } CR; /* Legacy naming - refer to CTRL in Reference Manual */ + + union { /* Free Running Timer */ + uint32_t R; + } TIMER; + + int32_t FLEXCAN_reserved000C; /* 0x000C-0x000F */ + + union { /* RX Global Mask */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RXGMASK; + + union { /* RX 14 Mask */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RX14MASK; + + union { /* RX 15 Mask */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RX15MASK; + + union { /* Error Counter Register */ + uint32_t R; + struct { + uint32_t:16; + uint32_t RXECNT:8; + uint32_t TXECNT:8; + } B; + } ECR; + + union { /* Error and Status Register */ + uint32_t R; + struct { + uint32_t:14; + + uint32_t TWRNINT:1; + uint32_t RWRNINT:1; + uint32_t BIT1ERR:1; + uint32_t BIT0ERR:1; + uint32_t ACKERR:1; + uint32_t CRCERR:1; + uint32_t FRMERR:1; + uint32_t STFERR:1; + uint32_t TXWRN:1; + uint32_t RXWRN:1; + uint32_t IDLE:1; + uint32_t TXRX:1; + uint32_t FLTCONF:2; + uint32_t:1; + uint32_t BOFFINT:1; + uint32_t ERRINT:1; + uint32_t WAKINT:1; + } B; + } ESR; + + union { /* Interruput Masks Register */ + uint32_t R; + struct { + uint32_t BUF63M:1; + uint32_t BUF62M:1; + uint32_t BUF61M:1; + uint32_t BUF60M:1; + uint32_t BUF59M:1; + uint32_t BUF58M:1; + uint32_t BUF57M:1; + uint32_t BUF56M:1; + uint32_t BUF55M:1; + uint32_t BUF54M:1; + uint32_t BUF53M:1; + uint32_t BUF52M:1; + uint32_t BUF51M:1; + uint32_t BUF50M:1; + uint32_t BUF49M:1; + uint32_t BUF48M:1; + uint32_t BUF47M:1; + uint32_t BUF46M:1; + uint32_t BUF45M:1; + uint32_t BUF44M:1; + uint32_t BUF43M:1; + uint32_t BUF42M:1; + uint32_t BUF41M:1; + uint32_t BUF40M:1; + uint32_t BUF39M:1; + uint32_t BUF38M:1; + uint32_t BUF37M:1; + uint32_t BUF36M:1; + uint32_t BUF35M:1; + uint32_t BUF34M:1; + uint32_t BUF33M:1; + uint32_t BUF32M:1; + } B; + } IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */ + + union { /* Interruput Masks Register */ + uint32_t R; + struct { + uint32_t BUF31M:1; + uint32_t BUF30M:1; + uint32_t BUF29M:1; + uint32_t BUF28M:1; + uint32_t BUF27M:1; + uint32_t BUF26M:1; + uint32_t BUF25M:1; + uint32_t BUF24M:1; + uint32_t BUF23M:1; + uint32_t BUF22M:1; + uint32_t BUF21M:1; + uint32_t BUF20M:1; + uint32_t BUF19M:1; + uint32_t BUF18M:1; + uint32_t BUF17M:1; + uint32_t BUF16M:1; + uint32_t BUF15M:1; + uint32_t BUF14M:1; + uint32_t BUF13M:1; + uint32_t BUF12M:1; + uint32_t BUF11M:1; + uint32_t BUF10M:1; + uint32_t BUF09M:1; + uint32_t BUF08M:1; + uint32_t BUF07M:1; + uint32_t BUF06M:1; + uint32_t BUF05M:1; + uint32_t BUF04M:1; + uint32_t BUF03M:1; + uint32_t BUF02M:1; + uint32_t BUF01M:1; + uint32_t BUF00M:1; + } B; + } IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */ + + union { /* Interruput Flag Register */ + uint32_t R; + struct { + uint32_t BUF63I:1; + uint32_t BUF62I:1; + uint32_t BUF61I:1; + uint32_t BUF60I:1; + uint32_t BUF59I:1; + uint32_t BUF58I:1; + uint32_t BUF57I:1; + uint32_t BUF56I:1; + uint32_t BUF55I:1; + uint32_t BUF54I:1; + uint32_t BUF53I:1; + uint32_t BUF52I:1; + uint32_t BUF51I:1; + uint32_t BUF50I:1; + uint32_t BUF49I:1; + uint32_t BUF48I:1; + uint32_t BUF47I:1; + uint32_t BUF46I:1; + uint32_t BUF45I:1; + uint32_t BUF44I:1; + uint32_t BUF43I:1; + uint32_t BUF42I:1; + uint32_t BUF41I:1; + uint32_t BUF40I:1; + uint32_t BUF39I:1; + uint32_t BUF38I:1; + uint32_t BUF37I:1; + uint32_t BUF36I:1; + uint32_t BUF35I:1; + uint32_t BUF34I:1; + uint32_t BUF33I:1; + uint32_t BUF32I:1; + } B; + } IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */ + + union { /* Interruput Flag Register */ + uint32_t R; + struct { + uint32_t BUF31I:1; + uint32_t BUF30I:1; + uint32_t BUF29I:1; + uint32_t BUF28I:1; + uint32_t BUF27I:1; + uint32_t BUF26I:1; + uint32_t BUF25I:1; + uint32_t BUF24I:1; + uint32_t BUF23I:1; + uint32_t BUF22I:1; + uint32_t BUF21I:1; + uint32_t BUF20I:1; + uint32_t BUF19I:1; + uint32_t BUF18I:1; + uint32_t BUF17I:1; + uint32_t BUF16I:1; + uint32_t BUF15I:1; + uint32_t BUF14I:1; + uint32_t BUF13I:1; + uint32_t BUF12I:1; + uint32_t BUF11I:1; + uint32_t BUF10I:1; + uint32_t BUF09I:1; + uint32_t BUF08I:1; + uint32_t BUF07I:1; + uint32_t BUF06I:1; + uint32_t BUF05I:1; + uint32_t BUF04I:1; + uint32_t BUF03I:1; + uint32_t BUF02I:1; + uint32_t BUF01I:1; + uint32_t BUF00I:1; + } B; + } IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */ + + uint32_t FLEXCAN_reserved0034[19]; /* 0x0034-0x007F */ + + struct canbuf_t { + union { + uint32_t R; + struct { + uint32_t:4; + uint32_t CODE:4; + uint32_t:1; + uint32_t SRR:1; + uint32_t IDE:1; + uint32_t RTR:1; + uint32_t LENGTH:4; + uint32_t TIMESTAMP:16; + } B; + } CS; + + union { + uint32_t R; + struct { + uint32_t PRIO:3; + uint32_t STD_ID:11; + uint32_t EXT_ID:18; + } B; + } ID; + + union { + uint8_t B[8]; /* Data buffer in Bytes (8 bits) */ + uint16_t H[4]; /* Data buffer in Half-words (16 bits) */ + uint32_t W[2]; /* Data buffer in words (32 bits) */ + uint32_t R[2]; /* Data buffer in words (32 bits) */ + } DATA; + + } BUF[64]; + + int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */ + + union { /* RX Individual Mask Registers */ + uint32_t R; + struct { + uint32_t MI31:1; + uint32_t MI30:1; + uint32_t MI29:1; + uint32_t MI28:1; + uint32_t MI27:1; + uint32_t MI26:1; + uint32_t MI25:1; + uint32_t MI24:1; + uint32_t MI23:1; + uint32_t MI22:1; + uint32_t MI21:1; + uint32_t MI20:1; + uint32_t MI19:1; + uint32_t MI18:1; + uint32_t MI17:1; + uint32_t MI16:1; + uint32_t MI15:1; + uint32_t MI14:1; + uint32_t MI13:1; + uint32_t MI12:1; + uint32_t MI11:1; + uint32_t MI10:1; + uint32_t MI9:1; + uint32_t MI8:1; + uint32_t MI7:1; + uint32_t MI6:1; + uint32_t MI5:1; + uint32_t MI4:1; + uint32_t MI3:1; + uint32_t MI2:1; + uint32_t MI1:1; + uint32_t MI0:1; + } B; + } RXIMR[64]; + + int32_t FLEXCAN_reserved0980[3488]; /* 0x0980-0x3FFF */ + + }; + +/****************************************************************************/ +/* MODULE : FlexRay */ +/****************************************************************************/ + + typedef union uMVR { + uint16_t R; + struct { + uint16_t CHIVER:8; /* CHI Version Number */ + uint16_t PEVER:8; /* PE Version Number */ + } B; + } MVR_t; + + typedef union uMCR { + uint16_t R; + struct { + uint16_t MEN:1; /* module enable */ + uint16_t:1; + uint16_t SCMD:1; /* single channel mode */ + uint16_t CHB:1; /* channel B enable */ + uint16_t CHA:1; /* channel A enable */ + uint16_t SFFE:1; /* synchronization frame filter enable */ + uint16_t:5; + uint16_t CLKSEL:1; /* protocol engine clock source select */ + uint16_t PRESCALE:3; /* protocol engine clock prescaler */ + uint16_t:1; + } B; + } MCR_t; + + typedef union uSTBSCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t STBSSEL:7; /* strobe signal select */ + uint16_t:3; + uint16_t ENB:1; /* strobe signal enable */ + uint16_t:2; + uint16_t STBPSEL:2; /* strobe port select */ + } B; + } STBSCR_t; + typedef union uSTBPCR { + uint16_t R; + struct { + uint16_t:12; + uint16_t STB3EN:1; /* strobe port enable */ + uint16_t STB2EN:1; /* strobe port enable */ + uint16_t STB1EN:1; /* strobe port enable */ + uint16_t STB0EN:1; /* strobe port enable */ + } B; + } STBPCR_t; + + typedef union uMBDSR { + uint16_t R; + struct { + uint16_t:1; + uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */ + uint16_t:1; + uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */ + } B; + } MBDSR_t; + typedef union uMBSSUTR { + uint16_t R; + struct { + + uint16_t:1; + uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */ + uint16_t:1; + uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */ + } B; + } MBSSUTR_t; + + typedef union uPOCR { + uint16_t R; + uint8_t byte[2]; + struct { + uint16_t WME:1; /* write mode external correction command */ + uint16_t:3; + uint16_t EOC_AP:2; /* external offset correction application */ + uint16_t ERC_AP:2; /* external rate correction application */ + uint16_t BSY:1; /* command write busy / write mode command */ + uint16_t:3; + uint16_t POCCMD:4; /* protocol command */ + } B; + } POCR_t; +/* protocol commands */ + typedef union uGIFER { + uint16_t R; + struct { + uint16_t MIF:1; /* module interrupt flag */ + uint16_t PRIF:1; /* protocol interrupt flag */ + uint16_t CHIF:1; /* CHI interrupt flag */ + uint16_t WKUPIF:1; /* wakeup interrupt flag */ + uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */ + uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */ + uint16_t RBIF:1; /* receive message buffer interrupt flag */ + uint16_t TBIF:1; /* transmit buffer interrupt flag */ + uint16_t MIE:1; /* module interrupt enable */ + uint16_t PRIE:1; /* protocol interrupt enable */ + uint16_t CHIE:1; /* CHI interrupt enable */ + uint16_t WKUPIE:1; /* wakeup interrupt enable */ + uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */ + uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */ + uint16_t RBIE:1; /* receive message buffer interrupt enable */ + uint16_t TBIE:1; /* transmit buffer interrupt enable */ + } B; + } GIFER_t; + typedef union uPIFR0 { + uint16_t R; + struct { + uint16_t FATLIF:1; /* fatal protocol error interrupt flag */ + uint16_t INTLIF:1; /* internal protocol error interrupt flag */ + uint16_t ILCFIF:1; /* illegal protocol configuration flag */ + uint16_t CSAIF:1; /* cold start abort interrupt flag */ + uint16_t MRCIF:1; /* missing rate correctio interrupt flag */ + uint16_t MOCIF:1; /* missing offset correctio interrupt flag */ + uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */ + uint16_t MXSIF:1; /* max sync frames detected interrupt flag */ + uint16_t MTXIF:1; /* media access test symbol received flag */ + uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */ + uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */ + uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */ + uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */ + uint16_t TI2IF:1; /* timer 2 expired interrupt flag */ + uint16_t TI1IF:1; /* timer 1 expired interrupt flag */ + uint16_t CYSIF:1; /* cycle start interrupt flag */ + } B; + } PIFR0_t; + typedef union uPIFR1 { + uint16_t R; + struct { + uint16_t EMCIF:1; /* error mode changed interrupt flag */ + uint16_t IPCIF:1; /* illegal protocol command interrupt flag */ + uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */ + uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */ + uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */ + uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */ + uint16_t:2; + uint16_t EVTIF:1; /* even cycle table written interrupt flag */ + uint16_t ODTIF:1; /* odd cycle table written interrupt flag */ + uint16_t:4; + } B; + } PIFR1_t; + typedef union uPIER0 { + uint16_t R; + struct { + uint16_t FATLIE:1; /* fatal protocol error interrupt enable */ + uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */ + uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */ + uint16_t CSAIE:1; /* cold start abort interrupt enable */ + uint16_t MRCIE:1; /* missing rate correctio interrupt enable */ + uint16_t MOCIE:1; /* missing offset correctio interrupt enable */ + uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */ + uint16_t MXSIE:1; /* max sync frames detected interrupt enable */ + uint16_t MTXIE:1; /* media access test symbol received interrupt enable */ + uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */ + uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */ + uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */ + uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */ + uint16_t TI2IE:1; /* timer 2 expired interrupt enable */ + uint16_t TI1IE:1; /* timer 1 expired interrupt enable */ + uint16_t CYSIE:1; /* cycle start interrupt enable */ + } B; + } PIER0_t; + typedef union uPIER1 { + uint16_t R; + struct { + uint16_t EMCIE:1; /* error mode changed interrupt enable */ + uint16_t IPCIE:1; /* illegal protocol command interrupt enable */ + uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */ + uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */ + uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */ + uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */ + uint16_t:2; + uint16_t EVTIE:1; /* even cycle table written interrupt enable */ + uint16_t ODTIE:1; /* odd cycle table written interrupt enable */ + uint16_t:4; + } B; + } PIER1_t; + typedef union uCHIERFR { + uint16_t R; + struct { + uint16_t FRLBEF:1; /* flame lost channel B error flag */ + uint16_t FRLAEF:1; /* frame lost channel A error flag */ + uint16_t PCMIEF:1; /* command ignored error flag */ + uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */ + uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */ + uint16_t MSBEF:1; /* message buffer search error flag */ + uint16_t MBUEF:1; /* message buffer utilization error flag */ + uint16_t LCKEF:1; /* lock error flag */ + uint16_t DBLEF:1; /* double transmit message buffer lock error flag */ + uint16_t SBCFEF:1; /* system bus communication failure error flag */ + uint16_t FIDEF:1; /* frame ID error flag */ + uint16_t DPLEF:1; /* dynamic payload length error flag */ + uint16_t SPLEF:1; /* static payload length error flag */ + uint16_t NMLEF:1; /* network management length error flag */ + uint16_t NMFEF:1; /* network management frame error flag */ + uint16_t ILSAEF:1; /* illegal access error flag */ + } B; + } CHIERFR_t; + typedef union uMBIVEC { + uint16_t R; + struct { + + uint16_t:1; + uint16_t TBIVEC:7; /* transmit buffer interrupt vector */ + uint16_t:1; + uint16_t RBIVEC:7; /* receive buffer interrupt vector */ + } B; + } MBIVEC_t; + + typedef union uPSR0 { + uint16_t R; + struct { + uint16_t ERRMODE:2; /* error mode */ + uint16_t SLOTMODE:2; /* slot mode */ + uint16_t:1; + uint16_t PROTSTATE:3; /* protocol state */ + uint16_t SUBSTATE:4; /* protocol sub state */ + uint16_t:1; + uint16_t WAKEUPSTATUS:3; /* wakeup status */ + } B; + } PSR0_t; + +/* protocol states */ +/* protocol sub-states */ +/* wakeup status */ + typedef union uPSR1 { + uint16_t R; + struct { + uint16_t CSAA:1; /* cold start attempt abort flag */ + uint16_t SCP:1; /* cold start path */ + uint16_t:1; + uint16_t REMCSAT:5; /* remanining coldstart attempts */ + uint16_t CPN:1; /* cold start noise path */ + uint16_t HHR:1; /* host halt request pending */ + uint16_t FRZ:1; /* freeze occured */ + uint16_t APTAC:5; /* allow passive to active counter */ + } B; + } PSR1_t; + typedef union uPSR2 { + uint16_t R; + struct { + uint16_t NBVB:1; /* NIT boundary violation on channel B */ + uint16_t NSEB:1; /* NIT syntax error on channel B */ + uint16_t STCB:1; /* symbol window transmit conflict on channel B */ + uint16_t SBVB:1; /* symbol window boundary violation on channel B */ + uint16_t SSEB:1; /* symbol window syntax error on channel B */ + uint16_t MTB:1; /* media access test symbol MTS received on channel B */ + uint16_t NBVA:1; /* NIT boundary violation on channel A */ + uint16_t NSEA:1; /* NIT syntax error on channel A */ + uint16_t STCA:1; /* symbol window transmit conflict on channel A */ + uint16_t SBVA:1; /* symbol window boundary violation on channel A */ + uint16_t SSEA:1; /* symbol window syntax error on channel A */ + uint16_t MTA:1; /* media access test symbol MTS received on channel A */ + uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */ + } B; + } PSR2_t; + typedef union uPSR3 { + uint16_t R; + struct { + uint16_t:2; + uint16_t WUB:1; /* wakeup symbol received on channel B */ + uint16_t ABVB:1; /* aggregated boundary violation on channel B */ + uint16_t AACB:1; /* aggregated additional communication on channel B */ + uint16_t ACEB:1; /* aggregated content error on channel B */ + uint16_t ASEB:1; /* aggregated syntax error on channel B */ + uint16_t AVFB:1; /* aggregated valid frame on channel B */ + uint16_t:2; + uint16_t WUA:1; /* wakeup symbol received on channel A */ + uint16_t ABVA:1; /* aggregated boundary violation on channel A */ + uint16_t AACA:1; /* aggregated additional communication on channel A */ + uint16_t ACEA:1; /* aggregated content error on channel A */ + uint16_t ASEA:1; /* aggregated syntax error on channel A */ + uint16_t AVFA:1; /* aggregated valid frame on channel A */ + } B; + } PSR3_t; + typedef union uCIFRR { + uint16_t R; + struct { + uint16_t:8; + uint16_t MIFR:1; /* module interrupt flag */ + uint16_t PRIFR:1; /* protocol interrupt flag */ + uint16_t CHIFR:1; /* CHI interrupt flag */ + uint16_t WUPIFR:1; /* wakeup interrupt flag */ + uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */ + uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */ + uint16_t RBIFR:1; /* receive message buffer interrupt flag */ + uint16_t TBIFR:1; /* transmit buffer interrupt flag */ + } B; + } CIFRR_t; + typedef union uSFCNTR { + uint16_t R; + struct { + uint16_t SFEVB:4; /* sync frames channel B, even cycle */ + uint16_t SFEVA:4; /* sync frames channel A, even cycle */ + uint16_t SFODB:4; /* sync frames channel B, odd cycle */ + uint16_t SFODA:4; /* sync frames channel A, odd cycle */ + } B; + } SFCNTR_t; + + typedef union uSFTCCSR { + uint16_t R; + struct { + uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */ + uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */ + uint16_t CYCNUM:6; /* cycle number */ + uint16_t ELKS:1; /* even cycle tables lock status */ + uint16_t OLKS:1; /* odd cycle tables lock status */ + uint16_t EVAL:1; /* even cycle tables valid */ + uint16_t OVAL:1; /* odd cycle tables valid */ + uint16_t:1; + uint16_t OPT:1; /*one pair trigger */ + uint16_t SDVEN:1; /* sync frame deviation table enable */ + uint16_t SIDEN:1; /* sync frame ID table enable */ + } B; + } SFTCCSR_t; + typedef union uSFIDRFR { + uint16_t R; + struct { + uint16_t:6; + uint16_t SYNFRID:10; /* sync frame rejection ID */ + } B; + } SFIDRFR_t; + + typedef union uTICCR { + uint16_t R; + struct { + uint16_t:2; + uint16_t T2CFG:1; /* timer 2 configuration */ + uint16_t T2REP:1; /* timer 2 repetitive mode */ + uint16_t:1; + uint16_t T2SP:1; /* timer 2 stop */ + uint16_t T2TR:1; /* timer 2 trigger */ + uint16_t T2ST:1; /* timer 2 state */ + uint16_t:3; + uint16_t T1REP:1; /* timer 1 repetitive mode */ + uint16_t:1; + uint16_t T1SP:1; /* timer 1 stop */ + uint16_t T1TR:1; /* timer 1 trigger */ + uint16_t T1ST:1; /* timer 1 state */ + + } B; + } TICCR_t; + typedef union uTI1CYSR { + uint16_t R; + struct { + uint16_t:2; + uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */ + uint16_t:2; + uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */ + + } B; + } TI1CYSR_t; + + typedef union uSSSR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* static slot number */ + uint16_t:1; + uint16_t SLOTNUMBER:11; /* selector */ + } B; + } SSSR_t; + + typedef union uSSCCR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:1; + uint16_t CNTCFG:2; /* counter configuration */ + uint16_t MCY:1; /* multi cycle selection */ + uint16_t VFR:1; /* valid frame selection */ + uint16_t SYF:1; /* sync frame selection */ + uint16_t NUF:1; /* null frame selection */ + uint16_t SUF:1; /* startup frame selection */ + uint16_t STATUSMASK:4; /* slot status mask */ + } B; + } SSCCR_t; + typedef union uSSR { + uint16_t R; + struct { + uint16_t VFB:1; /* valid frame on channel B */ + uint16_t SYB:1; /* valid sync frame on channel B */ + uint16_t NFB:1; /* valid null frame on channel B */ + uint16_t SUB:1; /* valid startup frame on channel B */ + uint16_t SEB:1; /* syntax error on channel B */ + uint16_t CEB:1; /* content error on channel B */ + uint16_t BVB:1; /* boundary violation on channel B */ + uint16_t TCB:1; /* tx conflict on channel B */ + uint16_t VFA:1; /* valid frame on channel A */ + uint16_t SYA:1; /* valid sync frame on channel A */ + uint16_t NFA:1; /* valid null frame on channel A */ + uint16_t SUA:1; /* valid startup frame on channel A */ + uint16_t SEA:1; /* syntax error on channel A */ + uint16_t CEA:1; /* content error on channel A */ + uint16_t BVA:1; /* boundary violation on channel A */ + uint16_t TCA:1; /* tx conflict on channel A */ + } B; + } SSR_t; + typedef union uMTSCFR { + uint16_t R; + struct { + uint16_t MTE:1; /* media access test symbol transmission enable */ + uint16_t:1; + uint16_t CYCCNTMSK:6; /* cycle counter mask */ + uint16_t:2; + uint16_t CYCCNTVAL:6; /* cycle counter value */ + } B; + } MTSCFR_t; + typedef union uRSBIR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t:1; + uint16_t SEL:2; /* selector */ + uint16_t:4; + uint16_t RSBIDX:8; /* receive shadow buffer index */ + } B; + } RSBIR_t; + typedef union uRFDSR { + uint16_t R; + struct { + uint16_t FIFODEPTH:8; /* fifo depth */ + uint16_t:1; + uint16_t ENTRYSIZE:7; /* entry size */ + } B; + } RFDSR_t; + + typedef union uRFRFCFR { + uint16_t R; + struct { + uint16_t WMD:1; /* write mode */ + uint16_t IBD:1; /* interval boundary */ + uint16_t SEL:2; /* filter number */ + uint16_t:1; + uint16_t SID:11; /* slot ID */ + } B; + } RFRFCFR_t; + + typedef union uRFRFCTR { + uint16_t R; + struct { + uint16_t:4; + uint16_t F3MD:1; /* filter mode */ + uint16_t F2MD:1; /* filter mode */ + uint16_t F1MD:1; /* filter mode */ + uint16_t F0MD:1; /* filter mode */ + uint16_t:4; + uint16_t F3EN:1; /* filter enable */ + uint16_t F2EN:1; /* filter enable */ + uint16_t F1EN:1; /* filter enable */ + uint16_t F0EN:1; /* filter enable */ + } B; + } RFRFCTR_t; + typedef union uPCR0 { + uint16_t R; + struct { + uint16_t ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_LENGTH:10; + } B; + } PCR0_t; + + typedef union uPCR1 { + uint16_t R; + struct { + uint16_t:2; + uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; + } B; + } PCR1_t; + + typedef union uPCR2 { + uint16_t R; + struct { + uint16_t MINISLOT_AFTER_ACTION_POINT:6; + uint16_t NUMBER_OF_STATIC_SLOTS:10; + } B; + } PCR2_t; + + typedef union uPCR3 { + uint16_t R; + struct { + uint16_t WAKEUP_SYMBOL_RX_LOW:6; + uint16_t MINISLOT_ACTION_POINT_OFFSET:5; + uint16_t COLDSTART_ATTEMPTS:5; + } B; + } PCR3_t; + + typedef union uPCR4 { + uint16_t R; + struct { + uint16_t CAS_RX_LOW_MAX:7; + uint16_t WAKEUP_SYMBOL_RX_WINDOW:9; + } B; + } PCR4_t; + + typedef union uPCR5 { + uint16_t R; + struct { + uint16_t TSS_TRANSMITTER:4; + uint16_t WAKEUP_SYMBOL_TX_LOW:6; + uint16_t WAKEUP_SYMBOL_RX_IDLE:6; + } B; + } PCR5_t; + + typedef union uPCR6 { + uint16_t R; + struct { + uint16_t:1; + uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; + uint16_t MACRO_INITIAL_OFFSET_A:7; + } B; + } PCR6_t; + + typedef union uPCR7 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_B:9; + uint16_t MICRO_PER_MACRO_NOM_HALF:7; + } B; + } PCR7_t; + + typedef union uPCR8 { + uint16_t R; + struct { + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; + uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; + uint16_t WAKEUP_SYMBOL_TX_IDLE:8; + } B; + } PCR8_t; + + typedef union uPCR9 { + uint16_t R; + struct { + uint16_t MINISLOT_EXISTS:1; + uint16_t SYMBOL_WINDOW_EXISTS:1; + uint16_t OFFSET_CORRECTION_OUT:14; + } B; + } PCR9_t; + + typedef union uPCR10 { + uint16_t R; + struct { + uint16_t SINGLE_SLOT_ENABLED:1; + uint16_t WAKEUP_CHANNEL:1; + uint16_t MACRO_PER_CYCLE:14; + } B; + } PCR10_t; + + typedef union uPCR11 { + uint16_t R; + struct { + uint16_t KEY_SLOT_USED_FOR_STARTUP:1; + uint16_t KEY_SLOT_USED_FOR_SYNC:1; + uint16_t OFFSET_CORRECTION_START:14; + } B; + } PCR11_t; + + typedef union uPCR12 { + uint16_t R; + struct { + uint16_t ALLOW_PASSIVE_TO_ACTIVE:5; + uint16_t KEY_SLOT_HEADER_CRC:11; + } B; + } PCR12_t; + + typedef union uPCR13 { + uint16_t R; + struct { + uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; + uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; + } B; + } PCR13_t; + + typedef union uPCR14 { + uint16_t R; + struct { + uint16_t RATE_CORRECTION_OUT:11; + uint16_t LISTEN_TIMEOUT_H:5; + } B; + } PCR14_t; + + typedef union uPCR15 { + uint16_t R; + struct { + uint16_t LISTEN_TIMEOUT_L:16; + } B; + } PCR15_t; + + typedef union uPCR16 { + uint16_t R; + struct { + uint16_t MACRO_INITIAL_OFFSET_B:7; + uint16_t NOISE_LISTEN_TIMEOUT_H:9; + } B; + } PCR16_t; + + typedef union uPCR17 { + uint16_t R; + struct { + uint16_t NOISE_LISTEN_TIMEOUT_L:16; + } B; + } PCR17_t; + + typedef union uPCR18 { + uint16_t R; + struct { + uint16_t WAKEUP_PATTERN:6; + uint16_t KEY_SLOT_ID:10; + } B; + } PCR18_t; + + typedef union uPCR19 { + uint16_t R; + struct { + uint16_t DECODING_CORRECTION_A:9; + uint16_t PAYLOAD_LENGTH_STATIC:7; + } B; + } PCR19_t; + + typedef union uPCR20 { + uint16_t R; + struct { + uint16_t MICRO_INITIAL_OFFSET_B:8; + uint16_t MICRO_INITIAL_OFFSET_A:8; + } B; + } PCR20_t; + + typedef union uPCR21 { + uint16_t R; + struct { + uint16_t EXTERN_RATE_CORRECTION:3; + uint16_t LATEST_TX:13; + } B; + } PCR21_t; + + typedef union uPCR22 { + uint16_t R; + struct { + uint16_t:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; + uint16_t MICRO_PER_CYCLE_H:4; + } B; + } PCR22_t; + + typedef union uPCR23 { + uint16_t R; + struct { + uint16_t micro_per_cycle_l:16; + } B; + } PCR23_t; + + typedef union uPCR24 { + uint16_t R; + struct { + uint16_t CLUSTER_DRIFT_DAMPING:5; + uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; + uint16_t MICRO_PER_CYCLE_MIN_H:4; + } B; + } PCR24_t; + + typedef union uPCR25 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MIN_L:16; + } B; + } PCR25_t; + + typedef union uPCR26 { + uint16_t R; + struct { + uint16_t ALLOW_HALT_DUE_TO_CLOCK:1; + uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; + uint16_t MICRO_PER_CYCLE_MAX_H:4; + } B; + } PCR26_t; + + typedef union uPCR27 { + uint16_t R; + struct { + uint16_t MICRO_PER_CYCLE_MAX_L:16; + } B; + } PCR27_t; + + typedef union uPCR28 { + uint16_t R; + struct { + uint16_t DYNAMIC_SLOT_IDLE_PHASE:2; + uint16_t MACRO_AFTER_OFFSET_CORRECTION:14; + } B; + } PCR28_t; + + typedef union uPCR29 { + uint16_t R; + struct { + uint16_t EXTERN_OFFSET_CORRECTION:3; + uint16_t MINISLOTS_MAX:13; + } B; + } PCR29_t; + + typedef union uPCR30 { + uint16_t R; + struct { + uint16_t:12; + uint16_t SYNC_NODE_MAX:4; + } B; + } PCR30_t; + + typedef struct uMSG_BUFF_CCS { + union { + uint16_t R; + struct { + uint16_t:1; + uint16_t MCM:1; /* message buffer commit mode */ + uint16_t MBT:1; /* message buffer type */ + uint16_t MTD:1; /* message buffer direction */ + uint16_t CMT:1; /* commit for transmission */ + uint16_t EDT:1; /* enable / disable trigger */ + uint16_t LCKT:1; /* lock request trigger */ + uint16_t MBIE:1; /* message buffer interrupt enable */ + uint16_t:3; + uint16_t DUP:1; /* data updated */ + uint16_t DVAL:1; /* data valid */ + uint16_t EDS:1; /* lock status */ + uint16_t LCKS:1; /* enable / disable status */ + uint16_t MBIF:1; /* message buffer interrupt flag */ + } B; + } MBCCSR; + union { + uint16_t R; + struct { + uint16_t MTM:1; /* message buffer transmission mode */ + uint16_t CHNLA:1; /* channel assignement */ + uint16_t CHNLB:1; /* channel assignement */ + uint16_t CCFE:1; /* cycle counter filter enable */ + uint16_t CCFMSK:6; /* cycle counter filter mask */ + uint16_t CCFVAL:6; /* cycle counter filter value */ + } B; + } MBCCFR; + union { + uint16_t R; + struct { + uint16_t:5; + uint16_t FID:11; /* frame ID */ + } B; + } MBFIDR; + union { + uint16_t R; + struct { + uint16_t:8; + uint16_t MBIDX:8; /* message buffer index */ + } B; + } MBIDXR; + } MSG_BUFF_CCS_t; + typedef union uSYSBADHR { + uint16_t R; + } SYSBADHR_t; + typedef union uSYSBADLR { + uint16_t R; + } SYSBADLR_t; + typedef union uPDAR { + uint16_t R; + } PDAR_t; + typedef union uCASERCR { + uint16_t R; + } CASERCR_t; + typedef union uCBSERCR { + uint16_t R; + } CBSERCR_t; + typedef union uCYCTR { + uint16_t R; + } CYCTR_t; + typedef union uMTCTR { + uint16_t R; + } MTCTR_t; + typedef union uSLTCTAR { + uint16_t R; + } SLTCTAR_t; + typedef union uSLTCTBR { + uint16_t R; + } SLTCTBR_t; + typedef union uRTCORVR { + uint16_t R; + } RTCORVR_t; + typedef union uOFCORVR { + uint16_t R; + } OFCORVR_t; + typedef union uSFTOR { + uint16_t R; + } SFTOR_t; + typedef union uSFIDAFVR { + uint16_t R; + } SFIDAFVR_t; + typedef union uSFIDAFMR { + uint16_t R; + } SFIDAFMR_t; + typedef union uNMVR { + uint16_t R; + } NMVR_t; + typedef union uNMVLR { + uint16_t R; + } NMVLR_t; + typedef union uT1MTOR { + uint16_t R; + } T1MTOR_t; + typedef union uTI2CR0 { + uint16_t R; + } TI2CR0_t; + typedef union uTI2CR1 { + uint16_t R; + } TI2CR1_t; + typedef union uSSCR { + uint16_t R; + } SSCR_t; + typedef union uRFSR { + uint16_t R; + } RFSR_t; + typedef union uRFSIR { + uint16_t R; + } RFSIR_t; + typedef union uRFARIR { + uint16_t R; + } RFARIR_t; + typedef union uRFBRIR { + uint16_t R; + } RFBRIR_t; + typedef union uRFMIDAFVR { + uint16_t R; + } RFMIDAFVR_t; + typedef union uRFMIAFMR { + uint16_t R; + } RFMIAFMR_t; + typedef union uRFFIDRFVR { + uint16_t R; + } RFFIDRFVR_t; + typedef union uRFFIDRFMR { + uint16_t R; + } RFFIDRFMR_t; + typedef union uLDTXSLAR { + uint16_t R; + } LDTXSLAR_t; + typedef union uLDTXSLBR { + uint16_t R; + } LDTXSLBR_t; + + typedef struct FR_tag { + volatile MVR_t MVR; /*module version register *//*0 */ + volatile MCR_t MCR; /*module configuration register *//*2 */ + volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */ + volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */ + volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */ + volatile STBPCR_t STBPCR; /*strobe port control register *//*A */ + volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */ + volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */ + uint16_t reserved3a[1]; /*10 */ + volatile PDAR_t PDAR; /*PE data register *//*12 */ + volatile POCR_t POCR; /*Protocol operation control register *//*14 */ + volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */ + volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */ + volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */ + volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */ + volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */ + volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */ + volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */ + volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */ + volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */ + volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */ + volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */ + volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */ + volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */ + volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */ + volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */ + volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */ + volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */ + volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */ + volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */ + volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */ + uint16_t reserved3[1]; /*3E */ + volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */ + volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */ + volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */ + volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */ + volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */ + volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */ + volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */ + volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */ + volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */ + volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */ + volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */ + volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */ + volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */ + volatile SSSR_t SSSR; /*slot status selection register *//*64 */ + volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */ + volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */ + volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */ + volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */ + volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */ + volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */ + volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */ + volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */ + volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */ + volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */ + volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */ + volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */ + volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */ + volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */ + volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */ + volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */ + volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */ + volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */ + volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */ + volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */ + volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */ + volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */ + volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */ + volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */ + volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */ + volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */ + volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */ + volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */ + volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */ + volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */ + volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */ + volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */ + volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */ + volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */ + volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */ + volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */ + volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */ + volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */ + volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */ + volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */ + volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */ + volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */ + volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */ + volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */ + volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */ + volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */ + volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */ + volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */ + volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */ + volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */ + uint16_t reserved2[17]; + volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */ + } FR_tag_t; + + typedef union uF_HEADER /* frame header */ + { + struct { + uint16_t:5; + uint16_t HDCRC:11; /* Header CRC */ + uint16_t:2; + uint16_t CYCCNT:6; /* Cycle Count */ + uint16_t:1; + uint16_t PLDLEN:7; /* Payload Length */ + uint16_t:1; + uint16_t PPI:1; /* Payload Preamble Indicator */ + uint16_t NUF:1; /* Null Frame Indicator */ + uint16_t SYF:1; /* Sync Frame Indicator */ + uint16_t SUF:1; /* Startup Frame Indicator */ + uint16_t FID:11; /* Frame ID */ + } B; + uint16_t WORDS[3]; + } F_HEADER_t; + typedef union uS_STSTUS /* slot status */ + { + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t CH:1; /* Channel */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t:1; + } RX; + struct { + uint16_t VFB:1; /* Valid Frame on channel B */ + uint16_t SYB:1; /* Sync Frame Indicator channel B */ + uint16_t NFB:1; /* Null Frame Indicator channel B */ + uint16_t SUB:1; /* Startup Frame Indicator channel B */ + uint16_t SEB:1; /* Syntax Error on channel B */ + uint16_t CEB:1; /* Content Error on channel B */ + uint16_t BVB:1; /* Boundary Violation on channel B */ + uint16_t TCB:1; /* Tx Conflict on channel B */ + uint16_t VFA:1; /* Valid Frame on channel A */ + uint16_t SYA:1; /* Sync Frame Indicator channel A */ + uint16_t NFA:1; /* Null Frame Indicator channel A */ + uint16_t SUA:1; /* Startup Frame Indicator channel A */ + uint16_t SEA:1; /* Syntax Error on channel A */ + uint16_t CEA:1; /* Content Error on channel A */ + uint16_t BVA:1; /* Boundary Violation on channel A */ + uint16_t TCA:1; /* Tx Conflict on channel A */ + } TX; + uint16_t R; + } S_STATUS_t; + + typedef struct uMB_HEADER /* message buffer header */ + { + F_HEADER_t FRAME_HEADER; + uint16_t DATA_OFFSET; + S_STATUS_t SLOT_STATUS; + } MB_HEADER_t; + +/* Define memories */ + +#define SRAM_START 0x40000000 +#define SRAM_SIZE 0x40000 +#define SRAM_END 0x4003FFFF + +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x400000 +#define FLASH_END 0x003FFFFF + +/* Define instances of modules */ +#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000) +#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) +#define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000) +#define FLASH FLASH_A +#define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000) +#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) +#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) + +#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_END 0xC3FC8FFC +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) + +#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) + +#define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000) +#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) +#define MPU (*( volatile struct MPU_tag *) 0xFFF10000) +#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) +#define STM (*( volatile struct STM_tag *) 0xFFF3C000) +#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA_A (*( volatile struct EDMA_tag *) 0xFFF44000) +#define EDMA EDMA_A +#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) +#define EDMA_B (*( volatile struct EDMA_tag *) 0xFFF54000) + +#define EQADC_A (*( volatile struct EQADC_tag *) 0xFFF80000) +#define EQADC EQADC_A +#define EQADC_B (*( volatile struct EQADC_tag *) 0xFFF84000) + +#define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000) +#define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF88800) +#define DECFIL_C (*( volatile struct DECFIL_tag *) 0xFFF89000) +#define DECFIL_D (*( volatile struct DECFIL_tag *) 0xFFF89800) +#define DECFIL_E (*( volatile struct DECFIL_tag *) 0xFFF8A000) +#define DECFIL_F (*( volatile struct DECFIL_tag *) 0xFFF8A800) +#define DECFIL_G (*( volatile struct DECFIL_tag *) 0xFFF8B000) +#define DECFIL_H (*( volatile struct DECFIL_tag *) 0xFFF8B800) + +#define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000) +#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) +#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000) + +#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) +#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000) +#define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFBC000) + +#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000) +#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) +#define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000) + +#define FR (*( volatile struct FR_tag *) 0xFFFE0000) +#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) + +#ifdef __MWERKS__ +#pragma pop +#endif + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ +#endif /* ifdef _MPC5674_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ diff --git a/bsps/powerpc/include/mpc55xx/mpc55xx.h b/bsps/powerpc/include/mpc55xx/mpc55xx.h new file mode 100644 index 0000000000..634be30e18 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/mpc55xx.h @@ -0,0 +1,155 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Documentation for this file + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/** + * @defgroup mpc55xx BSP for MPC55xx boards + */ + +/** + * @defgroup mpc55xx_config Configuration files + * + * @ingroup mpc55xx + * + * Makefiles, configure scripts etc. + */ + +/** + * @page mpc55xx_ext_doc External Documentation + * + * @section mpc55xx_ext_doc_mpc5567rm_1 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 1 of 2) + * @section mpc55xx_ext_doc_mpc5567rm_2 MPC5567 Microcontroller Reference Manual (Rev. 1, January 2007, Volume 2 of 2) + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_H +#define LIBCPU_POWERPC_MPC55XX_H + +#include <mpc55xx/regs.h> +#include <mpc55xx/regs-mmu.h> + +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes); +int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes, + uint32_t opmask, uint32_t *p_fail_addr); +int mpc55xx_flash_size(uint32_t *p_size); +int mpc55xx_flash_writable(void); +uint32_t mpc55xx_flash_address(void); +void mpc55xx_flash_set_read_only(void); +void mpc55xx_flash_set_read_write(void); + +int mpc55xx_physical_address(const void *addr, uint32_t *p_result); +int mpc55xx_mapped_address(const void *addr, uint32_t *p_result); + +/* Bits for opmask. */ +#define MPC55XX_FLASH_BLANK_CHECK 0x01 +#define MPC55XX_FLASH_UNLOCK 0x02 +#define MPC55XX_FLASH_ERASE 0x04 +#define MPC55XX_FLASH_PROGRAM 0x08 +#define MPC55XX_FLASH_VERIFY 0x10 + +/* Error returns. CONFIG or SIZE might mean you just + * need to check for new configuration bits. + * SIZE and RANGE mean you are outside of a known flash region. + * ERASE means the erase failed, + * PROGRAM means the program failed, + * BLANK means it wasn't blank and BLANK_CHECK was specified, + * VERIFY means VERIFY was set and it didn't match the source, + * and LOCK means either the locking failed or you needed to + * specify MPC55XX_FLASH_UNLOCK and didn't. + */ +#define MPC55XX_FLASH_CONFIG_ERR (-1) +#define MPC55XX_FLASH_SIZE_ERR (-2) +#define MPC55XX_FLASH_RANGE_ERR (-3) +#define MPC55XX_FLASH_ERASE_ERR (-4) +#define MPC55XX_FLASH_PROGRAM_ERR (-5) +#define MPC55XX_FLASH_NOT_BLANK_ERR (-6) +#define MPC55XX_FLASH_VERIFY_ERR (-7) +#define MPC55XX_FLASH_LOCK_ERR (-8) + +#define MPC55XX_CACHE_ALIGNED_MASK ((uintptr_t) 0x1f) + +#define MPC55XX_CACHE_LINE_SIZE 32 + +/** + * @brief Returns true if the buffer starting at @a s of size @a n is cache aligned. + */ +static inline int mpc55xx_is_cache_aligned( const void *s, size_t n) +{ + return !(((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) || (n & MPC55XX_CACHE_ALIGNED_MASK)); +} + +static inline uintptr_t mpc55xx_cache_aligned_start( const void *s) +{ + return ((uintptr_t) s & MPC55XX_CACHE_ALIGNED_MASK) ? (((uintptr_t) s & ~MPC55XX_CACHE_ALIGNED_MASK) + MPC55XX_CACHE_LINE_SIZE) : (uintptr_t)s; +} + +static inline size_t mpc55xx_non_cache_aligned_size( const void *s) +{ + return (uintptr_t) mpc55xx_cache_aligned_start( s) - (uintptr_t) s; +} + +static inline size_t mpc55xx_cache_aligned_size( const void *s, size_t n) +{ + return (n - mpc55xx_non_cache_aligned_size( s)) & ~MPC55XX_CACHE_ALIGNED_MASK; +} + +/** + * @brief Returns the number of leading zeros. + */ +static inline uint32_t mpc55xx_count_leading_zeros( uint32_t value) +{ + uint32_t count; + __asm__ ( + "cntlzw %0, %1;" + : "=r" (count) + : "r" (value) + ); + return count; +} + +static inline void mpc55xx_wait_for_interrupt(void) +{ + #ifdef MPC55XX_HAS_WAIT_INSTRUCTION + __asm__ volatile ("wait"); + #else + __asm__ volatile (""); + #endif +} + +static inline void mpc55xx_mmu_apply_config(const struct MMU_tag *config) +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, config->MAS0.R); + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, config->MAS1.R); + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS2, config->MAS2.R); + PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS3, config->MAS3.R); + __asm__ volatile ("tlbwe"); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_H */ diff --git a/bsps/powerpc/include/mpc55xx/reg-defs.h b/bsps/powerpc/include/mpc55xx/reg-defs.h new file mode 100644 index 0000000000..2d66f6a8d0 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/reg-defs.h @@ -0,0 +1,100 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Register definitions. + */ + +/* + * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H +#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H + +#include <bspopts.h> + +#if MPC55XX_CHIP_FAMILY == 551 + #define FLASH_BIUCR 0xFFFF801C +#else + #define FLASH_BIUCR 0xC3F8801C +#endif + +/* + * Definitions for FLASH_BIUCR (Flash BIU Control Register) + */ + +/* Fields for Flash Bus Interface Control */ +/* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */ + +/* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */ +#define FLASH_BUICR_EBI_PREFTCH 0x00080000 + +/* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */ +#define FLASH_BUICR_EDMA_PREFTCH 0x00040000 + +/* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */ +#define FLASH_BUICR_NEX_PREFTCH 0x00020000 + +/* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */ +#define FLASH_BUICR_CPU_PREFTCH 0x00010000 + +/* Fields for APC (access pipelining control bits [16:18]) */ +#define FLASH_BUICR_APC_0 0x00000000 +#define FLASH_BUICR_APC_1 0x00002000 +#define FLASH_BUICR_APC_2 0x00004000 +#define FLASH_BUICR_APC_3 0x00006000 +#define FLASH_BUICR_APC_4 0x00008000 +#define FLASH_BUICR_APC_5 0x0000A000 +#define FLASH_BUICR_APC_6 0x0000C000 +#define FLASH_BUICR_APC_NO 0x0000E000 + +/* Fields for WWSC (write wait state control bits [19:20]) */ +#define FLASH_BUICR_WWSC_1 0x00000800 +#define FLASH_BUICR_WWSC_2 0x00001000 +#define FLASH_BUICR_WWSC_3 0x00001800 + +/* Fields for RWSC (read wait state control bits [21:23]) */ +#define FLASH_BUICR_RWSC_0 0x00000000 +#define FLASH_BUICR_RWSC_1 0x00000100 +#define FLASH_BUICR_RWSC_2 0x00000200 +#define FLASH_BUICR_RWSC_3 0x00000300 +#define FLASH_BUICR_RWSC_4 0x00000400 +#define FLASH_BUICR_RWSC_5 0x00000500 +#define FLASH_BUICR_RWSC_6 0x00000600 +#define FLASH_BUICR_RWSC_7 0x00000700 + +/* Fields for DPFEN (data prefetch enable bits [24:25]) */ +#define FLASH_BUICR_DPFEN_0 0x00000000 +#define FLASH_BUICR_DPFEN_1 0x00000040 +#define FLASH_BUICR_DPFEN_3 0x000000C0 + +/* Fields for IPFEN (instruction prefetch enable bits [26:27]) */ +#define FLASH_BUICR_IPFEN_0 0x00000000 +#define FLASH_BUICR_IPFEN_1 0x00000010 +#define FLASH_BUICR_IPFEN_3 0x00000030 + +/* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */ +#define FLASH_BUICR_PFLIM_0 0x00000000 +#define FLASH_BUICR_PFLIM_1 0x00000002 +#define FLASH_BUICR_PFLIM_2 0x00000004 +#define FLASH_BUICR_PFLIM_3 0x00000006 +#define FLASH_BUICR_PFLIM_4 0x00000008 +#define FLASH_BUICR_PFLIM_5 0x0000000A +#define FLASH_BUICR_PFLIM_6 0x0000000C + +/* Fields for BFEN (enable line read buffer hits bit [31]) */ +#define FLASH_BUICR_BFEN 0x00000001 + +#endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */ diff --git a/bsps/powerpc/include/mpc55xx/regs-edma.h b/bsps/powerpc/include/mpc55xx/regs-edma.h new file mode 100644 index 0000000000..804730ccd8 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/regs-edma.h @@ -0,0 +1,710 @@ +/** + * @file + * + * @ingroup mpc55xx + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + +#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H +#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H + +#include <stdint.h> + +#include <bspopts.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/* MODULE : eDMA */ +/****************************************************************************/ + struct EDMA_tag { + union EDMA_CR_tag { + uint32_t R; + struct { +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint32_t:14; + uint32_t CX:1; + uint32_t ECX:1; +#else + uint32_t:16; +#endif + uint32_t GRP3PRI:2; + uint32_t GRP2PRI:2; + uint32_t GRP1PRI:2; + uint32_t GRP0PRI:2; +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint32_t EMLM:1; + uint32_t CLM:1; + uint32_t HALT:1; + uint32_t HOE:1; +#else + uint32_t:4; +#endif + uint32_t ERGA:1; + uint32_t ERCA:1; + uint32_t EDBG:1; + uint32_t EBW:1; + } B; + } CR; /* Control Register */ + + union { + uint32_t R; + struct { + uint32_t VLD:1; +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint32_t:14; + uint32_t ECX:1; +#else + uint32_t:15; +#endif + uint32_t GPE:1; + uint32_t CPE:1; + uint32_t ERRCHN:6; + uint32_t SAE:1; + uint32_t SOE:1; + uint32_t DAE:1; + uint32_t DOE:1; + uint32_t NCE:1; + uint32_t SGE:1; + uint32_t SBE:1; + uint32_t DBE:1; + } B; + } ESR; /* Error Status Register */ + + union { + uint32_t R; + struct { + uint32_t ERQ63:1; + uint32_t ERQ62:1; + uint32_t ERQ61:1; + uint32_t ERQ60:1; + uint32_t ERQ59:1; + uint32_t ERQ58:1; + uint32_t ERQ57:1; + uint32_t ERQ56:1; + uint32_t ERQ55:1; + uint32_t ERQ54:1; + uint32_t ERQ53:1; + uint32_t ERQ52:1; + uint32_t ERQ51:1; + uint32_t ERQ50:1; + uint32_t ERQ49:1; + uint32_t ERQ48:1; + uint32_t ERQ47:1; + uint32_t ERQ46:1; + uint32_t ERQ45:1; + uint32_t ERQ44:1; + uint32_t ERQ43:1; + uint32_t ERQ42:1; + uint32_t ERQ41:1; + uint32_t ERQ40:1; + uint32_t ERQ39:1; + uint32_t ERQ38:1; + uint32_t ERQ37:1; + uint32_t ERQ36:1; + uint32_t ERQ35:1; + uint32_t ERQ34:1; + uint32_t ERQ33:1; + uint32_t ERQ32:1; + } B; + } ERQRH; /* DMA Enable Request Register High */ + + union { + uint32_t R; + struct { + uint32_t ERQ31:1; + uint32_t ERQ30:1; + uint32_t ERQ29:1; + uint32_t ERQ28:1; + uint32_t ERQ27:1; + uint32_t ERQ26:1; + uint32_t ERQ25:1; + uint32_t ERQ24:1; + uint32_t ERQ23:1; + uint32_t ERQ22:1; + uint32_t ERQ21:1; + uint32_t ERQ20:1; + uint32_t ERQ19:1; + uint32_t ERQ18:1; + uint32_t ERQ17:1; + uint32_t ERQ16:1; + uint32_t ERQ15:1; + uint32_t ERQ14:1; + uint32_t ERQ13:1; + uint32_t ERQ12:1; + uint32_t ERQ11:1; + uint32_t ERQ10:1; + uint32_t ERQ09:1; + uint32_t ERQ08:1; + uint32_t ERQ07:1; + uint32_t ERQ06:1; + uint32_t ERQ05:1; + uint32_t ERQ04:1; + uint32_t ERQ03:1; + uint32_t ERQ02:1; + uint32_t ERQ01:1; + uint32_t ERQ00:1; + } B; + } ERQRL; /* DMA Enable Request Register Low */ + + union { + uint32_t R; + struct { + uint32_t EEI63:1; + uint32_t EEI62:1; + uint32_t EEI61:1; + uint32_t EEI60:1; + uint32_t EEI59:1; + uint32_t EEI58:1; + uint32_t EEI57:1; + uint32_t EEI56:1; + uint32_t EEI55:1; + uint32_t EEI54:1; + uint32_t EEI53:1; + uint32_t EEI52:1; + uint32_t EEI51:1; + uint32_t EEI50:1; + uint32_t EEI49:1; + uint32_t EEI48:1; + uint32_t EEI47:1; + uint32_t EEI46:1; + uint32_t EEI45:1; + uint32_t EEI44:1; + uint32_t EEI43:1; + uint32_t EEI42:1; + uint32_t EEI41:1; + uint32_t EEI40:1; + uint32_t EEI39:1; + uint32_t EEI38:1; + uint32_t EEI37:1; + uint32_t EEI36:1; + uint32_t EEI35:1; + uint32_t EEI34:1; + uint32_t EEI33:1; + uint32_t EEI32:1; + } B; + } EEIRH; /* DMA Enable Error Interrupt Register High */ + + union { + uint32_t R; + struct { + uint32_t EEI31:1; + uint32_t EEI30:1; + uint32_t EEI29:1; + uint32_t EEI28:1; + uint32_t EEI27:1; + uint32_t EEI26:1; + uint32_t EEI25:1; + uint32_t EEI24:1; + uint32_t EEI23:1; + uint32_t EEI22:1; + uint32_t EEI21:1; + uint32_t EEI20:1; + uint32_t EEI19:1; + uint32_t EEI18:1; + uint32_t EEI17:1; + uint32_t EEI16:1; + uint32_t EEI15:1; + uint32_t EEI14:1; + uint32_t EEI13:1; + uint32_t EEI12:1; + uint32_t EEI11:1; + uint32_t EEI10:1; + uint32_t EEI09:1; + uint32_t EEI08:1; + uint32_t EEI07:1; + uint32_t EEI06:1; + uint32_t EEI05:1; + uint32_t EEI04:1; + uint32_t EEI03:1; + uint32_t EEI02:1; + uint32_t EEI01:1; + uint32_t EEI00:1; + } B; + } EEIRL; /* DMA Enable Error Interrupt Register Low */ + + union { /* DMA Set Enable Request Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t SERQ:7; + } B; + } SERQR; + + union { /* DMA Clear Enable Request Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CERQ:7; + } B; + } CERQR; + + union { /* DMA Set Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t SEEI:7; + } B; + } SEEIR; + + union { /* DMA Clear Enable Error Interrupt Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CEEI:7; + } B; + } CEEIR; + + union { /* DMA Clear Interrupt Request Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CINT:7; + } B; + } CIRQR; + + union { /* DMA Clear error Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CERR:7; + } B; + } CER; + + union { /* Set Start Bit Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t SSB:7; + } B; + } SSBR; + + union { /* Clear Done Status Bit Register */ + uint8_t R; + struct { + uint8_t NOP:1; + uint8_t CDSB:7; + } B; + } CDSBR; + + union { + uint32_t R; + struct { + uint32_t INT63:1; + uint32_t INT62:1; + uint32_t INT61:1; + uint32_t INT60:1; + uint32_t INT59:1; + uint32_t INT58:1; + uint32_t INT57:1; + uint32_t INT56:1; + uint32_t INT55:1; + uint32_t INT54:1; + uint32_t INT53:1; + uint32_t INT52:1; + uint32_t INT51:1; + uint32_t INT50:1; + uint32_t INT49:1; + uint32_t INT48:1; + uint32_t INT47:1; + uint32_t INT46:1; + uint32_t INT45:1; + uint32_t INT44:1; + uint32_t INT43:1; + uint32_t INT42:1; + uint32_t INT41:1; + uint32_t INT40:1; + uint32_t INT39:1; + uint32_t INT38:1; + uint32_t INT37:1; + uint32_t INT36:1; + uint32_t INT35:1; + uint32_t INT34:1; + uint32_t INT33:1; + uint32_t INT32:1; + } B; + } IRQRH; /* DMA Interrupt Request High */ + + union { + uint32_t R; + struct { + uint32_t INT31:1; + uint32_t INT30:1; + uint32_t INT29:1; + uint32_t INT28:1; + uint32_t INT27:1; + uint32_t INT26:1; + uint32_t INT25:1; + uint32_t INT24:1; + uint32_t INT23:1; + uint32_t INT22:1; + uint32_t INT21:1; + uint32_t INT20:1; + uint32_t INT19:1; + uint32_t INT18:1; + uint32_t INT17:1; + uint32_t INT16:1; + uint32_t INT15:1; + uint32_t INT14:1; + uint32_t INT13:1; + uint32_t INT12:1; + uint32_t INT11:1; + uint32_t INT10:1; + uint32_t INT09:1; + uint32_t INT08:1; + uint32_t INT07:1; + uint32_t INT06:1; + uint32_t INT05:1; + uint32_t INT04:1; + uint32_t INT03:1; + uint32_t INT02:1; + uint32_t INT01:1; + uint32_t INT00:1; + } B; + } IRQRL; /* DMA Interrupt Request Low */ + + union { + uint32_t R; + struct { + uint32_t ERR63:1; + uint32_t ERR62:1; + uint32_t ERR61:1; + uint32_t ERR60:1; + uint32_t ERR59:1; + uint32_t ERR58:1; + uint32_t ERR57:1; + uint32_t ERR56:1; + uint32_t ERR55:1; + uint32_t ERR54:1; + uint32_t ERR53:1; + uint32_t ERR52:1; + uint32_t ERR51:1; + uint32_t ERR50:1; + uint32_t ERR49:1; + uint32_t ERR48:1; + uint32_t ERR47:1; + uint32_t ERR46:1; + uint32_t ERR45:1; + uint32_t ERR44:1; + uint32_t ERR43:1; + uint32_t ERR42:1; + uint32_t ERR41:1; + uint32_t ERR40:1; + uint32_t ERR39:1; + uint32_t ERR38:1; + uint32_t ERR37:1; + uint32_t ERR36:1; + uint32_t ERR35:1; + uint32_t ERR34:1; + uint32_t ERR33:1; + uint32_t ERR32:1; + } B; + } ERH; /* DMA Error High */ + + union { + uint32_t R; + struct { + uint32_t ERR31:1; + uint32_t ERR30:1; + uint32_t ERR29:1; + uint32_t ERR28:1; + uint32_t ERR27:1; + uint32_t ERR26:1; + uint32_t ERR25:1; + uint32_t ERR24:1; + uint32_t ERR23:1; + uint32_t ERR22:1; + uint32_t ERR21:1; + uint32_t ERR20:1; + uint32_t ERR19:1; + uint32_t ERR18:1; + uint32_t ERR17:1; + uint32_t ERR16:1; + uint32_t ERR15:1; + uint32_t ERR14:1; + uint32_t ERR13:1; + uint32_t ERR12:1; + uint32_t ERR11:1; + uint32_t ERR10:1; + uint32_t ERR09:1; + uint32_t ERR08:1; + uint32_t ERR07:1; + uint32_t ERR06:1; + uint32_t ERR05:1; + uint32_t ERR04:1; + uint32_t ERR03:1; + uint32_t ERR02:1; + uint32_t ERR01:1; + uint32_t ERR00:1; + } B; + } ERL; /* DMA Error Low */ + +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + union { /* hardware request status high */ + uint32_t R; + struct { + uint32_t HRS63:1; + uint32_t HRS62:1; + uint32_t HRS61:1; + uint32_t HRS60:1; + uint32_t HRS59:1; + uint32_t HRS58:1; + uint32_t HRS57:1; + uint32_t HRS56:1; + uint32_t HRS55:1; + uint32_t HRS54:1; + uint32_t HRS53:1; + uint32_t HRS52:1; + uint32_t HRS51:1; + uint32_t HRS50:1; + uint32_t HRS49:1; + uint32_t HRS48:1; + uint32_t HRS47:1; + uint32_t HRS46:1; + uint32_t HRS45:1; + uint32_t HRS44:1; + uint32_t HRS43:1; + uint32_t HRS42:1; + uint32_t HRS41:1; + uint32_t HRS40:1; + uint32_t HRS39:1; + uint32_t HRS38:1; + uint32_t HRS37:1; + uint32_t HRS36:1; + uint32_t HRS35:1; + uint32_t HRS34:1; + uint32_t HRS33:1; + uint32_t HRS32:1; + } B; + } HRSH; + + union { /* hardware request status low */ + uint32_t R; + struct { + uint32_t HRS31:1; + uint32_t HRS30:1; + uint32_t HRS29:1; + uint32_t HRS28:1; + uint32_t HRS27:1; + uint32_t HRS26:1; + uint32_t HRS25:1; + uint32_t HRS24:1; + uint32_t HRS23:1; + uint32_t HRS22:1; + uint32_t HRS21:1; + uint32_t HRS20:1; + uint32_t HRS19:1; + uint32_t HRS18:1; + uint32_t HRS17:1; + uint32_t HRS16:1; + uint32_t HRS15:1; + uint32_t HRS14:1; + uint32_t HRS13:1; + uint32_t HRS12:1; + uint32_t HRS11:1; + uint32_t HRS10:1; + uint32_t HRS09:1; + uint32_t HRS08:1; + uint32_t HRS07:1; + uint32_t HRS06:1; + uint32_t HRS05:1; + uint32_t HRS04:1; + uint32_t HRS03:1; + uint32_t HRS02:1; + uint32_t HRS01:1; + uint32_t HRS00:1; + } B; + } HRSL; + + uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */ +#else + uint32_t edma_reserved1[52]; +#endif + + union { + uint8_t R; + struct { + uint8_t ECP:1; +#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 + uint8_t DPA:1; +#else + uint8_t:1; +#endif + uint8_t GRPPRI:2; + uint8_t CHPRI:4; + } B; + } CPR[64]; + + uint32_t edma_reserved2[944]; + +/****************************************************************************/ +/* DMA2 Transfer Control Descriptor */ +/****************************************************************************/ + struct tcd_t { + uint32_t SADDR; /* source address */ + + /* Source and destination fields */ + union tcd_SDF_tag { + uint32_t R; + struct { + uint16_t SMOD:5; /* source address modulo */ + uint16_t SSIZE:3; /* source transfer size */ + uint16_t DMOD:5; /* destination address modulo */ + uint16_t DSIZE:3; /* destination transfer size */ + int16_t SOFF; /* signed source address offset */ + } B; + } SDF; + + uint32_t NBYTES; /* inner (“minor”) byte count */ + + int32_t SLAST; /* last destination address adjustment, or + scatter/gather address (if e_sg = 1) */ + + uint32_t DADDR; /* destination address */ + + /* CITER and destination fields */ + union tcd_CDF_tag { + uint32_t R; + struct { + uint16_t CITERE_LINK:1; + uint16_t CITER:15; + int16_t DOFF; /* signed destination address offset */ + } B; + struct { + uint16_t CITERE_LINK:1; + uint16_t CITERLINKCH:6; + uint16_t CITER:9; + int16_t DOFF; + } B_ALT; + struct { + uint16_t CITER; + int16_t DOFF; + } B_NOLINK; + } CDF; + + int32_t DLAST_SGA; + + /* BITER and misc fields */ + union tcd_BMF_tag { + uint32_t R; + struct { + uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */ + uint32_t BITER:15; + uint32_t BWC:2; /* bandwidth control */ + uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */ + uint32_t DONE:1; /* channel done */ + uint32_t ACTIVE:1; /* channel active */ + uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */ + uint32_t E_SG:1; /* enable scatter/gather descriptor */ + uint32_t D_REQ:1; /* disable ipd_req when done */ + uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + uint32_t INT_MAJ:1; /* interrupt on major loop completion */ + uint32_t START:1; /* explicit channel start */ + } B; + struct { + uint32_t BITERE_LINK:1; + uint32_t BITERLINKCH:6; + uint32_t BITER:9; + uint32_t BWC:2; + uint32_t MAJORLINKCH:6; + uint32_t DONE:1; + uint32_t ACTIVE:1; + uint32_t MAJORE_LINK:1; + uint32_t E_SG:1; + uint32_t D_REQ:1; + uint32_t INT_HALF:1; + uint32_t INT_MAJ:1; + uint32_t START:1; + } B_ALT; + struct { + uint16_t BITER; + uint16_t BWC:2; + uint16_t MAJORLINKCH:6; + uint16_t DONE:1; + uint16_t ACTIVE:1; + uint16_t MAJORE_LINK:1; + uint16_t E_SG:1; + uint16_t D_REQ:1; + uint16_t INT_HALF:1; + uint16_t INT_MAJ:1; + uint16_t START:1; + } B_NOLINK; + } BMF; + } TCD[64]; /* transfer_control_descriptor */ + }; + +#ifndef __cplusplus + static const struct tcd_t EDMA_TCD_DEFAULT = { + .SADDR = 0, + .SDF = { .R = 0 }, + .NBYTES = 0, + .SLAST = 0, + .DADDR = 0, + .CDF = { .R = 0 }, + .DLAST_SGA = 0, + .BMF = { .R = 0 } + }; +#endif /* __cplusplus */ + +#define EDMA_TCD_BITER_MASK 0x7fff + +#define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1) + +#define EDMA_TCD_BITER_LINKED_MASK 0x1ff + +#define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1) + +#define EDMA_TCD_LINK_AND_BITER(link, biter) \ + (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK)) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */ diff --git a/bsps/powerpc/include/mpc55xx/regs-mmu.h b/bsps/powerpc/include/mpc55xx/regs-mmu.h new file mode 100644 index 0000000000..e03047c4ad --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/regs-mmu.h @@ -0,0 +1,200 @@ +/** + * @file + * + * @ingroup mpc55xx + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + +#ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H +#define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H + +#include <stdint.h> + +#include <bspopts.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************/ +/* MMU */ +/****************************************************************************/ + struct MMU_tag { + union { + uint32_t R; + struct { + uint32_t : 2; + uint32_t TLBSEL : 2; + uint32_t : 7; + uint32_t ESEL : 5; + uint32_t : 11; + uint32_t NV : 5; + } B; + } MAS0; + + union { + uint32_t R; + struct { + uint32_t VALID : 1; + uint32_t IPROT : 1; + uint32_t : 6; + uint32_t TID : 8; + uint32_t : 3; + uint32_t TS : 1; + uint32_t TSIZE : 5; + uint32_t : 7; + } B; + } MAS1; + + union { + uint32_t R; + struct { + uint32_t EPN : 22; + uint32_t : 4; + uint32_t VLE : 1; + uint32_t W : 1; + uint32_t I : 1; + uint32_t M : 1; + uint32_t G : 1; + uint32_t E : 1; + } B; + } MAS2; + + union { + uint32_t R; + struct { + uint32_t RPN : 22; + uint32_t U0 : 1; + uint32_t U1 : 1; + uint32_t U2 : 1; + uint32_t U3 : 1; + uint32_t UX : 1; + uint32_t SX : 1; + uint32_t UW : 1; + uint32_t SW : 1; + uint32_t UR : 1; + uint32_t SR : 1; + } B; + } MAS3; + }; + + union MMU_MAS4_tag { + uint32_t R; + struct { + uint32_t : 2; + uint32_t TLBSELD : 2; + uint32_t : 10; + uint32_t TIDSELD : 2; + uint32_t : 4; + uint32_t TSIZED : 4; + uint32_t : 3; + uint32_t WD : 1; + uint32_t ID : 1; + uint32_t MD : 1; + uint32_t GD : 1; + uint32_t ED : 1; + } B; + }; + + union MMU_MAS6_tag { + uint32_t R; + struct { + uint32_t : 8; + uint32_t SPID : 8; + uint32_t : 15; + uint32_t SAS : 1; + } B; + }; + +#define MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addreff, addrreal, size, x, w, r, io) \ + { \ + .MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \ + .MAS1 = { .B = { \ + .VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \ + }, \ + .MAS2 = { .B = { \ + .EPN = (addreff) >> 10, .VLE = 0, \ + .W = (io) == 2, .I = (io) == 1, .M = 0, .G = (io) == 1, .E = 0 } \ + }, \ + .MAS3 = { .B = { \ + .RPN = (addrreal) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \ + .SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \ + } \ + } + +#define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \ + MPC55XX_MMU_TAG_TRANSLATE_INITIALIZER(idx, addr, addr, size, x, w, r, io) + +#define MPC55XX_MMU_1K 0 +#define MPC55XX_MMU_2K 1 +#define MPC55XX_MMU_4K 2 +#define MPC55XX_MMU_8K 3 +#define MPC55XX_MMU_16K 4 +#define MPC55XX_MMU_32K 5 +#define MPC55XX_MMU_64K 6 +#define MPC55XX_MMU_128K 7 +#define MPC55XX_MMU_256K 8 +#define MPC55XX_MMU_512K 9 +#define MPC55XX_MMU_1M 10 +#define MPC55XX_MMU_2M 11 +#define MPC55XX_MMU_4M 12 +#define MPC55XX_MMU_8M 13 +#define MPC55XX_MMU_16M 14 +#define MPC55XX_MMU_32M 15 +#define MPC55XX_MMU_64M 16 +#define MPC55XX_MMU_128M 17 +#define MPC55XX_MMU_256M 18 +#define MPC55XX_MMU_512M 19 +#define MPC55XX_MMU_1G 20 +#define MPC55XX_MMU_2G 21 +#define MPC55XX_MMU_4G 22 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */ diff --git a/bsps/powerpc/include/mpc55xx/regs.h b/bsps/powerpc/include/mpc55xx/regs.h new file mode 100644 index 0000000000..3a4e737f1a --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/regs.h @@ -0,0 +1,88 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Register definitions for the MPC55xx and MPC56xx microcontroller + * family. + */ + +/* + * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_REGS_H +#define LIBCPU_POWERPC_MPC55XX_REGS_H + +#include <bspopts.h> + +#if MPC55XX_CHIP_FAMILY == 551 + #include <mpc55xx/fsl-mpc551x.h> + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL_ENHANCED + #define MPC55XX_HAS_SIU +#elif MPC55XX_CHIP_FAMILY == 555 + #include <mpc55xx/fsl-mpc555x.h> + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL + #define MPC55XX_HAS_UNIFIED_CACHE + #define MPC55XX_HAS_SIU +#elif MPC55XX_CHIP_FAMILY == 556 + #include <mpc55xx/fsl-mpc556x.h> + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL + #define MPC55XX_HAS_UNIFIED_CACHE + #define MPC55XX_HAS_SIU +#elif MPC55XX_CHIP_FAMILY == 564 + #include <mpc55xx/fsl-mpc564xL.h> + #define MPC55XX_HAS_STM + #define MPC55XX_HAS_SWT + #define MPC55XX_HAS_MODE_CONTROL + #define MPC55XX_HAS_INSTRUCTION_CACHE + #define MPC55XX_HAS_LINFLEX + #define MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA + #define MPC55XX_HAS_SIU_LITE +#elif MPC55XX_CHIP_FAMILY == 566 + #include <mpc55xx/fsl-mpc5668.h> + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL_ENHANCED + #define MPC55XX_HAS_UNIFIED_CACHE + #define MPC55XX_HAS_SIU + /* + * TODO: This e200z650n3e core has a wait instruction, but it did not wake-up + * from PIT interrupts. + */ +#elif MPC55XX_CHIP_FAMILY == 567 + #include <mpc55xx/fsl-mpc567x.h> + #define MPC55XX_HAS_EBI + #define MPC55XX_HAS_ESCI + #define MPC55XX_HAS_EMIOS + #define MPC55XX_HAS_FMPLL_ENHANCED + #define MPC55XX_HAS_INSTRUCTION_CACHE + #define MPC55XX_HAS_DATA_CACHE + #define MPC55XX_HAS_SIU + #define MPC55XX_HAS_WAIT_INSTRUCTION +#else + #error "unsupported chip type" +#endif + +#define MPC55XX_ZERO_FLAGS { .R = 0 } + +#endif /* LIBCPU_POWERPC_MPC55XX_REGS_H */ diff --git a/bsps/powerpc/include/mpc55xx/siu.h b/bsps/powerpc/include/mpc55xx/siu.h new file mode 100644 index 0000000000..3495750145 --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/siu.h @@ -0,0 +1,313 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief System Integration Unit Access (SIU). + */ + +/* + * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_SIU_H +#define LIBCPU_POWERPC_MPC55XX_SIU_H + +#include <rtems.h> + +#include <mpc55xx/regs.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef enum { + #if MPC55XX_CHIP_FAMILY == 567 + PCR_MDO4_GPIO75 = 75, + PCR_MDO5_GPIO76 = 76, + PCR_MDO6_GPIO77 = 77, + PCR_MDO7_GPIO78 = 78, + PCR_MDO8_GPIO79 = 79, + PCR_MDO9_GPIO80 = 80, + PCR_MDO10_GPIO81 = 81, + PCR_MDO11_GPIO82 = 82, + PCR_CNTXA_TXDA_GPIO83 = 83, + PCR_CNRXA_RXDA_GPIO84 = 84, + PCR_CNTXB_PCSC3_GPIO85 = 85, + PCR_CNRXB_PCSC4_GPIO86 = 86, + PCR_CNTXC_PCSD3_GPIO87 = 87, + PCR_CNRXC_PCSD4_GPIO88 = 88, + PCR_TXDA_GPIO89 = 89, + PCR_RXDA_GPIO90 = 90, + PCR_TXDB_PCSD1_GPIO91 = 91, + PCR_RXDB_PCSD5_GPIO92 = 92, + PCR_SCKA_PCSC1_GPIO93 = 93, + PCR_SINA_PCSC2_GPIO94 = 94, + PCR_SOUTA_PCSC5_GPIO95 = 95, + PCR_PCSA0_PCSD2_GPIO96 = 96, + PCR_PCSA1_GPIO97 = 97, + PCR_PCSA2_GPIO98 = 98, + PCR_PCSA3_GPIO99 = 99, + PCR_PCSA4_GPIO100 = 100, + PCR_PCSA5_ETRIG1_GPIO101 = 101, + PCR_SCKB_GPIO102 = 102, + PCR_SINB_GPIO103 = 103, + PCR_SOUTB_GPIO104 = 104, + PCR_PCSB0_PCSD2_GPIO105 = 105, + PCR_PCSB1_PCSD0_GPIO106 = 106, + PCR_PCSB2_SOUTC_GPIO107 = 107, + PCR_PCSB3_SINC_GPIO108 = 108, + PCR_PCSB4_SCKC_GPIO109 = 109, + PCR_PCSB5_PCSC0_GPIO110 = 110, + PCR_TCRCLKA_IRQ7_GPIO113 = 113, + PCR_ETPUA0_ETPUA12_GPIO114 = 114, + PCR_ETPUA1_ETPUA13_GPIO115 = 115, + PCR_ETPUA2_ETPUA14_GPIO116 = 116, + PCR_ETPUA3_ETPUA15_GPIO117 = 117, + PCR_ETPUA4_ETPUA16_GPIO118 = 118, + PCR_ETPUA5_ETPUA17_GPIO119 = 119, + PCR_ETPUA6_ETPUA18_GPIO120 = 120, + PCR_ETPUA7_ETPUA19_GPIO121 = 121, + PCR_ETPUA8_ETPUA20_GPIO122 = 122, + PCR_ETPUA9_ETPUA21_GPIO123 = 123, + PCR_ETPUA10_ETPUA22_GPIO124 = 124, + PCR_ETPUA11_ETPUA23_GPIO125 = 125, + PCR_ETPUA12_PCSB1_GPIO126 = 126, + PCR_ETPUA13_PCSB3_GPIO127 = 127, + PCR_ETPUA14_PCSB4_GPIO128 = 128, + PCR_ETPUA15_PCSB5_GPIO129 = 129, + PCR_ETPUA16_PCSD1_GPIO130 = 130, + PCR_ETPUA17_PCSD2_GPIO131 = 131, + PCR_ETPUA18_PCSD3_GPIO132 = 132, + PCR_ETPUA19_PCSD4_GPIO133 = 133, + PCR_ETPUA20_IRQ8_GPIO134 = 134, + PCR_ETPUA21_IRQ9_GPIO135 = 135, + PCR_ETPUA22_IRQ10_GPIO136 = 136, + PCR_ETPUA23_IRQ11_GPIO137 = 137, + PCR_ETPUA24_IRQ12_GPIO138 = 138, + PCR_ETPUA25_IRQ13_GPIO139 = 139, + PCR_ETPUA26_IRQ14_GPIO140 = 140, + PCR_ETPUA27_IRQ15_GPIO141 = 141, + PCR_ETPUA28_PCSC1_GPIO142 = 142, + PCR_ETPUA29_PCSC2_GPIO143 = 143, + PCR_ETPUA30_PCSC3_GPIO144 = 144, + PCR_ETPUA31_PCSC4_GPIO145 = 145, + PCR_TCRCLKB_IRQ6_GPIO146 = 146, + PCR_ETPUB0_ETPUB16_GPIO147 = 147, + PCR_ETPUB1_ETPUB17_GPIO148 = 148, + PCR_ETPUB2_ETPUB18_GPIO149 = 149, + PCR_ETPUB3_ETPUB19_GPIO150 = 150, + PCR_ETPUB4_ETPUB20_GPIO151 = 151, + PCR_ETPUB5_ETPUB21_GPIO152 = 152, + PCR_ETPUB6_ETPUB22_GPIO153 = 153, + PCR_ETPUB7_ETPUB23_GPIO154 = 154, + PCR_ETPUB8_ETPUB24_GPIO155 = 155, + PCR_ETPUB9_ETPUB25_GPIO156 = 156, + PCR_ETPUB10_ETPUB26_GPIO157 = 157, + PCR_ETPUB11_ETPUB27_GPIO158 = 158, + PCR_ETPUB12_ETPUB28_GPIO159 = 159, + PCR_ETPUB13_ETPUB29_GPIO160 = 160, + PCR_ETPUB14_ETPUB30_GPIO161 = 161, + PCR_ETPUB15_ETPUB31_GPIO162 = 162, + PCR_ETPUB16_PCSA1_GPIO163 = 163, + PCR_ETPUB17_PCSA2_GPIO164 = 164, + PCR_ETPUB18_PCSA3_GPIO165 = 165, + PCR_ETPUB19_PCSA4_GPIO166 = 166, + PCR_ETPUB20_GPIO167 = 167, + PCR_ETPUB21_GPIO168 = 168, + PCR_ETPUB22_GPIO169 = 169, + PCR_ETPUB23_GPIO170 = 170, + PCR_ETPUB24_GPIO171 = 171, + PCR_ETPUB25_GPIO172 = 172, + PCR_ETPUB26_GPIO173 = 173, + PCR_ETPUB27_GPIO174 = 174, + PCR_ETPUB28_GPIO175 = 175, + PCR_ETPUB29_GPIO176 = 176, + PCR_ETPUB30_GPIO177 = 177, + PCR_ETPUB31_GPIO178 = 178, + PCR_EMIOS0_ETPUA0_GPIO179 = 179, + PCR_EMIOS1_ETPUA1_GPIO180 = 180, + PCR_EMIOS2_ETPUA2_GPIO181 = 181, + PCR_EMIOS3_ETPUA3_GPIO182 = 182, + PCR_EMIOS4_ETPUA4_GPIO183 = 183, + PCR_EMIOS5_ETPUA5_GPIO184 = 184, + PCR_EMIOS6_ETPUA6_GPIO185 = 185, + PCR_EMIOS7_ETPUA7_GPIO186 = 186, + PCR_EMIOS8_ETPUA8_GPIO187 = 187, + PCR_EMIOS9_ETPUA9_GPIO188 = 188, + PCR_EMIOS10_SCKD_GPIO189 = 189, + PCR_EMIOS11_SIND_GPIO190 = 190, + PCR_EMIOS12_SOUTC_GPIO191 = 191, + PCR_EMIOS13_SOUTD_GPIO192 = 192, + PCR_EMIOS14_IRQ0_GPIO193 = 193, + PCR_EMIOS15_IRQ1_GPIO194 = 194, + PCR_EMIOS16_ETPUB0_GPIO195 = 195, + PCR_EMIOS17_ETPUB1_GPIO196 = 196, + PCR_EMIOS18_ETPUB2_GPIO197 = 197, + PCR_EMIOS19_ETPUB3_GPIO198 = 198, + PCR_EMIOS20_ETPUB4_GPIO199 = 199, + PCR_EMIOS21_ETPUB5_GPIO200 = 200, + PCR_EMIOS22_ETPUB6_GPIO201 = 201, + PCR_EMIOS23_ETPUB7_GPIO202 = 202, + PCR_EMIOS24_PCSB0_GPIO203 = 203, + PCR_EMIOS25_PCSB1_GPIO204 = 204, + PCR_PLLCFG0_IRQ4_GPIO208 = 208, + PCR_PLLCFG1_IRQ5_GPIO209 = 209, + PCR_BOOTCFG0_IRQ2_GPIO211 = 211, + PCR_BOOTCFG1_IRQ3_GPIO212 = 212, + PCR_WKPCFG_NMI_GPIO213 = 213, + PCR_ENGCLK = 214, + PCR_MCKO = 219, + PCR_MDO0_GPIO220 = 220, + PCR_MDO1_GPIO221 = 221, + PCR_MDO2_GPIO222 = 222, + PCR_MDO3_GPIO223 = 223, + PCR_MSEO0 = 224, + PCR_MSEO1 = 225, + PCR_RDY = 226, + PCR_TDO = 228, + PCR_D_CLKOUT = 229, + PCR_RSTOUT = 230, + PCR_MDO12_GPIO231 = 231, + PCR_MDO13_GPIO232 = 232, + PCR_MDO14_GPIO233 = 233, + PCR_MDO15_GPIO234 = 234, + PCR_SCKC_SCK_C_LVDSP_GPIO235 = 235, + PCR_SINC_SCK_C_LVDSM_GPIO236 = 236, + PCR_SOUTC_SOUT_C_LVDSP_GPIO237 = 237, + PCR_PCSC0_SOUT_C_LVDSM_GPIO238 = 238, + PCR_PCSC1_GPIO239 = 239, + PCR_PCSC2_GPIO240 = 240, + PCR_PCSC3_GPIO241 = 241, + PCR_PCSC4_GPIO242 = 242, + PCR_PCSC5_GPIO243 = 243, + PCR_TXDC_ETRIG0_GPIO244 = 244, + PCR_RXDC_GPIO245 = 245, + PCR_CNTXD_GPIO246 = 246, + PCR_CNRXD_GPIO247 = 247, + PCR_FR_A_TX_GPIO248 = 248, + PCR_FR_A_RX_GPIO249 = 249, + PCR_FR_A_TX_EN_GPIO250 = 250, + PCR_FR_B_TX_GPIO251 = 251, + PCR_FR_B_RX_GPIO252 = 252, + PCR_FR_B_TX_EN_GPIO253 = 253, + PCR_D_CS0_GPIO256 = 256, + PCR_D_CS2_D_ADD_DAT31_GPIO257 = 257, + PCR_D_CS3_D_TEA_GPIO258 = 258, + PCR_D_ADD12_GPIO259 = 259, + PCR_D_ADD13_GPIO260 = 260, + PCR_D_ADD14_GPIO261 = 261, + PCR_D_ADD15_GPIO262 = 262, + PCR_D_ADD16_D_ADD_DAT16_GPIO263 = 263, + PCR_D_ADD17_D_ADD_DAT17_GPIO264 = 264, + PCR_D_ADD18_D_ADD_DAT18_GPIO265 = 265, + PCR_D_ADD19_D_ADD_DAT19_GPIO266 = 266, + PCR_D_ADD20_D_ADD_DAT20_GPIO267 = 267, + PCR_D_ADD21_D_ADD_DAT21_GPIO268 = 268, + PCR_D_ADD22_D_ADD_DAT22_GPIO269 = 269, + PCR_D_ADD23_D_ADD_DAT23_GPIO270 = 270, + PCR_D_ADD24_D_ADD_DAT24_GPIO271 = 271, + PCR_D_ADD25_D_ADD_DAT25_GPIO272 = 272, + PCR_D_ADD26_D_ADD_DAT26_GPIO273 = 273, + PCR_D_ADD27_D_ADD_DAT27_GPIO274 = 274, + PCR_D_ADD28_D_ADD_DAT28_GPIO275 = 275, + PCR_D_ADD29_D_ADD_DAT29_GPIO276 = 276, + PCR_D_ADD30_D_ADD_DAT30_GPIO277 = 277, + PCR_D_ADD_DAT0_GPIO278 = 278, + PCR_D_ADD_DAT1_GPIO279 = 279, + PCR_D_ADD_DAT2_GPIO280 = 280, + PCR_D_ADD_DAT3_GPIO281 = 281, + PCR_D_ADD_DAT4_GPIO282 = 282, + PCR_D_ADD_DAT5_GPIO283 = 283, + PCR_D_ADD_DAT6_GPIO284 = 284, + PCR_D_ADD_DAT7_GPIO285 = 285, + PCR_D_ADD_DAT8_GPIO286 = 286, + PCR_D_ADD_DAT9_GPIO287 = 287, + PCR_D_ADD_DAT10_GPIO288 = 288, + PCR_D_ADD_DAT11_GPIO289 = 289, + PCR_D_ADD_DAT12_GPIO290 = 290, + PCR_D_ADD_DAT13_GPIO291 = 291, + PCR_D_ADD_DAT14_GPIO292 = 292, + PCR_D_ADD_DAT15_GPIO293 = 293, + PCR_D_RD_WR_GPIO294 = 294, + PCR_D_WE0_GPIO295 = 295, + PCR_D_WE1_GPIO296 = 296, + PCR_D_OE_GPIO297 = 297, + PCR_D_TS_GPIO298 = 298, + PCR_D_ALE_GPIO299 = 299, + PCR_D_TA_GPIO300 = 300, + PCR_D_CS1_GPIO301 = 301, + PCR_D_BDIP_GPIO302 = 302, + PCR_D_WE2_GPIO303 = 303, + PCR_D_WE3_GPIO304 = 304, + PCR_D_ADD9_GPIO305 = 305, + PCR_D_ADD10_GPIO306 = 306, + PCR_D_ADD11_GPIO307 = 307, + PCR_EMIOS26_PCSB2_GPIO432 = 432, + PCR_EMIOS27_PCSB3_GPIO433 = 433, + PCR_EMIOS28_PCSC0_GPIO434 = 434, + PCR_EMIOS29_PCSC1_GPIO435 = 435, + PCR_EMIOS30_PCSC2_GPIO436 = 436, + PCR_EMIOS31_PCSC5_GPIO437 = 437, + PCR_TCRCLKC_GPIO440 = 440, + PCR_ETPUC0_GPIO441 = 441, + PCR_ETPUC1_GPIO442 = 442, + PCR_ETPUC2_GPIO443 = 443, + PCR_ETPUC3_GPIO444 = 444, + PCR_ETPUC4_GPIO445 = 445, + PCR_ETPUC5_GPIO446 = 446, + PCR_ETPUC6_GPIO447 = 447, + PCR_ETPUC7_GPIO448 = 448, + PCR_ETPUC8_GPIO449 = 449, + PCR_ETPUC9_IRQ0_GPIO450 = 450, + PCR_ETPUC10__IRQ1_GPIO451 = 451, + PCR_ETPUC11_IRQ2_GPIO452 = 452, + PCR_ETPUC12_IRQ3_GPIO453 = 453, + PCR_ETPUC13_3_IRQ4_GPIO454 = 454, + PCR_ETPUC14_4_IRQ5_GPIO455 = 455, + PCR_ETPUC15__GPIO456 = 456, + PCR_ETPUC16_FR_A_TX_GPIO457 = 457, + PCR_ETPUC17_FR_A_RX_GPIO458 = 458, + PCR_ETPUC18_FR_A_TX_EN_GPIO459 = 459, + PCR_ETPUC19_TXDA_GPIO460 = 460, + PCR_ETPUC20_RXDA_GPIO461 = 461, + PCR_ETPUC21_TXDB_GPIO462 = 462, + PCR_ETPUC22_RXDB_GPIO463 = 463, + PCR_ETPUC23_PCSD5_GPIO464 = 464, + PCR_ETPUC24_PCSD4_GPIO465 = 465, + PCR_ETPUC25_PCSD3_GPIO466 = 466, + PCR_ETPUC26_PCSD2_GPIO467 = 467, + PCR_ETPUC27_PCSD1_GPIO468 = 468, + PCR_ETPUC28_PCSD0_GPIO469 = 469, + PCR_ETPUC29_SCKD_GPIO470 = 470, + PCR_ETPUC30_SOUTD_GPIO471 = 471, + PCR_ETPUC31_SIND_GPIO472 = 472 + #else + PCR_TODO + #endif +} pcr_index; + +typedef struct mpc55xx_siu_pcr_entry { + uint16_t pcr_idx; /* first PCR index for this entry */ + uint16_t pcr_cnt; /* PCR count using this entry */ + union SIU_PCR_tag pcr_val; /* value to write to the PCR[idx++val] */ +} mpc55xx_siu_pcr_entry_t; + +rtems_status_code mpc55xx_siu_pcr_init(volatile struct SIU_tag *siu, + const mpc55xx_siu_pcr_entry_t *pcr_entry); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_SIU_H */ diff --git a/bsps/powerpc/include/mpc55xx/watchdog.h b/bsps/powerpc/include/mpc55xx/watchdog.h new file mode 100644 index 0000000000..d5a8af794e --- /dev/null +++ b/bsps/powerpc/include/mpc55xx/watchdog.h @@ -0,0 +1,68 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Header file for the watchdog timer. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBCPU_POWERPC_MPC55XX_WATCHDOG_H +#define LIBCPU_POWERPC_MPC55XX_WATCHDOG_H + +#include <stdbool.h> + +#include <rtems.h> + +#include <libcpu/powerpc-utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +static inline void mpc55xx_watchdog_clear() +{ + PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_TSR, BOOKE_TSR_WIS); +} + +static inline void mpc55xx_watchdog_enable_interrupt( bool enable) +{ + if (enable) { + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_WIE); + } else { + PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( BOOKE_TCR, BOOKE_TCR_WIE); + } +} + +static inline rtems_status_code mpc55xx_watchdog_set_time_base_bit( uint32_t bit) +{ + if (bit > 63) { + return RTEMS_INVALID_NUMBER; + } + + PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( + BOOKE_TCR, + BOOKE_TCR_WP( bit) | BOOKE_TCR_WPEXT( bit >> 2), + BOOKE_TCR_WP_MASK | BOOKE_TCR_WPEXT_MASK + ); + + return RTEMS_SUCCESSFUL; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBCPU_POWERPC_MPC55XX_WATCHDOG_H */ diff --git a/bsps/powerpc/include/mpc5xx.h b/bsps/powerpc/include/mpc5xx.h new file mode 100644 index 0000000000..fc9b756cbf --- /dev/null +++ b/bsps/powerpc/include/mpc5xx.h @@ -0,0 +1,626 @@ +/* + * + * MPC5xx Internal I/O Definitions + */ + +/* + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h: + * + * Submitted By: * + * * + * W. Eric Norum * + * Saskatchewan Accelerator Laboratory * + * University of Saskatchewan * + * 107 North Road * + * Saskatoon, Saskatchewan, CANADA * + * S7N 5C6 * + * * + * eric@skatter.usask.ca * + * * + * Modified for use with the MPC860 (original code was for MC68360) * + * by * + * Jay Monkman * + * Frasca International, Inc. * + * 906 E. Airport Rd. * + * Urbana, IL, 61801 * + * * + * jmonkman@frasca.com * + * * + * Modified further for use with the MPC821 by: * + * Andrew Bray <andy@chaos.org.uk> * + * * + * With some corrections/additions by: * + * Darlene A. Stewart and * + * Charles-Antoine Gauthier * + * Institute for Information Technology * + * National Research Council of Canada * + * Ottawa, ON K1A 0R6 * + * * + * Darlene.Stewart@iit.nrc.ca * + * charles.gauthier@iit.nrc.ca * + * * + * Corrections/additions: * + * Copyright (c) 1999, National Research Council of Canada * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC5XX_H +#define _MPC5XX_H + +#include <libcpu/spr.h> + + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Macros for accessing Special Purpose Registers (SPRs) + */ + +#define _eieio __asm__ volatile ("eieio\n"::) +#define _sync __asm__ volatile ("sync\n"::) +#define _isync __asm__ volatile ("isync\n"::) + +/* + * Core Registers (SPRs) + */ +#define DER 149 /* Debug Enable Register */ +#define IMMR 638 /* Internal Memory Map Register */ +#define IMMR_FLEN (1<<11) /* Internal flash ROM enabled */ + +/* + * Interrupt Control Registers (SPRs) + */ +#define EIE 80 /* External Interrupt Enable Register */ +#define EID 81 /* External Interrupt Disable Register */ +#define NRI 82 /* Non-Recoverable Interrupt Register */ + +#define ECR 148 /* Exception Cause Register */ + +/* + * Bus Control Registers (SPRs) + */ +#define LCTRL1 156 /* L-Bus Support Control Register 1 */ +#define LCTRL2 157 /* L-Bus Support Control Register 2 */ +#define ICTRL 158 /* I-Bus Support Control Register */ + +/* + * Burst Buffer Control Registers (SPRs) + */ +#define BBCMCR 560 /* Burst Buffer Configuration Register */ +#define BBCMCR_BE (1<<13) /* Burst enable */ +#define BBCMCR_ETRE (1<<12) /* Exception table relocation enable */ + +#define MI_RBA0 784 /* Region 0 Address Register */ +#define MI_RBA1 785 /* Region 1 Address Register */ +#define MI_RBA2 786 /* Region 2 Address Register */ +#define MI_RBA3 787 /* Region 3 Address Register */ + +#define MI_RA0 816 /* Region 0 Attribute Register */ +#define MI_RA1 817 /* Region 1 Attribute Register */ +#define MI_RA2 818 /* Region 2 Attribute Register */ +#define MI_RA3 819 /* Region 3 Attribute Register */ +#define MI_GRA 528 /* Region Global Attribute Register */ +#define MI_RA_PP (3 << 10) /* Protection bits: */ +#define MI_RA_PP_SUPV (1 << 10) /* Supervisor */ +#define MI_RA_PP_USER (2 << 10) /* User */ +#define MI_RA_G (1 << 6) /* Guarded region */ + + +/* + * L-Bus to U-Bus Interface (L2U) Registers (SPRs) + */ +#define L2U_MCR 568 /* L2U Module Configuration Register */ + +#define L2U_RBA0 792 /* L2U Region 0 Address Register */ +#define L2U_RBA1 793 /* L2U Region 1 Address Register */ +#define L2U_RBA2 794 /* L2U Region 2 Address Register */ +#define L2U_RBA3 795 /* L2U Region 3 Address Register */ + +#define L2U_RA0 824 /* L2U Region 0 Attribute Register */ +#define L2U_RA1 825 /* L2U Region 1 Attribute Register */ +#define L2U_RA2 826 /* L2U Region 2 Attribute Register */ +#define L2U_RA3 827 /* L2U Region 3 Attribute Register */ +#define L2U_GRA 536 /* L2U Global Region Attribute Register */ +#define L2U_RA_PP (3 << 10) /* Protection bits: */ +#define L2U_RA_PP_SUPV (1 << 10) /* Supervisor */ +#define L2U_RA_PP_USER (2 << 10) /* User */ +#define L2U_RA_G (1 << 6) /* Guarded region */ + + +/* + ************************************************************************* + * REGISTER SUBBLOCKS * + ************************************************************************* + */ + +/* + ************************************************************************* + * System Protection Control Register (SYPCR) * + ************************************************************************* + */ +#define USIU_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +#define USIU_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define USIU_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define USIU_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define USIU_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define USIU_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define USIU_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* + ************************************************************************* + * Software Service Register (SWSR) * + ************************************************************************* + */ +#define TICKLE_WATCHDOG() \ +do { \ + usiu.swsr = 0x556C; \ + usiu.swsr = 0xAA39; \ +} while (0) \ + +/* + ************************************************************************* + * Memory Control Registers * + ************************************************************************* + */ +#define USIU_MEMC_BR_BA(x) (((uint32_t)x)&0xffff8000) + /* Base address */ +#define USIU_MEMC_BR_AT(x) ((x)<<12) /* Address type */ +#define USIU_MEMC_BR_PS8 (1<<10) /* 8 bit port */ +#define USIU_MEMC_BR_PS16 (2<<10) /* 16 bit port */ +#define USIU_MEMC_BR_PS32 (0<<10) /* 32 bit port */ +#define USIU_MEMC_BR_WP (1<<8) /* Write protect */ +#define USIU_MEMC_BR_WEBS (1<<5) /* Write enable/byte select */ +#define USIU_MEMC_BR_TBDIP (1<<4) /* Toggle-Burst data in progress*/ +#define USIU_MEMC_BR_LBDIP (1<<3) /* Late-burst data in progress */ +#define USIU_MEMC_BR_SETA (1<<2) /* External transfer acknowledge */ +#define USIU_MEMC_BR_BI (1<<1) /* Burst inhibit */ +#define USIU_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define USIU_MEMC_OR_32K 0xffff8000 /* Address range */ +#define USIU_MEMC_OR_64K 0xffff0000 +#define USIU_MEMC_OR_128K 0xfffe0000 +#define USIU_MEMC_OR_256K 0xfffc0000 +#define USIU_MEMC_OR_512K 0xfff80000 +#define USIU_MEMC_OR_1M 0xfff00000 +#define USIU_MEMC_OR_2M 0xffe00000 +#define USIU_MEMC_OR_4M 0xffc00000 +#define USIU_MEMC_OR_8M 0xff800000 +#define USIU_MEMC_OR_16M 0xff000000 +#define USIU_MEMC_OR_32M 0xfe000000 +#define USIU_MEMC_OR_64M 0xfc000000 +#define USIU_MEMC_OR_128 0xf8000000 +#define USIU_MEMC_OR_256M 0xf0000000 +#define USIU_MEMC_OR_512M 0xe0000000 +#define USIU_MEMC_OR_1G 0xc0000000 +#define USIU_MEMC_OR_2G 0x80000000 +#define USIU_MEMC_OR_4G 0x00000000 +#define USIU_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define USIU_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define USIU_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define USIU_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define USIU_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define USIU_MEMC_OR_ETHR (1<<8) /* Extended hold time on reads */ +#define USIU_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define USIU_MEMC_OR_BSCY(x) ((x)<<1) /* Burst beat length in clocks */ +#define USIU_MEMC_OR_TRLX (1<<0) /* Relaxed timing in GPCM */ + +/* + ************************************************************************* + * Clocks and Reset Controlmer * + ************************************************************************* + */ + +#define USIU_SCCR_DBCT (1<<31) /* Disable backup clock for timers */ +#define USIU_SCCR_COM(x) ((x)<<29) /* Clock output mode */ +#define USIU_SCCR_RTDIV (1<<24) /* RTC, PIT divide by 256, not 4 */ +#define USIU_PRQEN (1<<21) /* MSR[POW] controls frequency */ +#define USIU_SCCR_EBDF(x) ((x)<<17) /* External bus division factor */ +#define USIU_LME (1<<16) /* Enable limp mode */ +#define USIU_ENGDIV(x) ((x)<<9) /* Set engineering clock divisor */ + +#define USIU_PLPRCR_MF(x) (((x)-1)<<20) /* PLL mult. factor (true) */ +#define USIU_PLPRCR_SPLS (1<<16) /* System PLL locked */ +#define USIU_PLPRCR_TEXPS (1<<14) /* Assert TEXP always */ + +/* + ************************************************************************* + * Programmable Interval Timer * + ************************************************************************* + */ +#define USIU_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ +#define USIU_PISCR_PS (1<<7) /* PIT Interrupt state */ +#define USIU_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define USIU_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ +#define USIU_PISCR_PTE (1<<0) /* PIT enable */ + +/* + ************************************************************************* + * Time Base * + ************************************************************************* + */ +#define USIU_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define USIU_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define USIU_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define USIU_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define USIU_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define USIU_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define USIU_TBSCR_TBE (1<<0) /* enable TB and decrementer */ + +/* + ************************************************************************* + * SIU Interrupt Mask * + ************************************************************************* + */ +#define USIU_SIMASK_IRM0 (1<<31) +#define USIU_SIMASK_LVM0 (1<<30) +#define USIU_SIMASK_IRM1 (1<<29) +#define USIU_SIMASK_LVM1 (1<<28) +#define USIU_SIMASK_IRM2 (1<<27) +#define USIU_SIMASK_LVM2 (1<<26) +#define USIU_SIMASK_IRM3 (1<<25) +#define USIU_SIMASK_LVM3 (1<<24) +#define USIU_SIMASK_IRM4 (1<<23) +#define USIU_SIMASK_LVM4 (1<<22) +#define USIU_SIMASK_IRM5 (1<<21) +#define USIU_SIMASK_LVM5 (1<<20) +#define USIU_SIMASK_IRM6 (1<<19) +#define USIU_SIMASK_LVM6 (1<<18) +#define USIU_SIMASK_IRM7 (1<<17) +#define USIU_SIMASK_LVM7 (1<<16) + +/* + ************************************************************************* + * SIU Module Control * + ************************************************************************* + */ +#define USIU_SIUMCR_EARB (1<<31) +#define USIU_SIUMCR_EARP0 (0<<28) +#define USIU_SIUMCR_EARP1 (1<<28) +#define USIU_SIUMCR_EARP2 (2<<28) +#define USIU_SIUMCR_EARP3 (3<<28) +#define USIU_SIUMCR_EARP4 (4<<28) +#define USIU_SIUMCR_EARP5 (5<<28) +#define USIU_SIUMCR_EARP6 (6<<28) +#define USIU_SIUMCR_EARP7 (7<<28) +#define USIU_SIUMCR_DSHW (1<<23) +#define USIU_SIUMCR_DBGC0 (0<<21) +#define USIU_SIUMCR_DBGC1 (1<<21) +#define USIU_SIUMCR_DBGC2 (2<<21) +#define USIU_SIUMCR_DBGC3 (3<<21) +#define USIU_SIUMCR_DBPC (1<<20) +#define USIU_SIUMCR_ATWC (1<<19) +#define USIU_SIUMCR_GPC0 (0<<17) +#define USIU_SIUMCR_GPC1 (1<<17) +#define USIU_SIUMCR_GPC2 (2<<17) +#define USIU_SIUMCR_GPC3 (3<<17) +#define USIU_SIUMCR_DLK (1<<16) +#define USIU_SIUMCR_SC0 (0<<13) +#define USIU_SIUMCR_SC1 (1<<13) +#define USIU_SIUMCR_SC2 (2<<13) +#define USIU_SIUMCR_SC3 (3<<13) +#define USIU_SIUMCR_RCTX (1<<12) +#define USIU_SIUMCR_MLRC0 (0<<10) +#define USIU_SIUMCR_MLRC1 (1<<10) +#define USIU_SIUMCR_MLRC2 (2<<10) +#define USIU_SIUMCR_MLRC3 (3<<10) +#define USIU_SIUMCR_MTSC (1<<7) + +/* + * Value to write to a key register to unlock the corresponding SIU register + */ +#define USIU_UNLOCK_KEY 0x55CCAA33 + +/* + ************************************************************************* + * UIMB Module Control * + ************************************************************************* + */ +#define UIMB_UMCR_STOP (1<<31) +#define UIMB_UMCR_IRQMUX(x) ((x)<<29) +#define UIMB_UMCR_HSPEED (1<<28) + +/* + ************************************************************************* + * QSMCM Serial Communications Interface (SCI) * + ************************************************************************* + */ + + +#define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ + +#define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ + +#define QSMCM_SCI_LOOPS (1<<14) /* Loopback test mode */ +#define QSMCM_SCI_WOMS (1<<13) /* Wire-or mode select */ +#define QSMCM_SCI_ILT (1<<12) /* Idle-line detect type */ +#define QSMCM_SCI_PT (1<<11) /* Parity type */ +#define QSMCM_SCI_PE (1<<10) /* Parity enable */ +#define QSMCM_SCI_M (1<<9) /* 11-bit mode */ +#define QSMCM_SCI_WAKE (1<<8) /* Wakeup mode */ + +#define QSMCM_SCI_TIE (1<<7) /* Transmitter interrupt enable */ +#define QSMCM_SCI_TCIE (1<<6) /* Transmit complete intr. enable */ +#define QSMCM_SCI_RIE (1<<5) /* Receiver interrupt enable */ +#define QSMCM_SCI_ILIE (1<<4) /* Idle line interrupt enable */ +#define QSMCM_SCI_TE (1<<3) /* Transmitter enable */ +#define QSMCM_SCI_RE (1<<2) /* Receiver enable */ +#define QSMCM_SCI_RWU (1<<1) /* Receiver wake-up enable */ +#define QSMCM_SCI_SBK (1<<0) /* Send break */ + +#define QSMCM_SCI_TDRE (1<<8) /* Transmit data register empty */ +#define QSMCM_SCI_TC (1<<7) /* Transmit complete */ +#define QSMCM_SCI_RDRF (1<<6) /* Receive data register full */ +#define QSMCM_SCI_RAF (1<<5) /* Receiver active flag */ +#define QSMCM_SCI_IDLE (1<<4) /* Idle line detected */ +#define QSMCM_SCI_OR (1<<3) /* Receiver overrun error */ +#define QSMCM_SCI_NF (1<<2) /* Receiver noise error flag */ +#define QSMCM_SCI_FE (1<<1) /* Receiver framing error */ +#define QSMCM_SCI_PF (1<<0) /* Receiver parity error */ + +/* + ************************************************************************* + * Unified System Interface Unit * + ************************************************************************* + */ + +/* + * Memory controller registers + */ +typedef struct m5xxMEMCRegisters_ { + uint32_t _br; + uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ +} m5xxMEMCRegisters_t; + +/* + * USIU itself + */ +typedef struct usiu_ { + /* + * SIU Block + */ + uint32_t siumcr; + uint32_t sypcr; + uint32_t _pad70; + uint16_t _pad0; + uint16_t swsr; + uint32_t sipend; + uint32_t simask; + uint32_t siel; + uint32_t sivec; + uint32_t tesr; + uint32_t sgpiodt1; + uint32_t sgpiodt2; + uint32_t sgpiocr; + uint32_t emcr; + uint8_t _pad71[0x03C-0x034]; + uint32_t pdmcr; + uint8_t _pad2[0x100-0x40]; + + /* + * MEMC Block + */ + m5xxMEMCRegisters_t memc[4]; + uint8_t _pad7[0x140-0x120]; + uint32_t dmbr; + uint32_t dmor; + uint8_t _pad8[0x178-0x148]; + uint16_t mstat; + uint8_t _pad9[0x200-0x17A]; + + /* + * System integration timers + */ + uint16_t tbscr; + uint16_t _pad10; + uint32_t tbreff0; + uint32_t tbreff1; + uint8_t _pad11[0x220-0x20c]; + uint16_t rtcsc; + uint16_t _pad12; + uint32_t rtc; + uint32_t rtsec; + uint32_t rtcal; + uint32_t _pad13[4]; + uint16_t piscr; + uint16_t _pad14; + uint16_t pitc; + uint16_t _pad_14_1; + uint16_t pitr; + uint16_t _pad_14_2; + uint8_t _pad15[0x280-0x24c]; + + /* + * Clocks and Reset + */ + uint32_t sccr; + uint32_t plprcr; + uint16_t rsr; + uint16_t _pad72; + uint16_t colir; + uint16_t _pad73; + uint16_t vsrmcr; + uint8_t _pad16[0x300-0x292]; + + /* + * System integration timers keys + */ + uint32_t tbscrk; + uint32_t tbreff0k; + uint32_t tbreff1k; + uint32_t tbk; + uint32_t _pad17[4]; + uint32_t rtcsk; + uint32_t rtck; + uint32_t rtseck; + uint32_t rtcalk; + uint32_t _pad18[4]; + uint32_t piscrk; + uint32_t pitck; + uint8_t _pad19[0x380-0x348]; + + /* + * Clocks and Reset Keys + */ + uint32_t sccrk; + uint32_t plprck; + uint32_t rsrk; + uint8_t _pad20[0x400-0x38c]; +} usiu_t; + +extern volatile usiu_t usiu; /* defined in linkcmds */ + +/* + ************************************************************************* + * Inter-Module Bus and Devices * + ************************************************************************* + */ + +/* + * Dual-Port TPU RAM (DPTRAM) + */ +typedef struct m5xxDPTRAMRegisters_ { + uint8_t pad[0x4000]; /* define later */ +} m5xxDPTRAMRegisters_t; + +/* + * Time Processor Unit (TPU) + */ +typedef struct m5xxTPU3Registers_ { + uint8_t pad[0x400]; /* define later */ +} m5xxTPU3Registers_t; + +/* + * Queued A/D Converter (QADC) + */ +typedef struct m5xxQADC64Registers_ { + uint8_t pad[0x400]; /* define later */ +} m5xxQADC64Registers_t; + +/* + * Serial Communications Interface (SCI) + */ +typedef struct m5xxSCIRegisters_ { + uint16_t sccr0; + uint16_t sccr1; + uint16_t scsr; + uint16_t scdr; +} m5xxSCIRegisters_t; + +/* + * Serial Peripheral Interface (SPI) + */ +typedef struct m5xxSPIRegisters_ { + uint16_t spcr0; + uint16_t spcr1; + uint16_t spcr2; + uint8_t spcr3; + uint8_t spsr; +} m5xxSPIRegisters_t; + +/* + * Queued Serial Multi-Channel Module (QSMCM) + */ +typedef struct m5xxQSMCMRegisters_ { + uint16_t qsmcmmcr; + uint16_t qtest; + uint16_t qdsci_il; + uint16_t qspi_il; + + m5xxSCIRegisters_t sci1; + + uint8_t _pad10[0x14-0x10]; + + uint16_t portqs; + uint16_t pqspar; + m5xxSPIRegisters_t spi; + + m5xxSCIRegisters_t sci2; + + uint16_t qsci1cr; + uint16_t qsci1sr; + uint16_t sctq[0x10]; + uint16_t scrq[0x10]; + + uint8_t _pad6C[0x140-0x06C]; + + uint16_t recram[0x20]; + uint16_t tranram[0x20]; + uint16_t comdram[0x20]; +} m5xxQSMCMRegisters_t; + +/* + * Modular Input/Output System (MIOS) + */ +typedef struct m5xxMIOS1Registers_ { + uint8_t pad[0x1000]; /* define later */ +} m5xxMIOS1Registers_t; + +/* + * Can 2.0B Controller (TouCAN) + */ +typedef struct m5xxTouCANRegisters_ { + uint8_t pad[0x400]; /* define later */ +} m5xxTouCANRegisters_t; + +/* + * U-Bus to IMB3 Bus Interface Module (UIMB) + */ +typedef struct m5xxUIMBRegisters_ { + uint32_t umcr; + uint32_t utstcreg; + uint32_t uipend; +} m5xxUIMBRegisters_t; + +/* + * IMB itself + */ +typedef struct imb_ { + m5xxDPTRAMRegisters_t dptram; + m5xxTPU3Registers_t tpu[2]; + m5xxQADC64Registers_t qadc[2]; + m5xxQSMCMRegisters_t qsmcm; + uint8_t _pad5200[0x6000-0x5200]; + m5xxMIOS1Registers_t mios; + m5xxTouCANRegisters_t toucan[2]; + uint8_t _pad7800[0x7F80-0x7800]; + m5xxUIMBRegisters_t uimb; +} imb_t; + +extern volatile imb_t imb; /* defined in linkcmds */ + + +/* + * Methods shared across libcpu and the BSP. + */ +void clockOn(void* unused); +void clockOff(void* unused); +int clockIsOn(void* unused); +rtems_isr Clock_isr(rtems_vector_number vector); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _MPC5XX_H */ diff --git a/bsps/powerpc/include/mpc5xx/console.h b/bsps/powerpc/include/mpc5xx/console.h new file mode 100644 index 0000000000..c0633af938 --- /dev/null +++ b/bsps/powerpc/include/mpc5xx/console.h @@ -0,0 +1,34 @@ +/* + * Console declarations + * + * + * MPC5xx port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC5XX_CONSOLE_H +#define _MPC5XX_CONSOLE_H + +#include <rtems/libio.h> +#include <rtems/termiostypes.h> + +void m5xx_uart_initialize(int minor); + +/* Termios callbacks */ +int m5xx_uart_firstOpen(int maj, int min, void *arg); +int m5xx_uart_lastClose(int maj, int min, void *arg); +int m5xx_uart_pollRead(int minor); +ssize_t m5xx_uart_pollWrite(int minor, const char* buf, size_t len); +ssize_t m5xx_uart_write (int minor, const char *buf, size_t len); +int m5xx_uart_setAttributes(int, const struct termios* t); + +#define NUM_PORTS 2 /* number of serial ports */ + +#define SCI1_MINOR 0 +#define SCI2_MINOR 1 + +#endif /* _MPC5XX_CONSOLE_H */ diff --git a/bsps/powerpc/include/mpc8260.h b/bsps/powerpc/include/mpc8260.h new file mode 100644 index 0000000000..ea088ebae8 --- /dev/null +++ b/bsps/powerpc/include/mpc8260.h @@ -0,0 +1,1510 @@ +/* buggy version of CPU */ +#define REV_0_2 + +/* +************************************************************************** +************************************************************************** +** ** +** MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER ** +** POWERQUICC II ** +** ** +** HARDWARE DECLARATIONS ** +** ** +** ** +** Submitted by: ** +** Andy Dachs ** ** +** Surrey Satellite Technology Limited ** ** +** http://www.sstl.co.uk ** ** +** a.dachs@sstl.co.uk ** ** +** ** +** Based on previous submissions for other PPC variants by: ** +** ** +** Submitted By: ** +** ** +** W. Eric Norum ** +** Saskatchewan Accelerator Laboratory ** +** University of Saskatchewan ** +** 107 North Road ** +** Saskatoon, Saskatchewan, CANADA ** +** S7N 5C6 ** +** ** +** eric@skatter.usask.ca ** +** ** +** Modified for use with the MPC860 (original code was for MC68360) ** +** by ** +** Jay Monkman ** +** Frasca International, Inc. ** +** 906 E. Airport Rd. ** +** Urbana, IL, 61801 ** +** ** +** jmonkman@frasca.com ** +** ** +** ** +************************************************************************** +************************************************************************** +*/ + +#ifndef _MPC8260_H +#define _MPC8260_H + +#ifndef ASM +/* + Macros for SPRs +*/ + + + + +/* +************************************************************************* +* REGISTER SUBBLOCKS * +************************************************************************* +*/ + + +/* + * Memory controller registers + */ +typedef struct m8260MEMCRegisters_ { + uint32_t br; + uint32_t _or; /* or is a C++ keyword :( */ +} m8260MEMCRegisters_t; + + +/* + * Fast Communication Controller Registers +*/ +typedef struct m8260FCCRegisters_ { + uint32_t gfmr; + uint32_t fpsmr; + uint16_t ftodr; + uint8_t fcc_pad0[2]; + uint16_t fdsr; + uint8_t fcc_pad1[2]; + uint32_t fcce; + uint32_t fccm; + uint8_t fccs; + uint8_t fcc_pad2[3]; + uint8_t ftirr_phy0; /* n/a on FCC3 */ + uint8_t ftirr_phy1; /* n/a on FCC3 */ + uint8_t ftirr_phy2; /* n/a on FCC3 */ + uint8_t ftirr_phy3; /* n/a on FCC3 */ +} m8260FCCRegisters_t; + + +/* + * Serial Communications Controller registers + */ +typedef struct m8260SCCRegisters_ { + uint32_t gsmr_l; + uint32_t gsmr_h; + uint16_t psmr; + uint8_t scc_pad0[2]; + uint16_t todr; + uint16_t dsr; + uint16_t scce; + uint8_t scc_pad2[2]; + uint16_t sccm; + uint8_t scc_pad3[1]; + uint8_t sccs; + uint8_t scc_pad1[8]; +} m8260SCCRegisters_t; + +/* + * Serial Management Controller registers + */ +typedef struct m8260SMCRegisters_ { + uint8_t smc_pad0[2]; + uint16_t smcmr; + uint8_t smc_pad2[2]; + uint8_t smce; + uint8_t smc_pad3[3]; + uint8_t smcm; + uint8_t smc_pad1[5]; +} m8260SMCRegisters_t; + + +/* + * Serial Interface With Time Slot Assigner Registers + */ +typedef struct m8260SIRegisters_ { + uint16_t siamr; + uint16_t sibmr; + uint16_t sicmr; + uint16_t sidmr; + uint8_t sigmr; + uint8_t si_pad0[1]; + uint8_t sicmdr; + uint8_t si_pad1[1]; + uint8_t sistr; + uint8_t si_pad2[1]; + uint16_t sirsr; +} m8260SIRegisters_t; + + +/* + * Multi Channel Controller registers + */ +typedef struct m8260MCCRegisters_ { + uint16_t mcce; + uint8_t mcc_pad2[2]; + uint16_t mccm; + uint16_t mcc_pad0; + uint8_t mccf; + uint8_t mcc_pad1[7]; +} m8260MCCRegisters_t; + + +/* +************************************************************************* +* RISC Timers * +************************************************************************* +*/ +/* +typedef struct m8260TimerParms_ { + uint16_t tm_base; + uint16_t _tm_ptr; + uint16_t _r_tmr; + uint16_t _r_tmv; + uint32_t tm_cmd; + uint32_t tm_cnt; +} m8260TimerParms_t; +*/ + +/* + * RISC Controller Configuration Register (RCCR) + * All other bits in this register are reserved. + */ +#define M8260_RCCR_TIME (1<<31) /* Enable timer */ +#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */ +#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */ +#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */ +#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */ +#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */ +#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */ +#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */ +#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */ +#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */ +#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */ +#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */ +#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */ +#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */ +#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */ +#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */ +#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */ +#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */ +#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */ + + + +/* + * Command register + * Set up this register before issuing a M8260_CR_OP_SET_TIMER command. + */ +#if 0 +#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */ +#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */ +#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */ +#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ +#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ +#endif + +/* +************************************************************************* +* DMA Controllers * +************************************************************************* +*/ +typedef struct m8260IDMAparms_ { + uint16_t ibase; + uint16_t dcm; + uint16_t ibdptr; + uint16_t dpr_buf; + uint16_t _buf_inv; + uint16_t ssmax; + uint16_t _dpr_in_ptr; + uint16_t sts; + uint16_t _dpr_out_ptr; + uint16_t seob; + uint16_t deob; + uint16_t dts; + uint16_t _ret_add; + uint16_t reserved; + uint32_t _bd_cnt; + uint32_t _s_ptr; + uint32_t _d_ptr; + uint32_t istate; +} m8260IDMAparms_t; + + +/* +************************************************************************* +* Serial Communication Controllers * +************************************************************************* +*/ + + +typedef struct m8260SCCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + uint32_t _rcrc; + uint32_t _tcrc; + union { + struct { + uint32_t _res0; + uint32_t _res1; + uint16_t max_idl; + uint16_t idlc; + uint16_t brkcr; + uint16_t parec; + uint16_t frmec; + uint16_t nosec; + uint16_t brkec; + uint16_t brklen; + uint16_t uaddr[2]; + uint16_t rtemp; + uint16_t toseq; + uint16_t character[8]; + uint16_t rccm; + uint16_t rccr; + uint16_t rlbc; + } uart; + struct { + uint32_t _pad0; + uint32_t c_mask; + uint32_t c_pres; + uint16_t disfc; + uint16_t crcec; + uint16_t abtsc; + uint16_t nmarc; + uint16_t retrc; + uint16_t mflr; + uint16_t _max_cnt; + uint16_t rfthr; + uint16_t _rfcnt; + uint16_t hmask; + uint16_t haddr1; + uint16_t haddr2; + uint16_t haddr3; + uint16_t haddr4; + uint16_t _tmp; + uint16_t _tmp_mb; + } hdlc; + struct { + uint32_t _pad0; + uint32_t crcc; + uint16_t prcrc; + uint16_t ptcrc; + uint16_t parec; + uint16_t bsync; + uint16_t bdle; + uint16_t character[8]; + uint16_t rccm; + } bisync; + struct { + uint32_t _crc_p; + uint32_t _crc_c; + } transparent; + struct { + uint32_t c_pres; + uint32_t c_mask; + uint32_t crcec; + uint32_t alec; + uint32_t disfc; + uint16_t pads; + uint16_t ret_lim; + uint16_t _ret_cnt; + uint16_t mflr; + uint16_t minflr; + uint16_t maxd1; + uint16_t maxd2; + uint16_t _maxd; + uint16_t _dma_cnt; + uint16_t _max_b; + uint16_t gaddr1; + uint16_t gaddr2; + uint16_t gaddr3; + uint16_t gaddr4; + uint32_t _tbuf0data0; + uint32_t _tbuf0data1; + uint32_t _tbuf0rba0; + uint32_t _tbuf0crc; + uint16_t _tbuf0bcnt; + uint16_t paddr_h; + uint16_t paddr_m; + uint16_t paddr_l; + uint16_t p_per; + uint16_t _rfbd_ptr; + uint16_t _tfbd_ptr; + uint16_t _tlbd_ptr; + uint32_t _tbuf1data0; + uint32_t _tbuf1data1; + uint32_t _tbuf1rba0; + uint32_t _tbuf1crc; + uint16_t _tbuf1bcnt; + uint16_t _tx_len; + uint16_t iaddr1; + uint16_t iaddr2; + uint16_t iaddr3; + uint16_t iaddr4; + uint16_t _boff_cnt; + uint16_t taddr_l; + uint16_t taddr_m; + uint16_t taddr_h; + } ethernet; + } un; +} m8260SCCparms_t; + + +/* + * Event and mask registers (SCCE, SCCM) + */ +#define M8260_SCCE_BRKE (1<<6) +#define M8260_SCCE_BRK (1<<5) +#define M8260_SCCE_TXE (1<<4) +#define M8260_SCCE_RXF (1<<3) +#define M8260_SCCE_BSY (1<<2) +#define M8260_SCCE_TX (1<<1) +#define M8260_SCCE_RX (1<<0) + + +/* +************************************************************************* +* Fast Serial Communication Controllers * +************************************************************************* +*/ + + +typedef struct m8260FCCparms_ { + uint16_t riptr; + uint16_t tiptr; + uint16_t _pad0; + uint16_t mrblr; + uint32_t rstate; + uint32_t rbase; + uint16_t _rbdstat; + uint16_t _rbdlen; + uint32_t _rdptr; + uint32_t tstate; + uint32_t tbase; + uint16_t _tbdstat; + uint16_t _tbdlen; + uint32_t _tdptr; + uint32_t _rbptr; + uint32_t _tbptr; + uint32_t _rcrc; + uint32_t _pad1; + uint32_t _tcrc; + + union { + struct { + uint32_t _pad0; + uint32_t _pad1; + uint32_t c_mask; + uint32_t c_pres; + uint16_t disfc; + uint16_t crcec; + uint16_t abtsc; + uint16_t nmarc; + uint32_t _max_cnt; + uint16_t mflr; + uint16_t rfthr; + uint16_t rfcnt; + uint16_t hmask; + uint16_t haddr1; + uint16_t haddr2; + uint16_t haddr3; + uint16_t haddr4; + uint16_t _ts_tmp; + uint16_t _tmp_mb; + } hdlc; + struct { + uint32_t _pad0; + uint32_t _pad1; + uint32_t c_mask; + uint32_t c_pres; + uint16_t disfc; + uint16_t crcec; + uint16_t abtsc; + uint16_t nmarc; + uint32_t _max_cnt; + uint16_t mflr; + uint16_t rfthr; + uint16_t rfcnt; + uint16_t hmask; + uint16_t haddr1; + uint16_t haddr2; + uint16_t haddr3; + uint16_t haddr4; + uint16_t _ts_tmp; + uint16_t _tmp_mb; + } transparent; + struct { + uint32_t _stat_buf; + uint32_t cam_ptr; + uint32_t c_mask; + uint32_t c_pres; + uint32_t crcec; + uint32_t alec; + uint32_t disfc; + uint16_t ret_lim; + uint16_t _ret_cnt; + uint16_t p_per; + uint16_t _boff_cnt; + uint32_t gaddr_h; + uint32_t gaddr_l; + uint16_t tfcstat; + uint16_t tfclen; + uint32_t tfcptr; + uint16_t mflr; + uint16_t paddr1_h; + uint16_t paddr1_m; + uint16_t paddr1_l; + uint16_t _ibd_cnt; + uint16_t _ibd_start; + uint16_t _ibd_end; + uint16_t _tx_len; + uint16_t _ibd_base; + uint32_t iaddr_h; + uint32_t iaddr_l; + uint16_t minflr; + uint16_t taddr_h; + uint16_t taddr_m; + uint16_t taddr_l; + uint16_t pad_ptr; + uint16_t _pad0; + uint16_t _cf_range; + uint16_t _max_b; + uint16_t maxd1; + uint16_t maxd2; + uint16_t _maxd; + uint16_t _dma_cnt; + uint32_t octc; + uint32_t colc; + uint32_t broc; + uint32_t mulc; + uint32_t uspc; + uint32_t frgc; + uint32_t ospc; + uint32_t jbrc; + uint32_t p64c; + uint32_t p65c; + uint32_t p128c; + uint32_t p256c; + uint32_t p512c; + uint32_t p1024c; + uint32_t _cam_buf; + uint32_t _pad1; + } ethernet; + } un; +} m8260FCCparms_t; + + +/* + * Receive and transmit function code register bits + * These apply to the function code registers of all devices, not just SCC. + */ +#define M8260_RFCR_BO(x) ((x)<<3) +#define M8260_RFCR_MOT (2<<3) +#define M8260_RFCR_LOCAL_BUS (2) +#define M8260_RFCR_60X_BUS (0) +#define M8260_TFCR_BO(x) ((x)<<3) +#define M8260_TFCR_MOT (2<<3) +#define M8260_TFCR_LOCAL_BUS (2) +#define M8260_TFCR_60X_BUS (0) + +/* +************************************************************************* +* Serial Management Controllers * +************************************************************************* +*/ +typedef struct m8260SMCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + union { + struct { + uint16_t max_idl; + uint16_t _idlc; + uint16_t _brkln; + uint16_t brkec; + uint16_t brkcr; + uint16_t _r_mask; + } uart; + struct { + uint16_t _pad0[6]; + } transparent; + } un; + uint32_t _pad6; +} m8260SMCparms_t; + +/* + * Mode register + */ +#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */ +#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */ +#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */ +#define M8260_SMCMR_EVEN (1<<8) /* Even parity */ +#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */ +#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */ +#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ +#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ +#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */ +#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */ +#define M8260_SMCMR_REN (1<<0) /* Enable receiver */ + +/* + * Event and mask registers (SMCE, SMCM) + */ +#define M8260_SMCE_TXE (1<<4) +#define M8260_SMCE_BSY (1<<2) +#define M8260_SMCE_TX (1<<1) +#define M8260_SMCE_RX (1<<0) + +/* +************************************************************************* +* Serial Peripheral Interface * +************************************************************************* +*/ +typedef struct m8260SPIparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; +} m8260SPIparms_t; + +/* + * Mode register (SPMODE) + */ +#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */ +#define M8260_SPMODE_CI (1<<13) /* Clock invert */ +#define M8260_SPMODE_CP (1<<12) /* Clock phase */ +#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ +#define M8260_SPMODE_REV (1<<10) /* Reverse data */ +#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */ +#define M8260_SPMODE_EN (1<<8) /* Enable SPI */ +#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */ +#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */ + +/* + * Mode register (SPCOM) + */ +#define M8260_SPCOM_STR (1<<7) /* Start transmit */ + +/* + * Event and mask registers (SPIE, SPIM) + */ +#define M8260_SPIE_MME (1<<5) /* Multi-master error */ +#define M8260_SPIE_TXE (1<<4) /* Tx error */ +#define M8260_SPIE_BSY (1<<2) /* Busy condition*/ +#define M8260_SPIE_TXB (1<<1) /* Tx buffer */ +#define M8260_SPIE_RXB (1<<0) /* Rx buffer */ + +/* +************************************************************************* +* SDMA (SCC, SMC, SPI) Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8260BufferDescriptor_ { + uint16_t status; + uint16_t length; + volatile void *buffer; +} m8260BufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8260_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8260_BD_MISS (1<<8) /* Ethernet */ +#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ +#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ +#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8260_BD_SHORT (1<<3) /* Ethernet */ +#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8260_BD_ABORT (1<<3) /* SCC HDLC */ +#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ +#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_COLLISION (1<<0) /* Ethernet */ +#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */ + +#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8xx_BD_MISS (1<<8) /* Ethernet */ +#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ +#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ +#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8xx_BD_SHORT (1<<3) /* Ethernet */ +#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */ +#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ +#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_PAD (1<<14) /* Ethernet */ +#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8260_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8260_BD_DEFER (1<<9) /* Ethernet */ +#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ +#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ + +#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_PAD (1<<14) /* Ethernet */ +#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8xx_BD_DEFER (1<<9) /* Ethernet */ +#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ + +/* +************************************************************************* +* IDMA Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8260IDMABufferDescriptor_ { + uint16_t status; + uint8_t dfcr; + uint8_t sfcr; + uint32_t length; + void *source; + void *destination; +} m8260IDMABufferDescriptor_t; + +/* +************************************************************************* +* RISC Communication Processor Module Command Register (CR) * +************************************************************************* +*/ +#define M8260_CR_RST (1<<31) /* Reset communication processor */ + +#define M8260_CR_FCC1 ((4<<26)|(16<<21)) /* FCC1 page and code */ +#define M8260_CR_FCC1_ATM ((4<<26)|(14<<21)) /* FCC1 ATM mode page and code */ +#define M8260_CR_FCC2 ((5<<26)|(17<<21)) /* FCC2 page and code */ +#define M8260_CR_FCC2_ATM ((5<<26)|(14<<21)) /* FCC2 ATM mode page and code */ +#define M8260_CR_FCC3 ((6<<26)|(18<<21)) /* FCC3 page and code */ +#define M8260_CR_SCC1 ((0<<26)|(4<<21)) /* SCC1 page and code */ +#define M8260_CR_SCC2 ((1<<26)|(5<<21)) /* SCC2 page and code */ +#define M8260_CR_SCC3 ((2<<26)|(6<<21)) /* SCC3 page and code */ +#define M8260_CR_SCC4 ((3<<26)|(7<<21)) /* SCC4 page and code */ +#define M8260_CR_SMC1 ((7<<26)|(8<<21)) /* SMC1 page and code */ +#define M8260_CR_SMC2 ((8<<26)|(9<<21)) /* SMC2 page and code */ +#define M8260_CR_RAND ((10<<26)|(14<<21)) /* SMC2 page and code */ +#define M8260_CR_SPI ((9<<26)|(10<<21)) /* SPI page and code */ +#define M8260_CR_I2C ((10<<26)|(11<<21)) /* I2C page and code */ +#define M8260_CR_TMR ((10<<26)|(15<<21)) /* Timer page and code */ +#define M8260_CR_MCC1 ((7<<26)|(28<<21)) /* MCC1 page and code */ +#define M8260_CR_MCC2 ((8<<26)|(29<<21)) /* MCC2 page and code */ +#define M8260_CR_IDMA1 ((7<<26)|(20<<21)) /* IDMA1 page and code */ +#define M8260_CR_IDMA2 ((8<<26)|(21<<21)) /* IDMA2 page and code */ +#define M8260_CR_IDMA3 ((9<<26)|(22<<21)) /* IDMA3 page and code */ +#define M8260_CR_IDMA4 ((10<<26)|(23<<21)) /* IDMA4 page and code */ + +#define M8260_CR_FLG (1<<16) /* Command sempahore flag */ + +#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */ +#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */ +#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */ +#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */ + +#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */ +#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */ +#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */ +#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */ +#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */ +#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */ +#define M8260_CR_OP_SET_TIMER (8) /* Timer */ +#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */ +#define M8260_CR_OP_START_IDMA (9) /* IDMA */ +#define M8260_CR_OP_STOP_RX (9) /* MCC */ +#define M8260_CR_OP_ATM_TX (10) /* FCC */ +#define M8260_CR_OP_RESET_BCS (10) /* SCC */ +#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */ +#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */ +#define M8260_CR_OP_RANDOM (12) /* RAND */ + +/* +************************************************************************* +* System Protection Control Register (SYPCR) * +************************************************************************* +*/ +#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* Memory Control Registers * +************************************************************************* +*/ +#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */ +#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */ +#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */ +#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */ +#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */ +#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */ +#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ +#define M8260_MSR_WPER (1<<7) /* Write protection error */ +#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ +#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */ +#define M8260_BR_AT(x) ((x)<<12) /* Address type */ +#define M8260_BR_PS8 (1<<10) /* 8 bit port */ +#define M8260_BR_PS16 (2<<10) /* 16 bit port */ +#define M8260_BR_PS32 (0<<10) /* 32 bit port */ +#define M8260_BR_PARE (1<<9) /* Parity checking enable */ +#define M8260_BR_WP (1<<8) /* Write protect */ +#define M8260_BR_MS_GPCM (0<<6) /* GPCM */ +#define M8260_BR_MS_UPMA (2<<6) /* UPM A */ +#define M8260_BR_MS_UPMB (3<<6) /* UPM B */ +#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */ +#define M8260_MEMC_OR_64K 0xffff0000 +#define M8260_MEMC_OR_128K 0xfffe0000 +#define M8260_MEMC_OR_256K 0xfffc0000 +#define M8260_MEMC_OR_512K 0xfff80000 +#define M8260_MEMC_OR_1M 0xfff00000 +#define M8260_MEMC_OR_2M 0xffe00000 +#define M8260_MEMC_OR_4M 0xffc00000 +#define M8260_MEMC_OR_8M 0xff800000 +#define M8260_MEMC_OR_16M 0xff000000 +#define M8260_MEMC_OR_32M 0xfe000000 +#define M8260_MEMC_OR_64M 0xfc000000 +#define M8260_MEMC_OR_128 0xf8000000 +#define M8260_MEMC_OR_256M 0xf0000000 +#define M8260_MEMC_OR_512M 0xe0000000 +#define M8260_MEMC_OR_1G 0xc0000000 +#define M8260_MEMC_OR_2G 0x80000000 +#define M8260_MEMC_OR_4G 0x00000000 +#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ +#define M8260_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define M8260_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */ +#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define M8260_MEMC_OR_SETA (1<<3) /* *TA generated externally */ +#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ +#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ + +/* +************************************************************************* +* UPM Registers (MxMR) * +************************************************************************* +*/ +#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ +#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ +#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ +#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ +#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ +#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ +#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ +#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ +/* +************************************************************************* +* Memory Command Register (MCR) * +************************************************************************* +*/ +#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */ +#define M8260_MEMC_MCR_READ (1<<30) /* READ command */ +#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */ +#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ +#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ +#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ +#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ +#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */ + + + +/* +************************************************************************* +* SI Mode Register (SIMODE) * +************************************************************************* +*/ +#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ +#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ +#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ +#define M8260_SI_SMC2_BRG2 (1<<28) +#define M8260_SI_SMC2_BRG3 (2<<28) +#define M8260_SI_SMC2_BRG4 (3<<28) +#define M8260_SI_SMC2_CLK5 (0<<28) +#define M8260_SI_SMC2_CLK6 (1<<28) +#define M8260_SI_SMC2_CLK7 (2<<28) +#define M8260_SI_SMC2_CLK8 (3<<28) +#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ +#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ +#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ +#define M8260_SI_SMC1_BRG2 (1<<12) +#define M8260_SI_SMC1_BRG3 (2<<12) +#define M8260_SI_SMC1_BRG4 (3<<12) +#define M8260_SI_SMC1_CLK1 (0<<12) +#define M8260_SI_SMC1_CLK2 (1<<12) +#define M8260_SI_SMC1_CLK3 (2<<12) +#define M8260_SI_SMC1_CLK4 (3<<12) + +/* +************************************************************************* +* SDMA Configuration Register (SDCR) * +************************************************************************* +*/ +#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ +#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ + +/* +************************************************************************* +* SDMA Status Register (SDSR) * +************************************************************************* +*/ +#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */ +#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ +#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ + +/* +************************************************************************* +* Baud (sic) Rate Generators * +************************************************************************* +*/ +#define M8260_BRG_RST (1<<17) /* Reset generator */ +#define M8260_BRG_EN (1<<16) /* Enable generator */ +#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ +#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ +#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ +#define M8260_BRG_ATB (1<<13) /* Autobaud */ +#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */ +#define M8260_BRG_57600 (32<<1) +#define M8260_BRG_38400 (64<<1) +#define M8260_BRG_19200 (129<<1) +#define M8260_BRG_9600 (259<<1) +#define M8260_BRG_4800 (520<<1) +#define M8260_BRG_2400 (1040<<1) +#define M8260_BRG_1200 (2082<<1) +#define M8260_BRG_600 ((259<<1) | 1) +#define M8260_BRG_300 ((520<<1) | 1) +#define M8260_BRG_150 ((1040<<1) | 1) +#define M8260_BRG_75 ((2080<<1) | 1) + +#define M8xx_BRG_RST (1<<17) /* Reset generator */ +#define M8xx_BRG_EN (1<<16) /* Enable generator */ +#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ + +#define M8260_BRG1 (1<<7) +#define M8260_BRG2 (1<<6) +#define M8260_BRG3 (1<<5) +#define M8260_BRG4 (1<<4) +#define M8260_BRG5 (1<<3) +#define M8260_BRG6 (1<<2) +#define M8260_BRG7 (1<<1) +#define M8260_BRG8 (1<<0) + + + +#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ +#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ +#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_STP1 (1<<1) /* Stop timer */ +#define M8260_TGCR_STP2 (1<<5) /* Stop timer */ +#define M8260_TGCR_STP3 (1<<9) /* Stop timer */ +#define M8260_TGCR_STP4 (1<<13) /* Stop timer */ +#define M8260_TGCR_RST1 (1<<0) /* Enable timer */ +#define M8260_TGCR_RST2 (1<<4) /* Enable timer */ +#define M8260_TGCR_RST3 (1<<8) /* Enable timer */ +#define M8260_TGCR_RST4 (1<<12) /* Enable timer */ +#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ +#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ + +#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */ +#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */ +#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */ +#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */ +#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ +#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */ +#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */ +#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ +#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ +#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ +#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */ + +#ifdef REV_0_2 +#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */ +#else +#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */ +#endif +#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */ +#define M8260_PISCR_PTE (1<<0) /* PIT enable */ + +#if 0 +#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */ +#endif + +#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */ +#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */ +#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */ +#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */ +#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */ +#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */ + +#define M8260_SIMASK_PC0 (1<<31) +#define M8260_SIMASK_PC1 (1<<30) +#define M8260_SIMASK_PC2 (1<<29) +#define M8260_SIMASK_PC3 (1<<28) +#define M8260_SIMASK_PC4 (1<<27) +#define M8260_SIMASK_PC5 (1<<26) +#define M8260_SIMASK_PC6 (1<<25) +#define M8260_SIMASK_PC7 (1<<24) +#define M8260_SIMASK_PC8 (1<<23) +#define M8260_SIMASK_PC9 (1<<22) +#define M8260_SIMASK_PC10 (1<<21) +#define M8260_SIMASK_PC11 (1<<20) +#define M8260_SIMASK_PC12 (1<<19) +#define M8260_SIMASK_PC13 (1<<18) +#define M8260_SIMASK_PC14 (1<<17) +#define M8260_SIMASK_PC15 (1<<16) +#define M8260_SIMASK_IRQ1 (1<<14) +#define M8260_SIMASK_IRQ2 (1<<13) +#define M8260_SIMASK_IRQ3 (1<<12) +#define M8260_SIMASK_IRQ4 (1<<11) +#define M8260_SIMASK_IRQ5 (1<<10) +#define M8260_SIMASK_IRQ6 (1<<9) +#define M8260_SIMASK_IRQ7 (1<<8) +#define M8260_SIMASK_TMCNT (1<<2) +#define M8260_SIMASK_PIT (1<<1) + +#define M8260_SIMASK_FCC1 (1<<31) +#define M8260_SIMASK_FCC2 (1<<30) +#define M8260_SIMASK_FCC3 (1<<29) +#define M8260_SIMASK_MCC1 (1<<27) +#define M8260_SIMASK_MCC2 (1<<26) +#define M8260_SIMASK_SCC1 (1<<23) +#define M8260_SIMASK_SCC2 (1<<22) +#define M8260_SIMASK_SCC3 (1<<21) +#define M8260_SIMASK_SCC4 (1<<20) +#define M8260_SIMASK_I2C (1<<15) +#define M8260_SIMASK_SPI (1<<14) +#define M8260_SIMASK_RTT (1<<13) +#define M8260_SIMASK_SMC1 (1<<12) +#define M8260_SIMASK_SMC2 (1<<11) +#define M8260_SIMASK_IDMA1 (1<<10) +#define M8260_SIMASK_IDMA2 (1<<9) +#define M8260_SIMASK_IDMA3 (1<<8) +#define M8260_SIMASK_IDMA4 (1<<7) +#define M8260_SIMASK_SDMA (1<<6) +#define M8260_SIMASK_TIMER1 (1<<4) +#define M8260_SIMASK_TIMER2 (1<<3) +#define M8260_SIMASK_TIMER3 (1<<2) +#define M8260_SIMASK_TIMER4 (1<<1) + +#define M8260_SIUMCR_EARB (1<<31) +#define M8260_SIUMCR_EARP0 (0<<28) +#define M8260_SIUMCR_EARP1 (1<<28) +#define M8260_SIUMCR_EARP2 (2<<28) +#define M8260_SIUMCR_EARP3 (3<<28) +#define M8260_SIUMCR_EARP4 (4<<28) +#define M8260_SIUMCR_EARP5 (5<<28) +#define M8260_SIUMCR_EARP6 (6<<28) +#define M8260_SIUMCR_EARP7 (7<<28) +#define M8260_SIUMCR_DSHW (1<<23) +#define M8260_SIUMCR_DBGC0 (0<<21) +#define M8260_SIUMCR_DBGC1 (1<<21) +#define M8260_SIUMCR_DBGC2 (2<<21) +#define M8260_SIUMCR_DBGC3 (3<<21) +#define M8260_SIUMCR_DBPC0 (0<<19) +#define M8260_SIUMCR_DBPC1 (1<<19) +#define M8260_SIUMCR_DBPC2 (2<<19) +#define M8260_SIUMCR_DBPC3 (3<<19) +#define M8260_SIUMCR_FRC (1<<17) +#define M8260_SIUMCR_DLK (1<<16) +#define M8260_SIUMCR_PNCS (1<<15) +#define M8260_SIUMCR_OPAR (1<<14) +#define M8260_SIUMCR_DPC (1<<13) +#define M8260_SIUMCR_MPRE (1<<12) +#define M8260_SIUMCR_MLRC0 (0<<10) +#define M8260_SIUMCR_MLRC1 (1<<10) +#define M8260_SIUMCR_MLRC2 (2<<10) +#define M8260_SIUMCR_MLRC3 (3<<10) +#define M8260_SIUMCR_AEME (1<<9) +#define M8260_SIUMCR_SEME (1<<8) +#define M8260_SIUMCR_BSC (1<<7) +#define M8260_SIUMCR_GB5E (1<<6) +#define M8260_SIUMCR_B2DD (1<<5) +#define M8260_SIUMCR_B3DD (1<<4) + +/* +************************************************************************* +* MPC8260 DUAL-PORT RAM AND REGISTERS * +************************************************************************* +*/ +typedef struct m8260_ { + + /* + * CPM Dual-Port RAM + */ + uint8_t dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */ + uint8_t cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */ + + m8260SCCparms_t scc1p; + uint8_t pad_scc1[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc2p; + uint8_t pad_scc2[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc3p; + uint8_t pad_scc3[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc4p; + uint8_t pad_scc4[256-sizeof(m8260SCCparms_t)]; + + m8260FCCparms_t fcc1p; + uint8_t pad_fcc1[256-sizeof(m8260FCCparms_t)]; + m8260FCCparms_t fcc2p; + uint8_t pad_fcc2[256-sizeof(m8260FCCparms_t)]; + m8260FCCparms_t fcc3p; + uint8_t pad_fcc3[256-sizeof(m8260FCCparms_t)]; + + uint8_t mcc1p[128]; + uint8_t pad_mcc1[124]; + uint16_t smc1_base; + uint16_t idma1_base; + uint8_t mcc2p[128]; + uint8_t pad_mcc2[124]; + uint16_t smc2_base; + uint16_t idma2_base; + uint8_t pad_spi[252]; + uint16_t spi_base; + uint16_t idma3_base; + uint8_t pad_risc[224]; + uint8_t risc_timers[16]; + uint16_t rev_num; + uint16_t cpm_pad7; + uint32_t cpm_pad8; + uint16_t rand; + uint16_t i2c_base; + uint16_t idma4_base; + uint8_t cpm_pad9[1282]; + + uint8_t cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */ + + m8260SMCparms_t smc1p; + m8260SMCparms_t smc2p; + uint8_t dpram3[4096-2*sizeof(m8260SMCparms_t)]; + + uint8_t cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */ + + + /* + * General SIU Block + */ + uint32_t siumcr; + uint32_t sypcr; + uint8_t siu_pad0[6]; + uint16_t swsr; + uint8_t siu_pad1[20]; + uint32_t bcr; + uint8_t ppc_acr; + uint8_t siu_pad4[3]; + uint32_t ppc_alrh; + uint32_t ppc_alr1; + uint8_t lcl_acr; + uint8_t siu_pad5[3]; + uint32_t lcl_alrh; + uint32_t lcl_alr1; + uint32_t tescr1; + uint32_t tescr2; + uint32_t l_tescr1; + uint32_t l_tescr2; + uint32_t pdtea; + uint8_t pdtem; + uint8_t siu_pad2[3]; + uint32_t ldtea; + uint8_t ldtem; + uint8_t siu_pad3[163]; + + + /* + * Memory Controller Block + */ + m8260MEMCRegisters_t memc[12]; + uint8_t mem_pad0[8]; + uint32_t mar; + uint8_t mem_pad1[4]; + uint32_t mamr; + uint32_t mbmr; + uint32_t mcmr; + uint32_t mdmr; + uint8_t mem_pad2[4]; + uint16_t mptpr; + uint8_t mem_pad5[2]; + uint32_t mdr; + uint8_t mem_pad3[4]; + uint32_t psdmr; + uint32_t lsdmr; + uint8_t purt; + uint8_t mem_pad6[3]; + uint8_t psrt; + uint8_t mem_pad7[3]; + uint8_t lurt; + uint8_t mem_pad8[3]; + uint8_t lsrt; + uint8_t mem_pad9[3]; + uint32_t immr; + uint8_t mem_pad4[84]; + + + /* + * System integration timers + */ + uint8_t sit_pad0[32]; + uint16_t tmcntsc; + uint8_t sit_pad6[2]; + uint32_t tmcnt; + uint32_t tmcntsec; + uint32_t tmcntal; + uint8_t sit_pad2[16]; + uint16_t piscr; + uint8_t sit_pad5[2]; + uint32_t pitc; + uint32_t pitr; + uint8_t sit_pad3[94]; + uint8_t sit_pad4[2390]; + + + /* + * Interrupt Controller + */ + uint16_t sicr; + uint8_t ict_pad1[2]; + uint32_t sivec; + uint32_t sipnr_h; + uint32_t sipnr_l; + uint32_t siprr; + uint32_t scprr_h; + uint32_t scprr_l; + uint32_t simr_h; + uint32_t simr_l; + uint32_t siexr; + uint8_t ict_pad0[88]; + + + /* + * Clocks and Reset + */ + uint32_t sccr; + uint8_t clr_pad1[4]; + uint32_t scmr; + uint8_t clr_pad2[4]; + uint32_t rsr; + uint32_t rmr; + uint8_t clr_pad0[104]; + + + /* + * Input/ Output Port + */ + uint32_t pdira; + uint32_t ppara; + uint32_t psora; + uint32_t podra; + uint32_t pdata; + uint8_t iop_pad0[12]; + uint32_t pdirb; + uint32_t pparb; + uint32_t psorb; + uint32_t podrb; + uint32_t pdatb; + uint8_t iop_pad1[12]; + uint32_t pdirc; + uint32_t pparc; + uint32_t psorc; + uint32_t podrc; + uint32_t pdatc; + uint8_t iop_pad2[12]; + uint32_t pdird; + uint32_t ppard; + uint32_t psord; + uint32_t podrd; + uint32_t pdatd; + uint8_t iop_pad3[12]; + + + /* + * CPM Timers + */ + uint8_t tgcr1; + uint8_t cpt_pad0[3]; + uint8_t tgcr2; + uint8_t cpt_pad1[11]; + uint16_t tmr1; + uint16_t tmr2; + uint16_t trr1; + uint16_t trr2; + uint16_t tcr1; + uint16_t tcr2; + uint16_t tcn1; + uint16_t tcn2; + uint16_t tmr3; + uint16_t tmr4; + uint16_t trr3; + uint16_t trr4; + uint16_t tcr3; + uint16_t tcr4; + uint16_t tcn3; + uint16_t tcn4; + uint16_t ter1; + uint16_t ter2; + uint16_t ter3; + uint16_t ter4; + uint8_t cpt_pad2[608]; + + + /* + * DMA Block + */ + uint8_t sdsr; + uint8_t dma_pad0[3]; + uint8_t sdmr; + uint8_t dma_pad1[3]; + + uint8_t idsr1; + uint8_t dma_pad2[3]; + uint8_t idmr1; + uint8_t dma_pad3[3]; + uint8_t idsr2; + uint8_t dma_pad4[3]; + uint8_t idmr2; + uint8_t dma_pad5[3]; + uint8_t idsr3; + uint8_t dma_pad6[3]; + uint8_t idmr3; + uint8_t dma_pad7[3]; + uint8_t idsr4; + uint8_t dma_pad8[3]; + uint8_t idmr4; + uint8_t dma_pad9[707]; + + + /* + * FCC Block + */ + m8260FCCRegisters_t fcc1; + m8260FCCRegisters_t fcc2; + m8260FCCRegisters_t fcc3; + + uint8_t fcc_pad0[656]; + + /* + * BRG 5-8 Block + */ + uint32_t brgc5; + uint32_t brgc6; + uint32_t brgc7; + uint32_t brgc8; + uint8_t brg_pad0[608]; + + + /* + * I2C + */ + uint8_t i2mod; + uint8_t i2m_pad0[3]; + uint8_t i2add; + uint8_t i2m_pad1[3]; + uint8_t i2brg; + uint8_t i2m_pad2[3]; + uint8_t i2com; + uint8_t i2m_pad3[3]; + uint8_t i2cer; + uint8_t i2m_pad4[3]; + uint8_t i2cmr; + uint8_t i2m_pad5[331]; + + + /* + * CPM Block + */ + uint32_t cpcr; + uint32_t rccr; + uint8_t cpm_pad3[14]; + uint16_t rter; + uint8_t cpm_pad[2]; + uint16_t rtmr; + uint16_t rtscr; + uint8_t cpm_pad4[2]; + uint32_t rtsr; + uint8_t cpm_pad5[12]; + + + /* + * BRG 1-4 Block + */ + uint32_t brgc1; + uint32_t brgc2; + uint32_t brgc3; + uint32_t brgc4; + + + /* + * SCC Block + */ + m8260SCCRegisters_t scc1; + m8260SCCRegisters_t scc2; + m8260SCCRegisters_t scc3; + m8260SCCRegisters_t scc4; + + + /* + * SMC Block + */ + m8260SMCRegisters_t smc1; + m8260SMCRegisters_t smc2; + + + /* + * SPI Block + */ + uint16_t spmode; + uint8_t spi_pad0[4]; + uint8_t spie; + uint8_t spi_pad1[3]; + uint8_t spim; + uint8_t spi_pad2[2]; + uint8_t spcom; + uint8_t spi_pad3[82]; + + + /* + * CPM Mux Block + */ + uint8_t cmxsi1cr; + uint8_t cmx_pad0[1]; + uint8_t cmxsi2cr; + uint8_t cmx_pad1[1]; + uint32_t cmxfcr; + uint32_t cmxscr; + uint8_t cmxsmr; + uint8_t cmx_pad2[1]; + uint16_t cmxuar; + uint8_t cmx_pad3[16]; + + + /* + * SI & MCC Blocks + */ + m8260SIRegisters_t si1; + m8260MCCRegisters_t mcc1; + m8260SIRegisters_t si2; + m8260MCCRegisters_t mcc2; + + uint8_t mcc_pad0[1152]; + + /* + * SI1 RAM + */ + uint8_t si1txram[512]; + uint8_t ram_pad0[512]; + uint8_t si1rxram[512]; + uint8_t ram_pad1[512]; + + + /* + * SI2 RAM + */ + uint8_t si2txram[512]; + uint8_t ram_pad2[512]; + uint8_t si2rxram[512]; + uint8_t ram_pad3[512]; + + +} m8260_t; + +extern volatile m8260_t m8260; +#endif /* ASM */ + +#endif /* _MPC8260_H */ diff --git a/bsps/powerpc/include/mpc8260/console.h b/bsps/powerpc/include/mpc8260/console.h new file mode 100644 index 0000000000..049cef6d89 --- /dev/null +++ b/bsps/powerpc/include/mpc8260/console.h @@ -0,0 +1,60 @@ +#ifndef _MPC8260_CONSOLE_H +#define _MPC8260_CONSOLE_H + +#include <rtems/libio.h> + +void m8xx_uart_initialize(void); +void m8xx_uart_interrupts_initialize(void); +void m8xx_uart_scc_initialize (int minor); +void m8xx_uart_smc_initialize (int minor); + +/* Termios callbacks */ +int m8xx_uart_pollRead(int minor); +ssize_t m8xx_uart_pollWrite(int minor, const char* buf, size_t len); +ssize_t m8xx_uart_write(int minor, const char *buf, size_t len); +int m8xx_uart_setAttributes(int, const struct termios* t); + + +#if 0 +int m8260_smc_set_attributes(int, const struct termios*); +int m8260_scc_set_attributes(int, const struct termios*); +void m8260_scc_initialize(int); +void m8260_smc_initialize(int); +int m8260_char_poll_read(int); +int m8260_char_poll_write(int, const char*, int); +rtems_isr m8260_scc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc2_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc3_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc4_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_smc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_smc2_console_interrupt_handler(rtems_vector_number); +int m8260_buf_poll_read(int, char**); +int m8260_buf_poll_write(int, char*, int); +void m8260_console_initialize(void); +rtems_device_driver m8260_console_read(rtems_device_major_number, + rtems_device_minor_number, + void*); +rtems_device_driver m8260_console_write(rtems_device_major_number, + rtems_device_minor_number, + void*); + + +typedef struct Buf_t_ { + struct Buf_t_ *next; + volatile char *buf; + volatile int len; + int pos; +} Buf_t; +#endif + +#define NUM_PORTS 6 + +#define SMC1_MINOR 0 +#define SMC2_MINOR 1 +#define SCC1_MINOR 2 +#define SCC2_MINOR 3 +#define SCC3_MINOR 4 +#define SCC4_MINOR 5 + + +#endif diff --git a/bsps/powerpc/include/mpc8260/cpm.h b/bsps/powerpc/include/mpc8260/cpm.h new file mode 100644 index 0000000000..31708a4199 --- /dev/null +++ b/bsps/powerpc/include/mpc8260/cpm.h @@ -0,0 +1,123 @@ +/* + * cpm.h + * + * This include file contains definitions pertaining + * to the Communications Processor Module (CPM) on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8260_CPM_H +#define _MPC8260_CPM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define M8xx_BRG_1 (1U << 0) +#define M8xx_BRG_2 (1U << 1) +#define M8xx_BRG_3 (1U << 2) +#define M8xx_BRG_4 (1U << 3) +#define M8xx_BRG_5 (1U << 4) +#define M8xx_BRG_6 (1U << 5) +#define M8xx_BRG_7 (1U << 6) +#define M8xx_BRG_8 (1U << 7) + + +#define M8260_SCC_BRGS (M8xx_BRG_1 | M8xx_BRG_2 | M8xx_BRG_3 | M8xx_BRG_4) +#define M8260_FCC_BRGS (M8xx_BRG_5 | M8xx_BRG_6 | M8xx_BRG_7 | M8xx_BRG_8) +#define M8260_SMC1_BRGS (M8xx_BRG_1|M8xx_BRG_7) +#define M8260_SMC2_BRGS (M8xx_BRG_2|M8xx_BRG_8) + + +#define M8xx_CLK_1 (1U << 0) +#define M8xx_CLK_2 (1U << 1) +#define M8xx_CLK_3 (1U << 2) +#define M8xx_CLK_4 (1U << 3) +#define M8xx_CLK_5 (1U << 4) +#define M8xx_CLK_6 (1U << 5) +#define M8xx_CLK_7 (1U << 6) +#define M8xx_CLK_8 (1U << 7) +#define M8xx_CLK_9 (1U << 8) +#define M8xx_CLK_10 (1U << 9) +#define M8xx_CLK_11 (1U << 10) +#define M8xx_CLK_12 (1U << 11) +#define M8xx_CLK_13 (1U << 12) +#define M8xx_CLK_14 (1U << 13) +#define M8xx_CLK_15 (1U << 14) +#define M8xx_CLK_16 (1U << 15) +#define M8xx_CLK_17 (1U << 16) +#define M8xx_CLK_18 (1U << 17) +#define M8xx_CLK_19 (1U << 18) +#define M8xx_CLK_20 (1U << 19) + +#define M8260_BRG1_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG2_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG3_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG4_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG5_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG6_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG7_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG8_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) + +#define M8260_SCC1_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_SCC2_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_SCC3_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) +#define M8260_SCC4_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) + +#define M8260_FCC1_CLKS (M8xx_CLK_9 | M8xx_CLK_10 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_FCC2_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) +#define M8260_FCC3_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) + +#define M8260_TDM_RXA1 (M8xx_CLK_1 | M8xx_CLK_19 ) +#define M8260_TDM_RXB1 (M8xx_CLK_3 | M8xx_CLK_9 ) +#define M8260_TDM_RXC1 (M8xx_CLK_5 | M8xx_CLK_13 ) +#define M8260_TDM_RXD1 (M8xx_CLK_7 | M8xx_CLK_15 ) +#define M8260_TDM_TXA1 (M8xx_CLK_2 | M8xx_CLK_20 ) +#define M8260_TDM_TXB1 (M8xx_CLK_4 | M8xx_CLK_10 ) +#define M8260_TDM_TXC1 (M8xx_CLK_6 | M8xx_CLK_14 ) +#define M8260_TDM_TXD1 (M8xx_CLK_8 | M8xx_CLK_16 ) + +#define M8260_TDM_RXA2 (M8xx_CLK_13 | M8xx_CLK_5 ) +#define M8260_TDM_RXB2 (M8xx_CLK_15 | M8xx_CLK_17 ) +#define M8260_TDM_RXC2 (M8xx_CLK_3 | M8xx_CLK_17 ) +#define M8260_TDM_RXD2 (M8xx_CLK_1 | M8xx_CLK_19 ) +#define M8260_TDM_TXA2 (M8xx_CLK_14 | M8xx_CLK_6 ) +#define M8260_TDM_TXB2 (M8xx_CLK_16 | M8xx_CLK_18 ) +#define M8260_TDM_TXC2 (M8xx_CLK_4 | M8xx_CLK_18 ) +#define M8260_TDM_TXD2 (M8xx_CLK_2 | M8xx_CLK_20 ) + + + +/* Functions */ + +void m8xx_cp_execute_cmd( uint32_t command ); +void *m8xx_dpram_allocate( unsigned int byte_count ); + +#define m8xx_bd_allocate(count) \ + m8xx_dpram_allocate( (count) * sizeof(m8260BufferDescriptor_t) ) +#define m8xx_RISC_timer_table_allocate(count) \ + m8xx_dpram_allocate( (count) * 4 ) + + + +int m8xx_get_brg_cd (int baud); +int m8xx_get_brg(unsigned brgmask, int baud); +void m8xx_free_brg(int brg_num); + + +int m8xx_get_clk( unsigned clkmask ); +void m8xx_free_clk( int clk_num ); + + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/mpc8260/mmu.h b/bsps/powerpc/include/mpc8260/mmu.h new file mode 100644 index 0000000000..9445dde3bc --- /dev/null +++ b/bsps/powerpc/include/mpc8260/mmu.h @@ -0,0 +1,47 @@ +/* + * mmu.h + * + * This include file contains definitions pertaining + * to the MMU on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8260_MMU_H +#define _MPC8260_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of an MPC8260. + */ +typedef struct { + uint32_t mmu_epn; /* Effective Page Number */ + uint32_t mmu_twc; /* Tablewalk Control Register */ + uint32_t mmu_rpn; /* Real Page Number */ +} MMU_TLB_table_t; + +/* + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * supplied by the BSP. + */ +extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ +extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ + +/* Functions */ + +void mmu_init( void ); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/mpc83xx/gtm.h b/bsps/powerpc/include/mpc83xx/gtm.h new file mode 100644 index 0000000000..a17510ed10 --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/gtm.h @@ -0,0 +1,67 @@ +/** + * @file + * + * @brief Header file for timer functions. + */ + +/* + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC83XX_TIMER_H +#define LIBBSP_POWERPC_MPC83XX_TIMER_H + +#include <stdint.h> +#include <stdbool.h> + +#include <rtems.h> + +#define MPC83XX_GTM_NUMBER 8 + +#define MPC83XX_GTM_CLOCK_CASCADED 0x0000 +#define MPC83XX_GTM_CLOCK_SYSTEM 0x0002 +#define MPC83XX_GTM_CLOCK_SYSTEM_SLOW 0x0004 +#define MPC83XX_GTM_CLOCK_EXTERN 0x0006 + +rtems_status_code mpc83xx_gtm_initialize( int timer, int clock); + +rtems_status_code mpc83xx_gtm_enable_restart( int timer, bool enable); + +rtems_status_code mpc83xx_gtm_set_clock( int timer, int clock); + +rtems_status_code mpc83xx_gtm_get_clock( int timer, int *clock); + +rtems_status_code mpc83xx_gtm_start( int timer); + +rtems_status_code mpc83xx_gtm_stop( int timer); + +rtems_status_code mpc83xx_gtm_set_value( int timer, uint16_t value); + +rtems_status_code mpc83xx_gtm_get_value( int timer, uint16_t *value); + +rtems_status_code mpc83xx_gtm_set_reference( int timer, uint16_t reference); + +rtems_status_code mpc83xx_gtm_get_reference( int timer, uint16_t *reference); + +rtems_status_code mpc83xx_gtm_set_prescale( int timer, uint8_t prescale); + +rtems_status_code mpc83xx_gtm_get_prescale( int timer, uint8_t *prescale); + +rtems_status_code mpc83xx_gtm_interrupt_get_vector( int timer, rtems_vector_number *vector); + +rtems_status_code mpc83xx_gtm_interrupt_enable( int timer); + +rtems_status_code mpc83xx_gtm_interrupt_disable( int timer); + +rtems_status_code mpc83xx_gtm_interrupt_clear( int timer); + +#endif /* LIBBSP_POWERPC_MPC83XX_TIMER_H */ diff --git a/bsps/powerpc/include/mpc83xx/mpc83xx.h b/bsps/powerpc/include/mpc83xx/mpc83xx.h new file mode 100644 index 0000000000..6f7417af1c --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/mpc83xx.h @@ -0,0 +1,1014 @@ +#ifndef _MPC83XX_MPC83XX_H +#define _MPC83XX_MPC83XX_H + +#include <bspopts.h> + +#if MPC83XX_CHIP_TYPE == 8343 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_USB1 TRUE +#elif MPC83XX_CHIP_TYPE == 8347 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_USB1 TRUE +#define M83xx_HAS_USB2 TRUE +#elif MPC83XX_CHIP_TYPE == 8349 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_WIDE_PCI TRUE +#define M83xx_HAS_USB1 TRUE +#define M83xx_HAS_USB2 TRUE +#elif MPC83XX_CHIP_TYPE == 8360 +#define M83xx_HAS_PCI TRUE +#define M83xx_HAS_QE TRUE +#endif + +#if !defined(ASM) + +#include <rtems.h> +#include <bsp/tsec.h> + +/* Offset Register Access Reset Section/Page */ +/* System Configuration Registers */ +typedef struct m83xxSysConRegisters_ { + volatile uint32_t immrbar; /* 0x0_00000 Internal memory map base address register R/W 0xFF40_0000 5.2.4.1/5-5 */ + uint8_t reserved0_0004[0x00008-0x00004];/* 0x0_0004 Reserved, should be cleared */ + volatile uint32_t altcbar; /* 0x0_0008 Alternate configuration base address register R/W 0x0000_0000 5.2.4.2/5-7 */ + uint8_t reserved0_000C[0x00020-0x0000C];/* 0x0_000C--0x0_001C Reserved, should be cleared */ + volatile uint32_t lblawbar0; /* 0x0_0020 LBC local access window 0 base address register R/W 0x0000_00001 5.2.4.3/5-7 */ + volatile uint32_t lblawar0; /* 0x0_0024 LBC local access window 0 attribute register R/W 0x0000_00002 5.2.4.4/5-8 */ + volatile uint32_t lblawbar1; /* 0x0_0028 LBC local access window 1 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ + volatile uint32_t lblawar1; /* 0x0_002C LBC local access window 1 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ + volatile uint32_t lblawbar2; /* 0x0_0030 LBC local access window 2 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ + volatile uint32_t lblawar2; /* 0x0_0034 LBC local access window 2 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ + volatile uint32_t lblawbar3; /* 0x0_0038 LBC local access window 3 base address register R/W 0x0000_0000 5.2.4.3/5-7 */ + volatile uint32_t lblawar3; /* 0x0_003C LBC local access window 3 attribute register R/W 0x0000_0000 5.2.4.4/5-8 */ + uint8_t reserved0_0040[0x00060-0x00040];/* 0x0_0040--0x0_005C Reserved, should be cleared */ + volatile uint32_t pcilawbar0; /* 0x0_0060 PCI local access window0 base address register R/W 0x0000_00003 5.2.4.5/5-9 */ + volatile uint32_t pcilawar0; /* 0x0_0064 PCI local access window0 attribute register R/W 0x0000_00004 5.2.4.6/5-10 */ + volatile uint32_t pcilawbar1; /* 0x0_0068 PCI local access window1 base address register R/W 0x0000_0000 5.2.4.5/5-9 */ + volatile uint32_t pcilawar1; /* 0x0_006C PCI local access window1 attribute register R/W 0x0000_0000 5.2.4.6/5-10 */ + uint8_t reserved0_0070[0x000A0-0x00070];/* 0x0_0070--0x0_009C Reserved, should be cleared */ + volatile uint32_t ddrlawbar0; /* 0x0_00A0 DDR local access window0 base address register R/W 0x0000_00005 5.2.4.7/5-12 */ + volatile uint32_t ddrlawar0; /* 0x0_00A4 DDR local access window0 attribute register R/W 0x0000_00006 5.2.4.8/5-13 */ + volatile uint32_t ddrlawbar1; /* 0x0_00A8 DDR local access window1 base address register R/W 0x0000_0000 5.2.4.7/5-12 */ + volatile uint32_t ddrlawar1; /* 0x0_00AC DDR local access window1 attribute register R/W 0x0000_0000 5.2.4.8/5-13 */ + uint8_t reserved0_00B0[0x00100-0x000B0];/* 0x0_00B0--0x0_0100 Reserved, should be cleared */ + volatile uint32_t sgprl; /* 0x0_0100 general purpose register low (SGPRL) R/W 0x0000_0000 5.3.2.1/5-17 */ + volatile uint32_t sgprh; /* 0x0_0104 general purpose register high (SGPRH) R/W 0x0000_0000 5.3.2.2/5-17 */ + volatile uint32_t spridr; /* 0x0_0108 part and revision ID register (SPRIDR) R 0x0000_0000 5.3.2.3/5-18 */ + uint8_t reserved0_010C[0x00110-0x0010C];/* 0x0_010C--0x0_0110 Reserved, should be cleared */ + volatile uint32_t spcr; /* 0x0_0110 priority configuration register (SPCR) R/W 0x0000_0000 5.3.2.4/5-19 */ + volatile uint32_t sicrl; /* 0x0_0114 I/O configuration register low (SICRL) R/W 0x0000_0000 5.3.2.5/5-21 */ + volatile uint32_t sicrh; /* 0x0_0118 I/O configuration register high (SICRH) R/W 0x0000_00007 5.3.2.6/5-24 */ + uint8_t reserved0_011C[0x00128-0x0011C];/* 0x0_011C--0x0_0128 Reserved */ + volatile uint32_t ddrcdr; /* 0x0_0128 control driver register (DDRCDR) R/W 0x7304_0001 5.3.2.8/5-28 */ + volatile uint32_t ddrdsr; /* 0x0_012C debug status register (DDRDSR) R 0x3300_0000 5.3.2.9/5-30 */ + uint8_t reserved0_0130[0x00150-0x00130];/* 0x0_0130--0x0_015C Reserved */ + volatile uint32_t gpr_1; /* 0x0_0150 General Purpose Register 1 (GPR_1) */ + uint8_t reserved0_0154[0x00200-0x00154];/* 0x0_0154--0x0_01FC Reserved */ +} m83xxSysConRegisters_t; +#define M83xx_SYSCON_SPCR_TBEN (1 << (31-9)) + +/* Watchdog Timer (WDT) Registers */ +typedef struct m83xxWDTRegisters_ { + uint8_t reserved0_0200[0x00204-0x00200];/* 0x0_0200 Reserved, should be cleared */ + volatile uint32_t swcrr; /* 0x0_0204 System watchdog control register R/W 0x0000_0007 5.4.4.1/5-33 */ + volatile uint32_t swcnr; /* 0x0_0208 System watchdog count register R 0x0000_FFFF 5.4.4.2/5-34 */ + uint8_t reserved0_020C[(0x0020E)-0x0020C];/* 0x0_020C Reserved, should be cleared */ + volatile uint16_t swsrr; /* 0x0_020E System watchdog service register R/W 0x0000_0000 5.4.4.3/5-34 */ +} m83xxWDTRegisters_t; + +/* Real Time Clock Module Registers (RTC) */ +typedef struct m83xxRTCRegisters_ { + volatile uint32_t rtcnr; /* 0x0_0300 Real time counter control register R/W 0x0000_0000 5.5.5.1/5-40 */ + volatile uint32_t rtldr; /* 0x0_0304 Real time counter load register R/W 0x0000_0000 5.5.5.2/5-41 */ + volatile uint32_t rtpsr; /* 0x0_0308 Real time counter prescale register R/W 0x0000_0000 5.5.5.3/5-41 */ + volatile uint32_t rtctr; /* 0x0_030C Real time counter register R 0x0000_0000 5.5.5.4/5-42 */ + volatile uint32_t rtevr; /* 0x0_0310 Real time counter event register R/W 0x0000_0000 5.5.5.5/5-42 */ + volatile uint32_t rtalr; /* 0x0_0314 Real time counter alarm register R/W 0xFFFF_FFFF 5.5.5.6/5-43 */ + uint8_t reserved0_0314[0x00320-0x00318];/* 0x0_0318--0x0_031F Reserved; should be cleared */ +} m83xxRTCRegisters_t; + + /* Periodic Interval Timer (PIT) Registers */ +typedef struct m83xxPITRegisters_ { + volatile uint32_t ptcnr; /* 0x0_0400 Periodic interval timer control register R/W 0x0000_0000 5.6.5.1/5-47 */ + volatile uint32_t ptldr; /* 0x0_0404 Periodic interval timer load register R/W 0x0000_0000 5.6.5.2/5-48 */ + volatile uint32_t ptpsr; /* 0x0_0408 Periodic interval timer prescale register R/W 0x0000_0000 5.6.5.3/5-49 */ + volatile uint32_t ptctr; /* 0x0_040C Periodic interval timer counter register R 0x0000_0000 5.6.5.4/5-49 */ + volatile uint32_t ptevr; /* 0x0_0410 Periodic interval timer event register R/W 0x0000_0000 5.6.5.5/5-50 */ + uint8_t reserved0_0414[0x00500-0x00414]; /* 0x0_0414--0x0_041F Reserved, should be cleared */ +} m83xxPITRegisters_t; + + /* Global Timers Module 1/2 */ +#define M83xxGTIdx(n) (n&3) +#define M83xxGTLowIdx(n) (n&1) +#define M83xxGTHighIdx(n) (((n)>>1)&1) +#define M83xxGTModIdx(n) (((n)>>2)&1) + +#define M83xxGTIdxCnt (4) +#define M83xxGTLowCnt (2) +#define M83xxGTHighCnt (2) +#define M83xxGTModCnt (2) + +typedef struct m83xxGTMRegisters_ { + struct { + volatile uint8_t reg; /* 0x0_0500 Timer 1+2/3+4 global timers configuration register R/W 0x00 5.7.5.1/5-57 */ + uint8_t reserved0_0501[0x00504-0x00501]; /* 0x0_0501--0x0_0503 Reserved, should be cleared */ + } gtcfr[M83xxGTHighCnt]; + uint8_t reserved0_0508[0x00510-0x00508]; /* 0x0_0508--0x0_050f Reserved, should be cleared */ + struct { + volatile uint16_t gtmdr[M83xxGTLowCnt]; /* 0x0_0510 Timer 1/2 global timers mode register R/W 0x0000 5.7.5.2/5-60 */ + volatile uint16_t gtrfr[M83xxGTLowCnt]; /* 0x0_0514 Timer 1/2 global timers reference register R/W 0x0000 5.7.5.3/5-62 */ + volatile uint16_t gtcpr[M83xxGTLowCnt]; /* 0x0_0518 Timer 1/2 global timers capture register R/W 0x0000 5.7.5.4/5-62 */ + volatile uint16_t gtcnr[M83xxGTLowCnt]; /* 0x0_051C Timer 1/2 global timers counter register R/W 0x0000 5.7.5.5/5-63 */ + } gt_tim_regs[M83xxGTHighCnt]; + volatile uint16_t gtevr[M83xxGTIdxCnt]; /* 0x0_0530 Timer 1-4 global timers event register Special 0x0000 5.7.5.6/5-63 */ + volatile uint16_t gtpsr[M83xxGTIdxCnt]; /* 0x0_0538 Timer 1-4 global timers prescale register R/W 0x0003 5.7.5.7/5-64 */ + uint8_t reserved0_0540[0x00600-0x00540]; /* 0x0_0540--0x0_05fc Reserved */ +} m83xxGTMRegisters_t; + + /* Integrated Programmable Interrupt Controller (IPIC) */ +typedef struct m83xxIPICRegisters_ { + volatile uint32_t sicfr; /* 0x0_0700 System global interrupt configuration register R/W 0x0000_0000 8.5.1/8-8 */ + volatile uint32_t sivcr; /* 0x0_0704 System global interrupt vector register R 0x0000_0000 8.5.2/8-9 */ + volatile uint32_t sipnr[2]; /* 0x0_0708 System internal interrupt pending register H/L R 0x0000_0000 8.5.3/8-11 */ + volatile uint32_t siprr[4]; /* 0x0_0710 System internal interrupt group A-D priority register R/W 0x0530_9770 8.5.4/8-14 */ + volatile uint32_t simsr[2]; /* 0x0_0720 System internal interrupt mask register H/L R/W 0x0000_0000 8.5.6/8-15 */ + uint8_t reserved0_0728[0x0072C-0x00728]; /* 0x0_072C--0x0_0728 Reserved, should be cleared */ + volatile uint32_t sepnr; /* 0x0_072C System external interrupt pending register R/W Special 8.5.8/8-18 */ + volatile uint32_t smprr[2]; /* 0x0_0730 System mixed interrupt group A/B priority register R/W 0x0530_9770 8.5.9/8-18 */ + volatile uint32_t semsr; /* 0x0_0738 System external interrupt mask register R/W 0x0000_0000 8.5.11/8-20 */ + volatile uint32_t secnr; /* 0x0_073C System external interrupt control register R/W 0x0000_0000 8.5.12/8-21 */ + volatile uint32_t sersr; /* 0x0_0740 System error status register R/W 0x0000_0000 8.5.13/8-22 */ + volatile uint32_t sermr; /* 0x0_0744 System error mask register R/W $ 8.5.14/8-23 */ + volatile uint32_t sercr; /* 0x0_0748 System error control register R/W 0x0000_0000 8.5.15/8-24 */ + uint8_t reserved0_074C[0x00750-0x0074C]; /* 0x0_074C--0x0_074F Reserved, should be cleared */ + volatile uint32_t sifcr[2]; /* 0x0_0750 System internal interrupt force register H/L R/W 0x0000_0000 8.5.16/8-25 */ + volatile uint32_t sefcr; /* 0x0_0758 System external interrupt force register R/W 0x0000_0000 8.5.17/8-26 */ + volatile uint32_t serfr; /* 0x0_075C System error force register R/W 0x0000_0000 8.5.18/8-26 */ + volatile uint32_t scvcr; /* 0x0_0760 System critical interrupt vector register R 0x0000_0000 8.5.19/8-27 */ + volatile uint32_t smvcr; /* 0x0_0764 System management interrupt vector register R 0x0000_0000 8.5.20/8-27 */ + uint8_t reserved0_0760[0x00800-0x00768]; /* 0x0_0768--0x0_07FF Reserved, should be cleared */ +} m83xxIPICRegisters_t; + +/* get vector number from vector register content */ +#define MPC83xx_VCR_TO_VEC(regval) ((regval) & 0x7f) + + + /* System Arbiter Registers */ +typedef struct m83xxARBRegisters_ { + volatile uint32_t acr; /* 0x0_0800 Arbiter configuration register R/W 0x0000_0000 6.2.1/6-2 */ + volatile uint32_t atr; /* 0x0_0804 Arbiter timers register R/W 0x00FF_00FF 6.2.2/6-4 */ + uint8_t reserved0_0808[0x0080C-0x00808]; /* 0x0_0808 Reserved, should be cleared R 0x0000_0000 */ + volatile uint32_t aer; /* 0x0_080C Arbiter event register R/W 0x0000_0000 6.2.3/6-5 */ + volatile uint32_t aidr; /* 0x0_0810 Arbiter interrupt definition register R/W 0x0000_0000 6.2.4/6-6 */ + volatile uint32_t amr; /* 0x0_0814 Arbiter mask register R/W 0x0000_0000 6.2.5/6-7 */ + volatile uint32_t aeatr; /* 0x0_0818 Arbiter event attributes register R 0x0000_0000 6.2.6/6-7 */ + volatile uint32_t aeadr; /* 0x0_081C Arbiter event address register R 0x0000_0000 6.2.7/6-9 */ + volatile uint32_t aerr; /* 0x0_0820 Arbiter event response register R/W 0x0000_0000 6.2.8/6-10 */ + uint8_t reserved0_0824[0x00900-0x00824]; /* 0x0_0824--0x0_08FF Reserved, should be cleared */ +} m83xxARBRegisters_t; + + /* Reset Module */ +typedef struct m83xxRESRegisters_ { + volatile uint32_t rcwlr; /* 0x0_0900 Reset configuration word low register R 0x0000_0000 4.5.1.1/4-32 */ + volatile uint32_t rcwhr; /* 0x0_0904 Reset configuration word high register R 0x0000_0000 4.5.1.2/4-32 */ + uint8_t reserved0_0908[0x00910-0x00908]; /* 0x0_0908--0x0_090C Reserved, should be cleared */ + volatile uint32_t rsr; /* 0x0_0910 Reset status register R/W 0x0000_0000 4.5.1.3/4-33 */ + volatile uint32_t rmr; /* 0x0_0914 Reset mode register R/W 0x0000_0000 4.5.1.4/4-34 */ + volatile uint32_t rpr; /* 0x0_0918 Reset protection register R/W 0x0000_0000 4.5.1.5/4-35 */ + volatile uint32_t rcr; /* 0x0_091C Reset control register R/W 0x0000_0000 4.5.1.6/4-36 */ + volatile uint32_t rcer; /* 0x0_0920 Reset control enable register R/W 0x0000_0000 4.5.1.7/4-36 */ + uint8_t reserved0_0924[0x00A00-0x00924]; /* 0x0_0924--0x0_09FC Reserved, should be cleared */ +} m83xxRESRegisters_t; + + /* Clock Module */ +typedef struct m83xxCLKRegisters_ { + volatile uint32_t spmr; /* 0x0_0A00 System PLL mode register R 0x0000_0000 4.5.2.1/4-37 */ + volatile uint32_t occr; /* 0x0_0A04 Output clock control register R/W 0x0000_0000 4.5.2.2/4-38 */ + volatile uint32_t sccr; /* 0x0_0A08 System clock control register R/W 0xFFFF_FFFF 4.5.2.3/4-40 */ + uint8_t reserved0_0A08[0x00B00-0x00A0C]; /* 0x0_0A0C--0x0_0AFC Reserved, should be cleared */ +} m83xxCLKRegisters_t; + /* Power Management Control Module */ +typedef struct m83xxPMCRegisters_ { + volatile uint32_t pmccr; /* 0x0_0B00 Power management controller configuration register R/W 0x0000_0000 5.8.3.1/5-69 */ + volatile uint32_t pmcer; /* 0x0_0B04 Power management controller event register R/W 0x0000_0000 5.8.3.2/5-70 */ + volatile uint32_t pmcmr; /* 0x0_0B08 Power management controller mask register R/W 0x0000_0000 5.8.3.3/5-71 */ + uint8_t reserved0_0B10[0x00C00-0x00B0C]; /* 0x0_0B0C--0x0_0BFC Reserved, should be cleared */ +} m83xxPMCRegisters_t; + /* GPIO1 Registers */ +typedef struct m83xxGPIORegisters_ { + volatile uint32_t gpdir; /* 0x0_0C00 GPIO1/2 direction register R/W 0x0000_0000 21.3.1/21-3 */ + volatile uint32_t gpdr; /* 0x0_0C04 GPIO1/2 open drain register R/W 0x0000_0000 21.3.2/21-4 */ + volatile uint32_t gpdat; /* 0x0_0C08 GPIO1/2 data register R/W 0x0000_0000 21.3.3/21-4 */ + volatile uint32_t gpier; /* 0x0_0C0C GPIO1/2 interrupt event register R/W Undefined 21.3.4/21-5 */ + volatile uint32_t gpimr; /* 0x0_0C10 GPIO1/2 interrupt mask register R/W 0x0000_0000 21.3.5/21-5 */ + volatile uint32_t gpicr; /* 0x0_0C14 GPIO1/2 external interrupt control register R/W 0x0000_0000 21.3.6/21-6 */ + uint8_t reserved0_0C1C[0x00D00-0x00C18]; /* 0x0_0C18--0x0_0CFF Reserved, should be cleared */ +} m83xxGPIORegisters_t; + + /* DLL */ +typedef struct m83xxDLLRegisters_ { + uint8_t reserved0_1000[0x01010-0x01000]; /* 0x0_1000--0x0_100F Reserved, should be cleared */ + volatile uint32_t mckenr; /* 0x0_1010 MCK enable register (MCKENR) R/W 0xFC00_0000 4.5.3/4-41 */ + uint8_t reserved0_1014[0x01100-0x01014]; /* 0x0_1014--0x0_10FF Reserved, should be cleared */ + volatile uint32_t reserved0_1100; /* 0x0_1100 Reserved. Reset value should be preserved. R/W 0x0500_0280 */ + volatile uint32_t reserved0_1104; /* 0x0_1104 Reserved. Reset value should be preserved. R/W 0x8004_0810 */ + volatile uint32_t dllovr; /* 0x0_1108 DLL override register (DLLOVR) R/W 0x0000_0000 22.4.1/22-4 */ + volatile uint32_t dllsr; /* 0x0_110C DLL status register (DLLSR) R 0x0000_0000 22.4.2/22-4 */ + volatile uint32_t dllck; /* 0x0_1110 DLL clock register (DLLCK) R/W 0xFC00_0000 22.4.3/22-5 */ + uint8_t reserved0_1110[0x01200-0x01114]; /* 0x0_1114--0x0_11FF Reserved, should be cleared */ +} m83xxDLLRegisters_t; + + /* DDR Memory Controller Memory Map */ +typedef struct m83xxDDRRegisters_ { + volatile uint32_t cs0_bnds; /* 0x0_2000 Chip select 0 memory bounds R/W 0x0000_0000 9.4.1.1/9-10 */ + uint8_t reserved0_2004[0x02008-0x02004]; /* 0x0_2004--0x0_2008 Reserved, should be cleared */ + volatile uint32_t cs1_bnds; /* 0x0_2008 Chip select 1 memory bounds R/W 0x0000_0000 */ + uint8_t reserved0_200C[0x02010-0x0200C]; /* 0x0_200C--0x0_2010 Reserved, should be cleared */ + volatile uint32_t cs2_bnds; /* 0x0_2010 Chip select 2 memory bounds R/W 0x0000_0000 */ + uint8_t reserved0_2014[0x02018-0x02014]; /* 0x0_2014--0x0_2018 Reserved, should be cleared */ + volatile uint32_t cs3_bnds; /* 0x0_2018 Chip select 3 memory bounds R/W 0x0000_0000 */ + uint8_t reserved0_201C[0x02080-0x0201C]; /* 0x0_201C--0x0_207F Reserved, should be cleared */ + volatile uint32_t cs0_config; /* 0x0_2080 Chip select 0 configuration R/W 0x0000_0000 9.4.1.2/9-11 */ + volatile uint32_t cs1_config; /* 0x0_2084 Chip select 1 configuration R/W 0x0000_0000 */ + volatile uint32_t cs2_config; /* 0x0_2088 Chip select 2 configuration R/W 0x0000_0000 */ + volatile uint32_t cs3_config; /* 0x0_208C Chip select 3 configuration R/W 0x0000_0000 */ + uint8_t reserved0_2090[0x02100-0x02090]; /* 0x0_2090--0x0_2100 Reserved, should be cleared */ + volatile uint32_t timing_cfg_3; /* 0x0_2100 DDR SDRAM timing configuration 3 R/W 0x0000_0000 9.4.1.3/9-13 */ + volatile uint32_t timing_cfg_0; /* 0x0_2104 DDR SDRAM timing configuration 0 R/W 0x0011_0105 9.4.1.4/9-14 */ + volatile uint32_t timing_cfg_1; /* 0x0_2108 DDR SDRAM timing configuration 1 R/W 0x0000_0000 9.4.1.5/9-16 */ + volatile uint32_t timing_cfg_2; /* 0x0_210C DDR SDRAM timing configuration 2 R/W 0x0000_0000 9.4.1.6/9-18 */ + volatile uint32_t ddr_sdram_cfg; /* 0x0_2110 DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-20 */ + volatile uint32_t ddr_sdram_cfg_2; /* 0x0_2114 DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22 */ + volatile uint32_t ddr_sdram_mode; /* 0x0;_2118 DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-24 */ + volatile uint32_t ddr_sdram_mode_2; /* 0x0_211C DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.10/9-24 */ + volatile uint32_t ddr_sdram_md_cntl; /* 0x0_2120 DDR SDRAM mode control R/W 0x0000_0000 9.4.1.11/9-25 */ + volatile uint32_t ddr_sdram_interval; /* 0x0_2124 DDR SDRAM interval configuration R/W 0x0000_0000 9.4.1.12/9-27 */ + volatile uint32_t ddr_data_init; /* 0x0_2128 DDR SDRAM data initialization R/W 0x0000_0000 9.4.1.13/9-28 */ + uint8_t reserved0_212C[0x02130-0x0212C]; /* 0x0_212C Reserved $ $ */ + volatile uint32_t ddr_sdram_clk_cntl; /* 0x0_2130 DDR SDRAM clock control R/W 0x0200_0000 9.4.1.14/9-28 */ + uint8_t reserved0_2134[0x02148-0x02134]; /* 0x0_2140 Reserved $ $ */ + volatile uint32_t ddr_init_address; /* 0x0_2148 DDR training initialization address R/W 0x0000_0000 9.4.1.15/9-29 */ + uint8_t reserved0_214C[0x02BF8-0x0214C]; /* 0x0_214C Reserved $ $ */ + volatile uint32_t ddr_ip_rev1; /* 0x0_2BF8 DDR IP block revision 1 R 0x0002_0200 9.4.1.16/9-30 */ + volatile uint32_t ddr_ip_rev2; /* 0x0_2BFC DDR IP block revision 2 R 0x0000_0000 9.4.1.17/9-30 */ + uint8_t reserved0_2C00[0x02E00-0x02C00]; /* 0x0_2C00 Reserved $ $ */ + volatile uint32_t data_err_inject_hi; /* 0x0_2E00 Memory data path error injection mask high R/W 0x0000_0000 9.4.1.18/9-31 */ + volatile uint32_t data_err_inject_lo; /* 0x0_2E04 Memory data path error injection mask low R/W 0x0000_0000 9.4.1.19/9-31 */ + volatile uint32_t ecc_err_inject; /* 0x0_2E08 Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.20/9-32 */ + uint8_t reserved0_2E0C[0x02E20-0x02E0C]; /* 0x0_2E0C Reserved $ $ */ + volatile uint32_t capture_data_hi; /* 0x0_2E20 Memory data path read capture high R/W 0x0000_0000 9.4.1.21/9-32 */ + volatile uint32_t capture_data_lo; /* 0x0_2E24 Memory data path read capture low R/W 0x0000_0000 9.4.1.22/9-33 */ + volatile uint32_t capture_ecc; /* 0x0_2E28 Memory data path read capture ECC R/W 0x0000_0000 9.4.1.23/9-33 */ + uint8_t reserved0_2E2C[0x02E40-0x02E2C]; /* 0x0_2E2C Reserved $ $ */ + volatile uint32_t err_detect; /* 0x0_2E40 Memory error detect w1c 0x0000_0000 9.4.1.24/9-33 */ + volatile uint32_t err_disable; /* 0x0_2E44 Memory error disable R/W 0x0000_0000 9.4.1.25/9-34 */ + volatile uint32_t err_int_en; /* 0x0_2E48 Memory error interrupt enable R/W 0x0000_0000 9.4.1.26/9-35 */ + volatile uint32_t capture_attributes; /* 0x0_2E4C Memory error attributes capture R/W 0x0000_0000 9.4.1.27/9-36 */ + volatile uint32_t capture_address; /* 0x0_2E50 Memory error address capture R/W 0x0000_0000 9.4.1.28/9-37 */ + uint8_t reserved0_2E54[0x02E58-0x02E54]; /* 0x0_2E54 Reserved $ $ */ + volatile uint32_t err_sbe; /* 0x0_2E58 Single-Bit ECC memory error management R/W 0x0000_0000 9.4.1.29/9-37 */ + uint8_t reserved0_2E5C[0x2F00-0x2E5C]; +} m83xxDDRRegisters_t; + + /* I2C Controller */ +typedef struct m83xxI2CRegisters_ { + volatile uint8_t i2cadr; /* 0x0_3000 I2C1 address register R/W 0x00 17.3.1.1/17-5 */ + uint8_t reserved0_3001[0x03004-0x03001]; + volatile uint8_t i2cfdr; /* 0x0_3004 I2C1 frequency divider register R/W 0x00 17.3.1.2/17-5 */ + uint8_t reserved0_3005[0x03008-0x03005]; + volatile uint8_t i2ccr; /* 0x0_3008 I2C1 control register R/W 0x00 17.3.1.3/17-6 */ + uint8_t reserved0_3009[0x0300C-0x03009]; + volatile uint8_t i2csr; /* 0x0_300C I2C1 status register R/W 0x81 17.3.1.4/17-8 */ + uint8_t reserved0_300D[0x03010-0x0300D]; + volatile uint8_t i2cdr; /* 0x0_3010 I2C1 data register R/W 0x00 17.3.1.5/17-9 */ + uint8_t reserved0_3011[0x03014-0x03011]; + volatile uint8_t i2cdfsrr; /* 0x0_3014 I2C1 digital filter sampling rate register R/W 0x0001_0000 17.3.1.6/17-10 */ + uint8_t reserved0_3015[0x03018-0x03015]; + uint8_t reserved0_3018[0x03100-0x03018]; /* 0x0_3018-30FF Reserved, should be cleared */ +} m83xxI2CRegisters_t; + + /* DUART */ +typedef struct m83xxDUARTRegisters_ { + union { + volatile uint8_t urbr; /* 0x0_4500 ULCR[DLAB] = 0 UART1 receiver buffer register R 0x00 18.3.1.1/18-6 */ + volatile uint8_t uthr; /* 0x0_4500 ULCR[DLAB] = 0 UART1 transmitter holding register W 0x00 18.3.1.2/18-6 */ + volatile uint8_t udlb; /* 0x0_4500 ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x00 18.3.1.3/18-7 */ + } urbr_uthr_udlb; + union { + volatile uint8_t uier; /* 0x0_4501 ULCR[DLAB] = 0 UART1 interrupt enable register R/W 0x00 18.3.1.4/18-8 */ + volatile uint8_t udmb; /* 0x0_4501 ULCR[DLAB] = 1 UART1 divisor most significant byte register R/W 0x00 18.3.1.3/18-7 */ + } uier_udmb; + union { + volatile uint8_t uiir; /* 0x0_4502 ULCR[DLAB] = 0 UART1 interrupt ID register R 0x01 18.3.1.5/18-9 */ + volatile uint8_t ufcr; /* 0x0_4502 ULCR[DLAB] = 0 UART1 FIFO control register W 0x00 18.3.1.6/18-10 */ + volatile uint8_t uafr; /* 0x0_4502 ULCR[DLAB] = 1 UART1 alternate function register R/W 0x00 18.3.1.12/18-16 */ + } uiir_ufcr_uafr; + volatile uint8_t ulcr; /* 0x0_4503 ULCR[DLAB] = x UART1 line control register R/W 0x00 18.3.1.7/18-11 */ + volatile uint8_t umcr; /* 0x0_4504 ULCR[DLAB] = x UART1 MODEM control register R/W 0x00 18.3.1.8/18-13 */ + volatile uint8_t ulsr; /* 0x0_4505 ULCR[DLAB] = x UART1 line status register R 0x60 18.3.1.9/18-14 */ + volatile uint8_t umsr; /* 0x0_4506 ULCR[DLAB] = x UART1 MODEM status register R 0x00 18.3.1.10/18-15 */ + volatile uint8_t uscr; /* 0x0_4507 ULCR[DLAB] = x UART1 scratch register R/W 0x00 18.3.1.11/18-16 */ + uint8_t reserved0_4508[0x04510-0x04508];/* 0x0_4508-450F Reserved */ + volatile uint8_t udsr; /* 0x0_4510 ULCR[DLAB] = x UART1 DMA status register R 0x01 18.3.1.13/18-17 */ + uint8_t reserved0_4511[0x04600-0x04511];/* 0x0_4511-45FF Reserved */ +} m83xxDUARTRegisters_t; + + /* Local Bus Controller (LBC) Registers */ +typedef struct m83xxLBCRegisters_ { + struct { + volatile uint32_t br; /* 0x0_5000 Base register 0 ,R/W 0x0000_RR01 10.3.1.1/10-11 */ + volatile uint32_t optionsr; /* 0x0_5004 Options register 0 R/W 0x0000_0FF7 10.3.1.2/10-12 */ + } bor[8]; + uint8_t reserved0_5040[0x05068-0x05040];/* 0x0_5040-5067 Reserved */ + volatile uint32_t mar; /* 0x0_5068 UPM address register R/W 0x0000_0000 10.3.1.3/10-18 */ + uint8_t reserved0_506C[0x05070-0x0506C];/* 0x0_506C-506F Reserved */ + volatile uint32_t mamr; /* 0x0_5070 UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19 */ + volatile uint32_t mbmr; /* 0x0_5074 UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19 */ + volatile uint32_t mcmr; /* 0x0_5078 UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19 */ + uint8_t reserved0_507C[0x05084-0x0507C];/* 0x0_507C-5083 Reserved */ + volatile uint32_t mrtpr; /* 0x0_5084 Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.5/10-21 */ + volatile uint32_t mdr; /* 0x0_5088 UPM data register R/W 0x0000_0000 10.3.1.6/10-22 */ + uint8_t reserved0_508C[0x05094-0x0508C];/* 0x0_508C-5093 Reserved */ + volatile uint32_t lsdmr; /* 0x0_5094 SDRAM mode register R/W 0x0000_0000 10.3.1.7/10-22 */ + uint8_t reserved0_5098[0x050A0-0x05098];/* 0x0_5098-509F Reserved */ + volatile uint32_t lurt; /* 0x0_50A0 UPM refresh timer R/W 0x0000_0000 10.3.1.8/10-24 */ + volatile uint32_t lsrt; /* 0x0_50A4 SDRAM refresh timer R/W 0x0000_0000 10.3.1.9/10-25 */ + uint8_t reserved0_50A8[0x050B0-0x050A8];/* 0x0_50A8-50AF Reserved */ + volatile uint32_t ltesr; /* 0x0_50B0 Transfer error status register Read/ bit-reset 0x0000_0000 10.3.1.10/10-26 */ + volatile uint32_t ltedr; /* 0x0_50B4 Transfer error check disable register R/W 0x0000_0000 10.3.1.11/10-27 */ + volatile uint32_t lteir; /* 0x0_50B8 Transfer error interrupt enable register R/W 0x0000_0000 10.3.1.12/10-27 */ + volatile uint32_t lteatr; /* 0x0_50BC Transfer error attributes register R/W 0x0000_0000 10.3.1.13/10-28 */ + volatile uint32_t ltear; /* 0x0_50C0 Transfer error address register R/W 0x0000_0000 10.3.1.14/10-29 */ + uint8_t reserved0_50C4[0x050D0-0x050C4];/* 0x0_50C4-50CF Reserved */ + volatile uint32_t lbcr; /* 0x0_50D0 Local bus configuration register R/W 0x0000_0000 10.3.1.15/10-29 */ + volatile uint32_t lcrr; /* 0x0_50D4 Clock ratio register R/W 0x8000_0008 10.3.1.16/10-30 */ + uint8_t reserved0_50D8[0x05100-0x050D8];/* 0x0_50D8-50FF Reserved */ +} m83xxLBCRegisters_t; + + /* Serial Peripheral Interface (SPI) */ +typedef struct m83xxSPIRegisters_ { + uint8_t reserved0_7000[0x07020-0x07000];/* 0x0_7000-7020 Reserved, should be cleared */ + volatile uint32_t spmode; /* 0x0_7020 SPI mode register R/W 0x0000_0000 19.4.1.1/19-9 */ + volatile uint32_t spie; /* 0x0_7024 SPI event register R/W 0x0000_0000 19.4.1.2/19-11 */ + volatile uint32_t spim; /* 0x0_7028 SPI mask register R/W 0x0000_0000 19.4.1.3/19-13 */ + volatile uint32_t spcom; /* 0x0_702C SPI command register R/W 0x0000_0000 19.4.1.4/19-14 */ + volatile uint32_t spitd; /* 0x0_7030 SPI transmit register R/W 0x0000_0000 19.4.1.5/19-14 */ + volatile uint32_t spird; /* 0x0_7034 SPI receive register R 0xFFFF_FFFF 19.4.1.6/19-15 */ + uint8_t reserved0_7038[0x07100-0x07038];/* 0x0_7038-70FF Reserved */ +} m83xxSPIRegisters_t; + /* SPIMODE register fields */ +#define MPC83XX_SPIMODE_LOOP (1 << (31- 1)) /* loopback */ +#define MPC83XX_SPIMODE_CI (1 << (31- 2)) /* clock invert */ +#define MPC83XX_SPIMODE_CP (1 << (31- 3)) /* clock phase */ +#define MPC83XX_SPIMODE_DIV16 (1 << (31- 4)) /* divide by 16 */ +#define MPC83XX_SPIMODE_REV (1 << (31- 5)) /* LSB first */ +#define MPC83XX_SPIMODE_M_S (1 << (31- 6)) /* master/slave */ +#define MPC83XX_SPIMODE_EN (1 << (31- 7)) /* enable */ +#define MPC83XX_SPIMODE_LEN(n) ((n) << (31-11)) /* length code */ +#define MPC83XX_SPIMODE_PM(n) ((n) << (31-15)) /* prescaler */ +#define MPC83XX_SPIMODE_OD (1 << (31-19)) /* open drain */ + + /* SPCOM register fields */ +#define MPC83XX_SPCOM_LST (1 << (31- 9)) /* last transfer */ + + /* SPIE/M register fields */ +#define MPC83XX_SPIE_LT (1 << (31-17)) /* last character transmitted */ +#define MPC83XX_SPIE_DNR (1 << (31-18)) /* data not ready */ +#define MPC83XX_SPIE_OV (1 << (31-19)) /* overrun */ +#define MPC83XX_SPIE_UN (1 << (31-20)) /* unterrun */ +#define MPC83XX_SPIE_MME (1 << (31-21)) /* multi-master error */ +#define MPC83XX_SPIE_NE (1 << (31-22)) /* not empty */ +#define MPC83XX_SPIE_NF (1 << (31-23)) /* not full */ + +typedef struct m83xxDMARegisters_ { + /* DMA Registers */ + uint8_t reserved0_8000[0x08030-0x08000];/* 0x0_8000-0x0_802f Reserved */ + volatile uint32_t omisr; /* 0x0_8030 Outbound message interrupt status register Special 0x0000_0000 12.4.1/12-4 */ + volatile uint32_t omimr; /* 0x0_8034 Outbound message interrupt mask register R/W 0x0000_0000 12.4.2/12-6 */ + uint8_t reserved0_8038[0x08050-0x08038];/* 0x0_8038-0x0_804f Reserved */ + volatile uint32_t imr0; /* 0x0_8050 Inbound message register 0 R/W 0x0000_0000 12.4.3/12-7 */ + volatile uint32_t imr1; /* 0x0_8054 Inbound message register 1 R/W 0x0000_0000 12.4.3/12-7 */ + volatile uint32_t omr0; /* 0x0_8058 Outbound message register 0 R/W 0x0000_0000 12.4.4/12-7 */ + volatile uint32_t omr1; /* 0x0_805C Outbound message register 1 R/W 0x0000_0000 12.4.4/12-7 */ + volatile uint32_t odr; /* 0x0_8060 Outbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */ + uint8_t reserved0_8064[0x08068-0x08064];/* 0x0_8064-0x0_8067 Reserved */ + volatile uint32_t idr; /* 0x0_8068 Inbound doorbell register R/W 0x0000_0000 12.4.5/12-8 */ + uint8_t reserved0_806C[0x08080-0x0806C];/* 0x0_806C-0x0_807F Reserved */ + volatile uint32_t imisr; /* 0x0_8080 Inbound message interrupt status register R/W 0x0000_0000 12.4.6/12-9 */ + volatile uint32_t imimr; /* 0x0_8084 Inbound message interrupt mask register R/W 0x0000_0000 12.4.7/12-11 */ + uint8_t reserved0_8088[0x080A8-0x08088];/* 0x0_8088-0x0_80A7 Reserved */ + struct m83xxDMAChannelRegisters_ { + uint8_t reserved0_80A8[0x08100-0x080A8];/* 0x0_80A8-0x0_80FF Reserved */ + volatile uint32_t dmamr0; /* 0x0_8100 DMA 0 mode register R/W 0x0000_0000 12.4.8.1/12-12 */ + volatile uint32_t dmasr0; /* 0x0_8104 DMA 0 status register R/W 0x0000_0000 12.4.8.2/12-14 */ + volatile uint32_t dmacdar0; /* 0x0_8108 DMA 0 current descriptor address register R/W 0x0000_0000 12.4.8.3/12-15 */ + uint8_t reserved0_810C[0x08110-0x0810C];/* 0x0_810C-0x0_810F Reserved */ + volatile uint32_t dmasar0; /* 0x0_8110 DMA 0 source address register R/W 0x0000_0000 12.4.8.4/12-16 */ + uint8_t reserved0_8114[0x08118-0x08114];/* 0x0_8114-0x0_8117 Reserved */ + volatile uint32_t dmadar0; /* 0x0_8118 DMA 0 destination address register R/W 0x0000_0000 12.4.8.5/12-16 */ + uint8_t reserved0_811C[0x08120-0x0811C];/* 0x0_8120-0x0_811C Reserved */ + volatile uint32_t dmabcr0; /* 0x0_8120 DMA 0 byte count register R/W 0x0000_0000 12.4.8.6/12-17 */ + volatile uint32_t dmandar0; /* 0x0_8124 DMA 0 next descriptor address register R/W 0x0000_0000 12.4.8.7/12-17 */ + }chan[4]; + volatile uint32_t dmagsr; /* 0x0_82A8 DMA general status register R 0x0000_0000 12.4.8.8/12-18 */ + uint8_t reserved0_82AC[0x082FF-0x082AC]; /* 0x0_82AC-0x0_82FF Reserved, should be cleared */ +} m83xxDMARegisters_t; + +/* Registers in DMA section use little-endian byte order */ + +/* DMA mode register */ +#define MPC83XX_DMAMR_DRCNT_1 (5 << 24) +#define MPC83XX_DMAMR_DRCNT_2 (6 << 24) +#define MPC83XX_DMAMR_DRCNT_4 (7 << 24) +#define MPC83XX_DMAMR_DRCNT_8 (8 << 24) +#define MPC83XX_DMAMR_DRCNT_16 (9 << 24) +#define MPC83XX_DMAMR_DRCNT_32 (0xA << 24) + +#define MPC83XX_DMAMR_BWC_1 (0 << 21) +#define MPC83XX_DMAMR_BWC_2 (1 << 21) +#define MPC83XX_DMAMR_BWC_4 (2 << 21) +#define MPC83XX_DMAMR_BWC_8 (3 << 21) +#define MPC83XX_DMAMR_BWC_16 (4 << 21) + +#define MPC83XX_DMAMR_DMSEN (1 << 20) +#define MPC83XX_DMAMR_IRQS (1 << 19) +#define MPC83XX_DMAMR_EMSEN (1 << 18) + +#define MPC83XX_DMAMR_DAHTS_1 (0 << 16) +#define MPC83XX_DMAMR_DAHTS_2 (1 << 16) +#define MPC83XX_DMAMR_DAHTS_4 (2 << 16) +#define MPC83XX_DMAMR_DAHTS_8 (3 << 16) + +#define MPC83XX_DMAMR_SAHTS_1 (0 << 14) +#define MPC83XX_DMAMR_SAHTS_2 (1 << 14) +#define MPC83XX_DMAMR_SAHTS_4 (2 << 14) +#define MPC83XX_DMAMR_SAHTS_8 (3 << 14) + +#define MPC83XX_DMAMR_DAHE (1 << 13) +#define MPC83XX_DMAMR_SAHE (1 << 12) + +#define MPC83XX_DMAMR_PRC_PCI_READ (0 << 10) +#define MPC83XX_DMAMR_PRC_PCI_READ_LINE (1 << 10) +#define MPC83XX_DMAMR_PRC_PCI_READ_MULTIPLE (2 << 10) + +#define MPC83XX_DMAMR_EOIIE (1 << 7) +#define MPC83XX_DMAMR_TEM (1 << 3) +#define MPC83XX_DMAMR_CTM (1 << 2) +#define MPC83XX_DMAMR_CC (1 << 1) +#define MPC83XX_DMAMR_CS (1 << 0) + +/* DMA status register */ +#define MPC83XX_DMASR_TE (1 << 7) +#define MPC83XX_DMASR_CB (1 << 2) +#define MPC83XX_DMASR_EOSI (1 << 1) +#define MPC83XX_DMASR_EOCDI (1 << 0) + +/* DMA current descriptor address register */ +#define MPC83XX_DMACDAR_SNEN (1 << 4) +#define MPC83XX_DMACDAR_EOSIE (1 << 3) + +/* DMA next descriptor address register */ +#define MPC83XX_DMANDAR_NSNEN (1 << 4) +#define MPC83XX_DMANDAR_NEOSIE (1 << 3) +#define MPC83XX_DMANDAR_EOTD (1 << 0) + + +typedef struct m83xxPCICfgRegisters_ { + /* PCI1 Software Configuration Registers */ + volatile uint32_t config_address; /* 0x0_8300 PCI1 CONFIG_ADDRESS W 13.3.1.1/13-16 */ + volatile uint32_t config_data; /* 0x0_8304 PCI1 CONFIG_DATA R/W 13.3.1.2/13-18 */ + volatile uint32_t int_ack; /* 0x0_8308 PCI1 INT_ACK R 13.3.1.3/13-18 */ + uint8_t reserved0_830C[0x08380-0x0830C]; /* 0x0_830C-0x0_837F Reserved */ +} m83xxPCICfgRegisters_t; + +typedef struct m83xxPCIIosRegisters_ { + /* Sequencer (IOS) */ + volatile uint32_t potar0; /* 0x0_8400 PCI outbound translation address register 0 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_8404[0x08408-0x08404];/* 0x0_8404 Reserved */ + volatile uint32_t pobar0; /* 0x0_8408 PCI outbound base address register 0 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_840C[0x08410-0x0840C];/* 0x0_840C Reserved */ + volatile uint32_t pocmr0; /* 0x0_8410 PCI outbound comparison mask register 0 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_8414[0x08418-0x08414];/* 0x0_8414 Reserved */ + volatile uint32_t potar1; /* 0x0_8418 PCI outbound translation address register 1 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_841C[0x08420-0x0841C];/* 0x0_841C Reserved */ + volatile uint32_t pobar1; /* 0x0_8420 PCI outbound base address register 1 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_8424[0x08428-0x08424];/* 0x0_8424 Reserved */ + volatile uint32_t pocmr1; /* 0x0_8428 PCI outbound comparison mask register 1 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_842C[0x08430-0x0842C];/* 0x0_842C Reserved */ + volatile uint32_t potar2; /* 0x0_8430 PCI outbound translation address register 2 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_8434[0x08438-0x08434];/* 0x0_8434 Reserved */ + volatile uint32_t pobar2; /* 0x0_8438 PCI outbound base address register 2 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_843C[0x08440-0x0843C];/* 0x0_843C Reserved */ + volatile uint32_t pocmr2; /* 0x0_8440 PCI outbound comparison mask register 2 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_8444[0x08448-0x08444];/* 0x0_8444 Reserved */ + volatile uint32_t potar3; /* 0x0_8448 PCI outbound translation address register 3 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_844C[0x08450-0x0844C];/* 0x0_844C Reserved */ + volatile uint32_t pobar3; /* 0x0_8450 PCI outbound base address register 3 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_8454[0x08458-0x08454];/* 0x0_8454 Reserved */ + volatile uint32_t pocmr3; /* 0x0_8458 PCI outbound comparison mask register 3 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_845C[0x08460-0x0845C];/* 0x0_845C Reserved */ + volatile uint32_t potar4; /* 0x0_8460 PCI outbound translation address register 4 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_8464[0x08468-0x08464];/* 0x0_8464 Reserved */ + volatile uint32_t pobar4; /* 0x0_8468 PCI outbound base address register 4 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_846C[0x08470-0x0846C];/* 0x0_846C Reserved */ + volatile uint32_t pocmr4; /* 0x0_8470 PCI outbound comparison mask register 4 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_8474[0x08478-0x08474];/* 0x0_8474 Reserved */ + volatile uint32_t potar5; /* 0x0_8478 PCI outbound translation address register 5 R/W 0x0000_0000 11.4.1/11-3 */ + uint8_t reserved0_847C[0x08480-0x0847C];/* 0x0_847C Reserved */ + volatile uint32_t pobar5; /* 0x0_8480 PCI outbound base address register 5 R/W 0x0000_0000 11.4.2/11-3 */ + uint8_t reserved0_8484[0x08488-0x08484];/* 0x0_8484 Reserved */ + volatile uint32_t pocmr5; /* 0x0_8488 PCI outbound comparison mask register 5 R/W 0x0000_0000 11.4.3/11-4 */ + uint8_t reserved0_848C[0x084F0-0x0848C];/* 0x0_848C Reserved */ + volatile uint32_t pmcr; /* 0x0_84F0 Power management control register R/W 0x0000_0000 11.4.4/11-5 */ + uint8_t reserved0_84F4[0x084F8-0x084F4];/* 0x0_84F4 Reserved */ + volatile uint32_t dtcr; /* 0x0_84F8 Discard timer control register R/W 0x0000_0000 11.4.5/11-6 */ + uint8_t reserved0_84FC[0x08500-0x084FC];/* 0x0_84FC Reserved */ +} m83xxPCIIosRegisters_t; + +typedef struct m83xxPCICtrlRegisters_ { + /* PCI1 Error Management Registers */ + volatile uint32_t pci_esr; /* 0x0_8500 PCI error status register R / w1c 0x0000_0000 13.3.2.1/13-18 */ + volatile uint32_t pci_ecdr; /* 0x0_8504 PCI error capture disable register R/W 0x0000_0000 13.3.2.2/13-19 */ + volatile uint32_t pci_eer; /* 0x0_8508 PCI error enable register R/W 0x0000_0000 13.3.2.3/13-20 */ + volatile uint32_t pci_eatcr; /* 0x0_850C PCI error attributes capture register R/W 0x0000_0000 13.3.2.4/13-21 */ + volatile uint32_t pci_eacr; /* 0x0_8510 PCI error address capture register R 0x0000_0000 13.3.2.5/13-23 */ + volatile uint32_t pci_eeacr; /* 0x0_8514 PCI error extended address capture register R 0x0000_0000 13.3.2.6/13-23 */ + volatile uint32_t pci_edlcr; /* 0x0_8518 PCI error data low capture register R 0x0000_0000 13.3.2.7/13-24 */ + volatile uint32_t pci_edhcr; /* 0x0_851C PCI error data high capture register R 0x0000_0000 13.3.2.8/13-24 */ + /* PCI1 Control and Status Registers */ + volatile uint32_t pci_gcr; /* 0x0_8520 PCI general control register R/W 0x0000_0000 13.3.2.9/13-24 */ + volatile uint32_t pci_ecr; /* 0x0_8524 PCI error control register R/W 0x0000_0000 13.3.2.10/13-25 */ + volatile uint32_t pci_gsr; /* 0x0_8528 PCI general status register R 0x0000_0000 13.3.2.11/13-26 */ + uint8_t reserved0_852C[0x08538-0x0852C];/* 0x0_852C Reserved */ + /* PCI1 Inbound ATU Registers */ + volatile uint32_t pitar2; /* 0x0_8538 PCI inbound translation address register 2 R/W 0x0000_0000 13.3.2.12/13-26 */ + uint8_t reserved0_853C[0x08540-0x0853C];/* 0x0_853C Reserved, should be cleared $ $ */ + volatile uint32_t pibar2; /* 0x0_8540 PCI inbound base address register 2 R/W 0x0000_0000 13.3.2.13/13-27 */ + volatile uint32_t piebar2; /* 0x0_8544 PCI inbound extended base address register 2 R/W 0x0000_0000 13.3.2.14/13-27 */ + volatile uint32_t piwar2; /* 0x0_8548 PCI inbound window attributes register 2 R/W 0x0000_0000 13.3.2.15/13-28 */ + uint8_t reserved0_854C[0x08550-0x0854C];/* 0x0_854C Reserved */ + volatile uint32_t pitar1; /* 0x0_8550 PCI inbound translation address register 1 R/W 0x0000_0000 13.3.2.12/13-26 */ + uint8_t reserved0_8550[0x08558-0x08554];/* 0x0_8554 Reserved, should be cleared $ $ */ + volatile uint32_t pibar1; /* 0x0_8558 PCI inbound base address register 1 R/W 0x0000_0000 13.3.2.13/13-27 */ + volatile uint32_t piebar1; /* 0x0_855C PCI inbound extended base address register 1 R/W 0x0000_0000 13.3.2.14/13-27 */ + volatile uint32_t piwar1; /* 0x0_8560 PCI inbound window attributes register 1 R/W 0x0000_0000 13.3.2.15/13-28 */ + uint8_t reserved0_8564[0x08568-0x08564];/* 0x0_8564 Reserved */ + volatile uint32_t pitar0; /* 0x0_8568 PCI inbound translation address register 0 R/W 0x0000_0000 13.3.2.12/13-26 */ + uint8_t reserved0_856c[0x08570-0x0856c];/* 0x0_856C Reserved, should be cleared $ $ */ + volatile uint32_t pibar0; /* 0x0_8570 PCI inbound base address register 0 R/W 0x0000_0000 13.3.2.13/13-27 */ + uint8_t reserved0_8574[0x08578-0x08574];/* 0x0_8574 Reserved */ + volatile uint32_t piwar0; /* 0x0_8578 PCI inbound window attributes register 0 R/W 0x0000_0000 13.3.2.14/13-27 */ + uint8_t reserved0_857c[0x08580-0x0857c];/* 0x0_857C Reserved, should be cleared $ $ */ + uint8_t reserved0_8580[0x08600-0x08580];/* 0x0_8580 Reserved */ +} m83xxPCICtrlRegisters_t; + +typedef struct m83xxUSB_MPHRegisters_ { + /* USB MPH Controller Registers */ + uint8_t reserved0x2_2000[0x22100-0x22000]; /* 0x2_2000--0x2_20FF Reserved, should be cleared */ + volatile uint16_t caplength; /* 0x2_2100 Capability register length R 0x40 16.3.1.1/16-19 */ + volatile uint16_t hciversion; /* 0x2_2102 Host interface version number R 0x0100 16.3.1.2/16-19 */ + volatile uint32_t hcsparams; /* 0x2_2104 Host crtl. structural parameters R 0x0121_0012 16.3.1.3/16-20 */ + volatile uint32_t hccparams; /* 0x2_2108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */ + uint8_t reserved0x2_210C[0x22140-0x2210C]; /* Reserved */ + volatile uint32_t usbcmd; /* 0x2_2140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */ + volatile uint32_t usbsts; /* 0x2_2144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */ + volatile uint32_t usbintr; /* 0x2_2148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */ + volatile uint32_t frindex; /* 0x2_214C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */ + uint8_t reserved0x2_2150[0x22154-0x22150]; /* Reserved */ + volatile uint32_t periodiclistbase; /* 0x2_2154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */ + volatile uint32_t asynclistaddr; /* 0x2_2158 Next asynchronous list addr R/W 0x0000_0000 16.3.2.8/16-32 */ + volatile uint32_t asyncttsts; /* 0x2_215C Asynchronous buffer status for embedded TT TBD 0x0000_0000 16.3.2.10/16-34 */ + volatile uint32_t burstsize; /* 0x2_2160 Programmable burst size R/W 0x000_1010 16.3.2.11/16-34 */ + volatile uint32_t txfilltuning; /* 0x2_2164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */ + volatile uint32_t txttfilltuning; /* 0x2_2168 Host TT transmit pre-buffer packet tuning R/W 0x0000_0000 16.3.2.13/16-37 */ + uint8_t reserved0x2_216c[0x22170-0x2216c]; /* Reserved */ + volatile uint32_t viewport; /* 0x2_2170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */ + uint8_t reserved0x2_2174[0x22180-0x22174]; /* Reserved */ + volatile uint32_t configflag; /* 0x2_2180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */ + volatile uint32_t portsc1; /* 0x2_2184 Port status/control 1 R/W 0x8C00_0001 16.3.2.16/16-39 */ + volatile uint32_t portsc2; /* 0x2_2188 Port status/control 2 R/W 0x8C00_0001 16.3.2.16/16-39 */ + uint8_t reserved0x2_218c[0x221A8-0x2218c]; /* Reserved */ + volatile uint32_t usbmode; /* 0x2_21A8 USB device mode R/W 0x0000_0003 16.3.2.18/16-47 */ + uint8_t reserved0x2_21AC[0x22400-0x221AC]; /* Reserved */ + volatile uint32_t snoop1; /* 0x2_2400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t snoop2; /* 0x2_2404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t age_cnt_thresh; /* 0x2_2408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */ + volatile uint32_t si_ctrl; /* 0x2_240C System interface control R/W 0x0000_0000 16.3.2.28/16-56 */ + volatile uint32_t pri_ctrl; /* 0x2_2410 Priority control R/W 0x0000_0000 16.3.2.29/16-56 */ + uint8_t reserved0x2_2414[0x22500-0x22414]; /* Reserved */ + volatile uint32_t control; /* 0x2_2500 Control R/W 0x0000_0000 16.3.2.30/16-57 */ + uint8_t reserved0x2_2504[0x23000-0x22504]; /* 0x2_2504--0x2_2FFF Reserved, should be cleared */ +} m83xxUSB_MPHRegisters_t; + +typedef struct m83xxUSB_DRRegisters_ { + /* USB DR Controller Registers */ + uint8_t reserved0x2_3000[0x23100-0x23000]; /* 0x2_3000--0x2_30FF Reserved, should be cleared */ + volatile uint16_t caplength; /* 0x2_3100 Capability register length R 0x40 16.3.1.1/16-19 */ + volatile uint16_t hciversion; /* 0x2_3102 Host interface version number R 0x0100 16.3.1.2/16-19 */ + volatile uint32_t hcsparams; /* 0x2_3104 Host crtl. structural parameters R 0x0111_0011 16.3.1.3/16-20 */ + volatile uint32_t hccparams; /* 0x2_3108 Host crtl. capability parameters R 0x0000_0006 16.3.1.4/16-21 */ + uint8_t reserved0x2_310c[0x23120-0x2310C]; /* 0x2_310c--0x2_311f Reserved */ + volatile uint32_t dciversion; /* 0x2_3120 Device interface version number R 0x0001 16.3.1.5/16-22 */ + volatile uint32_t dccparams; /* 0x2_3124 Device controller parameters R 0x0000_0186 16.3.1.6/16-22 */ + uint8_t reserved0x2_3128[0x23140-0x23128]; /* 0x2_3128--0x2_313f Reserved */ + volatile uint32_t usbcmd; /* 0x2_3140 USB command R/W 0x0008_nBn0 16.3.2.1/16-23 */ + volatile uint32_t usbsts; /* 0x2_3144 USB status R/W 0x0000_0000 16.3.2.2/16-26 */ + volatile uint32_t usbintr; /* 0x2_3148 USB interrupt enable R/W 0x0000_0000 16.3.2.3/16-28 */ + volatile uint32_t frindex; /* 0x2_314C USB frame index R/W 0x0000_nnnn 16.3.2.4/16-30 */ + uint8_t reserved0x2_3150[0x23154-0x23150]; /* 0x2_3150--0x2_3153 Reserved */ + union { + volatile uint32_t periodiclistbase; /* 0x2_3154 Frame list base address R/W 0xnnnn_0000 16.3.2.6/16-31 */ + volatile uint32_t deviceaddr; /* 0x2_3154 USB device address R/W 0x0000_0000 16.3.2.7/16-32 */ + } perbase_devaddr; + union { + volatile uint32_t asynclistaddr; /* 0x2_3158 Next asynchronous list addr (host mode) R/W 0x0000_0000 16.3.2.8/16-32 */ + volatile uint32_t addr; /* 0x2_3158 ENDPOINT Address at endpoint list (device mode) R/W 0x0000_0000 16.3.2.9/16-33 */ + } async_addr; + uint8_t reserved0x2_315c[0x23160-0x2315c]; /* 0x2_315c--0x2_315f Reserved */ + volatile uint32_t burstsize; /* 0x2_3160 Programmable burst size R/W 0x0000_1010 16.3.2.11/16-34 */ + volatile uint32_t txfilltuning; /* 0x2_3164 Host TT transmit pre-buffer packet tuning R/W 0x0002_0000 16.3.2.12/16-35 */ + uint8_t reserved0x2_3168[0x23170-0x23168]; /* 0x2_3168--0x2_316f Reserved */ + volatile uint32_t viewport; /* 0x2_3170 ULPI ULPI Register Access R/W 0x0000_0000 16.3.2.14/16-37 */ + uint8_t reserved0x2_3174[0x23180-0x23174]; /* 0x2_3174--0x2_317F Reserved */ + volatile uint32_t configflag; /* 0x2_3180 Configured flag register R 0x0000_0001 16.3.2.15/16-39 */ + volatile uint32_t portsc1; /* 0x2_3184 Port status/control R/W 0x9C00_0000 16.3.2.16/16-39 */ + uint8_t reserved0x2_3188[0x231A4-0x23188]; /* 0x2_3188--0x2_31A3 Reserved */ + volatile uint32_t otgsc; /* 0x2_31A4 On-the-Go status and control R/W 0x0000_0001 16.3.2.17/16-44 */ + volatile uint32_t usbmode; /* 0x2_31A8 USB device mode R/W 0x0000_0000 16.3.2.18/16-47 */ + volatile uint32_t endptsetupstat; /* 0x2_31AC Endpoint setup status R/W 0x0000_0000 16.3.2.19/16-48 */ + volatile uint32_t endpointprime; /* 0x2_31B0 Endpoint initialization R/W 0x0000_0000 16.3.2.20/16-48 */ + volatile uint32_t endptflush; /* 0x2_31B4 Endpoint de-initialize R/W 0x0000_0000 16.3.2.21/16-49 */ + volatile uint32_t endptstatus; /* 0x2_31B8 Endpoint status R 0x0000_0000 16.3.2.22/16-50 */ + volatile uint32_t endptcomplete; /* 0x2_31BC Endpoint complete R/W 0x0000_0000 16.3.2.23/16-50 */ + volatile uint32_t endptctrl[6]; /* 0x2_31C0 Endpoint control 0 R/W 0x0080_0080 16.3.2.24/16-51 */ + uint8_t reserved0x2_31D8[0x23400-0x231D8]; /* 0x2_31D8--0x2_33ff Reserved */ + volatile uint32_t snoop1; /* 0x2_3400 Snoop 1 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t snoop2; /* 0x2_3404 Snoop 2 R/W 0x0000_0000 16.3.2.26/16-53 */ + volatile uint32_t age_cnt_thresh; /* 0x2_3408 Age count threshold R/W 0x0000_0000 16.3.2.27/16-54 */ + volatile uint32_t pri_ctrl; /* 0x2_340C Priority control R/W 0x0000_0000 16.3.2.29/16-56 */ + volatile uint32_t si_ctrl; /* 0x2_3410 System interface control R/W 0x0000_0000 16.3.2.28/16-56 */ + uint8_t reserved0x2_3414[0x23500-0x23414]; /* 0x2_3414--0x2_34ff Reserved */ + volatile uint32_t control; /* 0x2_3500 Control R/W 0x0000_0000 16.3.2.30/16-57 */ + uint8_t reserved0x2_3504[0x24000-0x23504]; /* 0x2_3504--0x2_3FFF Reserved, should be cleared */ +} m83xxUSB_DRRegisters_t; + +#if 0 /* FIXME: to be formatted soon */ + /* Security Engine Address Map Registers */ + /* Controller Registers */ + volatile uint32_t reserved;## /* 0x3_0000--0x3_0FFF Reserved, should be cleared */ + volatile uint32_t imr; /* 0x3_1008 Interrupt mask register R/W 0x0000_0000_0000_0000 14.7.2.1/14-94 */ + volatile uint32_t isr; /* 0x3_1010 Interrupt status register R 0x0000_0000_0000_0000 14.7.2.2/14-96 */ + volatile uint32_t icr; /* 0x3_1018 Interrupt clear register W 0x0000_0000_0000_0000 14.7.2.3/14-96 */ + volatile uint32_t id; /* 0x3_1020 Identification register R 0x0000_0000_0000_00400x 14.7.2.4/14-98 */ + volatile uint32_t euasr; /* 0x3_1028 EU assignment status register R 0xF0F0_F0F0_00FF_F0F0 14.7.2/14-93 */ + volatile uint32_t mcr; /* 0x3_1030 Master control register R/W 0000_0000_0000_0000 14.7.2.5/14-98 */ + /* Channel 1 */ + volatile uint32_t cccr1; /* 0x3_1108 Crypto-channel 1 configuration register R/W 0x0000_0000_0000_0000 14.6.1.1/14-82 */ + volatile uint32_t ccpsr1; /* 0x3_1110 Crypto-channel 1 pointer status register R 0x0000_0000_0000_0007 14.6.1.2/14-85 */ + volatile uint32_t cdpr1; /* 0x3_1140 Crypto-channel 1 current descriptor pointer register R 0x0000_0000_0000_0000 14.6.1.3/14-90 */ + volatile uint32_t */ +0x3_1180--0x3_11BF + DBn /* volatile; uint32_t ff1, /* 0x3_1148 Crypto-channel 1 fetch FIFO address register W 0x0000_0000_0000_0000 14.6.1.4/14-90 Crypto-channel 1 descriptor buffers [0–7] R 0x0000_0000_0000_0000 14.6.1.5/14-91 */ + /* Channel 2-4: FIXME: same layout as channel 1*/ + /* Data Encryption Standard Execution Unit (DEU) */ + volatile uint32_t deumr; /* 0x3_2000 DEU mode register R/W 0x0000_0000_0000_0000 14.5.2.1/14-35 */ + volatile uint32_t deuksr; /* 0x3_2008 DEU key size register R/W 0x0000_0000_0000_0000 14.5.2.2/14-36 */ + volatile uint32_t deudsr; /* 0x3_2010 DEU data size register R/W 0x0000_0000_0000_0000 14.5.2.3/14-36 */ + volatile uint32_t deurcr; /* 0x3_2018 DEU reset control register R/W 0x0000_0000_0000_0000 14.5.2.4/14-37 */ + volatile uint32_t deusr; /* 0x3_2028 DEU status register R 0x0000_0000_0000_0000 14.5.2.5/14-37 */ + volatile uint32_t deuisr; /* 0x3_2030 DEU interrupt status register R 0x0000_0000_0000_0000 14.5.2.6/14-38 */ + volatile uint32_t deuicr; /* 0x3_2038 DEU interrupt control register R/W 0x0000_0000_0000_3000 14.5.2.7/14-40 */ + volatile uint32_t deueug; /* 0x3_2050 DEU EU-Go register W 0x0000_0000_0000_0000 14.5.2.8/14-41 */ + volatile uint32_t deuiv; /* 0x3_2100 DEU initialization vector register R/W 0x0000_0000_0000_0000 14.5.2.9/14-42 */ + volatile uint32_t deuk1; /* 0x3_2400 DEU key 1 register W $ 14.5.2.10/14-42 */ + volatile uint32_t deuk2; /* 0x3_2408 DEU key 2 register W $ 14.5.2.10/14-42 */ + volatile uint32_t deuk3; /* 0x3_2410 DEU key 3 register W $ 14.5.2.10/14-42 */ +0x3_2800--0x3_2FFF +DEU FIFO R/W 0x0000_0000_0000_0000 14.5.2.11/14-42 + /* Advanced Encryption Standard Execution Unit (AESU) */ + volatile uint32_t aesumr; /* 0x3_4000 AESU mode register R/W 0x0000_0000_0000_0000 14.5.6.1/14-68 */ + volatile uint32_t aesuksr; /* 0x3_4008 AESU key size register R/W 0x0000_0000_0000_0000 14.5.6.2/14-71 */ + volatile uint32_t aesudsr; /* 0x3_4010 AESU data size register R/W 0x0000_0000_0000_0000 14.5.6.3/14-71 */ + volatile uint32_t aesurcr; /* 0x3_4018 AESU reset control register R/W 0x0000_0000_0000_0000 14.5.6.4/14-72 */ + volatile uint32_t aesusr; /* 0x3_4028 AESU status register R 0x0000_0000_0000_0000 14.5.6.5/14-73 */ + volatile uint32_t aesuisr; /* 0x3_4030 AESU interrupt status register R 0x0000_0000_0000_0000 14.5.6.6/14-74 */ + volatile uint32_t aesuicr; /* 0x3_4038 AESU interrupt control register R/W 0x0000_0000_0000_1000 14.5.6.7/14-75 */ + volatile uint32_t aesuemr; /* 0x3_4050 AESU end-of-message register W 0x0000_0000_0000_0000 14.5.6.8/14-76 */ +0x3_4100 AESU context memory registers R/W 0x0000_0000_0000_0000 14.5.6.9/14-77 +0x3_4400--0x3_4408 +AESU key memory R/W 0x0000_0000_0000_0000 14.5.6.9.5/14-81 +0x3_4800--0x3_4FFF +AESU FIFO R/W 0x0000_0000_0000_0000 14.5.6.9.6/14-81 + /* Message Digest Execution Unit (MDEU) */ + volatile uint32_t mdeumr; /* 0x3_6000 MDEU mode register R/W 0x0000_0000_0000_0000 14.5.4.1/14-51 */ + volatile uint32_t mdeuksr; /* 0x3_6008 MDEU key size register R/W 0x0000_0000_0000_0000 14.5.4.3/14-55 */ + volatile uint32_t mdeudsr; /* 0x3_6010 MDEU data size register R/W 0x0000_0000_0000_0000 14.5.4.4/14-56 */ + volatile uint32_t mdeurcr; /* 0x3_6018 MDEU reset control register R/W 0x0000_0000_0000_0000 14.5.4.5/14-56 */ + volatile uint32_t mdeusr; /* 0x3_6028 MDEU status register R 0x0000_0000_0000_0000 14.5.4.6/14-57 */ + volatile uint32_t mdeuisr; /* 0x3_6030 MDEU interrupt status register R 0x0000_0000_0000_0000 14.5.4.7/14-58 */ + volatile uint32_t mdeuicr; /* 0x3_6038 MDEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.4.8/14-59 */ + volatile uint32_t mdeueug; /* 0x3_6050 MDEU EU-Go register W 0x0000_0000_0000_0000 14.5.4.10/14-61 */ +0x3_6100--0x3_6120 +MDEU context memory registers R/W 0x0000_0000_0000_0000 14.5.4.11/14-61 +0x3_6400--0x3_647F +MDEU key memory W 0x0000_0000_0000_0000 14.5.4.12/14-62 +0x3_6800--0x3_6FFF +MDEU FIFO W 0x0000_0000_0000_0000 14.5.4.13/14-63 + /* ARC Four Execution Unit (AFEU) */ + volatile uint32_t afeumr; /* 0x3_8000 AFEU mode register R/W 0x0000_0000_0000_0000 14.5.3.1/14-43 */ + volatile uint32_t afeuksr; /* 0x3_8008 AFEU key size register R/W 0x0000_0000_0000_0000 14.5.3.3/14-44 */ + volatile uint32_t afeudsr; /* 0x3_8010 AFEU data size register R/W 0x0000_0000_0000_0000 14.5.3.4/14-45 */ + volatile uint32_t afeurcr; /* 0x3_8018 AFEU reset control register R/W 0x0000_0000_0000_0000 14.5.3.5/14-46 */ + volatile uint32_t afeusr; /* 0x3_8028 AFEU status register R 0x0000_0000_0000_0000 14.5.3.6/14-46 */ + volatile uint32_t afeuisr; /* 0x3_8030 AFEU interrupt status register R 0x0000_0000_0000_0000 14.5.3.7/14-47 */ + volatile uint32_t afeuicr; /* 0x3_8038 AFEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.3.8/14-49 */ + volatile uint32_t afeuemr; /* 0x3_8050 AFEU end of message register W 0x0000_0000_0000_0000 14.5.3.9/14-50 */ +0x3_8100--0x3_81FF +AFEU context memory registers R/W 0x0000_0000_0000_0000 14.5.3.10.1/14-50 +0x3_8200 AFEU context memory pointers R/W 0x0000_0000_0000_0000 14.5.3.10.2/14-51 + volatile uint32_t afeuk0; /* 0x3_8400 AFEU key register 0 W $ 14.5.3.11/14-51 */ + volatile uint32_t afeuk1; /* 0x3_848 AFEU key register 1 W $ 14.5.3.11/14-51 */ +0x3_8800--0x3_8FFF +AFEU FIFO R/W 0x0000_0000_0000_0000 14.5.3.11.1/14-51 + /* Random Number Generator (RNG) */ + volatile uint32_t rngmr; /* 0x3_A000 RNG mode register R/W 0x0000_0000_0000_0000 14.5.5.1/14-63 */ + volatile uint32_t rngdsr; /* 0x3_A010 RNG data size register R/W 0x0000_0000_0000_0000 14.5.5.2/14-64 */ + volatile uint32_t rngrcr; /* 0x3_A018 RNG reset control register R/W 0x0000_0000_0000_0000 14.5.5.3/14-65 */ + volatile uint32_t rngsr; /* 0x3_A028 RNG status register R 0x0000_0000_0000_0000 14.5.5.4/14-65 */ + volatile uint32_t rngisr; /* 0x3_A030 RNG interrupt status register R 0x0000_0000 */ +_0000_0000 +14.5.5.5/14-66 + volatile uint32_t rngicr; /* 0x3_A038 RNG interrupt control register R/W 0x0000_0000 */ +_0000_1000 +14.5.5.6/14-67 + volatile uint32_t rngeug; /* 0x3_A050 RNG EU-Go register W 0x0000_0000 */ +_0000_0000 +14.5.5.7/14-68 +0x3_A800--0x3_AFFF +RNG FIFO R 0x0000_0000 +_0000_0000 +14.5.5.8/14-68 + /* Public Key Execution Unit (PKEU) */ + volatile uint32_t pkeumr; /* 0x3_C000 PKEU mode register R/W 0x0000_0000_0000_0000 14.5.1.1/14-26 */ + volatile uint32_t pkeuksr; /* 0x3_C008 PKEU key size register R/W 0x0000_0000_0000_0000 14.5.1.2/14-28 */ + volatile uint32_t pkeudsr; /* 0x3_C010 PKEU data size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */ + volatile uint32_t pkeurcr; /* 0x3_C018 PKEU reset control register R/W 0x0000_0000_0000_0000 14.5.1.5/14-29 */ + volatile uint32_t pkeusr; /* 0x3_C028 PKEU status register R 0x0000_0000_0000_0000 14.5.1.6/14-30 */ + volatile uint32_t pkeuisr; /* 0x3_C030 PKEU interrupt status register R 0x0000_0000_0000_0000 14.5.1.7/14-31 */ + volatile uint32_t pkeuicr; /* 0x3_C038 PKEU interrupt control register R/W 0x0000_0000_0000_1000 14.5.1.8/14-32 */ + volatile uint32_t pkeuabs; /* 0x3_C040 PKEU AB size register R/W 0x0000_0000_0000_0000 14.5.1.3/14-28 */ + volatile uint32_t pkeueug; /* 0x3_C050 PKEU EU-Go W 0x0000_0000_0000_0000 14.5.1.9/14-33 */ +0x3_C200--0x3_C23F +PKEU parameter memory A0 R/W 0x0000_0000_0000_0000 14.5.1.10/14-34 +0x3_C240--0x3_C27F +PKEU parameter memory A1 R/W 0x0000_0000_0000_0000 +0x3_C280--0x3_C2BF +PKEU parameter memory A2 R/W 0x0000_0000_0000_0000 +0x3_C2C0--0x3_C2FF +PKEU parameter memory A3 R/W 0x0000_0000_0000_0000 +0x3_C300--0x3_C33F +PKEU parameter memory B0 R/W 0x0000_0000_0000_0000 +0x3_C340--0x3_C37F +PKEU parameter memory B1 R/W 0x0000_0000_0000_0000 +0x3_C380--0x3_C3BF +PKEU parameter memory B2 R/W 0x0000_0000_0000_0000 +0x3_C3C0--0x3_C3FF +PKEU parameter memory B3 R/W 0x0000_0000_0000_0000 +0x3_C400--0x3_C4FF +PKEU parameter memory E W 0x0000_0000_0000_0000 +0x3_C800--0x3_C8FF +PKEU parameter memory N R/W 0x0000_0000_0000_0000 +#endif + +typedef struct m83xxRegisters_ { + m83xxSysConRegisters_t syscon; + m83xxWDTRegisters_t wdt; + uint8_t reserved0_0210[0x0300-0x0210]; + m83xxRTCRegisters_t rtc; + uint8_t reserved0_0320[0x0400-0x0320]; + m83xxPITRegisters_t pit; + m83xxGTMRegisters_t gtm[M83xxGTModCnt]; + m83xxIPICRegisters_t ipic; + m83xxARBRegisters_t arb; + m83xxRESRegisters_t res; + m83xxCLKRegisters_t clk; + m83xxPMCRegisters_t pmc; + m83xxGPIORegisters_t gpio[2]; + uint8_t reserved0_0E00[0x1000-0x0E00]; + m83xxDLLRegisters_t dll; + uint8_t reserved0_1200[0x2000-0x1200]; + m83xxDDRRegisters_t ddr; + uint8_t reserved0_2F00[0x3000-0x2F00]; + m83xxI2CRegisters_t i2c[2]; + uint8_t reserved0_3200[0x4000-0x3200]; + uint8_t reserved0_4000[0x4500-0x4000]; + m83xxDUARTRegisters_t duart[2]; + uint8_t reserved0_4700[0x5000-0x4700]; + m83xxLBCRegisters_t lbc; + uint8_t reserved0_5100[0x7000-0x5100]; + m83xxSPIRegisters_t spi; + uint8_t reserved0_7100[0x8000-0x7100]; + m83xxDMARegisters_t dma; + m83xxPCICfgRegisters_t pcicfg[2]; + m83xxPCIIosRegisters_t pciios; + m83xxPCICtrlRegisters_t pcictrl[2]; + uint8_t reserved0_8700[0x22000-0x8700]; + m83xxUSB_MPHRegisters_t usb_mph; + m83xxUSB_DRRegisters_t usb_dr; + volatile tsec_registers tsec[TSEC_COUNT]; +} m83xxRegisters_t; + +extern m83xxRegisters_t mpc83xx; + +static inline void mpc83xx_reset(void) +{ + _ISR_Set_level( 0 ); + + /* Set Reset Protection Register (RPR) to "RSTE" */ + mpc83xx.res.rpr = 0x52535445; + + /* + * Wait for Control Register Enabled in the + * Reset Control Enable Register (RCER). + */ + while (mpc83xx.res.rcer != 0x00000001) { + /* Wait */ + } + + /* Set Software Hard Reset in the Reset Control Register (RCR) */ + mpc83xx.res.rcr = 0x00000002; +} + +#endif /* !defined ASM */ +/* + * some definitions used in assembler startup + */ +/* + * default address of IMMRBAR + */ +#define IMMRBAR_DEFAULT 0xFF400000 +/* + * offsets of some registers + */ +#define LBLAWBAR0_OFF 0x00020 +#define LBLAWAR0_OFF 0x00024 +#define LBLAWBAR1_OFF 0x00028 +#define LBLAWAR1_OFF 0x0002C +#define LBLAWBAR2_OFF 0x00030 +#define LBLAWAR2_OFF 0x00034 +#define LBLAWBAR3_OFF 0x00038 +#define LBLAWAR3_OFF 0x0003C +#define PCILAWBAR0_OFF 0x00060 +#define PCILAWAR0_OFF 0x00064 +#define PCILAWBAR1_OFF 0x00068 +#define PCILAWAR1_OFF 0x0006C +#define DDRLAWBAR0_OFF 0x000A0 +#define DDRLAWAR0_OFF 0x000A4 +#define DDRLAWBAR1_OFF 0x000A8 +#define DDRLAWAR1_OFF 0x000AC + +#define BR0_OFF 0x05000 +#define OR0_OFF 0x05004 +#define BR1_OFF 0x05008 +#define OR1_OFF 0x0500C +#define BR2_OFF 0x05010 +#define OR2_OFF 0x05014 +#define BR3_OFF 0x05018 +#define OR3_OFF 0x0501C +#define BR4_OFF 0x05020 +#define OR4_OFF 0x05024 +#define BR5_OFF 0x05028 +#define OR5_OFF 0x0502C +#define BR6_OFF 0x05030 +#define OR6_OFF 0x05034 +#define BR7_OFF 0x05038 +#define OR7_OFF 0x0503C + +#define MRPTR_OFF 0x05084 +#define LSDMR_OFF 0x05094 +#define LSRT_OFF 0x050A4 +#define LCRR_OFF 0x050d4 + + +#define CS0_BNDS_OFF 0x02000 +#define CS1_BNDS_OFF 0x02008 +#define CS2_BNDS_OFF 0x02010 +#define CS3_BNDS_OFF 0x02018 +#define CS0_CONFIG_OFF 0x02080 +#define CS1_CONFIG_OFF 0x02084 +#define CS2_CONFIG_OFF 0x02088 +#define CS3_CONFIG_OFF 0x0208C +#define TIMING_CFG_3_OFF 0x02100 +#define TIMING_CFG_0_OFF 0x02104 +#define TIMING_CFG_1_OFF 0x02108 +#define TIMING_CFG_2_OFF 0x0210C +#define DDR_SDRAM_CFG_OFF 0x02110 +#define DDR_SDRAM_CFG_2_OFF 0x02114 +#define DDR_SDRAM_MODE_OFF 0x02118 +#define DDR_SDRAM_MODE_2_OFF 0x0211C +#define DDR_SDRAM_MD_CNTL_OFF 0x02120 +#define DDR_SDRAM_INTERVAL_OFF 0x02124 +#define DDR_SDRAM_DATA_INIT_OFF 0x02128 +#define DDRCDR_OFF 0x0012C +#define DDR_SDRAM_CLK_CNTL_OFF 0x02130 +#define DDR_SDRAM_INIT_ADDR_OFF 0x02148 +#define DDR_ERR_DISABLE_OFF 0x02E44 + +/* + * some bits in DDR_SDRAM_CFG register + */ +#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0)) /* enable memory */ +/* + * bits in DDR_SDRAM_CFG_2 register + */ +#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh */ +#define DDR_SDRAM_CFG_2_D_SR_IE (1 << (31- 1)) /* self refresh interrupt en */ +#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS (1 << (31- 2)) /* DLL reset disable */ +#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF (1 << (31- 5)) /* use diff. DQS */ +#define DDR_SDRAM_CFG_2_D_INIT (1 << (31-27)) /* Init DRAM with pattern */ + +/* + * bits in reset configuration words/registers + */ + /* Local bus clocking mode */ +#define RCWLR_LBIUCM_1_1 (0 << (31- 0)) /* 1:1 */ +#define RCWLR_LBIUCM_2_1 (1 << (31- 0)) /* 2:1 */ + /* DDR clocking mode */ +#define RCWLR_DDRCM_1_1 (0 << (31- 1)) /* 1:1 */ +#define RCWLR_DDRCM_2_1 (1 << (31- 1)) /* 2:1 */ + /* System PLL mult. factor */ +#define RCWLR_SPMF(n) (((n)&0xf)<<(31- 7)) + /* Core PLL mult. factor */ +#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) + +/* for MPC8309: */ +#define RCWLR_CEVCOD_1_8 (2<<(31-25)) /* QUICC internal PLL divider 1:8 */ +#define RCWLR_CEVCOD_1_4 (1<<(31-25)) /* QUICC internal PLL divider 1:4 */ +#define RCWLR_CEVCOD_1_2 (0<<(31-25)) /* QUICC internal PLL divider 1:2 */ + /* QUICC Engine PLL mult. factor */ +#define RCWLR_CEPDF_2 (1<<(31-26)) /* QUICC Engine divide PLL out by 2*/ + /* QUICC Engine PLL mult. factor */ +#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31)) + + /* PCI host mode */ +#define RCWHR_PCI_AGENT (0 << (31- 0)) /* agent mode */ +#define RCWHR_PCI_HOST (1 << (31- 0)) /* host mode */ + +#define RCWHR_PCI_32 (0 << (31- 1)) /* PCI bus width 32 bit */ +#define RCWHR_PCI_64 (1 << (31- 1)) /* PCI bus width 64 bit */ + +#define RCWHR_PCI1ARB_DIS (0 << (31- 2)) /* PCI1 arbiter disabled */ +#define RCWHR_PCI1ARB_EN (1 << (31- 2)) /* PCI1 arbiter enabled */ +#define RCWHR_PCI2ARB_DIS (0 << (31- 3)) /* PCI2 arbiter disabled */ +#define RCWHR_PCI2ARB_EN (1 << (31- 3)) /* PCI2 arbiter enabled */ + +#define RCWHR_CORE_DIS (1 << (31- 4)) /* CPU core disabled */ +#define RCWHR_CORE_EN (0 << (31- 4)) /* CPU core enabled */ + +#define RCWHR_BMS_LOW (0 << (31- 5)) /* Boot from low addr 0x00000100 */ +#define RCWHR_BMS_HIGH (1 << (31- 5)) /* Boot from high addr 0xFFF00100 */ + +#define RCWHR_BOOTSEQ_NONE (0 <<(31- 7)) /* Bootsequencer off */ +#define RCWHR_BOOTSEQ_NORM (1 <<(31- 7)) /* Bootsequencer normal I2C */ +#define RCWHR_BOOTSEQ_EXTD (2 <<(31- 7)) /* Bootsequencer extended I2C */ +#define RCWHR_BOOTSEQ_RSRV (3 <<(31- 7)) /* Bootsequencer reserved */ + +#define RCWHR_SW_DIS (0 << (31- 8)) /* Watchdog disabled */ +#define RCWHR_SW_EN (1 << (31- 8)) /* Watchdog enabled */ + +#define RCWHR_ROMLOC_DDR (0 << (31-11)) /* Initial ROM location:DDR Ram */ +#define RCWHR_ROMLOC_PCI1 (1 << (31-11)) /* Initial ROM location:PCI 1 */ +#define RCWHR_ROMLOC_PCI2 (2 << (31-11)) /* Initial ROM location:PCI 2 */ +#define RCWHR_ROMLOC_RSV1 (3 << (31-11)) /* Initial ROM location:Reserved */ +#define RCWHR_ROMLOC_RSV2 (4 << (31-11)) /* Initial ROM location:Reserved */ +#define RCWHR_ROMLOC_LB08 (5 << (31-11)) /* Initial ROM location:LBus 8bit*/ +#define RCWHR_ROMLOC_LB16 (6 << (31-11)) /* Initial ROM location:LBus 16bit*/ +#define RCWHR_ROMLOC_LB32 (7 << (31-11)) /* Initial ROM location:LBus 32bit*/ + +#define RCWHR_TSEC1M_RGMII (0 << (31-17)) /* TSEC1 Mode: RGMII */ +#define RCWHR_TSEC1M_RTBI (1 << (31-17)) /* TSEC1 Mode: RTBI */ +#define RCWHR_TSEC1M_GMII (2 << (31-17)) /* TSEC1 Mode: GMII */ +#define RCWHR_TSEC1M_TBI (3 << (31-17)) /* TSEC1 Mode: TBI */ + +#define RCWHR_TSEC2M_RGMII (0 << (31-19)) /* TSEC2 Mode: RGMII */ +#define RCWHR_TSEC2M_RTBI (1 << (31-19)) /* TSEC2 Mode: RTBI */ +#define RCWHR_TSEC2M_GMII (2 << (31-19)) /* TSEC2 Mode: GMII */ +#define RCWHR_TSEC2M_TBI (3 << (31-19)) /* TSEC2 Mode: TBI */ + +#define RCWHR_ENDIAN_BIG (0 << (31-28)) /* Big Endian Mode */ +#define RCWHR_ENDIAN_LIT (1 << (31-28)) /* True Little Endian Mode */ + +#define RCWHR_LALE_NORM (0 << (31-29)) /* normal LALE timing */ +#define RCWHR_LALE_EARLY (1 << (31-29)) /* early LALE negation */ + +#define RCWHR_LDP_PAR (0 << (31-30)) /* LDP0-3 are parity pins */ +#define RCWHR_LDP_SPC (1 << (31-30)) /* LDP0-3 are special pins */ + +/* + * For MPC8309: + */ +#define RCWHR_RLEXT_LGCY (0 << (31-13)) /* Boot ROM loc. extension: Legacy */ +#define RCWHR_RLEXT_NAND (1 << (31-13)) /* Boot ROM loc. extension: NAND Fl.*/ +#define RCWHR_RLEXT_RSV2 (2 << (31-13)) /* Boot ROM loc. extension: resrvd */ +#define RCWHR_RLEXT_RSV3 (3 << (31-13)) /* Boot ROM loc. extension: resrvd */ +#endif /* _MPC83XX_MPC83XX_H */ diff --git a/bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h b/bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h new file mode 100644 index 0000000000..206cb87cb4 --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/mpc83xx_i2cdrv.h @@ -0,0 +1,68 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the MPC83xx I2C driver declarations | +\*===============================================================*/ +#ifndef _MPC83XX_I2CDRV_H +#define _MPC83XX_I2CDRV_H + +#include <rtems/libi2c.h> +#include <rtems/irq.h> + +#include <bsp.h> + +#ifdef LIBBSP_POWERPC_GEN83XX_BSP_H + #include <mpc83xx/mpc83xx.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef LIBBSP_POWERPC_MPC55XXEVB_BSP_H + typedef struct { + volatile uint8_t i2cadr; + volatile uint8_t i2cfdr; + volatile uint8_t i2ccr; + volatile uint8_t i2csr; + volatile uint8_t i2cdr; + volatile uint8_t i2cdfsrr; + } m83xxI2CRegisters_t; +#endif + +typedef struct mpc83xx_i2c_softc { + m83xxI2CRegisters_t *reg_ptr; /* ptr to HW registers */ + int initialized; /* TRUE: module is initialized */ + rtems_irq_number irq_number; /* IRQ number used for this module */ + uint32_t base_frq; /* input frq for baud rate divider */ + rtems_id irq_sema_id; /* SEMA used for IRQ signalling */ + void (*probe)(struct mpc83xx_i2c_softc *self); +} mpc83xx_i2c_softc_t ; + +typedef struct { + rtems_libi2c_bus_t bus_desc; + struct mpc83xx_i2c_softc softc; +} mpc83xx_i2c_desc_t; + + +extern rtems_libi2c_bus_ops_t mpc83xx_i2c_ops; + +#ifdef __cplusplus +} +#endif + + +#endif /* _MPC83XX_I2CDRV_H */ diff --git a/bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h b/bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h new file mode 100644 index 0000000000..92fe66831a --- /dev/null +++ b/bsps/powerpc/include/mpc83xx/mpc83xx_spidrv.h @@ -0,0 +1,172 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC83xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the MPC83xx SPI driver declarations | +| NOTE: this driver has the same API as a I2C driver | +\*===============================================================*/ +#ifndef _MPC83XX_SPIDRV_H +#define _MPC83XX_SPIDRV_H + +#include <mpc83xx/mpc83xx.h> +#include <rtems/libi2c.h> +#include <rtems/irq.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct mpc83xx_spi_softc { + m83xxSPIRegisters_t *reg_ptr; + int initialized; + rtems_irq_number irq_number; + uint32_t base_frq; /* input frq for baud rate divider */ + rtems_id irq_sema_id; + uint32_t curr_addr; /* current spi address */ + uint32_t idle_char; + uint8_t bytes_per_char; + uint8_t bit_shift; +} mpc83xx_spi_softc_t ; + +typedef struct { + rtems_libi2c_bus_t bus_desc; + mpc83xx_spi_softc_t softc; +} mpc83xx_spi_desc_t; + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code mpc83xx_spi_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the driver | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh /* bus specifier structure */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_read_write_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| transmit/receive some bytes from SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *rbuf, /* buffer to store bytes */ + const unsigned char *tbuf, /* buffer to send bytes */ + int len /* number of bytes to transceive */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes received or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_read_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| receive some bytes from SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to store bytes */ + int len /* number of bytes to receive */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes received or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_write_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| send some bytes to SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to send */ + int len /* number of bytes to send */ + + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes sent or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code mpc83xx_spi_set_tfr_mode +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| set SPI to desired baudrate/clock mode/character mode | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int mpc83xx_spi_ioctl +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| perform selected ioctl function for SPI | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + int cmd, /* ioctl command code */ + void *arg /* additional argument array */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +#ifdef __cplusplus +} +#endif + + +#endif /* _MPC83XX_I2CDRV_H */ diff --git a/bsps/powerpc/include/mpc8xx.h b/bsps/powerpc/include/mpc8xx.h new file mode 100644 index 0000000000..3222e7fd03 --- /dev/null +++ b/bsps/powerpc/include/mpc8xx.h @@ -0,0 +1,1499 @@ +/* +************************************************************************** +************************************************************************** +** ** +** MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR ** +** ** +** HARDWARE DECLARATIONS ** +** ** +** ** +** Submitted By: ** +** ** +** W. Eric Norum ** +** Saskatchewan Accelerator Laboratory ** +** University of Saskatchewan ** +** 107 North Road ** +** Saskatoon, Saskatchewan, CANADA ** +** S7N 5C6 ** +** ** +** eric@skatter.usask.ca ** +** ** +** Modified for use with the MPC860 (original code was for MC68360) ** +** by ** +** Jay Monkman ** +** Frasca International, Inc. ** +** 906 E. Airport Rd. ** +** Urbana, IL, 61801 ** +** ** +** jmonkman@frasca.com ** +** ** +** Modified further for use with the MPC821 by: ** +** Andrew Bray <andy@chaos.org.uk> ** +** ** +** With some corrections/additions by: ** +** Darlene A. Stewart and ** +** Charles-Antoine Gauthier ** +** Institute for Information Technology ** +** National Research Council of Canada ** +** Ottawa, ON K1A 0R6 ** +** ** +** Darlene.Stewart@iit.nrc.ca ** +** charles.gauthier@iit.nrc.ca ** +** ** +** Corrections/additions: ** +** Copyright (c) 1999, National Research Council of Canada ** +************************************************************************** +************************************************************************** +*/ +#ifndef _MPC8XX_H +#define _MPC8XX_H + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Macros for accessing Special Purpose Registers (SPRs) + */ +#define _mtspr(_spr,_reg) __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) +#define _mfspr(_reg,_spr) __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) ) + +#define _isync __asm__ volatile ("isync\n"::) + +/* + * Core Registers (SPRs) + */ +#define M8xx_DEC 22 /* Decrementer Register */ +#define M8xx_DER 149 /* Debug Enable Register */ +#define M8xx_ICTRL 158 /* Instruction Support Control Register */ +#define M8xx_TBL_WR 284 /* Timebase Lower Write Register */ +#define M8xx_TBU_WR 285 /* Timebase Upper Write Register */ +#define M8xx_IMMR 638 /* Internal Memory Map Register */ + +/* + * Cache Control Registers (SPRs) + */ +#define M8xx_IC_CST 560 /* Instruction Cache Control and Status Register */ +#define M8xx_DC_CST 568 /* Data Cache Control and Status Register */ +#define M8xx_IC_ADR 561 /* Instruction Cache Address Register */ +#define M8xx_DC_ADR 569 /* Data Cache Address Register */ +#define M8xx_IC_DAT 562 /* Instruction Cache Data Port Register */ +#define M8xx_DC_DAT 570 /* Data Cache Data Port Register */ + +/* + * MMU Registers (SPRs) + */ +/* Control Registers */ +#define M8xx_MI_CTR 784 /* IMMU Control Register */ +#define M8xx_MD_CTR 792 /* DMMU Control Register */ +/* TLB Source Registers */ +#define M8xx_MI_EPN 787 /* IMMU Effective Page Number Register (EPN) */ +#define M8xx_MD_EPN 795 /* DMMU Effective Page Number Register (EPN) */ +#define M8xx_MI_TWC 789 /* IMMU Tablewalk Control Register (TWC) */ +#define M8xx_MD_TWC 797 /* DMMU Tablewalk Control Register (TWC) */ +#define M8xx_MI_RPN 790 /* IMMU Real (physical) Page Number Register (RPN) */ +#define M8xx_MD_RPN 798 /* DMMU Real (physical) Page Number Register (RPN) */ +/* Tablewalk Assist Registers */ +#define M8xx_M_TWB 796 /* MMU Tablewalk Base Register (TWB) */ +/* Protection Registers */ +#define M8xx_M_CASID 793 /* MMU Current Address Space ID Register */ +#define M8xx_MI_AP 786 /* IMMU Access Protection Register */ +#define M8xx_MD_AP 794 /* DMMU Access Protection Register */ +/* Scratch Register */ +#define M8xx_M_TW 799 /* MMU Tablewalk Special Register */ +/* Debug Registers */ +#define M8xx_MI_CAM 816 /* IMMU CAM Entry Read Register */ +#define M8xx_MI_RAM0 817 /* IMMU RAM Entry Read Register 0 */ +#define M8xx_MI_RAM1 818 /* IMMU RAM Entry Read Register 1 */ +#define M8xx_MD_CAM 824 /* DMMU CAM Entry Read Register */ +#define M8xx_MD_RAM0 825 /* DMMU RAM Entry Read Register 0 */ +#define M8xx_MD_RAM1 826 /* DMMU RAM Entry Read Register 1 */ + +#define M8xx_MI_CTR_GPM (1<<31) +#define M8xx_MI_CTR_PPM (1<<30) +#define M8xx_MI_CTR_CIDEF (1<<29) +#define M8xx_MI_CTR_RSV4I (1<<27) +#define M8xx_MI_CTR_PPCS (1<<25) +#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8) /* ITLB index */ + +#define M8xx_MD_CTR_GPM (1<<31) +#define M8xx_MD_CTR_PPM (1<<30) +#define M8xx_MD_CTR_CIDEF (1<<29) +#define M8xx_MD_CTR_WTDEF (1<<28) +#define M8xx_MD_CTR_RSV4D (1<<27) +#define M8xx_MD_CTR_TWAM (1<<26) +#define M8xx_MD_CTR_PPCS (1<<25) +#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8) /* DTLB index */ + +#define M8xx_MI_EPN_VALID (1<<9) + +#define M8xx_MD_EPN_VALID (1<<9) + +#define M8xx_MI_TWC_G (1<<4) +#define M8xx_MI_TWC_PSS (0<<2) +#define M8xx_MI_TWC_PS512 (1<<2) +#define M8xx_MI_TWC_PS8 (3<<2) +#define M8xx_MI_TWC_VALID (1) + +#define M8xx_MD_TWC_G (1<<4) +#define M8xx_MD_TWC_PSS (0<<2) +#define M8xx_MD_TWC_PS512 (1<<2) +#define M8xx_MD_TWC_PS8 (3<<2) +#define M8xx_MD_TWC_WT (1<<1) +#define M8xx_MD_TWC_VALID (1) + +#define M8xx_MI_RPN_F (0xf<<4) +#define M8xx_MI_RPN_16K (1<<3) +#define M8xx_MI_RPN_SHARED (1<<2) +#define M8xx_MI_RPN_CI (1<<1) +#define M8xx_MI_RPN_VALID (1) + +#define M8xx_MD_RPN_CHANGE (1<<8) +#define M8xx_MD_RPN_F (0xf<<4) +#define M8xx_MD_RPN_16K (1<<3) +#define M8xx_MD_RPN_SHARED (1<<2) +#define M8xx_MD_RPN_CI (1<<1) +#define M8xx_MD_RPN_VALID (1) + +#define M8xx_MI_AP_Kp (1) + +#define M8xx_MD_AP_Kp (1) + +#define M8xx_CACHE_CMD_SFWT (0x1<<24) +#define M8xx_CACHE_CMD_ENABLE (0x2<<24) +#define M8xx_CACHE_CMD_CFWT (0x3<<24) +#define M8xx_CACHE_CMD_DISABLE (0x4<<24) +#define M8xx_CACHE_CMD_STLES (0x5<<24) +#define M8xx_CACHE_CMD_LLCB (0x6<<24) +#define M8xx_CACHE_CMD_CLES (0x7<<24) +#define M8xx_CACHE_CMD_UNLOCK (0x8<<24) +#define M8xx_CACHE_CMD_UNLOCKALL (0xa<<24) +#define M8xx_CACHE_CMD_INVALIDATE (0xc<<24) +#define M8xx_CACHE_CMD_FLUSH (0xe<<24) + +/* +************************************************************************* +* REGISTER SUBBLOCKS * +************************************************************************* +*/ + +/* + * Memory controller registers + */ +typedef struct m8xxMEMCRegisters_ { + uint32_t _br; + uint32_t _or; /* Used to be called 'or'; reserved ANSI C++ keyword */ +} m8xxMEMCRegisters_t; + +/* + * Serial Communications Controller registers + */ +typedef struct m8xxSCCRegisters_ { + uint32_t gsmr_l; + uint32_t gsmr_h; + uint16_t psmr; + uint16_t _pad0; + uint16_t todr; + uint16_t dsr; + uint16_t scce; + uint16_t _pad1; + uint16_t sccm; + uint8_t _pad2; + uint8_t sccs; + uint32_t _pad3[2]; +} m8xxSCCRegisters_t; + +/* + * Serial Management Controller registers + */ +typedef struct m8xxSMCRegisters_ { + uint16_t _pad0; + uint16_t smcmr; + uint16_t _pad1; + uint8_t smce; + uint8_t _pad2; + uint16_t _pad3; + uint8_t smcm; + uint8_t _pad4; + uint32_t _pad5; +} m8xxSMCRegisters_t; + +/* + * Fast Ethernet Controller registers (Only on MPC8xxT) + */ +typedef struct m8xxFECRegisters_ { + uint32_t addr_low; + uint32_t addr_high; + uint32_t hash_table_high; + uint32_t hash_table_low; + uint32_t r_des_start; + uint32_t x_des_start; + uint32_t r_buf_size; + uint32_t _pad0[9]; + uint32_t ecntrl; + uint32_t ievent; + uint32_t imask; + uint32_t ivec; + uint32_t r_des_active; + uint32_t x_des_active; + uint32_t _pad1[10]; + uint32_t mii_data; + uint32_t mii_speed; + uint32_t _pad2[17]; + uint32_t r_bound; + uint32_t r_fstart; + uint32_t _pad3[6]; + uint32_t x_fstart; + uint32_t _pad4[17]; + uint32_t fun_code; + uint32_t _pad5[3]; + uint32_t r_cntrl; + uint32_t r_hash; + uint32_t _pad6[14]; + uint32_t x_cntrl; + uint32_t _pad7[30]; + +} m8xxFECRegisters_t; + +#define M8xx_FEC_IEVENT_HBERR (1 << 31) +#define M8xx_FEC_IEVENT_BABR (1 << 30) +#define M8xx_FEC_IEVENT_BABT (1 << 29) +#define M8xx_FEC_IEVENT_GRA (1 << 28) +#define M8xx_FEC_IEVENT_TFINT (1 << 27) +#define M8xx_FEC_IEVENT_TXB (1 << 26) +#define M8xx_FEC_IEVENT_RFINT (1 << 25) +#define M8xx_FEC_IEVENT_RXB (1 << 24) +#define M8xx_FEC_IEVENT_MII (1 << 23) +#define M8xx_FEC_IEVENT_EBERR (1 << 22) +#define M8xx_FEC_IMASK_HBEEN (1 << 31) +#define M8xx_FEC_IMASK_BREEN (1 << 30) +#define M8xx_FEC_IMASK_BTEN (1 << 29) +#define M8xx_FEC_IMASK_GRAEN (1 << 28) +#define M8xx_FEC_IMASK_TFIEN (1 << 27) +#define M8xx_FEC_IMASK_TBIEN (1 << 26) +#define M8xx_FEC_IMASK_RFIEN (1 << 25) +#define M8xx_FEC_IMASK_RBIEN (1 << 24) +#define M8xx_FEC_IMASK_MIIEN (1 << 23) +#define M8xx_FEC_IMASK_EBERREN (1 << 22) + + /* + * access macros to write to mii_data register + */ +#define M8xx_FEC_MII_DATA_ST ( 1 << (31- 1)) +#define M8xx_FEC_MII_DATA_OP_RD ( 2 << (31- 3)) +#define M8xx_FEC_MII_DATA_OP_WR ( 1 << (31- 3)) +#define M8xx_FEC_MII_DATA_PHYAD(n) (((n) & 0x3f) << (31- 8)) +#define M8xx_FEC_MII_DATA_PHYRA(n) (((n) & 0x3f) << (31-13)) +#define M8xx_FEC_MII_DATA_TA ( 2 << (31-15)) +#define M8xx_FEC_MII_DATA_WDATA(n) ((n) & 0xffff ) +#define M8xx_FEC_MII_DATA_RDATA(reg) ((reg) & 0xffff ) + /* + * bits for FEC X_CNTRL register + */ +#define M8xx_FEC_X_CNTRL_FDEN ( 1 << (31-29)) +#define M8xx_FEC_X_CNTRL_HBC ( 1 << (31-30)) +#define M8xx_FEC_X_CNTRL_GTS ( 1 << (31-31)) +/* +************************************************************************* +* Miscellaneous Parameters * +************************************************************************* +*/ +typedef struct m8xxMiscParms_ { + uint16_t rev_num; + uint16_t _res1; + uint32_t _res2; + uint32_t _res3; +} m8xxMiscParms_t; + +/* +************************************************************************* +* RISC Timers * +************************************************************************* +*/ +typedef struct m8xxTimerParms_ { + uint16_t tm_base; + uint16_t _tm_ptr; + uint16_t _r_tmr; + uint16_t _r_tmv; + uint32_t tm_cmd; + uint32_t tm_cnt; +} m8xxTimerParms_t; + +/* + * RISC Controller Configuration Register (RCCR) + * All other bits in this register are reserved. + */ +#define M8xx_RCCR_TIME (1<<15) /* Enable timer */ +#define M8xx_RCCR_TIMEP(x) ((x)<<8) /* Timer period */ +#define M8xx_RCCR_DR1M (1<<7) /* IDMA Rqst 1 Mode */ +#define M8xx_RCCR_DR0M (1<<6) /* IDMA Rqst 0 Mode */ +#define M8xx_RCCR_DRQP(x) ((x)<<4) /* IDMA Rqst Priority */ +#define M8xx_RCCR_EIE (1<<3) /* External Interrupt Enable */ +#define M8xx_RCCR_SCD (1<<2) /* Scheduler Configuration */ +#define M8xx_RCCR_ERAM(x) (x) /* Enable RAM Microcode */ + +/* + * Command register + * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command. + */ +#define M8xx_TM_CMD_V (1<<31) /* Set to enable timer */ +#define M8xx_TM_CMD_R (1<<30) /* Set for automatic restart */ +#define M8xx_TM_CMD_PWM (1<<29) /* Set for PWM operation */ +#define M8xx_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ +#define M8xx_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ + +/* +************************************************************************* +* DMA Controllers * +************************************************************************* +*/ +typedef struct m8xxIDMAparms_ { + uint16_t ibase; + uint16_t dcmr; + uint32_t _sapr; + uint32_t _dapr; + uint16_t ibptr; + uint16_t _write_sp; + uint32_t _s_byte_c; + uint32_t _d_byte_c; + uint32_t _s_state; + uint32_t _itemp[4]; + uint32_t _sr_mem; + uint16_t _read_sp; + uint16_t _res0; + uint16_t _res1; + uint16_t _res2; + uint32_t _d_state; +} m8xxIDMAparms_t; + + +/* +************************************************************************* +* DSP * +************************************************************************* +*/ +typedef struct m8xxDSPparms_ { + uint32_t fdbase; + uint32_t _fd_ptr; + uint32_t _dstate; + uint32_t _pad0; + uint16_t _dstatus; + uint16_t _i; + uint16_t _tap; + uint16_t _cbase; + uint16_t _pad1; + uint16_t _xptr; + uint16_t _pad2; + uint16_t _yptr; + uint16_t _m; + uint16_t _pad3; + uint16_t _n; + uint16_t _pad4; + uint16_t _k; + uint16_t _pad5; +} m8xxDSPparms_t; + +/* +************************************************************************* +* Serial Communication Controllers * +************************************************************************* +*/ +typedef struct m8xxSCCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + uint32_t _rcrc; + uint32_t _tcrc; + union { + struct { + uint32_t _res0; + uint32_t _res1; + uint16_t max_idl; + uint16_t _idlc; + uint16_t brkcr; + uint16_t parec; + uint16_t frmec; + uint16_t nosec; + uint16_t brkec; + uint16_t brkln; + uint16_t uaddr[2]; + uint16_t _rtemp; + uint16_t toseq; + uint16_t character[8]; + uint16_t rccm; + uint16_t rccr; + uint16_t rlbc; + } uart; + } un; +} m8xxSCCparms_t; + +typedef struct m8xxSCCENparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + uint32_t _rcrc; + uint32_t _tcrc; + union { + struct { + uint32_t _res0; + uint32_t _res1; + uint16_t max_idl; + uint16_t _idlc; + uint16_t brkcr; + uint16_t parec; + uint16_t frmec; + uint16_t nosec; + uint16_t brkec; + uint16_t brkln; + uint16_t uaddr[2]; + uint16_t _rtemp; + uint16_t toseq; + uint16_t character[8]; + uint16_t rccm; + uint16_t rccr; + uint16_t rlbc; + } uart; + struct { + uint32_t c_pres; + uint32_t c_mask; + uint32_t crcec; + uint32_t alec; + uint32_t disfc; + uint16_t pads; + uint16_t ret_lim; + uint16_t _ret_cnt; + uint16_t mflr; + uint16_t minflr; + uint16_t maxd1; + uint16_t maxd2; + uint16_t _maxd; + uint16_t dma_cnt; + uint16_t _max_b; + uint16_t gaddr1; + uint16_t gaddr2; + uint16_t gaddr3; + uint16_t gaddr4; + uint32_t _tbuf0data0; + uint32_t _tbuf0data1; + uint32_t _tbuf0rba0; + uint32_t _tbuf0crc; + uint16_t _tbuf0bcnt; + uint16_t paddr_h; + uint16_t paddr_m; + uint16_t paddr_l; + uint16_t p_per; + uint16_t _rfbd_ptr; + uint16_t _tfbd_ptr; + uint16_t _tlbd_ptr; + uint32_t _tbuf1data0; + uint32_t _tbuf1data1; + uint32_t _tbuf1rba0; + uint32_t _tbuf1crc; + uint16_t _tbuf1bcnt; + uint16_t _tx_len; + uint16_t iaddr1; + uint16_t iaddr2; + uint16_t iaddr3; + uint16_t iaddr4; + uint16_t _boff_cnt; + uint16_t taddr_m; + uint16_t taddr_l; + uint16_t taddr_h; + } ethernet; + } un; +} m8xxSCCENparms_t; + +/* + * Receive and transmit function code register bits + * These apply to the function code registers of all devices, not just SCC. + */ +#define M8xx_RFCR_BO(x) ((x)<<3) +#define M8xx_RFCR_MOT (2<<3) +#define M8xx_RFCR_DMA_SPACE(x) (x) +#define M8xx_TFCR_BO(x) ((x)<<3) +#define M8xx_TFCR_MOT (2<<3) +#define M8xx_TFCR_DMA_SPACE(x) (x) + +/* + * Event and mask registers (SCCE, SCCM) + */ +#define M8xx_SCCE_BRKE (1<<6) +#define M8xx_SCCE_BRK (1<<4) +#define M8xx_SCCE_BSY (1<<2) +#define M8xx_SCCE_TX (1<<1) +#define M8xx_SCCE_RX (1<<0) + +/* +************************************************************************* +* Serial Management Controllers * +************************************************************************* +*/ +typedef struct m8xxSMCparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; + union { + struct { + uint16_t max_idl; + uint16_t _idlc; + uint16_t brkln; + uint16_t brkec; + uint16_t brkcr; + uint16_t _r_mask; + } uart; + struct { + uint16_t _pad0[5]; + } transparent; + } un; +} m8xxSMCparms_t; + +/* + * Mode register + */ +#define M8xx_SMCMR_CLEN(x) ((x)<<11) /* Character length */ +#define M8xx_SMCMR_2STOP (1<<10) /* 2 stop bits */ +#define M8xx_SMCMR_PARITY (1<<9) /* Enable parity */ +#define M8xx_SMCMR_EVEN (1<<8) /* Even parity */ +#define M8xx_SMCMR_SM_GCI (0<<4) /* GCI Mode */ +#define M8xx_SMCMR_SM_UART (2<<4) /* UART Mode */ +#define M8xx_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ +#define M8xx_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ +#define M8xx_SMCMR_DM_ECHO (2<<2) /* Echo mode */ +#define M8xx_SMCMR_TEN (1<<1) /* Enable transmitter */ +#define M8xx_SMCMR_REN (1<<0) /* Enable receiver */ + +/* + * Event and mask registers (SMCE, SMCM) + */ +#define M8xx_SMCE_BRKE (1<<6) +#define M8xx_SMCE_BRK (1<<4) +#define M8xx_SMCE_BSY (1<<2) +#define M8xx_SMCE_TX (1<<1) +#define M8xx_SMCE_RX (1<<0) + +/* +************************************************************************* +* Serial Peripheral Interface * +************************************************************************* +*/ +typedef struct m8xxSPIparms_ { + uint16_t rbase; + uint16_t tbase; + uint8_t rfcr; + uint8_t tfcr; + uint16_t mrblr; + uint32_t _rstate; + uint32_t _pad0; + uint16_t _rbptr; + uint16_t _pad1; + uint32_t _pad2; + uint32_t _tstate; + uint32_t _pad3; + uint16_t _tbptr; + uint16_t _pad4; + uint32_t _pad5; +} m8xxSPIparms_t; + +/* + * Mode register (SPMODE) + */ +#define M8xx_SPMODE_LOOP (1<<14) /* Local loopback mode */ +#define M8xx_SPMODE_CI (1<<13) /* Clock invert */ +#define M8xx_SPMODE_CP (1<<12) /* Clock phase */ +#define M8xx_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ +#define M8xx_SPMODE_REV (1<<10) /* Reverse data */ +#define M8xx_SPMODE_MASTER (1<<9) /* SPI is master */ +#define M8xx_SPMODE_EN (1<<8) /* Enable SPI */ +#define M8xx_SPMODE_CLEN(x) ((x)<<4) /* Character length */ +#define M8xx_SPMODE_PM(x) (x) /* Prescaler modulus */ + +/* + * Mode register (SPCOM) + */ +#define M8xx_SPCOM_STR (1<<7) /* Start transmit */ + +/* + * Event and mask registers (SPIE, SPIM) + */ +#define M8xx_SPIE_MME (1<<5) /* Multi-master error */ +#define M8xx_SPIE_TXE (1<<4) /* Tx error */ +#define M8xx_SPIE_BSY (1<<2) /* Busy condition*/ +#define M8xx_SPIE_TXB (1<<1) /* Tx buffer */ +#define M8xx_SPIE_RXB (1<<0) /* Rx buffer */ + +/* +************************************************************************* +* SDMA (SCC, SMC, SPI) Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8xxBufferDescriptor_ { + volatile uint16_t status; + uint16_t length; + volatile void *buffer; +} m8xxBufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8xx_BD_MISS (1<<8) /* Ethernet */ +#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8xx_BD_LONG (1<<5) /* Ethernet */ +#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet */ +#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8xx_BD_SHORT (1<<3) /* Ethernet */ +#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet */ +#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_PAD (1<<14) /* Ethernet */ +#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8xx_BD_DEFER (1<<9) /* Ethernet */ +#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART */ + +/* +************************************************************************* +* IDMA Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8xxIDMABufferDescriptor_ { + uint16_t status; + uint8_t dfcr; + uint8_t sfcr; + uint32_t length; + void *source; + void *destination; +} m8xxIDMABufferDescriptor_t; + +/* +************************************************************************* +* RISC Communication Processor Module Command Register (CR) * +************************************************************************* +*/ +#define M8xx_CR_RST (1<<15) /* Reset communication processor */ +#define M8xx_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */ +#define M8xx_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */ +#define M8xx_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */ +#define M8xx_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */ +#define M8xx_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */ +#define M8xx_CR_OP_GR_STOP_TX (5<<8) /* SCC */ +#define M8xx_CR_OP_INIT_IDMA (5<<8) /* IDMA */ +#define M8xx_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */ +#define M8xx_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */ +#define M8xx_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */ +#define M8xx_CR_OP_SET_TIMER (8<<8) /* Timer */ +#define M8xx_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */ +#define M8xx_CR_OP_RESERT_BCS (10<<8) /* SCC */ +#define M8xx_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */ +#define M8xx_CR_OP_STOP_IDMA (11<<8) /* IDMA */ +#define M8xx_CR_OP_START_DSP (12<<8) /* DSP */ +#define M8xx_CR_OP_INIT_DSP (13<<8) /* DSP */ + +#define M8xx_CR_CHAN_SCC1 (0<<4) /* Channel selection */ +#define M8xx_CR_CHAN_I2C (1<<4) +#define M8xx_CR_CHAN_IDMA1 (1<<4) +#define M8xx_CR_CHAN_SCC2 (4<<4) +#define M8xx_CR_CHAN_SPI (5<<4) +#define M8xx_CR_CHAN_IDMA2 (5<<4) +#define M8xx_CR_CHAN_TIMER (5<<4) +#define M8xx_CR_CHAN_SCC3 (8<<4) +#define M8xx_CR_CHAN_SMC1 (9<<4) +#define M8xx_CR_CHAN_DSP1 (9<<4) +#define M8xx_CR_CHAN_SCC4 (12<<4) +#define M8xx_CR_CHAN_SMC2 (13<<4) +#define M8xx_CR_CHAN_DSP2 (13<<4) +#define M8xx_CR_FLG (1<<0) /* Command flag */ + +/* +************************************************************************* +* System Protection Control Register (SYPCR) * +************************************************************************* +*/ +#define M8xx_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* PCMCIA Control Registers +************************************************************************* +*/ +#define M8xx_PCMCIA_POR_BSIZE_1B (0x00 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_2B (0x01 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_4B (0x03 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_8B (0x02 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_16B (0x06 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_32B (0x07 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_64B (0x05 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_128B (0x04 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_256B (0x0C << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_512B (0x0D << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_1KB (0x0F << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_2KB (0x0E << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_4KB (0x0A << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_8KB (0x0B << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_16KB (0x09 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_32KB (0x08 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_64KB (0x18 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_128KB (0x19 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_256KB (0x1B << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_512KB (0x1A << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_1MB (0x1E << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_2MB (0x1F << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_4MB (0x1D << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_8MB (0x1C << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_16MB (0x14 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_32MB (0x15 << (31-4)) +#define M8xx_PCMCIA_POR_BSIZE_64MB (0x17 << (31-4)) + +#define M8xx_PCMCIA_POR_PSHT(x) (((x) & 0x0f) << (31-15)) +#define M8xx_PCMCIA_POR_PSST(x) (((x) & 0x0f) << (31-19)) +#define M8xx_PCMCIA_POR_PSL(x) (((x) & 0x1f) << (31-24)) +#define M8xx_PCMCIA_POR_PPS_8 ((0) << (31-19)) +#define M8xx_PCMCIA_POR_PPS_16 ((1) << (31-19)) + +#define M8xx_PCMCIA_POR_PRS_MEM ((0) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_ATT ((2) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_IO ((3) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_DMA ((4) << (31-28)) +#define M8xx_PCMCIA_POR_PRS_DML ((5) << (31-28)) + +#define M8xx_PCMCIA_POR_PSLOT_A ((0) << (31-29)) +#define M8xx_PCMCIA_POR_PSLOT_B ((1) << (31-29)) + +#define M8xx_PCMCIA_POR_WP ((1) << (31-30)) +#define M8xx_PCMCIA_POR_VALID ((1) << (31-31)) + +#define M8xx_PCMCIA_PGCR_CIRQLVL(x) (((x) & 0xff) << (31- 7)) +#define M8xx_PCMCIA_PGCR_CSCHLVL(x) (((x) & 0xff) << (31-15)) +#define M8xx_PCMCIA_PGCR_CDRQ_OFF ((0) << (31-17)) +#define M8xx_PCMCIA_PGCR_CDRQ_IOIS16 ((2) << (31-17)) +#define M8xx_PCMCIA_PGCR_CDRQ_SPKR ((3) << (31-17)) +#define M8xx_PCMCIA_PGCR_COE ((1) << (31-24)) +#define M8xx_PCMCIA_PGCR_CRESET ((1) << (31-25)) + +#define M8xx_PCMCIA_PIPR_CAVS1 ((1) << (31- 0)) +#define M8xx_PCMCIA_PIPR_CAVS2 ((1) << (31- 1)) +#define M8xx_PCMCIA_PIPR_CAWP ((1) << (31- 2)) +#define M8xx_PCMCIA_PIPR_CACD2 ((1) << (31- 3)) +#define M8xx_PCMCIA_PIPR_CACD1 ((1) << (31- 4)) +#define M8xx_PCMCIA_PIPR_CABVD2 ((1) << (31- 5)) +#define M8xx_PCMCIA_PIPR_CABVD1 ((1) << (31- 6)) +#define M8xx_PCMCIA_PIPR_CARDY ((1) << (31- 7)) +#define M8xx_PCMCIA_PIPR_CBVS1 ((1) << (31-16)) +#define M8xx_PCMCIA_PIPR_CBVS2 ((1) << (31-17)) +#define M8xx_PCMCIA_PIPR_CBWP ((1) << (31-18)) +#define M8xx_PCMCIA_PIPR_CBCD2 ((1) << (31-19)) +#define M8xx_PCMCIA_PIPR_CBCD1 ((1) << (31-20)) +#define M8xx_PCMCIA_PIPR_CBBVD2 ((1) << (31-21)) +#define M8xx_PCMCIA_PIPR_CBBVD1 ((1) << (31-22)) +#define M8xx_PCMCIA_PIPR_CBRDY ((1) << (31-23)) + + +#define M8xx_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8xx_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8xx_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8xx_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8xx_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8xx_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* Memory Control Registers * +************************************************************************* +*/ +#define M8xx_UPM_AMX_8col (0<<20) /* 8 column DRAM */ +#define M8xx_UPM_AMX_9col (1<<20) /* 9 column DRAM */ +#define M8xx_UPM_AMX_10col (2<<20) /* 10 column DRAM */ +#define M8xx_UPM_AMX_11col (3<<20) /* 11 column DRAM */ +#define M8xx_UPM_AMX_12col (4<<20) /* 12 column DRAM */ +#define M8xx_UPM_AMX_13col (5<<20) /* 13 column DRAM */ +#define M8xx_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ +#define M8xx_MSR_WPER (1<<7) /* Write protection error */ +#define M8xx_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ +#define M8xx_BR_BA(x) ((x)&0xffff8000) /* Base address */ +#define M8xx_BR_AT(x) ((x)<<12) /* Address type */ +#define M8xx_BR_PS8 (1<<10) /* 8 bit port */ +#define M8xx_BR_PS16 (2<<10) /* 16 bit port */ +#define M8xx_BR_PS32 (0<<10) /* 32 bit port */ +#define M8xx_BR_PARE (1<<9) /* Parity checking enable */ +#define M8xx_BR_WP (1<<8) /* Write protect */ +#define M8xx_BR_MS_GPCM (0<<6) /* GPCM */ +#define M8xx_BR_MS_UPMA (2<<6) /* UPM A */ +#define M8xx_BR_MS_UPMB (3<<6) /* UPM B */ +#define M8xx_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define M8xx_MEMC_OR_32K 0xffff8000 /* Address range */ +#define M8xx_MEMC_OR_64K 0xffff0000 +#define M8xx_MEMC_OR_128K 0xfffe0000 +#define M8xx_MEMC_OR_256K 0xfffc0000 +#define M8xx_MEMC_OR_512K 0xfff80000 +#define M8xx_MEMC_OR_1M 0xfff00000 +#define M8xx_MEMC_OR_2M 0xffe00000 +#define M8xx_MEMC_OR_4M 0xffc00000 +#define M8xx_MEMC_OR_8M 0xff800000 +#define M8xx_MEMC_OR_16M 0xff000000 +#define M8xx_MEMC_OR_32M 0xfe000000 +#define M8xx_MEMC_OR_64M 0xfc000000 +#define M8xx_MEMC_OR_128 0xf8000000 +#define M8xx_MEMC_OR_256M 0xf0000000 +#define M8xx_MEMC_OR_512M 0xe0000000 +#define M8xx_MEMC_OR_1G 0xc0000000 +#define M8xx_MEMC_OR_2G 0x80000000 +#define M8xx_MEMC_OR_4G 0x00000000 +#define M8xx_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define M8xx_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define M8xx_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ +#define M8xx_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define M8xx_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define M8xx_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define M8xx_MEMC_OR_BI (1<<8) /* Burst inhibit */ +#define M8xx_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define M8xx_MEMC_OR_SETA (1<<3) /* *TA generated externally */ +#define M8xx_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ +#define M8xx_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ + +/* +************************************************************************* +* UPM Registers (MxMR) * +************************************************************************* +*/ +#define M8xx_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ +#define M8xx_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ +#define M8xx_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ +#define M8xx_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ +#define M8xx_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ +#define M8xx_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ +#define M8xx_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ +#define M8xx_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ +/* +************************************************************************* +* Memory Command Register (MCR) * +************************************************************************* +*/ +#define M8xx_MEMC_MCR_WRITE (0<<30) /* WRITE command */ +#define M8xx_MEMC_MCR_READ (1<<30) /* READ command */ +#define M8xx_MEMC_MCR_RUN (2<<30) /* RUN command */ +#define M8xx_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ +#define M8xx_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ +#define M8xx_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ +#define M8xx_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ +#define M8xx_MEMC_MCR_MAD(x) (x) /* Machine address */ + + + +/* +************************************************************************* +* SI Mode Register (SIMODE) * +************************************************************************* +*/ +#define M8xx_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ +#define M8xx_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ +#define M8xx_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ +#define M8xx_SI_SMC2_BRG2 (1<<28) +#define M8xx_SI_SMC2_BRG3 (2<<28) +#define M8xx_SI_SMC2_BRG4 (3<<28) +#define M8xx_SI_SMC2_CLK5 (0<<28) +#define M8xx_SI_SMC2_CLK6 (1<<28) +#define M8xx_SI_SMC2_CLK7 (2<<28) +#define M8xx_SI_SMC2_CLK8 (3<<28) +#define M8xx_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ +#define M8xx_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ +#define M8xx_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ +#define M8xx_SI_SMC1_BRG2 (1<<12) +#define M8xx_SI_SMC1_BRG3 (2<<12) +#define M8xx_SI_SMC1_BRG4 (3<<12) +#define M8xx_SI_SMC1_CLK1 (0<<12) +#define M8xx_SI_SMC1_CLK2 (1<<12) +#define M8xx_SI_SMC1_CLK3 (2<<12) +#define M8xx_SI_SMC1_CLK4 (3<<12) + +/* +************************************************************************* +* SDMA Configuration Register (SDCR) * +************************************************************************* +*/ +#define M8xx_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ +#define M8xx_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ + +/* +************************************************************************* +* SDMA Status Register (SDSR) * +************************************************************************* +*/ +#define M8xx_SDSR_SBER (1<<7) /* SDMA Channel bus error */ +#define M8xx_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ +#define M8xx_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ + +/* +************************************************************************* +* Baud (sic) Rate Generators * +************************************************************************* +*/ +#define M8xx_BRG_RST (1<<17) /* Reset generator */ +#define M8xx_BRG_EN (1<<16) /* Enable generator */ +#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ +#define M8xx_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ +#define M8xx_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ +#define M8xx_BRG_ATB (1<<13) /* Autobaud */ +#define M8xx_BRG_115200 (21<<1) /* Assume 40 MHz clock */ +#define M8xx_BRG_57600 (32<<1) +#define M8xx_BRG_38400 (64<<1) +#define M8xx_BRG_19200 (129<<1) +#define M8xx_BRG_9600 (259<<1) +#define M8xx_BRG_4800 (520<<1) +#define M8xx_BRG_2400 (1040<<1) +#define M8xx_BRG_1200 (2082<<1) +#define M8xx_BRG_600 ((259<<1) | 1) +#define M8xx_BRG_300 ((520<<1) | 1) +#define M8xx_BRG_150 ((1040<<1) | 1) +#define M8xx_BRG_75 ((2080<<1) | 1) + +#define M8xx_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ +#define M8xx_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ +#define M8xx_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ +#define M8xx_TGCR_STP1 (1<<1) /* Stop timer */ +#define M8xx_TGCR_STP2 (1<<5) /* Stop timer */ +#define M8xx_TGCR_STP3 (1<<9) /* Stop timer */ +#define M8xx_TGCR_STP4 (1<<13) /* Stop timer */ +#define M8xx_TGCR_RST1 (1<<0) /* Enable timer */ +#define M8xx_TGCR_RST2 (1<<4) /* Enable timer */ +#define M8xx_TGCR_RST3 (1<<8) /* Enable timer */ +#define M8xx_TGCR_RST4 (1<<12) /* Enable timer */ +#define M8xx_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ +#define M8xx_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ + +#define M8xx_TMR_PS(x) ((x)<<8) /* Timer prescaler */ +#define M8xx_TMR_CE_RISE (1<<6) /* Capture on rising edge */ +#define M8xx_TMR_CE_FALL (2<<6) /* Capture on falling edge */ +#define M8xx_TMR_CE_ANY (3<<6) /* Capture on any edge */ +#define M8xx_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ +#define M8xx_TMR_ORI (1<<4) /* Interrupt on reaching reference */ +#define M8xx_TMR_RESTART (1<<3) /* Restart timer after reference */ +#define M8xx_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ +#define M8xx_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ +#define M8xx_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ +#define M8xx_TMR_TGATE (1<<0) /* TGATE controls timer */ + +#define M8xx_PISCR_PIRQ(x) (1<<(15-x)) /* PIT interrupt level */ +#define M8xx_PISCR_PS (1<<7) /* PIT Interrupt state */ +#define M8xx_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define M8xx_PISCR_PITF (1<<1) /* Stop timer when freeze asserted */ +#define M8xx_PISCR_PTE (1<<0) /* PIT enable */ + +#define M8xx_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define M8xx_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define M8xx_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define M8xx_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define M8xx_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define M8xx_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define M8xx_TBSCR_TBE (1<<0) /* enable TB and decrementer */ + +#define M8xx_SIMASK_IRM0 (1<<31) +#define M8xx_SIMASK_LVM0 (1<<30) +#define M8xx_SIMASK_IRM1 (1<<29) +#define M8xx_SIMASK_LVM1 (1<<28) +#define M8xx_SIMASK_IRM2 (1<<27) +#define M8xx_SIMASK_LVM2 (1<<26) +#define M8xx_SIMASK_IRM3 (1<<25) +#define M8xx_SIMASK_LVM3 (1<<24) +#define M8xx_SIMASK_IRM4 (1<<23) +#define M8xx_SIMASK_LVM4 (1<<22) +#define M8xx_SIMASK_IRM5 (1<<21) +#define M8xx_SIMASK_LVM5 (1<<20) +#define M8xx_SIMASK_IRM6 (1<<19) +#define M8xx_SIMASK_LVM6 (1<<18) +#define M8xx_SIMASK_IRM7 (1<<17) +#define M8xx_SIMASK_LVM7 (1<<16) + +#define M8xx_SIUMCR_EARB (1<<31) +#define M8xx_SIUMCR_EARP0 (0<<28) +#define M8xx_SIUMCR_EARP1 (1<<28) +#define M8xx_SIUMCR_EARP2 (2<<28) +#define M8xx_SIUMCR_EARP3 (3<<28) +#define M8xx_SIUMCR_EARP4 (4<<28) +#define M8xx_SIUMCR_EARP5 (5<<28) +#define M8xx_SIUMCR_EARP6 (6<<28) +#define M8xx_SIUMCR_EARP7 (7<<28) +#define M8xx_SIUMCR_DSHW (1<<23) +#define M8xx_SIUMCR_DBGC0 (0<<21) +#define M8xx_SIUMCR_DBGC1 (1<<21) +#define M8xx_SIUMCR_DBGC2 (2<<21) +#define M8xx_SIUMCR_DBGC3 (3<<21) +#define M8xx_SIUMCR_DBPC0 (0<<19) +#define M8xx_SIUMCR_DBPC1 (1<<19) +#define M8xx_SIUMCR_DBPC2 (2<<19) +#define M8xx_SIUMCR_DBPC3 (3<<19) +#define M8xx_SIUMCR_FRC (1<<17) +#define M8xx_SIUMCR_DLK (1<<16) +#define M8xx_SIUMCR_PNCS (1<<15) +#define M8xx_SIUMCR_OPAR (1<<14) +#define M8xx_SIUMCR_DPC (1<<13) +#define M8xx_SIUMCR_MPRE (1<<12) +#define M8xx_SIUMCR_MLRC0 (0<<10) +#define M8xx_SIUMCR_MLRC1 (1<<10) +#define M8xx_SIUMCR_MLRC2 (2<<10) +#define M8xx_SIUMCR_MLRC3 (3<<10) +#define M8xx_SIUMCR_AEME (1<<9) +#define M8xx_SIUMCR_SEME (1<<8) +#define M8xx_SIUMCR_BSC (1<<7) +#define M8xx_SIUMCR_GB5E (1<<6) +#define M8xx_SIUMCR_B2DD (1<<5) +#define M8xx_SIUMCR_B3DD (1<<4) + +/* + * Value to write to a key register to unlock the corresponding SIU register + */ +#define M8xx_UNLOCK_KEY 0x55CCAA33 + +/* +************************************************************************* +* MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address) * +************************************************************************* +*/ +typedef struct m8xx_ { + + /* + * SIU Block + */ + uint32_t siumcr; + uint32_t sypcr; +#if defined(mpc860) + uint32_t swt; +#elif defined(mpc821) + uint32_t _pad70; +#endif + uint16_t _pad0; + uint16_t swsr; + uint32_t sipend; + uint32_t simask; + uint32_t siel; + uint32_t sivec; + uint32_t tesr; + uint32_t _pad1[3]; + uint32_t sdcr; + uint8_t _pad2[0x80-0x34]; + + /* + * PCMCIA Block + */ + uint32_t pbr0; + uint32_t por0; + uint32_t pbr1; + uint32_t por1; + uint32_t pbr2; + uint32_t por2; + uint32_t pbr3; + uint32_t por3; + uint32_t pbr4; + uint32_t por4; + uint32_t pbr5; + uint32_t por5; + uint32_t pbr6; + uint32_t por6; + uint32_t pbr7; + uint32_t por7; + uint8_t _pad3[0xe0-0xc0]; + uint32_t pgcra; + uint32_t pgcrb; + uint32_t pscr; + uint32_t _pad4; + uint32_t pipr; + uint32_t _pad5; + uint32_t per; + uint32_t _pad6; + + /* + * MEMC Block + */ + m8xxMEMCRegisters_t memc[8]; + uint8_t _pad7[0x164-0x140]; + uint32_t mar; + uint32_t mcr; + uint32_t _pad8; + uint32_t mamr; + uint32_t mbmr; + uint16_t mstat; + uint16_t mptpr; + uint32_t mdr; + uint8_t _pad9[0x200-0x180]; + + /* + * System integration timers + */ + uint16_t tbscr; + uint16_t _pad10; + uint32_t tbreff0; + uint32_t tbreff1; + uint8_t _pad11[0x220-0x20c]; + uint16_t rtcsc; + uint16_t _pad12; + uint32_t rtc; + uint32_t rtsec; + uint32_t rtcal; + uint32_t _pad13[4]; + uint16_t piscr; + uint16_t _pad14; + uint16_t pitc; + uint16_t _pad_14_1; + uint16_t pitr; + uint16_t _pad_14_2; + uint8_t _pad15[0x280-0x24c]; + + + /* + * Clocks and Reset + */ + uint32_t sccr; + uint32_t plprcr; + uint32_t rsr; + uint8_t _pad16[0x300-0x28c]; + + + /* + * System integration timers keys + */ + uint32_t tbscrk; + uint32_t tbreff0k; + uint32_t tbreff1k; + uint32_t tbk; + uint32_t _pad17[4]; + uint32_t rtcsk; + uint32_t rtck; + uint32_t rtseck; + uint32_t rtcalk; + uint32_t _pad18[4]; + uint32_t piscrk; + uint32_t pitck; + uint8_t _pad19[0x380-0x348]; + + /* + * Clocks and Reset Keys + */ + uint32_t sccrk; + uint32_t plprck; + uint32_t rsrk; + uint8_t _pad20[0x400-0x38c]; + uint8_t _pad21[0x800-0x400]; + uint8_t _pad22[0x860-0x800]; + + + /* + * I2C + */ + uint8_t i2mod; + uint8_t _pad23[3]; + uint8_t i2add; + uint8_t _pad24[3]; + uint8_t i2brg; + uint8_t _pad25[3]; + uint8_t i2com; + uint8_t _pad26[3]; + uint8_t i2cer; + uint8_t _pad27[3]; + uint8_t i2cmr; + uint8_t _pad28[0x900-0x875]; + + /* + * DMA Block + */ + uint32_t _pad29; + uint32_t sdar; + uint8_t sdsr; + uint8_t _pad30[3]; + uint8_t sdmr; + uint8_t _pad31[3]; + uint8_t idsr1; + uint8_t _pad32[3]; + uint8_t idmr1; + uint8_t _pad33[3]; + uint8_t idsr2; + uint8_t _pad34[3]; + uint8_t idmr2; + uint8_t _pad35[0x930-0x91d]; + + /* + * CPM Interrupt Control Block + */ + uint16_t civr; + uint8_t _pad36[14]; + uint32_t cicr; + uint32_t cipr; + uint32_t cimr; + uint32_t cisr; + + /* + * I/O Port Block + */ + uint16_t padir; + uint16_t papar; + uint16_t paodr; + uint16_t padat; + uint8_t _pad37[8]; + uint16_t pcdir; + uint16_t pcpar; + uint16_t pcso; + uint16_t pcdat; + uint16_t pcint; + uint8_t _pad39[6]; + uint16_t pddir; + uint16_t pdpar; + uint16_t _pad40; + uint16_t pddat; + uint8_t _pad41[8]; + + /* + * CPM Timers Block + */ + uint16_t tgcr; + uint8_t _pad42[14]; + uint16_t tmr1; + uint16_t tmr2; + uint16_t trr1; + uint16_t trr2; + uint16_t tcr1; + uint16_t tcr2; + uint16_t tcn1; + uint16_t tcn2; + uint16_t tmr3; + uint16_t tmr4; + uint16_t trr3; + uint16_t trr4; + uint16_t tcr3; + uint16_t tcr4; + uint16_t tcn3; + uint16_t tcn4; + uint16_t ter1; + uint16_t ter2; + uint16_t ter3; + uint16_t ter4; + uint8_t _pad43[8]; + + /* + * CPM Block + */ + uint16_t cpcr; + uint16_t _pad44; + uint16_t rccr; + uint8_t _pad45; + uint8_t rmds; + uint32_t rmdr; + uint16_t rctr1; + uint16_t rctr2; + uint16_t rctr3; + uint16_t rctr4; + uint16_t _pad46; + uint16_t rter; + uint16_t _pad47; + uint16_t rtmr; + uint8_t _pad48[0x9f0-0x9dc]; + + /* + * BRG Block + */ + uint32_t brgc1; + uint32_t brgc2; + uint32_t brgc3; + uint32_t brgc4; + + /* + * SCC Block + */ + m8xxSCCRegisters_t scc1; + m8xxSCCRegisters_t scc2; +#if defined(mpc860) + m8xxSCCRegisters_t scc3; + m8xxSCCRegisters_t scc4; +#elif defined(mpc821) + uint8_t _pad72[0xa80-0xa40]; +#endif + + /* + * SMC Block + */ + m8xxSMCRegisters_t smc1; + m8xxSMCRegisters_t smc2; + + /* + * SPI Block + */ + uint16_t spmode; + uint16_t _pad49[2]; + uint8_t spie; + uint8_t _pad50; + uint16_t _pad51; + uint8_t spim; + uint8_t _pad52[2]; + uint8_t spcom; + uint16_t _pad53[2]; + + /* + * PIP Block + */ + uint16_t pipc; + uint16_t _pad54; + uint16_t ptpr; + uint32_t pbdir; + uint32_t pbpar; + uint16_t _pad55; + uint16_t pbodr; + uint32_t pbdat; + uint32_t _pad56[6]; + + /* + * SI Block + */ + uint32_t simode; + uint8_t sigmr; + uint8_t _pad57; + uint8_t sistr; + uint8_t sicmr; + uint32_t _pad58; + uint32_t sicr; + uint16_t sirp[2]; + uint32_t _pad59[3]; + uint8_t _pad60[0xc00-0xb00]; + uint8_t siram[512]; +#if defined(mpc860) + /* + * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC) + */ + m8xxFECRegisters_t fec; +#elif defined(mpc821) + uint8_t lcdram[512]; +#endif + uint8_t _pad62[0x2000-0x1000]; + + /* + * Dual-port RAM + */ + uint8_t dpram0[0x200]; /* BD/DATA/UCODE */ + uint8_t dpram1[0x200]; /* BD/DATA/UCODE */ + uint8_t dpram2[0x400]; /* BD/DATA/UCODE */ + uint8_t dpram3[0x600]; /* BD/DATA*/ + uint8_t dpram4[0x200]; /* BD/DATA/UCODE */ + uint8_t _pad63[0x3c00-0x3000]; + + /* When using SCC1 for ethernet, we lose the use of I2C since + * their parameters would overlap. Motorola has a microcode + * patch to move parameters around so that both can be used + * together. It is available on their web site somewhere + * under http://www.mot.com/mpc8xx. If ethernet is used on + * one (or more) of the other SCCs, then other CPM features + * will be unavailable: + * SCC2 -> lose SPI + * SCC3 -> lose SMC1 + * SCC4 -> lose SMC2 + * However, Ethernet only works on SCC1 on the 8xx. + */ + m8xxSCCENparms_t scc1p; + uint8_t _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)]; + m8xxMiscParms_t miscp; + uint8_t _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)]; + m8xxIDMAparms_t idma1p; + uint8_t _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)]; + + m8xxSCCparms_t scc2p; + uint8_t _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)]; + m8xxSPIparms_t spip; + uint8_t _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)]; + m8xxTimerParms_t tmp; + uint8_t _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)]; + m8xxIDMAparms_t idma2p; + uint8_t _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)]; + + m8xxSCCparms_t scc3p; /* Not available on MPC821 */ + uint8_t _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)]; + m8xxSMCparms_t smc1p; + uint8_t _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)]; + m8xxDSPparms_t dsp1p; + uint8_t _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)]; + + m8xxSCCparms_t scc4p; /* Not available on MPC821 */ + uint8_t _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)]; + m8xxSMCparms_t smc2p; + uint8_t _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)]; + m8xxDSPparms_t dsp2p; + uint8_t _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)]; +} m8xx_t; + +extern volatile m8xx_t m8xx; + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _MPC8XX_H */ diff --git a/bsps/powerpc/include/mpc8xx/console.h b/bsps/powerpc/include/mpc8xx/console.h new file mode 100644 index 0000000000..eea561e7eb --- /dev/null +++ b/bsps/powerpc/include/mpc8xx/console.h @@ -0,0 +1,32 @@ +#ifndef _MPC8XX_CONSOLE_H +#define _MPC8XX_CONSOLE_H + +#include <rtems/libio.h> + +void m8xx_uart_initialize(void); +void m8xx_uart_interrupts_initialize(void); +void m8xx_uart_scc_initialize (int minor); +void m8xx_uart_smc_initialize (int minor); + +/* Termios callbacks */ +int m8xx_uart_pollRead(int minor); +ssize_t m8xx_uart_pollWrite(int minor, const char* buf, size_t len); +ssize_t m8xx_uart_write(int minor, const char *buf, size_t len); +int m8xx_uart_setAttributes(int, const struct termios* t); + + +#ifdef mpc860 +#define NUM_PORTS 6 /* number of serial ports for mpc860 */ +#else +#define NUM_PORTS 4 /* number of serial ports for mpc821 */ +#endif + +#define SMC1_MINOR 0 +#define SMC2_MINOR 1 +#define SCC1_MINOR 2 +#define SCC2_MINOR 3 +#define SCC3_MINOR 4 +#define SCC4_MINOR 5 + + +#endif diff --git a/bsps/powerpc/include/mpc8xx/cpm.h b/bsps/powerpc/include/mpc8xx/cpm.h new file mode 100644 index 0000000000..49889bdc32 --- /dev/null +++ b/bsps/powerpc/include/mpc8xx/cpm.h @@ -0,0 +1,36 @@ +/* + * cpm.h + * + * This include file contains definitions pertaining + * to the Communications Processor Module (CPM) on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8XX_CPM_H +#define _MPC8XX_CPM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Functions */ + +void m8xx_cp_execute_cmd( uint16_t command ); +void *m8xx_dpram_allocate( unsigned int byte_count ); + +#define m8xx_bd_allocate(count) \ + m8xx_dpram_allocate( (count) * sizeof(m8xxBufferDescriptor_t) ) +#define m8xx_RISC_timer_table_allocate(count) \ + m8xx_dpram_allocate( (count) * 4 ) + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/mpc8xx/mmu.h b/bsps/powerpc/include/mpc8xx/mmu.h new file mode 100644 index 0000000000..f818b14be1 --- /dev/null +++ b/bsps/powerpc/include/mpc8xx/mmu.h @@ -0,0 +1,47 @@ +/* + * mmu.h + * + * This include file contains definitions pertaining + * to the MMU on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _MPC8XX_MMU_H +#define _MPC8XX_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of an MPC8xx. + */ +typedef struct { + uint32_t mmu_epn; /* Effective Page Number */ + uint32_t mmu_twc; /* Tablewalk Control Register */ + uint32_t mmu_rpn; /* Real Page Number */ +} MMU_TLB_table_t; + +/* + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * supplied by the BSP. + */ +extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ +extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ + +/* Functions */ + +void mmu_init( void ); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/bsps/powerpc/include/nvram.h b/bsps/powerpc/include/nvram.h new file mode 100644 index 0000000000..f579544336 --- /dev/null +++ b/bsps/powerpc/include/nvram.h @@ -0,0 +1,167 @@ +/* + * PreP compliant NVRAM access + * + * This file can be found in motorla or IBP PPC site. + */ + +#ifndef _PPC_NVRAM_H +#define _PPC_NVRAM_H + +#define NVRAM_AS0 0x74 +#define NVRAM_AS1 0x75 +#define NVRAM_DATA 0x77 + +/* RTC Offsets */ + +#define MOTO_RTC_SECONDS 0x1FF9 +#define MOTO_RTC_MINUTES 0x1FFA +#define MOTO_RTC_HOURS 0x1FFB +#define MOTO_RTC_DAY_OF_WEEK 0x1FFC +#define MOTO_RTC_DAY_OF_MONTH 0x1FFD +#define MOTO_RTC_MONTH 0x1FFE +#define MOTO_RTC_YEAR 0x1FFF +#define MOTO_RTC_CONTROLA 0x1FF8 +#define MOTO_RTC_CONTROLB 0x1FF9 + +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +/* Structure map for NVRAM on PowerPC Reference Platform */ +/* All fields are either character/byte strings which are valid either + endian or they are big-endian numbers. + + There are a number of Date and Time fields which are in RTC format, + big-endian. These are stored in UT (GMT). + + For enum's: if given in hex then they are bit significant, i.e. only + one bit is on for each enum. +*/ + +#define NVSIZE 4096 /* size of NVRAM */ +#define OSAREASIZE 512 /* size of OSArea space */ +#define CONFSIZE 1024 /* guess at size of Configuration space */ + +#ifndef ASM + +typedef struct _SECURITY { + unsigned long BootErrCnt; /* Count of boot password errors */ + unsigned long ConfigErrCnt; /* Count of config password errors */ + unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ + unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ + unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ + unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ + unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ + unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ + unsigned char Serial[16]; /* Box serial number */ +} SECURITY; + +typedef enum _OS_ID { + Unknown = 0, + Firmware = 1, + AIX = 2, + NT = 3, + MKOS2 = 4, + MKAIX = 5, + Taligent = 6, + Solaris = 7, + MK = 12 +} OS_ID; + +typedef struct _ERROR_LOG { + unsigned char ErrorLogEntry[40]; /* To be architected */ +} ERROR_LOG; + +typedef enum _BOOT_STATUS { + BootStarted = 0x01, + BootFinished = 0x02, + RestartStarted = 0x04, + RestartFinished = 0x08, + PowerFailStarted = 0x10, + PowerFailFinished = 0x20, + ProcessorReady = 0x40, + ProcessorRunning = 0x80, + ProcessorStart = 0x0100 +} BOOT_STATUS; + +typedef struct _RESTART_BLOCK { + unsigned short Version; + unsigned short Revision; + unsigned long ResumeReserve1[2]; + volatile unsigned long BootStatus; + unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ + void* RestartAddress; + void* SaveAreaAddr; + unsigned long SaveAreaLength; +} RESTART_BLOCK; + +typedef enum _OSAREA_USAGE { + Empty = 0, + Used = 1 +} OSAREA_USAGE; + +typedef enum _PM_MODE { + Suspend = 0x80, /* Part of state is in memory */ + Normal = 0x00 /* No power management in effect */ +} PMMode; + +typedef struct _HEADER { + unsigned short Size; /* NVRAM size in K(1024) */ + unsigned char Version; /* Structure map different */ + unsigned char Revision; /* Structure map the same -may + be new values in old fields + in other words old code still works */ + unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ + unsigned short Crc2; /* check sum of config */ + unsigned char LastOS; /* OS_ID */ + unsigned char Endian; /* B if big endian, L if little endian */ + unsigned char OSAreaUsage;/* OSAREA_USAGE */ + unsigned char PMMode; /* Shutdown mode */ + RESTART_BLOCK RestartBlock; + SECURITY Security; + ERROR_LOG ErrorLog[2]; + + /* Global Environment information */ + void* GEAddress; + unsigned long GELength; + + /* Date&Time from RTC of last change to Global Environment */ + unsigned long GELastWriteDT[2]; + + /* Configuration information */ + void* ConfigAddress; + unsigned long ConfigLength; + + /* Date&Time from RTC of last change to Configuration */ + unsigned long ConfigLastWriteDT[2]; + unsigned long ConfigCount; /* Count of entries in Configuration */ + + /* OS dependent temp area */ + void* OSAreaAddress; + unsigned long OSAreaLength; + + /* Date&Time from RTC of last change to OSArea */ + unsigned long OSAreaLastWriteDT[2]; +} HEADER; + +/* Here is the whole map of the NVRAM */ +typedef struct _NVRAM_MAP { + HEADER Header; + unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; + unsigned char OSArea[OSAREASIZE]; + unsigned char ConfigArea[CONFSIZE]; +} NVRAM_MAP; + +/* Routines to manipulate the NVRAM */ +void init_prep_nvram(void); +char *prep_nvram_get_var(const char *name); +char *prep_nvram_first_var(void); +char *prep_nvram_next_var(char *name); + +#endif /* ASM */ + +#endif /* _PPC_NVRAM_H */ diff --git a/bsps/powerpc/include/ppc4xx/ppc405ex.h b/bsps/powerpc/include/ppc4xx/ppc405ex.h new file mode 100644 index 0000000000..98ebbe28a2 --- /dev/null +++ b/bsps/powerpc/include/ppc4xx/ppc405ex.h @@ -0,0 +1,191 @@ +/* + +Constants for manipulating system registers of PPC 405EX in C + +Michael Hamel ADInstruments May 2008 + +*/ + +#include <libcpu/powerpc-utility.h> +/* Indirect access to Clocking/Power-On registers */ +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define mtcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ + } while (0) + +#define mfcpr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ + } while (0) + + +/* Indirect access to System registers */ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define mtsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ + } while (0) + +#define mfsdr(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ + } while (0) + +/* Indirect access to EBC registers */ +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +#define mtebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ + } while (0) + +#define mfebc(reg, d) \ + do { \ + PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ + d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ + } while (0) + +/* EBC DCRs */ +enum { + /* + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_BEAR = 0x20, + EBC0_BESR = 0x21, + EBC0_CFG = 0x23, + */ + EBC0_CID = 0x24 +}; + +enum { + SDR0_PINSTP = 0x40, + SDR0_UART0 = 0x120, + SDR0_UART1 = 0x121, + SDR0_C405 = 0x180, + SDR0_SRST0 = 0x200, + SDR0_MALTBL = 0x280, + SDR0_MALRBL = 0x2A0, + SDR0_MALTBS = 0x2C0, + SDR0_MALRBS = 0x2E0, + SDR0_PFC2 = 0x4102, + SDR0_MFR = 0x4300, + SDR0_EMAC0RXST = 0x4301, + SDR0_HSF = 0x4400 +}; + +enum { + CPR0_CLKUPD = 0x20, + CPR0_PLLC = 0x40, + CPR0_PLLD = 0x60, + CPR0_CPUD = 0x80, + CPR0_PLBD = 0xA0, + CPR0_OPBD = 0xC0, + CPR0_PERD = 0xE0, + CPR0_AHBD = 0x100, + CPR0_ICFG = 0x140 +}; + +/* Memory-mapped registers */ + + +/*======================= Ethernet =================== */ + +enum { + EMAC0EXAddress = 0xEF600900, + EMAC1EXAddress = 0xEF600A00, + + /* 405EX-specific bits in EMAC_MR1 */ + keEMAC1000Mbps = 0x00800000, + keEMAC16KRxFIFO = 0x00280000, + keEMAC8KRxFIFO = 0x00200000, + keEMAC4KRxFIFO = 0x00180000, + keEMAC2KRxFIFO = 0x00100000, + keEMAC1KRxFIFO = 0x00080000, + keEMAC16KTxFIFO = 0x00050000, + keEMAC8KTxFIFO = 0x00040000, + keEMAC4KTxFIFO = 0x00030000, + keEMAC2KTxFIFO = 0x00020000, + keEMAC1KTxFIFO = 0x00010000, + keEMACJumbo = 0x00000800, + keEMACIPHYAddr4 = 0x180, + keEMACOPB50MHz = 0x00, + keEMACOPB66MHz = 0x08, + keEMACOPB83MHz = 0x10, + keEMACOPB100MHz = 0x18, + keEMACOPBGt100 = 0x20, + + /* 405EX-specific bits in MAL0_CFG */ + keMALRdMaxBurst4 = 0, + keMALRdMaxBurst8 = 0x00100000, + keMALRdMaxBurst16 = 0x00200000, + keMALRdMaxBurst32 = 0x00300000, + + keMALWrLowPriority = 0, + keMALWrMedLowPriority = 0x00040000, + keMALWrMedHiPriority = 0x00080000, + keMALWrHighPriority = 0x000C0000, + + keMALWrMaxBurst4 = 0, + keMALWrMaxBurst8 = 0x00010000, + keMALWrMaxBurst16 = 0x00020000, + keMALWrMaxBurst32 = 0x00030000, + + /* 405EX-specific STA bits */ + keSTARun = 0x8000, + keSTADirectRd = 0x1000, + keSTADirectWr = 0x0800, + keSTAIndirAddr = 0x2000, + keSTAIndirRd = 0x3000, + keSTAIndirWr = 0x2800 +}; + +typedef struct GPIORegisters { + uint32_t OR; + uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ + uint32_t OSRL; + uint32_t OSRH; + uint32_t TSRL; + uint32_t TSRH; + uint32_t ODR; + uint32_t IR; + uint32_t RR1; + uint32_t RR2; + uint32_t RR3; + uint32_t unknown; + uint32_t ISR1L; + uint32_t ISR1H; + uint32_t ISR2L; + uint32_t ISR2H; + uint32_t ISR3L; + uint32_t ISR3H; +} GPIORegisters; + +enum { GPIOAddress = 0xEF600800 }; + +typedef struct RGMIIRegisters { + uint32_t FER; + uint32_t SSR; +} RGMIIRegisters; + +enum { RGMIIAddress = 0xEF600B00 }; + diff --git a/bsps/powerpc/include/ppc4xx/ppc405gp.h b/bsps/powerpc/include/ppc4xx/ppc405gp.h new file mode 100644 index 0000000000..9cf46a780a --- /dev/null +++ b/bsps/powerpc/include/ppc4xx/ppc405gp.h @@ -0,0 +1,214 @@ + +/* SDRAM DCRs */ +enum { + SDRAM0_BESR0 = 0, + SDRAM0_BESR1 = 8, + SDRAM0_BEAR = 0x10, + SDRAM0_CFG = 0x20, + SDRAM0_STATUS = 0x24, + SDRAM0_RTR = 0x30, + SDRAM0_PMIT = 0x34, + SDRAM0_TR = 0x80 +}; + + +/* EBC DCRs */ +enum { + EBC0_B0CR = 0, + EBC0_B1CR = 1, + EBC0_B2CR = 2, + EBC0_B3CR = 3, + EBC0_B4CR = 4, + EBC0_B5CR = 5, + EBC0_B6CR = 6, + EBC0_B7CR = 7, + EBC0_B0AP = 0x10, + EBC0_B1AP = 0x11, + EBC0_B2AP = 0x12, + EBC0_B3AP = 0x13, + EBC0_B4AP = 0x14, + EBC0_B5AP = 0x15, + EBC0_B6AP = 0x16, + EBC0_B7AP = 0x17, + EBC0_BEAR = 0x20, + EBC0_BESR0 = 0x21, + EBC0_BESR1 = 0x22, + EBC0_CFG = 0x23 +}; + +/* MAL DCRs, have to be #defines */ +#define MAL0_CFG 0x180 +#define MAL0_ESR 0x181 +#define MAL0_IER 0x182 +#define MAL0_TXCASR 0x184 +#define MAL0_TXCARR 0x185 +#define MAL0_TXEOBISR 0x186 +#define MAL0_TXDEIR 0x187 +#define MAL0_RXCASR 0x190 +#define MAL0_RXCARR 0x191 +#define MAL0_RXEOBISR 0x192 +#define MAL0_RXDEIR 0x193 +#define MAL0_TXCTP0R 0x1A0 +#define MAL0_TXCTP1R 0x1A1 +#define MAL0_RXCTP0R 0x1C0 +#define MAL0_RXCTP1R 0x1C1 +#define MAL0_RCBS0 0x1E0 +#define MAL0_RCBS1 0x1E1 + +/* Memory-mapped registers */ + +typedef struct EthernetRegisters_GP { + uint32_t mode0; + uint32_t mode1; + uint32_t xmtMode0; + uint32_t xmtMode1; + uint32_t rcvMode; + uint32_t intStatus; + uint32_t intEnable; + uint32_t addrHi; + uint32_t addrLo; + uint32_t VLANTPID; + uint32_t VLANTCI; + uint32_t pauseTimer; + uint32_t g_indivHash[4]; /* EX non-IP multicast addr/mask */ + uint32_t g_groupHash[4]; + uint32_t lastSrcLo; + uint32_t lastSrcHi; + uint32_t IPGap; + uint32_t STAcontrol; + uint32_t xmtReqThreshold; + uint32_t rcvWatermarks; + uint32_t bytesXmtd; + uint32_t bytesRcvd; + uint32_t e_unused2; + uint32_t e_revID; + uint32_t e_unused3[2]; + uint32_t e_indivHash[8]; + uint32_t e_groupHash[8]; + uint32_t e_xmtPause; +} EthernetRegisters_GP; + +typedef struct EthernetRegisters_GP EthernetRegisters_EX; + +enum { EMACAddress = 0xEF600800 }; +enum { EMAC0GPAddress = 0xEF600800 }; + +enum { + // Mode 0 bits + kEMACRxIdle = 0x80000000, + kEMACTxIdle = 0x40000000, + kEMACSoftRst = 0x20000000, + kEMACTxEnable = 0x10000000, + kEMACRxEnable = 0x08000000, + + // Mode 1 bits + kEMACFullDuplex = 0x80000000, + kEMACDoFlowControl = 0x10000000, + kEMACIgnoreSQE = 0x01000000, + kEMAC100MBbps = 0x00400000, + kEMAC4KRxFIFO = 0x00300000, + kEMAC2KTxFIFO = 0x00080000, + kEMACTx0Multi = 0x00008000, + kEMACTxDependent= 0x00014000, + kEMAC100Mbps = 0x00400000, + kgEMAC4KRxFIFO = 0x00300000, + kgEMAC2KTxFIFO = 0x00080000, + kgEMACTx0Multi = 0x00008000, + kgEMACTxDependent= 0x00014000, + + + // Tx mode bits + kEMACNewPacket0 = 0x80000000, + kEMACNewPacket1 = 0x40000000, + + // Receive mode bits + kEMACStripPadding = 0x80000000, + kEMACStripFCS = 0x40000000, + kEMACRcvRunts = 0x20000000, + kEMACRcvFCSErrs = 0x10000000, + kEMACRcvOversize = 0x08000000, + kEMACPromiscRcv = 0x01000000, + kEMACPromMultRcv = 0x00800000, + kEMACIndivRcv = 0x00400000, + kEMACHashRcv = 0x00200000, + kEMACBrcastRcv = 0x00100000, + kEMACMultcastRcv = 0x00080000, + keEMACNonIPMultcast = 0x00040000, + keEMACRxFIFOAFMax = 7, + + // EMAC_STACR bits + kgSTAComplete = 0x8000, + kSTAErr = 0x4000, + + // Interrupt status bits + kEMACIOverrun = 0x02000000, + kEMACIPause = 0x01000000, + kEMACIBadPkt = 0x00800000, + kEMACIRuntPkt = 0x00400000, + kEMACIShortEvt= 0x00200000, + kEMACIAlignErr= 0x00100000, + kEMACIBadFCS = 0x00080000, + kEMACIOverSize= 0x00040000, + kEMACILLCRange= 0x00020000, + kEMACISQEErr = 0x00000080, + kEMACITxErr = 0x00000040, + + // Buffer descriptor control bits + kMALTxReady = 0x8000, + kMALRxEmpty = 0x8000, + kMALWrap = 0x4000, + kMALContinuous = 0x2000, + kMALLast = 0x1000, + kMALRxFirst = 0x0800, + kMALInterrupt = 0x0400, + + kMALReset = 0x80000000, + kMALLowPriority = 0, + kMALMedLowPriority = 0x00400000, + kMALMedHiPriority = 0x00800000, + kMALHighPriority = 0x00C00000, + kMALLatency8 = 0x00040000, + kMALLockErr = 0x8000, + kMALCanBurst = 0x4000, + kMALLocksOPB = 0x80, + kMALLocksErrs = 0x2, + + // MAL channel masks + kMALChannel0 = 0x80000000, + kMALChannel1 = 0x40000000, + + // EMAC Tx descriptor bits sent + kEMACGenFCS = 0x200, + kEMACGenPad = 0x100, + kEMACInsSrcAddr = 0x080, + kEMACRepSrcAddr = 0x040, + kEMACInsVLAN = 0x020, + kEMACRepVLAN = 0x010, + + // EMAC TX descriptor bits returned + kEMACErrMask = 0x3FF, + kEMACFCSWrong = 0x200, + kEMACBadPrev = 0x100, + kEMACLostCarrier = 0x080, + kEMACDeferred = 0x040, + kEMACCollFail = 0x020, + kEMACLateColl = 0x010, + kEMACMultColl = 0x008, + kEMACOneColl = 0x004, + kEMACUnderrun = 0x002, + kEMACSQEFail = 0x001, + + // EMAC Rx descriptor bits returned + kEMACOverrun = 0x200, + kEMACPausePkt = 0x100, + kEMACBadPkt = 0x080, + kEMACRuntPkt = 0x040, + kEMACShortEvt = 0x020, + kEMACAlignErr = 0x010, + kEMACBadFCS = 0x008, + kEMACPktLong = 0x004, + kEMACPktOOR = 0x002, + kEMACPktIRL = 0x001 +}; + + diff --git a/bsps/powerpc/include/rtems/powerpc/cache.h b/bsps/powerpc/include/rtems/powerpc/cache.h new file mode 100644 index 0000000000..1fdc75ae8b --- /dev/null +++ b/bsps/powerpc/include/rtems/powerpc/cache.h @@ -0,0 +1,38 @@ +#ifndef _RTEMS_POWERPC_CACHE_H +#define _RTEMS_POWERPC_CACHE_H + +#include <rtems/powerpc/powerpc.h> /* for PPC_D_CACHE */ + +#ifdef _OLD_EXCEPTIONS + +#if (PPC_D_CACHE != 0) +#define _CPU_Data_Cache_Block_Flush( _address ) \ + do { register void *__address = (_address); \ + register uint32_t _zero = 0; \ + __asm__ volatile ( "dcbf %0,%1" : \ + "=r" (_zero), "=r" (__address) : \ + "0" (_zero), "1" (__address) \ + ); \ + } while (0) +#else +#define _CPU_Data_Cache_Block_Flush( _address ) /* nop */ +#endif + +/* + * FIXME: This is not used anywhere. + */ +#if (PPC_D_CACHE != 0) +#define _CPU_Data_Cache_Block_Invalidate( _address ) \ + do { register void *__address = (_address); \ + register uint32_t _zero = 0; \ + __asm__ volatile ( "dcbi %0,%1" : \ + "=r" (_zero), "=r" (__address) : \ + "0" (_zero), "1" (__address) \ + ); \ + } while (0) +#else +#define _CPU_Data_Cache_Block_Invalidate( _address ) /* nop */ +#endif +#endif + +#endif diff --git a/bsps/powerpc/include/rtems/powerpc/debugmod.h b/bsps/powerpc/include/rtems/powerpc/debugmod.h new file mode 100644 index 0000000000..61b650695c --- /dev/null +++ b/bsps/powerpc/include/rtems/powerpc/debugmod.h @@ -0,0 +1,124 @@ +/* debugmod.h + * + * This file contains definitions for the IBM/Motorola PowerPC + * family members. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> + * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> + * Surrey Satellite Technology Limited + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Note: + * This file is included by both C and assembler code ( -DASM ) + */ + +/* + * FIXME: This file is not used anywhere inside of RTEMS source-tree. + * Notify OAR if you actually use it, otherwise it might be removed in + * future versions of RTEMS + */ + +#ifndef _RTEMS_POWERPC_DEBUGMOD_H +#define _RTEMS_POWERPC_DEBUGMOD_H + +#warning "please read the FIXME inside of this file" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * This file contains the information required to build + * RTEMS for a particular member of the PowerPC family. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + * + * The following architectural feature definitions are defaulted + * unless specifically set by the model definition: + * + * + PPC_DEBUG_MODEL - PPC_DEBUG_MODEL_STANDARD + */ + +/* + * Define the debugging assistance models found in the PPC family. + * + * Standard: single step and branch trace + * Single Step Only: single step only + * IBM 4xx: debug exception + */ + +#define PPC_DEBUG_MODEL_STANDARD 1 +#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2 +#define PPC_DEBUG_MODEL_IBM4xx 3 + +#elif defined(ppc403) || defined(ppc405) || defined(ppc440) + +#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_IBM4xx + +#elif defined(ppc601) + +#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_SINGLE_STEP_ONLY + +#endif + +/* + * Use the default debug scheme defined in the architectural specification + * if another model has not been specified. + */ + +#ifndef PPC_DEBUG_MODEL +#define PPC_DEBUG_MODEL PPC_DEBUG_MODEL_STANDARD +#endif + +/* + * Interrupt/exception MSR bits set as defined on p. 2-20 in "The Programming + * Environments" and the manuals for various PPC models. + */ + +#if (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_STANDARD) +#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ +#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ +#define PPC_MSR_SE 0x000000400 /* bit 21 - single step trace enable */ +#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_SINGLE_STEP_ONLY) +#define PPC_MSR_DE 0x000000000 /* bit 22 - debug exception enable */ +#define PPC_MSR_BE 0x000000200 /* bit 22 - branch trace enable */ +#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ +#elif (PPC_DEBUG_MODEL == PPC_DEBUG_MODEL_IBM4xx) +#define PPC_MSR_DE 0x000000200 /* bit 22 - debug exception enable */ +#define PPC_MSR_BE 0x000000000 /* bit 22 - branch trace enable */ +#define PPC_MSR_SE 0x000000000 /* bit 21 - single step trace enable */ +#else +#error "MSR constants -- unknown PPC_DEBUG_MODEL!!" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_POWERPC_DEBUGMOD_H */ +/* end of include file */ diff --git a/bsps/powerpc/include/rtems/powerpc/powerpc.h b/bsps/powerpc/include/rtems/powerpc/powerpc.h new file mode 100644 index 0000000000..8b2cf1e371 --- /dev/null +++ b/bsps/powerpc/include/rtems/powerpc/powerpc.h @@ -0,0 +1,644 @@ +/** + * @file rtems/powerpc/powerpc.h + */ + +/* + * This file contains definitions for the IBM/Motorola PowerPC + * family members. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> + * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> + * Surrey Satellite Technology Limited + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * + * Note: + * This file is included by both C and assembler code ( -DASM ) + */ + + +#ifndef _RTEMS_POWERPC_POWERPC_H +#define _RTEMS_POWERPC_POWERPC_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Till S. 2008/07/10: + * + * Using the macros/definitions which depend on a preprocessor + * symbol defining the CPU flavor is discouraged. + * I recommend to not use definitions from this file and + * in particular - not to add more bits and pieces. + * + * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h) + * of features etc. + */ + +#include <rtems/score/powerpc.h> + +/* + * Unfortunately it is very inefficient to use run-time detection for the cache + * line size, so give the BSP the opportunity to define it here. + */ +#include <bspopts.h> + +/* + * This file contains the information required to build + * RTEMS for a particular member of the PowerPC family. It does + * this by setting variables to indicate which implementation + * dependent features are present in a particular member + * of the family. + * + * The following architectural feature definitions are defaulted + * unless specifically set by the model definition: + * + * + PPC_INTERRUPT_MAX - 16 + * + PPC_CACHE_ALIGNMENT + * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE + * + PPC_HAS_EXCEPTION_PREFIX - 1 + * + PPC_USE_MULTIPLE - 0 + */ + +/* + * Define the low power mode models + * + * Standard: as defined for 603e + * Nap Mode: nap mode only (604) + * XXX 403GB, 603, 603e, 604, 821 + */ + +#define PPC_LOW_POWER_MODE_NONE 0 +#define PPC_LOW_POWER_MODE_STANDARD 1 + +/** + * @brief For boards with no cache set PPC_CACHE_ALIGNMENT to this value. + */ +#define PPC_NO_CACHE_ALIGNMENT 4 + +/** + * @brief Used to define PPC_CACHE_ALIGN_POWER for boards with no cache (and + * PPC_NO_CACHE_ALIGNMENT defined). + */ +#define PPC_NO_CACHE_ALIGNMENT_POWER 2 + +/* + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. + */ + +#if defined(ppc403) +/* + * IBM 403 + * + * Developed for 403GA. Book checked for 403GB. + * + * Does not have user mode. + */ + +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 2048 +#define PPC_D_CACHE 1024 + +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + +#elif defined (ppc405) + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 /* except GP/CR */ +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + +#elif defined (ppc440) + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_HAS_RI 0 +#define PPC_HAS_RFCI 1 +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 32768 +#define PPC_D_CACHE 32768 +#define PPC_HAS_EXCEPTION_PREFIX 0 +#define PPC_HAS_EVPR 1 + +#elif defined(mpc555) + +/* Copied from mpc505 */ +#define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT + +/* Added by querbach@realtime.bc.ca */ +#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD + +/* Based on comments by Sergei Organov <osv@Javad.RU> */ +#define PPC_I_CACHE 0 +#define PPC_D_CACHE 0 + +#elif defined(mpc505) || defined(mpc509) +/* + * Submitted by Sergei Organov <osv@Javad.RU> as a patch against + * 3.6.0 long after 4.0 was released. This is just an attempt + * to get the setting correct. + */ + +#define CPU_MODEL_NAME "PowerPC 505/509" + +#define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 0 + + +#elif defined(ppc601) + +/* + * Submitted with original port -- book checked only. + */ + +#define PPC_USE_MULTIPLE 1 +#define PPC_I_CACHE 0 +#define PPC_D_CACHE 32768 + +#elif defined(ppc603) +/* + * Submitted with original port -- book checked only. + */ + +#define PPC_I_CACHE 8192 +#define PPC_D_CACHE 8192 + +#elif defined(ppc603e) + +/* + * Submitted with original port. + * + * Known to work on real hardware. + */ + +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 + +#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD + +#elif defined(mpc604) +/* + * Submitted with original port -- book checked only. + */ + +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 + +#elif defined(mpc860) +/* + * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 + * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) + */ +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 4096 +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_INTERRUPT_MAX 71 +#define PPC_USE_MULTIPLE 1 + +#define PPC_MSR_0 0x00009000 +#define PPC_MSR_1 0x00001000 +#define PPC_MSR_2 0x00001000 +#define PPC_MSR_3 0x00000000 + +#elif defined(mpc821) +/* + * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 + */ +#define PPC_I_CACHE 4096 +#define PPC_D_CACHE 4096 +#define PPC_CACHE_ALIGNMENT 16 +#define PPC_INTERRUPT_MAX 71 + +#define PPC_MSR_0 0x00009000 +#define PPC_MSR_1 0x00001000 +#define PPC_MSR_2 0x00001000 +#define PPC_MSR_3 0x00000000 + +#elif defined(mpc750) + +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 + +#elif defined(mpc7400) + +#define PPC_I_CACHE 32768 +#define PPC_D_CACHE 32768 + +#elif defined(mpc7455) +/* + * Added by S.K. Feng <feng1@bnl.gov> 10/03 + */ + +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_I_CACHE 32768 +#define PPC_D_CACHE 32768 + +#elif defined(mpc8260) +/* + * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000 + */ +#define PPC_I_CACHE 16384 +#define PPC_D_CACHE 16384 +#define PPC_CACHE_ALIGNMENT 32 +#define PPC_INTERRUPT_MAX 125 +#define PPC_USE_MULTIPLE 1 + +#elif defined(__ppc_generic) + +#else + +#error "Unsupported CPU Model" + +#endif + +/* + * If the maximum number of exception sources has not been defined, + * then default it to 16. + */ + +#ifndef PPC_INTERRUPT_MAX +#define PPC_INTERRUPT_MAX 16 +#endif + +#ifndef PPC_CACHE_ALIGNMENT +#define PPC_CACHE_ALIGNMENT PPC_DEFAULT_CACHE_LINE_SIZE +#endif + +#if (PPC_CACHE_ALIGNMENT == 16) +#define PPC_CACHE_ALIGN_POWER 4 +#elif (PPC_CACHE_ALIGNMENT == 32) +#define PPC_CACHE_ALIGN_POWER 5 +#elif (PPC_CACHE_ALIGNMENT == 64) +#define PPC_CACHE_ALIGN_POWER 6 +#elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT) +#define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER +#else +#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" +#endif + +/* + * Unless otherwise specified, assume the model has an IP/EP bit to + * set the exception address prefix. + */ + +#ifndef PPC_HAS_EXCEPTION_PREFIX +#define PPC_HAS_EXCEPTION_PREFIX 1 +#endif +/* + * Unless otherwise specified, assume the model has an RI bit to + * identify non-recoverable interrupts + */ + +#ifndef PPC_HAS_RI +#define PPC_HAS_RI 1 +#endif + +/* + * Unless otherwise specified, assume the model does NOT have + * 403 style EVPR register to set the exception address prefix. + */ + +#ifndef PPC_HAS_EVPR +#define PPC_HAS_EVPR 0 +#endif + +/* + * If no low power mode model was specified, then assume there is none. + */ + +#ifndef PPC_LOW_POWER_MODE +#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE +#endif + +/* + * Unless specified above, then assume the model does NOT have critical + * interrupt support. + */ + +#ifndef PPC_HAS_RFCI +#define PPC_HAS_RFCI 0 +#endif + +/* + * Unless specified above, do not use the load/store multiple instructions + * in a context switch. + */ + +#ifndef PPC_USE_MULTIPLE +#define PPC_USE_MULTIPLE 0 +#endif + +/* + * The following exceptions are not maskable, and are not + * necessarily predictable, so cannot be offered to RTEMS: + * Alignment exception - handled by the CPU module + * Data exceptions. + * Instruction exceptions. + */ + +/* + * Base Interrupt vectors supported on all models. + */ +#define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ +#define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ +#define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ +#define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ +#define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ +#define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ +#define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ +#define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ +#define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ +#define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ +#define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ +#define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ +#define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ +#define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ +#define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST + +#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET + +#if defined(ppc403) || defined(ppc405) || defined(ppc440) + +#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ +#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ +#define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ +#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ +#define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ +#define PPC_IRQ_LAST PPC_IRQ_DEBUG + +#elif defined(mpc505) || defined(mpc509) +#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ +#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) +#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) +#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) +#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) + +#elif defined(mpc555) +#define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ +#define PPC_IRQ_INST_PE (PPC_STD_IRQ_LAST+2) /* Insn protection error */ +#define PPC_IRQ_DATA_PE (PPC_STD_IRQ_LAST+3) /* Data protection error */ +#define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+4) /* Data breakpoint */ +#define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+5) /* Insn breakpoint */ +#define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+6) /* Maskable ext bkpt */ +#define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+7) /* Non-maskable ext bkpt */ +#define PPC_IRQ_LAST PPC_IRQ_NMEXT_BP + +#elif defined(ppc601) +#undef PPC_IRQ_TRACE +#define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ +#define PPC_IRQ_LAST PPC_IRQ_TRACE + +#elif defined(ppc602) +#define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) + +#elif defined(ppc603) || defined(ppc603e) +#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ +#define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ +#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ +#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ +#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ +#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT + +#elif defined(mpc604) +#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ +#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ +#define PPC_IRQ_LAST PPC_IRQ_SYS_MGT + +#elif defined(mpc860) || defined(mpc821) +#define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ +#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ +#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ +#define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ +#define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ +#define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ +#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ +#define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ +#define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ +#define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) +#define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) +#define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) +#define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) +#define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) +#define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) +#define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) +#define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) +#define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) +#define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) +#define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) +#define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) +#define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) +#define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) +#define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) +#define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) +#define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) +#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) +#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) +#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) +#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) +#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) +#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) +#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) +#define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) +#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) +#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) +#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) +#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) +#define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) +#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) +#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) +#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) +#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) +#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) +#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) +#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) +#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) +#define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) +#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) +#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) +#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) +#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) +#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) +#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) +#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) +#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) +#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) + +#define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 + +#elif defined(mpc8260) + +#define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ +#define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ +#define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ +#define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ +#define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ +#define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ +/* 0x1600 - 0x2F00 reserved */ +#define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) +#define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) +#define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) +#define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) +#define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) +#define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) +#define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) +#define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) +#define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) +#define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) +#define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) +#define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) +#define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) +#define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) +#define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) +#define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) +#define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) +#define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) +#define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) +#define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) +#define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) +#define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) +#define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) +#define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) +#define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) +#define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) +#define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) +#define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) +#define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) +#define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) +#define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) +#define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) +#define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) +#define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) +#define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) +#define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) +#define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) +#define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) +#define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) +#define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) +#define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) +#define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) +#define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) +#define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) +#define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) +#define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) +#define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) +#define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) +#define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) +#define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) +#define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) +#define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) +#define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) +#define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) +#define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) +#define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) +#define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) +#define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) +#define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) +#define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) +#define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) +#define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) +#define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) +#define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) + +#define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 + +#endif + + +/* + * If the maximum number of exception sources is too low, + * then fix it + */ + +#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST +#undef PPC_INTERRUPT_MAX +#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) +#endif + +/* + * Machine Status Register (MSR) Constants Used by RTEMS + */ + +#if PPC_HAS_RI +#define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ +#endif + +#define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ +#define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ + +/* + * Some PPC model manuals refer to the Exception Prefix (EP) bit as + * IP for no apparent reason. + */ +#if (PPC_HAS_EXCEPTION_PREFIX) +#define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ +#else +#define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ +#endif + +#if (PPC_HAS_FPU) +#define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ +#else +#define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ +#endif + +#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) +#define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ +#else +#define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ +#endif + +#define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ +#define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ + +#if (PPC_HAS_RFCI) +#define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ +#else +#define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ +#endif + +#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) + +#if defined(__powerpc64__) +#define PPC_MINIMUM_STACK_FRAME_SIZE 32 +#else +#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_POWERPC_POWERPC_H */ diff --git a/bsps/powerpc/include/tty_drv.h b/bsps/powerpc/include/tty_drv.h new file mode 100644 index 0000000000..d2024c89d7 --- /dev/null +++ b/bsps/powerpc/include/tty_drv.h @@ -0,0 +1,63 @@ +#ifdef ppc405 +#ifndef __tty_drv__ +#define __tty_drv__ + +/* functions */ +#ifdef __cplusplus +extern "C" { +#endif + + +/* ttyS1 entry points */ +rtems_device_driver tty0_initialize( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty0_open( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty0_control( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + + +/* tty1 & tty2 shared entry points */ +rtems_device_driver tty0_close( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + + +rtems_device_driver tty0_read( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + +rtems_device_driver tty0_write( + rtems_device_major_number, + rtems_device_minor_number, + void * +); + + +#define TTY0_DRIVER_TABLE_ENTRY \ + { tty0_initialize, tty0_open, tty0_close, \ + tty0_read, tty0_write, tty0_control } + + +#ifdef __cplusplus +} +#endif +/* end of include file */ + +#endif /* __tty_drv__ */ +#endif /* ppc405 */ diff --git a/bsps/powerpc/motorola_powerpc/headers.am b/bsps/powerpc/motorola_powerpc/headers.am new file mode 100644 index 0000000000..b577b15c5b --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/motorola_powerpc/include/bsp/irq.h diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h b/bsps/powerpc/motorola_powerpc/include/bsp.h new file mode 100644 index 0000000000..675796becf --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/bsp.h @@ -0,0 +1,248 @@ +/* + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ +#ifndef LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H +#define LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <libcpu/io.h> +#include <bsp/vectors.h> + +#ifdef qemu +#include <rtems/bspcmdline.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * diagram illustrating the role of the configuration + * constants + * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible + * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this + * address being 'visible' or not!). + * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME + * _VME_A32_WIN0_ON_VME: VME address of that same window + * + * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between + * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI + * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to + * the base address read from PCI config.space in order to translate that + * into a CPU address. + * + * NOTE: VME addresses should NEVER be translated using these constants! + * they are strictly for BSP internal use. Drivers etc. should use + * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). + * + * CPU ADDR PCI_ADDR VME ADDR + * + * 00000000 XXXXXXXX XXXXXXXX + * ^ ^ ........ + * | | + * | | e.g., RAM XXXXXXXX + * | | 00000000 + * | | ......... ^ + * | | (possible offset | + * | | between pci and XXXXXXXX | ...... + * | | cpu addresses) | + * | v | + * | PCI_MEM_BASE -------------> 00000000 --------------- | + * | ........ ........ ^ | + * | invisible | | + * | ........ from CPU | | + * v | | + * PCI_MEM_WIN0 ============= first visible PCI addr | | + * | | + * pci devices pci window | | + * visible here v v + * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME + * vme window + * VME devices hostbridge mapped by + * visible here universe + * ===================================================== + * + */ + +/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ +#if defined(mvme2100) +#define _IO_BASE CHRP_ISA_IO_BASE +#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET +/* offset of pci memory as seen from the CPU */ +#define PCI_MEM_BASE 0 +/* where (in CPU addr. space) does the PCI window start */ +#define PCI_MEM_WIN0 0x80000000 + +#else +#define _IO_BASE PREP_ISA_IO_BASE +#define _ISA_MEM_BASE PREP_ISA_MEM_BASE +#ifndef qemu +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET +/* offset of pci memory as seen from the CPU */ +#define PCI_MEM_BASE PREP_ISA_MEM_BASE +#define PCI_MEM_WIN0 0 +#else +#define PCI_DRAM_OFFSET 0 +#define PCI_MEM_BASE 0 +#define PCI_MEM_WIN0 PREP_ISA_MEM_BASE +#endif +#endif + + +/* + * Base address definitions for several devices + * + * MVME2100 is very similar but has fewer devices and uses on-CPU EPIC + * implementation of OpenPIC controller. It also cannot be probed to + * find out what it is which is VERY different from other Motorola boards. + */ + +#if defined(mvme2100) +#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000) +/* #define BSP_UART_IOBASE_COM1 (0xffe10000) */ +#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 + +#define MVME_HAS_DEC21140 +#else +#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8) +#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8) + +#if ! defined(qemu) +#define BSP_KBD_IOBASE ((_IO_BASE)+0x60) +#define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0) +#endif + +#if defined(mvme2300) +#define MVME_HAS_DEC21140 +#endif +#endif + +#define BSP_CONSOLE_PORT BSP_UART_COM1 +#define BSP_UART_BAUD_BASE 115200 + +#if defined(MVME_HAS_DEC21140) +struct rtems_bsdnet_ifconfig; +#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach +extern int rtems_dec21140_driver_attach(); +#endif + +#ifdef qemu +#define RTEMS_BSP_NETWORK_DRIVER_NAME "ne1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach +extern int rtems_ne_driver_attach(); +#endif + +#ifdef qemu +#define BSP_IDLE_TASK_BODY bsp_ppc_idle_task_body +extern void *bsp_ppc_idle_task_body(uintptr_t arg); +#endif + +#include <bsp/openpic.h> +/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver + * to implement VME IRQ priorities in software. + * Note that this requires support by the interrupt controller + * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c) + * and the BSP-specific universe initialization/configuration + * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c) + * + * ********* IMPORTANT NOTE ******** + * When deriving from this file (new BSPs) + * DO NOT define "BSP_PIC_DO_EOI" if you don't know what + * you are doing i.e., w/o implementing the required pieces + * mentioned above. + * ********* IMPORTANT NOTE ******** + */ +#define BSP_PIC_DO_EOI openpic_eoi(0) + +#ifndef ASM +#define outport_byte(port,value) outb(value,port) +#define outport_word(port,value) outw(value,port) +#define outport_long(port,value) outl(value,port) + +#define inport_byte(port,value) (value = inb(port)) +#define inport_word(port,value) (value = inw(port)) +#define inport_long(port,value) (value = inl(port)) + +/* + * Vital Board data Start using DATA RESIDUAL + */ + +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * Start of the heap + */ +extern unsigned int BSP_heap_start; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +/* + * String passed by the bootloader. + */ +extern char *BSP_commandline_string; + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern int BSP_disconnect_clock_handler (void); +extern int BSP_connect_clock_handler (void); + +/* clear hostbridge errors + * + * NOTE: The routine returns always (-1) if 'enableMCP==1' + * [semantics needed by libbspExt] if the MCP input is not wired. + * It returns and clears the error bits of the PCI status register. + * MCP support is disabled because: + * a) the 2100 has no raven chip + * b) the raven (2300) would raise machine check interrupts + * on PCI config space access to empty slots. + */ +extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for BSP methods which cross file boundaries + */ +void VIA_isa_bridge_interrupts_setup(void); + +#endif + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..9b355819f1 --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h @@ -0,0 +1,233 @@ +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H + +/* BSP specific address space configuration parameters */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/* + * The BSP maps VME address ranges into + * one BAT. + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout: + * + * BSP_VME_BAT_IDX defines + * which BAT to use for mapping the VME bus. + * If this is undefined, no extra BAT will be + * configured and VME has to share the available + * PCI address space with PCI devices. + * + * If you do define BSP_VME_BAT_IDX you must + * make sure the corresponding BAT is really + * available and unused! + */ + +#if defined(mvme2100) +#define _VME_A32_WIN0_ON_PCI 0x90000000 +#define _VME_A24_ON_PCI 0x9f000000 +#define _VME_A16_ON_PCI 0x9fff0000 +#define BSP_VME_BAT_IDX 1 +#else +#define _VME_A32_WIN0_ON_PCI 0x10000000 +#define _VME_A24_ON_PCI 0x1f000000 +#define _VME_A16_ON_PCI 0x1fff0000 +#define BSP_VME_BAT_IDX 0 +#endif + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a run-time configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map the board RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0xc0000000 + +/* Define BSP_PCI_VME_DRIVER_DOES_EOI to let the vmeUniverse + * driver (Tsi148 driver doesn't implement this) implement + * VME IRQ priorities in software. + * + * Here's how this works: + * + * 1) VME IRQ happens + * 2) universe propagates IRQ to PCI/PPC/main interrupt + * controller ('PIC' - programmable interrupt controller). + * 3) PIC driver dispatches universe driver's ISR + * 4) universe driver ISR acknowledges IRQ on VME, + * determines VME vector. + * ++++++++++++ stuff between ++ signs is related to SW priorities +++++++++ + * 5) universe driver *masks* all VME IRQ levels <= interrupting + * level. + * 6) universe driver calls PIC driver's 'EOI' routine. + * This effectively re-enables PCI and hence higher + * level VME interrupts. + * 7) universe driver dispatches user VME ISR. + * + * ++>> HIGHER PRIORITY VME IRQ COULD HAPPEN HERE and would be handled <<++ + * + * 8) user ISR returns, universe driver re-enables lower + * level VME interrupts, returns. + * 9) universe driver ISR returns control to PIC driver + * 10) PIC driver *omits* regular EOI sequence since this + * was already done by universe driver (step 6). + * ++++++++++++ end of special handling (SW priorities) ++++++++++++++++++++ + * 11) PIC driver ISR dispatcher returns. + * + * Note that the BSP *MUST* provide the following hooks + * in order for this to work: + * a) bsp.h must define the symbol BSP_PIC_DO_EOI to + * a sequence of instructions that terminates an + * interrupt at the interrupt controller. + * b) The interrupt controller driver must check the + * interrupt source and *must omit* running the EOI + * sequence if the interrupt source is the vmeUniverse + * (because the universe driver already ran BSP_PIC_DO_EOI) + * The interrupt controller must define the variable + * + * int _BSP_vme_bridge_irq = -1; + * + * which is assigned the universe's interrupt line information + * by vme_universe.c:BSP_VMEIrqMgrInstall(). The interrupt + * controller driver may use this variable to determine + * if an IRQ was caused by the universe. + * + * c) define BSP_PCI_VME_DRIVER_DOES_EOI + * + * NOTE: If a) and b) are not implemented by the BSP + * BSP_PCI_VME_DRIVER_DOES_EOI must be *undefined*. + */ +#define BSP_PCI_VME_DRIVER_DOES_EOI + +#ifdef BSP_PCI_VME_DRIVER_DOES_EOI +/* don't reference vmeUniverse0PciIrqLine directly from the irq + * controller driver - leave it up to BSP_VMEIrqMgrInstall() to + * set _BSP_vme_bridge_irq. That way, we can avoid linking + * the universe driver if VME is unused... + */ +extern int _BSP_vme_bridge_irq; +#endif + +/* If your BSP requires a non-standard way to configure + * the VME interrupt manager then define the symbol + * + * BSP_VME_UNIVERSE_INSTALL_IRQ_MGR + * + * to a proper instruction sequence that installs the + * universe interrupt manager. This requires knowledge + * of the wiring between the universe and the PIC (main + * interrupt controller), i.e., which IRQ 'pins' of the + * universe are wired to which 'lines'/inputs at the PIC. + * (consult vmeUniverse.h for more information). + * + * When installing the universe IRQ manager it is also + * possible to specify whether it should try to share + * PIC interrupts with other sources. This might not + * be supported by all BSPs (but the unverse driver + * recognizes that). + * + * If BSP_VME_UNIVERSE_INSTALL_IRQ_MGR is undefined then + * the default algorithm is used (vme_universe.c): + * + * This default setup uses only a single wire. It reads + * the PIC 'line' from PCI configuration space and assumes + * this to be wired to the first (LIRQ0) IRQ input at the + * universe. The default setup tries to use interrupt + * sharing. + */ + +#include <bsp/motorola.h> +#include <bsp/pci.h> + +#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ +do { \ +int bus, dev, i = 0, j; \ +const struct _int_map *bspmap; \ + /* install the VME interrupt manager; \ + * if there's a bsp route map, use it to \ + * configure additional lines... \ + */ \ + err = -1; \ + if (0 == pci_find_device(0x10e3, 0x0000, 0, &bus, &dev, &i)){ \ + if ( (bspmap = motorolaIntMap(currentBoard)) ) { \ + for ( i=0; bspmap[i].bus >= 0; i++ ) { \ + if ( bspmap[i].bus == bus && bspmap[i].slot == dev ) { \ + int pins[5], names[4]; \ + /* found it; use info here... */ \ + /* copy up to 4 entries; terminated with -1 pin */ \ + for ( j=0; \ + j<5 && (pins[j]=bspmap[i].pin_route[j].pin-1)>=0; \ + j++) { \ + names[j] = bspmap[i].pin_route[j].int_name[0]; \ + } \ + pins[4] = -1; \ + if ( 0 == vmeUniverseInstallIrqMgrAlt( \ + VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, /* shared IRQs */\ + pins[0], names[0], \ + pins[1], names[1], \ + pins[2], names[2], \ + pins[3], names[3], \ + -1) ) { \ + i = -1; \ + break; \ + } \ + } \ + } \ + } \ + if ( i >= 0 ) \ + err = vmeUniverseInstallIrqMgrAlt( \ + VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, \ + 0,-1, \ + -1); \ + } \ +} while (0) + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +#endif diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h new file mode 100644 index 0000000000..2d575d8122 --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h @@ -0,0 +1,204 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by RTEMS to write interrupt handlers. + * + * Copyright (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef BSP_POWERPC_IRQ_H +#define BSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include <rtems/irq.h> + +/* + * 8259 edge/level control definitions at VIA + */ +#define ISA8259_M_ELCR 0x4d0 +#define ISA8259_S_ELCR 0x4d1 + +#define ELCRS_INT15_LVL 0x80 +#define ELCRS_INT14_LVL 0x40 +#define ELCRS_INT13_LVL 0x20 +#define ELCRS_INT12_LVL 0x10 +#define ELCRS_INT11_LVL 0x08 +#define ELCRS_INT10_LVL 0x04 +#define ELCRS_INT9_LVL 0x02 +#define ELCRS_INT8_LVL 0x01 +#define ELCRM_INT7_LVL 0x80 +#define ELCRM_INT6_LVL 0x40 +#define ELCRM_INT5_LVL 0x20 +#define ELCRM_INT4_LVL 0x10 +#define ELCRM_INT3_LVL 0x8 +#define ELCRM_INT2_LVL 0x4 +#define ELCRM_INT1_LVL 0x2 +#define ELCRM_INT0_LVL 0x1 + + /* PIC's command and mask registers */ +#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ +#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ +#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ +#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ + + /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ +#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ +#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ +#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * rtems_irq_number Definitions + */ + +/* + * ISA IRQ handler related definitions + */ +#define BSP_ISA_IRQ_NUMBER (16) +#define BSP_ISA_IRQ_LOWEST_OFFSET (0) +#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#ifndef qemu +#define BSP_PCI_IRQ_NUMBER (16) +#else +#define BSP_PCI_IRQ_NUMBER (0) +#endif +#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) +/* + * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) +/* Misc vectors for OPENPIC irqs (IPI, timers) + */ +#ifndef qemu +#define BSP_MISC_IRQ_NUMBER (8) +#else +#define BSP_MISC_IRQ_NUMBER (0) +#endif + +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) +/* + * Some ISA IRQ symbolic name definition + */ +#define BSP_ISA_PERIODIC_TIMER (0) +#define BSP_ISA_KEYBOARD (1) +#define BSP_ISA_UART_COM2_IRQ (3) +#define BSP_ISA_UART_COM1_IRQ (4) +#define BSP_ISA_RT_TIMER1 (8) +#define BSP_ISA_RT_TIMER3 (10) +/* + * Some PCI IRQ symbolic name definition + */ +#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) +#if BSP_PCI_IRQ_NUMBER > 0 +#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) +#endif + +#if defined(mvme2100) +#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) +#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) +#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) +#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4) +#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5) +#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7) +#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) +#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) +#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) +#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13) +#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14) +#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15) +#else +#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ +#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ +#endif + +/* + * Some Processor execption handled as RTEMS IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + + +/* + * Type definition for RTEMS managed interrupts + */ +typedef unsigned short rtems_i8259_masks; + +extern volatile rtems_i8259_masks i8259s_cache; + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ +/* + * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- + */ +void BSP_i8259s_init(void); + +/* + * function to disable a particular irq at 8259 level. After calling + * this function, even if the device asserts the interrupt line it will + * not be propagated further to the processor + * + * RETURNS: 1/0 if the interrupt was enabled/disabled originally or + * a value < 0 on error. + */ +int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); +/* + * function to enable a particular irq at 8259 level. After calling + * this function, if the device asserts the interrupt line it will + * be propagated further to the processor + */ +int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); +/* + * function to acknowledge a particular irq at 8259 level. After calling + * this function, if a device asserts an enabled interrupt line it will + * be propagated further to the processor. Mainly usefull for people + * writing raw handlers as this is automagically done for RTEMS managed + * handlers. + */ +int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); +/* + * function to check if a particular irq is enabled at 8259 level. After calling + */ +int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); +extern void BSP_i8259s_init(void); + +/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */ +#include <bsp/irq_supp.h> + +#ifdef __cplusplus +}; +#endif + +#endif +#endif diff --git a/bsps/powerpc/motorola_powerpc/include/tm27.h b/bsps/powerpc/motorola_powerpc/include/tm27.h new file mode 100644 index 0000000000..81eb55a54a --- /dev/null +++ b/bsps/powerpc/motorola_powerpc/include/tm27.h @@ -0,0 +1,64 @@ +/* + * @file + * @ingroup powerpc_motorola_powerpc + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + */ + +#include <bsp/irq.h> + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + rtems_fatal_error_occurred(1); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 8; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/mpc55xxevb/headers.am b/bsps/powerpc/mpc55xxevb/headers.am new file mode 100644 index 0000000000..6dffbe060c --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/headers.am @@ -0,0 +1,15 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h diff --git a/bsps/powerpc/mpc55xxevb/include/bsp.h b/bsps/powerpc/mpc55xxevb/include/bsp.h new file mode 100644 index 0000000000..eee5d208c1 --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp.h @@ -0,0 +1,104 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Global BSP variables and functions + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_BSP_H +#define LIBBSP_POWERPC_MPC55XXEVB_BSP_H + +#include <bspopts.h> + +#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN + +#define BSP_FEATURE_IRQ_EXTENSION + +#define MPC55XX_PERIPHERAL_CLOCK \ + (MPC55XX_SYSTEM_CLOCK / MPC55XX_SYSTEM_CLOCK_DIVIDER) + +#ifndef ASM + +#include <rtems.h> + +#include <libcpu/powerpc-utility.h> + +#include <bsp/tictac.h> +#include <bsp/linker-symbols.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @brief System clock frequency */ +extern unsigned int bsp_clock_speed; + +/** @brief Time base clicks per micro second */ +extern uint32_t bsp_clicks_per_usec; + +/** @brief Convert Decrementer ticks to microseconds */ +#define BSP_Convert_decrementer( _value ) \ + (((unsigned long long) (_value)) / ((unsigned long long)bsp_clicks_per_usec)) + +rtems_status_code mpc55xx_sd_card_init( bool mount); + +/* Network driver configuration */ + +struct rtems_bsdnet_ifconfig; + +int smsc9218i_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH smsc9218i_attach_detach + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" + +rtems_status_code bsp_register_i2c(void); + +void bsp_restart(void *addr); + +void *bsp_idle_thread(uintptr_t arg); + +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +LINKER_SYMBOL(bsp_section_dsram_begin) +LINKER_SYMBOL(bsp_section_dsram_end) +LINKER_SYMBOL(bsp_section_dsram_size) +LINKER_SYMBOL(bsp_section_dsram_load_begin) +LINKER_SYMBOL(bsp_section_dsram_load_end) + +#define BSP_DSRAM_SECTION __attribute__((section(".bsp_dsram"))) + +LINKER_SYMBOL(bsp_section_sysram_begin) +LINKER_SYMBOL(bsp_section_sysram_end) +LINKER_SYMBOL(bsp_section_sysram_size) +LINKER_SYMBOL(bsp_section_sysram_load_begin) +LINKER_SYMBOL(bsp_section_sysram_load_end) + +#define BSP_SYSRAM_SECTION __attribute__((section(".bsp_sysram"))) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_BSP_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h new file mode 100644 index 0000000000..4be6788141 --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-esci.h @@ -0,0 +1,57 @@ +/** + * @file + * + * @brief Console ESCI API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H +#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H + +#include "console-generic.h" + +#undef CR0 +#undef CR1 +#undef CR2 +#undef CR3 + +#include <mpc55xx/regs.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef MPC55XX_HAS_ESCI + +extern const console_generic_callbacks mpc55xx_esci_callbacks; + +typedef struct { + volatile struct ESCI_tag *regs; + struct rtems_termios_tty *tty; + int transmit_nest_level; + bool transmit_in_progress; + rtems_vector_number irq; +} mpc55xx_esci_context; + +extern mpc55xx_esci_context mpc55xx_esci_devices []; + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h new file mode 100644 index 0000000000..c3f7a4628f --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-generic.h @@ -0,0 +1,81 @@ +/** + * @file + * + * @brief Generic console driver API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_SHARED_CONSOLE_GENERIC_H +#define LIBBSP_SHARED_CONSOLE_GENERIC_H + +#include <rtems/libio.h> +#include <rtems/termiostypes.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_callbacks termios_callbacks; + int (*poll_read)(int minor); + void (*poll_write)(int minor, char c); +} console_generic_callbacks; + +typedef struct { + void *context; + const console_generic_callbacks *callbacks; + const char *device_path; +} console_generic_info; + +extern const console_generic_info console_generic_info_table []; + +extern const size_t console_generic_info_count; + +extern const rtems_device_minor_number console_generic_minor; + +#define CONSOLE_GENERIC_INFO_TABLE \ + const console_generic_info console_generic_info_table [] + +#define CONSOLE_GENERIC_INFO(context, callbacks, device_path) \ + { context, callbacks, device_path } + +#define CONSOLE_GENERIC_INFO_COUNT \ + const size_t console_generic_info_count = \ + sizeof(console_generic_info_table) / sizeof(console_generic_info_table [0]) + +#define CONSOLE_GENERIC_MINOR(minor) \ + const rtems_device_minor_number console_generic_minor = (minor) + +static inline void *console_generic_get_context(int minor) +{ + return console_generic_info_table [minor].context; +} + +static inline struct rtems_termios_tty *console_generic_get_tty_at_open( + void *arg +) +{ + const rtems_libio_open_close_args_t *oc = + (const rtems_libio_open_close_args_t *) arg; + + return (struct rtems_termios_tty *) oc->iop->data1; +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_SHARED_CONSOLE_GENERIC_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h b/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h new file mode 100644 index 0000000000..c70f36d13b --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/console-linflex.h @@ -0,0 +1,64 @@ +/** + * @file + * + * @brief Console LINFlexD API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H +#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H + +#include "console-generic.h" + +#undef CR0 +#undef CR1 +#undef CR2 +#undef CR3 + +#include <mpc55xx/regs.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef MPC55XX_HAS_LINFLEX + +extern const console_generic_callbacks mpc55xx_linflex_callbacks; + +typedef struct { + volatile LINFLEX_tag *regs; + struct rtems_termios_tty *tty; + rtems_vector_number irq_rxi; + rtems_vector_number irq_txi; + rtems_vector_number irq_err; + volatile SIU_PCR_tag *tx_pcr_register; + uint8_t tx_pa_value:2; + volatile SIU_PCR_tag *rx_pcr_register; + volatile SIUL_PSMI_8B_tag *rx_psmi_register; + uint8_t rx_padsel_value:4; + int transmit_nest_level; + bool transmit_in_progress; +} mpc55xx_linflex_context; + +extern mpc55xx_linflex_context mpc55xx_linflex_devices []; + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/irq.h b/bsps/powerpc/mpc55xxevb/include/bsp/irq.h new file mode 100644 index 0000000000..4efa92219e --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/irq.h @@ -0,0 +1,499 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief IRQ + */ + +/* + * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H + +#include <rtems/irq-extension.h> +#include <rtems/irq.h> + +#include <bspopts.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* + * Interrupt numbers + */ + +#define MPC55XX_IRQ_INVALID 0x10000U +#define MPC55XX_IRQ_MIN 0U + +/* Software interrupts */ +#define MPC55XX_IRQ_SOFTWARE_MIN 0U +#define MPC55XX_IRQ_SOFTWARE_MAX 7U +#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v) +#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i) +#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U) + +#if MPC55XX_CHIP_FAMILY == 551 + #define MPC55XX_IRQ_MAX 293U + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID) + + /* I2C */ + #define MPC55XX_IRQ_I2C(mod) \ + ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID) + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U + #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U + + /* PIT */ + #define MPC55XX_IRQ_RTI 148U + #define MPC55XX_IRQ_PIT(timer) (148U + (timer)) + + /* eTPU */ + #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID + + /* DSPI */ + #define MPC55XX_IRQ_DSPI_BASE(mod) \ + ((mod) == 0 ? 117U : \ + ((mod) == 1 ? 122U : \ + ((mod) == 2 ? 274U : \ + ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID)))) + + /* eMIOS */ + #define MPC55XX_IRQ_EMIOS(ch) \ + ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID) + + /* eQADC */ + #define MPC55XX_IRQ_EQADC_BASE(mod) \ + ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID) + + /* eSCI */ + #define MPC55XX_IRQ_ESCI(mod) \ + ((mod) == 0 ? 113U : \ + ((mod) == 1 ? 114U : \ + ((mod) == 2 ? 115U : \ + ((mod) == 3 ? 116U : \ + ((mod) == 4 ? 270U : \ + ((mod) == 5 ? 271U : \ + ((mod) == 6 ? 272U : \ + ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID)))))))) + + /* FlexCAN */ + #define MPC55XX_IRQ_CAN_BASE(mod) \ + ((mod) == 0 ? 127U : \ + ((mod) == 1 ? 157U : \ + ((mod) == 2 ? 178U : \ + ((mod) == 3 ? 199U : \ + ((mod) == 4 ? 220U : \ + ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID)))))) + + /* FlexRay */ + #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ + ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID) +#elif MPC55XX_CHIP_FAMILY == 564 + #define MPC55XX_IRQ_MAX 255U + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID) + + /* SWT */ + #define MPC55XX_IRQ_SWT_0 28U + #define MPC55XX_IRQ_SWT_1 29U + + /* STM */ + #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U) + + /* ECSM */ + #define MPC55XX_IRQ_ECSM_FAS 9U + #define MPC55XX_IRQ_ECSM_NCE 35U + #define MPC55XX_IRQ_ECSM_COR 36U + + /* MC */ + #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U + #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U + #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U + #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U + #define MPC55XX_IRQ_MC_RGM_FRAE 56U + + /* XOSC */ + #define MPC55XX_IRQ_XOSC 57U + + /* PIT */ + #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ + ((ch) == 3 ? 127U : ((ch) + 59U)) + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U + + /* ADC */ + #define MPC55XX_IRQ_ADC_BASE(mod) \ + ((mod) == 0 ? 62U : \ + ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID)) + + /* DSPI */ + #define MPC55XX_IRQ_DSPI_BASE(mod) \ + ((mod) == 0 ? 74U : \ + ((mod) == 1 ? 94U : \ + ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID))) + + /* FlexCAN */ + #define MPC55XX_IRQ_CAN_BASE(mod) \ + ((mod) == 0 ? 65U : \ + ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID)) + + /* FlexPWM */ + #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \ + ((mod) == 0 ? 179U : \ + ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID)) + + /* FlexRay */ + #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ + ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID) + + /* LINFlexD */ + #define MPC55XX_IRQ_LINFLEX_BASE(mod) \ + ((mod) == 0 ? 79U : \ + ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID)) + + /* eTimer */ + #define MPC55XX_IRQ_ETIMER_BASE(mod) \ + ((mod) == 0 ? 157U : \ + ((mod) == 1 ? 168U : \ + ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID))) + + /* CTU */ + #define MPC55XX_IRQ_CTU_MRS 193U + #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U) + #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U) + #define MPC55XX_IRQ_CTU_ADC 206U + #define MPC55XX_IRQ_CTU_ERR 207U + + /* SEMA */ + #define MPC55XX_IRQ_SEMA_0 247U + #define MPC55XX_IRQ_SEMA_1 248U + + /* FCCU */ + #define MPC55XX_IRQ_FCCU_ALRM 250U + #define MPC55XX_IRQ_FCCU_CFG_TO 251U + #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U + #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U + + /* PMU */ + #define MPC55XX_IRQ_PMU 254U + + /* SWG */ + #define MPC55XX_IRQ_SWG 255U +#elif MPC55XX_CHIP_FAMILY == 566 + #define MPC55XX_IRQ_MAX 315U + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID) + + /* PIT */ + #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ + ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID) + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U + + /* eMIOS */ + #define MPC55XX_IRQ_EMIOS(ch) \ + ((unsigned) (ch) < 24U ? 58U + (ch) : \ + ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID)) + + /* eSCI */ + #define MPC55XX_IRQ_ESCI(mod) \ + ((unsigned) (mod) < 4U ? 113U + (mod) : \ + ((unsigned) (mod) < 8U ? 270U + (mod) : \ + ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID))) +#else + #if MPC55XX_CHIP_FAMILY == 555 + #define MPC55XX_IRQ_MAX 307U + #elif MPC55XX_CHIP_FAMILY == 556 + #define MPC55XX_IRQ_MAX 360U + #elif MPC55XX_CHIP_FAMILY == 567 + #define MPC55XX_IRQ_MAX 479U + #else + #error "unsupported chip type" + #endif + + /* eDMA */ + #define MPC55XX_IRQ_EDMA_ERROR(group) \ + ((group) == 0 ? 10U : \ + ((group) == 1 ? 210U : \ + ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID))) + #define MPC55XX_IRQ_EDMA(ch) \ + ((unsigned) (ch) < 32U ? 11U + (ch) : \ + ((unsigned) (ch) < 64U ? 179U + (ch) : \ + ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID))) + + /* I2C */ + #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID + + /* SIU external interrupts */ + #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U + #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U + #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U + #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U + #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U + + /* PIT */ + #define MPC55XX_IRQ_RTI 305U + #define MPC55XX_IRQ_PIT(ch) (301U + (ch)) + + /* eTPU */ + #define MPC55XX_IRQ_ETPU_BASE(mod) \ + ((mod) == 0 ? 67U : \ + ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID)) + + /* DSPI */ + #define MPC55XX_IRQ_DSPI_BASE(mod) \ + ((mod) == 0 ? 275U : \ + ((mod) == 1 ? 131U : \ + ((mod) == 2 ? 136U : \ + ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID)))) + + /* eMIOS */ + #define MPC55XX_IRQ_EMIOS(ch) \ + ((unsigned) (ch) < 16U ? 51U + (ch) : \ + ((unsigned) (ch) < 24U ? 186U + (ch) : \ + ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID))) + + /* eQADC */ + #define MPC55XX_IRQ_EQADC_BASE(mod) \ + ((mod) == 0 ? 100U : \ + ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID)) + + /* eSCI */ + #define MPC55XX_IRQ_ESCI(mod) \ + ((mod) == 0 ? 146U : \ + ((mod) == 1 ? 149U : \ + ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID))) + + /* FlexCAN */ + #define MPC55XX_IRQ_CAN_BASE(mod) \ + ((mod) == 0 ? 152U : \ + ((mod) == 1 ? 280U : \ + ((mod) == 2 ? 173U : \ + ((mod) == 3 ? 308U : \ + ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID))))) + + /* FlexRay */ + #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ + ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID) +#endif + +#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U) + +/* ADC */ +#define MPC55XX_IRQ_ADC_EOC(mod) \ + (MPC55XX_IRQ_ADC_BASE(mod) + 0U) +#define MPC55XX_IRQ_ADC_ER(mod) \ + (MPC55XX_IRQ_ADC_BASE(mod) + 1U) +#define MPC55XX_IRQ_ADC_WD(mod) \ + (MPC55XX_IRQ_ADC_BASE(mod) + 2U) + +/* eTimer */ +#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \ + (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch)) +#define MPC55XX_IRQ_ETIMER_WTIF(mod) \ + (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U) +#define MPC55XX_IRQ_ETIMER_RCF(mod) \ + (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U) + +/* eTPU */ +#define MPC55XX_IRQ_ETPU(mod) \ + (MPC55XX_IRQ_ETPU_BASE(mod) + 0U) +#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \ + (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch)) + +/* DSPI */ +#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U) +#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U) +#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U) +#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U) +#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U) + +/* eQADC */ +#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 0U) +#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U) +#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U) +#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U) +#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U) +#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \ + (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U) + +/* FlexCAN */ +#if MPC55XX_CHIP_FAMILY == 564 + #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U) + #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U) + #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U) + #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U) + #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U) + #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U) + #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U) +#else + #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U) + #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U) + #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U) + #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U) + #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U) + #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U) + #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U) + #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U) + #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U) + #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U) + #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U) + #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U) + #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U) + #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U) + #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U) + #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U) + #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U) + #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U) + #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U) + #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U) +#endif + +/* FlexPWM */ +#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U) +#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U) +#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U) +#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U) +#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U) + +/* FlexRay */ +#if MPC55XX_CHIP_FAMILY == 564 + #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U) + #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U) + #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U) + #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U) + #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U) + #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U) + #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U) + #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U) + #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U) + #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U) +#else + #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U) + #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U) + #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U) + #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U) + #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U) + #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U) + #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U) + #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U) +#endif + +/* LINFlexD */ +#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U) +#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U) +#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U) + +/* Checks */ +#define MPC55XX_IRQ_IS_VALID(v) \ + ((v) >= MPC55XX_IRQ_MIN && \ + (v) <= MPC55XX_IRQ_MAX) +#define MPC55XX_IRQ_IS_SOFTWARE(v) \ + ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \ + (v) <= MPC55XX_IRQ_SOFTWARE_MAX) + +/* + * Interrupt controller + */ + +#define MPC55XX_INTC_MIN_PRIORITY 1U +#define MPC55XX_INTC_MAX_PRIORITY 15U +#define MPC55XX_INTC_DISABLED_PRIORITY 0U +#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1) +#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1) +#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \ + ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY) + +rtems_status_code mpc55xx_interrupt_handler_install( + rtems_vector_number vector, + const char *info, + rtems_option options, + unsigned priority, + rtems_interrupt_handler handler, + void *arg +); + +rtems_status_code mpc55xx_intc_get_priority( + rtems_vector_number vector, + unsigned *priority +); + +rtems_status_code mpc55xx_intc_set_priority( + rtems_vector_number vector, + unsigned priority +); + +rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector); + +rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector); + +/** + * @addtogroup bsp_interrupt + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN + +#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX + +#ifdef BSP_INTERRUPT_HANDLER_TABLE_SIZE + #define BSP_INTERRUPT_USE_INDEX_TABLE + #define BSP_INTERRUPT_NO_HEAP_USAGE +#endif + +/** @} */ + +/* Legacy API */ +#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch) +#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch) + +#ifdef __cplusplus +}; +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_IRQ_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h b/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h new file mode 100644 index 0000000000..b432b9cecd --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/mpc55xx-config.h @@ -0,0 +1,170 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief Low-level configuration. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H +#define LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H + +#include <stddef.h> + +#include <libcpu/powerpc-utility.h> + +#include <bsp/start.h> + +#include <mpc55xx/regs.h> +#include <mpc55xx/regs-mmu.h> +#include <mpc55xx/siu.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + uint32_t index : 10; + uint32_t count : 10; + uint32_t output : 1; + union SIU_PCR_tag pcr; +} mpc55xx_siu_pcr_config; + +extern BSP_START_DATA_SECTION const mpc55xx_siu_pcr_config + mpc55xx_start_config_siu_pcr []; + +extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_siu_pcr_count []; + +extern BSP_START_DATA_SECTION const struct + MMU_tag mpc55xx_start_config_mmu_early []; + +extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_mmu_early_count []; + +extern BSP_START_DATA_SECTION const struct + MMU_tag mpc55xx_start_config_mmu []; + +extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_mmu_count []; + +#ifdef MPC55XX_HAS_FMPLL + typedef struct { + union FMPLL_SYNCR_tag syncr_tmp; + union FMPLL_SYNCR_tag syncr_final; + } mpc55xx_clock_config; +#endif + +#ifdef MPC55XX_HAS_FMPLL_ENHANCED + typedef struct { + union FMPLL_ESYNCR2_tag esyncr2_tmp; + union FMPLL_ESYNCR2_tag esyncr2_final; + union FMPLL_ESYNCR1_tag esyncr1_final; + } mpc55xx_clock_config; +#endif + +#ifdef MPC55XX_HAS_MODE_CONTROL + typedef struct { + struct { + PLLD_CR_32B_tag cr; + PLLD_MR_32B_tag mr; + } fmpll [2]; + CGM_OC_EN_32B_tag oc_en; + CGM_OCDS_SC_32B_tag ocds_sc; + CGM_SC_DC0_3_32B_tag sc_dc0_3; + CGM_AUXCLK_tag auxclk [5]; + } mpc55xx_clock_config; +#endif + +extern BSP_START_DATA_SECTION const mpc55xx_clock_config + mpc55xx_start_config_clock []; + +#ifdef MPC55XX_HAS_EBI + typedef struct { + union EBI_MCR_tag ebi_mcr; + uint32_t siu_eccr_ebdf; + } mpc55xx_ebi_config; + + extern BSP_START_DATA_SECTION const mpc55xx_ebi_config + mpc55xx_start_config_ebi []; + + extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_ebi_count []; + + extern BSP_START_DATA_SECTION const struct EBI_CS_tag + mpc55xx_start_config_ebi_cs []; + + extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_ebi_cs_count []; + + extern BSP_START_DATA_SECTION const struct EBI_CAL_CS_tag + mpc55xx_start_config_ebi_cal_cs []; + + extern BSP_START_DATA_SECTION const size_t + mpc55xx_start_config_ebi_cal_cs_count []; +#endif + +/** + * @brief Start prologue. + * + * In case the BSP enabled the MPC55XX_ENABLE_START_PROLOGUE option, then this + * function will be called directly after the Boot Assist Module (BAM) jumped + * to the start entry defined by the reset configuration. + * + * This function executes in the context initialized by the BAM. There exists + * no valid stack pointer and the internal RAM has an invalid ECC state. + * + * The default implementation does nothing. The application may provide its + * own implementation. + */ +void mpc55xx_start_prologue(void); + +void mpc55xx_start_early(void); + +void mpc55xx_start_flash(void); + +void mpc55xx_start_cache(void); + +void mpc55xx_start_clock(void); + +void mpc55xx_start_watchdog(void); + +void mpc55xx_start_mmu_apply_config(const struct MMU_tag *config, size_t count); + +uint32_t mpc55xx_get_system_clock(void); + +LINKER_SYMBOL(bsp_ram_start) +LINKER_SYMBOL(bsp_ram_end) +LINKER_SYMBOL(bsp_ram_size) + +LINKER_SYMBOL(bsp_ram_1_start) +LINKER_SYMBOL(bsp_ram_1_end) +LINKER_SYMBOL(bsp_ram_1_size) + +LINKER_SYMBOL(bsp_rom_start) +LINKER_SYMBOL(bsp_rom_end) +LINKER_SYMBOL(bsp_rom_size) + +#ifdef MPC55XX_BOOTFLAGS + extern uint32_t mpc55xx_bootflag_0 []; +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H */ diff --git a/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h b/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h new file mode 100644 index 0000000000..e4366b039c --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/bsp/smsc9218i.h @@ -0,0 +1,704 @@ +/** + * @file + * + * @ingroup mpc55xx + * + * @brief SMSC - LAN9218i + */ + +/* + * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp.h> + +/** + * @name Memory Map + * @{ + */ + +typedef struct { + uint32_t rx_fifo_data; + uint32_t rx_fifo_data_aliases [7]; + uint32_t tx_fifo_data; + uint32_t tx_fifo_data_aliases [7]; + uint32_t rx_fifo_status; + uint32_t rx_fifo_status_peek; + uint32_t tx_fifo_status; + uint32_t tx_fifo_status_peek; + uint32_t id_rev; + uint32_t irq_cfg; + uint32_t int_sts; + uint32_t int_en; + uint32_t reserved_0; + uint32_t byte_test; + uint32_t fifo_int; + uint32_t rx_cfg; + uint32_t tx_cfg; + uint32_t hw_cfg; + uint32_t rx_dp_ctl; + uint32_t rx_fifo_inf; + uint32_t tx_fifo_inf; + uint32_t pmt_ctrl; + uint32_t gpio_cfg; + uint32_t gpt_cfg; + uint32_t gpt_cnt; + uint32_t reserved_1; + uint32_t word_swap; + uint32_t free_run; + uint32_t rx_drop; + uint32_t mac_csr_cmd; + uint32_t mac_csr_data; + uint32_t afc_cfg; + uint32_t e2p_cmd; + uint32_t e2p_data; +} smsc9218i_registers; + +/* + * SMSC9218 registers are accessed little-endian (address 0x3fff8000, A22 used + * as END_SEL). + */ +#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT + volatile smsc9218i_registers *const smsc9218i = + (volatile smsc9218i_registers *) 0x3fff8000; + volatile smsc9218i_registers *const smsc9218i_dma = + (volatile smsc9218i_registers *) 0x3fff8200; +#else + volatile smsc9218i_registers *const smsc9218i = + (volatile smsc9218i_registers *) 0x3fff8000; + volatile smsc9218i_registers *const smsc9218i_dma = + (volatile smsc9218i_registers *) 0x3fff8000; +#endif + +/** @} */ + +#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT + #define SMSC9218I_BIT_POS(pos) (pos) +#else + #define SMSC9218I_BIT_POS(pos) \ + ((pos) > 15 ? \ + ((pos) > 23 ? (pos) - 24 : (pos) - 8) \ + : ((pos) > 7 ? (pos) + 8 : (pos) + 24)) +#endif + +#define SMSC9218I_FLAG(pos) \ + (1U << SMSC9218I_BIT_POS(pos)) + +#define SMSC9218I_FIELD_8(val, pos) \ + (((val) & 0xff) << SMSC9218I_BIT_POS(pos)) + +#define SMSC9218I_GET_FIELD_8(reg, pos) \ + (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff) + +#define SMSC9218I_FIELD_16(val, pos) \ + (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \ + | SMSC9218I_FIELD_8((val), pos)) + +#define SMSC9218I_GET_FIELD_16(reg, pos) \ + ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \ + | SMSC9218I_GET_FIELD_8(reg, pos)) + +#ifdef SMSC9218I_BIG_ENDIAN_SUPPORT + #define SMSC9218I_SWAP(val) (val) +#else + #define SMSC9218I_SWAP(val) \ + ((((val) >> 24) & 0xff) \ + | ((((val) >> 16) & 0xff) << 8) \ + | ((((val) >> 8) & 0xff) << 16) \ + | (((val) & 0xff) << 24)) +#endif + +/** + * @name Receive Status + * @{ + */ + +#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30) +#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff) +#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15) +#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13) +#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12) +#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11) +#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10) +#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7) +#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6) +#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5) +#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4) +#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3) +#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2) +#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1) + +/** @} */ + +/** + * @name Transmit Status + * @{ + */ + +#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) +#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15) +#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11) +#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10) +#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9) +#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8) +#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2) +#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Transmit Command A + * @{ + */ + +#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31) +#define SMSC9218I_TX_A_END_ALIGN_4 0 +#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24) +#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25) +#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16) +#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13) +#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12) +#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0) + +/** @} */ + +/** + * @name Transmit Command B + * @{ + */ + +#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16) +#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) +#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13) +#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12) +#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0) + +/** @} */ + +/** + * @name Chip ID and Revision + * @{ + */ + +#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16) +#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0) +#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U +#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU + +/** @} */ + +/** + * @name Interrupt Configuration + * @{ + */ + +#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24) +#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24) +#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14) +#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13) +#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12) +#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8) +#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4) +#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Interrupt Enable and Status + * @{ + */ + +#define SMSC9218I_INT_SW SMSC9218I_FLAG(31) +#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25) +#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24) +#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23) +#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21) +#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20) +#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19) +#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18) +#define SMSC9218I_INT_PME SMSC9218I_FLAG(17) +#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16) +#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15) +#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14) +#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13) +#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10) +#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9) +#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8) +#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7) +#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4) +#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3) +#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2) +#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1) +#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Byte Order Testing + * @{ + */ + +#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U) + +/** @} */ + +/** + * @name FIFO Level Interrupts + * @{ + */ + +#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24) +#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24) +#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16) +#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0) +#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0) + +/** @} */ + +/** + * @name Receive Configuration + * @{ + */ + +#define SMSC9218I_RX_CFG_END_ALIGN_4 0 +#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30) +#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31) +#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24) +#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24) +#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15) +#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8) +#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8) + +/** @} */ + +/** + * @name Transmit Configuration + * @{ + */ + +#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15) +#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14) +#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2) +#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1) +#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Hardware Configuration + * @{ + */ + +#define SMSC9218I_HW_CFG_LED_3 SMSC9218I_FLAG(30) +#define SMSC9218I_HW_CFG_LED_2 SMSC9218I_FLAG(29) +#define SMSC9218I_HW_CFG_LED_1 SMSC9218I_FLAG(28) +#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24) +#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20) +#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16) +#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2) +#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1) +#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name Receive Datapath Control + * @{ + */ + +#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31) + +/** @} */ + +/** + * @name Receive FIFO Information + * @{ + */ + +#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name Transmit FIFO Information + * @{ + */ + +#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) +#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name Power Management Control + * @{ + */ + +#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0 +#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12) +#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13) +#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10) +#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9) +#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8) +#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6) +#define SMSC9218I_PMT_CTRL_WUPS_NO 0 +#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4) +#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5) +#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3) +#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2) +#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1) +#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0) + +/** @} */ + +/** + * @name General Purpose IO Configuration + * @{ + */ + +#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30) +#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29) +#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28) +#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26) +#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25) +#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24) +#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18) +#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17) +#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16) +#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10) +#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9) +#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8) +#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4) +#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3) +#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0) +#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2) +#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1) + +/** @} */ + +/** + * @name General Purpose Timer Configuration + * @{ + */ + +#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29) +#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0) +#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name General Purpose Timer Count + * @{ + */ + +#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0) + +/** @} */ + +/** + * @name Word Swap + * @{ + */ + +#define SMSC9218I_ENDIAN_BIG 0xffffffffU + +/** @} */ + +/** + * @name Free Run Counter + * @{ + */ + +#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg) + +/** @} */ + +/** + * @name Receiver Dropped Frames Counter + * @{ + */ + +#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg) + +/** @} */ + +/** + * @name EEPROM Command Register + * @{ + */ + +#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31) + +/** @} */ + +/** + * @name MAC Control and Status Synchronizer Command + * @{ + */ + +#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31) +#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30) +#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0) +#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0) + +/** @} */ + +/** + * @name MAC Control Register + * @{ + */ + +#define SMSC9218I_MAC_CR 0x00000001U +#define SMSC9218I_MAC_CR_RXALL 0x80000000U +#define SMSC9218I_MAC_CR_HBDIS 0x10000000U +#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U +#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U +#define SMSC9218I_MAC_CR_FDPX 0x00100000U +#define SMSC9218I_MAC_CR_MCPAS 0x00080000U +#define SMSC9218I_MAC_CR_PRMS 0x00040000U +#define SMSC9218I_MAC_CR_INVFILT 0x00020000U +#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U +#define SMSC9218I_MAC_CR_HFILT 0x00008000U +#define SMSC9218I_MAC_CR_HPFILT 0x00002000U +#define SMSC9218I_MAC_CR_LCOLL 0x00001000U +#define SMSC9218I_MAC_CR_BCAST 0x00000800U +#define SMSC9218I_MAC_CR_DISRTY 0x00000400U +#define SMSC9218I_MAC_CR_PADSTR 0x00000100U +#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U +#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U +#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U +#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U +#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U +#define SMSC9218I_MAC_CR_DFCHK 0x00000020U +#define SMSC9218I_MAC_CR_TXEN 0x00000008U +#define SMSC9218I_MAC_CR_RXEN 0x00000004U + +/** @} */ + +/** + * @name MAC Address High + * @{ + */ + +#define SMSC9218I_MAC_ADDRH 0x00000002U +#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU + +/** @} */ + +/** + * @name MAC Address Low + * @{ + */ + +#define SMSC9218I_MAC_ADDRL 0x00000003U +#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU + +/** @} */ + +/** + * @name Multicast Hash Table High + * @{ + */ + +#define SMSC9218I_MAC_HASHH 0x00000004U +#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU + +/** @} */ + +/** + * @name Multicast Hash Table Low + * @{ + */ + +#define SMSC9218I_MAC_HASHL 0x00000005U +#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU + +/** @} */ + +/** + * @name MII Access + * @{ + */ + +#define SMSC9218I_MAC_MII_ACC 0x00000006U +#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11) +#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1) +#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0) +#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6) + +/** @} */ + +/** + * @name MII Data + * @{ + */ + +#define SMSC9218I_MAC_MII_DATA 0x00000007U + +/** @} */ + +/** + * @name Flow Control + * @{ + */ + +#define SMSC9218I_MAC_FLOW 0x00000008U +#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U +#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U +#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U +#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U + +/** @} */ + +/** + * @name VLAN1 Tag + * @{ + */ + +#define SMSC9218I_MAC_VLAN1 0x00000009U + +/** @} */ + +/** + * @name VLAN2 Tag + * @{ + */ + +#define SMSC9218I_MAC_VLAN2 0x0000000aU + +/** @} */ + +/** + * @name Wake-up Frame Filter + * @{ + */ + +#define SMSC9218I_MAC_WUFF 0x0000000bU + +/** @} */ + +/** + * @name Wake-up Control and Status + * @{ + */ + +#define SMSC9218I_MAC_WUCSR 0x0000000cU +#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U +#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U +#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U +#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U +#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U + +/** @} */ + +/** + * @name PHY Identifier 1 + * @{ + */ + +#define SMSC9218I_PHY_ID1_LAN9118 0x7 + +/** @} */ + +/** + * @name PHY Identifier 2 + * @{ + */ + +#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3 + +/** @} */ + +/** + * @name Mode Control and Status + * @{ + */ + +#define SMSC9218I_PHY_MCSR 0x00000011U +#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U +#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U + +/** @} */ + +/** + * @name Special Modes + * @{ + */ + +#define SMSC9218I_PHY_SPMODES 0x00000012U + +/** @} */ + +/** + * @name Special Control and Status Indications + * @{ + */ + +#define SMSC9218I_PHY_CSIR 0x0000001bU +#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U +#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U +#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U + +/** @} */ + +/** + * @name Interrupt Source Flag + * @{ + */ + +#define SMSC9218I_PHY_ISR 0x0000001dU +#define SMSC9218I_PHY_ISR_INT7 0x00000080U +#define SMSC9218I_PHY_ISR_INT6 0x00000040U +#define SMSC9218I_PHY_ISR_INT5 0x00000020U +#define SMSC9218I_PHY_ISR_INT4 0x00000010U +#define SMSC9218I_PHY_ISR_INT3 0x00000008U +#define SMSC9218I_PHY_ISR_INT2 0x00000004U +#define SMSC9218I_PHY_ISR_INT1 0x00000002U + +/** @} */ + +/** + * @name Interrupt Mask + * @{ + */ + +#define SMSC9218I_PHY_IMR 0x0000001eU +#define SMSC9218I_PHY_IMR_INT7 0x00000080U +#define SMSC9218I_PHY_IMR_INT6 0x00000040U +#define SMSC9218I_PHY_IMR_INT5 0x00000020U +#define SMSC9218I_PHY_IMR_INT4 0x00000010U +#define SMSC9218I_PHY_IMR_INT3 0x00000008U +#define SMSC9218I_PHY_IMR_INT2 0x00000004U +#define SMSC9218I_PHY_IMR_INT1 0x00000002U + +/** @} */ + +/** + * @name PHY Special Control and Status + * @{ + */ + +#define SMSC9218I_PHY_PHYSCSR 0x0000001fU +#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U +#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U +#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU +#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U +#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U +#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U +#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U + +/** @} */ diff --git a/bsps/powerpc/mpc55xxevb/include/tm27.h b/bsps/powerpc/mpc55xxevb/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/mpc55xxevb/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/mpc8260ads/headers.am b/bsps/powerpc/mpc8260ads/headers.am new file mode 100644 index 0000000000..10c6e42313 --- /dev/null +++ b/bsps/powerpc/mpc8260ads/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mpc8260ads/include/bsp/irq.h diff --git a/bsps/powerpc/mpc8260ads/include/bsp.h b/bsps/powerpc/mpc8260ads/include/bsp.h new file mode 100644 index 0000000000..c207a2ec99 --- /dev/null +++ b/bsps/powerpc/mpc8260ads/include/bsp.h @@ -0,0 +1,86 @@ +/* + * This include file contains all board IO definitions. + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_MPC8260ADS_BSP_H +#define LIBBSP_POWERPC_MPC8260ADS_BSP_H + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <mpc8260.h> +#include <mpc8260/cpm.h> +#include <mpc8260/mmu.h> +#include <mpc8260/console.h> +#include <bsp/irq.h> +#include <bsp/vectors.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Board configuration registers + */ + +typedef struct bcsr + +{ + uint32_t bcsr0; /* Board Control and Status Register */ + uint32_t bcsr1; + uint32_t bcsr2; + uint32_t bcsr3; + +} BCSR; + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; +extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach + +/* miscellaneous stuff assumed to exist */ + +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +/* +#define NOCACHE_MEM_SIZE 512*1024 +*/ + +/* functions */ + +#if 0 +void M8260ExecuteRISC( uint32_t command ); +void *M8260AllocateBufferDescriptors( int count ); +void *M8260AllocateRiscTimers( int count ); +extern char M8260DefaultWatchdogFeeder; +#endif + +/* + * Prototypes for items shared across file boundaries in the BSP + */ +extern uint32_t bsp_serial_per_sec; +void *bsp_idle_thread( uintptr_t ignored ); +void cpu_init(void); +int mbx8xx_console_get_configuration(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/mpc8260ads/include/bsp/irq.h b/bsps/powerpc/mpc8260ads/include/bsp/irq.h new file mode 100644 index 0000000000..1dd18611fc --- /dev/null +++ b/bsps/powerpc/mpc8260ads/include/bsp/irq.h @@ -0,0 +1,193 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> + * Surrey Satellite Technology Limited + * The interrupt handling on the mpc8260 seems quite different from + * the 860 (I don't know the 860 well). Although some interrupts + * are routed via the CPM irq and some are direct to the SIU they all + * appear logically the same. Therefore I removed the distinction + * between SIU and CPM interrupts. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H +#include <rtems/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* +extern volatile unsigned int ppc_cached_irq_mask; +*/ + +/* + * Symblolic IRQ names and related definitions. + */ + + /* + * CPM IRQ handlers related definitions + * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#define BSP_CPM_IRQ_NUMBER (64) +#define BSP_CPM_IRQ_LOWEST_OFFSET (0) +#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1) + /* + * PowerPc exceptions handled as interrupt where a rtems managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET) + + /* + * Some SIU IRQ symbolic name definition. Please note that + * INT IRQ are defined but a single one will be used to + * redirect all CPM interrupt. + * + * On the mpc8260 all this seems to be transparent. Although the + * CPM, PIT and TMCNT interrupt may well be the only interrupts routed + * to the SIU at the hardware level all of them appear as CPM interupts + * to software apart from the registers for setting priority. + * + * The MPC8260 User Manual seems shot through with inconsistencies + * about this whole area. + */ + + /* + * Some CPM IRQ symbolic name definition + */ +#define BSP_CPM_IRQ_ERROR (BSP_CPM_IRQ_LOWEST_OFFSET + 0) +#define BSP_CPM_IRQ_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 1) +#define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 2) +#define BSP_CPM_IRQ_RISC_TIMERS (BSP_CPM_IRQ_LOWEST_OFFSET + 3) +#define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4) +#define BSP_CPM_IRQ_SMC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 5) +#define BSP_CPM_IRQ_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 6) +#define BSP_CPM_IRQ_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 7) +#define BSP_CPM_IRQ_IDMA3 (BSP_CPM_IRQ_LOWEST_OFFSET + 8) +#define BSP_CPM_IRQ_IDMA4 (BSP_CPM_IRQ_LOWEST_OFFSET + 9) +#define BSP_CPM_IRQ_SDMA (BSP_CPM_IRQ_LOWEST_OFFSET + 10) + +#define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 12) +#define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 13) +#define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 14) +#define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 15) +#define BSP_CPM_IRQ_TMCNT (BSP_CPM_IRQ_LOWEST_OFFSET + 16) +#define BSP_CPM_IRQ_PIT (BSP_CPM_IRQ_LOWEST_OFFSET + 17) + +#define BSP_CPM_IRQ_IRQ1 (BSP_CPM_IRQ_LOWEST_OFFSET + 19) +#define BSP_CPM_IRQ_IRQ2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20) +#define BSP_CPM_IRQ_IRQ3 (BSP_CPM_IRQ_LOWEST_OFFSET + 21) +#define BSP_CPM_IRQ_IRQ4 (BSP_CPM_IRQ_LOWEST_OFFSET + 22) +#define BSP_CPM_IRQ_IRQ5 (BSP_CPM_IRQ_LOWEST_OFFSET + 23) +#define BSP_CPM_IRQ_IRQ6 (BSP_CPM_IRQ_LOWEST_OFFSET + 24) +#define BSP_CPM_IRQ_IRQ7 (BSP_CPM_IRQ_LOWEST_OFFSET + 25) + +#define BSP_CPM_IRQ_FCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 32) +#define BSP_CPM_IRQ_FCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 33) +#define BSP_CPM_IRQ_FCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 34) +#define BSP_CPM_IRQ_MCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 36) +#define BSP_CPM_IRQ_MCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 37) + +#define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 40) +#define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 41) +#define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 42) +#define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 43) + +#define BSP_CPM_IRQ_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 48) +#define BSP_CPM_IRQ_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 49) +#define BSP_CPM_IRQ_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 50) +#define BSP_CPM_IRQ_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 51) +#define BSP_CPM_IRQ_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 52) +#define BSP_CPM_IRQ_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 53) +#define BSP_CPM_IRQ_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 54) +#define BSP_CPM_IRQ_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 55) +#define BSP_CPM_IRQ_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 56) +#define BSP_CPM_IRQ_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 57) +#define BSP_CPM_IRQ_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 58) +#define BSP_CPM_IRQ_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 59) +#define BSP_CPM_IRQ_PC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 60) +#define BSP_CPM_IRQ_PC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 61) +#define BSP_CPM_IRQ_PC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 62) +#define BSP_CPM_IRQ_PC0 (BSP_CPM_IRQ_LOWEST_OFFSET + 63) + + /* + * Some Processor exception handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) +#define BSP_PERIODIC_TIMER (BSP_DECREMENTER) + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +#define CPM_INTERRUPT + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ +/* + * ------------------------ PPC CPM Mngt Routines ------- + */ + +/* + * function to disable a particular irq. After calling + * this function, even if the device asserts the interrupt line it will + * not be propagated further to the processor + */ +int BSP_irq_disable_at_cpm (const rtems_irq_number irqLine); +/* + * function to enable a particular irq. After calling + * this function, if the device asserts the interrupt line it will + * be propagated further to the processor + */ +int BSP_irq_enable_at_cpm (const rtems_irq_number irqLine); +/* + * function to acknoledge a particular irq. After calling + * this function, if a device asserts an enabled interrupt line it will + * be propagated further to the processor. Mainly usefull for people + * writting raw handlers as this is automagically done for rtems managed + * handlers. + */ +int BSP_irq_ack_at_cpm (const rtems_irq_number irqLine); +/* + * function to check if a particular irq is enabled. After calling + */ +int BSP_irq_enabled_at_cpm (const rtems_irq_number irqLine); + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + +/* Now that we have defined some basics, include the generic support */ +#include <bsp/irq-generic.h> + +#endif + +#endif diff --git a/bsps/powerpc/mpc8260ads/include/tm27.h b/bsps/powerpc/mpc8260ads/include/tm27.h new file mode 100644 index 0000000000..b1eafc47aa --- /dev/null +++ b/bsps/powerpc/mpc8260ads/include/tm27.h @@ -0,0 +1,46 @@ +/* + * @file + * @ingroup powerpc_mpc8260ads + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <rtems/powerpc/powerpc.h> + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) \ + do { \ + static rtems_irq_connect_data scIrqData = { \ + PPC_IRQ_SCALL, \ + (rtems_irq_hdl) handler, \ + NULL, \ + NULL, \ + NULL \ + }; \ + BSP_install_rtems_irq_handler (&scIrqData); \ + } while(0) + +#define Cause_tm27_intr() __asm__ volatile ("sc") + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/bsps/powerpc/mvme3100/headers.am b/bsps/powerpc/mvme3100/headers.am new file mode 100644 index 0000000000..3a242350e6 --- /dev/null +++ b/bsps/powerpc/mvme3100/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h diff --git a/bsps/powerpc/mvme3100/include/bsp.h b/bsps/powerpc/mvme3100/include/bsp.h new file mode 100644 index 0000000000..3fbfcb3120 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp.h @@ -0,0 +1,343 @@ +/** + * @file + * + * @ingroup mvme3100_bsp + * + * @brief This file contains BSP API definition. + */ + +/* + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Adapted for the mvme3100 BSP by T. Straumann, 2007. + */ +#ifndef LIBBSP_POWERPC_MVME3100_BSP_H +#define LIBBSP_POWERPC_MVME3100_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <libcpu/io.h> +#include <bsp/vectors.h> + +/** + * @defgroup mvme3100_bsp confdefs.h overrides + * + * @ingroup powerpc_mvme3100 + * + * @brief confdefs.h overrides for this BSP: + */ + +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +/* + * diagram illustrating the role of the configuration + * constants + * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible + * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this + * address being 'visible' or not!). + * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME + * _VME_A32_WIN0_ON_VME: VME address of that same window + * + * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between + * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI + * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to + * the base address read from PCI config.space in order to translate that + * into a CPU address. + * + * NOTE: VME addresses should NEVER be translated using these constants! + * they are strictly for BSP internal use. Drivers etc. should use + * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). + * + * CPU ADDR PCI_ADDR VME ADDR + * + * 00000000 XXXXXXXX XXXXXXXX + * ^ ^ ........ + * | | + * | | e.g., RAM XXXXXXXX + * | | 00000000 + * | | ......... ^ + * | | (possible offset | + * | | between pci and XXXXXXXX | ...... + * | | cpu addresses) | + * | v | + * | PCI_MEM_BASE -------------> 00000000 --------------- | + * | ........ ........ ^ | + * | invisible | | + * | ........ from CPU | | + * v | | + * PCI_MEM_WIN0 ============= first visible PCI addr | | + * | | + * pci devices pci window | | + * visible here v v + * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME + * vme window + * VME devices hostbridge mapped by + * visible here universe + * ===================================================== + * + */ + +/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ +#define _IO_BASE 0xe0000000 /* Motload's PCI IO base */ +#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET +/* offset of pci memory as seen from the CPU */ +#define PCI_MEM_BASE 0 +/* where (in CPU addr. space) does the PCI window start */ +#define PCI_MEM_WIN0 0x80000000 + +/* + * Base address definitions for several devices + */ + +#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 +#define BSP_OPEN_PIC_BIG_ENDIAN + +#define BSP_8540_CCSR_BASE (0xe1000000) + +#define BSP_UART_IOBASE_COM1 (BSP_8540_CCSR_BASE+0x4500) +#define BSP_UART_IOBASE_COM2 (BSP_8540_CCSR_BASE+0x4600) +#define PCI_CONFIG_ADDR (BSP_8540_CCSR_BASE+0x8000) +#define PCI_CONFIG_DATA (BSP_8540_CCSR_BASE+0x8004) +#define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val)) + +#define BSP_CONSOLE_PORT BSP_UART_COM1 +#define BSP_UART_BAUD_BASE (-9600) /* use existing divisor to determine clock rate */ +#define BSP_UART_USE_SHARED_IRQS + +#define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) + +/* I2C Devices */ +/* Note that the i2c addresses stated in the manual are + * left-shifted by one bit. + */ +#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ +#define BSP_USR0_I2C_ADDR (0xA4>>1) /* the 1st user EEPROM */ +#define BSP_USR1_I2C_ADDR (0xA6>>1) /* the 2nd user EEPROM */ +#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ +#define BSP_RTC_I2C_ADDR (0xD0>>1) /* the DS1375 wall-clock */ + +#define BSP_I2C_BUS_DESCRIPTOR mpc8540_i2c_bus_descriptor + +#define BSP_I2C_BUS0_NAME "/dev/i2c0" + +#define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" +#define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" +#define BSP_I2C_USR1_EEPROM_NAME "usr1-eeprom" +#define BSP_I2C_DS1621_NAME "ds1621" +#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME +#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" +#define BSP_I2C_DS1375_RAW_NAME "ds1375-raw" +#define BSP_I2C_RTC_RAW_NAME BSP_I2C_DS1375_RAW_NAME + +#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) +#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) +#define BSP_I2C_USR1_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR1_EEPROM_NAME) +#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) +#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME +#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) +#define BSP_I2C_DS1375_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1375_RAW_NAME) + +/* Definitions useful for bootloader (netboot); where to find + * boot/'environment' parameters. + */ +#define BSP_EEPROM_BOOTPARMS_NAME BSP_I2C_USR1_EEPROM_DEV_NAME +#define BSP_EEPROM_BOOTPARMS_SIZE 1024 +#define BSP_EEPROM_BOOTPARMS_OFFSET 0 +#define BSP_BOOTPARMS_WRITE_ENABLE() do { BSP_eeprom_write_enable(); } while (0) +#define BSP_BOOTPARMS_WRITE_DISABLE() do { BSP_eeprom_write_protect();} while (0) + + +#ifdef __cplusplus +extern "C" { +#endif +/* Initialize the I2C driver and register all devices + * RETURNS 0 on success, -1 on error. + * + * Access to the VPD and user EEPROMS as well + * as the ds1621 temperature sensor is possible + * by means of file nodes + * + * /dev/i2c0.vpd-eeprom (read-only) + * /dev/i2c0.usr-eeprom (read-write) + * /dev/i2c0.usr1-eeprom (read-write) + * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) + * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) + * /dev/i2c0.ds1375-raw (read-write; transfer bytes to/from the ds1375) + * + */ +int BSP_i2c_initialize(void); +#define BSP_PREDRIVER_I2C_INIT + +/* System Control Register */ +#define BSP_MVME3100_SYS_CR ((volatile uint8_t *)0xe2000001) +#define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5) +#define BSP_MVME3100_SYS_CR_RESET (5<<5) +#define BSP_MVME3100_SYS_CR_EEPROM_WP (1<<1) +#define BSP_MVME3100_SYS_CR_TSTAT_MSK (1<<0) + +/* LED support */ +#define BSP_MVME3100_SYS_IND_REG ((volatile uint8_t *)0xe2000002) +#define BSP_LED_BRD_FAIL (1<<0) +#define BSP_LED_USR1 (1<<1) +#define BSP_LED_USR2 (1<<2) +#define BSP_LED_USR3 (1<<3) + +/* Flash CSR */ +#define BSP_MVME3100_FLASH_CSR ((volatile uint8_t *)0xe2000003) +#define BSP_MVME3100_FLASH_CSR_FLASH_RDY (1<<0) +#define BSP_MVME3100_FLASH_CSR_FBT_BLK_SEL (1<<1) +#define BSP_MVME3100_FLASH_CSR_F_WP_HW (1<<2) +#define BSP_MVME3100_FLASH_CSR_F_WP_SW (1<<3) +#define BSP_MVME3100_FLASH_CSR_MAP_SEL (1<<4) + +/* Phy interrupt detect */ +#define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) + +/* Atomically set bits in a sys-register; The bits set in 'mask' + * are set in the register others; are left unmodified. + * + * RETURNS: old state. + * + * NOTE : since BSP_setSysReg( reg, 0 ) does not make + * any changes this call may be used + * to read the current status w/o modifying it. + */ +uint8_t BSP_setSysReg(volatile uint8_t *r, uint8_t mask); + +/* Atomically clear bits in a sys-register; The bits set in 'mask' + * are cleared in the register; others are left unmodified. + * + * RETURNS: old state. + * + * NOTE : since BSP_clrSysReg( reg, 0 ) does not make + * any changes this call may be used + * to read the current status w/o modifying it. + */ + +uint8_t BSP_clrSysReg(volatile uint8_t *r, uint8_t mask); + +/* Convenience wrappers around BSP_setSysReg()/BSP_clrSysReg() */ + +/* Set write-protection for all EEPROM devices + * RETURNS: old status + */ +uint8_t BSP_eeprom_write_protect(void); + +/* Disengage write-protection for all EEPROM devices + * RETURNS: old status + */ +uint8_t BSP_eeprom_write_enable(void); + +/* Set LEDs that have their bit set in the mask + * + * RETURNS: old status. + * + * NOTE : since BSP_setLEDs( 0 ) does not make + * any changes this call may be used + * to read the current status w/o modifying it. + */ +uint8_t BSP_setLEDs(uint8_t mask); + +/* Clear LEDs that have their bit set in the mask + * + * RETURNS: old status + * + * NOTE: : see above (BSP_setLEDs) + */ +uint8_t BSP_clrLEDs(uint8_t mask); + +#if 0 +#define outport_byte(port,value) outb(value,port) +#define outport_word(port,value) outw(value,port) +#define outport_long(port,value) outl(value,port) + +#define inport_byte(port,value) (value = inb(port)) +#define inport_word(port,value) (value = inw(port)) +#define inport_long(port,value) (value = inl(port)) +#endif + +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; +/* + * The commandline as passed from the bootloader. + */ +extern char *BSP_commandline_string; + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +extern rtems_configuration_table BSP_Configuration; +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern int BSP_disconnect_clock_handler (void); +extern int BSP_connect_clock_handler (void); + +/* clear hostbridge errors + * + * NOTE: The routine returns always (-1) if 'enableMCP==1' + * [semantics needed by libbspExt] if the MCP input is not wired. + * It returns and clears the error bits of the PCI status register. + * MCP support is disabled because: + * a) the 2100 has no raven chip + * b) the raven (2300) would raise machine check interrupts + * on PCI config space access to empty slots. + */ +extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); +extern void BSP_motload_pci_fixup(void); + +struct rtems_bsdnet_ifconfig; + +int +rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "tse1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsec_attach + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +extern void BSP_vme_config(void); +extern void BSP_pciConfigDump_early( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/VMEConfig.h b/bsps/powerpc/mvme3100/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..10b424c2a8 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/VMEConfig.h @@ -0,0 +1,132 @@ +/** + * @file + * + * @ingroup powerpc_vmeconfig + * + * @brief mvme3100 BSP specific address space configuration parameters + */ + +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2002..2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +/* + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout: + */ + +#define _VME_A32_WIN0_ON_PCI 0xc0000000 +#define _VME_CSR_ON_PCI 0xce000000 +#define _VME_A24_ON_PCI 0xcf000000 +#define _VME_A16_ON_PCI 0xcfff0000 + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a run-time configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map the board RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0xc0000000 + +/* If your BSP requires a non-standard way to configure + * the VME interrupt manager then define the symbol + * + * BSP_VME_INSTALL_IRQ_MGR + * + * to a proper instruction sequence that installs the + * universe interrupt manager. This requires knowledge + * of the wiring between the universe and the PIC (main + * interrupt controller), i.e., which IRQ 'pins' of the + * universe are wired to which 'lines'/inputs at the PIC. + * (consult vmeUniverse.h for more information). + * + * When installing the universe IRQ manager it is also + * possible to specify whether it should try to share + * PIC interrupts with other sources. This might not + * be supported by all BSPs (but the unverse driver + * recognizes that). + * + * If BSP_VME_INSTALL_IRQ_MGR is undefined then + * the default algorithm is used (vme_universe.c): + * + * This default setup uses only a single wire. It reads + * the PIC 'line' from PCI configuration space and assumes + * this to be wired to the first (LIRQ0) IRQ input at the + * universe. The default setup tries to use interrupt + * sharing. + */ + +extern int BSP_VMEInit(void); +extern int BSP_VMEIrqMgrInstall(void); + +/** + * @defgroup powerpc_vme BSP_VME_INSTALL_IRQ_MGR Support + * + * @ingroup powerpc_mvme3100 + * + * @brief BSP_VME_INSTALL_IRQ_MGR Support Package + */ +#define BSP_VME_INSTALL_IRQ_MGR(err) \ + do { \ + err = vmeTsi148InstallIrqMgrAlt(\ + VMETSI148_IRQ_MGR_FLAG_SHARED, /* use shared IRQs */ \ + 0, BSP_VME0_IRQ, \ + 1, BSP_VME1_IRQ, \ + 2, BSP_VME2_IRQ, \ + 3, BSP_VME3_IRQ, \ + -1 /* terminate list */ \ + ); \ + } while (0) + +/* This BSP uses the Tsi148 Driver */ +#define _VME_DRIVER_TSI148 + +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h b/bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h new file mode 100644 index 0000000000..7eb0358eae --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/if_tsec_pub.h @@ -0,0 +1,475 @@ +/** + * @file + * + * @ingroup powerpc_iftsecpub + * + * @brief IF_TSEC_PUB Support + */ + +#ifndef IF_TSEC_PUBLIC_INTERFACE_H +#define IF_TSEC_PUBLIC_INTERFACE_H + +/* + * Authorship + * ---------- + * This software ('mvme3100' RTEMS BSP) was created by + * + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'mvme3100' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <rtems.h> +#include <stdio.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Opaque driver handle */ +struct tsec_private; + +/********** Low-level Driver API ****************/ + +/** + * @defgroup powerpc_iftsecpub Low-level Driver API + * + * @ingroup powerpc_mvme3100 + * + * @brief This API provides driver access to applications that + * want to use e.g., the second ethernet interface + * independently from the BSD TCP/IP stack. E.g., for + * raw ethernet packet communication... + */ + +#define TSEC_TXIRQ ( (1<<(31-9)) | (1<<(31-11)) ) +#define TSEC_RXIRQ ( (1<<(31-0)) | (1<<(31- 3)) | (1<<(31-24)) ) +#define TSEC_LKIRQ ( 1<<(31- 4) ) +/* + * Setup an interface. + * Allocates resources for descriptor rings and sets up the driver software structure. + * + * Arguments: + * unit: + * interface # (1..2). The interface must not be attached to BSD already. + * + * driver_tid: + * ISR posts RTEMS event # ('unit' - 1) to task with ID 'driver_tid' and disables interrupts + * from this interface. + * + * void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred): + * Pointer to user-supplied callback to release a buffer that had been sent + * by BSP_tsec_send_buf() earlier. The callback is passed 'cleanup_txbuf_arg' + * and a flag indicating whether the send had been successful. + * The driver no longer accesses 'user_buf' after invoking this callback. + * CONTEXT: This callback is executed either by BSP_tsec_swipe_tx() or + * BSP_tsec_send_buf(), BSP_tsec_init_hw(), BSP_tsec_stop_hw() (the latter + * ones calling BSP_tsec_swipe_tx()). + * void *cleanup_txbuf_arg: + * Closure argument that is passed on to 'cleanup_txbuf()' callback; + * + * void *(*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + * Pointer to user-supplied callback to allocate a buffer for subsequent + * insertion into the RX ring by the driver. + * RETURNS: opaque handle to the buffer (which may be a more complex object + * such as an 'mbuf'). The handle is not used by the driver directly + * but passed back to the 'consume_rxbuf()' callback. + * Size of the available data area and pointer to buffer's data area + * in '*psize' and '*p_data_area', respectively. + * If no buffer is available, this routine should return NULL in which + * case the driver drops the last packet and re-uses the last buffer + * instead of handing it out to 'consume_rxbuf()'. + * CONTEXT: Called when initializing the RX ring (BSP_tsec_init_hw()) or when + * swiping it (BSP_tsec_swipe_rx()). + * + * + * void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len); + * Pointer to user-supplied callback to pass a received buffer back to + * the user. The driver no longer accesses the buffer after invoking this + * callback (with 'len'>0, see below). 'user_buf' is the buffer handle + * previously generated by 'alloc_rxbuf()'. + * The callback is passed 'cleanup_rxbuf_arg' and a 'len' + * argument giving the number of bytes that were received. + * 'len' may be <=0 in which case the 'user_buf' argument is NULL. + * 'len' == 0 means that the last 'alloc_rxbuf()' had failed, + * 'len' < 0 indicates a receiver error. In both cases, the last packet + * was dropped/missed and the last buffer will be re-used by the driver. + * NOTE: the data are 'prefixed' with two bytes, i.e., the ethernet packet header + * is stored at offset 2 in the buffer's data area. Also, the FCS (4 bytes) + * is appended. 'len' accounts for both. + * CONTEXT: Called from BSP_tsec_swipe_rx(). + * void *cleanup_rxbuf_arg: + * Closure argument that is passed on to 'consume_rxbuf()' callback; + * + * rx_ring_size, tx_ring_size: + * How many big to make the RX and TX descriptor rings. Note that the sizes + * may be 0 in which case a reasonable default will be used. + * If either ring size is < 0 then the RX or TX will be disabled. + * Note that it is illegal in this case to use BSP_tsec_swipe_rx() or + * BSP_tsec_swipe_tx(), respectively. + * + * irq_mask: + * Interrupts to enable. OR of flags from above. + * + */ +struct tsec_private * +BSP_tsec_setup( + int unit, + rtems_id driver_tid, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void * cleanup_txbuf_arg, + void * (*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void * consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + +/* + * Alternate 'setup' routine allowing the user to install an ISR rather + * than a task ID. + * All parameters (other than 'isr' / 'isr_arg') and the return value + * are identical to the BSP_tsec_setup() entry point. + */ +struct tsec_private * +BSP_tsec_setup_1( + int unit, + void (*isr)(void *isr_arg), + void * isr_arg, + void (*cleanup_txbuf)(void *user_buf, void *cleanup_txbuf_arg, int error_on_tx_occurred), + void * cleanup_txbuf_arg, + void * (*alloc_rxbuf)(int *p_size, uintptr_t *p_data_addr), + void (*consume_rxbuf)(void *user_buf, void *consume_rxbuf_arg, int len), + void * consume_rxbuf_arg, + int rx_ring_size, + int tx_ring_size, + int irq_mask +); + + +/* + * Descriptor scavenger; cleanup the TX ring, passing all buffers + * that have been sent to the cleanup_tx() callback. + * This routine is called from BSP_tsec_send_buf(), BSP_tsec_init_hw(), + * BSP_tsec_stop_hw(). + * + * RETURNS: number of buffers processed. + */ + +int +BSP_tsec_swipe_tx(struct tsec_private *mp); + + +/* + * Reset statistics counters. + */ +void +BSP_tsec_reset_stats(struct tsec_private *mp); + +/* + * Initialize interface hardware + * + * 'mp' handle obtained by from BSP_tsec_setup(). + * 'promisc' whether to set promiscuous flag. + * 'enaddr' pointer to six bytes with MAC address. Read + * from the device if NULL. + * NOTE: multicast filter is cleared by this routine. + */ +void +BSP_tsec_init_hw(struct tsec_private *mp, int promisc, unsigned char *enaddr); + +/* + * Clear multicast hash filter. No multicast frames are accepted + * after executing this routine (unless the hardware was initialized + * in 'promiscuous' mode). + * + * Reset reference count for all hash-table entries + * to zero (see BSP_tsec_mcast_filter_accept_del()). + */ +void +BSP_tsec_mcast_filter_clear(struct tsec_private *mp); + +/* + * Program multicast filter to accept all multicast frames. + * + * Increment reference count for all hash-table entries + * by one (see BSP_tsec_mcast_filter_accept_del()). + */ +void +BSP_tsec_mcast_filter_accept_all(struct tsec_private *mp); + +/* + * Add a MAC address to the multicast filter and increment + * the reference count for the matching hash-table entry + * (see BSP_tsec_mcast_filter_accept_del()). + * + * Existing entries are not changed but note that + * the filter is imperfect, i.e., multiple MAC addresses + * may alias to a single filter entry. Hence software + * filtering must still be performed. + * + */ +void +BSP_tsec_mcast_filter_accept_add(struct tsec_private *mp, unsigned char *enaddr); + +/* + * Remove a MAC address from the (imperfec) multicast + * filter. + * Note that the driver maintains an internal reference + * counter for each multicast hash. The hash-table + * entry is only cleared when the reference count + * reaches zero ('del' has been called the same + * amount of times as 'add' for an address (or + * any alias) that matches a given table entry. + * BSP_tsec_mcast_filter_clear() resets all reference + * counters to zero. + */ +void +BSP_tsec_mcast_filter_accept_del(struct tsec_private *mp, unsigned char *enaddr); + +/* + * Dump statistics to FILE 'f'. If NULL, stdout is used. + */ +void +BSP_tsec_dump_stats(struct tsec_private *mp, FILE *f); + +/* + * Shutdown hardware and clean out the rings + */ +void +BSP_tsec_stop_hw(struct tsec_private *mp); + +/* + * calls BSP_tsec_stop_hw(), releases all resources and marks the interface + * as unused. + * RETURNS 0 on success, nonzero on failure. + * NOTE: the handle MUST NOT be used after successful execution of this + * routine. + */ +int +BSP_tsec_detach(struct tsec_private *mp); + +/* + * Enqueue a mbuf chain or a raw data buffer for transmission; + * RETURN: #bytes sent or -1 if there are not enough free descriptors + * + * If 'len' is <=0 then 'm_head' is assumed to point to a mbuf chain. + * OTOH, a raw data packet (or a different type of buffer) + * may be sent (non-BSD driver) by pointing data_p to the start of + * the data and passing 'len' > 0. + * 'm_head' is passed back to the 'cleanup_txbuf()' callback. + * + * Comments: software cache-flushing incurs a penalty if the + * packet cannot be queued since it is flushed anyways. + * The algorithm is slightly more efficient in the normal + * case, though. + * + * RETURNS: # bytes enqueued to device for transmission or -1 if no + * space in the TX ring was available. + */ + +int +BSP_tsec_send_buf(struct tsec_private *mp, void *m_head, void *data_p, int len); + +/* + * Retrieve all received buffers from the RX ring, replacing them + * by fresh ones (obtained from the alloc_rxbuf() callback). The + * received buffers are passed to consume_rxbuf(). + * + * RETURNS: number of buffers processed. + */ +int +BSP_tsec_swipe_rx(struct tsec_private *mp); + +/* read ethernet address from hw to buffer */ +void +BSP_tsec_read_eaddr(struct tsec_private *mp, unsigned char *eaddr); + +/* Read MII register */ +uint32_t +BSP_tsec_mdio_rd(struct tsec_private *mp, unsigned reg); + +/* Write MII register */ +int +BSP_tsec_mdio_wr(struct tsec_private *mp, unsigned reg, uint32_t val); + +/* + * read/write media word. + * 'cmd': can be SIOCGIFMEDIA, SIOCSIFMEDIA, 0 or 1. The latter + * are aliased to the former for convenience. + * 'parg': pointer to media word. + * + * RETURNS: 0 on success, nonzero on error + */ +int +BSP_tsec_media_ioctl(struct tsec_private *mp, int cmd, int *parg); + +/* Interrupt related routines */ + +/* + * When it comes to interrupts the chip has two rather + * annoying features: + * 1 once an IRQ is pending, clearing the IMASK does not + * de-assert the interrupt line. + * 2 the chip has three physical interrupt lines even though + * all events are reported in a single register. Rather + * useless; we must hook 3 ISRs w/o any real benefit. + * In fact, it makes our life a bit more difficult: + * + * Hence, for (1) we would have to mask interrupts at the PIC + * but to re-enable them we would have to do that three times + * because of (2). + * + * Therefore, we take the following approach: + * + * ISR masks all interrupts on the TSEC, acks/clears them + * and stores the acked irqs in the device struct where + * it is picked up by BSP_tsec_ack_irqs(). + * Since all interrupts are disabled until the daemon + * re-enables them after calling BSP_tsec_ack_irqs() + * no interrupts are lost. + * + * BUT: NO isr (including PHY isrs) MUST INTERRUPT ANY + * OTHER ONE, i.e., they all must have the same + * priority. Otherwise, integrity of the cached + * irq_pending variable may be compromised. + */ + +/* Note: the BSP_tsec_enable/disable/ack_irqs() entry points + * are deprecated. + * The newer API where the user passes a mask allows + * for more selective control. + */ + +/* Enable interrupts at device */ +void +BSP_tsec_enable_irqs(struct tsec_private *mp); + +/* Disable interrupts at device */ +void +BSP_tsec_disable_irqs(struct tsec_private *mp); + +/* + * Acknowledge (and clear) interrupts. + * RETURNS: interrupts that were raised. + */ +uint32_t +BSP_tsec_ack_irqs(struct tsec_private *mp); + +/* Enable interrupts included in 'mask' (leaving + * already enabled interrupts on). If the mask includes + * bits that were not passed to the 'setup' routine then + * the behavior is undefined. + */ +void +BSP_tsec_enable_irq_mask(struct tsec_private *mp, uint32_t irq_mask); + +/* Disable interrupts included in 'mask' (leaving + * other ones that are currently enabled on). If the mask + * includes bits that were not passed to the 'setup' routine + * then the behavior is undefined. + + * RETURNS: Bitmask of interrupts that were enabled upon entry + * into this routine. This can be used to restore the previous + * state. + */ +uint32_t +BSP_tsec_disable_irq_mask(struct tsec_private *mp, uint32_t irq_mask); + +/* Acknowledge and clear selected interrupts. + * + * RETURNS: All pending interrupts. + * + * NOTE: Only pending interrupts contained in 'mask' + * are cleared. Others are left pending. + * + * This routine can be used to check for pending + * interrupts (pass mask == 0) or to clear all + * interrupts (pass mask == -1). + */ +uint32_t +BSP_tsec_ack_irq_mask(struct tsec_private *mp, uint32_t mask); + + +/* Retrieve the driver daemon TID that was passed to + * BSP_tsec_setup(). + */ + +rtems_id +BSP_tsec_get_tid(struct tsec_private *mp); + +struct tsec_private * +BSP_tsec_getp(unsigned index); + +/* + * + * Example driver task loop (note: no synchronization of + * buffer access shown!). + * RTEMS_EVENTx = 0,1 or 2 depending on IF unit. + * + * / * setup (obtain handle) and initialize hw here * / + * + * do { + * / * ISR disables IRQs and posts event * / + * rtems_event_receive( RTEMS_EVENTx, RTEMS_WAIT | RTEMS_EVENT_ANY, RTEMS_NO_TIMEOUT, &evs ); + * irqs = BSP_tsec_ack_irqs(handle); + * if ( irqs & BSP_TSEC_IRQ_TX ) { + * BSP_tsec_swipe_tx(handle); / * cleanup_txbuf() callback executed * / + * } + * if ( irqs & BSP_TSEC_IRQ_RX ) { + * BSP_tsec_swipe_rx(handle); / * alloc_rxbuf() and consume_rxbuf() executed * / + * } + * BSP_tsec_enable_irqs(handle); + * } while (1); + * + */ + +/* PUBLIC RTEMS BSDNET ATTACH FUNCTION */ +struct rtems_bsdnet_ifconfig; + +int +rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/irq.h b/bsps/powerpc/mvme3100/include/bsp/irq.h new file mode 100644 index 0000000000..0158e05149 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/irq.h @@ -0,0 +1,137 @@ +/** + * @file + * + * @ingroup powerpc_irq + * + * @brief This include file describe the data structure and the functions + * implemented by RTEMS to write interrupt handlers. + */ + +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by RTEMS to write interrupt handlers. + * + * Copyright (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Adapted for the mvme3100 BSP by T. Straumann, 2007. + */ + +#ifndef BSP_POWERPC_IRQ_H +#define BSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include <rtems/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup powerpc_irq Definitions + * + * @ingroup powerpc_mvme3100 + * + * @brief rtems_irq_number Definitions + */ + +/* Must pad number of external sources to 16 because + * of the layout of vector/priority registers in the + * 8540's openpic where there is a gap between + * registers corresponding to external and core sources. + */ +#define BSP_EXT_IRQ_NUMBER (16) +#define BSP_CORE_IRQ_NUMBER (32) + +/* openpic glue code from shared/irq assigns priorities and configures + * initial ISRs for BSP_PCI_IRQ_NUMBER entries (plus ISA stuff on legacy + * boards). Hence PCI_IRQ_NUMBER must also cover the internal sources + * even though they have nothing to do with PCI. + */ +#define BSP_PCI_IRQ_NUMBER (BSP_EXT_IRQ_NUMBER + BSP_CORE_IRQ_NUMBER) +#define BSP_PCI_IRQ_LOWEST_OFFSET (0) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_CORE_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_EXT_IRQ_NUMBER) +#define BSP_CORE_IRQ_MAX_OFFSET (BSP_CORE_IRQ_LOWEST_OFFSET + BSP_CORE_IRQ_NUMBER - 1) + +/* + * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CORE_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) +/* Misc vectors for OPENPIC irqs (IPI, timers) + */ +#define BSP_MISC_IRQ_NUMBER (8) +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) + +/* + * Some PCI IRQ symbolic name definition + */ +#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) + +#define BSP_VME0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 0) +#define BSP_VME1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) +#define BSP_VME2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) +#define BSP_VME3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) + +#define BSP_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) +#define BSP_TEMP_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) +#define BSP_PHY_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) +#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 11) + +/* Weird - they provide 3 different IRQ lines per ethernet controller + * but only one shared line for 2 UARTs ??? + */ +#define BSP_UART_COM1_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26) +#define BSP_UART_COM2_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26) +#define BSP_I2C_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 27) + +/* + * Some internal (CORE) name definitions + */ +/* Ethernet (FEC) */ +#define BSP_CORE_IRQ_FEC (BSP_CORE_IRQ_LOWEST_OFFSET + 25) +/* i2c controller */ +#define BSP_CORE_IRQ_I2C (BSP_CORE_IRQ_LOWEST_OFFSET + 27) + +/* + * Some Processor execption handled as RTEMS IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +/*-------------------------------------------------------------------------+ +| Function Prototypes. ++--------------------------------------------------------------------------*/ + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); + +#include <bsp/irq_supp.h> + +#ifdef __cplusplus +}; +#endif + +#endif +#endif diff --git a/bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h b/bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h new file mode 100644 index 0000000000..181b45f468 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/bsp/mpc8540_i2c_busdrv.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @ingroup powerpc_mpc8540i2cbusdrv + * + * @brief I2C bus driver for mpc8540-based boards + */ + +#ifndef MPC8540_I2C_BUS_DRIVER_H +#define MPC8540_I2C_BUS_DRIVER_H + +/* + * Authorship + * ---------- + * This software ('mvme3100' RTEMS BSP) was created by + * + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * The 'mvme3100' BSP was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#include <rtems.h> +#include <rtems/libi2c.h> + +/* for registration with libi2c */ +extern rtems_libi2c_bus_t *mpc8540_i2c_bus_descriptor; + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/bsps/powerpc/mvme3100/include/tm27.h b/bsps/powerpc/mvme3100/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/mvme3100/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/mvme5500/headers.am b/bsps/powerpc/mvme5500/headers.am new file mode 100644 index 0000000000..94c03a6982 --- /dev/null +++ b/bsps/powerpc/mvme5500/headers.am @@ -0,0 +1,21 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/GT64260eth.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/VMEConfig.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/VPD.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/bspException.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/gtpcireg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/gtreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/if_wmreg.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/mvme5500/include/bsp/pcireg.h diff --git a/bsps/powerpc/mvme5500/include/bsp.h b/bsps/powerpc/mvme5500/include/bsp.h new file mode 100644 index 0000000000..c1b17cee10 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. + */ + +#ifndef LIBBSP_POWERPC_MVME5500_BSP_H +#define LIBBSP_POWERPC_MVME5500_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <libcpu/io.h> +#include <bsp/vectors.h> + +/* Board type */ +typedef enum { + undefined = 0, + MVME5500, + MVME6100 +} BSP_BoardTypes; + +BSP_BoardTypes BSP_getBoardType(void); + +/* Board type */ +typedef enum { + Undefined, + UNIVERSE2, + TSI148, +} BSP_VMEchipTypes; + +BSP_VMEchipTypes BSP_getVMEchipType(void); + +/* The version of Discovery system controller */ + +typedef enum { + notdefined, + GT64260A, + GT64260B, + MV64360, +} DiscoveryChipVersion; + +DiscoveryChipVersion BSP_getDiscoveryChipVersion(void); + +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ +#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ + +#define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base + */ +#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ + +/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ +#define _IO_BASE GT64x60_REG_BASE + +#define BSP_NVRAM_BASE_ADDR 0xf1110000 + +#define BSP_RTC_INTA_REG 0x7ff0 +#define BSP_RTC_SECOND 0x7ff2 +#define BSP_RTC_MINUTE 0x7ff3 +#define BSP_RTC_HOUR 0x7ff4 +#define BSP_RTC_DATE 0x7ff5 +#define BSP_RTC_INTERRUPTS 0x7ff6 +#define BSP_RTC_WATCHDOG 0x7ff7 + +/* PCI0 Domain I/O space */ +#define PCI0_IO_BASE 0xf0000000 +#define PCI1_IO_BASE 0xf0800000 + +/* PCI 0 memory space as seen from the CPU */ +#define PCI0_MEM_BASE 0x80000000 +#define PCI_MEM_BASE 0 /* glue for vmeUniverse */ +#define PCI_MEM_BASE_ADJUSTMENT 0 + +/* address of our ram on the PCI bus */ +#define PCI_DRAM_OFFSET 0 + +/* PCI 1 memory space as seen from the CPU */ +#define PCI1_MEM_BASE 0xe0000000 +#define PCI1_MEM_SIZE 0x10000000 + +/* Needed for hot adding via PMCspan on the PCI0 local bus. + * This is board dependent, only because mvme5500 + * supports hot adding and has more than one local PCI + * bus. + */ +#define BSP_MAX_PCI_BUS_ON_PCI0 8 +#define BSP_MAX_PCI_BUS_ON_PCI1 2 +#define BSP_MAX_PCI_BUS (BSP_MAX_PCI_BUS_ON_PCI0+BSP_MAX_PCI_BUS_ON_PCI1) + + +/* The glues to Till's vmeUniverse, although the name does not + * actually reflect the relevant architect of the MVME5500. + */ +#define BSP_PCI_IRQ0 BSP_GPP_IRQ_LOWEST_OFFSET + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */ + +/* uart.c uses out_8 instead of outb */ +#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 +#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 + +#define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ +#define BSP_UART_BAUD_BASE 115200 + +/* + * Total memory using RESIDUAL DATA + */ +extern unsigned int BSP_mem_size; +/* + * PCI Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * processor clock frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +extern void bsp_reset(void); +/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ +extern int BSP_disconnect_clock_handler(void); +extern int BSP_connect_clock_handler(void); + +unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); + +/* + * Prototypes for methods called only from .S for dependency tracking + */ +char *save_boot_params( + void *r3, + void *r4, + void *r5, + char *cmdline_start, + char *cmdline_end +); +void zero_bss(void); + +/* + * Prototypes for methods in the BSP that cross file boundaries + */ +uint32_t probeMemoryEnd(void); +void pci_interface(void); +void BSP_printPicIsrTbl(void); +int I2Cread_eeprom( + unsigned char I2cBusAddr, + uint32_t devA2A1A0, + uint32_t AddrBytes, + unsigned char *pBuff, + uint32_t numBytes +); + +#if 0 +#define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach +#else +#define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach +#endif + +extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); + +#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() + +static inline void lwmemBar(void) +{ + __asm__ volatile("lwsync":::"memory"); +} + +static inline void io_flush(void) +{ + __asm__ volatile("isync":::"memory"); +} + +static inline void memBar(void) +{ + __asm__ volatile("sync":::"memory"); +} + +static inline void ioBar(void) +{ + __asm__ volatile("eieio":::"memory"); +} + +#endif + +#endif /* !ASM */ diff --git a/bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h b/bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h new file mode 100644 index 0000000000..1377e6f607 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/GT64260TWSI.h @@ -0,0 +1,20 @@ +#ifndef __GT64260TWSI_h +#define __GT64260TWSI_h + +/* GT64260TWSI.h - header for the GT64260 Two-Wire Serial Interface */ + +/* TWSI Control Register Bits */ +#define TWSI_ACK 4 +#define TWSI_INTFLG 8 +#define TWSI_STOP 0x10 +#define TWSI_START 0x20 +#define TWSI_TWSIEN 0x40 +#define TWSI_INTEN 0x80 + +void GT64260TWSIinit(void); +int GT64260TWSIstart(void); +int GT64260TWSIwrite(unsigned char Data); +int GT64260TWSIread(unsigned char *, int lastByte); +int GT64260TWSIstop(void); + +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/GT64260eth.h b/bsps/powerpc/mvme5500/include/bsp/GT64260eth.h new file mode 100644 index 0000000000..2703bb423e --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/GT64260eth.h @@ -0,0 +1,140 @@ +/* GT64260eth.h + * + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * RTEMS/Mvme5500 port 2004 by S. Kate Feng, <feng1@bnl.gov>, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* Keep the ring sizes a power of two for efficiency. + Making the Tx ring too long decreases the effectiveness of channel + bonding and packet priority. + There are no ill effects from too-large receive rings. */ +#define TX_RING_SIZE 32 +#define GT_NEXTTX(x) ((x + 1) % TX_RING_SIZE ) +#define TX_QUARTER_FULL TX_RING_SIZE/2 +#define TX_HALF_FULL TX_RING_SIZE/2 +#define RX_RING_SIZE 16 +#define HASH_TABLE_SIZE 16 +#define HASH_DRAM_SIZE HASH_TABLE_SIZE*1024 /* size of DRAM for hash table */ +#define INTR_ERR_SIZE 16 + +enum GTeth_txprio { + GE_TXPRIO_HI=1, + GE_TXPRIO_LO=0, + GE_TXPRIO_NONE=2 +}; +enum GTeth_rxprio { + GE_RXPRIO_HI=3, + GE_RXPRIO_MEDHI=2, + GE_RXPRIO_MEDLO=1, + GE_RXPRIO_LO=0 +}; + +struct GTeth_softc { + struct GTeth_desc txq_desc[TX_RING_SIZE]; /* transmit descriptor memory */ + struct GTeth_desc rxq_desc[RX_RING_SIZE]; /* receive descriptor memory */ + struct mbuf* txq_mbuf[TX_RING_SIZE]; /* transmit buffer memory */ + struct mbuf* rxq_mbuf[RX_RING_SIZE]; /* receive buffer memory */ + struct GTeth_softc *next_module; + volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* capture the right intr_status */ + unsigned int intr_err_ptr1; /* ptr used in GTeth_error() */ + unsigned int intr_err_ptr2; /* ptr used in ISR */ + struct ifqueue txq_pendq; /* these are ready to go to the GT */ + unsigned int txq_pending; + unsigned int txq_lo; /* next to be given to GT DMA */ + unsigned int txq_fi; /* next to be free */ + unsigned int txq_to_cpu; /* next to be returned to CPU */ + unsigned int txq_ei_gapcount; /* counter until next EI */ + unsigned int txq_nactive; /* number of active descriptors */ + unsigned int txq_nintr; /* number of txq desc. send TX_EVENT */ + unsigned int txq_outptr; /* where to put next transmit packet */ + unsigned int txq_inptr; /* start of 1st queued tx packet */ + unsigned int txq_free; /* free Tx queue slots. */ + unsigned txq_intrbits; /* bits to write to EIMR */ + unsigned txq_esdcmrbits; /* bits to write to ESDCMR */ + unsigned txq_epsrbits; /* bits to test with EPSR */ + + caddr_t txq_ectdp; /* offset to cur. tx desc ptr reg */ + unsigned long txq_desc_busaddr; /* bus addr of tx descriptors */ + caddr_t txq_buf_busaddr; /* bus addr of tx buffers */ + + struct mbuf *rxq_curpkt; /* mbuf for current packet */ + struct GTeth_desc *rxq_head_desc; /* rxq head descriptor */ + unsigned int rxq_fi; /* next to be returned to CPU */ + unsigned int rxq_active; /* # of descriptors given to GT */ + unsigned rxq_intrbits; /* bits to write to EIMR */ + unsigned long rxq_desc_busaddr; /* bus addr of rx descriptors */ + + struct arpcom arpcom; /* rtems if structure, contains ifnet */ + int sc_macno; /* which mac? 0, 1, or 2 */ + + unsigned int sc_tickflags; + #define GE_TICK_TX_IFSTART 0x0001 + #define GE_TICK_RX_RESTART 0x0002 + unsigned int sc_flags; + #define GE_ALLMULTI 0x0001 + #define GE_PHYSTSCHG 0x0002 + #define GE_RXACTIVE 0x0004 + unsigned sc_pcr; /* current EPCR value */ + unsigned sc_pcxr; /* current EPCXR value */ + unsigned sc_intrmask; /* current EIMR value */ + unsigned sc_idlemask; /* suspended EIMR bits */ + unsigned sc_max_frame_length; /* maximum frame length */ + unsigned rx_buf_sz; + + /* Hash table related members */ + unsigned long long *sc_hashtable; + unsigned int sc_hashmask; /* 0x1ff or 0x1fff */ + + rtems_id daemonTid; + rtems_id daemonSync; /* synchronization with the daemon */ + /* statistics */ + struct { + volatile unsigned long rxInterrupts; + + volatile unsigned long txInterrupts; + unsigned long txMultiBuffPacket; + unsigned long txMultiMaxLen; + unsigned long txSinglMaxLen; + unsigned long txMultiMaxLoop; + unsigned long txBuffMaxLen; + unsigned long length_errors; + unsigned long frame_errors; + unsigned long crc_errors; + unsigned long or_errors; /* overrun error */ + } stats; +}; diff --git a/bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h b/bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h new file mode 100644 index 0000000000..d9081ccb53 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/GT64260ethreg.h @@ -0,0 +1,879 @@ +/* $NetBSD: GT64260ethreg.h,v 1.2 2003/03/17 16:41:16 matt Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DEV_GTETHREG_H_ +#define _DEV_GTETHREG_H_ + +#define ETH__BIT(bit) (1U << (bit)) +#define ETH__LLBIT(bit) (1ULL << (bit)) +#define ETH__MASK(bit) (ETH__BIT(bit) - 1) +#define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1) +#define ETH__GEN(n, off) (0x2400+((n) << 10)+(ETH__ ## off)) +#define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len)) +#define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len)) +#define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit))) +#define ETH__INS(new, bit) ((new) << (bit)) +#define ETH__LLINS(new, bit) ((unsigned long long)(new) << (bit)) + +/* + * Descriptors used for both receive & transmit data. Note that the descriptor + * must start on a 4LW boundary. Since the GT accesses the descriptor as + * two 64-bit quantities, we must present them 32bit quantities in the right + * order based on endianess. + */ + +struct GTeth_desc { +#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN /* for mvme5500 */ + unsigned ed_lencnt; /* Buffer size is hi 16 bits; Byte count (rx) is lo 16 */ + unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */ + unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */ + unsigned ed_bufptr; /* pointer to packet buffer */ +#endif +#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN + unsigned ed_cmdsts; /* command (hi16)/status (lo16) bits */ + unsigned ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ + unsigned ed_bufptr; /* pointer to packet buffer */ + unsigned ed_nxtptr; /* next descriptor (must be 4LW aligned) */ +#endif +}; + +/* Ethernet 0 address control (Low), Offset: 0xf200 */ +#define RxBSnoopEn ETH__BIT(6) /* Rx buffer snoop enable,1=enable*/ +#define TxBSnoopEn ETH__BIT(14) /* Tx buffer snoop enable */ +#define RxDSnoopEn ETH__BIT(22) /* Rx descriptor snoop enable */ +#define TxDSnoopEn ETH__BIT(30) /* Tx descriptor snoop enable */ + +/* Ethernet 0 address control (High), Offset: 0xf204 */ +#define HashSnoopEn ETH__BIT(6) /* Hash Table snoop enable */ + +/* <skf> */ +#define GT_CUU_Eth0_AddrCtrlLow 0xf200 +#define GT_CUU_Eth0_AddrCtrlHigh 0xf204 + +/* Table 578: Ethernet TX Descriptor - Command/Status word + * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set, + * otherwise should be 0 (tx). + */ + +#define TX_STS_LC ETH__BIT(5) /* Late Collision */ +#define TX_STS_UR ETH__BIT(6) /* Underrun error */ +#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */ +#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */ +#define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */ +#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */ +#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ +#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ +#define TX_CMD_P ETH__BIT(18) /* Pad Packet */ +#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */ +#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ +#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */ +#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ + +#define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O) +#define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O) + +/* Table 608: Ethernet RX Descriptor - Command/Status Word + * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set, + * otherwise should be ignored (rx). + */ +#define RX_STS_CE ETH__BIT(0) /* CRC Error */ +#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */ +#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */ +#define RX_STS_OR ETH__BIT(6) /* Overrun Error */ +#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */ +#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */ +#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */ +#define RX_STS_M ETH__BIT(12) /* Missed Frame */ +#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */ +#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */ +#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */ +#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ +#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ +#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ +#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */ +#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ + +/* Table 586: Hash Table Entry Fields + */ +#define HSH_V ETH__LLBIT(0) /* Entry is valid */ +#define HSH_S ETH__LLBIT(1) /* Skip this entry */ +#define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */ +#define HSH_R ETH__LLBIT(2) /* Receive(1) */ +#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2) +#define HSH_PRIO_INS(v) ETH__LLINS(v, 51) +#define HSH_ADDR_MASK 0x7fffff8LLU +#define HSH_LIMIT 12 + + +#define ETH_EPAR 0x2000 /* PHY Address Register */ +#define ETH_ESMIR 0x2010 /* SMI Register */ + +#define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */ +#define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */ +#define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */ +#define ETH_SIZE 0x0400 /* Register Space */ + +#define ETH__EBASE 0x0000 /* Base of Registers */ +#define ETH__EPCR 0x0000 /* Port Config. Register */ +#define ETH__EPCXR 0x0008 /* Port Config. Extend Reg */ +#define ETH__EPCMR 0x0010 /* Port Command Register */ +#define ETH__EPSR 0x0018 /* Port Status Register */ +#define ETH__ESPR 0x0020 /* Port Serial Parameters Reg */ +#define ETH__EHTPR 0x0028 /* Port Hash Table Pointer Reg*/ +#define ETH__EFCSAL 0x0030 /* Flow Control Src Addr Low */ +#define ETH__EFCSAH 0x0038 /* Flow Control Src Addr High */ +#define ETH__ESDCR 0x0040 /* SDMA Configuration Reg */ +#define ETH__ESDCMR 0x0048 /* SDMA Command Register */ +#define ETH__EICR 0x0050 /* Interrupt Cause Register */ +#define ETH__EIMR 0x0058 /* Interrupt Mask Register */ +#define ETH__EFRDP0 0x0080 /* First Rx Desc Pointer 0 */ +#define ETH__EFRDP1 0x0084 /* First Rx Desc Pointer 1 */ +#define ETH__EFRDP2 0x0088 /* First Rx Desc Pointer 2 */ +#define ETH__EFRDP3 0x008c /* First Rx Desc Pointer 3 */ +#define ETH__ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */ +#define ETH__ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */ +#define ETH__ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */ +#define ETH__ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */ +#define ETH__ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */ +#define ETH__ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */ +#define ETH__EDSCP2P0L 0x0060 /* IP Differentiated Services + CodePoint to Priority0 low */ +#define ETH__EDSCP2P0H 0x0064 /* IP Differentiated Services + CodePoint to Priority0 high*/ +#define ETH__EDSCP2P1L 0x0068 /* IP Differentiated Services + CodePoint to Priority1 low */ +#define ETH__EDSCP2P1H 0x006c /* IP Differentiated Services + CodePoint to Priority1 high*/ +#define ETH__EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */ +#define ETH__EMIBCTRS 0x0100 /* MIB Counters */ + +/* SKF : we are only concerned with the Ethernet0 for the mvme5500 board */ +#define ETH0_EBASE 0x2400 /* Base of Registers */ +#define ETH0_EPCR 0x2400 /* Port Config. Register */ +#define ETH0_EPCXR 0x2408 /* Port Config. Extend Reg */ +#define ETH0_EPCMR 0x2410 /* Port Command Register */ +#define ETH0_EPSR 0x2418 /* Port Status Register */ +#define ETH0_ESPR 0x2420 /* Port Serial Parameters Reg */ +#define ETH0_EHTPR 0x2428 /* Port Hash Table Pointer Reg*/ +#define ETH0_EFCSAL 0x2430 /* Flow Control Src Addr Low */ +#define ETH0_EFCSAH 0x2438 /* Flow Control Src Addr High */ +#define ETH0_ESDCR 0x2440 /* SDMA Configuration Reg */ +#define ETH0_ESDCMR 0x2448 /* SDMA Command Register */ +#define ETH0_EICR 0x2450 /* Interrupt Cause Register */ +#define ETH0_EIMR 0x2458 /* Interrupt Mask Register */ +#define ETH0_EFRDP0 0x2480 /* First Rx Desc Pointer 0 */ +#define ETH0_EFRDP1 0x2484 /* First Rx Desc Pointer 1 */ +#define ETH0_EFRDP2 0x2488 /* First Rx Desc Pointer 2 */ +#define ETH0_EFRDP3 0x248c /* First Rx Desc Pointer 3 */ +#define ETH0_ECRDP0 0x24a0 /* Current Rx Desc Pointer 0 */ +#define ETH0_ECRDP1 0x24a4 /* Current Rx Desc Pointer 1 */ +#define ETH0_ECRDP2 0x24a8 /* Current Rx Desc Pointer 2 */ +#define ETH0_ECRDP3 0x24ac /* Current Rx Desc Pointer 3 */ +#define ETH0_ECTDP0 0x24e0 /* Current Tx Desc Pointer 0 */ +#define ETH0_ECTDP1 0x24e4 /* Current Tx Desc Pointer 1 */ +#define ETH0_EDSCP2P0L 0x2460 /* IP Differentiated Services + CodePoint to Priority0 low */ +#define ETH0_EDSCP2P0H 0x2464 /* IP Differentiated Services + CodePoint to Priority0 high*/ +#define ETH0_EDSCP2P1L 0x2468 /* IP Differentiated Services + CodePoint to Priority1 low */ +#define ETH0_EDSCP2P1H 0x246c /* IP Differentiated Services + CodePoint to Priority1 high*/ +#define ETH0_EVPT2P 0x2468 /* VLAN Prio. Tag to Priority */ +#define ETH0_EMIBCTRS 0x2500 /* MIB Counters */ + +#define ETH_BASE(n) ETH__GEN(n, EBASE) +#define ETH_EPCR(n) ETH__GEN(n, EPCR) /* Port Config. Register */ +#define ETH_EPCXR(n) ETH__GEN(n, EPCXR) /* Port Config. Extend Reg */ +#define ETH_EPCMR(n) ETH__GEN(n, EPCMR) /* Port Command Register */ +#define ETH_EPSR(n) ETH__GEN(n, EPSR) /* Port Status Register */ +#define ETH_ESPR(n) ETH__GEN(n, ESPR) /* Port Serial Parameters Reg */ +#define ETH_EHTPR(n) ETH__GEN(n, EHPTR) /* Port Hash Table Pointer Reg*/ +#define ETH_EFCSAL(n) ETH__GEN(n, EFCSAL) /* Flow Control Src Addr Low */ +#define ETH_EFCSAH(n) ETH__GEN(n, EFCSAH) /* Flow Control Src Addr High */ +#define ETH_ESDCR(n) ETH__GEN(n, ESDCR) /* SDMA Configuration Reg */ +#define ETH_ESDCMR(n) ETH__GEN(n, ESDCMR) /* SDMA Command Register */ +#define ETH_EICR(n) ETH__GEN(n, EICR) /* Interrupt Cause Register */ +#define ETH_EIMR(n) ETH__GEN(n, EIMR) /* Interrupt Mask Register */ +#define ETH_EFRDP0(n) ETH__GEN(n, EFRDP0) /* First Rx Desc Pointer 0 */ +#define ETH_EFRDP1(n) ETH__GEN(n, EFRDP1) /* First Rx Desc Pointer 1 */ +#define ETH_EFRDP2(n) ETH__GEN(n, EFRDP2) /* First Rx Desc Pointer 2 */ +#define ETH_EFRDP3(n) ETH__GEN(n, EFRDP3) /* First Rx Desc Pointer 3 */ +#define ETH_ECRDP0(n) ETH__GEN(n, ECRDP0) /* Current Rx Desc Pointer 0 */ +#define ETH_ECRDP1(n) ETH__GEN(n, ECRDP1) /* Current Rx Desc Pointer 1 */ +#define ETH_ECRDP2(n) ETH__GEN(n, ECRDP2) /* Current Rx Desc Pointer 2 */ +#define ETH_ECRDP3(n) ETH__GEN(n, ECRDP3) /* Current Rx Desc Pointer 3 */ +#define ETH_ECTDP0(n) ETH__GEN(n, ECTDP0) /* Current Tx Desc Pointer 0 */ +#define ETH_ECTDP1(n) ETH__GEN(n, ECTDP1) /* Current Tx Desc Pointer 1 */ +#define ETH_EDSCP2P0L(n) ETH__GEN(n, EDSCP2P0L) /* IP Differentiated Services + CodePoint to Priority0 low */ +#define ETH_EDSCP2P0H(n) ETH__GEN(n, EDSCP2P0H) /* IP Differentiated Services + CodePoint to Priority0 high*/ +#define ETH_EDSCP2P1L(n) ETH__GEN(n, EDSCP2P1L) /* IP Differentiated Services + CodePoint to Priority1 low */ +#define ETH_EDSCP2P1H(n) ETH__GEN(n, EDSCP1P1H) /* IP Differentiated Services + CodePoint to Priority1 high*/ +#define ETH_EVPT2P(n) ETH__GEN(n, EVPT2P) /* VLAN Prio. Tag to Priority */ +#define ETH_EMIBCTRS(n) ETH__GEN(n, EMIBCTRS) /* MIB Counters */ + +#define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f) + +#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\ + ETH__INS(reg, 21)|\ + ETH_ESMIR_ReadOpcode) +#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\ + ETH__INS(reg, 21)|\ + ETH__INS(val, 0)|\ + ETH_ESMIR_WriteOpcode) +#define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16) +#define ETH_ESMIR_WriteOpcode 0 +#define ETH_ESMIR_ReadOpcode ETH__BIT(26) +#define ETH_ESMIR_ReadValid ETH__BIT(27) +#define ETH_ESMIR_Busy ETH__BIT(28) + +/* + * Table 597: Port Configuration Register (PCR) + * 00:00 PM Promiscuous mode + * 0: Normal mode (Frames are only received if the + * destination address is found in the hash + * table) + * 1: Promiscuous mode (Frames are received + * regardless of their destination address. + * Errored frames are discarded unless the Port + * Configuration register's PBF bit is set) + * 01:01 RBM Reject Broadcast Mode + * 0: Receive broadcast address + * 1: Reject frames with broadcast address + * Overridden by the promiscuous mode. + * 02:02 PBF Pass Bad Frames + * (0: Normal mode, 1: Pass bad Frames) + * The Ethernet receiver passes to the CPU errored + * frames (like fragments and collided packets) + * that are normally rejected. + * NOTE: Frames are only passed if they + * successfully pass address filtering. + * 06:03 Reserved + * 07:07 EN Enable (0: Disabled, 1: Enable) + * When enabled, the ethernet port is ready to + * transmit/receive. + * 09:08 LPBK Loop Back Mode + * 00: Normal mode + * 01: Internal loop back mode (TX data is looped + * back to the RX lines. No transition is seen + * on the interface pins) + * 10: External loop back mode (TX data is looped + * back to the RX lines and also transmitted + * out to the MII interface pins) + * 11: Reserved + * 10:10 FC Force Collision + * 0: Normal mode. + * 1: Force Collision on any TX frame. + * For RXM test (in Loopback mode). + * 11:11 Reserved. + * 12:12 HS Hash Size + * 0: 8K address filtering + * (256KB of memory space required). + * 1: 512 address filtering + * ( 16KB of memory space required). + * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1) + * 14:14 HDM Hash Default Mode + * 0: Discard addresses not found in address table + * 1: Pass addresses not found in address table + * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex) + * NOTE: Valid only when auto-negotiation for + * duplex mode is disabled. + * 30:16 Reserved + * 31:31 ACCS Accelerate Slot Time + * (0: Normal mode, 1: Reserved) + */ +#define ETH_EPCR_PM ETH__BIT(0) +#define ETH_EPCR_RBM ETH__BIT(1) +#define ETH_EPCR_PBF ETH__BIT(2) +#define ETH_EPCR_EN ETH__BIT(7) +#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2) +#define ETH_EPCR_LPBK_Normal 0 +#define ETH_EPCR_LPBK_Internal 1 +#define ETH_EPCR_LPBK_External 2 +#define ETH_EPCR_FC ETH__BIT(10) + +#define ETH_EPCR_HS ETH__BIT(12) +#define ETH_EPCR_HS_8K 0 +#define ETH_EPCR_HS_512 ETH_EPCR_HS + +#define ETH_EPCR_HM ETH__BIT(13) +#define ETH_EPCR_HM_0 0 +#define ETH_EPCR_HM_1 ETH_EPCR_HM + +#define ETH_EPCR_HDM ETH__BIT(14) +#define ETH_EPCR_HDM_Discard 0 +#define ETH_EPCR_HDM_Pass ETH_EPCR_HDM + +#define ETH_EPCR_HD_Half 0 +#define ETH_EPCR_HD_Full ETH_EPCR_HD_Full + +#define ETH_EPCR_ACCS ETH__BIT(31) + + + +/* + * Table 598: Port Configuration Extend Register (PCXR) + * 00:00 IGMP IGMP Packets Capture Enable + * 0: IGMP packets are treated as normal Multicast + * packets. + * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3 + * are trapped and sent to high priority RX + * queue. + * 01:01 SPAN Spanning Tree Packets Capture Enable + * 0: BPDU (Bridge Protocol Data Unit) packets are + * treated as normal Multicast packets. + * 1: BPDU packets are trapped and sent to high + * priority RX queue. + * 02:02 PAR Partition Enable (0: Normal, 1: Partition) + * When more than 61 collisions occur while + * transmitting, the port enters Partition mode. + * It waits for the first good packet from the + * wire and then goes back to Normal mode. Under + * Partition mode it continues transmitting, but + * it does not receive. + * 05:03 PRIOtx Priority weight in the round-robin between high + * and low priority TX queues. + * 000: 1 pkt from HIGH, 1 pkt from LOW. + * 001: 2 pkt from HIGH, 1 pkt from LOW. + * 010: 4 pkt from HIGH, 1 pkt from LOW. + * 011: 6 pkt from HIGH, 1 pkt from LOW. + * 100: 8 pkt from HIGH, 1 pkt from LOW. + * 101: 10 pkt from HIGH, 1 pkt from LOW. + * 110: 12 pkt from HIGH, 1 pkt from LOW. + * 111: All pkt from HIGH, 0 pkt from LOW. LOW is + * served only if HIGH is empty. + * NOTE: If the HIGH queue is emptied before + * finishing the count, the count is reset + * until the next first HIGH comes in. + * 07:06 PRIOrx Default Priority for Packets Received on this + * Port (00: Lowest priority, 11: Highest priority) + * 08:08 PRIOrx_Override Override Priority for Packets Received on this + * Port (0: Do not override, 1: Override with + * <PRIOrx> field) + * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode + * (0: Enable, 1: Disable) + * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control + * 0: Enable; When enabled, 1 is written (through + * SMI access) to the PHY's register 4 bit 10 + * to advertise flow-control capability. + * 1: Disable; Only enables flow control after the + * PHY address is set by the CPU. When changing + * the PHY address the flow control + * auto-negotiation must be disabled. + * 11:11 FLP Force Link Pass + * (0: Force Link Pass, 1: Do NOT Force Link pass) + * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable) + * NOTE: Only valid when auto negotiation for flow + * control is disabled. + * 13:13 Reserved + * 15:14 MFL Max Frame Length + * Maximum packet allowed for reception (including + * CRC): 00: 1518 bytes, 01: 1536 bytes, + * 10: 2048 bytes, 11: 64K bytes + * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect) + * 17:17 MIBctrMode Reserved. (MBZ) + * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec) + * NOTE: Only valid if SpeedEn bit is set. + * 19:19 SpeedEn Enable Auto-negotiation for Speed + * (0: Enable, 1: Disable) + * 20:20 RMIIen RMII enable + * 0: Port functions as MII port + * 1: Port functions as RMII port + * 21:21 DSCPen DSCP enable + * 0: IP DSCP field decoding is disabled. + * 1: IP DSCP field decoding is enabled. + * 31:22 Reserved + */ +#define ETH_EPCXR_IGMP ETH__BIT(0) +#define ETH_EPCXR_SPAN ETH__BIT(1) +#define ETH_EPCXR_PAR ETH__BIT(2) +#define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3) +#define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3) +#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8) +#define ETH_EPCXR_DLPXen ETH__BIT(9) +#define ETH_EPCXR_FCTLen ETH__BIT(10) +#define ETH_EPCXR_FLP ETH__BIT(11) +#define ETH_EPCXR_FCTL ETH__BIT(12) +#define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2) +#define ETH_EPCXR_MFL_1518 0 +#define ETH_EPCXR_MFL_1536 1 +#define ETH_EPCXR_MFL_2048 2 +#define ETH_EPCXR_MFL_64K 3 +#define ETH_EPCXR_MIBclrMode ETH__BIT(16) +#define ETH_EPCXR_MIBctrMode ETH__BIT(17) +#define ETH_EPCXR_Speed ETH__BIT(18) +#define ETH_EPCXR_SpeedEn ETH__BIT(19) +#define ETH_EPCXR_RMIIEn ETH__BIT(20) +#define ETH_EPCXR_DSCPEn ETH__BIT(21) + + + +/* + * Table 599: Port Command Register (PCMR) + * 14:00 Reserved + * 15:15 FJ Force Jam / Flow Control + * When in half-duplex mode, the CPU uses this bit + * to force collisions on the Ethernet segment. + * When the CPU recognizes that it is going to run + * out of receive buffers, it can force the + * transmitter to send jam frames, forcing + * collisions on the wire. To allow transmission + * on the Ethernet segment, the CPU must clear the + * FJ bit when more resources are available. When + * in full-duplex and flow-control is enabled, this + * bit causes the port's transmitter to send + * flow-control PAUSE packets. The CPU must reset + * this bit when more resources are available. + * 31:16 Reserved + */ + +#define ETH_EPCMR_FJ ETH__BIT(15) + + +/* + * Table 600: Port Status Register (PSR) -- Read Only + * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs) + * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full) + * 02:02 Fctl Indicates Flow-control Mode + * (0: enabled, 1: disabled) + * 03:03 Link Indicates Link Status (0: down, 1: up) + * 04:04 Pause Indicates that the port is in flow-control + * disabled state. This bit is set when an IEEE + * 802.3x flow-control PAUSE (XOFF) packet is + * received (assuming that flow-control is + * enabled and the port is in full-duplex mode). + * Reset when XON is received, or when the XOFF + * timer has expired. + * 05:05 TxLow Tx Low Priority Status + * Indicates the status of the low priority + * transmit queue: (0: Stopped, 1: Running) + * 06:06 TxHigh Tx High Priority Status + * Indicates the status of the high priority + * transmit queue: (0: Stopped, 1: Running) + * 07:07 TXinProg TX in Progress + * Indicates that the port's transmitter is in an + * active transmission state. + * 31:08 Reserved + */ +#define ETH_EPSR_Speed ETH__BIT(0) +#define ETH_EPSR_Duplex ETH__BIT(1) +#define ETH_EPSR_Fctl ETH__BIT(2) +#define ETH_EPSR_Link ETH__BIT(3) +#define ETH_EPSR_Pause ETH__BIT(4) +#define ETH_EPSR_TxLow ETH__BIT(5) +#define ETH_EPSR_TxHigh ETH__BIT(6) +#define ETH_EPSR_TXinProg ETH__BIT(7) + + +/* + * Table 601: Serial Parameters Register (SPR) + * 01:00 JAM_LENGTH Two bits to determine the JAM Length + * (in Backpressure) as follows: + * 00 = 12K bit-times + * 01 = 24K bit-times + * 10 = 32K bit-times + * 11 = 48K bit-times + * 06:02 JAM_IPG Five bits to determine the JAM IPG. + * The step is four bit-times. The value may vary + * between 4 bit time to 124. + * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA. + * The step is four bit-times. The value may vary + * between 4 bit time to 124. + * 16:12 IPG_DATA Inter-Packet Gap (IPG) + * The step is four bit-times. The value may vary + * between 12 bit time to 124. + * NOTE: These bits may be changed only when the + * Ethernet ports is disabled. + * 21:17 Data_Blind Data Blinder + * The number of nibbles from the beginning of the + * IPG, in which the IPG counter is restarted when + * detecting a carrier activity. Following this + * value, the port enters the Data Blinder zone and + * does not reset the IPG counter. This ensures + * fair access to the medium. + * The default is 10 hex (64 bit times - 2/3 of the + * default IPG). The step is 4 bit-times. Valid + * range is 3 to 1F hex nibbles. + * NOTE: These bits may be only changed when the + * Ethernet port is disabled. + * 22:22 Limit4 The number of consecutive packet collisions that + * occur before the collision counter is reset. + * 0: The port resets its collision counter after + * 16 consecutive retransmit trials and + * restarts the Backoff algorithm. + * 1: The port resets its collision counter and + * restarts the Backoff algorithm after 4 + * consecutive transmit trials. + * 31:23 Reserved + */ +#define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2) +#define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5) +#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5) +#define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5) +#define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5) +#define ETH_ESPR_Limit4(v) ETH__BIT(22) + +/* + * Table 602: Hash Table Pointer Register (HTPR) + * 31:00 HTP 32-bit pointer to the address table. + * Bits [2:0] must be set to zero. + */ + +/* + * Table 603: Flow Control Source Address Low (FCSAL) + * 15:0 SA[15:0] Source Address + * The least significant bits of the source + * address for the port. This address is used for + * Flow Control. + * 31:16 Reserved + */ + +/* + * Table 604: Flow Control Source Address High (FCSAH) + * 31:0 SA[47:16] Source Address + * The most significant bits of the source address + * for the port. This address is used for Flow + * Control. + */ + + +/* + * Table 605: SDMA Configuration Register (SDCR) + * 01:00 Reserved + * 05:02 RC Retransmit Count + * Sets the maximum number of retransmits per + * packet. After executing retransmit for RC + * times, the TX SDMA closes the descriptor with a + * Retransmit Limit error indication and processes + * the next packet. When RC is set to 0, the + * number of retransmits is unlimited. In this + * case, the retransmit process is only terminated + * if CPU issues an Abort command. + * 06:06 BLMR Big/Little Endian Receive Mode + * The DMA supports Big or Little Endian + * configurations on a per channel basis. The BLMR + * bit only affects data transfer to memory. + * 0: Big Endian + * 1: Little Endian + * 07:07 BLMT Big/Little Endian Transmit Mode + * The DMA supports Big or Little Endian + * configurations on a per channel basis. The BLMT + * bit only affects data transfer from memory. + * 0: Big Endian + * 1: Little Endian + * 08:08 POVR PCI Override + * When set, causes the SDMA to direct all its + * accesses in PCI_0 direction and overrides + * normal address decoding process. + * 09:09 RIFB Receive Interrupt on Frame Boundaries + * When set, the SDMA Rx generates interrupts only + * on frame boundaries (i.e. after writing the + * frame status to the descriptor). + * 11:10 Reserved + * 13:12 BSZ Burst Size + * Sets the maximum burst size for SDMA + * transactions: + * 00: Burst is limited to 1 64bit words. + * 01: Burst is limited to 2 64bit words. + * 10: Burst is limited to 4 64bit words. + * 11: Burst is limited to 8 64bit words. + * 31:14 Reserved + */ +#define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4) +#define ETH_ESDCR_BLMR ETH__BIT(6) +#define ETH_ESDCR_BLMT ETH__BIT(7) +#define ETH_ESDCR_POVR ETH__BIT(8) +#define ETH_ESDCR_RIFB ETH__BIT(9) +#define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2) +#define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\ + (v) |= ETH__INS(n, 12)) +#define ETH_ESDCR_BSZ_1 0 +#define ETH_ESDCR_BSZ_2 1 +#define ETH_ESDCR_BSZ_4 2 +#define ETH_ESDCR_BSZ_8 3 + +#define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \ + "4 64-bit words", "8 64-bit words" } + +/* + * Table 606: SDMA Command Register (SDCMR) + * 06:00 Reserved + * 07:07 ERD Enable RX DMA. + * Set to 1 by the CPU to cause the SDMA to start + * a receive process. Cleared when the CPU issues + * an Abort Receive command. + * 14:08 Reserved + * 15:15 AR Abort Receive + * Set to 1 by the CPU to abort a receive SDMA + * operation. When the AR bit is set, the SDMA + * aborts its current operation and moves to IDLE. + * No descriptor is closed. The AR bit is cleared + * upon entering IDLE. After setting the AR bit, + * the CPU must poll the bit to verify that the + * abort sequence is completed. + * 16:16 STDH Stop TX High + * Set to 1 by the CPU to stop the transmission + * process from the high priority queue at the end + * of the current frame. An interrupt is generated + * when the stop command has been executed. + * Writing 1 to STDH resets TXDH bit. + * Writing 0 to this bit has no effect. + * 17:17 STDL Stop TX Low + * Set to 1 by the CPU to stop the transmission + * process from the low priority queue at the end + * of the current frame. An interrupt is generated + * when the stop command has been executed. + * Writing 1 to STDL resets TXDL bit. + * Writing 0 to this bit has no effect. + * 22:18 Reserved + * 23:23 TXDH Start Tx High + * Set to 1 by the CPU to cause the SDMA to fetch + * the first descriptor and start a transmit + * process from the high priority Tx queue. + * Writing 1 to TXDH resets STDH bit. + * Writing 0 to this bit has no effect. + * 24:24 TXDL Start Tx Low + * Set to 1 by the CPU to cause the SDMA to fetch + * the first descriptor and start a transmit + * process from the low priority Tx queue. + * Writing 1 to TXDL resets STDL bit. + * Writing 0 to this bit has no effect. + * 30:25 Reserved + * 31:31 AT Abort Transmit + * Set to 1 by the CPU to abort a transmit DMA + * operation. When the AT bit is set, the SDMA + * aborts its current operation and moves to IDLE. + * No descriptor is closed. Cleared upon entering + * IDLE. After setting AT bit, the CPU must poll + * it in order to verify that the abort sequence + * is completed. + */ +#define ETH_ESDCMR_ERD ETH__BIT(7) +#define ETH_ESDCMR_AR ETH__BIT(15) +#define ETH_ESDCMR_STDH ETH__BIT(16) +#define ETH_ESDCMR_STDL ETH__BIT(17) +#define ETH_ESDCMR_TXDH ETH__BIT(23) +#define ETH_ESDCMR_TXDL ETH__BIT(24) +#define ETH_ESDCMR_AT ETH__BIT(31) + +/* + * Table 607: Interrupt Cause Register (ICR) + * 00:00 RxBuffer Rx Buffer Return + * Indicates an Rx buffer returned to CPU ownership + * or that the port finished reception of a Rx + * frame in either priority queues. + * NOTE: In order to get a Rx Buffer return per + * priority queue, use bit 19:16. This bit is + * set upon closing any Rx descriptor which + * has its EI bit set. To limit the + * interrupts to frame (rather than buffer) + * boundaries, the user must set SDMA + * Configuration register's RIFB bit. When + * the RIFB bit is set, an interrupt + * generates only upon closing the first + * descriptor of a received packet, if this + * descriptor has it EI bit set. + * 01:01 Reserved + * 02:02 TxBufferHigh Tx Buffer for High priority Queue + * Indicates a Tx buffer returned to CPU ownership + * or that the port finished transmission of a Tx + * frame. + * NOTE: This bit is set upon closing any Tx + * descriptor which has its EI bit set. To + * limit the interrupts to frame (rather than + * buffer) boundaries, the user must set EI + * only in the last descriptor. + * 03:03 TxBufferLow Tx Buffer for Low Priority Queue + * Indicates a Tx buffer returned to CPU ownership + * or that the port finished transmission of a Tx + * frame. + * NOTE: This bit is set upon closing any Tx + * descriptor which has its EI bit set. To + * limit the interrupts to frame (rather than + * buffer) boundaries, the user must set EI + * only in the last descriptor. + * 05:04 Reserved + * 06:06 TxEndHigh Tx End for High Priority Queue + * Indicates that the Tx DMA stopped processing the + * high priority queue after stop command, or that + * it reached the end of the high priority + * descriptor chain. + * 07:07 TxEndLow Tx End for Low Priority Queue + * Indicates that the Tx DMA stopped processing the + * low priority queue after stop command, or that + * it reached the end of the low priority + * descriptor chain. + * 08:08 RxError Rx Resource Error + * Indicates a Rx resource error event in one of + * the priority queues. + * NOTE: To get a Rx Resource Error Indication per + * priority queue, use bit 23:20. + * 09:09 Reserved + * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue + * Indicates a Tx resource error event during + * packet transmission from the high priority queue + * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue + * Indicates a Tx resource error event during + * packet transmission from the low priority queue + * 12:12 RxOVR Rx Overrun + * Indicates an overrun event that occurred during + * reception of a packet. + * 13:13 TxUdr Tx Underrun + * Indicates an underrun event that occurred during + * transmission of packet from either queue. + * 15:14 Reserved + * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[0] + * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[1]. + * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[2]. + * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3] + * Indicates a Rx buffer returned to CPU ownership + * or that the port completed reception of a Rx + * frame in a receive priority queue[3]. + * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0] + * Indicates a Rx resource error event in receive + * priority queue[0]. + * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1] + * Indicates a Rx resource error event in receive + * priority queue[1]. + * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2] + * Indicates a Rx resource error event in receive + * priority queue[2]. + * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3] + * Indicates a Rx resource error event in receive + * priority queue[3]. + * 27:24 Reserved + * 28:29 MIIPhySTC MII PHY Status Change + * Indicates a status change reported by the PHY + * connected to this port. Set when the MII + * management interface block identifies a change + * in PHY's register 1. + * 29:29 SMIdone SMI Command Done + * Indicates that the SMI completed a MII + * management command (either read or write) that + * was initiated by the CPU writing to the SMI + * register. + * 30:30 Reserved + * 31:31 EtherIntSum Ethernet Interrupt Summary + * This bit is a logical OR of the (unmasked) bits + * [30:04] in the Interrupt Cause register. + */ + +#define ETH_IR_RxBuffer ETH__BIT(0) +#define ETH_IR_TxBufferHigh ETH__BIT(2) +#define ETH_IR_TxBufferLow ETH__BIT(3) +#define ETH_IR_TxEndHigh ETH__BIT(6) +#define ETH_IR_TxEndLow ETH__BIT(7) +#define ETH_IR_RxError ETH__BIT(8) +#define ETH_IR_TxErrorHigh ETH__BIT(10) +#define ETH_IR_TxErrorLow ETH__BIT(11) +#define ETH_IR_RxOVR ETH__BIT(12) +#define ETH_IR_TxUdr ETH__BIT(13) +#define ETH_IR_RxBuffer_0 ETH__BIT(16) +#define ETH_IR_RxBuffer_1 ETH__BIT(17) +#define ETH_IR_RxBuffer_2 ETH__BIT(18) +#define ETH_IR_RxBuffer_3 ETH__BIT(19) +#define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4) +#define ETH_IR_RxError_0 ETH__BIT(20) +#define ETH_IR_RxError_1 ETH__BIT(21) +#define ETH_IR_RxError_2 ETH__BIT(22) +#define ETH_IR_RxError_3 ETH__BIT(23) +#define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4) +#define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\ + ETH_IR_RxBuffer_1|\ + ETH_IR_RxBuffer_2|\ + ETH_IR_RxBuffer_3|\ + ETH_IR_RxError_0|\ + ETH_IR_RxError_1|\ + ETH_IR_RxError_2|\ + ETH_IR_RxError_3) +#define ETH_IR_MIIPhySTC ETH__BIT(28) +#define ETH_IR_SMIdone ETH__BIT(29) +#define ETH_IR_EtherIntSum (1<<31) +#define ETH_IR_Summary (1<<31) +#define ETH_IR_ErrorSum 0x803d00 +#define INTR_RX_ERROR 0x801100 +#define INTR_TX_ERROR 0x002c00 + +/* + * Table 608: Interrupt Mask Register (IMR) + * 31:00 Various Mask bits for the Interrupt Cause register. + */ + +/* + * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L), + * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries. + */ + +/* + * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H) + * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries. + */ + +/* + * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L) + * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries. + */ + +/* + * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H) + * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries. + */ + +/* + * Table 613: VLAN Priority Tag to Priority (VPT2P) + * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0] + * entries. + * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0] + * entries. + * 31:16 Reserved + */ +#endif /* _DEV_GTETHREG_H_ */ diff --git a/bsps/powerpc/mvme5500/include/bsp/VMEConfig.h b/bsps/powerpc/mvme5500/include/bsp/VMEConfig.h new file mode 100644 index 0000000000..ecc5789899 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/VMEConfig.h @@ -0,0 +1,67 @@ +#ifndef RTEMS_BSP_VME_CONFIG_H +#define RTEMS_BSP_VME_CONFIG_H +/* VMEConfig.h, S. Kate Feng modified it for MVME5500 3/04 + * + * May 2011 : Use the VME shared IRQ handlers. + * + * It seems that the implementation of VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND + * is not fully developed. The UNIV_REGOFF_VCSR_BS is defined for VME64 + * specification, which does not apply to a VME32 crate. In order to avoid + * spurious VME interrupts, a better and more universal solution is + * to flush the vmeUniverse FIFO by reading a register back within the + * users' Interrupt Service Routine (ISR) before returning. + * + * Some devices might require the ISR to issue an interrupt status READ + * after its IRQ is cleared, but before its corresponding interrupt + * is enabled again. + * + */ + +/* + * Prototypes + */ +int BSP_VMEInit(void); +int BSP_VMEIrqMgrInstall(void); + +/* BSP specific address space configuration parameters */ + +/* + * The BSP maps VME address ranges into + * one BAT. + * NOTE: the BSP (startup/bspstart.c) uses + * hardcoded window lengths that match this + * layout: + */ +#define _VME_A32_WIN0_ON_PCI 0x90000000 +/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate + * CSR for space. + */ +#define _VME_CSR_ON_PCI 0x9e000000 +#define _VME_A24_ON_PCI 0x9f000000 +#define _VME_A16_ON_PCI 0x9fff0000 + +/* Reuse BAT 0 for VME */ +#define BSP_VME_BAT_IDX 0 + +/* start of the A32 window on the VME bus + * TODO: this should perhaps be a configuration option + */ +#define _VME_A32_WIN0_ON_VME 0x20000000 + +/* if _VME_DRAM_OFFSET is defined, the BSP + * will map our RAM onto the VME bus, starting + * at _VME_DRAM_OFFSET + */ +#define _VME_DRAM_OFFSET 0x90000000 + +#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ + do { \ + err = vmeUniverseInstallIrqMgrAlt(VMEUNIVERSE_IRQ_MGR_FLAG_SHARED,\ + 0, BSP_GPP_VME_VLINT0, \ + 1, BSP_GPP_VME_VLINT1, \ + 2, BSP_GPP_VME_VLINT2, \ + 3, BSP_GPP_VME_VLINT3, \ + -1 /* terminate list */); \ + } while (0) + +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/VPD.h b/bsps/powerpc/mvme5500/include/bsp/VPD.h new file mode 100644 index 0000000000..33aec8b74c --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/VPD.h @@ -0,0 +1,9 @@ +/* The mapping of the Configuration VPD + * + * (C) 2004, NSLS, Brookhaven National Laboratory, + * S. Kate Feng, <feng1@bnl.gov> + * + */ + +#define VPD_ENET0_OFFSET 0x3c +#define VPD_ENET1_OFFSET 0x45 diff --git a/bsps/powerpc/mvme5500/include/bsp/bspException.h b/bsps/powerpc/mvme5500/include/bsp/bspException.h new file mode 100644 index 0000000000..7cd816e818 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/bspException.h @@ -0,0 +1,99 @@ +#ifndef BSP_EXCEPTION_HANDLER_H +#define BSP_EXCEPTION_HANDLER_H + +/* A slightly improved exception 'default' exception handler for RTEMS / SVGM */ + +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 5/2002, + * Stanford Linear Accelerator Center, Stanford University. + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <bsp/vectors.h> + +/* Two types of exception intercepting / catching is supported: + * + * - lowlevel handling (runs at IRQ level, before restoring any + * task context). + * - highlevel handling. + * + * A lowlevel user hook is invoked twice, before and after processing + * (printing) the exception. + * If the user hook returns a nonzero value, normal processing + * is skipped (including the second call to the hook) + * + * If the hook returns nonzero to the second call, no default + * 'panic' occurs. + * + * Default 'panic': + * - if a task context is available: + * - if a highlevel handler is installed, pass control + * to the highlevel handler when returning from the + * exception (the highlevel handler should probably + * do a longjmp()). Otherwise: + * - try to suspend interrupted task. + * - hang if no task context is available. + * + */ + +typedef struct BSP_ExceptionExtensionRec_ *BSP_ExceptionExtension; + +typedef int (*BSP_ExceptionHookProc)(BSP_Exception_frame *frame, BSP_ExceptionExtension ext, int after); + +typedef struct BSP_ExceptionExtensionRec_ { + BSP_ExceptionHookProc lowlevelHook; + int quiet; /* silence the exception handler */ + void (*highlevelHook)(BSP_ExceptionExtension); + /* user fields may be added after this */ +} BSP_ExceptionExtensionRec; + +#define SRR1_TEA_EXC (1<<(31-13)) +#define SRR1_MCP_EXC (1<<(31-12)) + +void +BSP_exceptionHandler(BSP_Exception_frame* excPtr); + +/* install an exception handler to the current task context */ +BSP_ExceptionExtension +BSP_exceptionHandlerInstall(BSP_ExceptionExtension e); + +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h b/bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h new file mode 100644 index 0000000000..9fb53869ff --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/bspMvme5500.h @@ -0,0 +1,15 @@ +/* GT64260 register base mapping on the MVME5500 + * + * (C) Shuchen K. Feng <feng1@bnl.gov>,NSLS, + * Brookhaven National Laboratory, 2003 + * + */ +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define GT64260_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ +#define GT64260_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ + +#define GT64260_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base + */ +#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ diff --git a/bsps/powerpc/mvme5500/include/bsp/gtpcireg.h b/bsps/powerpc/mvme5500/include/bsp/gtpcireg.h new file mode 100644 index 0000000000..74751f6088 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/gtpcireg.h @@ -0,0 +1,99 @@ +/* $NetBSD: gtpcireg.h,v 1.2 2003/03/24 17:03:18 matt Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#define PCI_ARBCTL_EN (1<<31) + +#define PCI_COMMAND_SB_DIS 0x2000 /* PCI configuration read will stop + * acting as sync barrier transactin + */ + +#define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4 + +#define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 + +#define PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */ + +#define PCI_BARE_IntMemEn 0x200 + +#define PCI_ACCCTLBASEL_PrefetchEn 0x0001000 +#define PCI_ACCCTLBASEL_RdPrefetch 0x0010000 +#define PCI_ACCCTLBASEL_RdLinePrefetch 0x0020000 +#define PCI_ACCCTLBASEL_RdMulPrefetch 0x0040000 +#define PCI_ACCCTLBASEL_WBurst_8_QW 0x0100000 +#define PCI_ACCCTLBASEL_PCISwap_NoSwap 0x1000000 + +#define PCI0_P2P_CONFIG 0x1d14 +#define PCI_SNOOP_BASE0_LOW 0x1f00 +#define PCI_SNOOP_BASE0_HIGH 0x1f04 +#define PCI_SNOOP_TOP0 0x1f08 + +#define PCI0_SCS0_BAR_SIZE 0x0c08 +#define PCI0_SCS1_BAR_SIZE 0x0d08 +#define PCI0_SCS2_BAR_SIZE 0x0c0c +#define PCI0_SCS3_BAR_SIZE 0x0d0c + +#define PCI0_BASE_ADDR_REG_ENABLE 0x0c3c +#define PCI0_ARBITER_CNTL 0x1d00 +#define PCI0_ACCESS_CNTL_BASE0_LOW 0x1e00 +#define PCI0_ACCESS_CNTL_BASE0_HIGH 0x1e04 +#define PCI0_ACCESS_CNTL_BASE0_TOP 0x1e08 + +#define PCI0_ACCESS_CNTL_BASE1_LOW 0x1e10 +#define PCI0_ACCESS_CNTL_BASE1_HIGH 0x1e14 +#define PCI0_ACCESS_CNTL_BASE1_TOP 0x1e18 + +#define PCI1_BASE_ADDR_REG_ENABLE 0x0cbc +#define PCI1_ARBITER_CNTL 0x1d80 +#define PCI1_ACCESS_CNTL_BASE0_LOW 0x1e80 +#define PCI1_ACCESS_CNTL_BASE0_HIGH 0x1e84 +#define PCI1_ACCESS_CNTL_BASE0_TOP 0x1e88 + +#define PCI1_ACCESS_CNTL_BASE1_LOW 0x1e90 +#define PCI1_ACCESS_CNTL_BASE1_HIGH 0x1e94 +#define PCI1_ACCESS_CNTL_BASE1_TOP 0x1e98 + +#define PCI_SNOOP_BASE1_LOW 0x1f10 +#define PCI_SNOOP_BASE1_HIGH 0x1f14 +#define PCI_SNOOP_TOP1 0x1f18 + +#define PCI0_CMD_CNTL 0xc00 + +#define PCI1_P2P_CONFIG 0x1d94 +#define PCI1_CMD_CNTL 0xc80 +#define PCI1_CONFIG_ADDR 0xc78 +#define PCI1_CONFIG_DATA 0xc7c diff --git a/bsps/powerpc/mvme5500/include/bsp/gtreg.h b/bsps/powerpc/mvme5500/include/bsp/gtreg.h new file mode 100644 index 0000000000..e9aaeff844 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/gtreg.h @@ -0,0 +1,810 @@ +/* $NetBSD: gtreg.h,v 1.1 2003/03/05 22:08:22 matt Exp $ */ + +/* + * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Allegro Networks, Inc., and Wasabi Systems, Inc. + * 4. The name of Allegro Networks, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * 5. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND + * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DISCOVERY_DEV_GTREG_H_ +#define _DISCOVERY_DEV_GTREG_H_ + +#define GT__BIT(bit) (1U << (bit)) +#define GT__MASK(bit) (GT__BIT(bit) - 1) +#define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) +#define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) +#define GT__INS(new, bit) ((new) << (bit)) + + +/* + * Table 30: CPU Address Decode Register Map + */ +#define GT_SCS0_Low_Decode 0x0008 +#define GT_SCS0_High_Decode 0x0010 +#define GT_SCS1_Low_Decode 0x0208 +#define GT_SCS1_High_Decode 0x0210 +#define GT_SCS2_Low_Decode 0x0018 +#define GT_SCS2_High_Decode 0x0020 +#define GT_SCS3_Low_Decode 0x0218 +#define GT_SCS3_High_Decode 0x0220 +#define GT_CS0_Low_Decode 0x0028 +#define GT_CS0_High_Decode 0x0030 +#define GT_CS1_Low_Decode 0x0228 +#define GT_CS1_High_Decode 0x0230 +#define GT_CS2_Low_Decode 0x0248 +#define GT_CS2_High_Decode 0x0250 +#define GT_CS3_Low_Decode 0x0038 +#define GT_CS3_High_Decode 0x0040 +#define GT_BootCS_Low_Decode 0x0238 +#define GT_BootCS_High_Decode 0x0240 +#define GT_PCI0_IO_Low_Decode 0x0048 +#define GT_PCI0_IO_High_Decode 0x0050 +#define GT_PCI0_Mem0_Low_Decode 0x0058 +#define GT_PCI0_Mem0_High_Decode 0x0060 +#define GT_PCI0_Mem1_Low_Decode 0x0080 +#define GT_PCI0_Mem1_High_Decode 0x0088 +#define GT_PCI0_Mem2_Low_Decode 0x0258 +#define GT_PCI0_Mem2_High_Decode 0x0260 +#define GT_PCI0_Mem3_Low_Decode 0x0280 +#define GT_PCI0_Mem3_High_Decode 0x0288 +#define GT_PCI1_IO_Low_Decode 0x0090 +#define GT_PCI1_IO_High_Decode 0x0098 +#define GT_PCI1_Mem0_Low_Decode 0x00a0 +#define GT_PCI1_Mem0_High_Decode 0x00a8 +#define GT_PCI1_Mem1_Low_Decode 0x00b0 +#define GT_PCI1_Mem1_High_Decode 0x00b8 +#define GT_PCI1_Mem2_Low_Decode 0x02a0 +#define GT_PCI1_Mem2_High_Decode 0x02a8 +#define GT_PCI1_Mem3_Low_Decode 0x02b0 +#define GT_PCI1_Mem3_High_Decode 0x02b8 +#define GT_Internal_Decode 0x0068 +#define GT_CPU0_Low_Decode 0x0290 +#define GT_CPU0_High_Decode 0x0298 +#define GT_CPU1_Low_Decode 0x02c0 +#define GT_CPU1_High_Decode 0x02c8 +#define GT_PCI0_IO_Remap 0x00f0 +#define GT_PCI0_Mem0_Remap_Low 0x00f8 +#define GT_PCI0_Mem0_Remap_High 0x0320 +#define GT_PCI0_Mem1_Remap_Low 0x0100 +#define GT_PCI0_Mem1_Remap_High 0x0328 +#define GT_PCI0_Mem2_Remap_Low 0x02f8 +#define GT_PCI0_Mem2_Remap_High 0x0330 +#define GT_PCI0_Mem3_Remap_Low 0x0300 +#define GT_PCI0_Mem3_Remap_High 0x0338 +#define GT_PCI1_IO_Remap 0x0108 +#define GT_PCI1_Mem0_Remap_Low 0x0110 +#define GT_PCI1_Mem0_Remap_High 0x0340 +#define GT_PCI1_Mem1_Remap_Low 0x0118 +#define GT_PCI1_Mem1_Remap_High 0x0348 +#define GT_PCI1_Mem2_Remap_Low 0x0310 +#define GT_PCI1_Mem2_Remap_High 0x0350 +#define GT_PCI1_Mem3_Remap_Low 0x0318 +#define GT_PCI1_Mem3_Remap_High 0x0358 + + +/* + * Table 31: CPU Control Register Map + */ +#define GT_CPU_Cfg 0x0000 +#define GT_CPU_Mode 0x0120 +#define GT_CPU_Master_Ctl 0x0160 +#define GT_CPU_If_Xbar_Ctl_Low 0x0150 +#define GT_CPU_If_Xbar_Ctl_High 0x0158 +#define GT_CPU_If_Xbar_Timeout 0x0168 +#define GT_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 +#define GT_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 + +/* + * Table 32: CPU Sync Barrier Register Map + */ +#define GT_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) +#define GT_PCI0_Sync_Barrier 0x00c0 +#define GT_PCI1_Sync_Barrier 0x00c8 + +/* + * Table 33: CPU Access Protection Register Map + */ +#define GT_Protect_Low_0 0x0180 +#define GT_Protect_High_0 0x0188 +#define GT_Protect_Low_1 0x0190 +#define GT_Protect_High_1 0x0198 +#define GT_Protect_Low_2 0x01a0 +#define GT_Protect_High_2 0x01a8 +#define GT_Protect_Low_3 0x01b0 +#define GT_Protect_High_3 0x01b8 +#define GT_Protect_Low_4 0x01c0 +#define GT_Protect_High_4 0x01c8 +#define GT_Protect_Low_5 0x01d0 +#define GT_Protect_High_5 0x01d8 +#define GT_Protect_Low_6 0x01e0 +#define GT_Protect_High_6 0x01e8 +#define GT_Protect_Low_7 0x01f0 +#define GT_Protect_High_7 0x01f8 + +/* + * Table 34: Snoop Control Register Map + */ +#define GT_Snoop_Base_0 0x0380 +#define GT_Snoop_Top_0 0x0388 +#define GT_Snoop_Base_1 0x0390 +#define GT_Snoop_Top_1 0x0398 +#define GT_Snoop_Base_2 0x03a0 +#define GT_Snoop_Top_2 0x03a8 +#define GT_Snoop_Base_3 0x03b0 +#define GT_Snoop_Top_3 0x03b8 + +/* + * Table 35: CPU Error Report Register Map + */ +#define GT_CPU_Error_Address_Low 0x0070 +#define GT_CPU_Error_Address_High 0x0078 +#define GT_CPU_Error_Data_Low 0x0128 +#define GT_CPU_Error_Data_High 0x0130 +#define GT_CPU_Error_Parity 0x0138 +#define GT_CPU_Error_Cause 0x0140 +#define GT_CPU_Error_Mask 0x0148 + +#define GT_DecodeAddr_SET(g, r, v) \ + do { \ + gt_read((g), GT_Internal_Decode); \ + gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ + while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ + } while (0) + +#define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) +#define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) + +#define GT_MPP_Control0 0xf000 +#define GT_MPP_Control1 0xf004 +#define GT_MPP_Control2 0xf008 +#define GT_MPP_Control3 0xf00c + +/* <skf> added for GT64260 */ +#define GT_MPP_SerialPortMultiplex 0xf010 + +#define GT_GPP_IO_Control 0xf100 +#define GT_GPP_Level_Control 0xf110 +#define GT_GPP_Value 0xf104 +#define GT_GPP_Interrupt_Cause 0xf108 +#define GT_GPP_Interrupt_Mask 0xf10c +/* + * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 + * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 + * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 + * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 + * Table 44: CS[0]* Low Decode Address, Offset: 0x028 + * Table 46: CS[1]* Low Decode Address, Offset: 0x228 + * Table 48: CS[2]* Low Decode Address, Offset: 0x248 + * Table 50: CS[3]* Low Decode Address, Offset: 0x038 + * Table 52: BootCS* Low Decode Address, Offset: 0x238 + * Table 75: CPU 0 Low Decode Address, Offset: 0x290 + * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 + * + * 11:00 LowAddr SCS[0] Base Address + * 31:12 Reserved Must be 0. + */ + +/* + * Table 37: SCS[0]* High Decode Address, Offset: 0x010 + * Table 39: SCS[1]* High Decode Address, Offset: 0x210 + * Table 41: SCS[2]* High Decode Address, Offset: 0x020 + * Table 43: SCS[3]* High Decode Address, Offset: 0x220 + * Table 45: CS[0]* High Decode Address, Offset: 0x030 + * Table 47: CS[1]* High Decode Address, Offset: 0x230 + * Table 49: CS[2]* High Decode Address, Offset: 0x250 + * Table 51: CS[3]* High Decode Address, Offset: 0x040 + * Table 53: BootCS* High Decode Address, Offset: 0x240 + * Table 76: CPU 0 High Decode Address, Offset: 0x298 + * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 + * + * 11:00 HighAddr SCS[0] Top Address + * 31:12 Reserved + */ + +/* + * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 + * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 + * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 + * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 + * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 + * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 + * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 + * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 + * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 + * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 + * + * 11:00 LowAddr PCI IO/Memory Space Base Address + * 23:12 Reserved + * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; + * 1: No swapping; 2: Both byte and word swap; + * 3: Word swap; 4..7: Reserved) + * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when + * configured to 64-bit PCI bus and not I/O) + * 0: Assert s REQ64* only when transaction + * is longer than 64-bits. + * 1: Always assert REQ64*. + * 31:28 Reserved + */ +#define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) +#define GT_PCISwap_ByteSwap 0 +#define GT_PCISwap_NoSwap 1 +#define GT_PCISwap_ByteWordSwap 2 +#define GT_PCISwap_WordSwap 3 +#define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) + +/* + * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 + * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 + * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 + * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 + * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 + * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 + * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 + * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 + * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 + * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 + * + * 11:00 HighAddr PCI_0 I/O Space Top Address + * 31:12 Reserved + */ + +/* + * Table 74: Internal Space Decode, Offset: 0x068 + * 15:00 IntDecode GT64260 Internal Space Base Address + * 23:16 Reserved + * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. + * NOTE: Reserved for Galileo Technology usage. + * Relevant only for PCI master configuration + * transactions on the PCI bus. + * 31:27 Reserved + */ + +/* + * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 + * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 + * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 + * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 + * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 + * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 + * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 + * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 + * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 + * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 + * + * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) + * 31:12 Reserved + */ + +/* + * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 + * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 + * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 + * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 + * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 + * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 + * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 + * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 + * + * 31:00 Remap PCI Memory Address Remap (high 32 bits) + */ + +/* + * Table 97: CPU Configuration, Offset: 0x000 + * 07:00 NoMatchCnt CPU Address Miss Counter + * 08:08 NoMatchCntEn CPU Address Miss Counter Enable + * NOTE: Relevant only if multi-GT is enabled. + * (0: Disabled; 1: Enabled) + * 09:09 NoMatchCntExt CPU address miss counter MSB + * 10:10 Reserved + * 11:11 AACKDelay Address Acknowledge Delay + * 0: AACK* is asserted one cycle after TS*. + * 1: AACK* is asserted two cycles after TS*. + * 12:12 Endianess Must be 0 + * NOTE: The GT64260 does not support the PowerPC + * Little Endian convention + * 13:13 Pipeline Pipeline Enable + * 0: Disabled. The GT64260 will not respond with + * AACK* to a new CPU transaction, before the + * previous transaction data phase completes. + * 1: Enabled. + * 14:14 Reserved + * 15:15 TADelay Transfer Acknowledge Delay + * 0: TA* is asserted one cycle after AACK* + * 1: TA* is asserted two cycles after AACK* + * 16:16 RdOOO Read Out of Order Completion + * 0: Not Supported, Data is always returned in + * order (DTI[0-2] is always driven + * 1: Supported + * 17:17 StopRetry Relevant only if PCI Retry is enabled + * 0: Keep Retry all PCI transactions targeted + * to the GT64260. + * 1: Stop Retry of PCI transactions. + * 18:18 MultiGTDec Multi-GT Address Decode + * 0: Normal address decoding + * 1: Multi-GT address decoding + * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 21:20 Reserved + * 22:22 PErrProp Parity Error Propagation + * 0: GT64260 always drives good parity on + * DP[0-7] during CPU reads. + * 1: GT64260 drives bad parity on DP[0-7] in case + * the read response from the target interface + * comes with erroneous data indication + * (e.g. ECC error from SDRAM interface). + * 25:23 Reserved + * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... + * 0: is not checked. (Not connected) + * 1: is checked (Connected) + * 27:27 RemapWrDis Address Remap Registers Write Control + * 0: Write to Low Address decode register. + * Results in writing of the corresponding + * Remap register. + * 1: Write to Low Address decode register. No + * affect on the corresponding Remap register. + * 28:28 ConfSBDis Configuration Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 29:29 IOSBDis I/O Read Sync Barrier Disable + * 0: enabled; 1: disabled + * 30:30 ClkSync Clocks Synchronization + * 0: The CPU interface is running with SysClk, + * which is asynchronous to TClk. + * 1: The CPU interface is running with TClk. + * 31:31 Reserved + */ +#define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) +#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) +#define GT_CPUCfg_NoMatchCntExt GT__BIT(10) +#define GT_CPUCfg_AACKDelay GT__BIT(11) +#define GT_CPUCfg_Endianess GT__BIT(12) +#define GT_CPUCfg_Pipeline GT__BIT(13) +#define GT_CPUCfg_TADelay GT__BIT(15) +#define GT_CPUCfg_RdOOO GT__BIT(16) +#define GT_CPUCfg_StopRetry GT__BIT(17) +#define GT_CPUCfg_MultiGTDec GT__BIT(18) +#define GT_CPUCfg_DPValid GT__BIT(19) +#define GT_CPUCfg_PErrProp GT__BIT(22) +#define GT_CPUCfg_APValid GT__BIT(26) +#define GT_CPUCfg_RemapWrDis GT__BIT(27) +#define GT_CPUCfg_ConfSBDis GT__BIT(28) +#define GT_CPUCfg_IOSBDis GT__BIT(29) +#define GT_CPUCfg_ClkSync GT__BIT(30) + +/* + * Table 98: CPU Mode, Offset: 0x120, Read only + * 01:00 MultiGTID Multi-GT ID + * Represents the ID to which the GT64260 responds + * to during a multi-GT address decoding period. + * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration + * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions + * 07:04 CPUType + * 0x0-0x3: Reserved + * 0x4: 64-bit PowerPC CPU, 60x bus + * 0x5: 64-bit PowerPC CPU, MPX bus + * 0x6-0xf: Reserved + * 31:08 Reserved + */ +#define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) +#define GT_CPUMode_MultiGT GT__BIT(2) +#define GT_CPUMode_RetryEn GT__BIT(3) +#define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) + +/* + * Table 99: CPU Master Control, Offset: 0x160 + * 07:00 Reserved + * 08:08 IntArb CPU Bus Internal Arbiter Enable + * NOTE: Only relevant to 60x bus mode. When + * running MPX bus, the GT64260 internal + * arbiter must be used. + * 0: Disabled. External arbiter is required. + * 1: Enabled. Use the GT64260 CPU bus arbiter. + * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control + * NOTE: This bit must be set to 1. It is reserved + * for Galileo Technology usage. + * 0: Enable internal bus sharing between master + * and slave interfaces. + * 1: Disable internal bus sharing between master + * and slave interfaces. + * 10:10 MWrTrig Master Write Transaction Trigger + * 0: With first valid write data + * 1: With last valid write data + * 11:11 MRdTrig Master Read Response Trigger + * 0: With first valid read data + * 1: With last valid read data + * 12:12 CleanBlock Clean Block Snoop Transaction Support + * 0: CPU does not support clean block (603e,750) + * 1: CPU supports clean block (604e,G4) + * 13:13 FlushBlock Flush Block Snoop Transaction Support + * 0: CPU does not support flush block (603e,750) + * 1: CPU supports flush block (604e,G4) + * 31:14 Reserved + */ +#define GT_CPUMstrCtl_IntArb GT__BIT(8) +#define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) +#define GT_CPUMstrCtl_MWrTrig GT__BIT(10) +#define GT_CPUMstrCtl_MRdTrig GT__BIT(11) +#define GT_CPUMstrCtl_CleanBlock GT__BIT(12) +#define GT_CPUMstrCtl_FlushBlock GT__BIT(13) + +#define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ +#define GT_ArbSlice_DEVICE 0x1 /* Device request */ +#define GT_ArbSlice_NULL 0x2 /* NULL request */ +#define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ +#define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ +#define GT_ArbSlice_COMM 0x5 /* Comm unit access */ +#define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ +#define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ + /* 0x8-0xf: Reserved */ + +/* Pass in the slice number (from 0..16) as 'n' + */ +#define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) + +/* + * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 + * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter + */ + +/* + * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 + * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter + */ + +/* + * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 + * NOTE: Reserved for Galileo Technology usage. + * 07:00 Timeout Crossbar Arbiter Timeout Preset Value + * 15:08 Reserved + * 16:16 TimeoutEn Crossbar Arbiter Timer Enable + * (0: Enable; 1: Disable) + * 31:17 Reserved + */ + +/* + * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 + * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter + * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter + * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter + * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter + * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter + * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter + * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter + * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter + */ +/* + * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 + * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter + * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter + * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter + * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter + * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter + * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter + * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter + * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter + */ + +/* + * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 + * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 + * NOTE: The read data is random and should be ignored. + * 31:00 SyncBarrier A CPU read from this register creates a + * synchronization barrier cycle. + */ + +/* + * Table 107: CPU Protect Address 0 Low, Offset: 0x180 + * Table 109: CPU Protect Address 1 Low, Offset: 0x190 + * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 + * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 + * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 + * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 + * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 + * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 + * + * 11:00 LowAddr CPU Protect Region Base Address + * Corresponds to address bits[31:20]. + * 15:12 Reserved. Must be 0 + * 16:16 AccProtect CPU Access Protect + * Access is (0: allowed; 1: forbidden) + * 17:17 WrProtect CPU Write Protect + * Writes are (0: allowed; 1: forbidden) + * 18:18 CacheProtect CPU caching protect. Caching (block read) + * is (0: allowed; 1: forbidden) + * 31:19 Reserved + */ +#define GT_CPU_AccProtect GT__BIT(16) +#define GT_CPU_WrProtect GT__BIT(17) +#define GT_CPU_CacheProtect GT__BIT(18) + +/* + * Table 108: CPU Protect Address 0 High, Offset: 0x188 + * Table 110: CPU Protect Address 1 High, Offset: 0x198 + * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 + * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 + * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 + * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 + * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 + * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 + * + * 11:00 HighAddr CPU Protect Region Top Address + * Corresponds to address bits[31:20] + * 31:12 Reserved + */ + +/* + * Table 123: Snoop Base Address 0, Offset: 0x380 + * Table 125: Snoop Base Address 1, Offset: 0x390 + * Table 127: Snoop Base Address 2, Offset: 0x3a0 + * Table 129: Snoop Base Address 3, Offset: 0x3b0 + * + * 11:00 LowAddr Snoop Region Base Address [31:20] + * 15:12 Reserved Must be 0. + * 17:16 Snoop Snoop Type + * 0x0: No Snoop + * 0x1: Snoop to WT region + * 0x2: Snoop to WB region + * 0x3: Reserved + * 31:18 Reserved + */ +#define GT_Snoop_GET(v) GT__EXT((v), 16, 2) +#define GT_Snoop_INS(v) GT__INS((v), 16) +#define GT_Snoop_None 0 +#define GT_Snoop_WT 1 +#define GT_Snoop_WB 2 + + +/* + * Table 124: Snoop Top Address 0, Offset: 0x388 + * Table 126: Snoop Top Address 1, Offset: 0x398 + * Table 128: Snoop Top Address 2, Offset: 0x3a8 + * Table 130: Snoop Top Address 3, Offset: 0x3b8 + * 11:00 HighAddr Snoop Region Top Address [31:20] + * 31:12 Reserved + */ + + +/* + * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. + * In case of multiple errors, only the first one is latched. New error + * report latching is enabled only after the CPU Error Address Low register + * is being read. + * 31:00 ErrAddr Latched address bits [31:0] of a CPU + * transaction in case of: + * o illegal address (failed address decoding) + * o access protection violation + * o bad data parity + * o bad address parity + * Upon address latch, no new address are + * registered (due to additional error condition), + * until the register is being read. + */ + +/* + * Table 132: CPU Error Address High, Offset: 0x078, Read Only. + * Once data is latched, no new data can be registered (due to additional + * error condition), until CPU Error Low Address is being read (which + * implies, it should be the last being read by the interrupt handler). + * 03:00 Reserved + * 07:04 ErrPar Latched address parity bits in case + * of bad CPU address parity detection. + * 31:08 Reserved + */ +#define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) + +/* + * Table 133: CPU Error Data Low, Offset: 0x128, Read only. + * 31:00 PErrData Latched data bits [31:0] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 134: CPU Error Data High, Offset: 0x130, Read only. + * 31:00 PErrData Latched data bits [63:32] in case of bad data + * parity sampled on write transactions or on + * master read transactions. + */ + +/* + * Table 135: CPU Error Parity, Offset: 0x138, Read only. + * 07:00 PErrPar Latched data parity bus in case of bad data + * parity sampled on write transactions or on + * master read transactions. + * 31:10 Reserved + */ +#define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) + +/* + * Table 136: CPU Error Cause, Offset: 0x140 + * Bits[7:0] are clear only. A cause bit is set upon an error condition + * occurrence. Write a 0 value to clear the bit. Writing a 1 value has + * no affect. + * 00:00 AddrOut CPU Address Out of Range + * 01:01 AddrPErr Bad Address Parity Detected + * 02:02 TTErr Transfer Type Violation. + * The CPU attempts to burst (read or write) to an + * internal register. + * 03:03 AccErr Access to a Protected Region + * 04:04 WrErr Write to a Write Protected Region + * 05:05 CacheErr Read from a Caching protected region + * 06:06 WrDataPErr Bad Write Data Parity Detected + * 07:07 RdDataPErr Bad Read Data Parity Detected + * 26:08 Reserved + * 31:27 Sel Specifies the error event currently being + * reported in Error Address, Error Data, and + * Error Parity registers. + * 0x0: AddrOut + * 0x1: AddrPErr + * 0x2: TTErr + * 0x3: AccErr + * 0x4: WrErr + * 0x5: CacheErr + * 0x6: WrDataPErr + * 0x7: RdDataPErr + * 0x8-0x1f: Reserved + */ +#define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) +#define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) +#define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) +#define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) +#define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) +#define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) +#define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) +#define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) + +#define GT_CPUError_Sel_AddrOut 0 +#define GT_CPUError_Sel_AddrPErr 1 +#define GT_CPUError_Sel_TTErr 2 +#define GT_CPUError_Sel_AccErr 3 +#define GT_CPUError_Sel_WrErr 4 +#define GT_CPUError_Sel_CacheErr 5 +#define GT_CPUError_Sel_WrDataPErr 6 +#define GT_CPUError_Sel_RdDataPErr 7 + +#define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) + +/* + * Table 137: CPU Error Mask, Offset: 0x148 + * 00:00 AddrOut If set to 1, enables AddrOut interrupt. + * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. + * 02:02 TTErr If set to 1, enables TTErr interrupt. + * 03:03 AccErr If set to 1, enables AccErr interrupt. + * 04:04 WrErr If set to 1, enables WrErr interrupt. + * 05:05 CacheErr If set to 1, enables CacheErr interrupt. + * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. + * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. + * 31:08 Reserved + */ + +/* Comm Unit Arbiter Control */ +#define GT_CommUnitArb_Ctrl 0xf300 /*<skf>*/ +/* + * Comm Unit Interrupt registers + */ +#define GT_CommUnitIntr_Cause 0xf310 +#define GT_CommUnitIntr_Mask 0xf314 +#define GT_CommUnitIntr_ErrAddr 0xf318 + +#define GT_CommUnitIntr_E0 0x00000007 +#define GT_CommUnitIntr_E1 0x00000070 +#define GT_CommUnitIntr_E2 0x00000700 +#define GT_CommUnitIntr_S0 0x00070000 +#define GT_CommUnitIntr_S1 0x00700000 +#define GT_CommUnitIntr_Sel 0x70000000 + +/* + * SDRAM Error Report (ECC) Registers + */ +#define GT_ECC_Data_Lo 0x484 /* latched Error Data (low) */ +#define GT_ECC_Data_Hi 0x480 /* latched Error Data (high) */ +#define GT_ECC_Addr 0x490 /* latched Error Address */ +#define GT_ECC_Rec 0x488 /* latched ECC code from SDRAM */ +#define GT_ECC_Calc 0x48c /* latched ECC code from SDRAM */ +#define GT_ECC_Ctl 0x494 /* ECC Control */ +#define GT_ECC_Count 0x498 /* ECC 1-bit error count */ + +/* + * Watchdog Registers + */ +#define GT_WDOG_Config 0xb410 +#define GT_WDOG_Value 0xb414 +#define GT_WDOG_Value_NMI GT__MASK(24) +#define GT_WDOG_Config_Preset GT__MASK(24) +#define GT_WDOG_Config_Ctl1a GT__BIT(24) +#define GT_WDOG_Config_Ctl1b GT__BIT(25) +#define GT_WDOG_Config_Ctl2a GT__BIT(26) +#define GT_WDOG_Config_Ctl2b GT__BIT(27) +#define GT_WDOG_Config_Enb GT__BIT(31) + +#define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) +#define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) + +/* + * Device Bus Interrupts + */ +#define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ +#define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ +#define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ + +/* + * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK + */ +#define GT_DEVBUS_DBurstErr GT__BIT(0) +#define GT_DEVBUS_DRdyErr GT__BIT(1) +#define GT_DEVBUS_Sel GT__BIT(27) +#define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) + +/* TWSI Interface - TWSI Interface Registers <skf> */ +#define TWSI_SLV_ADDR 0xc000 +#define TWSI_EXT_SLV_ADDR 0xc010 +#define TWSI_DATA 0xc004 +#define TWSI_CTRL 0xc008 +#define TWSI_STATUS 0xc00c +#define TWSI_BAUDE_RATE 0xc00c +#define TWSI_SFT_RST 0xc01c + +/* Section 25.2 : Table 734 <skf> */ + +#define GT64260_MAIN_INT_CAUSE_LO 0xc18 /* read Only */ +#define GT64260_MAIN_INT_CAUSE_HI 0xc68 /* read Only */ +#define GT64260_CPU_INT_MASK_LO 0xc1c +#define GT64260_CPU_INT_MASK_HI 0xc6c +#define GT64260_CPU_SEL_CAUSE 0xc70 /* read Only */ +#define GT_PCI0_INT_MASK_LO 0xc24 +#define GT_PCI0_INT_MASK_HI 0xc64 +#define GT_PCI0_SEL_CAUSE 0xc74 /* read Only */ +#define GT_PCI1_INT_MASK_LO 0xca4 +#define GT_PCI1_INT_MASK_HI 0xce4 +#define GT_PCI1_SEL_CAUSE 0xcf4 /* read Only */ +#define GT_CPU_INT0_MASK 0xe60 +#define GT_CPU_INT1_MASK 0xe64 +#define GT_CPU_INT2_MASK 0xe68 +#define GT_CPU_INT3_MASK 0xe6c + +#endif /* !_DISCOVERY_DEV_GTREG_H */ diff --git a/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h b/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h new file mode 100644 index 0000000000..3e21c62581 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/if_wmreg.h @@ -0,0 +1,740 @@ +/* $NetBSD: if_wmreg.h,v 1.22 2007/04/29 20:35:21 bouyer Exp $ */ + +/* + * Copyright (c) 2001 Wasabi Systems, Inc. + * All rights reserved. + * + * Written by Jason R. Thorpe for Wasabi Systems, Inc. + * Some are added by Shuchen Kate Feng <feng1@bnl.gov>, + * NSLS, Brookhaven National Laboratory. All rights reserved. + * under the Deaprtment of Energy contract DE-AC02-98CH10886 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the NetBSD Project by + * Wasabi Systems, Inc. + * 4. The name of Wasabi Systems, Inc. may not be used to endorse + * or promote products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Register description for the Intel i82542 (``Wiseman''), + * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit + * Ethernet chips. + */ + +/* + * The wiseman supports 64-bit PCI addressing. This structure + * describes the address in descriptors. + */ +typedef struct wiseman_addr { + uint32_t wa_low; /* low-order 32 bits */ + uint32_t wa_high; /* high-order 32 bits */ +} __attribute__((__packed__)) wiseman_addr_t; + +/* + * The Wiseman receive descriptor. + * + * The receive descriptor ring must be aligned to a 4K boundary, + * and there must be an even multiple of 8 descriptors in the ring. + */ +typedef volatile struct wiseman_rxdesc { + wiseman_addr_t wrx_addr; /* buffer address */ + + uint16_t wrx_len; /* buffer length */ + uint16_t wrx_cksum; /* checksum (starting at PCSS) */ + + uint8_t wrx_status; /* Rx status */ + uint8_t wrx_errors; /* Rx errors */ + uint16_t wrx_special; /* special field (VLAN, etc.) */ +} __attribute__((__packed__)) wiseman_rxdesc_t; + +/* wrx_status bits */ +#define WRX_ST_DD (1U << 0) /* descriptor done */ +#define WRX_ST_EOP (1U << 1) /* end of packet */ +#define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ +#define WRX_ST_VP (1U << 3) /* VLAN packet */ +#define WRX_ST_BPDU (1U << 4) /* ??? */ +#define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ +#define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ +#define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ + +/* wrx_error bits */ +#define WRX_ER_CE (1U << 0) /* CRC error */ +#define WRX_ER_SE (1U << 1) /* symbol error */ +#define WRX_ER_SEQ (1U << 2) /* sequence error */ +#define WRX_ER_ICE (1U << 3) /* ??? */ +#define WRX_ER_CXE (1U << 4) /* carrier extension error */ +#define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ +#define WRX_ER_IPE (1U << 6) /* IP checksum error */ +#define WRX_ER_RXE (1U << 7) /* Rx data error */ + +/* wrx_special field for VLAN packets */ +#define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ +#define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ +#define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ + +/* + * The Wiseman transmit descriptor. + * + * The transmit descriptor ring must be aligned to a 4K boundary, + * and there must be an even multiple of 8 descriptors in the ring. + */ +typedef struct wiseman_tx_fields { + uint8_t wtxu_status; /* Tx status */ + uint8_t wtxu_options; /* options */ + uint16_t wtxu_vlan; /* VLAN info */ +} __attribute__((__packed__)) wiseman_txfields_t; +typedef volatile struct wiseman_txdesc { + wiseman_addr_t wtx_addr; /* buffer address */ + uint32_t wtx_cmdlen; /* command and length */ + wiseman_txfields_t wtx_fields; /* fields; see below */ +} __attribute__((__packed__)) wiseman_txdesc_t; + +/* Commands for wtx_cmdlen */ +#define WTX_CMD_EOP (1U << 24) /* end of packet */ +#define WTX_CMD_IFCS (1U << 25) /* insert FCS */ +#define WTX_CMD_RS (1U << 27) /* report status */ +#define WTX_CMD_RPS (1U << 28) /* report packet sent */ +#define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ +#define WTX_CMD_VLE (1U << 30) /* VLAN enable */ +#define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ + +/* Descriptor types (if DEXT is set) */ +#define WTX_DTYP_C (0U << 20) /* context */ +#define WTX_DTYP_D (1U << 20) /* data */ + +/* wtx_fields status bits */ +#define WTX_ST_DD (1U << 0) /* descriptor done */ +#define WTX_ST_EC (1U << 1) /* excessive collisions */ +#define WTX_ST_LC (1U << 2) /* late collision */ +#define WTX_ST_TU (1U << 3) /* transmit underrun */ + +/* wtx_fields option bits for IP/TCP/UDP checksum offload */ +#define WTX_IXSM (1U << 0) /* IP checksum offload */ +#define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ + +/* Maximum payload per Tx descriptor */ +#define WTX_MAX_LEN 4096 + +/* + * The Livengood TCP/IP context descriptor. + */ +struct livengood_tcpip_ctxdesc { + uint32_t tcpip_ipcs; /* IP checksum context */ + uint32_t tcpip_tucs; /* TCP/UDP checksum context */ + uint32_t tcpip_cmdlen; + uint32_t tcpip_seg; /* TCP segmentation context */ +}; + +/* commands for context descriptors */ +#define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ +#define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ +#define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ + +#define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ +#define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ +#define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ + +#define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ +#define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ +#define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ + +#define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) +#define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) +#define WTX_TCPIP_SEG_MSS(x) ((x) << 16) + +/* + * PCI config registers used by the Wiseman. + */ +#define WM_PCI_MMBA PCI_MAPREG_START +/* registers for FLASH access on ICH8 */ +#define WM_ICH8_FLASH 0x0014 + +/* + * Wiseman Control/Status Registers. + */ +#define WMREG_CTRL 0x0000 /* Device Control Register */ +#define CTRL_FD (1U << 0) /* full duplex */ +#define CTRL_BEM (1U << 1) /* big-endian mode */ +#define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ +#define CTRL_LRST (1U << 3) /* link reset */ +#define CTRL_ASDE (1U << 5) /* auto speed detect enable */ +#define CTRL_SLU (1U << 6) /* set link up */ +#define CTRL_ILOS (1U << 7) /* invert loss of signal */ +#define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ +#define CTRL_SPEED_10 CTRL_SPEED(0) +#define CTRL_SPEED_100 CTRL_SPEED(1) +#define CTRL_SPEED_1000 CTRL_SPEED(2) +#define CTRL_SPEED_MASK CTRL_SPEED(3) +#define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ +#define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ +#define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ +#define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ +#define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ +#define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ +#define CTRL_SWDPINS_SHIFT 18 +#define CTRL_SWDPINS_MASK 0x0f +#define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) +#define CTRL_SWDPIO_SHIFT 22 +#define CTRL_SWDPIO_MASK 0x0f +#define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) +#define CTRL_RST (1U << 26) /* device reset */ +#define CTRL_RFCE (1U << 27) /* Rx flow control enable */ +#define CTRL_TFCE (1U << 28) /* Tx flow control enable */ +#define CTRL_VME (1U << 30) /* VLAN Mode Enable */ +#define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ + +#define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ + +#define WMREG_STATUS 0x0008 /* Device Status Register */ +#define STATUS_FD (1U << 0) /* full duplex */ +#define STATUS_LU (1U << 1) /* link up */ +#define STATUS_TCKOK (1U << 2) /* Tx clock running */ +#define STATUS_RBCOK (1U << 3) /* Rx clock running */ +#define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ +#define STATUS_FUNCID_MASK 3 /* ... */ +#define STATUS_TXOFF (1U << 4) /* Tx paused */ +#define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ +#define STATUS_SPEED(x) ((x) << 6) /* speed indication */ +#define STATUS_SPEED_10 STATUS_SPEED(0) +#define STATUS_SPEED_100 STATUS_SPEED(1) +#define STATUS_SPEED_1000 STATUS_SPEED(2) +#define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ +#define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ +#define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ +#define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ +#define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ +#define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ +#define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) +#define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) +#define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) +#define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) + +#define WMREG_EECD 0x0010 /* EEPROM Control Register */ +#define EECD_SK (1U << 0) /* clock */ +#define EECD_CS (1U << 1) /* chip select */ +#define EECD_DI (1U << 2) /* data in */ +#define EECD_DO (1U << 3) /* data out */ +#define EECD_FWE(x) ((x) << 4) /* flash write enable control */ +#define EECD_FWE_DISABLED EECD_FWE(1) +#define EECD_FWE_ENABLED EECD_FWE(2) +#define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ +#define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ +#define EECD_EE_PRES (1U << 8) /* EEPROM present */ +#define EECD_EE_SIZE (1U << 9) /* EEPROM size + (0 = 64 word, 1 = 256 word) */ +#define EECD_EE_AUTORD (1U << 9) /* auto read done */ +#define EECD_EE_ABITS (1U << 10) /* EEPROM address bits + (based on type) */ +#define EECD_EE_TYPE (1U << 13) /* EEPROM type + (0 = Microwire, 1 = SPI) */ +#define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ + +#define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ +#define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ +#define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ + +#define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ +#define SPI_OPC_READ 0x03 /* SPI "read" opcode */ +#define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ +#define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ +#define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ +#define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ +#define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ +#define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ + +#define SPI_SR_RDY 0x01 +#define SPI_SR_WEN 0x02 +#define SPI_SR_BP0 0x04 +#define SPI_SR_BP1 0x08 +#define SPI_SR_WPEN 0x80 + +#define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */ +#define EEPROM_OFF_CFG1 0x0a /* config word 1 */ +#define EEPROM_OFF_CFG2 0x0f /* config word 2 */ +#define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */ + +#define EEPROM_CFG1_LVDID (1U << 0) +#define EEPROM_CFG1_LSSID (1U << 1) +#define EEPROM_CFG1_PME_CLOCK (1U << 2) +#define EEPROM_CFG1_PM (1U << 3) +#define EEPROM_CFG1_ILOS (1U << 4) +#define EEPROM_CFG1_SWDPIO_SHIFT 5 +#define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT) +#define EEPROM_CFG1_IPS1 (1U << 8) +#define EEPROM_CFG1_LRST (1U << 9) +#define EEPROM_CFG1_FD (1U << 10) +#define EEPROM_CFG1_FRCSPD (1U << 11) +#define EEPROM_CFG1_IPS0 (1U << 12) +#define EEPROM_CFG1_64_32_BAR (1U << 13) + +#define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1) +#define EEPROM_CFG2_APM_EN (1U << 2) +#define EEPROM_CFG2_64_BIT (1U << 3) +#define EEPROM_CFG2_MAX_READ (1U << 4) +#define EEPROM_CFG2_DMCR_MAP (1U << 5) +#define EEPROM_CFG2_133_CAP (1U << 6) +#define EEPROM_CFG2_MSI_DIS (1U << 7) +#define EEPROM_CFG2_FLASH_DIS (1U << 8) +#define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) +#define EEPROM_CFG2_ANE (1U << 11) +#define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12) +#define EEPROM_CFG2_ASDE (1U << 14) +#define EEPROM_CFG2_APM_PME (1U << 15) +#define EEPROM_CFG2_SWDPIO_SHIFT 4 +#define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT) + +#define EEPROM_SWDPIN_MASK 0xdf +#define EEPROM_SWDPIN_SWDPIN_SHIFT 0 +#define EEPROM_SWDPIN_SWDPIO_SHIFT 8 + +#define WMREG_EERD 0x0014 /* EEPROM read */ +#define EERD_DONE 0x02 /* done bit */ +#define EERD_START 0x01 /* First bit for telling part to start operation */ +#define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ +#define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ + +#define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ +#define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ +#define CTRL_EXT_SWDPINS_SHIFT 4 +#define CTRL_EXT_SWDPINS_MASK 0x0d +#define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT + (x) - 4)) +#define CTRL_EXT_SWDPIO_SHIFT 8 +#define CTRL_EXT_SWDPIO_MASK 0x0d +#define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT + (x) - 4)) +#define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ +#define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ +#define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ +#define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ +#define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ +#define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ +#define CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define CTRL_EXT_LINK_MODE_GMII 0x00000000 +#define CTRL_EXT_LINK_MODE_TBI 0x00C00000 +#define CTRL_EXT_LINK_MODE_KMRN 0x00000000 +#define CTRL_EXT_LINK_MODE_SERDES 0x00C00000 + + +#define WMREG_MDIC 0x0020 /* MDI Control Register */ +#define MDIC_DATA(x) ((x) & 0xffff) +#define MDIC_REGADD(x) ((x) << 16) +#define MDIC_PHYADD(x) ((x) << 21) +#define MDIC_OP_WRITE (1U << 26) +#define MDIC_OP_READ (2U << 26) +#define MDIC_READY (1U << 28) +#define MDIC_I (1U << 29) /* interrupt on MDI complete */ +#define MDIC_E (1U << 30) /* MDI error */ + +#define WMREG_FCAL 0x0028 /* Flow Control Address Low */ +#define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ + +#define WMREG_FCAH 0x002c /* Flow Control Address High */ +#define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ + +#define WMREG_FCT 0x0030 /* Flow Control Type */ + +#define WMREG_VET 0x0038 /* VLAN Ethertype */ + +#define WMREG_RAL_BASE 0x0040 /* Receive Address List */ +#define WMREG_CORDOVA_RAL_BASE 0x5400 +#define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) +#define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) + /* + * Receive Address List: The LO part is the low-order 32-bits + * of the MAC address. The HI part is the high-order 16-bits + * along with a few control bits. + */ +#define RAL_AS(x) ((x) << 16) /* address select */ +#define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ +#define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ +#define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ +#define RAL_AV (1U << 31) /* entry is valid */ + +#define WM_RAL_TABSIZE 16 +#define WM_ICH8_RAL_TABSIZE 7 + +#define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ +#define ICR_TXDW (1U << 0) /* Tx desc written back */ +#define ICR_TXQE (1U << 1) /* Tx queue empty */ +#define ICR_LSC (1U << 2) /* link status change */ +#define ICR_RXSEQ (1U << 3) /* receive sequence error */ +#define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ +#define ICR_RXO (1U << 6) /* Rx overrun */ +#define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ +#define ICR_MDAC (1U << 9) /* MDIO access complete */ +#define ICR_RXCFG (1U << 10) /* Receiving /C/ */ +#define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ +#define ICR_INT (1U << 31) /* device generated an interrupt */ + +#define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ +#define ITR_IVAL_MASK 0xffff /* Interval mask */ +#define ITR_IVAL_SHIFT 0 /* Interval shift */ + +#define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ + /* See ICR bits. */ + +#define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ + /* See ICR bits. */ + +#define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ + /* See ICR bits. */ + +#define WMREG_RCTL 0x0100 /* Receive Control */ +#define RCTL_EN (1U << 1) /* receiver enable */ +#define RCTL_SBP (1U << 2) /* store bad packets */ +#define RCTL_UPE (1U << 3) /* unicast promisc. enable */ +#define RCTL_MPE (1U << 4) /* multicast promisc. enable */ +#define RCTL_LPE (1U << 5) /* large packet enable */ +#define RCTL_LBM(x) ((x) << 6) /* loopback mode */ +#define RCTL_LBM_NONE RCTL_LBM(0) +#define RCTL_LBM_PHY RCTL_LBM(3) +#define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ +#define RCTL_RDMTS_1_2 RCTL_RDMTS(0) +#define RCTL_RDMTS_1_4 RCTL_RDMTS(1) +#define RCTL_RDMTS_1_8 RCTL_RDMTS(2) +#define RCTL_RDMTS_MASK RCTL_RDMTS(3) +#define RCTL_MO(x) ((x) << 12) /* multicast offset */ +#define RCTL_BAM (1U << 15) /* broadcast accept mode */ +#define RCTL_2k (0 << 16) /* 2k Rx buffers */ +#define RCTL_1k (1 << 16) /* 1k Rx buffers */ +#define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ +#define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ +#define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ +#define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ +#define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ +#define RCTL_DPF (1U << 22) /* discard pause frames */ +#define RCTL_PMCF (1U << 23) /* pass MAC control frames */ +#define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ +#define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ + +#define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ +#define WMREG_RDTR 0x2820 +#define RDTR_FPD (1U << 31) /* flush partial descriptor */ + +#define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ + +#define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ +#define WMREG_RDBAL 0x2800 + +#define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ +#define WMREG_RDBAH 0x2804 + +#define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ +#define WMREG_RDLEN 0x2808 + +#define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ +#define WMREG_RDH 0x2810 + +#define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ +#define WMREG_RDT 0x2818 + +#define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */ +#define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ +#define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ +#define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ +#define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ + +#define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ + +#define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ + +#define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ + +#define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ + +#define WMREG_OLD_RDH1 0x0148 + +#define WMREG_OLD_RDT1 0x0150 + +#define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ +#define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ +#define FCRTH_DFLT 0x00008000 + +#define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ +#define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ +#define FCRTL_DFLT 0x00004000 +#define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + +#define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ +#define FCTTV_DFLT 0x00000600 + +#define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ + /* See MII ANAR_X bits. */ +#define TXCW_TxConfig (1U << 30) /* Tx Config */ +#define TXCW_ANE (1U << 31) /* Autonegotiate */ + +#define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ + /* See MII ANLPAR_X bits. */ +#define RXCW_NC (1U << 26) /* no carrier */ +#define RXCW_IV (1U << 27) /* config invalid */ +#define RXCW_CC (1U << 28) /* config change */ +#define RXCW_C (1U << 29) /* /C/ reception */ +#define RXCW_SYNCH (1U << 30) /* synchronized */ +#define RXCW_ANC (1U << 31) /* autonegotiation complete */ + +#define WMREG_MTA 0x0200 /* Multicast Table Array */ +#define WMREG_CORDOVA_MTA 0x5200 + +#define WMREG_TCTL 0x0400 /* Transmit Control Register */ +#define TCTL_EN (1U << 1) /* transmitter enable */ +#define TCTL_PSP (1U << 3) /* pad short packets */ +#define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ +#define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ +#define TCTL_SWXOFF (1U << 22) /* software XOFF */ +#define TCTL_RTLC (1U << 24) /* retransmit on late collision */ +#define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ +#define TCTL_MULR (1U << 28) /* multiple request */ + +#define TX_COLLISION_THRESHOLD 15 +#define TX_COLLISION_DISTANCE_HDX 512 +#define TX_COLLISION_DISTANCE_FDX 64 + +#define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ +#define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ +#define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ + +#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 + +#define WMREG_TQSA_LO 0x0408 + +#define WMREG_TQSA_HI 0x040c + +#define WMREG_TIPG 0x0410 /* Transmit IPG Register */ +#define TIPG_IPGT(x) (x) /* IPG transmit time */ +#define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ +#define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ + +#define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) +#define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) +#define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) +#define TIPG_1000T_80003_DFLT \ + (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) +#define TIPG_10_100_80003_DFLT \ + (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) + +#define WMREG_TQC 0x0418 + +#define WMREG_EEWR 0x102c /* EEPROM write */ + +#define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ + +#define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ + +#define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ + +#define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ + +#define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ + +#define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ + +#define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ + +#define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ + +#define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ + +#define WMREG_OLD_TBDAL 0x0420 /* Transmit Descriptor Base Lo */ +#define WMREG_TBDAL 0x3800 + +#define WMREG_OLD_TBDAH 0x0424 /* Transmit Descriptor Base Hi */ +#define WMREG_TBDAH 0x3804 + +#define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ +#define WMREG_TDLEN 0x3808 + +#define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ +#define WMREG_TDH 0x3810 + +#define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ +#define WMREG_TDT 0x3818 + +#define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ +#define WMREG_TIDV 0x3820 + +#define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */ +#define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ +#define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ +#define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ + +#define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ + +#define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ + +#define WMREG_VFTA 0x0600 + +#define WM_MC_TABSIZE 128 +#define WM_ICH8_MC_TABSIZE 32 +#define WM_VLAN_TABSIZE 128 + +#define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ +#define PBA_BYTE_SHIFT 10 /* KB -> bytes */ +#define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ +#define PBA_8K 0x0008 +#define PBA_12K 0x000c +#define PBA_16K 0x0010 /* 16K, default Tx allocation */ +#define PBA_22K 0x0016 +#define PBA_24K 0x0018 +#define PBA_30K 0x001e +#define PBA_32K 0x0020 +#define PBA_40K 0x0028 +#define PBA_48K 0x0030 /* 48K, default Rx allocation */ + +#define WMREG_PBS 0x1000 /* Packet Buffer Size (ICH8 only ?) */ + +#define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ +#define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ + +#define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum + Threshold (Cordova) */ +#define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ +#define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ + +#define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ +#define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ +#define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ +#define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ +#define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ + +#define WMREG_RXERRC 0x400C /* receive error Count - R/clr */ +#define WMREG_COLC 0x4028 /* collision Count - R/clr */ +#define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ +#define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ +#define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ +#define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ +#define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ + +#define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ +#define KUMCTRLSTA_MASK 0x0000FFFF +#define KUMCTRLSTA_OFFSET 0x001F0000 +#define KUMCTRLSTA_OFFSET_SHIFT 16 +#define KUMCTRLSTA_REN 0x00200000 + +#define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 +#define KUMCTRLSTA_OFFSET_CTRL 0x00000001 +#define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 +#define KUMCTRLSTA_OFFSET_DIAG 0x00000003 +#define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 +#define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 +#define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 +#define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E +#define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F + +/* FIFO Control */ +#define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 +#define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 + +/* In-Band Control */ +#define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 +#define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 + +/* Half-Duplex Control */ +#define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 +#define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 + +#define WMREG_MDPHYA 0x003C /* PHY address - RW */ + +#define WMREG_MANC2H 0x5860 /* Managment Control To Host - RW */ + +#define WMREG_SWSM 0x5b50 /* SW Semaphore */ +#define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +#define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ +#define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ + +#define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ +#define SWFW_EEP_SM 0x0001 /* eeprom access */ +#define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ +#define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ +#define SWFW_MAC_CSR_SM 0x0008 +#define SWFW_SOFT_SHIFT 0 /* software semaphores */ +#define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ + +#define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ +#define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 +#define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 +#define EXTCNFCTR_D_UD_ENABLE 0x00000004 +#define EXTCNFCTR_D_UD_LATENCY 0x00000008 +#define EXTCNFCTR_D_UD_OWNER 0x00000010 +#define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 +#define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 +#define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 +#define E1000_EXTCNF_CTRL_SWFLAG EXTCNFCTR_MDIO_SW_OWNERSHIP + +/* ich8 flash control */ +#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ +#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ +#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ +#define ICH_FLASH_SEG_SIZE_256 256 +#define ICH_FLASH_SEG_SIZE_4K 4096 +#define ICH_FLASH_SEG_SIZE_64K 65536 + +#define ICH_CYCLE_READ 0x0 +#define ICH_CYCLE_RESERVED 0x1 +#define ICH_CYCLE_WRITE 0x2 +#define ICH_CYCLE_ERASE 0x3 + +#define ICH_FLASH_GFPREG 0x0000 +#define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ +#define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ +#define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ +#define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ +#define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ +#define HSFSTS_ERSZ_SHIFT 3 +#define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ +#define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ +#define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ +#define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ +#define HSFCTL_GO 0x0001 /* Flash Cycle Go */ +#define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ +#define HSFCTL_CYCLE_SHIFT 1 +#define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ +#define HSFCTL_BCOUNT_SHIFT 8 +#define ICH_FLASH_FADDR 0x0008 +#define ICH_FLASH_FDATA0 0x0010 +#define ICH_FLASH_FRACC 0x0050 +#define ICH_FLASH_FREG0 0x0054 +#define ICH_FLASH_FREG1 0x0058 +#define ICH_FLASH_FREG2 0x005C +#define ICH_FLASH_FREG3 0x0060 +#define ICH_FLASH_FPR0 0x0074 +#define ICH_FLASH_FPR1 0x0078 +#define ICH_FLASH_SSFSTS 0x0090 +#define ICH_FLASH_SSFCTL 0x0092 +#define ICH_FLASH_PREOP 0x0094 +#define ICH_FLASH_OPTYPE 0x0096 +#define ICH_FLASH_OPMENU 0x0098 + +#define ICH_FLASH_REG_MAPSIZE 0x00A0 +#define ICH_FLASH_SECTOR_SIZE 4096 +#define ICH_GFPREG_BASE_MASK 0x1FFF +#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF + +/* start of Kate Feng added */ +#define WMREG_GPTC 0x4080 /* Good packets transmitted count */ +#define WMREG_GPRC 0x4074 /* Good packets received count */ +#define WMREG_CRCERRS 0x4000 /* CRC Error Count */ +#define WMREG_RLEC 0x4040 /* Receive Length Error Count */ +/* end of Kate Feng added */ diff --git a/bsps/powerpc/mvme5500/include/bsp/irq.h b/bsps/powerpc/mvme5500/include/bsp/irq.h new file mode 100644 index 0000000000..6704c2f626 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/irq.h @@ -0,0 +1,137 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Copyright 2004, 2005 Brookhaven National Laboratory and + * Shuchen Kate Feng <feng1@bnl.gov> + * + * - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC) + * - Discovery GT64260 interrupt controller instead of 8259. + * - Added support for software IRQ priority levels. + * - modified to optimize the IRQ latency and handling + */ + +#ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H +#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 +#include <rtems/irq.h> + +#ifndef ASM + +#define OneTierIrqPrioTbl 1 + +/* + * Symbolic IRQ names and related definitions. + */ + +/* leave the ISA symbols in there, so we can reuse shared/irq.c + * Also, we start numbering PCI irqs at 16 because the OPENPIC + * driver relies on this when mapping irq number <-> vectors + * (OPENPIC_VEC_SOURCE in openpic.h) + */ + + /* See section 25.2 , Table 734 of GT64260 controller + * Main Interrupt Cause Low register + */ +#define BSP_MICL_IRQ_NUMBER (32) +#define BSP_MICL_IRQ_LOWEST_OFFSET (0) +#define BSP_MICL_IRQ_MAX_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1) + /* + * Main Interrupt Cause High register + */ +#define BSP_MICH_IRQ_NUMBER (32) +#define BSP_MICH_IRQ_LOWEST_OFFSET (BSP_MICL_IRQ_MAX_OFFSET+1) +#define BSP_MICH_IRQ_MAX_OFFSET (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1) + /* External GPP Interrupt assignements + */ +#define BSP_GPP_IRQ_NUMBER (32) +#define BSP_GPP_IRQ_LOWEST_OFFSET (BSP_MICH_IRQ_MAX_OFFSET+1) +#define BSP_GPP_IRQ_MAX_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1) + + /* + * PowerPc exceptions handled as interrupt where a rtems managed interrupt + * handler might be connected + */ +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) + + /* allow a couple of vectors for VME and counter/timer irq sources etc. + * This is probably not needed any more. + */ +#define BSP_MISC_IRQ_NUMBER (30) +#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) + + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) +#define BSP_MAIN_IRQ_NUMBER (64) +#define BSP_PIC_IRQ_NUMBER (96) +#define BSP_LOWEST_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) + + /* Main CPU interrupt cause (Low) */ +#define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8) +#define BSP_MAIN_PCI0_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+12) +#define BSP_MAIN_PCI0_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+13) +#define BSP_MAIN_PCI0_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+14) +#define BSP_MAIN_PCI0_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+15) +#define BSP_MAIN_PCI1_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+16) +#define BSP_MAIN_PCI1_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+18) +#define BSP_MAIN_PCI1_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+19) +#define BSP_MAIN_PCI1_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+20) + + + /* Main CPU interrupt cause (High) */ +#define BSP_MAIN_ETH0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET) +#define BSP_MAIN_ETH1_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+1) +#define BSP_MAIN_ETH2_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+2) +#define BSP_MAIN_GPP7_0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+24) +#define BSP_MAIN_GPP15_8_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+25) +#define BSP_MAIN_GPP23_16_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+26) +#define BSP_MAIN_GPP31_24_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+27) + + /* on the MVME5500, these are the GT64260B external GPP0 interrupt */ +#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET) +#define BSP_UART_COM2_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) +#define BSP_UART_COM1_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) +#define BSP_GPP8_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+8) +#define BSP_GPP_PMC1_INTA (BSP_GPP8_IRQ_OFFSET) +#define BSP_GPP16_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+16) +#define BSP_GPP24_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+24) +#define BSP_GPP_VME_VLINT0 (BSP_GPP_IRQ_LOWEST_OFFSET+12) +#define BSP_GPP_VME_VLINT1 (BSP_GPP_IRQ_LOWEST_OFFSET+13) +#define BSP_GPP_VME_VLINT2 (BSP_GPP_IRQ_LOWEST_OFFSET+14) +#define BSP_GPP_VME_VLINT3 (BSP_GPP_IRQ_LOWEST_OFFSET+15) +#define BSP_GPP_PMC2_INTA (BSP_GPP_IRQ_LOWEST_OFFSET+16) +#define BSP_GPP_82544_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+20) +#define BSP_GPP_WDT_NMI_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+24) +#define BSP_GPP_WDT_EXP_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+25) + + /* + * Some Processor execption handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +extern void BSP_rtems_irq_mng_init(unsigned cpuId); + +#include <bsp/irq_supp.h> + +#endif +#endif diff --git a/bsps/powerpc/mvme5500/include/bsp/pcireg.h b/bsps/powerpc/mvme5500/include/bsp/pcireg.h new file mode 100644 index 0000000000..2b8b10d853 --- /dev/null +++ b/bsps/powerpc/mvme5500/include/bsp/pcireg.h @@ -0,0 +1,386 @@ +/* $NetBSD: pcireg.h,v 1.44 2003/12/02 16:31:06 briggs Exp $ */ + +/* + * Copyright (c) 1995, 1996, 1999, 2000 + * Christopher G. Demetriou. All rights reserved. + * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. + * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Charles M. Hannum. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include <bsp.h> + +/* + * PCI Class and Revision Register; defines type and revision of device. + */ +#define PCI_CLASS_REG 0x08 + +#define PCI_CLASS_SHIFT 24 +#define PCI_CLASS_MASK 0xff +#define PCI_CLASS(cr) \ + (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) + +#define PCI_SUBCLASS_SHIFT 16 +#define PCI_SUBCLASS_MASK 0xff +#define PCI_SUBCLASS(cr) \ + (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) + +#define PCI_INTERFACE_SHIFT 8 +#define PCI_INTERFACE_MASK 0xff +#define PCI_INTERFACE(cr) \ + (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) + +#define PCI_REVISION_SHIFT 0 +#define PCI_REVISION_MASK 0xff +#define PCI_REVISION(cr) \ + (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) + +#define PCI_CLASS_CODE(mainclass, subclass, interface) \ + ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \ + (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \ + (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT)) + +/* base classes */ +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_CLASS_MASS_STORAGE 0x01 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MEMORY 0x05 +#define PCI_CLASS_BRIDGE 0x06 +#define PCI_CLASS_COMMUNICATIONS 0x07 +#define PCI_CLASS_SYSTEM 0x08 +#define PCI_CLASS_INPUT 0x09 +#define PCI_CLASS_DOCK 0x0a +#define PCI_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_SERIALBUS 0x0c +#define PCI_CLASS_WIRELESS 0x0d +#define PCI_CLASS_I2O 0x0e +#define PCI_CLASS_SATCOM 0x0f +#define PCI_CLASS_CRYPTO 0x10 +#define PCI_CLASS_DASP 0x11 +#define PCI_CLASS_UNDEFINED 0xff + +/* 0x00 prehistoric subclasses */ +#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 + +/* 0x01 mass storage subclasses */ +#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 +#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 +#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 +#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 +#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 +#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 +#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 +#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 + +/* 0x02 network subclasses */ +#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 +#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 +#define PCI_SUBCLASS_NETWORK_FDDI 0x02 +#define PCI_SUBCLASS_NETWORK_ATM 0x03 +#define PCI_SUBCLASS_NETWORK_ISDN 0x04 +#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 +#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 +#define PCI_SUBCLASS_NETWORK_MISC 0x80 + +/* 0x03 display subclasses */ +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_3D 0x02 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 + +/* 0x04 multimedia subclasses */ +#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 +#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 +#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 +#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 + +/* 0x05 memory subclasses */ +#define PCI_SUBCLASS_MEMORY_RAM 0x00 +#define PCI_SUBCLASS_MEMORY_FLASH 0x01 +#define PCI_SUBCLASS_MEMORY_MISC 0x80 + +/* 0x06 bridge subclasses */ +#define PCI_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ +#define PCI_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 +#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 +#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 +#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 +#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a +#define PCI_SUBCLASS_BRIDGE_MISC 0x80 + +/* 0x07 communications subclasses */ +#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 +#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 +#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 +#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 +#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 +#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 +#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 + +/* 0x08 system subclasses */ +#define PCI_SUBCLASS_SYSTEM_PIC 0x00 +#define PCI_SUBCLASS_SYSTEM_DMA 0x01 +#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 +#define PCI_SUBCLASS_SYSTEM_RTC 0x03 +#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 +#define PCI_SUBCLASS_SYSTEM_MISC 0x80 + +/* 0x09 input subclasses */ +#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 +#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 +#define PCI_SUBCLASS_INPUT_MOUSE 0x02 +#define PCI_SUBCLASS_INPUT_SCANNER 0x03 +#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 +#define PCI_SUBCLASS_INPUT_MISC 0x80 + +/* 0x0a dock subclasses */ +#define PCI_SUBCLASS_DOCK_GENERIC 0x00 +#define PCI_SUBCLASS_DOCK_MISC 0x80 + +/* 0x0b processor subclasses */ +#define PCI_SUBCLASS_PROCESSOR_386 0x00 +#define PCI_SUBCLASS_PROCESSOR_486 0x01 +#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 +#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 +#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 +#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 +#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 + +/* 0x0c serial bus subclasses */ +#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 +#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 +#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 +#define PCI_SUBCLASS_SERIALBUS_USB 0x03 +#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ +#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 +#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 +#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 +#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 +#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 + +/* 0x0d wireless subclasses */ +#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 +#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 +#define PCI_SUBCLASS_WIRELESS_RF 0x10 +#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 +#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 +#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 +#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 +#define PCI_SUBCLASS_WIRELESS_MISC 0x80 + +/* 0x0e I2O (Intelligent I/O) subclasses */ +#define PCI_SUBCLASS_I2O_STANDARD 0x00 + +/* 0x0f satellite communication subclasses */ +/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ +#define PCI_SUBCLASS_SATCOM_TV 0x01 +#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 +#define PCI_SUBCLASS_SATCOM_VOICE 0x03 +#define PCI_SUBCLASS_SATCOM_DATA 0x04 + +/* 0x10 encryption/decryption subclasses */ +#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 +#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 +#define PCI_SUBCLASS_CRYPTO_MISC 0x80 + +/* 0x11 data acquisition and signal processing subclasses */ +#define PCI_SUBCLASS_DASP_DPIO 0x00 +#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 +#define PCI_SUBCLASS_DASP_SYNC 0x10 +#define PCI_SUBCLASS_DASP_MGMT 0x20 +#define PCI_SUBCLASS_DASP_MISC 0x80 + +/* + * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. + */ +#define PCI_BHLC_REG 0x0c + +#define PCI_BIST_SHIFT 24 +#define PCI_BIST_MASK 0xff +#define PCI_BIST(bhlcr) \ + (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) + +#define PCI_HDRTYPE_SHIFT 16 +#define PCI_HDRTYPE_MASK 0xff +#define PCI_HDRTYPE(bhlcr) \ + (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) + +#define PCI_HDRTYPE_TYPE(bhlcr) \ + (PCI_HDRTYPE(bhlcr) & 0x7f) +#define PCI_HDRTYPE_MULTIFN(bhlcr) \ + ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) + +#define PCI_LATTIMER_SHIFT 8 +#define PCI_LATTIMER_MASK 0xff +#define PCI_LATTIMER(bhlcr) \ + (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) + +#define PCI_CACHELINE_SHIFT 0 +#define PCI_CACHELINE_MASK 0xff +#define PCI_CACHELINE(bhlcr) \ + (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) + +#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \ + ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \ + (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \ + (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \ + (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \ + (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT)) + +/* + * PCI header type + */ +#define PCI_HDRTYPE_DEVICE 0 +#define PCI_HDRTYPE_PPB 1 +#define PCI_HDRTYPE_PCB 2 + +/* + * Mapping registers + */ +#define PCI_MAPREG_START 0x10 +#define PCI_MAPREG_END 0x28 +#define PCI_MAPREG_ROM 0x30 +#define PCI_MAPREG_PPB_END 0x18 +#define PCI_MAPREG_PCB_END 0x14 + +#define PCI_MAPREG_TYPE(mr) \ + ((mr) & PCI_MAPREG_TYPE_MASK) +#define PCI_MAPREG_TYPE_MASK 0x00000001 + +#define PCI_MAPREG_TYPE_MEM 0x00000000 +#define PCI_MAPREG_TYPE_IO 0x00000001 +#define PCI_MAPREG_ROM_ENABLE 0x00000001 + +#define PCI_MAPREG_MEM_TYPE(mr) \ + ((mr) & PCI_MAPREG_MEM_TYPE_MASK) +#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 + +#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 +#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 +#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 + +#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ + (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) +#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 + +#define PCI_MAPREG_MEM_ADDR(mr) \ + ((mr) & PCI_MAPREG_MEM_ADDR_MASK) +#define PCI_MAPREG_MEM_SIZE(mr) \ + (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) +#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 + +#define PCI_MAPREG_MEM64_ADDR(mr) \ + ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) +#define PCI_MAPREG_MEM64_SIZE(mr) \ + (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) +#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL + +#define PCI_MAPREG_IO_ADDR(mr) \ + ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK) +#define PCI_MAPREG_IO_SIZE(mr) \ + (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) +#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc + +#define PCI_MAPREG_SIZE_TO_MASK(size) \ + (-(size)) + +#define PCI_MAPREG_NUM(offset) \ + (((unsigned)(offset)-PCI_MAPREG_START)/4) + + +/* + * Cardbus CIS pointer (PCI rev. 2.1) + */ +#define PCI_CARDBUS_CIS_REG 0x28 + +/* + * Subsystem identification register; contains a vendor ID and a device ID. + * Types/macros for PCI_ID_REG apply. + * (PCI rev. 2.1) + */ +#define PCI_SUBSYS_ID_REG 0x2c + +/* + * capabilities link list (PCI rev. 2.2) + */ +#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ +#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ +#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) +#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) +#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) + +#define PCI_CAP_RESERVED0 0x00 +#define PCI_CAP_PWRMGMT 0x01 +#define PCI_CAP_AGP 0x02 +#define PCI_CAP_VPD 0x03 +#define PCI_CAP_SLOTID 0x04 +#define PCI_CAP_MSI 0x05 +#define PCI_CAP_CPCI_HOTSWAP 0x06 +#define PCI_CAP_PCIX 0x07 +#define PCI_CAP_LDT 0x08 +#define PCI_CAP_VENDSPEC 0x09 +#define PCI_CAP_DEBUGPORT 0x0a +#define PCI_CAP_CPCI_RSRCCTL 0x0b +#define PCI_CAP_HOTPLUG 0x0c +#define PCI_CAP_AGP8 0x0e +#define PCI_CAP_SECURE 0x0f +#define PCI_CAP_PCIEXPRESS 0x10 +#define PCI_CAP_MSIX 0x11 + +/* + * Vital Product Data; access via capability pointer (PCI rev 2.2). + */ +#define PCI_VPD_ADDRESS_MASK 0x7fff +#define PCI_VPD_ADDRESS_SHIFT 16 +#define PCI_VPD_ADDRESS(ofs) \ + (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) +#define PCI_VPD_DATAREG(ofs) ((ofs) + 4) +#define PCI_VPD_OPFLAG 0x80000000 + +/* + * Power Management Capability; access via capability pointer. + */ + +/* Power Management Capability Register */ +#define PCI_PMCR 0x02 +#define PCI_PMCR_D1SUPP 0x0200 +#define PCI_PMCR_D2SUPP 0x0400 +/* Power Management Control Status Register */ +#define PCI_PMCSR 0x04 +#define PCI_PMCSR_STATE_MASK 0x03 +#define PCI_PMCSR_STATE_D0 0x00 +#define PCI_PMCSR_STATE_D1 0x01 +#define PCI_PMCSR_STATE_D2 0x02 +#define PCI_PMCSR_STATE_D3 0x03 + diff --git a/bsps/powerpc/mvme5500/include/tm27.h b/bsps/powerpc/mvme5500/include/tm27.h new file mode 100644 index 0000000000..2a80618cfb --- /dev/null +++ b/bsps/powerpc/mvme5500/include/tm27.h @@ -0,0 +1,66 @@ +/* + * @file + * @ingroup powerpc_mvme5500 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <bsp/irq.h> + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; + +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + rtems_fatal_error_occurred(1); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 1; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/psim/headers.am b/bsps/powerpc/psim/headers.am new file mode 100644 index 0000000000..a1f49d3727 --- /dev/null +++ b/bsps/powerpc/psim/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/psim/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/psim/include/psim.h +include_HEADERS += ../../../../../../bsps/powerpc/psim/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/psim/include/bsp/irq.h diff --git a/bsps/powerpc/psim/include/bsp.h b/bsps/powerpc/psim/include/bsp.h new file mode 100644 index 0000000000..cffc9632e7 --- /dev/null +++ b/bsps/powerpc/psim/include/bsp.h @@ -0,0 +1,90 @@ +/* bsp.h + * + * This include file contains all Papyrus board IO definitions. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_PSIM_BSP_H +#define LIBBSP_POWERPC_PSIM_BSP_H + +#include <bspopts.h> + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include <rtems.h> +#include <libcpu/io.h> +#include <bsp/vectors.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Constants */ + +/* + * Information placed in the linkcmds file. + */ + +extern int end; /* last address in the program */ +extern int RAM_END; + +extern uint32_t BSP_mem_size; + +#define BSP_Convert_decrementer( _value ) ( (unsigned long long) _value ) + +/* macros */ +#define Processor_Synchronize() \ + __asm__ (" eieio ") + +/* + * Network configuration + */ +struct rtems_bsdnet_ifconfig; + +int rtems_ifsim_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "ifsim1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ifsim_attach + +/* + * Interfaces to required Clock Driver support methods + */ +int BSP_disconnect_clock_handler(void); +int BSP_connect_clock_handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#define BSP_HAS_NO_VME + +#endif diff --git a/bsps/powerpc/psim/include/bsp/irq.h b/bsps/powerpc/psim/include/bsp/irq.h new file mode 100644 index 0000000000..376c95a627 --- /dev/null +++ b/bsps/powerpc/psim/include/bsp/irq.h @@ -0,0 +1,74 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#ifndef ASM + +#include <rtems/irq.h> + + +/* + * Symblolic IRQ names and related definitions. + */ + +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +#define BSP_PCI_IRQ_NUMBER (16) +#define BSP_PCI_IRQ_LOWEST_OFFSET (0) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) + + + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + /* + * Some Processor execption handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +#include <bsp/irq_supp.h> + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +#ifdef __cplusplus +extern "C" { +#endif + +void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/bsps/powerpc/psim/include/psim.h b/bsps/powerpc/psim/include/psim.h new file mode 100644 index 0000000000..e7b6fa7578 --- /dev/null +++ b/bsps/powerpc/psim/include/psim.h @@ -0,0 +1,90 @@ +/* + * PSIM addresses and constants based upon the configuration + * of devices used in the script provided by RTEMS. + */ + +#ifndef __PSIM_h +#define __PSIM_h + +/* + * RAM Information + */ + +extern char RamBase[]; +extern char RamSize[]; + +/* + * RamBase/RamSize is defined by the linker script; + * CPP symbols are AFAIK unused and deprecated. + */ +#define PSIM_RAM_SIZE ((unsigned long)RamSize) +#define PSIM_RAM_BASE ((void*)RamBase) + +/* + * NVRAM/RTC Structure and Information + */ + +#define PSIM_RTC_FREEZE 0xc0 +#define PSIM_RTC_UPDATE 0x00 + +typedef struct { + volatile uint8_t Control; /* 0x04 */ + volatile uint8_t Second; /* 0x05 */ + volatile uint8_t Minute; /* 0x06 */ + volatile uint8_t Hour; /* 0x07 */ + volatile uint8_t Day; /* 0x08 */ + volatile uint8_t Date; /* 0x09 */ + volatile uint8_t Month; /* 0x0a */ + volatile uint8_t Year; /* 0x0b */ +} psim_rtc_t; + +/* + * System V IPC Semaphore -- Read Only + */ + +typedef struct { + volatile uint32_t obtain_value; /* 0x00 */ + volatile uint32_t lock; /* 0x04 */ + volatile uint32_t unlock; /* 0x08 */ +} psim_sysv_sem_t; + +typedef struct { + /* 0x0c000000 - 0x0c007FFF - AMD 29F040 */ + volatile uint8_t Flash[ 512 * 1024 ]; + + /* 0x0c080000 - 0x0c0FFFFF - NVRAM/NVRAM */ + volatile uint8_t nvram[ 512 * 1024 ]; + + /* 0x0c100000 - 0x0c100007 - NVRAM/RTC */ + psim_rtc_t RTC; + + /* 0x0c100008 - 0x0c10000F - NVRAM/RTC */ + uint8_t gap1[8]; + + /* 0x0c100010 - 0x0c10001b - System V IPC Semaphore */ + psim_sysv_sem_t Semaphore; + + /* 0x0c10001c - 0x0c10001f - NVRAM/RTC */ + uint8_t gap2[4]; + + /* 0x0c100020 - 0x0c10005F - Ethernet */ + volatile uint8_t Ethtap[ 64 ]; + + /* 0x0c100060 - 0x0c10FFFF - NVRAM/RTC */ + uint8_t gap3[65440]; + + /* 0x0c110000 - 0x0c12FFFF - System V IPC Shared Memory */ + uint8_t SharedMemory[ 128 * 1024 ]; + + /* 0x0c130000 - 0x0c170000 - OpenPIC IRQ Controller */ + volatile uint8_t OpenPIC[ 256 * 1024 ]; + +} psim_registers_t; + +/* + * Data Structure Overlay for Registers. See linkcmds for placement. + */ +extern psim_registers_t PSIM; + +#endif +/* end of include file */ diff --git a/bsps/powerpc/psim/include/tm27.h b/bsps/powerpc/psim/include/tm27.h new file mode 100644 index 0000000000..3a41283a13 --- /dev/null +++ b/bsps/powerpc/psim/include/tm27.h @@ -0,0 +1,66 @@ +/* + * @file + * @ingroup powerpc_psim + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <bsp/irq.h> + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +void nullFunc() {} +static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, + 0, + (rtems_irq_enable)nullFunc, + (rtems_irq_disable)nullFunc, + (rtems_irq_is_enabled) nullFunc}; + +void Install_tm27_vector(void (*_handler)()) +{ + clockIrqData.hdl = _handler; + if (!BSP_install_rtems_irq_handler (&clockIrqData)) { + printk("Error installing clock interrupt handler!\n"); + rtems_fatal_error_occurred(1); + } +} + +#define Cause_tm27_intr() \ + do { \ + uint32_t _clicks = 1; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + + +#define Clear_tm27_intr() \ + do { \ + uint32_t _clicks = 0xffffffff; \ + __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ + } while (0) + +#define Lower_tm27_intr() \ + do { \ + uint32_t _msr = 0; \ + _ISR_Set_level( 0 ); \ + __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + _msr |= 0x8002; \ + __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ + } while (0) + +#endif diff --git a/bsps/powerpc/qemuppc/headers.am b/bsps/powerpc/qemuppc/headers.am new file mode 100644 index 0000000000..21ab8382a5 --- /dev/null +++ b/bsps/powerpc/qemuppc/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/qemuppc/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/qemuppc/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qemuppc/include/bsp/irq.h diff --git a/bsps/powerpc/qemuppc/include/bsp.h b/bsps/powerpc/qemuppc/include/bsp.h new file mode 100644 index 0000000000..240cfd3bea --- /dev/null +++ b/bsps/powerpc/qemuppc/include/bsp.h @@ -0,0 +1,47 @@ +/* + * This include file contains some definitions specific to the + * qemu powerpc Prep simulator + */ + +/* + * COPYRIGHT (c) 1989-2014. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QEMUPPC_BSP_H +#define LIBBSP_POWERPC_QEMUPPC_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Convert decrementer value to tenths of microseconds (used by shared timer + * driver). + */ +#define BSP_Convert_decrementer( _value ) \ + ((int) (((_value) * 10) / bsp_clicks_per_usec)) + +/* + * Prototypes for methods that are referenced from .S + */ +void cmain(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/qemuppc/include/bsp/irq.h b/bsps/powerpc/qemuppc/include/bsp/irq.h new file mode 100644 index 0000000000..7124dbcaf8 --- /dev/null +++ b/bsps/powerpc/qemuppc/include/bsp/irq.h @@ -0,0 +1,76 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_IRQ_H +#define LIBBSP_POWERPC_IRQ_H + +#define BSP_SHARED_HANDLER_SUPPORT 1 + +#ifndef ASM + +#include <rtems/irq.h> + + +/* + * Symblolic IRQ names and related definitions. + */ + +/* + * PCI IRQ handlers related definitions + * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE + */ +/* FIXME: do we need PCI interrrupts here ? */ +#define BSP_PCI_IRQ_NUMBER (16) +#define BSP_PCI_IRQ_LOWEST_OFFSET (0) +#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) + +#define BSP_PROCESSOR_IRQ_NUMBER (1) +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) + + + /* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) +#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) +#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) + + /* + * Some Processor execption handled as rtems IRQ symbolic name definition + */ +#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +/* #include <bsp/irq_supp.h> */ + +#ifdef __cplusplus +extern "C" { +#endif + +void BSP_rtems_irq_mng_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/bsps/powerpc/qemuppc/include/tm27.h b/bsps/powerpc/qemuppc/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/qemuppc/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/qoriq/headers.am b/bsps/powerpc/qoriq/headers.am new file mode 100644 index 0000000000..9d23263d43 --- /dev/null +++ b/bsps/powerpc/qoriq/headers.am @@ -0,0 +1,24 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/tm27.h + +include_asmdir = $(includedir)/asm +include_asm_HEADERS = +include_asm_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/asm/epapr_hcalls.h +include_asm_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/asm/fsl_hcalls.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/intercom.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/mmu.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/qoriq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/tsec-config.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/bsp/uart-bridge.h + +include_uapi_asmdir = $(includedir)/uapi/asm +include_uapi_asm_HEADERS = +include_uapi_asm_HEADERS += ../../../../../../bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h diff --git a/bsps/powerpc/qoriq/include/asm/epapr_hcalls.h b/bsps/powerpc/qoriq/include/asm/epapr_hcalls.h new file mode 100644 index 0000000000..3d87cca611 --- /dev/null +++ b/bsps/powerpc/qoriq/include/asm/epapr_hcalls.h @@ -0,0 +1,573 @@ +/* + * ePAPR hcall interface + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * Author: Timur Tabi <timur@freescale.com> + * + * This file is provided under a dual BSD/GPL license. When using or + * redistributing this file, you may do so under either license. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* A "hypercall" is an "sc 1" instruction. This header file file provides C + * wrapper functions for the ePAPR hypervisor interface. It is inteded + * for use by Linux device drivers and other operating systems. + * + * The hypercalls are implemented as inline assembly, rather than assembly + * language functions in a .S file, for optimization. It allows + * the caller to issue the hypercall instruction directly, improving both + * performance and memory footprint. + */ + +#ifndef _EPAPR_HCALLS_H +#define _EPAPR_HCALLS_H + +#include <uapi/asm/epapr_hcalls.h> + +#ifndef __ASSEMBLY__ +#include <sys/endian.h> + +/* + * Hypercall register clobber list + * + * These macros are used to define the list of clobbered registers during a + * hypercall. Technically, registers r0 and r3-r12 are always clobbered, + * but the gcc inline assembly syntax does not allow us to specify registers + * on the clobber list that are also on the input/output list. Therefore, + * the lists of clobbered registers depends on the number of register + * parmeters ("+r" and "=r") passed to the hypercall. + * + * Each assembly block should use one of the HCALL_CLOBBERSx macros. As a + * general rule, 'x' is the number of parameters passed to the assembly + * block *except* for r11. + * + * If you're not sure, just use the smallest value of 'x' that does not + * generate a compilation error. Because these are static inline functions, + * the compiler will only check the clobber list for a function if you + * compile code that calls that function. + * + * r3 and r11 are not included in any clobbers list because they are always + * listed as output registers. + * + * XER, CTR, and LR are currently listed as clobbers because it's uncertain + * whether they will be clobbered. + * + * Note that r11 can be used as an output parameter. + * + * The "memory" clobber is only necessary for hcalls where the Hypervisor + * will read or write guest memory. However, we add it to all hcalls because + * the impact is minimal, and we want to ensure that it's present for the + * hcalls that need it. +*/ + +/* List of common clobbered registers. Do not use this macro. */ +#define EV_HCALL_CLOBBERS "r0", "r12", "xer", "ctr", "lr", "cc", "memory" + +#define EV_HCALL_CLOBBERS8 EV_HCALL_CLOBBERS +#define EV_HCALL_CLOBBERS7 EV_HCALL_CLOBBERS8, "r10" +#define EV_HCALL_CLOBBERS6 EV_HCALL_CLOBBERS7, "r9" +#define EV_HCALL_CLOBBERS5 EV_HCALL_CLOBBERS6, "r8" +#define EV_HCALL_CLOBBERS4 EV_HCALL_CLOBBERS5, "r7" +#define EV_HCALL_CLOBBERS3 EV_HCALL_CLOBBERS4, "r6" +#define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5" +#define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4" + +extern bool epapr_paravirt_enabled; +extern uint32_t epapr_hypercall_start[]; + +#ifdef CONFIG_EPAPR_PARAVIRT +int __init epapr_paravirt_early_init(void); +#else +static inline int epapr_paravirt_early_init(void) { return 0; } +#endif + +/* + * We use "uintptr_t" to define a register because it's guaranteed to be a + * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit + * platform. + * + * All registers are either input/output or output only. Registers that are + * initialized before making the hypercall are input/output. All + * input/output registers are represented with "+r". Output-only registers + * are represented with "=r". Do not specify any unused registers. The + * clobber list will tell the compiler that the hypercall modifies those + * registers, which is good enough. + */ + +/** + * ev_int_set_config - configure the specified interrupt + * @interrupt: the interrupt number + * @config: configuration for this interrupt + * @priority: interrupt priority + * @destination: destination CPU number + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_set_config(unsigned int interrupt, + uint32_t config, unsigned int priority, uint32_t destination) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + + r11 = EV_HCALL_TOKEN(EV_INT_SET_CONFIG); + r3 = interrupt; + r4 = config; + r5 = priority; + r6 = destination; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6) + : : EV_HCALL_CLOBBERS4 + ); + + return r3; +} + +/** + * ev_int_get_config - return the config of the specified interrupt + * @interrupt: the interrupt number + * @config: returned configuration for this interrupt + * @priority: returned interrupt priority + * @destination: returned destination CPU number + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_get_config(unsigned int interrupt, + uint32_t *config, unsigned int *priority, uint32_t *destination) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + + r11 = EV_HCALL_TOKEN(EV_INT_GET_CONFIG); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5), "=r" (r6) + : : EV_HCALL_CLOBBERS4 + ); + + *config = r4; + *priority = r5; + *destination = r6; + + return r3; +} + +/** + * ev_int_set_mask - sets the mask for the specified interrupt source + * @interrupt: the interrupt number + * @mask: 0=enable interrupts, 1=disable interrupts + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_set_mask(unsigned int interrupt, + unsigned int mask) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = EV_HCALL_TOKEN(EV_INT_SET_MASK); + r3 = interrupt; + r4 = mask; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + return r3; +} + +/** + * ev_int_get_mask - returns the mask for the specified interrupt source + * @interrupt: the interrupt number + * @mask: returned mask for this interrupt (0=enabled, 1=disabled) + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_get_mask(unsigned int interrupt, + unsigned int *mask) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = EV_HCALL_TOKEN(EV_INT_GET_MASK); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *mask = r4; + + return r3; +} + +/** + * ev_int_eoi - signal the end of interrupt processing + * @interrupt: the interrupt number + * + * This function signals the end of processing for the the specified + * interrupt, which must be the interrupt currently in service. By + * definition, this is also the highest-priority interrupt. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_eoi(unsigned int interrupt) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = EV_HCALL_TOKEN(EV_INT_EOI); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * ev_byte_channel_send - send characters to a byte stream + * @handle: byte stream handle + * @count: (input) num of chars to send, (output) num chars sent + * @buffer: pointer to a 16-byte buffer + * + * @buffer must be at least 16 bytes long, because all 16 bytes will be + * read from memory into registers, even if count < 16. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_byte_channel_send(unsigned int handle, + unsigned int *count, const char buffer[EV_BYTE_CHANNEL_MAX_BYTES]) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r8 __asm__("r8"); + const uint32_t *p = (const uint32_t *) buffer; + + r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_SEND); + r3 = handle; + r4 = *count; + r5 = be32toh(p[0]); + r6 = be32toh(p[1]); + r7 = be32toh(p[2]); + r8 = be32toh(p[3]); + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), + "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), "+r" (r8) + : : EV_HCALL_CLOBBERS6 + ); + + *count = r4; + + return r3; +} + +/** + * ev_byte_channel_receive - fetch characters from a byte channel + * @handle: byte channel handle + * @count: (input) max num of chars to receive, (output) num chars received + * @buffer: pointer to a 16-byte buffer + * + * The size of @buffer must be at least 16 bytes, even if you request fewer + * than 16 characters, because we always write 16 bytes to @buffer. This is + * for performance reasons. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_byte_channel_receive(unsigned int handle, + unsigned int *count, char buffer[EV_BYTE_CHANNEL_MAX_BYTES]) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r8 __asm__("r8"); + uint32_t *p = (uint32_t *) buffer; + + r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_RECEIVE); + r3 = handle; + r4 = *count; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), + "=r" (r5), "=r" (r6), "=r" (r7), "=r" (r8) + : : EV_HCALL_CLOBBERS6 + ); + + *count = r4; + p[0] = htobe32(r5); + p[1] = htobe32(r6); + p[2] = htobe32(r7); + p[3] = htobe32(r8); + + return r3; +} + +/** + * ev_byte_channel_poll - returns the status of the byte channel buffers + * @handle: byte channel handle + * @rx_count: returned count of bytes in receive queue + * @tx_count: returned count of free space in transmit queue + * + * This function reports the amount of data in the receive queue (i.e. the + * number of bytes you can read), and the amount of free space in the transmit + * queue (i.e. the number of bytes you can write). + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_byte_channel_poll(unsigned int handle, + unsigned int *rx_count, unsigned int *tx_count) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + + r11 = EV_HCALL_TOKEN(EV_BYTE_CHANNEL_POLL); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4), "=r" (r5) + : : EV_HCALL_CLOBBERS3 + ); + + *rx_count = r4; + *tx_count = r5; + + return r3; +} + +/** + * ev_int_iack - acknowledge an interrupt + * @handle: handle to the target interrupt controller + * @vector: returned interrupt vector + * + * If handle is zero, the function returns the next interrupt source + * number to be handled irrespective of the hierarchy or cascading + * of interrupt controllers. If non-zero, specifies a handle to the + * interrupt controller that is the target of the acknowledge. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_int_iack(unsigned int handle, + unsigned int *vector) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = EV_HCALL_TOKEN(EV_INT_IACK); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *vector = r4; + + return r3; +} + +/** + * ev_doorbell_send - send a doorbell to another partition + * @handle: doorbell send handle + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_doorbell_send(unsigned int handle) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = EV_HCALL_TOKEN(EV_DOORBELL_SEND); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * ev_idle -- wait for next interrupt on this core + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int ev_idle(void) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = EV_HCALL_TOKEN(EV_IDLE); + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "=r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +#ifdef CONFIG_EPAPR_PARAVIRT +static inline unsigned long epapr_hypercall(unsigned long *in, + unsigned long *out, + unsigned long nr) +{ + unsigned long register r0 asm("r0"); + unsigned long register r3 asm("r3") = in[0]; + unsigned long register r4 asm("r4") = in[1]; + unsigned long register r5 asm("r5") = in[2]; + unsigned long register r6 asm("r6") = in[3]; + unsigned long register r7 asm("r7") = in[4]; + unsigned long register r8 asm("r8") = in[5]; + unsigned long register r9 asm("r9") = in[6]; + unsigned long register r10 asm("r10") = in[7]; + unsigned long register r11 asm("r11") = nr; + unsigned long register r12 asm("r12"); + + asm volatile("bl epapr_hypercall_start" + : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6), + "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11), + "=r"(r12) + : "r"(r3), "r"(r4), "r"(r5), "r"(r6), "r"(r7), "r"(r8), + "r"(r9), "r"(r10), "r"(r11) + : "memory", "cc", "xer", "ctr", "lr"); + + out[0] = r4; + out[1] = r5; + out[2] = r6; + out[3] = r7; + out[4] = r8; + out[5] = r9; + out[6] = r10; + out[7] = r11; + + return r3; +} +#else +static unsigned long epapr_hypercall(unsigned long *in, + unsigned long *out, + unsigned long nr) +{ + return EV_UNIMPLEMENTED; +} +#endif + +static inline long epapr_hypercall0_1(unsigned int nr, unsigned long *r2) +{ + unsigned long in[8]; + unsigned long out[8]; + unsigned long r; + + r = epapr_hypercall(in, out, nr); + *r2 = out[0]; + + return r; +} + +static inline long epapr_hypercall0(unsigned int nr) +{ + unsigned long in[8]; + unsigned long out[8]; + + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall1(unsigned int nr, unsigned long p1) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall2(unsigned int nr, unsigned long p1, + unsigned long p2) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + in[1] = p2; + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall3(unsigned int nr, unsigned long p1, + unsigned long p2, unsigned long p3) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + in[1] = p2; + in[2] = p3; + return epapr_hypercall(in, out, nr); +} + +static inline long epapr_hypercall4(unsigned int nr, unsigned long p1, + unsigned long p2, unsigned long p3, + unsigned long p4) +{ + unsigned long in[8]; + unsigned long out[8]; + + in[0] = p1; + in[1] = p2; + in[2] = p3; + in[3] = p4; + return epapr_hypercall(in, out, nr); +} +#endif /* !__ASSEMBLY__ */ +#endif /* _EPAPR_HCALLS_H */ diff --git a/bsps/powerpc/qoriq/include/asm/fsl_hcalls.h b/bsps/powerpc/qoriq/include/asm/fsl_hcalls.h new file mode 100644 index 0000000000..ba76c132aa --- /dev/null +++ b/bsps/powerpc/qoriq/include/asm/fsl_hcalls.h @@ -0,0 +1,653 @@ +/* + * Freescale hypervisor call interface + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Author: Timur Tabi <timur@freescale.com> + * + * This file is provided under a dual BSD/GPL license. When using or + * redistributing this file, you may do so under either license. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_HCALLS_H +#define _FSL_HCALLS_H + +#include <stdint.h> +#include <asm/epapr_hcalls.h> + +#define FH_API_VERSION 1 + +#define FH_ERR_GET_INFO 1 +#define FH_PARTITION_GET_DTPROP 2 +#define FH_PARTITION_SET_DTPROP 3 +#define FH_PARTITION_RESTART 4 +#define FH_PARTITION_GET_STATUS 5 +#define FH_PARTITION_START 6 +#define FH_PARTITION_STOP 7 +#define FH_PARTITION_MEMCPY 8 +#define FH_DMA_ENABLE 9 +#define FH_DMA_DISABLE 10 +#define FH_SEND_NMI 11 +#define FH_VMPIC_GET_MSIR 12 +#define FH_SYSTEM_RESET 13 +#define FH_GET_CORE_STATE 14 +#define FH_ENTER_NAP 15 +#define FH_EXIT_NAP 16 +#define FH_CLAIM_DEVICE 17 +#define FH_PARTITION_STOP_DMA 18 + +/* vendor ID: Freescale Semiconductor */ +#define FH_HCALL_TOKEN(num) _EV_HCALL_TOKEN(EV_FSL_VENDOR_ID, num) + +/* + * We use "uintptr_t" to define a register because it's guaranteed to be a + * 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit + * platform. + * + * All registers are either input/output or output only. Registers that are + * initialized before making the hypercall are input/output. All + * input/output registers are represented with "+r". Output-only registers + * are represented with "=r". Do not specify any unused registers. The + * clobber list will tell the compiler that the hypercall modifies those + * registers, which is good enough. + */ + +/** + * fh_send_nmi - send NMI to virtual cpu(s). + * @vcpu_mask: send NMI to virtual cpu(s) specified by this mask. + * + * Returns 0 for success, or EINVAL for invalid vcpu_mask. + */ +static inline unsigned int fh_send_nmi(unsigned int vcpu_mask) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_SEND_NMI); + r3 = vcpu_mask; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/* Arbitrary limits to avoid excessive memory allocation in hypervisor */ +#define FH_DTPROP_MAX_PATHLEN 4096 +#define FH_DTPROP_MAX_PROPLEN 32768 + +/** + * fh_partition_get_dtprop - get a property from a guest device tree. + * @handle: handle of partition whose device tree is to be accessed + * @dtpath_addr: physical address of device tree path to access + * @propname_addr: physical address of name of property + * @propvalue_addr: physical address of property value buffer + * @propvalue_len: length of buffer on entry, length of property on return + * + * Returns zero on success, non-zero on error. + */ +static inline unsigned int fh_partition_get_dtprop(int handle, + uint64_t dtpath_addr, + uint64_t propname_addr, + uint64_t propvalue_addr, + uint32_t *propvalue_len) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r8 __asm__("r8"); + register uintptr_t r9 __asm__("r9"); + register uintptr_t r10 __asm__("r10"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_DTPROP); + r3 = handle; + +#ifdef CONFIG_PHYS_64BIT + r4 = dtpath_addr >> 32; + r6 = propname_addr >> 32; + r8 = propvalue_addr >> 32; +#else + r4 = 0; + r6 = 0; + r8 = 0; +#endif + r5 = (uint32_t)dtpath_addr; + r7 = (uint32_t)propname_addr; + r9 = (uint32_t)propvalue_addr; + r10 = *propvalue_len; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), + "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), + "+r" (r8), "+r" (r9), "+r" (r10) + : : EV_HCALL_CLOBBERS8 + ); + + *propvalue_len = r4; + return r3; +} + +/** + * Set a property in a guest device tree. + * @handle: handle of partition whose device tree is to be accessed + * @dtpath_addr: physical address of device tree path to access + * @propname_addr: physical address of name of property + * @propvalue_addr: physical address of property value + * @propvalue_len: length of property + * + * Returns zero on success, non-zero on error. + */ +static inline unsigned int fh_partition_set_dtprop(int handle, + uint64_t dtpath_addr, + uint64_t propname_addr, + uint64_t propvalue_addr, + uint32_t propvalue_len) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r8 __asm__("r8"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r7 __asm__("r7"); + register uintptr_t r9 __asm__("r9"); + register uintptr_t r10 __asm__("r10"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_SET_DTPROP); + r3 = handle; + +#ifdef CONFIG_PHYS_64BIT + r4 = dtpath_addr >> 32; + r6 = propname_addr >> 32; + r8 = propvalue_addr >> 32; +#else + r4 = 0; + r6 = 0; + r8 = 0; +#endif + r5 = (uint32_t)dtpath_addr; + r7 = (uint32_t)propname_addr; + r9 = (uint32_t)propvalue_addr; + r10 = propvalue_len; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), + "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7), + "+r" (r8), "+r" (r9), "+r" (r10) + : : EV_HCALL_CLOBBERS8 + ); + + return r3; +} + +/** + * fh_partition_restart - reboot the current partition + * @partition: partition ID + * + * Returns an error code if reboot failed. Does not return if it succeeds. + */ +static inline unsigned int fh_partition_restart(unsigned int partition) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_RESTART); + r3 = partition; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +#define FH_PARTITION_STOPPED 0 +#define FH_PARTITION_RUNNING 1 +#define FH_PARTITION_STARTING 2 +#define FH_PARTITION_STOPPING 3 +#define FH_PARTITION_PAUSING 4 +#define FH_PARTITION_PAUSED 5 +#define FH_PARTITION_RESUMING 6 + +/** + * fh_partition_get_status - gets the status of a partition + * @partition: partition ID + * @status: returned status code + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_get_status(unsigned int partition, + unsigned int *status) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_GET_STATUS); + r3 = partition; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *status = r4; + + return r3; +} + +/** + * fh_partition_start - boots and starts execution of the specified partition + * @partition: partition ID + * @entry_point: guest physical address to start execution + * + * The hypervisor creates a 1-to-1 virtual/physical IMA mapping, so at boot + * time, guest physical address are the same as guest virtual addresses. + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_start(unsigned int partition, + uint32_t entry_point, int load) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_START); + r3 = partition; + r4 = entry_point; + r5 = load; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5) + : : EV_HCALL_CLOBBERS3 + ); + + return r3; +} + +/** + * fh_partition_stop - stops another partition + * @partition: partition ID + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_stop(unsigned int partition) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP); + r3 = partition; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * struct fh_sg_list: definition of the fh_partition_memcpy S/G list + * @source: guest physical address to copy from + * @target: guest physical address to copy to + * @size: number of bytes to copy + * @reserved: reserved, must be zero + * + * The scatter/gather list for fh_partition_memcpy() is an array of these + * structures. The array must be guest physically contiguous. + * + * This structure must be aligned on 32-byte boundary, so that no single + * strucuture can span two pages. + */ +struct fh_sg_list { + uint64_t source; /**< guest physical address to copy from */ + uint64_t target; /**< guest physical address to copy to */ + uint64_t size; /**< number of bytes to copy */ + uint64_t reserved; /**< reserved, must be zero */ +} __attribute__ ((aligned(32))); + +/** + * fh_partition_memcpy - copies data from one guest to another + * @source: the ID of the partition to copy from + * @target: the ID of the partition to copy to + * @sg_list: guest physical address of an array of &fh_sg_list structures + * @count: the number of entries in @sg_list + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_memcpy(unsigned int source, + unsigned int target, uint64_t sg_list, unsigned int count) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_MEMCPY); + r3 = source; + r4 = target; + r5 = (uint32_t) sg_list; + +#ifdef CONFIG_PHYS_64BIT + r6 = sg_list >> 32; +#else + r6 = 0; +#endif + r7 = count; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), + "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), "+r" (r7) + : : EV_HCALL_CLOBBERS5 + ); + + return r3; +} + +/** + * fh_dma_enable - enable DMA for the specified device + * @liodn: the LIODN of the I/O device for which to enable DMA + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_dma_enable(unsigned int liodn) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_DMA_ENABLE); + r3 = liodn; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * fh_dma_disable - disable DMA for the specified device + * @liodn: the LIODN of the I/O device for which to disable DMA + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_dma_disable(unsigned int liodn) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_DMA_DISABLE); + r3 = liodn; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + + +/** + * fh_vmpic_get_msir - returns the MPIC-MSI register value + * @interrupt: the interrupt number + * @msir_val: returned MPIC-MSI register value + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_vmpic_get_msir(unsigned int interrupt, + unsigned int *msir_val) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_VMPIC_GET_MSIR); + r3 = interrupt; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "=r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *msir_val = r4; + + return r3; +} + +/** + * fh_system_reset - reset the system + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_system_reset(void) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_SYSTEM_RESET); + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "=r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + + +/** + * fh_err_get_info - get platform error information + * @queue id: + * 0 for guest error event queue + * 1 for global error event queue + * + * @pointer to store the platform error data: + * platform error data is returned in registers r4 - r11 + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_err_get_info(int queue, uint32_t *bufsize, + uint32_t addr_hi, uint32_t addr_lo, int peek) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + register uintptr_t r5 __asm__("r5"); + register uintptr_t r6 __asm__("r6"); + register uintptr_t r7 __asm__("r7"); + + r11 = FH_HCALL_TOKEN(FH_ERR_GET_INFO); + r3 = queue; + r4 = *bufsize; + r5 = addr_hi; + r6 = addr_lo; + r7 = peek; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4), "+r" (r5), "+r" (r6), + "+r" (r7) + : : EV_HCALL_CLOBBERS5 + ); + + *bufsize = r4; + + return r3; +} + + +#define FH_VCPU_RUN 0 +#define FH_VCPU_IDLE 1 +#define FH_VCPU_NAP 2 + +/** + * fh_get_core_state - get the state of a vcpu + * + * @handle: handle of partition containing the vcpu + * @vcpu: vcpu number within the partition + * @state:the current state of the vcpu, see FH_VCPU_* + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_get_core_state(unsigned int handle, + unsigned int vcpu, unsigned int *state) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_GET_CORE_STATE); + r3 = handle; + r4 = vcpu; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + *state = r4; + return r3; +} + +/** + * fh_enter_nap - enter nap on a vcpu + * + * Note that though the API supports entering nap on a vcpu other + * than the caller, this may not be implmented and may return EINVAL. + * + * @handle: handle of partition containing the vcpu + * @vcpu: vcpu number within the partition + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_enter_nap(unsigned int handle, unsigned int vcpu) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_ENTER_NAP); + r3 = handle; + r4 = vcpu; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + return r3; +} + +/** + * fh_exit_nap - exit nap on a vcpu + * @handle: handle of partition containing the vcpu + * @vcpu: vcpu number within the partition + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_exit_nap(unsigned int handle, unsigned int vcpu) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + register uintptr_t r4 __asm__("r4"); + + r11 = FH_HCALL_TOKEN(FH_EXIT_NAP); + r3 = handle; + r4 = vcpu; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3), "+r" (r4) + : : EV_HCALL_CLOBBERS2 + ); + + return r3; +} +/** + * fh_claim_device - claim a "claimable" shared device + * @handle: fsl,hv-device-handle of node to claim + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_claim_device(unsigned int handle) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_CLAIM_DEVICE); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} + +/** + * Run deferred DMA disabling on a partition's private devices + * + * This applies to devices which a partition owns either privately, + * or which are claimable and still actively owned by that partition, + * and which do not have the no-dma-disable property. + * + * @handle: partition (must be stopped) whose DMA is to be disabled + * + * Returns 0 for success, or an error code. + */ +static inline unsigned int fh_partition_stop_dma(unsigned int handle) +{ + register uintptr_t r11 __asm__("r11"); + register uintptr_t r3 __asm__("r3"); + + r11 = FH_HCALL_TOKEN(FH_PARTITION_STOP_DMA); + r3 = handle; + + asm volatile("bl epapr_hypercall_start" + : "+r" (r11), "+r" (r3) + : : EV_HCALL_CLOBBERS1 + ); + + return r3; +} +#endif diff --git a/bsps/powerpc/qoriq/include/bsp.h b/bsps/powerpc/qoriq/include/bsp.h new file mode 100644 index 0000000000..d7e9e95b3f --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp.h @@ -0,0 +1,128 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief BSP API. + */ + +/* + * Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_BSP_H +#define LIBBSP_POWERPC_QORIQ_BSP_H + +#include <bspopts.h> + +#ifdef QORIQ_IS_HYPERVISOR_GUEST +#define QORIQ_THREAD_COUNT 1 +#else +#define QORIQ_THREAD_COUNT QORIQ_PHYSICAL_THREAD_COUNT +#endif + +#ifndef ASM + +#include <rtems.h> + +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_FDT_IS_SUPPORTED + +#define QORIQ_CHIP(alpha, num) ((alpha) * 10000 + (num)) + +#define QORIQ_CHIP_P1020 QORIQ_CHIP('P', 1020) + +#define QORIQ_CHIP_T2080 QORIQ_CHIP('T', 2080) + +#define QORIQ_CHIP_T4240 QORIQ_CHIP('T', 4240) + +#define QORIQ_CHIP_VARIANT QORIQ_CHIP(QORIQ_CHIP_SERIES, QORIQ_CHIP_NUMBER) + +#define QORIQ_CHIP_IS_T_VARIANT(variant) ((variant) / 10000 == 'T') + +extern unsigned BSP_bus_frequency; + +struct rtems_bsdnet_ifconfig; + +int BSP_tsec_attach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +int qoriq_if_intercom_attach_detach( + struct rtems_bsdnet_ifconfig *config, + int attaching +); + +#if defined(HAS_UBOOT) + /* Routine to obtain U-Boot environment variables */ + const char *bsp_uboot_getenv( + const char *name + ); +#endif + +void bsp_restart(void *addr) RTEMS_NO_RETURN; + +void *bsp_idle_thread( uintptr_t ignored ); +#define BSP_IDLE_TASK_BODY bsp_idle_thread + +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH4 qoriq_if_intercom_attach_detach + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" +#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" +#define RTEMS_BSP_NETWORK_DRIVER_NAME3 "tsec3" +#define RTEMS_BSP_NETWORK_DRIVER_NAME4 "intercom1" + +/* Internal data and functions */ + +typedef struct { + uint64_t addr; + uint64_t r3; + uint32_t reserved_0; + uint32_t pir; + uint64_t r6; + uint32_t reserved_1[8]; +} qoriq_start_spin_table; + +extern qoriq_start_spin_table * +qoriq_start_spin_table_addr[QORIQ_CPU_COUNT / QORIQ_THREAD_COUNT]; + +void qoriq_start_thread(void); + +void qoriq_restart_secondary_processor( + const qoriq_start_spin_table *spin_table +) RTEMS_NO_RETURN; + +void qoriq_initialize_exceptions(void *interrupt_stack_begin); + +void qoriq_decrementer_dispatch(void); + +extern uint32_t bsp_time_base_frequency; + +extern uint32_t qoriq_clock_frequency; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_QORIQ_BSP_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/intercom.h b/bsps/powerpc/qoriq/include/bsp/intercom.h new file mode 100644 index 0000000000..39b2ba938e --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/intercom.h @@ -0,0 +1,125 @@ +/** + * @file + * + * @ingroup QorIQInterCom + * + * @brief Inter-Processor Communication API. + */ + +/* + * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_INTERCOM_H +#define LIBBSP_POWERPC_QORIQ_INTERCOM_H + +#include <rtems.h> +#include <rtems/chain.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup QorIQInterCom QorIQ - Inter-Processor Communication Support + * + * @ingroup QorIQ + * + * @brief Inter-processor communication support. + * + * @{ + */ + +uint32_t qoriq_spin_lock(uint32_t *lock); + +void qoriq_spin_unlock(uint32_t *lock, uint32_t msr); + +#define INTERCOM_CORE_COUNT 2 + +#define INTERCOM_SERVICE_COUNT 8 + +typedef enum { + INTERCOM_TYPE_MPCI, + INTERCOM_TYPE_UART_0, + INTERCOM_TYPE_UART_1, + INTERCOM_TYPE_NETWORK, + INTERCOM_TYPE_CUSTOM_0, + INTERCOM_TYPE_CUSTOM_1, + INTERCOM_TYPE_CUSTOM_2, + INTERCOM_TYPE_CUSTOM_3, + INTERCOM_TYPE_CUSTOM_4 +} intercom_type; + +typedef enum { + INTERCOM_SIZE_64 = 0, + INTERCOM_SIZE_512, + INTERCOM_SIZE_2K, + INTERCOM_SIZE_4K +} intercom_size; + +typedef struct intercom_packet { + union { + struct intercom_packet *next; + rtems_chain_node node; + } glue; + intercom_type type_index; + intercom_size size_index; + uint32_t flags; + size_t size; + uint32_t cache_line_alignment [2]; + char data []; +} intercom_packet; + +typedef void (*intercom_service)(intercom_packet *packet, void *arg); + +void qoriq_intercom_init(void); + +void qoriq_intercom_start(void); + +void qoriq_intercom_service_install(intercom_type type, intercom_service service, void *arg); + +void qoriq_intercom_service_remove(intercom_type type); + +intercom_packet *qoriq_intercom_allocate_packet(intercom_type type, intercom_size size); + +void qoriq_intercom_send_packets(int destination_core, intercom_packet *first, intercom_packet *last); + +static inline void qoriq_intercom_send_packet(int destination_core, intercom_packet *packet) +{ + qoriq_intercom_send_packets(destination_core, packet, packet); +} + +void qoriq_intercom_broadcast_packets(intercom_packet *first, intercom_packet *last); + +static inline void qoriq_intercom_broadcast_packet(intercom_packet *packet) +{ + qoriq_intercom_broadcast_packets(packet, packet); +} + +void qoriq_intercom_send(int destination_core, intercom_type type, intercom_size size, const void *buf, size_t n); + +void qoriq_intercom_free_packet(intercom_packet *packet); + +intercom_packet *qoriq_intercom_clone_packet(const intercom_packet *packet); + +#ifdef RTEMS_MULTIPROCESSING + extern rtems_mpci_table qoriq_intercom_mpci; +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_INTERCOM_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/irq.h b/bsps/powerpc/qoriq/include/bsp/irq.h new file mode 100644 index 0000000000..e178057950 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/irq.h @@ -0,0 +1,401 @@ +/** + * @file + * + * @ingroup QorIQInterrupt + * + * @brief Interrupt API. + */ + +/* + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_IRQ_H +#define LIBBSP_POWERPC_QORIQ_IRQ_H + +#include <bsp.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> +#include <rtems/score/processormask.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#ifdef QORIQ_IS_HYPERVISOR_GUEST + +#define BSP_INTERRUPT_VECTOR_MAX 1023 + +#else /* !QORIQ_IS_HYPERVISOR_GUEST */ + +#define QORIQ_IRQ_ERROR 0 + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + +#define QORIQ_IRQ_PCI_EXPRESS_1 4 +#define QORIQ_IRQ_PCI_EXPRESS_2 5 +#define QORIQ_IRQ_PCI_EXPRESS_3 6 +#define QORIQ_IRQ_PCI_EXPRESS_4 7 +#define QORIQ_IRQ_PAMU 8 +#define QORIQ_IRQ_IFC 9 +#define QORIQ_IRQ_DMA_CHANNEL_1_1 12 +#define QORIQ_IRQ_DMA_CHANNEL_1_2 13 +#define QORIQ_IRQ_DMA_CHANNEL_1_3 14 +#define QORIQ_IRQ_DMA_CHANNEL_1_4 15 +#define QORIQ_IRQ_DMA_CHANNEL_2_1 16 +#define QORIQ_IRQ_DMA_CHANNEL_2_2 17 +#define QORIQ_IRQ_DMA_CHANNEL_2_3 18 +#define QORIQ_IRQ_DMA_CHANNEL_2_4 19 +#define QORIQ_IRQ_DUART_1 20 +#define QORIQ_IRQ_DUART_2 21 +#define QORIQ_IRQ_DUARL_I2C_1 22 +#define QORIQ_IRQ_DUARL_I2C_2 23 +#define QORIQ_IRQ_PCI_EXPRESS_1_INTA 24 +#define QORIQ_IRQ_PCI_EXPRESS_2_INTA 25 +#define QORIQ_IRQ_PCI_EXPRESS_3_INTA 26 +#define QORIQ_IRQ_PCI_EXPRESS_4_INTA 27 +#define QORIQ_IRQ_USB_1 28 +#define QORIQ_IRQ_USB_2 29 +#define QORIQ_IRQ_ESDHC 32 +#define QORIQ_IRQ_PERF_MON 36 +#define QORIQ_IRQ_ESPI 37 +#define QORIQ_IRQ_GPIO_2 38 +#define QORIQ_IRQ_GPIO_1 39 +#define QORIQ_IRQ_SATA_1 52 +#define QORIQ_IRQ_SATA_2 53 +#define QORIQ_IRQ_DMA_CHANNEL_1_5 60 +#define QORIQ_IRQ_DMA_CHANNEL_1_6 61 +#define QORIQ_IRQ_DMA_CHANNEL_1_7 62 +#define QORIQ_IRQ_DMA_CHANNEL_1_8 63 +#define QORIQ_IRQ_DMA_CHANNEL_2_5 64 +#define QORIQ_IRQ_DMA_CHANNEL_2_6 65 +#define QORIQ_IRQ_DMA_CHANNEL_2_7 66 +#define QORIQ_IRQ_DMA_CHANNEL_2_8 67 +#define QORIQ_IRQ_EVENT_PROC_UNIT_1 68 +#define QORIQ_IRQ_EVENT_PROC_UNIT_2 69 +#define QORIQ_IRQ_GPIO_3 70 +#define QORIQ_IRQ_GPIO_4 71 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_1 72 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_2 73 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_3 74 +#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_4 75 +#define QORIQ_IRQ_SEC_5_2_GLOBAL_ERROR 76 +#define QORIQ_IRQ_SEC_MON 77 +#define QORIQ_IRQ_EVENT_PROC_UNIT_3 78 +#define QORIQ_IRQ_EVENT_PROC_UNIT_4 79 +#define QORIQ_IRQ_FRAME_MGR 80 +#define QORIQ_IRQ_MDIO_1 84 +#define QORIQ_IRQ_MDIO_2 85 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_0 88 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_0 89 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_1 90 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_1 91 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_2 92 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_2 93 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_3 94 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_3 95 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_4 96 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_4 97 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_5 98 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_5 99 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_6 100 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_6 101 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_7 102 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_7 103 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_8 104 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_8 105 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_9 106 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_9 107 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_10 109 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_10 109 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_11 110 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_11 111 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_12 112 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_12 113 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_13 114 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_13 115 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_14 116 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_14 117 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_15 118 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_15 119 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_16 120 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_16 121 +#define QORIQ_IRQ_QUEUE_MGR_PORTAL_17 122 +#define QORIQ_IRQ_BUFFER_MGR_PORTAL_17 123 +#define QORIQ_IRQ_DMA_CHANNEL_3_1 240 +#define QORIQ_IRQ_DMA_CHANNEL_3_2 241 +#define QORIQ_IRQ_DMA_CHANNEL_3_3 242 +#define QORIQ_IRQ_DMA_CHANNEL_3_4 243 +#define QORIQ_IRQ_DMA_CHANNEL_3_5 244 +#define QORIQ_IRQ_DMA_CHANNEL_3_6 245 +#define QORIQ_IRQ_DMA_CHANNEL_3_7 246 +#define QORIQ_IRQ_DMA_CHANNEL_3_8 247 + +#define QORIQ_IRQ_EXT_BASE 256 + +#else /* QORIQ_CHIP_VARIANT */ + +/** + * @defgroup QoriqInterruptP1020 QorIQ - P1020 Internal Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief P1020 internal interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_ETSEC_TX_1_GROUP_1 1 +#define QORIQ_IRQ_ETSEC_RX_1_GROUP_1 2 +#define QORIQ_IRQ_ETSEC_ER_1_GROUP_1 8 +#define QORIQ_IRQ_ETSEC_TX_3_GROUP_1 9 +#define QORIQ_IRQ_ETSEC_RX_3_GROUP_1 10 +#define QORIQ_IRQ_ETSEC_ER_3_GROUP_1 11 +#define QORIQ_IRQ_ETSEC_TX_2_GROUP_1 35 +#define QORIQ_IRQ_ETSEC_RX_2_GROUP_1 36 +#define QORIQ_IRQ_TDM 46 +#define QORIQ_IRQ_TDM_ERROR 47 +#define QORIQ_IRQ_ETSEC_ER_2_GROUP_1 51 + +/** @} */ + +/** + * @defgroup QoriqInterruptP2020 QorIQ - P2020 Internal Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief P2020 internal interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_L2_CACHE 0 +#define QORIQ_IRQ_ECM 1 +#define QORIQ_IRQ_DDR_CONTROLLER 2 +#define QORIQ_IRQ_PCI_EXPRESS_3 8 +#define QORIQ_IRQ_PCI_EXPRESS_2 9 +#define QORIQ_IRQ_PCI_EXPRESS_1 10 +#define QORIQ_IRQ_SRIO_ERR_WRT_1_2 32 +#define QORIQ_IRQ_SRIO_OUT_DOORBELL_1 33 +#define QORIQ_IRQ_SRIO_IN_DOORBELL_1 34 +#define QORIQ_IRQ_SRIO_OUT_MSG_1 37 +#define QORIQ_IRQ_SRIO_IN_MSG_1 38 +#define QORIQ_IRQ_SRIO_OUT_MSG_2 39 +#define QORIQ_IRQ_SRIO_IN_MSG_2 40 + +/** @} */ + +/** + * @defgroup QoriqInterruptAll QorIQ - Internal Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief Internal interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_ELBC 3 +#define QORIQ_IRQ_DMA_CHANNEL_1_1 4 +#define QORIQ_IRQ_DMA_CHANNEL_2_1 5 +#define QORIQ_IRQ_DMA_CHANNEL_3_1 6 +#define QORIQ_IRQ_DMA_CHANNEL_4_1 7 +#define QORIQ_IRQ_USB_1 12 +#define QORIQ_IRQ_ETSEC_TX_1 13 +#define QORIQ_IRQ_ETSEC_RX_1 14 +#define QORIQ_IRQ_ETSEC_TX_3 15 +#define QORIQ_IRQ_ETSEC_RX_3 16 +#define QORIQ_IRQ_ETSEC_ER_3 17 +#define QORIQ_IRQ_ETSEC_ER_1 18 +#define QORIQ_IRQ_ETSEC_TX_2 19 +#define QORIQ_IRQ_ETSEC_RX_2 20 +#define QORIQ_IRQ_ETSEC_ER_2 24 +#define QORIQ_IRQ_DUART_1 26 +#define QORIQ_IRQ_I2C 27 +#define QORIQ_IRQ_PERFORMANCE_MONITOR 28 +#define QORIQ_IRQ_SECURITY_1 29 +#define QORIQ_IRQ_USB_2 30 +#define QORIQ_IRQ_GPIO 31 +#define QORIQ_IRQ_SECURITY_2 42 +#define QORIQ_IRQ_ESPI 43 +#define QORIQ_IRQ_ETSEC_IEEE_1588_1 52 +#define QORIQ_IRQ_ETSEC_IEEE_1588_2 53 +#define QORIQ_IRQ_ETSEC_IEEE_1588_3 54 +#define QORIQ_IRQ_ESDHC 56 +#define QORIQ_IRQ_DMA_CHANNEL_1_2 60 +#define QORIQ_IRQ_DMA_CHANNEL_2_2 61 +#define QORIQ_IRQ_DMA_CHANNEL_3_2 62 +#define QORIQ_IRQ_DMA_CHANNEL_4_2 63 + +/** @} */ + +#define QORIQ_IRQ_EXT_BASE 64 + +#endif /* QORIQ_CHIP_VARIANT */ + +/** + * @defgroup QoriqInterruptExternal QorIQ - External Interrupt Sources + * + * @ingroup QorIQInterrupt + * + * @brief External interrupt sources. + * + * @{ + */ + +#define QORIQ_IRQ_EXT_0 (QORIQ_IRQ_EXT_BASE + 0) +#define QORIQ_IRQ_EXT_1 (QORIQ_IRQ_EXT_BASE + 1) +#define QORIQ_IRQ_EXT_2 (QORIQ_IRQ_EXT_BASE + 2) +#define QORIQ_IRQ_EXT_3 (QORIQ_IRQ_EXT_BASE + 3) +#define QORIQ_IRQ_EXT_4 (QORIQ_IRQ_EXT_BASE + 4) +#define QORIQ_IRQ_EXT_5 (QORIQ_IRQ_EXT_BASE + 5) +#define QORIQ_IRQ_EXT_6 (QORIQ_IRQ_EXT_BASE + 6) +#define QORIQ_IRQ_EXT_7 (QORIQ_IRQ_EXT_BASE + 7) +#define QORIQ_IRQ_EXT_8 (QORIQ_IRQ_EXT_BASE + 8) +#define QORIQ_IRQ_EXT_9 (QORIQ_IRQ_EXT_BASE + 9) +#define QORIQ_IRQ_EXT_10 (QORIQ_IRQ_EXT_BASE + 10) +#define QORIQ_IRQ_EXT_11 (QORIQ_IRQ_EXT_BASE + 11) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Interprocessor Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Interprocessor interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_IPI_BASE (QORIQ_IRQ_EXT_11 + 1) +#define QORIQ_IRQ_IPI_0 (QORIQ_IRQ_IPI_BASE + 0) +#define QORIQ_IRQ_IPI_1 (QORIQ_IRQ_IPI_BASE + 1) +#define QORIQ_IRQ_IPI_2 (QORIQ_IRQ_IPI_BASE + 2) +#define QORIQ_IRQ_IPI_3 (QORIQ_IRQ_IPI_BASE + 3) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Message Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Message interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_MI_BASE (QORIQ_IRQ_IPI_3 + 1) +#define QORIQ_IRQ_MI_0 (QORIQ_IRQ_MI_BASE + 0) +#define QORIQ_IRQ_MI_1 (QORIQ_IRQ_MI_BASE + 1) +#define QORIQ_IRQ_MI_2 (QORIQ_IRQ_MI_BASE + 2) +#define QORIQ_IRQ_MI_3 (QORIQ_IRQ_MI_BASE + 3) +#define QORIQ_IRQ_MI_4 (QORIQ_IRQ_MI_BASE + 4) +#define QORIQ_IRQ_MI_5 (QORIQ_IRQ_MI_BASE + 5) +#define QORIQ_IRQ_MI_6 (QORIQ_IRQ_MI_BASE + 6) +#define QORIQ_IRQ_MI_7 (QORIQ_IRQ_MI_BASE + 7) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Shared Message Signaled Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Shared message signaled interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_MSI_BASE (QORIQ_IRQ_MI_7 + 1) +#define QORIQ_IRQ_MSI_0 (QORIQ_IRQ_MSI_BASE + 0) +#define QORIQ_IRQ_MSI_1 (QORIQ_IRQ_MSI_BASE + 1) +#define QORIQ_IRQ_MSI_2 (QORIQ_IRQ_MSI_BASE + 2) +#define QORIQ_IRQ_MSI_3 (QORIQ_IRQ_MSI_BASE + 3) +#define QORIQ_IRQ_MSI_4 (QORIQ_IRQ_MSI_BASE + 4) +#define QORIQ_IRQ_MSI_5 (QORIQ_IRQ_MSI_BASE + 5) +#define QORIQ_IRQ_MSI_6 (QORIQ_IRQ_MSI_BASE + 6) +#define QORIQ_IRQ_MSI_7 (QORIQ_IRQ_MSI_BASE + 7) + +/** @} */ + +/** + * @defgroup QoriqInterruptIPI QorIQ - Global Timer Interrupts + * + * @ingroup QorIQInterrupt + * + * @brief Global Timer interrupts. + * + * @{ + */ + +#define QORIQ_IRQ_GT_BASE (QORIQ_IRQ_MSI_7 + 1) +#define QORIQ_IRQ_GT_A_0 (QORIQ_IRQ_GT_BASE + 0) +#define QORIQ_IRQ_GT_A_1 (QORIQ_IRQ_GT_BASE + 1) +#define QORIQ_IRQ_GT_A_2 (QORIQ_IRQ_GT_BASE + 2) +#define QORIQ_IRQ_GT_A_3 (QORIQ_IRQ_GT_BASE + 3) +#define QORIQ_IRQ_GT_B_0 (QORIQ_IRQ_GT_BASE + 4) +#define QORIQ_IRQ_GT_B_1 (QORIQ_IRQ_GT_BASE + 5) +#define QORIQ_IRQ_GT_B_2 (QORIQ_IRQ_GT_BASE + 6) +#define QORIQ_IRQ_GT_B_3 (QORIQ_IRQ_GT_BASE + 7) + +#define BSP_INTERRUPT_VECTOR_MAX QORIQ_IRQ_GT_B_3 + +/** @} */ + +#endif /* QORIQ_IS_HYPERVISOR_GUEST */ + +/** + * @defgroup QorIQInterrupt QorIQ - Interrupt Support + * + * @ingroup QorIQ + * + * @brief Interrupt support. + * + * @{ + */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define QORIQ_PIC_PRIORITY_LOWEST 1 +#define QORIQ_PIC_PRIORITY_HIGHEST 15 +#define QORIQ_PIC_PRIORITY_DISABLED 0 +#define QORIQ_PIC_PRIORITY_INVALID (QORIQ_PIC_PRIORITY_HIGHEST + 1) +#define QORIQ_PIC_PRIORITY_DEFAULT (QORIQ_PIC_PRIORITY_LOWEST + 1) +#define QORIQ_PIC_PRIORITY_IS_VALID(p) \ + ((p) >= QORIQ_PIC_PRIORITY_DISABLED && (p) <= QORIQ_PIC_PRIORITY_HIGHEST) + +rtems_status_code qoriq_pic_set_priority( + rtems_vector_number vector, + int new_priority, + int *old_priority +); + +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_IRQ_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/mmu.h b/bsps/powerpc/qoriq/include/bsp/mmu.h new file mode 100644 index 0000000000..4cacb1b375 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/mmu.h @@ -0,0 +1,101 @@ +/** + * @file + * + * @ingroup QorIQMMU + * + * @brief MMU API. + */ + +/* + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_MMU_H +#define LIBBSP_POWERPC_QORIQ_MMU_H + +#include <stdint.h> +#include <stdbool.h> + +#include <bspopts.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup QorIQMMU QorIQ - MMU Support + * + * @ingroup QorIQ + * + * @brief MMU support. + * + * @{ + */ + +#define QORIQ_MMU_MIN_POWER 12 +#define QORIQ_MMU_MAX_POWER 30 +#define QORIQ_MMU_POWER_STEP 2 + +typedef struct { + uintptr_t begin; + uintptr_t last; + uint32_t mas1; + uint32_t mas2; + uint32_t mas3; + uint32_t mas7; +} qoriq_mmu_entry; + +typedef struct { + int count; + qoriq_mmu_entry entries [QORIQ_TLB1_ENTRY_COUNT]; +} qoriq_mmu_context; + +void qoriq_mmu_context_init(qoriq_mmu_context *self); + +bool qoriq_mmu_add( + qoriq_mmu_context *self, + uintptr_t begin, + uintptr_t last, + uint32_t mas1, + uint32_t mas2, + uint32_t mas3, + uint32_t mas7 +); + +void qoriq_mmu_partition(qoriq_mmu_context *self, int max_count); + +void qoriq_mmu_write_to_tlb1(qoriq_mmu_context *self, int first_tlb); + +void qoriq_mmu_change_perm(uint32_t test, uint32_t set, uint32_t clear); + +void qoriq_mmu_config(bool boot_processor, int first_tlb, int scratch_tlb); + +void qoriq_tlb1_write( + int esel, + uint32_t mas1, + uint32_t mas2, + uint32_t mas3, + uint32_t mas7, + uintptr_t ea, + int tsize +); + +void qoriq_tlb1_invalidate(int esel); + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_MMU_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/qoriq.h b/bsps/powerpc/qoriq/include/bsp/qoriq.h new file mode 100644 index 0000000000..2d28d0aec7 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/qoriq.h @@ -0,0 +1,559 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief QorIQ Configuration, Control and Status Registers. + */ + +/* + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_QORIQ_H +#define LIBBSP_POWERPC_QORIQ_QORIQ_H + +#include <bsp.h> +#include <bsp/tsec.h> +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define QORIQ_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)] +#define QORIQ_RESERVE(a, b) uint8_t reserved_ ## b [b - a] + +typedef struct { + uint32_t reg; + QORIQ_FILL(0x00000, 0x00010, uint32_t); +} qoriq_pic_reg; + +typedef struct { + uint32_t ccr; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t bcr; + QORIQ_FILL(0x00010, 0x00020, uint32_t); + uint32_t vpr; + QORIQ_FILL(0x00020, 0x00030, uint32_t); + uint32_t dr; + QORIQ_FILL(0x00030, 0x00040, uint32_t); +} qoriq_pic_global_timer; + +#define GTCCR_TOG BSP_BBIT32(0) +#define GTCCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) + +#define GTBCR_CI BSP_BBIT32(0) +#define GTBCR_COUNT(val) BSP_BFLD32(val, 1, 31) +#define GTBCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31) +#define GTBCR_COUNT_SET(reg, val) BSP_BFLD32SET(reg, val, 1, 31) + +typedef struct { + uint32_t misc; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t internal [2]; + QORIQ_FILL(0x00010, 0x00020, uint32_t [2]); +} qoriq_pic_bit_field; + +typedef struct { + uint32_t vpr; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t dr; + QORIQ_FILL(0x00010, 0x00020, uint32_t); +} qoriq_pic_src_cfg; + +typedef struct { + QORIQ_RESERVE(0x00000, 0x00040); + qoriq_pic_reg ipidr [4]; + uint32_t ctpr; + QORIQ_FILL(0x00080, 0x00090, uint32_t); + uint32_t whoami; + QORIQ_FILL(0x00090, 0x000a0, uint32_t); + uint32_t iack; + QORIQ_FILL(0x000a0, 0x000b0, uint32_t); + uint32_t eoi; + QORIQ_FILL(0x000b0, 0x01000, uint32_t); +} qoriq_pic_per_cpu; + +typedef struct { + uint32_t brr1; + QORIQ_FILL(0x00000, 0x00010, uint32_t); + uint32_t brr2; + QORIQ_FILL(0x00010, 0x00040, uint32_t); + qoriq_pic_reg ipidr [4]; + uint32_t ctpr; + QORIQ_FILL(0x00080, 0x00090, uint32_t); + uint32_t whoami; + QORIQ_FILL(0x00090, 0x000a0, uint32_t); + uint32_t iack; + QORIQ_FILL(0x000a0, 0x000b0, uint32_t); + uint32_t eoi; + QORIQ_FILL(0x000b0, 0x01000, uint32_t); + uint32_t frr; + QORIQ_FILL(0x01000, 0x01020, uint32_t); + uint32_t gcr; + QORIQ_FILL(0x01020, 0x01080, uint32_t); + uint32_t vir; + QORIQ_FILL(0x01080, 0x01090, uint32_t); + uint32_t pir; + QORIQ_FILL(0x01090, 0x010a0, uint32_t); + qoriq_pic_reg ipivpr [4]; + uint32_t svr; + QORIQ_FILL(0x010e0, 0x010f0, uint32_t); + uint32_t tfrra; + QORIQ_FILL(0x010f0, 0x01100, uint32_t); + qoriq_pic_global_timer gta [4]; + QORIQ_RESERVE(0x01200, 0x01300); + uint32_t tcra; + QORIQ_FILL(0x01300, 0x01308, uint32_t); + uint32_t erqsr; + QORIQ_FILL(0x01308, 0x01310, uint32_t); + qoriq_pic_bit_field irqsr; + qoriq_pic_bit_field cisr; + qoriq_pic_bit_field pm [4]; + QORIQ_RESERVE(0x013d0, 0x01400); + qoriq_pic_reg msgr03 [4]; + QORIQ_RESERVE(0x01440, 0x01500); + uint32_t mer03; + QORIQ_FILL(0x01500, 0x01510, uint32_t); + uint32_t msr03; + QORIQ_FILL(0x01510, 0x01600, uint32_t); + qoriq_pic_reg msir [8]; + QORIQ_RESERVE(0x01680, 0x01720); + uint32_t msisr; + QORIQ_FILL(0x01720, 0x01740, uint32_t); + uint32_t msiir; + QORIQ_FILL(0x01740, 0x020f0, uint32_t); + uint32_t tfrrb; + QORIQ_FILL(0x020f0, 0x02100, uint32_t); + qoriq_pic_global_timer gtb [4]; + QORIQ_RESERVE(0x02200, 0x02300); + uint32_t tcrb; + QORIQ_FILL(0x02300, 0x02400, uint32_t); + qoriq_pic_reg msgr47 [4]; + QORIQ_RESERVE(0x02440, 0x02500); + uint32_t mer47; + QORIQ_FILL(0x02500, 0x02510, uint32_t); + uint32_t msr47; + QORIQ_FILL(0x02510, 0x10000, uint32_t); + qoriq_pic_src_cfg ei [12]; + QORIQ_RESERVE(0x10180, 0x10200); + qoriq_pic_src_cfg ii_0 [160]; + qoriq_pic_src_cfg mi [8]; + QORIQ_RESERVE(0x11700, 0x11c00); + qoriq_pic_src_cfg msi [8]; + QORIQ_RESERVE(0x11d00, 0x13000); + qoriq_pic_src_cfg ii_1 [96]; + QORIQ_RESERVE(0x13c00, 0x20000); + qoriq_pic_per_cpu per_cpu [2]; +} qoriq_pic; + +#define GTTCR_ROVR(val) BSP_BFLD32(val, 5, 7) +#define GTTCR_ROVR_GET(reg) BSP_BFLD32GET(reg, 5, 7) +#define GTTCR_ROVR_SET(reg, val) BSP_BFLD32SET(reg, val, 5, 7) +#define GTTCR_RTM BSP_BBIT32(15) +#define GTTCR_CLKR(val) BSP_BFLD32(val, 22, 23) +#define GTTCR_CLKR_GET(reg) BSP_BFLD32GET(reg, 22, 23) +#define GTTCR_CLKR_SET(reg, val) BSP_BFLD32SET(reg, val, 22, 23) +#define GTTCR_CASC(val) BSP_BFLD32(val, 29, 31) +#define GTTCR_CASC_GET(reg) BSP_BFLD32GET(reg, 29, 31) +#define GTTCR_CASC_SET(reg, val) BSP_BFLD32SET(reg, val, 29, 31) + +typedef struct { +} qoriq_uart; + +typedef struct { + uint32_t gpdir; + uint32_t gpodr; + uint32_t gpdat; + uint32_t gpier; + uint32_t gpimr; + uint32_t gpicr; + uint32_t gpibe; + QORIQ_RESERVE(0x001c, 0x1000); +} qoriq_gpio; + +typedef struct { + QORIQ_RESERVE(0x000, 0x100); + uint16_t caplength; + uint16_t hciversion; + uint32_t hcsparams; + uint32_t hccparams; + QORIQ_RESERVE(0x10c, 0x120); + uint32_t dciversion; + uint32_t dccparams; + QORIQ_RESERVE(0x128, 0x140); + uint32_t usbcmd; + uint32_t usbsts; + uint32_t usbintr; + uint32_t frindex; + QORIQ_RESERVE(0x150, 0x154); + union { + uint32_t periodiclistbase; + uint32_t deviceaddr; + } perbase_devaddr; + union { + uint32_t asynclistaddr; + uint32_t addr; + } async_addr; + QORIQ_RESERVE(0x15c, 0x160); + uint32_t burstsize; + uint32_t txfilltuning; + QORIQ_RESERVE(0x168, 0x170); + uint32_t viewport; + QORIQ_RESERVE(0x174, 0x180); + uint32_t configflag; + uint32_t portsc1; + QORIQ_RESERVE(0x188, 0x1a8); + uint32_t usbmode; + uint32_t endptsetupstat; + uint32_t endpointprime; + uint32_t endptflush; + uint32_t endptstatus; + uint32_t endptcomplete; + uint32_t endptctrl[6]; + QORIQ_RESERVE(0x1d8, 0x400); + uint32_t snoop1; + uint32_t snoop2; + uint32_t age_cnt_thresh; + uint32_t pri_ctrl; + uint32_t si_ctrl; + QORIQ_RESERVE(0x414, 0x500); + uint32_t control; +} qoriq_usb; + +typedef struct { + uint32_t dsaddr; + uint32_t blkattr; + uint32_t cmdarg; + uint32_t xfertyp; + uint32_t cmdrsp0; + uint32_t cmdrsp1; + uint32_t cmdrsp2; + uint32_t cmdrsp3; + uint32_t datport; + uint32_t prsstat; + uint32_t proctl; + uint32_t sysctl; + uint32_t irqstat; + uint32_t irqstaten; + uint32_t irqsigen; + uint32_t autoc12err; + uint32_t hostcapblt; + uint32_t wml; + QORIQ_FILL(0x00044, 0x00050, uint32_t); + uint32_t fevt; + QORIQ_FILL(0x00050, 0x000fc, uint32_t); + uint32_t hostver; + QORIQ_FILL(0x000fc, 0x0040c, uint32_t); + uint32_t dcr; +} qoriq_esdhc; + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + +typedef struct { + uint32_t ccsrbarh; + uint32_t ccsrbarl; + uint32_t ccsrar; + uint32_t altcbarh; + uint32_t altcbarl; + uint32_t altcar; + uint32_t bstrh; + uint32_t bstrl; + uint32_t bstar; +} qoriq_lcc; + +#define LCC_BSTAR_EN BSP_BBIT32(0) + +typedef struct { + uint32_t lawbarh; + uint32_t lawbarl; + uint32_t lawar; + uint32_t reserved_0xc; +} qoriq_law; + +typedef struct { + uint32_t reserved_0x0[640]; + uint32_t qmbm_warmrst; +} qoriq_dcfg; + +typedef struct { + QORIQ_RESERVE(0x0000, 0x1000); +} qoriq_bman; + +typedef struct { + QORIQ_RESERVE(0x0000, 0x1000); +} qoriq_qman; + +typedef struct { + QORIQ_RESERVE(0x000000, 0x100000); +} qoriq_fman; + +typedef struct { + qoriq_lcc lcc; + QORIQ_FILL(0x000000, 0x000c00, qoriq_lcc); + qoriq_law law [32]; + QORIQ_FILL(0x000c00, 0x001000, qoriq_law [32]); + QORIQ_RESERVE(0x001000, 0x040000); + qoriq_pic pic; + QORIQ_FILL(0x040000, 0x070000, qoriq_pic); + QORIQ_RESERVE(0x070000, 0x0e0000); + qoriq_dcfg dcfg; + QORIQ_FILL(0x0e0000, 0x0e1000, qoriq_dcfg); + QORIQ_RESERVE(0x0e1000, 0x114000); + qoriq_esdhc esdhc; + QORIQ_FILL(0x114000, 0x115000, qoriq_esdhc); + QORIQ_RESERVE(0x115000, 0x11c500); + qoriq_uart uart_0; + QORIQ_FILL(0x11c500, 0x11c600, qoriq_uart); + qoriq_uart uart_1; + QORIQ_FILL(0x11c600, 0x11d500, qoriq_uart); + qoriq_uart uart_2; + QORIQ_FILL(0x11d500, 0x11d600, qoriq_uart); + qoriq_uart uart_3; + QORIQ_FILL(0x11d600, 0x11e000, qoriq_uart); + QORIQ_RESERVE(0x11e000, 0x130000); + qoriq_gpio gpio[4]; + QORIQ_RESERVE(0x134000, 0x210000); + qoriq_usb usb_1; + QORIQ_FILL(0x210000, 0x211000, qoriq_usb); + QORIQ_RESERVE(0x211000, 0x318000); + qoriq_qman qman; + QORIQ_RESERVE(0x319000, 0x31a000); + qoriq_bman bman; + QORIQ_RESERVE(0x31b000, 0x400000); + qoriq_fman fman[2]; + QORIQ_RESERVE(0x600000, 0x2000000); +} qoriq_ccsr; + +#else /* QORIQ_CHIP_VARIANT */ + +typedef struct { + uint32_t ccsrbar; + uint32_t reserved_0; + uint32_t altcbar; + uint32_t reserved_1; + uint32_t altcar; + uint32_t reserved_2 [3]; + uint32_t bptr; +} qoriq_lcc; + +#define CCSRBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23) +#define CCSRBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23) +#define CCSRBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23) + +#define ALTCBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23) +#define ALTCBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23) +#define ALTCBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23) + +#define ALTCAR_EN BSP_BBIT32(0) +#define ALTCAR_TRGT_ID(val) BSP_BFLD32(val, 8, 11) +#define ALTCAR_TRGT_ID_GET(reg) BSP_BFLD32GET(reg, 8, 11) +#define ALTCAR_TRGT_ID_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11) + +#define BPTR_EN BSP_BBIT32(0) +#define BPTR_BOOT_PAGE(val) BSP_BFLD32(val, 8, 31) +#define BPTR_BOOT_PAGE_GET(reg) BSP_BFLD32GET(reg, 8, 31) +#define BPTR_BOOT_PAGE_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31) + +typedef struct { + uint32_t bar; + uint32_t reserved_0; + uint32_t ar; + uint32_t reserved_1 [5]; +} qoriq_law; + +#define LAWBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 31) +#define LAWBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 31) +#define LAWBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31) + +#define LAWAR_EN BSP_BBIT32(0) +#define LAWAR_TRGT(val) BSP_BFLD32(val, 8, 11) +#define LAWAR_TRGT_GET(reg) BSP_BFLD32GET(reg, 8, 11) +#define LAWAR_TRGT_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11) +#define LAWAR_SIZE(val) BSP_BFLD32(val, 26, 31) +#define LAWAR_SIZE_GET(reg) BSP_BFLD32GET(reg, 26, 31) +#define LAWAR_SIZE_SET(reg, val) BSP_BFLD32SET(reg, val, 26, 31) + +typedef struct { +} qoriq_ecm; + +typedef struct { +} qoriq_ddr_controller; + +typedef struct { +} qoriq_i2c; + +typedef struct { +} qoriq_local_bus; + +typedef struct { +} qoriq_spi; + +typedef struct { +} qoriq_pci_express; + +typedef struct { +} qoriq_tdm; + +typedef struct { +} qoriq_l2_cache; + +typedef struct { +} qoriq_dma; + +typedef struct { +} qoriq_tdm_dma; + +typedef struct { +} qoriq_sec; + +typedef struct { +} qoriq_serial_rapid_io; + +typedef struct { +} qoriq_global_utilities; + +typedef struct { +} qoriq_performance_monitor; + +typedef struct { +} qoriq_debug_watchpoint; + +typedef struct { +} qoriq_serdes; + +typedef struct { +} qoriq_boot_rom; + +typedef struct { + qoriq_lcc lcc; + QORIQ_FILL(0x00000, 0x00c08, qoriq_lcc); + qoriq_law law [12]; + QORIQ_FILL(0x00c08, 0x01000, qoriq_law [12]); + qoriq_ecm ecm; + QORIQ_FILL(0x01000, 0x02000, qoriq_ecm); + qoriq_ddr_controller ddr_controller; + QORIQ_FILL(0x02000, 0x03000, qoriq_ddr_controller); + qoriq_i2c i2c; + QORIQ_FILL(0x03000, 0x04000, qoriq_i2c); + QORIQ_RESERVE(0x04000, 0x04500); + qoriq_uart uart_0; + QORIQ_FILL(0x04500, 0x04600, qoriq_uart); + qoriq_uart uart_1; + QORIQ_FILL(0x04600, 0x04700, qoriq_uart); + QORIQ_RESERVE(0x04700, 0x05000); + qoriq_local_bus local_bus; + QORIQ_FILL(0x05000, 0x06000, qoriq_local_bus); + qoriq_spi spi; + QORIQ_FILL(0x06000, 0x07000, qoriq_spi); + QORIQ_RESERVE(0x07000, 0x08000); + qoriq_pci_express pci_express_3; + QORIQ_FILL(0x08000, 0x09000, qoriq_pci_express); + qoriq_pci_express pci_express_2; + QORIQ_FILL(0x09000, 0x0a000, qoriq_pci_express); + qoriq_pci_express pci_express_1; + QORIQ_FILL(0x0a000, 0x0b000, qoriq_pci_express); + QORIQ_RESERVE(0x0b000, 0x0c000); + qoriq_dma dma_2; + QORIQ_FILL(0x0c000, 0x0d000, qoriq_dma); + QORIQ_RESERVE(0x0d000, 0x0f000); + qoriq_gpio gpio; + QORIQ_RESERVE(0x10000, 0x16000); + qoriq_tdm tdm; + QORIQ_FILL(0x16000, 0x17000, qoriq_tdm); + QORIQ_RESERVE(0x17000, 0x20000); + qoriq_l2_cache l2_cache; + QORIQ_FILL(0x20000, 0x21000, qoriq_l2_cache); + qoriq_dma dma_1; + QORIQ_FILL(0x21000, 0x22000, qoriq_dma); + qoriq_usb usb_1; + QORIQ_FILL(0x22000, 0x23000, qoriq_usb); + qoriq_usb usb_2; + QORIQ_FILL(0x23000, 0x24000, qoriq_usb); + tsec_registers tsec_1; + QORIQ_FILL(0x24000, 0x25000, tsec_registers); + tsec_registers tsec_2; + QORIQ_FILL(0x25000, 0x26000, tsec_registers); + tsec_registers tsec_3; + QORIQ_FILL(0x26000, 0x27000, tsec_registers); + QORIQ_RESERVE(0x27000, 0x2c000); + qoriq_tdm_dma tdm_dma; + QORIQ_FILL(0x2c000, 0x2d000, qoriq_tdm_dma); + QORIQ_RESERVE(0x2d000, 0x2e000); + qoriq_esdhc esdhc; + QORIQ_FILL(0x2e000, 0x2f000, qoriq_esdhc); + QORIQ_RESERVE(0x2f000, 0x30000); + qoriq_sec sec; + QORIQ_FILL(0x30000, 0x31000, qoriq_sec); + QORIQ_RESERVE(0x31000, 0x40000); + qoriq_pic pic; + QORIQ_FILL(0x40000, 0x80000, qoriq_pic); + QORIQ_RESERVE(0x80000, 0xb0000); + tsec_registers tsec_1_group_0; + QORIQ_FILL(0xb0000, 0xb1000, tsec_registers); + tsec_registers tsec_2_group_0; + QORIQ_FILL(0xb1000, 0xb2000, tsec_registers); + tsec_registers tsec_3_group_0; + QORIQ_FILL(0xb2000, 0xb3000, tsec_registers); + QORIQ_RESERVE(0xb3000, 0xb4000); + tsec_registers tsec_1_group_1; + QORIQ_FILL(0xb4000, 0xb5000, tsec_registers); + tsec_registers tsec_2_group_1; + QORIQ_FILL(0xb5000, 0xb6000, tsec_registers); + tsec_registers tsec_3_group_1; + QORIQ_FILL(0xb6000, 0xb7000, tsec_registers); + QORIQ_RESERVE(0xb7000, 0xc0000); + qoriq_serial_rapid_io serial_rapid_io; + QORIQ_FILL(0xc0000, 0xe0000, qoriq_serial_rapid_io); + qoriq_global_utilities global_utilities; + QORIQ_FILL(0xe0000, 0xe1000, qoriq_global_utilities); + qoriq_performance_monitor performance_monitor; + QORIQ_FILL(0xe1000, 0xe2000, qoriq_performance_monitor); + qoriq_debug_watchpoint debug_watchpoint; + QORIQ_FILL(0xe2000, 0xe3000, qoriq_debug_watchpoint); + qoriq_serdes serdes; + QORIQ_FILL(0xe3000, 0xe4000, qoriq_serdes); + QORIQ_RESERVE(0xe4000, 0xf0000); + qoriq_boot_rom boot_rom; + QORIQ_FILL(0xf0000, 0x100000, qoriq_boot_rom); +} qoriq_ccsr; + +#endif /* QORIQ_CHIP_VARIANT */ + +extern volatile qoriq_ccsr qoriq; + +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) +extern uint8_t qoriq_bman_portal[2][16777216]; +extern uint8_t qoriq_qman_portal[2][16777216]; + +void qoriq_clear_ce_portal(void *base, size_t size); +void qoriq_clear_ci_portal(void *base, size_t size); +#endif + +static inline void qoriq_reset_qman_and_bman(void) +{ +#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) + qoriq.dcfg.qmbm_warmrst = 0x3; + + while ((qoriq.dcfg.qmbm_warmrst & 0x3) != 0) { + /* Wait for reset done */ + } +#endif +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_QORIQ_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/tsec-config.h b/bsps/powerpc/qoriq/include/bsp/tsec-config.h new file mode 100644 index 0000000000..b1a70e7486 --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/tsec-config.h @@ -0,0 +1,36 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief TSEC configuration. + */ + +/* + * Copyright (c) 2010 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H +#define LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define TSEC_COUNT 3 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H */ diff --git a/bsps/powerpc/qoriq/include/bsp/uart-bridge.h b/bsps/powerpc/qoriq/include/bsp/uart-bridge.h new file mode 100644 index 0000000000..97e6553b7c --- /dev/null +++ b/bsps/powerpc/qoriq/include/bsp/uart-bridge.h @@ -0,0 +1,72 @@ +/** + * @file + * + * @ingroup QorIQUartBridge + * + * @brief UART to Intercom bridge API. + */ + +/* + * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H +#define LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H + +#include <rtems/termiostypes.h> + +#include <bsp/intercom.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * @defgroup QorIQUartBridge QorIQ - UART to Intercom Bridge Support + * + * @ingroup QorIQ + * + * @brief UART to Intercom bridge support. + * + * @{ + */ + +typedef struct { + rtems_termios_device_context base; + const char *device_path; + intercom_type type; + rtems_id transmit_task; + rtems_chain_control transmit_fifo; +} uart_bridge_master_context; + +typedef struct { + rtems_termios_device_context base; + struct rtems_termios_tty *tty; + intercom_type type; + rtems_id transmit_task; + rtems_chain_control transmit_fifo; +} uart_bridge_slave_context; + +bool qoriq_uart_bridge_master_probe(rtems_termios_device_context *base); + +extern const rtems_termios_device_handler qoriq_uart_bridge_master; + +extern const rtems_termios_device_handler qoriq_uart_bridge_slave; + +/** @} */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H */ diff --git a/bsps/powerpc/qoriq/include/tm27.h b/bsps/powerpc/qoriq/include/tm27.h new file mode 100644 index 0000000000..46264b7e67 --- /dev/null +++ b/bsps/powerpc/qoriq/include/tm27.h @@ -0,0 +1,96 @@ +/** + * @file + * + * @ingroup QorIQ + * + * @brief Support file for Timer Test 27. + */ + +/* + * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 + #error "This is an RTEMS internal file you must not include directly." +#endif /* _RTEMS_TMTEST27 */ + +#ifndef TMTESTS_TM27_H +#define TMTESTS_TM27_H + +#include <assert.h> + +#include <libcpu/powerpc-utility.h> + +#include <bsp/irq.h> +#include <bsp/qoriq.h> + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define IPI_INDEX_LOW 1 + +#define IPI_INDEX_HIGH 2 + +static void Install_tm27_vector(void (*handler)(rtems_vector_number)) +{ + rtems_status_code sc; + rtems_vector_number low = QORIQ_IRQ_IPI_0 + IPI_INDEX_LOW; + rtems_vector_number high = QORIQ_IRQ_IPI_0 + IPI_INDEX_HIGH; + + sc = rtems_interrupt_handler_install( + low, + "tm17 low", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = qoriq_pic_set_priority(low, 1, NULL); + assert(sc == RTEMS_SUCCESSFUL); + + sc = rtems_interrupt_handler_install( + high, + "tm17 high", + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) handler, + NULL + ); + assert(sc == RTEMS_SUCCESSFUL); + + sc = qoriq_pic_set_priority(high, 2, NULL); + assert(sc == RTEMS_SUCCESSFUL); +} + +static void qoriq_tm27_cause(uint32_t ipi_index) +{ + uint32_t self = ppc_processor_id(); + + qoriq.pic.per_cpu[self].ipidr[ipi_index].reg = UINT32_C(1) << self; +} + +static void Cause_tm27_intr() +{ + qoriq_tm27_cause(IPI_INDEX_LOW); +} + +static void Clear_tm27_intr() +{ + /* Nothing to do */ +} + +static void Lower_tm27_intr(void) +{ + qoriq_tm27_cause(IPI_INDEX_HIGH); +} + +#endif /* TMTESTS_TM27_H */ diff --git a/bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h b/bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h new file mode 100644 index 0000000000..b4504f3944 --- /dev/null +++ b/bsps/powerpc/qoriq/include/uapi/asm/epapr_hcalls.h @@ -0,0 +1,98 @@ +/* + * ePAPR hcall interface + * + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * Author: Timur Tabi <timur@freescale.com> + * + * This file is provided under a dual BSD/GPL license. When using or + * redistributing this file, you may do so under either license. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _UAPI_ASM_POWERPC_EPAPR_HCALLS_H +#define _UAPI_ASM_POWERPC_EPAPR_HCALLS_H + +#define EV_BYTE_CHANNEL_SEND 1 +#define EV_BYTE_CHANNEL_RECEIVE 2 +#define EV_BYTE_CHANNEL_POLL 3 +#define EV_INT_SET_CONFIG 4 +#define EV_INT_GET_CONFIG 5 +#define EV_INT_SET_MASK 6 +#define EV_INT_GET_MASK 7 +#define EV_INT_IACK 9 +#define EV_INT_EOI 10 +#define EV_INT_SEND_IPI 11 +#define EV_INT_SET_TASK_PRIORITY 12 +#define EV_INT_GET_TASK_PRIORITY 13 +#define EV_DOORBELL_SEND 14 +#define EV_MSGSND 15 +#define EV_IDLE 16 + +/* vendor ID: epapr */ +#define EV_LOCAL_VENDOR_ID 0 /* for private use */ +#define EV_EPAPR_VENDOR_ID 1 +#define EV_FSL_VENDOR_ID 2 /* Freescale Semiconductor */ +#define EV_IBM_VENDOR_ID 3 /* IBM */ +#define EV_GHS_VENDOR_ID 4 /* Green Hills Software */ +#define EV_ENEA_VENDOR_ID 5 /* Enea */ +#define EV_WR_VENDOR_ID 6 /* Wind River Systems */ +#define EV_AMCC_VENDOR_ID 7 /* Applied Micro Circuits */ +#define EV_KVM_VENDOR_ID 42 /* KVM */ + +/* The max number of bytes that a byte channel can send or receive per call */ +#define EV_BYTE_CHANNEL_MAX_BYTES 16 + + +#define _EV_HCALL_TOKEN(id, num) (((id) << 16) | (num)) +#define EV_HCALL_TOKEN(hcall_num) _EV_HCALL_TOKEN(EV_EPAPR_VENDOR_ID, hcall_num) + +/* epapr return codes */ +#define EV_SUCCESS 0 +#define EV_EPERM 1 /* Operation not permitted */ +#define EV_ENOENT 2 /* Entry Not Found */ +#define EV_EIO 3 /* I/O error occurred */ +#define EV_EAGAIN 4 /* The operation had insufficient + * resources to complete and should be + * retried + */ +#define EV_ENOMEM 5 /* There was insufficient memory to + * complete the operation */ +#define EV_EFAULT 6 /* Bad guest address */ +#define EV_ENODEV 7 /* No such device */ +#define EV_EINVAL 8 /* An argument supplied to the hcall + was out of range or invalid */ +#define EV_INTERNAL 9 /* An internal error occurred */ +#define EV_CONFIG 10 /* A configuration error was detected */ +#define EV_INVALID_STATE 11 /* The object is in an invalid state */ +#define EV_UNIMPLEMENTED 12 /* Unimplemented hypercall */ +#define EV_BUFFER_OVERFLOW 13 /* Caller-supplied buffer too small */ + +#endif /* _UAPI_ASM_POWERPC_EPAPR_HCALLS_H */ diff --git a/bsps/powerpc/ss555/headers.am b/bsps/powerpc/ss555/headers.am new file mode 100644 index 0000000000..f53a4bd6b2 --- /dev/null +++ b/bsps/powerpc/ss555/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/ss555/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/ss555/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/ss555/include/bsp/irq.h diff --git a/bsps/powerpc/ss555/include/bsp.h b/bsps/powerpc/ss555/include/bsp.h new file mode 100644 index 0000000000..a82d10a667 --- /dev/null +++ b/bsps/powerpc/ss555/include/bsp.h @@ -0,0 +1,91 @@ +/* + * This file includes definitions for the Intec SS555. + */ + +/* + * SS555 port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SS555_BSP_H +#define LIBBSP_POWERPC_SS555_BSP_H + +#ifndef ASM + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> +#include <mpc5xx.h> +#include <mpc5xx/console.h> +#include <libcpu/vectors.h> +#include <bsp/irq.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Clock definitions + */ + +#define BSP_CRYSTAL_HZ 4000000 /* crystal frequency, Hz */ +#define BSP_CLOCK_HZ 40000000 /* CPU clock frequency, Hz + +/* + * I/O definitions + * + * The SS555 board includes a CPLD to control on-board features and + * off-board devices. + */ +typedef struct cpld_ { + uint8_t cs3a[32]; /* Chip select 3A */ + uint8_t pad0[0x200000 - 0x000020]; + + uint8_t cs3b[32]; /* Chip select 3B */ + uint8_t pad2[0x400000 - 0x200020]; + + uint8_t cs3c[32]; /* Chip select 3C */ + uint8_t pad4[0x600000 - 0x400020]; + + uint8_t cs3d[32]; /* Chip select 3D */ + uint8_t pad6[0x800000 - 0x600020]; + + uint8_t serial_ints; /* Enable/disable serial interrupts */ + uint8_t serial_resets; /* Enable/disable serial resets */ + uint8_t serial_ack; /* Acknowledge serial transfers */ + uint8_t pad8[0xA00000 - 0x800003]; + + uint8_t iflash_writess; /* Enable/disable internal-flash writes */ + uint8_t nflash_writess; /* Enable/disable NAND-flash writes */ + uint8_t padA[0xC00000 - 0xA00002]; +} cpld_t; + +extern volatile cpld_t cpld; /* defined in linkcmds */ + +/* clock/p_clock.c */ +extern int BSP_disconnect_clock_handler (void); + +extern int BSP_connect_clock_handler (rtems_irq_hdl hdl); + +/* + * Prototypes for methods called from .S to support dependency tracking. + */ +void _InitSS555(void); + +#ifdef __cplusplus +} +#endif + +#endif /* !ASM */ + +#endif diff --git a/bsps/powerpc/ss555/include/bsp/irq.h b/bsps/powerpc/ss555/include/bsp/irq.h new file mode 100644 index 0000000000..44e39608b1 --- /dev/null +++ b/bsps/powerpc/ss555/include/bsp/irq.h @@ -0,0 +1,66 @@ +/* irq.h + * + * This include file describe the data structure and the functions implemented + * by rtems to write interrupt handlers. + * + * + * SS555 port sponsored by Defence Research and Development Canada - Suffield + * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) + * + * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: + * + * CopyRight (C) 1999 valette@crf.canon.fr + * + * This code is heavilly inspired by the public specification of STREAM V2 + * that can be found at : + * + * <http://www.chorus.com/Documentation/index.html> by following + * the STREAM API Specification Document link. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_SS555_IRQ_IRQ_H +#define LIBBSP_POWERPC_SS555_IRQ_IRQ_H + +#include <libcpu/irq.h> + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * These are no longer prototyped anywhere else. This appears to be + * remnants of the IRQ code upgrade. + * + * --joel 28 April 2010 + */ +int CPU_install_rtems_irq_handler(const rtems_irq_connect_data* irq); +int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data* irq); +int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq); +int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config); +int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config); +void C_default_exception_handler(CPU_Exception_frame* excPtr); + +/* + * The SS555 has no external interrupt controller chip, so use the standard + * routines from the CPU-dependent code. + */ +#define BSP_install_rtems_irq_handler(ptr) CPU_install_rtems_irq_handler(ptr) +#define BSP_get_current_rtems_irq_handler(ptr) CPU_get_current_rtems_irq_handler(ptr) +#define BSP_remove_rtems_irq_handler(ptr) CPU_remove_rtems_irq_handler(ptr) +#define BSP_rtems_irq_mngt_set(config) CPU_rtems_irq_mngt_set(config) +#define BSP_rtems_irq_mngt_get(config) CPU_rtems_irq_mngt_get(config) +#define BSP_rtems_irq_mng_init(cpuId) CPU_rtems_irq_mng_init(cpuId) + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* LIBBSP_POWERPC_SS555_IRQ_IRQ_H */ diff --git a/bsps/powerpc/ss555/include/tm27.h b/bsps/powerpc/ss555/include/tm27.h new file mode 100644 index 0000000000..5106801744 --- /dev/null +++ b/bsps/powerpc/ss555/include/tm27.h @@ -0,0 +1,56 @@ +/* + * @file + * @ingroup powerpc_ss555 + * @brief Implementations for interrupt mechanisms for Time Test 27 + */ + +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * + * The following require that IRQ7 be jumpered to ground. On the SS555, + * this can be done by shorting together CN5 pin 48 and CN5 pin 50. + */ + +#define MUST_WAIT_FOR_INTERRUPT 1 + +#define Install_tm27_vector( handler ) \ +{ \ + extern rtems_irq_connect_data tm27IrqData; \ + usiu.siel |= (1 << 17); \ + usiu.sipend |= (1 << 17); \ + \ + tm27IrqData.hdl = (rtems_irq_hdl)handler; \ + BSP_install_rtems_irq_handler (&tm27IrqData); \ +} + +#define Cause_tm27_intr() \ +{ \ + usiu.siel &= ~(1 << 17); \ +} + +#define Clear_tm27_intr() \ +{ \ + usiu.siel |= (1 << 17); \ + usiu.sipend |= (1 << 17); \ +} + +#define Lower_tm27_intr() \ +{ \ + ppc_cached_irq_mask |= (1 << 17); \ + usiu.simask = ppc_cached_irq_mask; \ +} + +#endif diff --git a/bsps/powerpc/t32mppc/headers.am b/bsps/powerpc/t32mppc/headers.am new file mode 100644 index 0000000000..57d3bd9be1 --- /dev/null +++ b/bsps/powerpc/t32mppc/headers.am @@ -0,0 +1,10 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/t32mppc/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/t32mppc/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/t32mppc/include/bsp/irq.h diff --git a/bsps/powerpc/t32mppc/include/bsp.h b/bsps/powerpc/t32mppc/include/bsp.h new file mode 100644 index 0000000000..c27f235ef6 --- /dev/null +++ b/bsps/powerpc/t32mppc/include/bsp.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_T32MPPC_BSP_H +#define LIBBSP_POWERPC_T32MPPC_BSP_H + +#include <bspopts.h> + +#ifndef ASM + +#include <rtems.h> + +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +extern uint32_t bsp_time_base_frequency; + +void t32mppc_decrementer_dispatch(void); + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_T32MPPC_BSP_H */ diff --git a/bsps/powerpc/t32mppc/include/bsp/irq.h b/bsps/powerpc/t32mppc/include/bsp/irq.h new file mode 100644 index 0000000000..0053aa5ac1 --- /dev/null +++ b/bsps/powerpc/t32mppc/include/bsp/irq.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_T32MPPC_IRQ_H +#define LIBBSP_POWERPC_T32MPPC_IRQ_H + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> +#include <rtems/score/processormask.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX 0 + +RTEMS_INLINE_ROUTINE void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +) +{ + (void) vector; + (void) affinity; +} + +RTEMS_INLINE_ROUTINE void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +) +{ + (void) vector; + _Processor_mask_From_index( affinity, 0 ); +} + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_POWERPC_T32MPPC_IRQ_H */ diff --git a/bsps/powerpc/t32mppc/include/tm27.h b/bsps/powerpc/t32mppc/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/t32mppc/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/tqm8xx/headers.am b/bsps/powerpc/tqm8xx/headers.am new file mode 100644 index 0000000000..a3c97f53da --- /dev/null +++ b/bsps/powerpc/tqm8xx/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/spi.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/tqm8xx/include/bsp/tqm.h diff --git a/bsps/powerpc/tqm8xx/include/bsp.h b/bsps/powerpc/tqm8xx/include/bsp.h new file mode 100644 index 0000000000..5c8eae81b4 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp.h @@ -0,0 +1,169 @@ +/* + * RTEMS TQM8xx BSP + * This include file contains all board IO definitions. + */ + +/* + * This file has been adapted to MPC8xx by: + * Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + * Copyright (c) 2008 + * Embedded Brains GmbH + * Obere Lagerstr. 30 + * D-82178 Puchheim + * Germany + * rtems@embedded-brains.de + * + * COPYRIGHT (c) 1989-2008. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_POWERPC_TQM8XX_BSP_H +#define LIBBSP_POWERPC_TQM8XX_BSP_H + +/* + * indicate, that BSP is booted via TQMMon + */ +#define BSP_HAS_TQMMON + +#include <libcpu/powerpc-utility.h> + +LINKER_SYMBOL(TopRamReserved); + +LINKER_SYMBOL( bsp_ram_start); +LINKER_SYMBOL( bsp_ram_end); +LINKER_SYMBOL( bsp_ram_size); + +LINKER_SYMBOL( bsp_rom_start); +LINKER_SYMBOL( bsp_rom_end); +LINKER_SYMBOL( bsp_rom_size); + +LINKER_SYMBOL( bsp_section_text_start); +LINKER_SYMBOL( bsp_section_text_end); +LINKER_SYMBOL( bsp_section_text_size); + +LINKER_SYMBOL( bsp_section_data_start); +LINKER_SYMBOL( bsp_section_data_end); +LINKER_SYMBOL( bsp_section_data_size); + +LINKER_SYMBOL( bsp_section_bss_start); +LINKER_SYMBOL( bsp_section_bss_end); +LINKER_SYMBOL( bsp_section_bss_size); + +LINKER_SYMBOL( bsp_interrupt_stack_start); +LINKER_SYMBOL( bsp_interrupt_stack_end); +LINKER_SYMBOL( bsp_interrupt_stack_size); + +LINKER_SYMBOL( bsp_work_area_start); + +#ifndef ASM + +#include <bspopts.h> + +#include <rtems.h> +#include <rtems/irq.h> +#include <mpc8xx.h> +#include <mpc8xx/cpm.h> +#include <mpc8xx/mmu.h> +#include <mpc8xx/console.h> +#include <bsp/vectors.h> +#include <bsp/tqm.h> +#include <libcpu/powerpc-utility.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Network driver configuration + */ +struct rtems_bsdnet_ifconfig; + +#if BSP_USE_NETWORK_FEC +extern int rtems_fec_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); +#define RTEMS_BSP_FEC_NETWORK_DRIVER_NAME "fec1" +#define RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH rtems_fec_enet_driver_attach +#endif + +#if BSP_USE_NETWORK_SCC +extern int rtems_scc_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); +#define RTEMS_BSP_SCC_NETWORK_DRIVER_NAME "scc1" +#define RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH rtems_scc_enet_driver_attach +#endif + +#if BSP_USE_NETWORK_FEC +#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_FEC_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH +#elif BSP_USE_NETWORK_SCC +#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_SCC_NETWORK_DRIVER_NAME +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH +#endif +/* + * We need to decide how much memory will be non-cacheable. This + * will mainly be memory that will be used in DMA (network and serial + * buffers). + */ +#define NOCACHE_MEM_SIZE 512*1024 + +/* + * indicate, that BSP has IDE driver + */ +#undef RTEMS_BSP_HAS_IDE_DRIVER + +/* + * SPI driver configuration + */ + + /* select values for SPI addressing */ +#define PGHPLUS_SPI_ADDR_EEPROM 0 +#define PGHPLUS_SPI_ADDR_DISP4 1 + /* NOTE: DISP4 occupies two consecutive addresses for data and control port */ +#define PGHPLUS_SPI_ADDR_DISP4_DATA (PGHPLUS_SPI_ADDR_DISP4) +#define PGHPLUS_SPI_ADDR_DISP4_CTRL (PGHPLUS_SPI_ADDR_DISP4_DATA+1) + + /* bit masks for Port B lines */ +#define PGHPLUS_PB_SPI_EEP_CE_MSK (1<< 0) +#define PGHPLUS_PB_SPI_DISP4_RS_MSK (1<<15) +#define PGHPLUS_PB_SPI_DISP4_CE_MSK (1<<14) + +/* + * our (internal) bus frequency + */ +extern uint32_t BSP_bus_frequency; + +/* + * Interfaces to required Clock Driver support methods + */ +int BSP_disconnect_clock_handler(void); +int BSP_connect_clock_handler (rtems_irq_hdl); + +extern uint32_t bsp_clock_speed; + +char serial_getc(void); + +int serial_tstc(void); + +void serial_init(void); + +int mbx8xx_console_get_configuration(void); + +void _InitTQM8xx (void); + +rtems_status_code bsp_register_spi(void); + +void *bsp_idle_thread( uintptr_t ignored ); + +void cpu_init(void); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h b/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h new file mode 100644 index 0000000000..c1c414e25f --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h @@ -0,0 +1,477 @@ +/*===============================================================*\ +| Project: RTEMS BSP support for TQ modules | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains definitions to interact with TQC's | +| processor modules | +\*===============================================================*/ +/* derived from mbx8xx BSP */ +/* + * MPC8xx Internal Memory Map + * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) + * + * The I/O on the MPC860 is comprised of blocks of special registers + * and the dual port ram for the Communication Processor Module. + * Within this space are functional units such as the SIU, memory + * controller, system timers, and other control functions. It is + * a combination that I found difficult to separate into logical + * functional files.....but anyone else is welcome to try. -- Dan + */ +#ifndef __IMMAP_8XX__ +#define __IMMAP_8XX__ + +/* System configuration registers. +*/ +typedef struct sys_conf { + unsigned int sc_siumcr; + unsigned int sc_sypcr; + unsigned int sc_swt; + char res1[2]; + unsigned short sc_swsr; + unsigned int sc_sipend; + unsigned int sc_simask; + unsigned int sc_siel; + unsigned int sc_sivec; + unsigned int sc_tesr; + char res2[0xc]; + unsigned int sc_sdcr; + char res3[0x4c]; +} sysconf8xx_t; + +/* PCMCIA configuration registers. +*/ +typedef struct pcmcia_conf { + unsigned int pcmc_pbr0; + unsigned int pcmc_por0; + unsigned int pcmc_pbr1; + unsigned int pcmc_por1; + unsigned int pcmc_pbr2; + unsigned int pcmc_por2; + unsigned int pcmc_pbr3; + unsigned int pcmc_por3; + unsigned int pcmc_pbr4; + unsigned int pcmc_por4; + unsigned int pcmc_pbr5; + unsigned int pcmc_por5; + unsigned int pcmc_pbr6; + unsigned int pcmc_por6; + unsigned int pcmc_pbr7; + unsigned int pcmc_por7; + char res1[0x20]; + unsigned int pcmc_pgcra; + unsigned int pcmc_pgcrb; + unsigned int pcmc_pscr; + char res2[4]; + unsigned int pcmc_pipr; + char res3[4]; + unsigned int pcmc_per; + char res4[4]; +} pcmconf8xx_t; + +/* Memory controller registers. +*/ +typedef struct mem_ctlr { + unsigned int memc_br0; + unsigned int memc_or0; + unsigned int memc_br1; + unsigned int memc_or1; + unsigned int memc_br2; + unsigned int memc_or2; + unsigned int memc_br3; + unsigned int memc_or3; + unsigned int memc_br4; + unsigned int memc_or4; + unsigned int memc_br5; + unsigned int memc_or5; + unsigned int memc_br6; + unsigned int memc_or6; + unsigned int memc_br7; + unsigned int memc_or7; + char res1[0x24]; + unsigned int memc_mar; + unsigned int memc_mcr; + char res2[4]; + unsigned int memc_mamr; + unsigned int memc_mbmr; + unsigned short memc_mstat; + unsigned short memc_mptpr; + unsigned int memc_mdr; + char res3[0x80]; +} memctl8xx_t; + +/* System Integration Timers. +*/ +typedef struct sys_int_timers { + unsigned short sit_tbscr; + unsigned int sit_tbreff0; + unsigned int sit_tbreff1; + char res1[0x14]; + unsigned short sit_rtcsc; + unsigned int sit_rtc; + unsigned int sit_rtsec; + unsigned int sit_rtcal; + char res2[0x10]; + unsigned short sit_piscr; + char res3[2]; + unsigned int sit_pitc; + unsigned int sit_pitr; + char res4[0x34]; +} sit8xx_t; + +#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) +#define TBSCR_REFA ((unsigned short)0x0080) +#define TBSCR_REFB ((unsigned short)0x0040) +#define TBSCR_REFAE ((unsigned short)0x0008) +#define TBSCR_REFBE ((unsigned short)0x0004) +#define TBSCR_TBF ((unsigned short)0x0002) +#define TBSCR_TBE ((unsigned short)0x0001) + +#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) +#define RTCSC_SEC ((unsigned short)0x0080) +#define RTCSC_ALR ((unsigned short)0x0040) +#define RTCSC_38K ((unsigned short)0x0010) +#define RTCSC_SIE ((unsigned short)0x0008) +#define RTCSC_ALE ((unsigned short)0x0004) +#define RTCSC_RTF ((unsigned short)0x0002) +#define RTCSC_RTE ((unsigned short)0x0001) + +#define PISCR_PIRQ_MASK ((unsigned short)0xff00) +#define PISCR_PS ((unsigned short)0x0080) +#define PISCR_PIE ((unsigned short)0x0004) +#define PISCR_PTF ((unsigned short)0x0002) +#define PISCR_PTE ((unsigned short)0x0001) + +/* Clocks and Reset. +*/ +typedef struct clk_and_reset { + unsigned int car_sccr; + unsigned int car_plprcr; + unsigned int car_rsr; + char res[0x74]; /* Reserved area */ +} car8xx_t; + +/* System Integration Timers keys. +*/ +typedef struct sitk { + unsigned int sitk_tbscrk; + unsigned int sitk_tbreff0k; + unsigned int sitk_tbreff1k; + unsigned int sitk_tbk; + char res1[0x10]; + unsigned int sitk_rtcsck; + unsigned int sitk_rtck; + unsigned int sitk_rtseck; + unsigned int sitk_rtcalk; + char res2[0x10]; + unsigned int sitk_piscrk; + unsigned int sitk_pitck; + char res3[0x38]; +} sitk8xx_t; + +/* Clocks and reset keys. +*/ +typedef struct cark { + unsigned int cark_sccrk; + unsigned int cark_plprcrk; + unsigned int cark_rsrk; + char res[0x474]; +} cark8xx_t; + +/* The key to unlock registers maintained by keep-alive power. +*/ +#define KAPWR_KEY ((unsigned int)0x55ccaa33) + +/* LCD interface. MPC821 Only. +*/ +typedef struct lcd { + unsigned short lcd_lcolr[16]; + char res[0x20]; + unsigned int lcd_lccr; + unsigned int lcd_lchcr; + unsigned int lcd_lcvcr; + char res2[4]; + unsigned int lcd_lcfaa; + unsigned int lcd_lcfba; + char lcd_lcsr; + char res3[0x7]; +} lcd8xx_t; + +/* I2C +*/ +typedef struct i2c { + unsigned char i2c_i2mod; + char res1[3]; + unsigned char i2c_i2add; + char res2[3]; + unsigned char i2c_i2brg; + char res3[3]; + unsigned char i2c_i2com; + char res4[3]; + unsigned char i2c_i2cer; + char res5[3]; + unsigned char i2c_i2cmr; + char res6[0x8b]; +} i2c8xx_t; + +/* DMA control/status registers. +*/ +typedef struct sdma_csr { + char res1[4]; + unsigned int sdma_sdar; + unsigned char sdma_sdsr; + char res3[3]; + unsigned char sdma_sdmr; + char res4[3]; + unsigned char sdma_idsr1; + char res5[3]; + unsigned char sdma_idmr1; + char res6[3]; + unsigned char sdma_idsr2; + char res7[3]; + unsigned char sdma_idmr2; + char res8[0x13]; +} sdma8xx_t; + +/* Communication Processor Module Interrupt Controller. +*/ +typedef struct cpm_ic { + unsigned short cpic_civr; + char res[0xe]; + unsigned int cpic_cicr; + unsigned int cpic_cipr; + unsigned int cpic_cimr; + unsigned int cpic_cisr; +} cpic8xx_t; + +/* Input/Output Port control/status registers. +*/ +typedef struct io_port { + unsigned short iop_padir; + unsigned short iop_papar; + unsigned short iop_paodr; + unsigned short iop_padat; + char res1[8]; + unsigned short iop_pcdir; + unsigned short iop_pcpar; + unsigned short iop_pcso; + unsigned short iop_pcdat; + unsigned short iop_pcint; + char res2[6]; + unsigned short iop_pddir; + unsigned short iop_pdpar; + char res3[2]; + unsigned short iop_pddat; + char res4[8]; +} iop8xx_t; + +/* Communication Processor Module Timers +*/ +typedef struct cpm_timers { + unsigned short cpmt_tgcr; + char res1[0xe]; + unsigned short cpmt_tmr1; + unsigned short cpmt_tmr2; + unsigned short cpmt_trr1; + unsigned short cpmt_trr2; + unsigned short cpmt_tcr1; + unsigned short cpmt_tcr2; + unsigned short cpmt_tcn1; + unsigned short cpmt_tcn2; + unsigned short cpmt_tmr3; + unsigned short cpmt_tmr4; + unsigned short cpmt_trr3; + unsigned short cpmt_trr4; + unsigned short cpmt_tcr3; + unsigned short cpmt_tcr4; + unsigned short cpmt_tcn3; + unsigned short cpmt_tcn4; + unsigned short cpmt_ter1; + unsigned short cpmt_ter2; + unsigned short cpmt_ter3; + unsigned short cpmt_ter4; + char res2[8]; +} cpmtimer8xx_t; + +/* Finally, the Communication Processor stuff..... +*/ +typedef struct scc { /* Serial communication channels */ + unsigned int scc_gsmrl; + unsigned int scc_gsmrh; + unsigned short scc_pmsr; + char res1[2]; + unsigned short scc_todr; + unsigned short scc_dsr; + unsigned short scc_scce; + char res2[2]; + unsigned short scc_sccm; + char res3; + unsigned char scc_sccs; + char res4[8]; +} scc_t; + +typedef struct smc { /* Serial management channels */ + char res1[2]; + unsigned short smc_smcmr; + char res2[2]; + unsigned char smc_smce; + char res3[3]; + unsigned char smc_smcm; + char res4[5]; +} smc_t; + +/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but + * it fits within the address space. + */ +typedef struct fec { + unsigned int fec_addr_low; /* LS 32 bits of station address */ + unsigned short fec_addr_high; /* MS 16 bits of address */ + unsigned short res1; + unsigned int fec_hash_table_high; + unsigned int fec_hash_table_low; + unsigned int fec_r_des_start; + unsigned int fec_x_des_start; + unsigned int fec_r_buff_size; + unsigned int res2[9]; + unsigned int fec_ecntrl; + unsigned int fec_ievent; + unsigned int fec_imask; + unsigned int fec_ivec; + unsigned int fec_r_des_active; + unsigned int fec_x_des_active; + unsigned int res3[10]; + unsigned int fec_mii_data; + unsigned int fec_mii_speed; + unsigned int res4[17]; + unsigned int fec_r_bound; + unsigned int fec_r_fstart; + unsigned int res5[6]; + unsigned int fec_x_fstart; + unsigned int res6[17]; + unsigned int fec_fun_code; + unsigned int res7[3]; + unsigned int fec_r_cntrl; + unsigned int fec_r_hash; + unsigned int res8[14]; + unsigned int fec_x_cntrl; + unsigned int res9[0x1e]; +} fec_t; + +typedef struct comm_proc { + /* General control and status registers. + */ + unsigned short cp_cpcr; + char res1[2]; + unsigned short cp_rccr; + char res2[6]; + unsigned short cp_cpmcr1; + unsigned short cp_cpmcr2; + unsigned short cp_cpmcr3; + unsigned short cp_cpmcr4; + char res3[2]; + unsigned short cp_rter; + char res4[2]; + unsigned short cp_rtmr; + char res5[0x14]; + + /* Baud rate generators. + */ + unsigned int cp_brgc1; + unsigned int cp_brgc2; + unsigned int cp_brgc3; + unsigned int cp_brgc4; + + /* Serial Communication Channels. + */ + scc_t cp_scc[4]; + + /* Serial Management Channels. + */ + smc_t cp_smc[2]; + + /* Serial Peripheral Interface. + */ + unsigned short cp_spmode; + char res6[4]; + unsigned char cp_spie; + char res7[3]; + unsigned char cp_spim; + char res8[2]; + unsigned char cp_spcom; + char res9[2]; + + /* Parallel Interface Port. + */ + char res10[2]; + unsigned short cp_pipc; + char res11[2]; + unsigned short cp_ptpr; + unsigned int cp_pbdir; + unsigned int cp_pbpar; + char res12[2]; + unsigned short cp_pbodr; + unsigned int cp_pbdat; + char res13[0x18]; + + /* Serial Interface and Time Slot Assignment. + */ + unsigned int cp_simode; + unsigned char cp_sigmr; + char res14; + unsigned char cp_sistr; + unsigned char cp_sicmr; + char res15[4]; + unsigned int cp_sicr; + unsigned int cp_sirp; + char res16[0x10c]; + unsigned char cp_siram[0x200]; + + /* The fast ethernet controller is not really part of the CPM, + * but it resides in the address space. + */ + fec_t cp_fec; + char res18[0x1000]; + + /* Dual Ported RAM follows. + * There are many different formats for this memory area + * depending upon the devices used and options chosen. + */ + unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ + unsigned char res19[0xc00]; + unsigned char cp_dparam[0x400]; /* Parameter RAM */ +} cpm8xx_t; + +/* Internal memory map. +*/ +typedef struct immap { + sysconf8xx_t im_siu_conf; /* SIU Configuration */ + pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ + memctl8xx_t im_memctl; /* Memory Controller */ + sit8xx_t im_sit; /* System integration timers */ + car8xx_t im_clkrst; /* Clocks and reset */ + sitk8xx_t im_sitk; /* Sys int timer keys */ + cark8xx_t im_clkrstk; /* Clocks and reset keys */ + lcd8xx_t im_lcd; /* LCD (821 only) */ + i2c8xx_t im_i2c; /* I2C control/status */ + sdma8xx_t im_sdma; /* SDMA control/status */ + cpic8xx_t im_cpic; /* CPM Interrupt Controller */ + iop8xx_t im_ioport; /* IO Port control/status */ + cpmtimer8xx_t im_cpmtimer; /* CPM timers */ + cpm8xx_t im_cpm; /* Communication processor */ +} immap_t; + +#endif /* __IMMAP_8XX__ */ diff --git a/bsps/powerpc/tqm8xx/include/bsp/irq.h b/bsps/powerpc/tqm8xx/include/bsp/irq.h new file mode 100644 index 0000000000..2d66829037 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/irq.h @@ -0,0 +1,160 @@ +/*===============================================================*\ +| Project: RTEMS TQM8xx BSP | ++-----------------------------------------------------------------+ +| This file has been adapted to MPC8xx by | +| Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | +| Copyright (c) 2008 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | +| | +| See the other copyright notice below for the original parts. | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the console driver | +\*===============================================================*/ +/* derived from: generic MPC83xx BSP */ +#ifndef TQM8xx_IRQ_IRQ_H +#define TQM8xx_IRQ_IRQ_H + +#include <stdbool.h> + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_SIU_PER_IRQ_NUMBER 16 +#define BSP_SIU_IRQ_LOWEST_OFFSET 0 +#define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET\ + +BSP_SIU_PER_IRQ_NUMBER-1) + +#define BSP_IS_SIU_IRQ(irqnum) \ + (((irqnum) >= BSP_SIU_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_SIU_IRQ_MAX_OFFSET)) + +#define BSP_CPM_PER_IRQ_NUMBER 32 +#define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_MAX_OFFSET+1) +#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET\ + +BSP_CPM_PER_IRQ_NUMBER-1) + +#define BSP_IS_CPM_IRQ(irqnum) \ + (((irqnum) >= BSP_CPM_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_CPM_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 1 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_SIU_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_SIU_IRQ(irqnum) \ + || BSP_IS_CPM_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_SIU_EXT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 0, + BSP_SIU_INT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 1, + BSP_SIU_EXT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 2, + BSP_SIU_INT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 3, + BSP_SIU_EXT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 4, + BSP_SIU_INT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 5, + BSP_SIU_EXT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 6, + BSP_SIU_INT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 7, + BSP_SIU_EXT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 8, + BSP_SIU_INT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 9, + BSP_SIU_EXT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 10, + BSP_SIU_INT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 11, + BSP_SIU_EXT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 12, + BSP_SIU_INT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 13, + BSP_SIU_EXT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 14, + BSP_SIU_INT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 15, + BSP_SIU_IRQ_LAST = BSP_SIU_IRQ_MAX_OFFSET, + /* + * Some CPM IRQ symbolic name definition + */ + BSP_CPM_IRQ_ERROR = (BSP_CPM_IRQ_LOWEST_OFFSET), + BSP_CPM_IRQ_PARALLEL_IO_PC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 1), + BSP_CPM_IRQ_PARALLEL_IO_PC5 = (BSP_CPM_IRQ_LOWEST_OFFSET + 2), + BSP_CPM_IRQ_SMC2_OR_PIP = (BSP_CPM_IRQ_LOWEST_OFFSET + 3), + BSP_CPM_IRQ_SMC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 4), + BSP_CPM_IRQ_SPI = (BSP_CPM_IRQ_LOWEST_OFFSET + 5), + BSP_CPM_IRQ_PARALLEL_IO_PC6 = (BSP_CPM_IRQ_LOWEST_OFFSET + 6), + BSP_CPM_IRQ_TIMER_4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 7), + BSP_CPM_IRQ_PARALLEL_IO_PC7 = (BSP_CPM_IRQ_LOWEST_OFFSET + 9), + BSP_CPM_IRQ_PARALLEL_IO_PC8 = (BSP_CPM_IRQ_LOWEST_OFFSET + 10), + BSP_CPM_IRQ_PARALLEL_IO_PC9 = (BSP_CPM_IRQ_LOWEST_OFFSET + 11), + BSP_CPM_IRQ_TIMER_3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 12), + BSP_CPM_IRQ_PARALLEL_IO_PC10= (BSP_CPM_IRQ_LOWEST_OFFSET + 14), + BSP_CPM_IRQ_PARALLEL_IO_PC11= (BSP_CPM_IRQ_LOWEST_OFFSET + 15), + BSP_CPM_I2C = (BSP_CPM_IRQ_LOWEST_OFFSET + 16), + BSP_CPM_RISC_TIMER_TABLE = (BSP_CPM_IRQ_LOWEST_OFFSET + 17), + BSP_CPM_IRQ_TIMER_2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 18), + BSP_CPM_IDMA2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 20), + BSP_CPM_IDMA1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 21), + BSP_CPM_SDMA_CHANNEL_BUS_ERR= (BSP_CPM_IRQ_LOWEST_OFFSET + 22), + BSP_CPM_IRQ_PARALLEL_IO_PC12= (BSP_CPM_IRQ_LOWEST_OFFSET + 23), + BSP_CPM_IRQ_PARALLEL_IO_PC13= (BSP_CPM_IRQ_LOWEST_OFFSET + 24), + BSP_CPM_IRQ_TIMER_1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 25), + BSP_CPM_IRQ_PARALLEL_IO_PC14= (BSP_CPM_IRQ_LOWEST_OFFSET + 26), + BSP_CPM_IRQ_SCC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 27), + BSP_CPM_IRQ_SCC3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 28), + BSP_CPM_IRQ_SCC2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 29), + BSP_CPM_IRQ_SCC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 30), + BSP_CPM_IRQ_PARALLEL_IO_PC15= (BSP_CPM_IRQ_LOWEST_OFFSET + 31), + BSP_CPM_IRQ_LAST = BSP_CPM_IRQ_MAX_OFFSET, + } rtems_irq_symbolic_name; + + /* + * Symbolic name for CPM interrupt on SIU Internal level 2 + */ +#define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2 +#define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6 +#define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3 + +#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET + +#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET + +extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine); + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* TQM8XX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/tqm8xx/include/bsp/spi.h b/bsps/powerpc/tqm8xx/include/bsp/spi.h new file mode 100644 index 0000000000..e2af971c8d --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/spi.h @@ -0,0 +1,146 @@ +/*===============================================================*\ +| Project: RTEMS support for MPC8xx | ++-----------------------------------------------------------------+ +| Copyright (c) 2009 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains the MPC8xx SPI driver declarations | +\*===============================================================*/ +#ifndef _M8XX_SPIDRV_H +#define _M8XX_SPIDRV_H + +#include <mpc8xx.h> +#include <rtems/libi2c.h> +#include <rtems/irq.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct m8xx_spi_softc { + int initialized; + rtems_id irq_sema_id; + rtems_isr_entry old_handler; + m8xxBufferDescriptor_t *rx_bd; + m8xxBufferDescriptor_t *tx_bd; +} m8xx_spi_softc_t ; + +typedef struct { + rtems_libi2c_bus_t bus_desc; + m8xx_spi_softc_t softc; +} m8xx_spi_desc_t; + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code m8xx_spi_init +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| initialize the driver | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh /* bus specifier structure */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| o = ok or error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int m8xx_spi_read_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| receive some bytes from SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to store bytes */ + int len /* number of bytes to receive */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes received or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int m8xx_spi_write_bytes +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| send some bytes to SPI device | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + unsigned char *buf, /* buffer to send */ + int len /* number of bytes to send */ + + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| number of bytes sent or (negative) error code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +rtems_status_code m8xx_spi_set_tfr_mode +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| set SPI to desired baudrate/clock mode/character mode | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +/*=========================================================================*\ +| Function: | +\*-------------------------------------------------------------------------*/ +int m8xx_spi_ioctl +( +/*-------------------------------------------------------------------------*\ +| Purpose: | +| perform selected ioctl function for SPI | ++---------------------------------------------------------------------------+ +| Input Parameters: | +\*-------------------------------------------------------------------------*/ + rtems_libi2c_bus_t *bh, /* bus specifier structure */ + int cmd, /* ioctl command code */ + void *arg /* additional argument array */ + ); +/*-------------------------------------------------------------------------*\ +| Return Value: | +| rtems_status_code | +\*=========================================================================*/ + +#ifdef __cplusplus +} +#endif + + +#endif /* _M8XX_SPIDRV_H */ diff --git a/bsps/powerpc/tqm8xx/include/bsp/tqm.h b/bsps/powerpc/tqm8xx/include/bsp/tqm.h new file mode 100644 index 0000000000..11f6001304 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/bsp/tqm.h @@ -0,0 +1,51 @@ +/*===============================================================*\ +| Project: RTEMS BSP support for TQ modules | ++-----------------------------------------------------------------+ +| Partially based on the code references which are named below. | +| Adaptions, modifications, enhancements and any recent parts of | +| the code are: | +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file contains definitions to interact with TQC's | +| processor modules | +\*===============================================================*/ + +#ifndef __TQM_H__ +#define __TQM_H__ +#include <rtems.h> + +typedef struct { + uint32_t sdram_size; /* existing SDRAM size */ + uint32_t flash_base; /* start address flash */ + uint32_t flash_size; /* existing Flash size */ + uint32_t flash_offset; + uint32_t sram_base; /* start address sram */ + uint32_t sram_size; /* existing sram size */ + uint32_t immr_base; /* start address internal memory map */ + uint32_t reboot; /* reboot flag */ + uint8_t ip_addr[4]; /* IP address */ + uint8_t eth_addr[6]; /* ethernet (MAC) address */ + uint8_t gap_42[2]; /* gap for alignment */ + void (*put_char)(int c); /* function to output characters */ +} tqm_bd_info_t; + +#define TQM_BD_INFO_ADDR 0x3400 +#define TQM_BD_INFO (*(tqm_bd_info_t *)TQM_BD_INFO_ADDR) + +#define TQM_CONF_INFO_BLOCK_ADDR 0x4001fe00 + +#define IMAP_ADDR ((unsigned int)0xfa200000) +#define IMAP_SIZE ((unsigned int)(64 * 1024)) + +#endif /* __TQM_H__ */ diff --git a/bsps/powerpc/tqm8xx/include/tm27.h b/bsps/powerpc/tqm8xx/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/tqm8xx/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/virtex/headers.am b/bsps/powerpc/virtex/headers.am new file mode 100644 index 0000000000..9feceaf16d --- /dev/null +++ b/bsps/powerpc/virtex/headers.am @@ -0,0 +1,13 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/tm27.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/xiltemac.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex/include/xparameters_dflt.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex/include/bsp/opbintctrl.h diff --git a/bsps/powerpc/virtex/include/bsp.h b/bsps/powerpc/virtex/include/bsp.h new file mode 100644 index 0000000000..2f61ee2517 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp.h @@ -0,0 +1,84 @@ +/* bsp.h + * + * This include file contains all GEN405 board IO definitions. + * + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_POWERPC_VIRTEX_BSP_H +#define LIBBSP_POWERPC_VIRTEX_BSP_H + +#include <bspopts.h> + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include <rtems.h> +#include <bsp/irq.h> +#include <bsp/vectors.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN + +/* miscellaneous stuff assumed to exist */ +extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ + +/* Network Defines */ +#if 1 /* EB/doe changes */ +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#else +#include "xiltemac.h" +#define RTEMS_BSP_NETWORK_DRIVER_NAME XILTEMAC_DRIVER_PREFIX +#endif +struct rtems_bsdnet_ifconfig; +extern int xilTemac_driver_attach(struct rtems_bsdnet_ifconfig*, int ); +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH xilTemac_driver_attach + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif diff --git a/bsps/powerpc/virtex/include/bsp/irq.h b/bsps/powerpc/virtex/include/bsp/irq.h new file mode 100644 index 0000000000..1ce5b68b98 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp/irq.h @@ -0,0 +1,94 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX_IRQ_IRQ_H +#define VIRTEX_IRQ_IRQ_H + +#include <rtems/irq.h> +#include <rtems/irq-extension.h> +#include <bsp/opbintctrl.h> + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ +#define BSP_OPBINTC_PER_IRQ_NUMBER XPAR_INTC_MAX_NUM_INTR_INPUTS +#define BSP_OPBINTC_IRQ_LOWEST_OFFSET 0 +#define BSP_OPBINTC_IRQ_MAX_OFFSET (BSP_OPBINTC_IRQ_LOWEST_OFFSET\ + +BSP_OPBINTC_PER_IRQ_NUMBER-1) + +#define BSP_IS_OPBINTC_IRQ(irqnum) \ + (((irqnum) >= BSP_OPBINTC_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_OPBINTC_IRQ_MAX_OFFSET)) +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_OPBINTC_IRQ_MAX_OFFSET+1) +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_OPBINTC_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) \ + (BSP_IS_PROCESSOR_IRQ(irqnum) \ + || BSP_IS_OPBINTC_IRQ(irqnum)) + +#define BSP_INTERRUPT_VECTOR_MIN 0 +#define BSP_INTERRUPT_VECTOR_MAX BSP_PROCESSOR_IRQ_MAX_OFFSET + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_OPBINTC_IRQ_FIRST = BSP_OPBINTC_IRQ_LOWEST_OFFSET, + /* + * Note: for this BSP, the peripheral names are derived + * from the Xilinx parameter file + */ + BSP_OPBINTC_IRQ_LAST = BSP_OPBINTC_IRQ_MAX_OFFSET, + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + +#define BSP_OPBINTC_XPAR(xname) (BSP_OPBINTC_IRQ_LOWEST_OFFSET+xname) + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex/include/bsp/opbintctrl.h b/bsps/powerpc/virtex/include/bsp/opbintctrl.h new file mode 100644 index 0000000000..4ade0e48f8 --- /dev/null +++ b/bsps/powerpc/virtex/include/bsp/opbintctrl.h @@ -0,0 +1,75 @@ +/* opbintctrl.h + * + * This file contains definitions and declarations for the + * Xilinx Off Processor Bus (OPB) Interrupt Controller + * + * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca> + * COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _INCLUDE_OPBINTCTRL_H +#define _INCLUDE_OPBINTCTRL_H + +#include <rtems.h> +#include <rtems/system.h> +#include <rtems/score/isr.h> +#include <rtems/irq.h> +#include <bspopts.h> +#include RTEMS_XPARAMETERS_H + +#define USE_GREG_INTERRUPTS + +#ifdef __cplusplus +extern "C" { +#endif + + +/* extern XIntc InterruptController; + */ + + +/* Maximum number of IRQs. Defined in vhdl model */ +#define OPB_INTC_IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +/* Width of INTC registers. Defined in vhdl model */ +#define OPB_INTC_REGISTER_WIDTH 32 + +/* Base Register address and register offsets. Defined in vhdl model */ +#define OPB_INTC_BASE XPAR_INTC_SINGLE_BASEADDR + + + + + +/* Interrupt Status Register */ +#define OPB_INTC_ISR 0x0 +/* Interrupt Pending Register (ISR && IER) */ +#define OPB_INTC_IPR 0x4 +/* Interrupt Enable Register */ +#define OPB_INTC_IER 0x8 +/* Interrupt Acknowledge Register */ +#define OPB_INTC_IAR 0xC +/* Set Interrupt Enable (same as read/mask/write to IER) */ +#define OPB_INTC_SIE 0x10 +/* Clear Interrupt Enable (same as read/mask/write to IER) */ +#define OPB_INTC_CIE 0x14 +/* Interrupt Vector Address (highest priority vector number from IPR) */ +#define OPB_INTC_IVR 0x18 +/* Master Enable Register */ +#define OPB_INTC_MER 0x1C + +/* Master Enable Register: Hardware Interrupt Enable */ +#define OPB_INTC_MER_HIE 0x2 + +/* Master Enable Register: Master IRQ Enable */ +#define OPB_INTC_MER_ME 0x1 + +#ifdef __cplusplus +} +#endif + +#endif /* _INCLUDE_OPBINTCTRL_H */ diff --git a/bsps/powerpc/virtex/include/tm27.h b/bsps/powerpc/virtex/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/virtex/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/virtex/include/xiltemac.h b/bsps/powerpc/virtex/include/xiltemac.h new file mode 100644 index 0000000000..185b89bdc1 --- /dev/null +++ b/bsps/powerpc/virtex/include/xiltemac.h @@ -0,0 +1,375 @@ +/* + * Driver for plb inteface of the xilinx temac 3.00a + * + * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca> + * Copyright (c) 2007 Linn Products Ltd, Scotland. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef _XILINX_TEMAC_ +#define _XILINX_TEMAC_ +#include <rtems/irq.h> + + +#define XILTEMAC_DRIVER_PREFIX "xiltemac" + +#define DRIVER_PREFIX XILTEMAC_DRIVER_PREFIX + + +/** IPIF interrupt and reset registers + */ +#define XTE_DISR_OFFSET 0x00000000 /**< Device interrupt status */ +#define XTE_DIPR_OFFSET 0x00000004 /**< Device interrupt pending */ +#define XTE_DIER_OFFSET 0x00000008 /**< Device interrupt enable */ +#define XTE_DIIR_OFFSET 0x00000018 /**< Device interrupt ID */ +#define XTE_DGIE_OFFSET 0x0000001C /**< Device global interrupt enable */ +#define XTE_IPISR_OFFSET 0x00000020 /**< IP interrupt status */ +#define XTE_IPIER_OFFSET 0x00000028 /**< IP interrupt enable */ +#define XTE_DSR_OFFSET 0x00000040 /**< Device software reset (write) */ + +/** IPIF transmit fifo + */ +#define XTE_PFIFO_TX_BASE_OFFSET 0x00002000 /**< Packet FIFO Tx channel */ +#define XTE_PFIFO_TX_VACANCY_OFFSET 0x00002004 /**< Packet Fifo Tx Vacancy */ +#define XTE_PFIFO_TX_DATA_OFFSET 0x00002100 /**< IPIF Tx packet fifo port */ + +/** IPIF receive fifo + */ +#define XTE_PFIFO_RX_BASE_OFFSET 0x00002010 /**< Packet FIFO Rx channel */ +#define XTE_PFIFO_RX_VACANCY_OFFSET 0x00002014 /**< Packet Fifo Rx Vacancy */ +#define XTE_PFIFO_RX_DATA_OFFSET 0x00002200 /**< IPIF Rx packet fifo port */ + +/** IPIF fifo masks + */ +#define XTE_PFIFO_COUNT_MASK 0x00FFFFFF + +/** IPIF transmit and recieve DMA offsets + */ +#define XTE_DMA_SEND_OFFSET 0x00002300 /**< DMA Tx channel */ +#define XTE_DMA_RECV_OFFSET 0x00002340 /**< DMA Rx channel */ + +/** IPIF IPIC_TO_TEMAC Core Registers + */ +#define XTE_CR_OFFSET 0x00001000 /**< Control */ +#define XTE_TPLR_OFFSET 0x00001004 /**< Tx packet length (FIFO) */ +#define XTE_TSR_OFFSET 0x00001008 /**< Tx status (FIFO) */ +#define XTE_RPLR_OFFSET 0x0000100C /**< Rx packet length (FIFO) */ +#define XTE_RSR_OFFSET 0x00001010 /**< Receive status */ +#define XTE_IFGP_OFFSET 0x00001014 /**< Interframe gap */ +#define XTE_TPPR_OFFSET 0x00001018 /**< Tx pause packet */ + +/** TEMAC Core Registers + * These are registers defined within the device's hard core located in the + * processor block. They are accessed with the host interface. These registers + * are addressed offset by XTE_HOST_IPIF_OFFSET or by the DCR base address + * if so configured. + */ +#define XTE_HOST_IPIF_OFFSET 0x00003000 /**< Offset of host registers when + memory mapped into IPIF */ +#define XTE_ERXC0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000200) /**< Rx configuration word 0 */ +#define XTE_ERXC1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000240) /**< Rx configuration word 1 */ +#define XTE_ETXC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000280) /**< Tx configuration */ +#define XTE_EFCC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000002C0) /**< Flow control configuration */ +#define XTE_ECFG_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000300) /**< EMAC configuration */ +#define XTE_EGMIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000320) /**< RGMII/SGMII configuration */ +#define XTE_EMC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000340) /**< Management configuration */ +#define XTE_EUAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000380) /**< Unicast address word 0 */ +#define XTE_EUAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000384) /**< Unicast address word 1 */ +#define XTE_EMAW0_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000388) /**< Multicast address word 0 */ +#define XTE_EMAW1_OFFSET (XTE_HOST_IPIF_OFFSET + 0x0000038C) /**< Multicast address word 1 */ +#define XTE_EAFM_OFFSET (XTE_HOST_IPIF_OFFSET + 0x00000390) /**< Promisciuous mode */ +#define XTE_EIRS_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A0) /**< IRstatus */ +#define XTE_EIREN_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003A4) /**< IRenable */ +#define XTE_EMIID_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B0) /**< MIIMwrData */ +#define XTE_EMIIC_OFFSET (XTE_HOST_IPIF_OFFSET + 0x000003B4) /**< MiiMcnt */ + +/* Register masks. The following constants define bit locations of various + * control bits in the registers. Constants are not defined for those registers + * that have a single bit field representing all 32 bits. For further + * information on the meaning of the various bit masks, refer to the HW spec. + */ + +/** Interrupt status bits for top level interrupts + * These bits are associated with the XTE_DISR_OFFSET, XTE_DIPR_OFFSET, + * and XTE_DIER_OFFSET registers. + */ +#define XTE_DXR_SEND_FIFO_MASK 0x00000040 /**< Send FIFO channel */ +#define XTE_DXR_RECV_FIFO_MASK 0x00000020 /**< Receive FIFO channel */ +#define XTE_DXR_RECV_DMA_MASK 0x00000010 /**< Receive DMA channel */ +#define XTE_DXR_SEND_DMA_MASK 0x00000008 /**< Send DMA channel */ +#define XTE_DXR_CORE_MASK 0x00000004 /**< Core */ +#define XTE_DXR_DPTO_MASK 0x00000002 /**< Data phase timeout */ +#define XTE_DXR_TERR_MASK 0x00000001 /**< Transaction error */ + +/** Interrupt status bits for MAC interrupts + * These bits are associated with XTE_IPISR_OFFSET and XTE_IPIER_OFFSET + * registers. + */ +#define XTE_IPXR_XMIT_DONE_MASK 0x00000001 /**< Tx complete */ +#define XTE_IPXR_RECV_DONE_MASK 0x00000002 /**< Rx complete */ +#define XTE_IPXR_AUTO_NEG_MASK 0x00000004 /**< Auto negotiation complete */ +#define XTE_IPXR_RECV_REJECT_MASK 0x00000008 /**< Rx packet rejected */ +#define XTE_IPXR_XMIT_SFIFO_EMPTY_MASK 0x00000010 /**< Tx status fifo empty */ +#define XTE_IPXR_RECV_LFIFO_EMPTY_MASK 0x00000020 /**< Rx length fifo empty */ +#define XTE_IPXR_XMIT_LFIFO_FULL_MASK 0x00000040 /**< Tx length fifo full */ +#define XTE_IPXR_RECV_LFIFO_OVER_MASK 0x00000080 /**< Rx length fifo overrun + Note that this signal is + no longer asserted by HW + */ +#define XTE_IPXR_RECV_LFIFO_UNDER_MASK 0x00000100 /**< Rx length fifo underrun */ +#define XTE_IPXR_XMIT_SFIFO_OVER_MASK 0x00000200 /**< Tx status fifo overrun */ +#define XTE_IPXR_XMIT_SFIFO_UNDER_MASK 0x00000400 /**< Tx status fifo underrun */ +#define XTE_IPXR_XMIT_LFIFO_OVER_MASK 0x00000800 /**< Tx length fifo overrun */ +#define XTE_IPXR_XMIT_LFIFO_UNDER_MASK 0x00001000 /**< Tx length fifo underrun */ +#define XTE_IPXR_RECV_PFIFO_ABORT_MASK 0x00002000 /**< Rx packet rejected due to + full packet FIFO */ +#define XTE_IPXR_RECV_LFIFO_ABORT_MASK 0x00004000 /**< Rx packet rejected due to + full length FIFO */ + +#define XTE_IPXR_RECV_DROPPED_MASK \ + (XTE_IPXR_RECV_REJECT_MASK | \ + XTE_IPXR_RECV_PFIFO_ABORT_MASK | \ + XTE_IPXR_RECV_LFIFO_ABORT_MASK) /**< IPXR bits that indicate a dropped + receive frame */ +#define XTE_IPXR_XMIT_ERROR_MASK \ + (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \ + XTE_IPXR_XMIT_LFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_LFIFO_UNDER_MASK) /**< IPXR bits that indicate transmit + errors */ + +#define XTE_IPXR_RECV_ERROR_MASK \ + (XTE_IPXR_RECV_DROPPED_MASK | \ + XTE_IPXR_RECV_LFIFO_UNDER_MASK) /**< IPXR bits that indicate receive + errors */ + +#define XTE_IPXR_FIFO_FATAL_ERROR_MASK \ + (XTE_IPXR_XMIT_SFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_SFIFO_UNDER_MASK | \ + XTE_IPXR_XMIT_LFIFO_OVER_MASK | \ + XTE_IPXR_XMIT_LFIFO_UNDER_MASK | \ + XTE_IPXR_RECV_LFIFO_UNDER_MASK) /**< IPXR bits that indicate errors with + one of the length or status FIFOs + that is fatal in nature. These bits + can only be cleared by a device + reset */ + +/** Software reset register (DSR) + */ +#define XTE_DSR_RESET_MASK 0x0000000A /**< Write this value to DSR to + reset entire core */ + + +/** Global interrupt enable register (DGIE) + */ +#define XTE_DGIE_ENABLE_MASK 0x80000000 /**< Write this value to DGIE to + enable interrupts from this + device */ + +/** Control Register (CR) + */ +#define XTE_CR_HTRST_MASK 0x00000008 /**< Reset hard temac */ +#define XTE_CR_BCREJ_MASK 0x00000004 /**< Disable broadcast address + filtering */ +#define XTE_CR_MCREJ_MASK 0x00000002 /**< Disable multicast address + filtering */ +#define XTE_CR_HDUPLEX_MASK 0x00000001 /**< Enable half duplex operation */ + + +/** Transmit Packet Length Register (TPLR) + */ +#define XTE_TPLR_TXPL_MASK 0x00003FFF /**< Tx packet length in bytes */ + + +/** Transmit Status Register (TSR) + */ +#define XTE_TSR_TXED_MASK 0x80000000 /**< Excess deferral error */ +#define XTE_TSR_PFIFOU_MASK 0x40000000 /**< Packet FIFO underrun */ +#define XTE_TSR_TXA_MASK 0x3E000000 /**< Transmission attempts */ +#define XTE_TSR_TXLC_MASK 0x01000000 /**< Late collision error */ +#define XTE_TSR_TPCF_MASK 0x00000001 /**< Transmit packet complete + flag */ + +#define XTE_TSR_ERROR_MASK \ + (XTE_TSR_TXED_MASK | \ + XTE_TSR_PFIFOU_MASK | \ + XTE_TSR_TXLC_MASK) /**< TSR bits that indicate an + error */ + + +/** Receive Packet Length Register (RPLR) + */ +#define XTE_RPLR_RXPL_MASK 0x00003FFF /**< Rx packet length in bytes */ + + +/** Receive Status Register (RSR) + */ +#define XTE_RSR_RPCF_MASK 0x00000001 /**< Receive packet complete + flag */ + +/** Interframe Gap Register (IFG) + */ +#define XTE_IFG_IFGD_MASK 0x000000FF /**< IFG delay */ + + +/** Transmit Pause Packet Register (TPPR) + */ +#define XTE_TPPR_TPPD_MASK 0x0000FFFF /**< Tx pause packet data */ + + +/** Receiver Configuration Word 1 (ERXC1) + */ +#define XTE_ERXC1_RXRST_MASK 0x80000000 /**< Receiver reset */ +#define XTE_ERXC1_RXJMBO_MASK 0x40000000 /**< Jumbo frame enable */ +#define XTE_ERXC1_RXFCS_MASK 0x20000000 /**< FCS not stripped */ +#define XTE_ERXC1_RXEN_MASK 0x10000000 /**< Receiver enable */ +#define XTE_ERXC1_RXVLAN_MASK 0x08000000 /**< VLAN enable */ +#define XTE_ERXC1_RXHD_MASK 0x04000000 /**< Half duplex */ +#define XTE_ERXC1_RXLT_MASK 0x02000000 /**< Length/type check disable */ +#define XTE_ERXC1_ERXC1_MASK 0x0000FFFF /**< Pause frame source address + bits [47:32]. Bits [31:0] + are stored in register + ERXC0 */ + + +/** Transmitter Configuration (ETXC) + */ +#define XTE_ETXC_TXRST_MASK 0x80000000 /**< Transmitter reset */ +#define XTE_ETXC_TXJMBO_MASK 0x40000000 /**< Jumbo frame enable */ +#define XTE_ETXC_TXFCS_MASK 0x20000000 /**< Generate FCS */ +#define XTE_ETXC_TXEN_MASK 0x10000000 /**< Transmitter enable */ +#define XTE_ETXC_TXVLAN_MASK 0x08000000 /**< VLAN enable */ +#define XTE_ETXC_TXHD_MASK 0x04000000 /**< Half duplex */ +#define XTE_ETXC_TXIFG_MASK 0x02000000 /**< IFG adjust enable */ + + +/** Flow Control Configuration (EFCC) + */ +#define XTE_EFCC_TXFLO_MASK 0x40000000 /**< Tx flow control enable */ +#define XTE_EFCC_RXFLO_MASK 0x20000000 /**< Rx flow control enable */ + + +/** EMAC Configuration (ECFG) + */ +#define XTE_ECFG_LINKSPD_MASK 0xC0000000 /**< Link speed */ +#define XTE_ECFG_RGMII_MASK 0x20000000 /**< RGMII mode enable */ +#define XTE_ECFG_SGMII_MASK 0x10000000 /**< SGMII mode enable */ +#define XTE_ECFG_1000BASEX_MASK 0x08000000 /**< 1000BaseX mode enable */ +#define XTE_ECFG_HOSTEN_MASK 0x04000000 /**< Host interface enable */ +#define XTE_ECFG_TX16BIT 0x02000000 /**< 16 bit Tx client enable */ +#define XTE_ECFG_RX16BIT 0x01000000 /**< 16 bit Rx client enable */ + +#define XTE_ECFG_LINKSPD_10 0x00000000 /**< XTE_ECFG_LINKSPD_MASK for + 10 Mbit */ +#define XTE_ECFG_LINKSPD_100 0x40000000 /**< XTE_ECFG_LINKSPD_MASK for + 100 Mbit */ +#define XTE_ECFG_LINKSPD_1000 0x80000000 /**< XTE_ECFG_LINKSPD_MASK for + 1000 Mbit */ + +/** EMAC RGMII/SGMII Configuration (EGMIC) + */ +#define XTE_EGMIC_RGLINKSPD_MASK 0xC0000000 /**< RGMII link speed */ +#define XTE_EGMIC_SGLINKSPD_MASK 0x0000000C /**< SGMII link speed */ +#define XTE_EGMIC_RGSTATUS_MASK 0x00000002 /**< RGMII link status */ +#define XTE_EGMIC_RGHALFDUPLEX_MASK 0x00000001 /**< RGMII half duplex */ + +#define XTE_EGMIC_RGLINKSPD_10 0x00000000 /**< XTE_EGMIC_RGLINKSPD_MASK + for 10 Mbit */ +#define XTE_EGMIC_RGLINKSPD_100 0x40000000 /**< XTE_EGMIC_RGLINKSPD_MASK + for 100 Mbit */ +#define XTE_EGMIC_RGLINKSPD_1000 0x80000000 /**< XTE_EGMIC_RGLINKSPD_MASK + for 1000 Mbit */ +#define XTE_EGMIC_SGLINKSPD_10 0x00000000 /**< XTE_SGMIC_RGLINKSPD_MASK + for 10 Mbit */ +#define XTE_EGMIC_SGLINKSPD_100 0x00000004 /**< XTE_SGMIC_RGLINKSPD_MASK + for 100 Mbit */ +#define XTE_EGMIC_SGLINKSPD_1000 0x00000008 /**< XTE_SGMIC_RGLINKSPD_MASK + for 1000 Mbit */ + +/** EMAC Management Configuration (EMC) + */ +#define XTE_EMC_MDIO_MASK 0x00000040 /**< MII management enable */ +#define XTE_EMC_CLK_DVD_MAX 0x3F /**< Maximum MDIO divisor */ + + +/** EMAC Unicast Address Register Word 1 (EUAW1) + */ +#define XTE_EUAW1_MASK 0x0000FFFF /**< Station address bits [47:32] + Station address bits [31:0] + are stored in register + EUAW0 */ + + +/** EMAC Multicast Address Register Word 1 (EMAW1) + */ +#define XTE_EMAW1_CAMRNW_MASK 0x00800000 /**< CAM read/write control */ +#define XTE_EMAW1_CAMADDR_MASK 0x00030000 /**< CAM address mask */ +#define XTE_EUAW1_MASK 0x0000FFFF /**< Multicast address bits [47:32] + Multicast address bits [31:0] + are stored in register + EMAW0 */ +#define XTE_EMAW1_CAMMADDR_SHIFT_MASK 16 /**< Number of bits to shift right + to align with + XTE_EMAW1_CAMADDR_MASK */ + + +/** EMAC Address Filter Mode (EAFM) + */ +#define XTE_EAFM_EPPRM_MASK 0x80000000 /**< Promiscuous mode enable */ + + +/** EMAC MII Management Write Data (EMIID) + */ +#define XTE_EMIID_MIIMWRDATA_MASK 0x0000FFFF /**< Data port */ + + +/** EMAC MII Management Control (EMIIC) + */ +#define XTE_EMIID_MIIMDECADDR_MASK 0x0000FFFF /**< Address port */ + + +struct XilTemacStats +{ + volatile uint32_t iInterrupts; + + volatile uint32_t iRxInterrupts; + volatile uint32_t iRxRejectedInterrupts; + volatile uint32_t iRxRejectedInvalidFrame; + volatile uint32_t iRxRejectedDataFifoFull; + volatile uint32_t iRxRejectedLengthFifoFull; + volatile uint32_t iRxMaxDrained; + volatile uint32_t iRxStrayEvents; + + volatile uint32_t iTxInterrupts; + volatile uint32_t iTxMaxDrained; +}; + +#define MAX_UNIT_BYTES 50 + +struct XilTemac +{ + struct arpcom iArpcom; + struct XilTemacStats iStats; + struct ifnet* iIfp; + + char iUnitName[MAX_UNIT_BYTES]; + + uint32_t iAddr; + rtems_event_set iIoEvent; + + int iIsrVector; + +#if PPC_HAS_CLASSIC_EXCEPTIONS + rtems_isr_entry iOldHandler; +#else + rtems_irq_connect_data iOldHandler; +#endif + int iIsPresent; +}; + + +#endif /* _XILINX_EMAC_*/ diff --git a/bsps/powerpc/virtex/include/xparameters_dflt.h b/bsps/powerpc/virtex/include/xparameters_dflt.h new file mode 100644 index 0000000000..b31cb26fe8 --- /dev/null +++ b/bsps/powerpc/virtex/include/xparameters_dflt.h @@ -0,0 +1,192 @@ +/******************************************************************* +* +* CAUTION: This file is automatically generated by libgen. +* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 +* DO NOT EDIT. +* +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. +* +* Description: Driver parameters +* +*******************************************************************/ + +#define STDIN_BASEADDRESS 0x40600000 +#define STDOUT_BASEADDRESS 0x40600000 + +/******************************************************************/ + +/* Definitions for driver PLBARB */ +#define XPAR_XPLBARB_NUM_INSTANCES 1 + +/* Definitions for peripheral PLB */ +#define XPAR_PLB_BASEADDR 0x00000000 +#define XPAR_PLB_HIGHADDR 0x00000000 +#define XPAR_PLB_DEVICE_ID 0 +#define XPAR_PLB_PLB_NUM_MASTERS 3 + + +/******************************************************************/ + +/* Definitions for driver OPBARB */ +#define XPAR_XOPBARB_NUM_INSTANCES 1 + +/* Definitions for peripheral OPB */ +#define XPAR_OPB_BASEADDR 0xFFFFFFFF +#define XPAR_OPB_HIGHADDR 0x00000000 +#define XPAR_OPB_DEVICE_ID 0 +#define XPAR_OPB_NUM_MASTERS 1 + + +/******************************************************************/ + +/* Definitions for driver UARTLITE */ +#define XPAR_XUARTLITE_NUM_INSTANCES 1 + +/* Definitions for peripheral CONSOLE */ +#define XPAR_CONSOLE_BASEADDR 0x40600000 +#define XPAR_CONSOLE_HIGHADDR 0x4060FFFF +#define XPAR_CONSOLE_DEVICE_ID 0 +#define XPAR_CONSOLE_BAUDRATE 115200 +#define XPAR_CONSOLE_USE_PARITY 0 +#define XPAR_CONSOLE_ODD_PARITY 0 +#define XPAR_CONSOLE_DATA_BITS 8 + + +/******************************************************************/ + +/* Definitions for driver GPIO */ +#define XPAR_XGPIO_NUM_INSTANCES 3 + +/* Definitions for peripheral LEDS */ +#define XPAR_LEDS_BASEADDR 0x40000000 +#define XPAR_LEDS_HIGHADDR 0x4000FFFF +#define XPAR_LEDS_DEVICE_ID 0 +#define XPAR_LEDS_INTERRUPT_PRESENT 0 +#define XPAR_LEDS_IS_DUAL 0 + + +/* Definitions for peripheral PBLEDS */ +#define XPAR_PBLEDS_BASEADDR 0x40020000 +#define XPAR_PBLEDS_HIGHADDR 0x4002FFFF +#define XPAR_PBLEDS_DEVICE_ID 1 +#define XPAR_PBLEDS_INTERRUPT_PRESENT 0 +#define XPAR_PBLEDS_IS_DUAL 0 + + +/* Definitions for peripheral PUSHBUTTONS */ +#define XPAR_PUSHBUTTONS_BASEADDR 0x40040000 +#define XPAR_PUSHBUTTONS_HIGHADDR 0x4004FFFF +#define XPAR_PUSHBUTTONS_DEVICE_ID 2 +#define XPAR_PUSHBUTTONS_INTERRUPT_PRESENT 1 +#define XPAR_PUSHBUTTONS_IS_DUAL 0 + + +/******************************************************************/ + +/* Definitions for driver TMRCTR */ +#define XPAR_XTMRCTR_NUM_INSTANCES 1 + +/* Definitions for peripheral OPBTIMER */ +#define XPAR_OPBTIMER_BASEADDR 0x41C00000 +#define XPAR_OPBTIMER_HIGHADDR 0x41C0FFFF +#define XPAR_OPBTIMER_DEVICE_ID 0 + + +/******************************************************************/ + +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 3 +#define XPAR_XINTC_HAS_IPR 1 +#define XPAR_XINTC_USE_DCR 0 +/* Definitions for driver INTC */ +#define XPAR_XINTC_NUM_INSTANCES 1 + +/* Definitions for peripheral INTC */ +#define XPAR_INTC_BASEADDR 0x41200000 +#define XPAR_INTC_HIGHADDR 0x4120FFFF +#define XPAR_INTC_DEVICE_ID 0 +#define XPAR_INTC_KIND_OF_INTR 0x00000000 + + +/******************************************************************/ + +#define XPAR_INTC_SINGLE_BASEADDR 0x41200000 +#define XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_INTC_DEVICE_ID +#define XPAR_OPBTIMER_INTERRUPT_MASK 0X000001 +#define XPAR_INTC_OPBTIMER_INTERRUPT_INTR 0 +#define XPAR_ETHERNET_IP2INTC_IRPT_MASK 0X000002 +#define XPAR_INTC_ETHERNET_IP2INTC_IRPT_INTR 1 +#define XPAR_PUSHBUTTONS_IP2INTC_IRPT_MASK 0X000004 +#define XPAR_INTC_PUSHBUTTONS_IP2INTC_IRPT_INTR 2 + +/******************************************************************/ + +/* Definitions for driver DDR */ +#define XPAR_XDDR_NUM_INSTANCES 1 + +/* Definitions for peripheral DDR_SDRAM_64MX32 */ +#define XPAR_DDR_SDRAM_64MX32_ECC_BASEADDR 0xFFFFFFFF +#define XPAR_DDR_SDRAM_64MX32_ECC_HIGHADDR 0x00000000 +#define XPAR_DDR_SDRAM_64MX32_DEVICE_ID 0 +#define XPAR_DDR_SDRAM_64MX32_INCLUDE_ECC_INTR 0 + + +/******************************************************************/ + +/* Definitions for peripheral DDR_SDRAM_64MX32 */ +#define XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x00000000 +#define XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x03FFFFFF + +/******************************************************************/ + + +/* Definitions for peripheral HARD_TEMAC_0 */ +#define XPAR_HARD_TEMAC_0_PHY_TYPE 1 + + +/******************************************************************/ + +/* Definitions for driver TEMAC */ +#define XPAR_XTEMAC_NUM_INSTANCES 1 + +/* Definitions for peripheral ETHERNET */ +#define XPAR_ETHERNET_DEVICE_ID 0 +#define XPAR_ETHERNET_BASEADDR 0x81200000 +#define XPAR_ETHERNET_HIGHADDR 0x8120FFFF +#define XPAR_ETHERNET_RXFIFO_DEPTH 32768 +#define XPAR_ETHERNET_TXFIFO_DEPTH 32768 +#define XPAR_ETHERNET_MAC_FIFO_DEPTH 64 +#define XPAR_ETHERNET_DMA_TYPE 1 +#define XPAR_ETHERNET_TX_DRE_TYPE 0 +#define XPAR_ETHERNET_RX_DRE_TYPE 0 +#define XPAR_ETHERNET_INCLUDE_TX_CSUM 0 +#define XPAR_ETHERNET_INCLUDE_RX_CSUM 0 + + +/******************************************************************/ + + +/* Definitions for peripheral FLASH */ +#define XPAR_FLASH_NUM_BANKS_MEM 1 + + +/******************************************************************/ + +/* Definitions for peripheral FLASH */ +#define XPAR_FLASH_MEM0_BASEADDR 0x06000000 +#define XPAR_FLASH_MEM0_HIGHADDR 0x067FFFFF + +/******************************************************************/ + + +/* Definitions for peripheral PLB_BRAM_IF_CNTLR_1 */ +#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff8000 +#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff + + +/******************************************************************/ + +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 + +/******************************************************************/ + diff --git a/bsps/powerpc/virtex4/headers.am b/bsps/powerpc/virtex4/headers.am new file mode 100644 index 0000000000..9ea2ab1635 --- /dev/null +++ b/bsps/powerpc/virtex4/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex4/include/bsp/mmu.h diff --git a/bsps/powerpc/virtex4/include/bsp.h b/bsps/powerpc/virtex4/include/bsp.h new file mode 100644 index 0000000000..91e7ddf4ab --- /dev/null +++ b/bsps/powerpc/virtex4/include/bsp.h @@ -0,0 +1,83 @@ +/* + * This include file contains all Virtex4 board IO definitions. + */ + +/* + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_POWERPC_VIRTEX4_BSP_H +#define LIBBSP_POWERPC_VIRTEX4_BSP_H + +#include <bspopts.h> + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include <rtems.h> + +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* miscellaneous stuff assumed to exist */ +extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ + +extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ +#endif /* ASM */ + +void BSP_ask_for_reset(void); + +/* + * Prototypes for BSP methods shared across file boundaries + */ +void zero_bss(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/virtex4/include/bsp/irq.h b/bsps/powerpc/virtex4/include/bsp/irq.h new file mode 100644 index 0000000000..45ef69adbf --- /dev/null +++ b/bsps/powerpc/virtex4/include/bsp/irq.h @@ -0,0 +1,79 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX4_IRQ_IRQ_H +#define VIRTEX4_IRQ_IRQ_H + +#include <rtems/irq.h> + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ + /* Not supported at this level */ + +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET 0 +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) + +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) (BSP_IS_PROCESSOR_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + + extern rtems_irq_connect_data *BSP_rtems_irq_tbl; + void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data); + void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused); + void BSP_rtems_irq_mngt_init(unsigned cpuId); + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX4_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex4/include/bsp/mmu.h b/bsps/powerpc/virtex4/include/bsp/mmu.h new file mode 100644 index 0000000000..3e2710b95c --- /dev/null +++ b/bsps/powerpc/virtex4/include/bsp/mmu.h @@ -0,0 +1,269 @@ +#ifndef RTEMS_VIRTEX4_MMU_H +#define RTEMS_VIRTEX4_MMU_H +/** + * @file + * + * @ingroup Virtex4MMU + * + * @brief Routines to manipulate the PPC 405 MMU. + */ +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * and was transcribed for the PPC 405 by + * R. Claus <claus@slac.stanford.edu>, 2012, + * Stanford Linear Accelerator Center, Stanford University, + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <rtems.h> +#include <inttypes.h> +#include <stdio.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup Virtex4MMU Virtex 4 - MMU Support + * + * @ingroup Virtex4 + * + * @brief MMU support. + * + * @{ + */ + +/* Some routines require or return a index 'key'. + */ +typedef int bsp_tlb_idx_t; + +/* Cache the relevant TLB entries so that we can make sure the user cannot + * create conflicting (overlapping) entries. Keep them public for informational + * purposes. + */ +typedef struct { + struct { + uint32_t pad:24; + uint32_t tid:8; /** Translation ID */ + } id; + struct { + uint32_t epn:22; /** Effective page number */ + uint32_t size:3; /** Page size */ + uint32_t v:1; /** Valid */ + uint32_t att:2; /** Little-endian, User-defined */ + uint32_t pad:4; + } hi; /** High word*/ + struct { + uint32_t rpn:22; /** Real page number */ + uint32_t perm:6; /** Execute enable, Write-enable, Zone select */ + uint32_t wimg:4; /** Write-through, Caching inhibited, Mem coherent, Guarded */ + } lo; /** Low word */ +} bsp_tlb_entry_t; + +#define NTLBS 64 + +extern bsp_tlb_entry_t* bsp_mmu_cache; + + +// These constants will have to be shifted right by 20 bits before +// being inserted the high word of the TLB. + +#define MMU_M_SIZE_1K (0x00000000U) +#define MMU_M_SIZE_4K (0x08000000U) +#define MMU_M_SIZE_16K (0x10000000U) +#define MMU_M_SIZE_64K (0x18000000U) +#define MMU_M_SIZE_256K (0x20000000U) +#define MMU_M_SIZE_1M (0x28000000U) +#define MMU_M_SIZE_4M (0x30000000U) +#define MMU_M_SIZE_16M (0x38000000U) +#define MMU_M_SIZE_MIN (MMU_M_SIZE_1K) +#define MMU_M_SIZE_MAX (MMU_M_SIZE_16M) +#define MMU_M_SIZE (0x38000000U) +#define MMU_V_SIZE (27) + +#define MMU_M_ATTR_LITTLE_ENDIAN (0x02000000U) +#define MMU_M_ATTR_USER0 (0x01000000U) +#define MMU_M_ATTR (0x03000000U) +#define MMU_V_ATTR (24) + +// These constants have the same bit positions they'll occupy +// in low word of the TLB. + +#define MMU_M_PERM_EXEC (0x00000200U) +#define MMU_M_PERM_DATA_WRITE (0x00000100U) +#define MMU_M_PERM_ZONE_SELECT (0x000000f0U) +#define MMU_M_PERM (0x000003f0U) +#define MMU_V_PERM (4) + +#define MMU_M_PROP_WRITE_THROUGH (0x00000008U) +#define MMU_M_PROP_UNCACHED (0x00000004U) +#define MMU_M_PROP_MEM_COHERENT (0x00000002U) +#define MMU_M_PROP_GUARDED (0x00000001U) +#define MMU_M_PROP (0x0000000fU) +#define MMU_V_PROP (0) + + +/* + * Dump (cleartext) content info from cached TLB entries + * to a file (stdout if f==NULL). + */ +void +bsp_mmu_dump_cache(FILE *f); + +/* Read a TLB entry from the hardware and store the settings in the + * bsp_mmu_cache[] structure. + * + * The routine can perform this operation quietly or + * print information to a file. + * + * 'key': TLB entry index. + * 'quiet': perform operation silently (no info printed) if nonzero. + * 'f': open FILE where to print information. May be NULL, in + * which case 'stdout' is used. + * + * RETURNS: + * 0: success; TLB entry is VALID + * +1: success but TLB entry is INVALID + * < 0: error (-1: invalid argument) + * (-2: driver not initialized) + */ +int +bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f); + +/* Initialize cache. Should be done only once although this is not enforced. + * + * RETURNS: zero on success, nonzero on error; in this case the driver will + * refuse to change TLB entries (other than disabling them). + */ +int +bsp_mmu_initialize(void); + +/* Find first free TLB entry by examining all entries' valid bit. The first + * entry without the valid bit set is returned. + * + * RETURNS: A free TLB entry number. -1 if no entry can be found. + */ +bsp_tlb_idx_t +bsp_mmu_find_first_free(void); + +/* Write a TLB entry (can also be used to disable an entry). + * + * The routine checks against the cached data in bsp_mmu_cache[] + * to prevent the user from generating overlapping entries. + * + * 'idx': TLB entry # to manipulate + * 'ea': Effective address (must be page aligned) + * 'pa': Physical address (must be page aligned) + * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes. + * 'sz' may also be one of the following: + * - page size in bytes ( >= 1024 ); the selector + * value is then computed by this routine. + * However, 'sz' must be a valid page size + * or -1 will be returned. + * - a value < 0 to invalidate/disable the + * TLB entry. + * 'flgs': Page's little-endian & user-defined flags, permissions and attributes + * 'tid': Translation ID + * + * RETURNS: 0 on success, nonzero on error: + * + * >0: requested mapping would overlap with + * existing mapping in another entry. Return + * value gives conflicting entry + 1; i.e., + * if a value of 4 is returned then the request + * conflicts with existing mapping in entry 3. + * -1: invalid argument + * -3: driver not initialized (or initialization failed). + * <0: other error + */ +bsp_tlb_idx_t +bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, uint sz, + uint32_t flgs, uint32_t tid); + +/* Check if a ea/tid/sz mapping overlaps with an existing entry. + * + * 'ea': The Effective Address to match against + * 'sz': The 'logarithmic' size selector; the page size + * is 1024*2^(2*sz). + * 'tid': The TID to match against + * + * RETURNS: + * >= 0: index of TLB entry that already provides a mapping + * which overlaps within the ea range. + * -1: SUCCESS (no conflicting entry found) + * <=-2: ERROR (invalid input) + */ +bsp_tlb_idx_t +bsp_mmu_match(uint32_t ea, int sz, uint32_t tid); + +/* Find TLB index that maps 'ea/tid' combination + * + * 'ea': Effective address to match against + * 'tid': The TID to match against + * + * RETURNS: index 'key'; i.e., the index number. + * + * On error (no mapping) -1 is returned. + */ +bsp_tlb_idx_t +bsp_mmu_find(uint32_t ea, uint32_t tid); + +/* Mark TLB entry as invalid ('disabled'). + * + * 'key': TLB entry index. + * + * RETURNS: zero on success, nonzero on error (TLB unchanged). + * + * NOTE: If a TLB entry is disabled the associated + * entry in bsp_mmu_cache[] is also marked as disabled. + */ +int +bsp_mmu_invalidate(bsp_tlb_idx_t key); + +/** @} */ + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/virtex4/include/tm27.h b/bsps/powerpc/virtex4/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/virtex4/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> diff --git a/bsps/powerpc/virtex5/headers.am b/bsps/powerpc/virtex5/headers.am new file mode 100644 index 0000000000..4a5dff7ff9 --- /dev/null +++ b/bsps/powerpc/virtex5/headers.am @@ -0,0 +1,11 @@ +## This file was generated by "./boostrap -H". + +include_HEADERS = +include_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/bsp.h +include_HEADERS += include/bspopts.h +include_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/tm27.h + +include_bspdir = $(includedir)/bsp +include_bsp_HEADERS = +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/bsp/irq.h +include_bsp_HEADERS += ../../../../../../bsps/powerpc/virtex5/include/bsp/mmu.h diff --git a/bsps/powerpc/virtex5/include/bsp.h b/bsps/powerpc/virtex5/include/bsp.h new file mode 100644 index 0000000000..ee9f20058d --- /dev/null +++ b/bsps/powerpc/virtex5/include/bsp.h @@ -0,0 +1,107 @@ +/* @file + * + * This include file contains all GEN405 board IO definitions. + */ + +/* + * derived from helas403/include/bsp.h: + * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp + * Author: Thomas Doerfler <td@imd.m.isar.de> + * IMD Ingenieurbuero fuer Microcomputertechnik + * + * COPYRIGHT (c) 1998 by IMD + * + * Changes from IMD are covered by the original distributions terms. + * This file has been derived from the papyrus BSP. + * + * Author: Andrew Bray <andy@i-cubed.co.uk> + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + */ + +#ifndef LIBBSP_POWERPC_VIRTEX5_BSP_H +#define LIBBSP_POWERPC_VIRTEX5_BSP_H + +#include <bspopts.h> + +/* + * confdefs.h overrides for this BSP: + * - Interrupt stack space is not minimum if defined. + */ +#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) + +#ifdef ASM +/* Definition of where to store registers in alignment handler */ +#define ALIGN_REGS 0x0140 + +#else +#include <rtems.h> +#include <bsp/default-initial-extension.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* miscellaneous stuff assumed to exist */ +extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ + +/* + * Bus Frequency + */ +extern unsigned int BSP_bus_frequency; +/* + * Processor Clock Frequency + */ +extern unsigned int BSP_processor_frequency; +/* + * Time base divisior (how many tick for 1 second). + */ +extern unsigned int BSP_time_base_divisor; + +/* + * Macro used by shared MPC6xx timer driver + */ +#define BSP_Convert_decrementer( _value ) \ + ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) + +/* + * Interfaces to required Clock Driver support methods + */ +int BSP_disconnect_clock_handler(void); +int BSP_connect_clock_handler(void); + +/* + * Prototypes for BSP methods shared across file boundaries + */ +void zero_bss(void); + +#endif /* ASM */ + +void BSP_ask_for_reset(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsps/powerpc/virtex5/include/bsp/irq.h b/bsps/powerpc/virtex5/include/bsp/irq.h new file mode 100644 index 0000000000..066090de7f --- /dev/null +++ b/bsps/powerpc/virtex5/include/bsp/irq.h @@ -0,0 +1,82 @@ +/*===============================================================*\ +| Project: RTEMS virtex BSP | ++-----------------------------------------------------------------+ +| Copyright (c) 2007 | +| Embedded Brains GmbH | +| Obere Lagerstr. 30 | +| D-82178 Puchheim | +| Germany | +| rtems@embedded-brains.de | ++-----------------------------------------------------------------+ +| The license and distribution terms for this file may be | +| found in the file LICENSE in this distribution or at | +| | +| http://www.rtems.org/license/LICENSE. | +| | ++-----------------------------------------------------------------+ +| this file declares constants of the interrupt controller | +\*===============================================================*/ +#ifndef VIRTEX5_IRQ_IRQ_H +#define VIRTEX5_IRQ_IRQ_H + +#include <rtems/irq.h> + +/* + * the following definitions specify the indices used + * to interface the interrupt handler API + */ + +/* + * Peripheral IRQ handlers related definitions + */ + /* Not supported at this level */ + +/* + * Processor IRQ handlers related definitions + */ +#define BSP_PROCESSOR_IRQ_NUMBER 3 +#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET 0 +#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ + +BSP_PROCESSOR_IRQ_NUMBER-1) + +#define BSP_IS_PROCESSOR_IRQ(irqnum) \ + (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ + ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) + +/* + * Summary + */ +#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) +#define BSP_LOWEST_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET +#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET + +#define BSP_IS_VALID_IRQ(irqnum) (BSP_IS_PROCESSOR_IRQ(irqnum)) + +#ifndef ASM +#ifdef __cplusplus +extern "C" { +#endif + +/* + * index table for the module specific handlers, a few entries are only placeholders + */ + typedef enum { + BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, + BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, + BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 + } rtems_irq_symbolic_name; + + extern rtems_irq_connect_data *BSP_rtems_irq_tbl; + void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data); + void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused); + void BSP_rtems_irq_mngt_init(unsigned cpuId); + +#define BSP_DEC BSP_PIT +#define BSP_DECREMENTER BSP_PIT + +#ifdef __cplusplus +} +#endif +#endif /* ASM */ + +#endif /* VIRTEX5_IRQ_IRQ_H */ diff --git a/bsps/powerpc/virtex5/include/bsp/mmu.h b/bsps/powerpc/virtex5/include/bsp/mmu.h new file mode 100644 index 0000000000..a3fb32b662 --- /dev/null +++ b/bsps/powerpc/virtex5/include/bsp/mmu.h @@ -0,0 +1,287 @@ +#ifndef RTEMS_VIRTEX5_MMU_H +#define RTEMS_VIRTEX5_MMU_H +/** + * @file + * + * @ingroup Virtex5MMU + * + * @brief Routines to manipulate the PPC 440 MMU. + */ +/* + * Authorship + * ---------- + * This software was created by + * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, + * Stanford Linear Accelerator Center, Stanford University. + * and was transcribed for the PPC 440 by + * R. Claus <claus@slac.stanford.edu>, 2012, + * Stanford Linear Accelerator Center, Stanford University, + * + * Acknowledgement of sponsorship + * ------------------------------ + * This software was produced by + * the Stanford Linear Accelerator Center, Stanford University, + * under Contract DE-AC03-76SFO0515 with the Department of Energy. + * + * Government disclaimer of liability + * ---------------------------------- + * Neither the United States nor the United States Department of Energy, + * nor any of their employees, makes any warranty, express or implied, or + * assumes any legal liability or responsibility for the accuracy, + * completeness, or usefulness of any data, apparatus, product, or process + * disclosed, or represents that its use would not infringe privately owned + * rights. + * + * Stanford disclaimer of liability + * -------------------------------- + * Stanford University makes no representations or warranties, express or + * implied, nor assumes any liability for the use of this software. + * + * Stanford disclaimer of copyright + * -------------------------------- + * Stanford University, owner of the copyright, hereby disclaims its + * copyright and all other rights in this software. Hence, anyone may + * freely use it for any purpose without restriction. + * + * Maintenance of notices + * ---------------------- + * In the interest of clarity regarding the origin and status of this + * SLAC software, this and all the preceding Stanford University notices + * are to remain affixed to any copy or derivative of this software made + * or distributed by the recipient and are to be affixed to any copy of + * software made or distributed by the recipient that contains a copy or + * derivative of this software. + * + * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 + */ + +#include <rtems.h> +#include <inttypes.h> +#include <stdio.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup Virtex5MMU Virtex 5 - MMU Support + * + * @ingroup Virtex5 + * + * @brief MMU support. + * + * @{ + */ + +/* Some routines require or return an index 'key'. + */ +typedef int bsp_tlb_idx_t; + +/* Cache the relevant TLB entries so that we can make sure the user cannot + * create conflicting (overlapping) entries. Keep them public for informational + * purposes. + */ +typedef struct { + struct { + uint32_t pad:24; + uint32_t tid:8; /** Translation ID */ + } id; + struct { + uint32_t epn:22; /** Effective page number */ + uint32_t v:1; /** Valid */ + uint32_t ts:1; /** Translation Address Space */ + uint32_t size:4; /** Page size */ + uint32_t tpar:4; /** Tag parity */ + } w0; + struct { + uint32_t rpn:22; /** The real (translated) page number. */ + uint32_t par1:2; /** For matching the TLB array parity */ + uint32_t pad:4; + uint32_t erpn:4; /** Extended Real Page Number */ + } w1; + struct { + uint32_t par2:2; /** Parity for TLB word 2 */ + uint32_t pad1:14; + uint32_t att:4; /** User-defined attributes */ + uint32_t wimge:5; /** Write-Through/Caching Inhibited/Memory Coherent/Guarded/Endian */ + uint32_t pad2:1; + uint32_t perm:6; /** User-State Executable/Writeable/Readable Supervisor-State Executable/Writeable/Readable */ + } w2; +} bsp_tlb_entry_t; + +#define NTLBS 64 + +extern bsp_tlb_entry_t* bsp_mmu_cache; + +// These constants will have to be shifted right by 20 bits before +// being inserted the high word of the TLB. + +#define MMU_M_SIZE_1K (0x00000000U) +#define MMU_M_SIZE_4K (0x08000000U) +#define MMU_M_SIZE_16K (0x10000000U) +#define MMU_M_SIZE_64K (0x18000000U) +#define MMU_M_SIZE_256K (0x20000000U) +#define MMU_M_SIZE_1M (0x28000000U) +#define MMU_M_SIZE_16M (0x38000000U) +#define MMU_M_SIZE_256M (0x48000000U) +#define MMU_M_SIZE_MIN (MMU_M_SIZE_1K) +#define MMU_M_SIZE_MAX (MMU_M_SIZE_256M) +#define MMU_M_SIZE (0x78000000U) +#define MMU_V_SIZE (27) + +// These constants have the same bit positions they'll occupy +// in low word of the TLB. + +#define MMU_M_ATTR_USER0 (0x00010000U) +#define MMU_M_ATTR_USER1 (0x00008000U) +#define MMU_M_ATTR_USER2 (0x00004000U) +#define MMU_M_ATTR_USER3 (0x00002000U) +#define MMU_M_ATTR (0x0001e000U) +#define MMU_V_ATTR (13) + +#define MMU_M_PROP_WRITE_THROUGH (0x00001000U) +#define MMU_M_PROP_UNCACHED (0x00000800U) +#define MMU_M_PROP_MEM_COHERENT (0x00000400U) +#define MMU_M_PROP_GUARDED (0x00000200U) +#define MMU_M_PROP_LITTLE_ENDIAN (0x00000100U) +#define MMU_M_PROP (0x00000f00U) +#define MMU_V_PROP (8) + +#define MMU_M_PERM_USER_EXEC (0x00000020U) +#define MMU_M_PERM_USER_WRITE (0x00000010U) +#define MMU_M_PERM_USER_READ (0x00000008U) +#define MMU_M_PERM_SUPER_EXEC (0x00000004U) +#define MMU_M_PERM_SUPER_WRITE (0x00000002U) +#define MMU_M_PERM_SUPER_READ (0x00000001U) +#define MMU_M_PERM (0x0000003fU) +#define MMU_V_PERM (0) + + +/* + * Dump (cleartext) content info from cached TLB entries + * to a file (stdout if f==NULL). + */ +void +bsp_mmu_dump_cache(FILE *f); + +/* Read a TLB entry from the hardware and store the settings in the + * bsp_mmu_cache[] structure. + * + * The routine can perform this operation quietly or + * print information to a file. + * + * 'key': TLB entry index. + * 'quiet': perform operation silently (no info printed) if nonzero. + * 'f': open FILE where to print information. May be NULL, in + * which case 'stdout' is used. + * + * RETURNS: + * 0: success; TLB entry is VALID + * +1: success but TLB entry is INVALID + * < 0: error (-1: invalid argument) + * (-2: driver not initialized) + */ +int +bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f); + +/* Initialize cache. Should be done only once although this is not enforced. + * + * RETURNS: zero on success, nonzero on error; in this case the driver will + * refuse to change TLB entries (other than disabling them). + */ +int +bsp_mmu_initialize(void); + +/* Find first free TLB entry by examining all entries' valid bit. The first + * entry without the valid bit set is returned. + * + * RETURNS: A free TLB entry number. -1 if no entry can be found. + */ +bsp_tlb_idx_t +bsp_mmu_find_first_free(void); + +/* Write a TLB entry (can also be used to disable an entry). + * + * The routine checks against the cached data in bsp_mmu_cache[] + * to prevent the user from generating overlapping entries. + * + * 'idx': TLB entry # to manipulate + * 'ea': Effective address (must be page aligned) + * 'pa': Physical address (must be page aligned) + * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes. + * 'sz' may also be one of the following: + * - page size in bytes ( >= 1024 ); the selector + * value is then computed by this routine. + * However, 'sz' must be a valid page size + * or -1 will be returned. + * - a value < 0 to invalidate/disable the + * TLB entry. + * 'flgs': Page's User-defined flags, permissions and WIMGE page attributes + * 'tid': Translation ID + * 'ts': Translation Space + * 'erpn': Extended Real Page Number + * + * RETURNS: 0 on success, nonzero on error: + * + * >0: requested mapping would overlap with + * existing mapping in another entry. Return + * value gives conflicting entry + 1; i.e., + * if a value of 4 is returned then the request + * conflicts with existing mapping in entry 3. + * -1: invalid argument + * -3: driver not initialized (or initialization failed). + * <0: other error + */ +bsp_tlb_idx_t +bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, int sz, + uint32_t flgs, uint32_t tid, uint32_t ts, uint32_t erpn); + +/* Check if a ea/tid/ts/sz mapping overlaps with an existing entry. + * + * 'ea': The Effective Address to match against + * 'sz': The 'logarithmic' size selector; the page size + * is 1024*2^(2*sz). + * 'tid': Translation ID + * 'ts': Translation Space + * + * RETURNS: + * >= 0: index of TLB entry that already provides a mapping + * which overlaps within the ea range. + * -1: SUCCESS (no conflicting entry found) + * <=-2: ERROR (invalid input) + */ +bsp_tlb_idx_t +bsp_mmu_match(uint32_t ea, int sz, uint32_t tid, uint32_t ts); + +/* Find TLB index that maps 'ea/tid/ts' combination + * + * 'ea': Effective address to match against + * 'tid': Translation ID + * 'ts': Translation Space + * + * RETURNS: index 'key'; i.e., the index number. + * + * On error (no mapping) -1 is returned. + */ +bsp_tlb_idx_t +bsp_mmu_find(uint32_t ea, uint32_t tid, uint32_t ts); + +/* Mark TLB entry as invalid ('disabled'). + * + * 'key': TLB entry index. + * + * RETURNS: zero on success, nonzero on error (TLB unchanged). + * + * NOTE: If a TLB entry is disabled the associated + * entry in bsp_tlb_cache[] is also marked as disabled. + */ +int +bsp_mmu_invalidate(bsp_tlb_idx_t key); + +/** @} */ + +#ifdef __cplusplus +}; +#endif + +#endif diff --git a/bsps/powerpc/virtex5/include/tm27.h b/bsps/powerpc/virtex5/include/tm27.h new file mode 100644 index 0000000000..0dfa7bf628 --- /dev/null +++ b/bsps/powerpc/virtex5/include/tm27.h @@ -0,0 +1 @@ +#include <rtems/tm27-default.h> |