diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-22 13:00:27 +0100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-23 09:24:49 +0100 |
commit | 9f3a08ef2de99714d679aecf6b1ecb4e11869424 (patch) | |
tree | 0d876016ae1dd067b1815dd79715cc7edc752f1e /bsps | |
parent | bsps/arm: Invalidate TLB in start.S (diff) | |
download | rtems-9f3a08ef2de99714d679aecf6b1ecb4e11869424.tar.bz2 |
bsps: Use header file for GIC architecture support
This avoids a function call overhead in the interrupt dispatching.
Update #4202.
Diffstat (limited to 'bsps')
-rw-r--r-- | bsps/aarch64/include/dev/irq/arm-gic-arch.h (renamed from bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c) | 20 | ||||
-rw-r--r-- | bsps/arm/include/dev/irq/arm-gic-arch.h (renamed from bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c) | 18 | ||||
-rw-r--r-- | bsps/include/dev/irq/arm-gic-irq.h | 13 | ||||
-rw-r--r-- | bsps/shared/dev/irq/arm-gicv2.c | 1 | ||||
-rw-r--r-- | bsps/shared/dev/irq/arm-gicv3.c | 1 |
5 files changed, 34 insertions, 19 deletions
diff --git a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c b/bsps/aarch64/include/dev/irq/arm-gic-arch.h index 4c26ec3c2b..c3332faf42 100644 --- a/bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c +++ b/bsps/aarch64/include/dev/irq/arm-gic-arch.h @@ -34,10 +34,18 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include <dev/irq/arm-gic-irq.h> +#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H +#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H + +#include <rtems/score/cpu.h> + #include <bsp/irq-generic.h> -void arm_interrupt_handler_dispatch(rtems_vector_number vector) +#ifdef __cplusplus +extern "C" { +#endif + +static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector) { uint32_t interrupt_level = _CPU_ISR_Get_level(); AArch64_interrupt_enable(1); @@ -45,7 +53,7 @@ void arm_interrupt_handler_dispatch(rtems_vector_number vector) _CPU_ISR_Set_level(interrupt_level); } -void arm_interrupt_facility_set_exception_handler(void) +static inline void arm_interrupt_facility_set_exception_handler(void) { AArch64_set_exception_handler( AARCH64_EXCEPTION_SPx_IRQ, @@ -56,3 +64,9 @@ void arm_interrupt_facility_set_exception_handler(void) _AArch64_Exception_interrupt_nest ); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */ diff --git a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c b/bsps/arm/include/dev/irq/arm-gic-arch.h index 7c0462d04d..fe981da4f7 100644 --- a/bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c +++ b/bsps/arm/include/dev/irq/arm-gic-arch.h @@ -34,12 +34,18 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#ifndef _RTEMS_DEV_IRQ_ARM_GIC_ARM_H +#define _RTEMS_DEV_IRQ_ARM_GIC_ARM_H + #include <libcpu/arm-cp15.h> -#include <dev/irq/arm-gic-irq.h> #include <bsp/irq-generic.h> #include <rtems/score/armv4.h> -void arm_interrupt_handler_dispatch(rtems_vector_number vector) +#ifdef __cplusplus +extern "C" { +#endif + +static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector) { uint32_t psr = _ARMV4_Status_irq_enable(); bsp_interrupt_handler_dispatch(vector); @@ -47,10 +53,16 @@ void arm_interrupt_handler_dispatch(rtems_vector_number vector) _ARMV4_Status_restore(psr); } -void arm_interrupt_facility_set_exception_handler(void) +static inline void arm_interrupt_facility_set_exception_handler(void) { arm_cp15_set_exception_handler( ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt ); } + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_DEV_IRQ_ARM_GIC_ARM_H */ diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h index 5270331624..5ce9d54684 100644 --- a/bsps/include/dev/irq/arm-gic-irq.h +++ b/bsps/include/dev/irq/arm-gic-irq.h @@ -97,19 +97,6 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq( return sc; } -/** - * This architecture-specific function sets the exception vector for handling - * IRQs. - */ -void arm_interrupt_facility_set_exception_handler(void); - -/** - * This architecture-specific function dispatches a triggered IRQ. - * - * @param[in] vector The vector on which the IRQ occurred. - */ -void arm_interrupt_handler_dispatch(rtems_vector_number vector); - uint32_t arm_gic_irq_processor_count(void); void arm_gic_irq_initialize_secondary_cpu(void); diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c index 74989a4de5..c29cae1d97 100644 --- a/bsps/shared/dev/irq/arm-gicv2.c +++ b/bsps/shared/dev/irq/arm-gicv2.c @@ -13,6 +13,7 @@ */ #include <dev/irq/arm-gic.h> +#include <dev/irq/arm-gic-arch.h> #include <bsp/irq.h> #include <bsp/irq-generic.h> diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index 77128adb5b..113b840068 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -26,6 +26,7 @@ */ #include <dev/irq/arm-gic.h> +#include <dev/irq/arm-gic-arch.h> #include <bsp/irq.h> #include <bsp/irq-generic.h> |