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authorSebastian Huber <sebastian.huber@embedded-brains.de>2012-01-23 11:19:22 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2012-01-23 11:19:22 +0100
commita762dc2a49fad0e7797806fefd34d144b6d998b2 (patch)
tree3f21a6ba6320a3a89581a3d1e2be5162bb8a904f
parent9bf3a868655f260c2fa6cbcab16f0218cf53e5b8 (diff)
downloadrtems-a762dc2a49fad0e7797806fefd34d144b6d998b2.tar.bz2
Support for MPC5643L.
Rework of the start sequence to reduce the amount assembler code and to support configuration tables which may be provided by the application.
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am51
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/README73
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c168
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac18
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-config.c32
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-esci.c339
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-generic.c167
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-linflex.c419
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-esci.h57
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-generic.h81
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-linflex.h64
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h90
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/xkt564levb.cfg10
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c7
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am40
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c23
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c157
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/fmpll-syncr-vals.c92
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/get-system-clock.c85
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.xkt564levb36
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c6
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c6
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-cache.S106
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-clock.c99
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-clock.c122
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs-cal.c (renamed from c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cal-cs-config.c)40
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs.c (renamed from c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cs-config.c)20
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu-early.c42
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c (renamed from c/src/lib/libbsp/powerpc/mpc55xxevb/startup/mmu-config.c)77
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-siu-pcr.c (renamed from c/src/lib/libbsp/powerpc/mpc55xxevb/startup/siu-pcr-config.c)25
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-early.c175
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-flash.S (renamed from c/src/lib/libcpu/powerpc/mpc55xx/misc/flash.S)107
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-watchdog.c37
-rw-r--r--c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S360
-rw-r--r--c/src/lib/libcpu/powerpc/Makefile.am9
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c2
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c20
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/emios/emios.c24
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h25
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h3
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h3
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h3
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h20666
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h3
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h224
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h6
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h130
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h24
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h28
-rw-r--r--c/src/lib/libcpu/powerpc/mpc55xx/misc/fmpll.S193
-rw-r--r--c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c1
-rw-r--r--c/src/lib/libcpu/powerpc/preinstall.am8
-rw-r--r--c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c4
-rw-r--r--c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h1
54 files changed, 23519 insertions, 1089 deletions
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
index 7c6e0df099..933dfe91da 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
@@ -30,6 +30,7 @@ dist_project_lib_DATA += startup/linkcmds.mpc5566evb
dist_project_lib_DATA += startup/linkcmds.mpc5566evb_spe
dist_project_lib_DATA += startup/linkcmds.mpc5674fevb
dist_project_lib_DATA += startup/linkcmds.mpc5674fevb_spe
+dist_project_lib_DATA += startup/linkcmds.xkt564levb
dist_project_lib_DATA += startup/linkcmds.phycore_mpc5554
noinst_LIBRARIES += libbsp.a
@@ -41,16 +42,20 @@ include_HEADERS += ../../shared/include/tm27.h
nodist_include_HEADERS = include/bspopts.h ../../shared/tod.h \
../../shared/include/coverhd.h
-include_bsp_HEADERS = include/mpc55xxevb.h \
- include/smsc9218i.h \
- include/mpc55xx-config.h \
- ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h \
- ../../shared/include/irq-generic.h \
- ../../shared/include/irq-info.h \
- ../../shared/include/utility.h \
- ../shared/include/linker-symbols.h \
- ../shared/include/start.h \
- ../shared/include/tictac.h
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h
+include_bsp_HEADERS += ../../shared/include/irq-generic.h
+include_bsp_HEADERS += ../../shared/include/irq-info.h
+include_bsp_HEADERS += ../../shared/include/utility.h
+include_bsp_HEADERS += ../shared/include/linker-symbols.h
+include_bsp_HEADERS += ../shared/include/start.h
+include_bsp_HEADERS += ../shared/include/tictac.h
+include_bsp_HEADERS += include/mpc55xx-config.h
+include_bsp_HEADERS += include/mpc55xxevb.h
+include_bsp_HEADERS += include/smsc9218i.h
+include_bsp_HEADERS += include/console-esci.h
+include_bsp_HEADERS += include/console-generic.h
+include_bsp_HEADERS += include/console-linflex.h
# startup
libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -58,25 +63,36 @@ libbsp_a_SOURCES += ../../shared/bspclean.c
libbsp_a_SOURCES += ../../shared/bsplibc.c
libbsp_a_SOURCES += ../../shared/bsppost.c
libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
-libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
libbsp_a_SOURCES += ../shared/src/bsp-start-zero.S
libbsp_a_SOURCES += ../shared/src/memcpy.c
libbsp_a_SOURCES += ../shared/src/tictac.c
libbsp_a_SOURCES += ../shared/startup/bspidle.c
libbsp_a_SOURCES += startup/bspstart.c
-libbsp_a_SOURCES += startup/fmpll-syncr-vals.c
libbsp_a_SOURCES += startup/exc-vector-base.S
-libbsp_a_SOURCES += startup/ebi-cs-config.c
-libbsp_a_SOURCES += startup/ebi-cal-cs-config.c
-libbsp_a_SOURCES += startup/mmu-config.c
-libbsp_a_SOURCES += startup/siu-pcr-config.c
-libbsp_a_SOURCES += startup/early-init.c
+libbsp_a_SOURCES += startup/get-system-clock.c
libbsp_a_SOURCES += startup/reset.c
+libbsp_a_SOURCES += startup/start-config-clock.c
+libbsp_a_SOURCES += startup/start-config-ebi-cs.c
+libbsp_a_SOURCES += startup/start-config-ebi-cs-cal.c
+libbsp_a_SOURCES += startup/start-config-mmu.c
+libbsp_a_SOURCES += startup/start-config-mmu-early.c
+libbsp_a_SOURCES += startup/start-config-siu-pcr.c
+libbsp_a_SOURCES += startup/start-early.c
+libbsp_a_SOURCES += startup/start-cache.S
+libbsp_a_SOURCES += startup/start-clock.c
+libbsp_a_SOURCES += startup/start-flash.S
+libbsp_a_SOURCES += startup/start-watchdog.c
# clock
libbsp_a_SOURCES += clock/clock-config.c
+# console
+libbsp_a_SOURCES += console/console-config.c
+libbsp_a_SOURCES += console/console-esci.c
+libbsp_a_SOURCES += console/console-generic.c
+libbsp_a_SOURCES += console/console-linflex.c
+
# irq_generic
libbsp_a_SOURCES += ../../shared/src/irq-generic.c \
../../shared/src/irq-legacy.c \
@@ -107,7 +123,6 @@ libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/edma.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/emios.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/dspi.rel \
- ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/esci.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/README b/c/src/lib/libbsp/powerpc/mpc55xxevb/README
index 476433d1ff..df4a8e8a52 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/README
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/README
@@ -1,64 +1,15 @@
-OVERVIEW
-========
+Supported MCUs:
-BSP NAME: mpc55xxevb
-BOARD: Freescale MPC5566 evaluation board MPC5566EVB
-BUS: N/A
-CPU FAMILY: ppc
-CPU: PowerPC e200z6
-COPROCESSORS: N/A
-MODE: 32 bit mode
+ o MPC5516
+ o MPC5554
+ o MPC5566
+ o MPC5643L
+ o MPC5674F
-PERIPHERALS
-===========
+Supported boards:
-TIMERS: not yet supported
- RESOLUTION: not yet supported
-SERIAL PORTS: 2 internal eSCI
-REAL-TIME CLOCK: N/A
-DMA: eDMA
-VIDEO: N/A
-SCSI: N/A
-NETWORKING: FEC (not yet supported)
- SMSC9218I (external)
-SPI: DSPI
-
-DRIVER INFORMATION
-==================
-
-CLOCK DRIVER: EMIOS channel 23
-IOSUPP DRIVER: N/A
-SHMSUPP: N/A
-TIMER DRIVER: not yet supported
-TTY DRIVER: BSP
-
-STDIO
-=====
-
-PORT: ESCI A
-ELECTRICAL: N/A
-BAUD: 115200
-BITS PER CHARACTER: 8
-PARITY: N
-STOP BITS: 1
-
-NOTES
-=====
-
-BUS WIDTH: 32 bit Flash, 32 bit SDRAM
-FLASH: 3 MByte
-INTERNAL RAM: 128 kByte SDRAM
-EXTERNAL RAM: 512 kByte SDRAM
-
-
-DEBUGGING / CODE LOADING
-========================
-
-Tested using the Lauterbach TRACE32 ICD debugger.
-
-ISSUES
-======
-
-The memory blocks allocated by LibBlock are in general not cache aligned so we
-cannot use DMA transfers. This is suboptimal in combination with a SD Card and
-SPI.
+ o embedded brains GmbH GWLCFM
+ o phyCORE MPC5554
+ o Freescale MPC5566EVB
+ o Freescale XKT564L KIT
+ o Axiom MPC567XADAT516 / MPC567XEVBFXMB
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c
index 0d1561880f..d8a6594ad2 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c
@@ -7,81 +7,76 @@
*/
/*
- * Copyright (c) 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
+ * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
-#include <mpc55xx/regs.h>
-#include <mpc55xx/emios.h>
-
-#include <rtems.h>
-
#include <bsp.h>
#include <bsp/irq.h>
-#define RTEMS_STATUS_CHECKS_USE_PRINTK
+#include <mpc55xx/regs.h>
-#include <rtems/status-checks.h>
+static uint64_t mpc55xx_clock_factor;
-/* This is defined in clockdrv_shell.h */
-rtems_isr Clock_isr( rtems_vector_number vector);
+#if defined(MPC55XX_CLOCK_EMIOS_CHANNEL)
-#define Clock_driver_support_at_tick() \
- do { \
- union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS; \
- csr.B.FLAG = 1; \
- EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.R = csr.R; \
- } while (0)
+#include <mpc55xx/emios.h>
-static uint64_t mpc55xx_clock_factor;
+static void mpc55xx_clock_at_tick(void)
+{
+ union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS;
+ csr.B.FLAG = 1;
+ EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.R = csr.R;
+}
-static void mpc55xx_clock_handler_install( rtems_isr_entry isr,
- rtems_isr_entry *old_isr)
+static void mpc55xx_clock_handler_install(rtems_isr_entry isr)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
sc = mpc55xx_interrupt_handler_install(
- MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
+ MPC55XX_IRQ_EMIOS(MPC55XX_CLOCK_EMIOS_CHANNEL),
"clock",
RTEMS_INTERRUPT_UNIQUE,
MPC55XX_INTC_MIN_PRIORITY,
(rtems_interrupt_handler) isr,
NULL
);
- *old_isr = NULL;
- RTEMS_CHECK_SC_VOID( sc, "install clock interrupt handler");
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
}
-static void mpc55xx_clock_initialize( void)
+static void mpc55xx_clock_initialize(void)
{
volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
union EMIOS_CCR_tag ccr = MPC55XX_ZERO_FLAGS;
union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS;
unsigned prescaler = mpc55xx_emios_global_prescaler();
- uint64_t interval = ((uint64_t) bsp_clock_speed
- * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000;
+ uint64_t reference_clock = bsp_clock_speed;
+ uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
+ uint64_t interval = (reference_clock * us_per_tick) / 1000000;
- mpc55xx_clock_factor = (1000000000ULL << 32) / bsp_clock_speed;
+ mpc55xx_clock_factor = (1000000000ULL << 32) / reference_clock;
/* Apply prescaler */
if (prescaler > 0) {
interval /= (uint64_t) prescaler;
} else {
- RTEMS_SYSLOG_ERROR( "unexpected global eMIOS prescaler\n");
+ rtems_fatal_error_occurred(0xdeadbeef);
}
/* Check interval */
if (interval == 0 || interval > MPC55XX_EMIOS_VALUE_MAX) {
- interval = MPC55XX_EMIOS_VALUE_MAX;
- RTEMS_SYSLOG_ERROR( "clock timer interval out of range\n");
+ rtems_fatal_error_occurred(0xdeadbeef);
}
/* Configure eMIOS channel */
@@ -103,37 +98,28 @@ static void mpc55xx_clock_initialize( void)
regs->CADR.R = (uint32_t) interval - 1;
/* Set control register */
-#if MPC55XX_CHIP_TYPE / 10 == 551
- ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
-#else
- ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
-#endif
+ #if MPC55XX_CHIP_TYPE / 10 == 551
+ ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
+ #else
+ ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
+ #endif
ccr.B.UCPREN = 1;
ccr.B.FEN = 1;
ccr.B.FREN = 1;
regs->CCR.R = ccr.R;
}
-static void mpc55xx_clock_cleanup( void)
+static void mpc55xx_clock_cleanup(void)
{
- rtems_status_code sc = RTEMS_SUCCESSFUL;
volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
union EMIOS_CCR_tag ccr = MPC55XX_ZERO_FLAGS;
/* Set channel in GPIO mode */
ccr.B.MODE = MPC55XX_EMIOS_MODE_GPIO_INPUT;
regs->CCR.R = ccr.R;
-
- /* Remove interrupt handler */
- sc = rtems_interrupt_handler_remove(
- MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
- (rtems_interrupt_handler) Clock_isr,
- NULL
- );
- RTEMS_CHECK_SC_VOID( sc, "remove clock interrupt handler");
}
-static uint32_t mpc55xx_clock_nanoseconds_since_last_tick( void)
+static uint32_t mpc55xx_clock_nanoseconds_since_last_tick(void)
{
volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL];
uint64_t c = regs->CCNTR.R;
@@ -147,13 +133,87 @@ static uint32_t mpc55xx_clock_nanoseconds_since_last_tick( void)
return (uint32_t) ((c * k) >> 32);
}
-#define Clock_driver_support_initialize_hardware() mpc55xx_clock_initialize()
+#elif defined(MPC55XX_CLOCK_PIT_CHANNEL)
+
+static void mpc55xx_clock_at_tick(void)
+{
+ volatile PIT_RTI_CHANNEL_tag *channel =
+ &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
+ PIT_RTI_TFLG_32B_tag tflg = { .B = { .TIF = 1 } };
+
+ channel->TFLG.R = tflg.R;
+}
+
+static void mpc55xx_clock_handler_install(rtems_isr_entry isr)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+ sc = mpc55xx_interrupt_handler_install(
+ MPC55XX_IRQ_PIT_CHANNEL(MPC55XX_CLOCK_PIT_CHANNEL),
+ "clock",
+ RTEMS_INTERRUPT_UNIQUE,
+ MPC55XX_INTC_MIN_PRIORITY,
+ (rtems_interrupt_handler) isr,
+ NULL
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+}
+
+static void mpc55xx_clock_initialize(void)
+{
+ volatile PIT_RTI_CHANNEL_tag *channel =
+ &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
+ uint64_t reference_clock = bsp_clock_speed;
+ uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
+ uint64_t interval = (reference_clock * us_per_tick) / 1000000;
+ PIT_RTI_PITMCR_32B_tag pitmcr = { .B = { .FRZ = 1 } };
+ PIT_RTI_TCTRL_32B_tag tctrl = { .B = { .TIE = 1, .TEN = 1 } };
+
+ mpc55xx_clock_factor = (1000000000ULL << 32) / reference_clock;
+
+ PIT_RTI.PITMCR.R = pitmcr.R;
+ channel->LDVAL.R = interval;
+ channel->TCTRL.R = tctrl.R;
+}
+
+static void mpc55xx_clock_cleanup(void)
+{
+ volatile PIT_RTI_CHANNEL_tag *channel =
+ &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
-#define Clock_driver_support_install_isr( isr, old_isr) \
- mpc55xx_clock_handler_install(isr,&old_isr)
+ channel->TCTRL.R = 0;
+}
-#define Clock_driver_support_shutdown_hardware() mpc55xx_clock_cleanup()
+static uint32_t mpc55xx_clock_nanoseconds_since_last_tick(void)
+{
+ volatile PIT_RTI_CHANNEL_tag *channel =
+ &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL];
+ uint32_t c = channel->CVAL.R;
+ uint32_t i = channel->LDVAL.R;
+ uint64_t k = mpc55xx_clock_factor;
+ if (channel->TFLG.B.TIF != 0) {
+ c = channel->CVAL.R - i;
+ }
+
+ return (uint32_t) (((i - c) * k) >> 32);
+}
+
+#endif
+
+#define Clock_driver_support_at_tick() \
+ mpc55xx_clock_at_tick()
+#define Clock_driver_support_initialize_hardware() \
+ mpc55xx_clock_initialize()
+#define Clock_driver_support_install_isr(isr, old_isr) \
+ do { \
+ mpc55xx_clock_handler_install(isr); \
+ old_isr = NULL; \
+ } while (0)
+#define Clock_driver_support_shutdown_hardware() \
+ mpc55xx_clock_cleanup()
#define Clock_driver_nanoseconds_since_last_tick \
mpc55xx_clock_nanoseconds_since_last_tick
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac b/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
index 9ec3dbe0d4..6bc0eb4bc3 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
@@ -24,6 +24,7 @@ RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([gwlcfm],[])
+RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([xkt564levb],[])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb*],[1])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5674fevb*],[1])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
@@ -36,6 +37,7 @@ RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[mpc5674fevb*],[255])
+RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[xkt564levb*],[127])
RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[mpc5566evb*],[127])
RTEMS_BSPOPTS_SET([BSP_INTERRUPT_HANDLER_TABLE_SIZE],[*],[63])
RTEMS_BSPOPTS_HELP([BSP_INTERRUPT_HANDLER_TABLE_SIZE],
@@ -50,6 +52,7 @@ RTEMS_BSPOPTS_HELP([MPC55XX_ESCI_USE_INTERRUPTS],
[define to zero or one to disable or enable interrupts for the eSCI devices])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[gwlcfm],[40000000])
+RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[xkt564levb*],[40000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[mpc5674fevb*],[40000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[*] ,[8000000])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_REF_CLOCK],
@@ -74,6 +77,7 @@ RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[*] ,[12])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_MFD],
[Must be defined to be the PLL multiplication factor for clock generation])
+RTEMS_BSPOPTS_SET([MPC55XX_EMIOS_PRESCALER],[xkt564levb*],[])
RTEMS_BSPOPTS_SET([MPC55XX_EMIOS_PRESCALER],[gwlcfm],[66])
RTEMS_BSPOPTS_SET([MPC55XX_EMIOS_PRESCALER],[*] ,[1])
RTEMS_BSPOPTS_HELP([MPC55XX_EMIOS_PRESCALER],
@@ -96,17 +100,28 @@ RTEMS_BSPOPTS_HELP([SMSC9218I_EDMA_TX_CHANNEL],
[transmit eDMA channel for SMSC9218I network interface])
RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[mpc5674fevb*],[31])
+RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[xkt564levb*],[])
RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_EMIOS_CHANNEL],[*],[23])
RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_EMIOS_CHANNEL],
[selects the eMIOS channel for the RTEMS system tick (the default is the last channel)])
+RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_PIT_CHANNEL],[xkt564levb*],[3])
+RTEMS_BSPOPTS_SET([MPC55XX_CLOCK_PIT_CHANNEL],[*],[])
+RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_PIT_CHANNEL],
+[selects the PIT channel for the RTEMS system tick (the default is the last channel)])
+
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5674fevb*],[5674])
+RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[xkt564levb*],[5643])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb*],[5566])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[gwlcfm] ,[5516])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[*] ,[5554])
RTEMS_BSPOPTS_HELP([MPC55XX_CHIP_TYPE],
[specifies the chip type in use (e.g. 5554 for MPC5554)])
+RTEMS_BSPOPTS_SET([MPC55XX_EARLY_STACK_SIZE],[*],[1024])
+RTEMS_BSPOPTS_HELP([MPC55XX_EARLY_STACK_SIZE],
+[size of the early initialization stack in bytes])
+
RTEMS_BSPOPTS_SET([MPC55XX_BOOTFLAGS],[*],[])
RTEMS_BSPOPTS_HELP([MPC55XX_BOOTFLAGS],
[if defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
@@ -114,6 +129,9 @@ RTEMS_BSPOPTS_HELP([MPC55XX_BOOTFLAGS],
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674FEVB],[mpc5674fevb*],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5674FEVB],[if defined, use custom settings for MPC5674FEVB board])
+RTEMS_BSPOPTS_SET([MPC55XX_BOARD_XKT564LEVB],[xkt564levb*],[1])
+RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_XKT564LEVB],[if defined, use custom settings for XKT564LEVB board])
+
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5566EVB],[mpc5566evb*],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5566EVB],[if defined, use custom settings for MPC5566EVB board])
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-config.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-config.c
new file mode 100644
index 0000000000..816c8552b6
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-config.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/console-generic.h>
+#include <bsp/console-esci.h>
+#include <bsp/console-linflex.h>
+
+CONSOLE_GENERIC_INFO_TABLE = {
+ #ifdef MPC55XX_HAS_ESCI
+ CONSOLE_GENERIC_INFO(mpc55xx_esci_devices + 0, &mpc55xx_esci_callbacks, "/dev/ttyS0"),
+ CONSOLE_GENERIC_INFO(mpc55xx_esci_devices + 1, &mpc55xx_esci_callbacks, "/dev/ttyS1")
+ #endif
+ #ifdef MPC55XX_HAS_LINFLEX
+ CONSOLE_GENERIC_INFO(mpc55xx_linflex_devices + 0, &mpc55xx_linflex_callbacks, "/dev/ttyS0"),
+ CONSOLE_GENERIC_INFO(mpc55xx_linflex_devices + 1, &mpc55xx_linflex_callbacks, "/dev/ttyS1")
+ #endif
+};
+
+CONSOLE_GENERIC_INFO_COUNT;
+
+CONSOLE_GENERIC_MINOR(0);
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-esci.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-esci.c
new file mode 100644
index 0000000000..737936b75f
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-esci.c
@@ -0,0 +1,339 @@
+/**
+ * @file
+ *
+ * @brief Console ESCI implementation.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/console-esci.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+
+#ifdef MPC55XX_HAS_ESCI
+
+mpc55xx_esci_context mpc55xx_esci_devices [] = {
+ {
+ .regs = &ESCI_A,
+ .irq = MPC55XX_IRQ_ESCI(0)
+ }, {
+ .regs = &ESCI_B,
+ .irq = MPC55XX_IRQ_ESCI(1)
+ }
+};
+
+static void mpc55xx_esci_poll_write(int minor, char c)
+{
+ mpc55xx_esci_context *self = console_generic_get_context(minor);
+ const union ESCI_SR_tag clear_tdre = { .B = { .TDRE = 1 } };
+ volatile struct ESCI_tag *regs = self->regs;
+ rtems_interrupt_level level;
+ bool done = false;
+ bool wait_for_transmit_done = false;
+
+ rtems_interrupt_disable(level);
+ if (self->transmit_nest_level == 0) {
+ union ESCI_CR1_tag cr1 = { .R = regs->CR1.R };
+
+ if (cr1.B.TIE != 0) {
+ cr1.B.TIE = 0;
+ regs->CR1.R = cr1.R;
+ wait_for_transmit_done = !self->transmit_in_progress;
+ self->transmit_nest_level = 1;
+ }
+ } else {
+ ++self->transmit_nest_level;
+ }
+ rtems_interrupt_enable(level);
+
+ while (!done) {
+ rtems_interrupt_disable(level);
+ bool tx = self->transmit_in_progress;
+ if (!tx || (tx && regs->SR.B.TDRE)) {
+ regs->SR.R = clear_tdre.R;
+ regs->DR.B.D = c;
+ self->transmit_in_progress = true;
+ done = true;
+ }
+ rtems_interrupt_enable(level);
+ }
+
+ done = false;
+ while (!done) {
+ rtems_interrupt_disable(level);
+ if (wait_for_transmit_done) {
+ if (regs->SR.B.TDRE) {
+ regs->SR.R = clear_tdre.R;
+ self->transmit_in_progress = false;
+ done = true;
+ }
+ } else {
+ done = true;
+ }
+
+ if (done && self->transmit_nest_level > 0) {
+ --self->transmit_nest_level;
+
+ if (self->transmit_nest_level == 0) {
+ union ESCI_CR1_tag cr1 = { .R = regs->CR1.R };
+
+ cr1.B.TIE = 1;
+ regs->CR1.R = cr1.R;
+ }
+ }
+ rtems_interrupt_enable(level);
+ }
+}
+
+static inline void mpc55xx_esci_interrupts_clear_and_enable(
+ mpc55xx_esci_context *self
+)
+{
+ volatile struct ESCI_tag *regs = self->regs;
+ union ESCI_CR1_tag cr1 = MPC55XX_ZERO_FLAGS;
+ rtems_interrupt_level level;
+
+ rtems_interrupt_disable(level);
+ cr1.R = regs->CR1.R;
+ cr1.B.RIE = 1;
+ cr1.B.TIE = 1;
+ regs->CR1.R = cr1.R;
+ regs->SR.R = regs->SR.R;
+ rtems_interrupt_enable(level);
+}
+
+static inline void mpc55xx_esci_interrupts_disable(mpc55xx_esci_context *self)
+{
+ volatile struct ESCI_tag *regs = self->regs;
+ union ESCI_CR1_tag cr1 = MPC55XX_ZERO_FLAGS;
+ rtems_interrupt_level level;
+
+ rtems_interrupt_disable(level);
+ cr1.R = regs->CR1.R;
+ cr1.B.RIE = 0;
+ cr1.B.TIE = 0;
+ regs->CR1.R = cr1.R;
+ rtems_interrupt_enable(level);
+}
+
+static void mpc55xx_esci_interrupt_handler(void *arg)
+{
+ mpc55xx_esci_context *self = arg;
+ volatile struct ESCI_tag *regs = self->regs;
+ union ESCI_SR_tag sr = MPC55XX_ZERO_FLAGS;
+ union ESCI_SR_tag active = MPC55XX_ZERO_FLAGS;
+ rtems_interrupt_level level;
+
+ /* Status */
+ sr.R = regs->SR.R;
+
+ /* Receive data register full? */
+ if (sr.B.RDRF != 0) {
+ active.B.RDRF = 1;
+ }
+
+ /* Transmit data register empty? */
+ if (sr.B.TDRE != 0) {
+ active.B.TDRE = 1;
+ }
+
+ /* Clear flags */
+ rtems_interrupt_disable(level);
+ regs->SR.R = active.R;
+ self->transmit_in_progress = false;
+ rtems_interrupt_enable(level);
+
+ /* Enqueue */
+ if (active.B.RDRF != 0) {
+ char c = regs->DR.B.D;
+ rtems_termios_enqueue_raw_characters(self->tty, &c, 1);
+ }
+
+ /* Dequeue */
+ if (active.B.TDRE != 0) {
+ rtems_termios_dequeue_characters(self->tty, 1);
+ }
+}
+
+static int mpc55xx_esci_set_attributes(int minor, const struct termios *t)
+{
+ mpc55xx_esci_context *self = console_generic_get_context(minor);
+ volatile struct ESCI_tag *regs = self->regs;
+ union ESCI_CR1_tag cr1 = { .R = regs->CR1.R };
+ union ESCI_CR2_tag cr2 = MPC55XX_ZERO_FLAGS;
+ rtems_termios_baud_t br = rtems_termios_baud_to_number(t->c_cflag);
+
+ /* Enable module */
+ cr2.B.MDIS = 0;
+
+ /* Interrupts */
+ cr1.B.TCIE = 0;
+ cr1.B.ILIE = 0;
+ cr2.B.IEBERR = 0;
+ cr2.B.ORIE = 0;
+ cr2.B.NFIE = 0;
+ cr2.B.FEIE = 0;
+ cr2.B.PFIE = 0;
+
+ /* Disable receiver wake-up standby */
+ cr1.B.RWU = 0;
+
+ /* Disable DMA channels */
+ cr2.B.RXDMA = 0;
+ cr2.B.TXDMA = 0;
+
+ /* Idle line type */
+ cr1.B.ILT = 0;
+
+ /* Disable loops */
+ cr1.B.LOOPS = 0;
+
+ /* Enable or disable receiver */
+ cr1.B.RE = (t->c_cflag & CREAD) ? 1 : 0;
+
+ /* Enable transmitter */
+ cr1.B.TE = 1;
+
+ /* Baud rate */
+ if (br > 0) {
+ br = bsp_clock_speed / (16 * br);
+ br = (br > 8191) ? 8191 : br;
+ } else {
+ br = 0;
+ }
+ cr1.B.SBR = br;
+
+ /* Number of data bits */
+ if ((t->c_cflag & CSIZE) != CS8) {
+ return -1;
+ }
+ cr1.B.M = 0;
+
+ /* Parity */
+ cr1.B.PE = (t->c_cflag & PARENB) ? 1 : 0;
+ cr1.B.PT = (t->c_cflag & PARODD) ? 1 : 0;
+
+ /* Stop bits */
+ if (t->c_cflag & CSTOPB ) {
+ /* Two stop bits */
+ return -1;
+ }
+
+ /* Disable LIN */
+ regs->LCR.R = 0;
+
+ /* Set control registers */
+ regs->CR2.R = cr2.R;
+ regs->CR1.R = cr1.R;
+
+ return 0;
+}
+
+static int mpc55xx_esci_first_open(int major, int minor, void *arg)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+ int rv = 0;
+ mpc55xx_esci_context *self = console_generic_get_context(minor);
+ struct rtems_termios_tty *tty = console_generic_get_tty_at_open(arg);
+
+ self->tty = tty;
+
+ rv = rtems_termios_set_initial_baud(tty, 115200);
+ if (rv != 0) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ rv = mpc55xx_esci_set_attributes(minor, &tty->termios);
+ if (rv != 0) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ sc = mpc55xx_interrupt_handler_install(
+ self->irq,
+ "eSCI",
+ RTEMS_INTERRUPT_UNIQUE,
+ MPC55XX_INTC_DEFAULT_PRIORITY,
+ mpc55xx_esci_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ mpc55xx_esci_interrupts_clear_and_enable(self);
+ self->transmit_in_progress = false;
+
+ return 0;
+}
+
+static int mpc55xx_esci_last_close(int major, int minor, void* arg)
+{
+ mpc55xx_esci_context *self = console_generic_get_context(minor);
+
+ mpc55xx_esci_interrupts_disable(self);
+ self->tty = NULL;
+
+ return 0;
+}
+
+static int mpc55xx_esci_poll_read(int minor)
+{
+ mpc55xx_esci_context *self = console_generic_get_context(minor);
+ volatile struct ESCI_tag *regs = self->regs;
+ union ESCI_SR_tag sr = MPC55XX_ZERO_FLAGS;
+ rtems_interrupt_level level;
+ int c = -1;
+
+ rtems_interrupt_disable(level);
+ if (regs->SR.B.RDRF != 0) {
+ /* Clear flag */
+ sr.B.RDRF = 1;
+ regs->SR.R = sr.R;
+
+ /* Read */
+ c = regs->DR.B.D;
+ }
+ rtems_interrupt_enable(level);
+
+ return c;
+}
+
+static int mpc55xx_esci_write(int minor, const char *out, size_t n)
+{
+ mpc55xx_esci_context *self = console_generic_get_context(minor);
+ rtems_interrupt_level level;
+
+ rtems_interrupt_disable(level);
+ self->regs->DR.B.D = out [0];
+ self->transmit_in_progress = true;
+ rtems_interrupt_enable(level);
+
+ return 0;
+}
+
+const console_generic_callbacks mpc55xx_esci_callbacks = {
+ .termios_callbacks = {
+ .firstOpen = mpc55xx_esci_first_open,
+ .lastClose = mpc55xx_esci_last_close,
+ .write = mpc55xx_esci_write,
+ .setAttributes = mpc55xx_esci_set_attributes,
+ .outputUsesInterrupts = TERMIOS_IRQ_DRIVEN
+ },
+ .poll_read = mpc55xx_esci_poll_read,
+ .poll_write = mpc55xx_esci_poll_write
+};
+
+#endif /* MPC55XX_HAS_ESCI */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-generic.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-generic.c
new file mode 100644
index 0000000000..e6c2c587a2
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-generic.c
@@ -0,0 +1,167 @@
+/**
+ * @file
+ *
+ * @brief Generic console driver implementation.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/console-generic.h>
+
+#include <rtems/console.h>
+
+static const struct termios console_generic_termios = {
+ .c_cflag = CS8 | CREAD | CLOCAL | B115200
+};
+
+static void console_generic_char_out(char c)
+{
+ int minor = (int) console_generic_minor;
+ const console_generic_callbacks *cb =
+ console_generic_info_table [minor].callbacks;
+
+ if (c == '\n') {
+ (*cb->poll_write)(minor, '\r');
+ }
+
+ (*cb->poll_write)(minor, c);
+}
+
+static int console_generic_char_in(void)
+{
+ int minor = (int) console_generic_minor;
+ const console_generic_callbacks *cb =
+ console_generic_info_table [minor].callbacks;
+
+ return (*cb->poll_read)(minor);
+}
+
+static void console_generic_char_out_do_init(void)
+{
+ int minor = (int) console_generic_minor;
+ const console_generic_callbacks *cb =
+ console_generic_info_table [minor].callbacks;
+ const struct termios *term = &console_generic_termios;
+
+ BSP_output_char = console_generic_char_out;
+ (*cb->termios_callbacks.setAttributes)(minor, term);
+}
+
+static void console_generic_char_out_init(char c)
+{
+ console_generic_char_out_do_init();
+ console_generic_char_out(c);
+}
+
+rtems_device_driver console_initialize(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+ const console_generic_info *info_table = console_generic_info_table;
+ rtems_device_minor_number count = console_generic_info_count;
+ rtems_device_minor_number console = console_generic_minor;
+
+ if (count <= 0) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ rtems_termios_initialize();
+
+ for (minor = 0; minor < count; ++minor) {
+ const console_generic_info *info = info_table + minor;
+
+ sc = rtems_io_register_name(info->device_path, major, minor);
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+ }
+
+ sc = rtems_io_register_name(CONSOLE_DEVICE_NAME, major, console);
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ console_generic_char_out_do_init();
+
+ return sc;
+}
+
+rtems_device_driver console_open(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+ rtems_device_minor_number count = console_generic_info_count;
+
+ if (minor < count) {
+ const console_generic_info *info = &console_generic_info_table [minor];
+
+ sc = rtems_termios_open(
+ major,
+ minor,
+ arg,
+ &info->callbacks->termios_callbacks
+ );
+ } else {
+ sc = RTEMS_INVALID_ID;
+ }
+
+ return sc;
+}
+
+rtems_device_driver console_close(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ return rtems_termios_close(arg);
+}
+
+rtems_device_driver console_read(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ return rtems_termios_read(arg);
+}
+
+rtems_device_driver console_write(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ return rtems_termios_write(arg);
+}
+
+rtems_device_driver console_control(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+)
+{
+ return rtems_termios_ioctl(arg);
+}
+
+BSP_output_char_function_type BSP_output_char = console_generic_char_out_init;
+
+BSP_polling_getchar_function_type BSP_poll_char = console_generic_char_in;
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-linflex.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-linflex.c
new file mode 100644
index 0000000000..54ac08ed56
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/console/console-linflex.c
@@ -0,0 +1,419 @@
+/**
+ * @file
+ *
+ * @brief Console LINFlexD implementation.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/console-linflex.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+
+#ifdef MPC55XX_HAS_LINFLEX
+
+mpc55xx_linflex_context mpc55xx_linflex_devices [] = {
+ {
+ .regs = &LINFLEX0,
+ .irq_rxi = MPC55XX_IRQ_LINFLEX_RXI(0),
+ .irq_txi = MPC55XX_IRQ_LINFLEX_TXI(0),
+ .irq_err = MPC55XX_IRQ_LINFLEX_ERR(0),
+ .tx_pcr_register = &((SIU_tag *) &SIUL)->PCR18,
+ .tx_pa_value = 1,
+ .rx_pcr_register = &((SIU_tag *) &SIUL)->PCR19,
+ .rx_psmi_register = &((SIU_tag *) &SIUL)->PSMI31,
+ .rx_padsel_value = 0
+ }, {
+ .regs = &LINFLEX1,
+ .irq_rxi = MPC55XX_IRQ_LINFLEX_RXI(1),
+ .irq_txi = MPC55XX_IRQ_LINFLEX_TXI(1),
+ .irq_err = MPC55XX_IRQ_LINFLEX_ERR(1),
+ .tx_pcr_register = &((SIU_tag *) &SIUL)->PCR94,
+ .tx_pa_value = 1,
+ .rx_pcr_register = &((SIU_tag *) &SIUL)->PCR95,
+ .rx_psmi_register = &((SIU_tag *) &SIUL)->PSMI32,
+ .rx_padsel_value = 2
+ }
+};
+
+void enter_init_mode(volatile LINFLEX_tag *regs)
+{
+ LINFLEX_LINCR1_32B_tag cr1 = { .R = regs->LINCR1.R };
+ cr1.B.SLEEP = 0;
+ cr1.B.INIT = 1;
+ regs->LINCR1.R = cr1.R;
+}
+
+void enter_active_mode(volatile LINFLEX_tag *regs)
+{
+ LINFLEX_LINCR1_32B_tag cr1 = { .R = regs->LINCR1.R };
+ cr1.B.SLEEP = 0;
+ cr1.B.INIT = 0;
+ regs->LINCR1.R = cr1.R;
+}
+
+void enter_sleep_mode(volatile LINFLEX_tag *regs)
+{
+ LINFLEX_LINCR1_32B_tag cr1 = { .R = regs->LINCR1.R };
+ cr1.B.SLEEP = 1;
+ cr1.B.INIT = 0;
+ regs->LINCR1.R = cr1.R;
+}
+
+static void mpc55xx_linflex_poll_write(int minor, char c)
+{
+ mpc55xx_linflex_context *self = console_generic_get_context(minor);
+ volatile LINFLEX_tag *regs = self->regs;
+ const LINFLEX_UARTSR_32B_tag clear_dtf = { .B = { .DTF_TFF = 1 } };
+ rtems_interrupt_level level;
+ bool done = false;
+ bool wait_for_transmit_done = false;
+
+ rtems_interrupt_disable(level);
+ if (self->transmit_nest_level == 0) {
+ LINFLEX_LINIER_32B_tag ier = { .R = regs->LINIER.R };
+
+ if (ier.B.DTIE != 0) {
+ ier.B.DTIE = 0;
+ regs->LINIER.R = ier.R;
+ wait_for_transmit_done = !self->transmit_in_progress;
+ self->transmit_nest_level = 1;
+ }
+ } else {
+ ++self->transmit_nest_level;
+ }
+ rtems_interrupt_enable(level);
+
+ while (!done) {
+ rtems_interrupt_disable(level);
+ bool tx = self->transmit_in_progress;
+ if (!tx || (tx && regs->UARTSR.B.DTF_TFF)) {
+ regs->UARTSR.R = clear_dtf.R;
+ regs->BDRL.B.DATA0 = c;
+ self->transmit_in_progress = true;
+ done = true;
+ }
+ rtems_interrupt_enable(level);
+ }
+
+ done = false;
+ while (!done) {
+ rtems_interrupt_disable(level);
+ if (wait_for_transmit_done) {
+ if (regs->UARTSR.B.DTF_TFF) {
+ regs->UARTSR.R = clear_dtf.R;
+ self->transmit_in_progress = false;
+ done = true;
+ }
+ } else {
+ done = true;
+ }
+
+ if (done && self->transmit_nest_level > 0) {
+ --self->transmit_nest_level;
+
+ if (self->transmit_nest_level == 0) {
+ LINFLEX_LINIER_32B_tag ier = { .R = regs->LINIER.R };
+
+ ier.B.DTIE = 1;
+ regs->LINIER.R = ier.R;
+ }
+ }
+ rtems_interrupt_enable(level);
+ }
+}
+
+static void mpc55xx_linflex_rx_interrupt_handler(void *arg)
+{
+ mpc55xx_linflex_context *self = arg;
+ volatile LINFLEX_tag *regs = self->regs;
+ char c = regs->BDRM.B.DATA4;
+ const LINFLEX_UARTSR_32B_tag clear_flags = { .B = { .RMB = 1, .DRF_RFE = 1 } };
+
+ regs->UARTSR.R = clear_flags.R;
+
+ rtems_termios_enqueue_raw_characters(self->tty, &c, 1);
+}
+
+static void mpc55xx_linflex_tx_interrupt_handler(void *arg)
+{
+ mpc55xx_linflex_context *self = arg;
+ volatile LINFLEX_tag *regs = self->regs;
+
+ regs->UARTSR.B.DTF_TFF = 1; /* clear flag */
+ self->transmit_in_progress = false;
+
+ rtems_termios_dequeue_characters(self->tty, 1);
+}
+
+/*
+static void mpc55xx_linflex_err_interrupt_handler(void *arg)
+{
+ mpc55xx_linflex_context *self = arg;
+}
+*/
+
+static int mpc55xx_linflex_set_attributes(int minor, const struct termios *t)
+{
+ mpc55xx_linflex_context *self = console_generic_get_context(minor);
+ volatile LINFLEX_tag *regs = self->regs;
+ LINFLEX_UARTCR_32B_tag uartcr = { .R = 0 };
+ LINFLEX_GCR_32B_tag gcr = { .R = 0 };
+ LINFLEX_LINIER_32B_tag ier = { .R = 0 };
+ rtems_termios_baud_t br = rtems_termios_baud_to_number(t->c_cflag);
+ LINFLEX_LINFBRR_32B_tag fbrr = { .R = 0 };
+ LINFLEX_LINIBRR_32B_tag ibrr = { .R = 0 };
+
+ enter_init_mode(regs);
+
+ /* Set to UART-mode */
+ uartcr.B.UART = 1;
+ regs->UARTCR.R = uartcr.R;
+
+ /* Set to buffer mode with size 1 */
+ uartcr.B.TDFL_TFC = 0;
+ uartcr.B.RDFL_RFC0 = 0;
+ uartcr.B.RFBM = 0;
+ uartcr.B.TFBM = 0;
+
+ /* Enable receiver and transmitter */
+ uartcr.B.RXEN = 1;
+ uartcr.B.TXEN = 1;
+
+ /* Number of data bits */
+ uartcr.B.WL1 = 0;
+ if ((t->c_cflag & CSIZE) == CS8) {
+ uartcr.B.WL0 = 1;
+ } else if ((t->c_cflag & CSIZE) == CS7) {
+ uartcr.B.WL0 = 0;
+ } else {
+ return -1;
+ }
+
+ /* Parity */
+ uartcr.B.PCE = (t->c_cflag & PARENB) ? 1 : 0;
+ uartcr.B.PC1 = 0;
+ uartcr.B.PC0 = (t->c_cflag & PARODD) ? 1 : 0;
+
+ /* Stop bits */
+ gcr.B.STOP = (t->c_cflag & CSTOPB) ? 1 : 0;
+
+ /* Set control registers */
+ regs->UARTCR.R = uartcr.R;
+ regs->GCR.R = gcr.R;
+
+ /* Interrupts */
+ ier.B.DTIE = 1;
+ ier.B.DRIE = 1;
+ regs->LINIER.R = ier.R;
+
+ /* Baud rate */
+ if (br > 0) {
+ uint32_t lfdiv_mult_32 = bsp_clock_speed * 2 / br;
+ if((lfdiv_mult_32 & 0x1) != 0) {
+ ++lfdiv_mult_32;
+ }
+ fbrr.B.FBR = (lfdiv_mult_32 >> 1) & 0xF;
+ ibrr.B.IBR = lfdiv_mult_32 >> 5;
+ } else {
+ return -1;
+ }
+ regs->LINFBRR.R = fbrr.R;
+ regs->LINIBRR.R = ibrr.R;
+
+ enter_active_mode(regs);
+
+ return 0;
+}
+
+static int mpc55xx_linflex_first_open(int major, int minor, void *arg)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+ int rv = 0;
+ mpc55xx_linflex_context *self = console_generic_get_context(minor);
+ struct rtems_termios_tty *tty = console_generic_get_tty_at_open(arg);
+ SIU_PCR_tag pcr = { .R = 0 };
+ SIUL_PSMI_8B_tag psmi = { .R = 0 };
+
+ self->tty = tty;
+
+ pcr.B.IBE = 1;
+ self->rx_pcr_register->R = pcr.R;
+ psmi.B.PADSEL = self->rx_padsel_value;
+ self->rx_psmi_register->R = psmi.R;
+ pcr.R = 0;
+ pcr.B.OBE = 1;
+ pcr.B.PA = self->tx_pa_value;
+ self->tx_pcr_register->R = pcr.R;
+
+ rv = rtems_termios_set_initial_baud(tty, 115200);
+ if (rv != 0) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ rv = mpc55xx_linflex_set_attributes(minor, &tty->termios);
+ if (rv != 0) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ sc = mpc55xx_interrupt_handler_install(
+ self->irq_rxi,
+ "LINFlexD RXI",
+ RTEMS_INTERRUPT_UNIQUE,
+ MPC55XX_INTC_DEFAULT_PRIORITY,
+ mpc55xx_linflex_rx_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ sc = mpc55xx_interrupt_handler_install(
+ self->irq_txi,
+ "LINFlexD TXI",
+ RTEMS_INTERRUPT_UNIQUE,
+ MPC55XX_INTC_DEFAULT_PRIORITY,
+ mpc55xx_linflex_tx_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ /*
+ sc = mpc55xx_interrupt_handler_install(
+ self->irq_err,
+ "LINFlexD ERR",
+ RTEMS_INTERRUPT_UNIQUE,
+ MPC55XX_INTC_DEFAULT_PRIORITY,
+ mpc55xx_linflex_err_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+ */
+
+ return 0;
+}
+
+static int mpc55xx_linflex_last_close(int major, int minor, void* arg)
+{
+ rtems_status_code sc = RTEMS_SUCCESSFUL;
+ mpc55xx_linflex_context *self = console_generic_get_context(minor);
+ volatile LINFLEX_tag *regs = self->regs;
+ SIU_PCR_tag pcr = { .R = 0 };
+ SIUL_PSMI_8B_tag psmi = { .R = 0 };
+
+ /* enter initialization mode */
+ enter_init_mode(regs);
+
+ /* disable interrupts */
+ regs->LINIER.R = 0;
+
+ /* set module to sleep mode */
+ enter_sleep_mode(regs);
+
+ sc = rtems_interrupt_handler_remove(
+ self->irq_rxi,
+ mpc55xx_linflex_rx_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ sc = rtems_interrupt_handler_remove(
+ self->irq_txi,
+ mpc55xx_linflex_tx_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+
+ /*
+ sc = rtems_interrupt_handler_remove(
+ self->irq_err,
+ mpc55xx_linflex_err_interrupt_handler,
+ self
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ rtems_fatal_error_occurred(0xdeadbeef);
+ }
+ */
+
+ pcr.B.IBE = 1;
+ self->rx_pcr_register->R = pcr.R;
+ self->tx_pcr_register->R = pcr.R;
+ psmi.R = 0;
+ self->rx_psmi_register->R = psmi.R;
+
+ self->tty = NULL;
+
+ return 0;
+}
+
+static int mpc55xx_linflex_poll_read(int minor)
+{
+ mpc55xx_linflex_context *self = console_generic_get_context(minor);
+ volatile LINFLEX_tag *regs = self->regs;
+ rtems_interrupt_level level;
+ int c = -1;
+
+ rtems_interrupt_disable(level);
+ if (regs->UARTSR.B.DRF_RFE != 0) {
+ /* Clear flag */
+ regs->UARTSR.B.DRF_RFE = 1;
+
+ /* Read */
+ c = regs->BDRM.B.DATA4;
+ }
+ rtems_interrupt_enable(level);
+
+ return c;
+}
+
+static int mpc55xx_linflex_write(int minor, const char *out, size_t n)
+{
+ mpc55xx_linflex_context *self = console_generic_get_context(minor);
+ volatile LINFLEX_tag *regs = self->regs;
+ rtems_interrupt_level level;
+
+ rtems_interrupt_disable(level);
+
+ regs->BDRL.B.DATA0 = out [0];
+ self->transmit_in_progress = true;
+ /* TODO: send more then one byte */
+
+ rtems_interrupt_enable(level);
+
+ return 0;
+}
+
+const console_generic_callbacks mpc55xx_linflex_callbacks = {
+ .termios_callbacks = {
+ .firstOpen = mpc55xx_linflex_first_open,
+ .lastClose = mpc55xx_linflex_last_close,
+ .write = mpc55xx_linflex_write,
+ .setAttributes = mpc55xx_linflex_set_attributes,
+ .outputUsesInterrupts = TERMIOS_IRQ_DRIVEN
+ },
+ .poll_read = mpc55xx_linflex_poll_read,
+ .poll_write = mpc55xx_linflex_poll_write
+};
+
+#endif /* MPC55XX_HAS_LINFLEX */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-esci.h b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-esci.h
new file mode 100644
index 0000000000..1e51ecde7e
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-esci.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * @brief Console ESCI API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H
+#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H
+
+#include "console-generic.h"
+
+#undef CR0
+#undef CR1
+#undef CR2
+#undef CR3
+
+#include <mpc55xx/regs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef MPC55XX_HAS_ESCI
+
+extern const console_generic_callbacks mpc55xx_esci_callbacks;
+
+typedef struct {
+ volatile struct ESCI_tag *regs;
+ struct rtems_termios_tty *tty;
+ int transmit_nest_level;
+ bool transmit_in_progress;
+ rtems_vector_number irq;
+} mpc55xx_esci_context;
+
+extern mpc55xx_esci_context mpc55xx_esci_devices [];
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_ESCI_H */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-generic.h b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-generic.h
new file mode 100644
index 0000000000..630f9da873
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-generic.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * @brief Generic console driver API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_SHARED_CONSOLE_GENERIC_H
+#define LIBBSP_SHARED_CONSOLE_GENERIC_H
+
+#include <rtems/libio.h>
+#include <rtems/termiostypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+typedef struct {
+ rtems_termios_callbacks termios_callbacks;
+ int (*poll_read)(int minor);
+ void (*poll_write)(int minor, char c);
+} console_generic_callbacks;
+
+typedef struct {
+ void *context;
+ const console_generic_callbacks *callbacks;
+ const char *device_path;
+} console_generic_info;
+
+extern const console_generic_info console_generic_info_table [];
+
+extern const size_t console_generic_info_count;
+
+extern const rtems_device_minor_number console_generic_minor;
+
+#define CONSOLE_GENERIC_INFO_TABLE \
+ const console_generic_info console_generic_info_table []
+
+#define CONSOLE_GENERIC_INFO(context, callbacks, device_path) \
+ { context, callbacks, device_path }
+
+#define CONSOLE_GENERIC_INFO_COUNT \
+ const size_t console_generic_info_count = \
+ sizeof(console_generic_info_table) / sizeof(console_generic_info_table [0])
+
+#define CONSOLE_GENERIC_MINOR(minor) \
+ const rtems_device_minor_number console_generic_minor = (minor)
+
+static inline void *console_generic_get_context(int minor)
+{
+ return console_generic_info_table [minor].context;
+}
+
+static inline struct rtems_termios_tty *console_generic_get_tty_at_open(
+ void *arg
+)
+{
+ const rtems_libio_open_close_args_t *oc =
+ (const rtems_libio_open_close_args_t *) arg;
+
+ return (struct rtems_termios_tty *) oc->iop->data1;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_SHARED_CONSOLE_GENERIC_H */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-linflex.h b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-linflex.h
new file mode 100644
index 0000000000..791bb8c983
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/console-linflex.h
@@ -0,0 +1,64 @@
+/**
+ * @file
+ *
+ * @brief Console LINFlexD API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H
+#define LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H
+
+#include "console-generic.h"
+
+#undef CR0
+#undef CR1
+#undef CR2
+#undef CR3
+
+#include <mpc55xx/regs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef MPC55XX_HAS_LINFLEX
+
+extern const console_generic_callbacks mpc55xx_linflex_callbacks;
+
+typedef struct {
+ volatile LINFLEX_tag *regs;
+ struct rtems_termios_tty *tty;
+ rtems_vector_number irq_rxi;
+ rtems_vector_number irq_txi;
+ rtems_vector_number irq_err;
+ volatile SIU_PCR_tag *tx_pcr_register;
+ uint8_t tx_pa_value:2;
+ volatile SIU_PCR_tag *rx_pcr_register;
+ volatile SIUL_PSMI_8B_tag *rx_psmi_register;
+ uint8_t rx_padsel_value:4;
+ int transmit_nest_level;
+ bool transmit_in_progress;
+} mpc55xx_linflex_context;
+
+extern mpc55xx_linflex_context mpc55xx_linflex_devices [];
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_MPC55XXEVB_CONSOLE_LINFLEX_H */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h
index 181e519921..93d212f807 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h
@@ -3,7 +3,7 @@
*
* @ingroup mpc55xx
*
- * @brief MPC55XX low-level configuration.
+ * @brief Low-level configuration.
*/
/*
@@ -27,6 +27,10 @@
#include <stddef.h>
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp/start.h>
+
#include <mpc55xx/regs.h>
#include <mpc55xx/regs-mmu.h>
@@ -38,25 +42,89 @@ typedef struct {
uint16_t index;
uint16_t count;
union SIU_PCR_tag pcr;
-} mpc55xx_siu_pcr_config_entry;
+} mpc55xx_siu_pcr_config;
+
+extern const mpc55xx_siu_pcr_config mpc55xx_start_config_siu_pcr [];
+
+extern const size_t mpc55xx_start_config_siu_pcr_count [];
+
+extern const struct MMU_tag mpc55xx_start_config_mmu_early [];
+
+extern const size_t mpc55xx_start_config_mmu_early_count [];
+
+extern const struct MMU_tag mpc55xx_start_config_mmu [];
+
+extern const size_t mpc55xx_start_config_mmu_count [];
+
+#ifdef MPC55XX_HAS_FMPLL
+ typedef struct {
+ union FMPLL_SYNCR_tag syncr_tmp;
+ union FMPLL_SYNCR_tag syncr_final;
+ } mpc55xx_clock_config;
+#endif
+
+#ifdef MPC55XX_HAS_FMPLL_ENHANCED
+ typedef struct {
+ union FMPLL_ESYNCR2_tag esyncr2_tmp;
+ union FMPLL_ESYNCR2_tag esyncr2_final;
+ union FMPLL_ESYNCR1_tag esyncr1_final;
+ } mpc55xx_clock_config;
+#endif
+
+#ifdef MPC55XX_HAS_MODE_CONTROL
+ typedef struct {
+ struct {
+ PLLD_CR_32B_tag cr;
+ PLLD_MR_32B_tag mr;
+ } fmpll [2];
+ CGM_OC_EN_32B_tag oc_en;
+ CGM_OCDS_SC_32B_tag ocds_sc;
+ CGM_SC_DC0_3_32B_tag sc_dc0_3;
+ CGM_AUXCLK_tag auxclk [5];
+ } mpc55xx_clock_config;
+#endif
+
+extern const mpc55xx_clock_config mpc55xx_start_config_clock [];
+
+#ifdef MPC55XX_HAS_EBI
+ extern const struct EBI_CS_tag mpc55xx_start_config_ebi_cs [];
+
+ extern const size_t mpc55xx_start_config_ebi_cs_count [];
+
+ extern const struct EBI_CAL_CS_tag mpc55xx_start_config_ebi_cal_cs [];
+
+ extern const size_t mpc55xx_start_config_ebi_cal_cs_count [];
+#endif
+
+void mpc55xx_start_early(void);
+
+void mpc55xx_start_flash(void);
-extern const mpc55xx_siu_pcr_config_entry mpc55xx_siu_pcr_config [];
+void mpc55xx_start_cache(void);
-extern const size_t mpc55xx_siu_pcr_config_count [];
+void mpc55xx_start_clock(void);
-extern const struct MMU_tag mpc55xx_mmu_config [];
+void mpc55xx_start_watchdog(void);
-extern const size_t mpc55xx_mmu_config_count [];
+void mpc55xx_start_mmu_apply_config(const struct MMU_tag *config, size_t count);
-extern const struct EBI_CS_tag mpc55xx_ebi_cs_config [];
+uint32_t mpc55xx_get_system_clock(void);
-extern const size_t mpc55xx_ebi_cs_config_count [];
+LINKER_SYMBOL(bsp_ram_start)
+LINKER_SYMBOL(bsp_ram_end)
+LINKER_SYMBOL(bsp_ram_size)
-extern const struct EBI_CAL_CS_tag mpc55xx_ebi_cal_cs_config [];
+LINKER_SYMBOL(bsp_ram_1_start)
+LINKER_SYMBOL(bsp_ram_1_end)
+LINKER_SYMBOL(bsp_ram_1_size)
-extern const size_t mpc55xx_ebi_cal_cs_config_count [];
+LINKER_SYMBOL(bsp_rom_start)
+LINKER_SYMBOL(bsp_rom_end)
+LINKER_SYMBOL(bsp_rom_size)
-void mpc55xx_early_init(void);
+#ifdef MPC55XX_BOOTFLAGS
+ extern uint32_t mpc55xx_bootflag_0 [];
+#endif
#ifdef __cplusplus
}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/xkt564levb.cfg b/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/xkt564levb.cfg
new file mode 100644
index 0000000000..eb9c0db185
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/xkt564levb.cfg
@@ -0,0 +1,10 @@
+##
+#
+# @file
+#
+# @ingroup mpc55xx_config
+#
+# @brief Configuration file for XKT564LEVB evaluation board.
+#
+
+include $(RTEMS_ROOT)/make/custom/mpc55xx.inc
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
index c1a00b0498..4202a49066 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
@@ -22,6 +22,10 @@
* $Id$
*/
+#include <rtems.h>
+
+#ifdef RTEMS_NETWORKING
+
#define __INSIDE_RTEMS_BSD_TCPIP_STACK__ 1
#define __BSD_VISIBLE 1
@@ -34,7 +38,6 @@
#include <string.h>
#include <inttypes.h>
-#include <rtems.h>
#include <rtems/rtems_bsdnet.h>
#include <rtems/rtems_mii_ioctl.h>
@@ -1909,3 +1912,5 @@ int smsc9218i_attach_detach(
/* FIXME: Return value */
return 0;
}
+
+#endif /* RTEMS_NETWORKING */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am
index 6e70981145..8992081670 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am
@@ -77,6 +77,10 @@ $(PROJECT_LIB)/linkcmds.mpc5674fevb_spe: startup/linkcmds.mpc5674fevb_spe $(PROJ
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5674fevb_spe
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5674fevb_spe
+$(PROJECT_LIB)/linkcmds.xkt564levb: startup/linkcmds.xkt564levb $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.xkt564levb
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.xkt564levb
+
$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
@@ -101,18 +105,6 @@ $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
-$(PROJECT_INCLUDE)/bsp/mpc55xxevb.h: include/mpc55xxevb.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
-
-$(PROJECT_INCLUDE)/bsp/smsc9218i.h: include/smsc9218i.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/smsc9218i.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/smsc9218i.h
-
-$(PROJECT_INCLUDE)/bsp/mpc55xx-config.h: include/mpc55xx-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
-
$(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h: ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h
@@ -141,3 +133,27 @@ $(PROJECT_INCLUDE)/bsp/tictac.h: ../shared/include/tictac.h $(PROJECT_INCLUDE)/b
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tictac.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tictac.h
+$(PROJECT_INCLUDE)/bsp/mpc55xx-config.h: include/mpc55xx-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
+
+$(PROJECT_INCLUDE)/bsp/mpc55xxevb.h: include/mpc55xxevb.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xxevb.h
+
+$(PROJECT_INCLUDE)/bsp/smsc9218i.h: include/smsc9218i.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/smsc9218i.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/smsc9218i.h
+
+$(PROJECT_INCLUDE)/bsp/console-esci.h: include/console-esci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console-esci.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console-esci.h
+
+$(PROJECT_INCLUDE)/bsp/console-generic.h: include/console-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console-generic.h
+
+$(PROJECT_INCLUDE)/bsp/console-linflex.h: include/console-linflex.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console-linflex.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console-linflex.h
+
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
index 6555a6e3de..66cfa17f14 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
@@ -43,11 +43,9 @@
#include <bsp/start.h>
#include <bsp/mpc55xx-config.h>
+extern Heap_Control *RTEMS_Malloc_Heap;
+
/* Symbols defined in linker command file */
-LINKER_SYMBOL(bsp_ram_start);
-LINKER_SYMBOL(bsp_ram_end);
-LINKER_SYMBOL(bsp_external_ram_start);
-LINKER_SYMBOL(bsp_external_ram_size);
LINKER_SYMBOL(mpc55xx_exc_vector_base);
unsigned int bsp_clock_speed = 0;
@@ -147,5 +145,20 @@ void bsp_start(void)
}
mpc55xx_edma_init();
- mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
+ #ifdef MPC55XX_EMIOS_PRESCALER
+ mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
+ #endif
+}
+
+void bsp_pretasking_hook(void)
+{
+ #if MPC55XX_CHIP_TYPE / 10 == 564
+ _Heap_Extend(
+ RTEMS_Malloc_Heap,
+ bsp_section_rwextra_end,
+ (uintptr_t) bsp_ram_end
+ - (uintptr_t) bsp_section_rwextra_end,
+ NULL
+ );
+ #endif
}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c
deleted file mode 100644
index 3b213f228a..0000000000
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
- * @file
- *
- * @ingroup mpc55xx
- *
- * @brief BSP early initialization code.
- */
-
-/*
- * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
- *
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * 82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * $Id$
- */
-
-#include <bsp/mpc55xx-config.h>
-#include <bsp/linker-symbols.h>
-#include <bsp/start.h>
-#include <bsp.h>
-
-#include <mpc55xx/mpc55xx.h>
-
-#include <string.h>
-
-#ifdef MPC55XX_BOOTFLAGS
-extern uint32_t mpc55xx_bootflag_0 [];
-#endif
-
-static void BSP_START_TEXT_SECTION mpc55xx_siu_init(void)
-{
- size_t i = 0;
-
-#if defined(MPC55XX_BOARD_GWLCFM)
- SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */
- SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */
- SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */
-#endif
-
- for (i = 0; i < mpc55xx_siu_pcr_config_count [0]; ++i) {
- const mpc55xx_siu_pcr_config_entry *e = &mpc55xx_siu_pcr_config [i];
- int j = e->index;
- int n = j + e->count;
- uint32_t pcr = e->pcr.R;
-
- while (j < n) {
- SIU.PCR [j].R = pcr;
- ++j;
- }
- }
-}
-
-static void BSP_START_TEXT_SECTION mpc55xx_ebi_chip_select_init(void)
-{
- size_t i = 0;
-
- for (i = 0; i < mpc55xx_ebi_cs_config_count [0]; ++i) {
- EBI.CS [i] = mpc55xx_ebi_cs_config [i];
- }
-
- for (i = 0; i < mpc55xx_ebi_cal_cs_config_count [0]; ++i) {
- EBI.CAL_CS [i] = mpc55xx_ebi_cal_cs_config [i];
- }
-}
-
-static void BSP_START_TEXT_SECTION mpc55xx_ebi_init(void)
-{
-#if defined(MPC55XX_BOARD_GWLCFM)
- /*
- * init EBI for Muxed AD bus
- */
- EBI.MCR.B.DBM = 1;
- EBI.MCR.B.AD_MUX = 1; /* use multiplexed bus */
- EBI.MCR.B.D16_31 = 1; /* use lower AD bus */
-
- SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */
-#elif defined(MPC55XX_BOARD_MPC5674FEVB)
- struct EBI_tag ebi = {
- .MCR = {
- .B = {
- .ACGE = 0,
- .MDIS = 0,
- .D16_31 = 0,
- .AD_MUX = 0,
- .DBM = 0
- }
- }
- };
-
- EBI.MCR.R = ebi.MCR.R;
-#endif
-}
-
-static void BSP_START_TEXT_SECTION mpc55xx_mmu_init(void)
-{
-#ifdef MPC55XX_BOOTFLAGS
- /* If the low bit of bootflag 0 is clear don't change the MMU. */
- bool do_mmu_init = (mpc55xx_bootflag_0 [0] & 1) != 0;
-#else
- bool do_mmu_init = true;
-#endif
-
- if (do_mmu_init) {
- size_t i = 0;
-
- for (i = 0; i < mpc55xx_mmu_config_count [0]; ++i) {
- const struct MMU_tag *tag = &mpc55xx_mmu_config [i];
- PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS0, tag->MAS0.R);
- PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS1, tag->MAS1.R);
- PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS2, tag->MAS2.R);
- PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS3, tag->MAS3.R);
- __asm__ volatile ("tlbwe");
- }
- }
-}
-
-static void BSP_START_TEXT_SECTION mpc55xx_load_section(
- void *dst,
- const void *src,
- size_t n
-)
-{
- if (dst != src) {
- memcpy(dst, src, n);
- }
-}
-
-void BSP_START_TEXT_SECTION mpc55xx_early_init(void)
-{
- mpc55xx_load_section(
- &bsp_section_fast_text_begin [0],
- &bsp_section_fast_text_load_begin [0],
- (size_t) bsp_section_fast_text_size
- );
- mpc55xx_load_section(
- &bsp_section_fast_data_begin [0],
- &bsp_section_fast_data_load_begin [0],
- (size_t) bsp_section_fast_data_size
- );
- mpc55xx_load_section(
- &bsp_section_data_begin [0],
- &bsp_section_data_load_begin [0],
- (size_t) bsp_section_data_size
- );
- mpc55xx_siu_init();
- mpc55xx_ebi_chip_select_init();
- mpc55xx_ebi_init();
- mpc55xx_mmu_init();
-}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/fmpll-syncr-vals.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/fmpll-syncr-vals.c
deleted file mode 100644
index 0fb7a8d4ae..0000000000
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/fmpll-syncr-vals.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/**
- * @file
- *
- * @ingroup mpc55xx
- *
- * @brief BSP startup code.
- */
-
-/*
- * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
- *
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * 82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * $Id$
- */
-
-#include <mpc55xx/regs.h>
-
-#if MPC55XX_CHIP_TYPE / 10 == 551 || MPC55XX_CHIP_TYPE / 10 == 567
-/*
- * define init values for FMPLL ESYNCRx
- * (used in start.S/fmpll.S)
- */
-#define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
-#define EMFD_VAL (MPC55XX_FMPLL_MFD-16)
-#define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
-#define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
-#define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
-
-const struct fmpll_syncr_vals_t {
- union FMPLL_ESYNCR2_tag esyncr2_temp;
- union FMPLL_ESYNCR2_tag esyncr2_final;
- union FMPLL_ESYNCR1_tag esyncr1_final;
-} mpc55xx_fmpll_config =
- {
- { /* esyncr2_temp */
- .B.LOCEN=0,
- .B.LOLRE=0,
- .B.LOCRE=0,
- .B.LOLIRQ=0,
- .B.LOCIRQ=0,
- .B.ERATE=0,
- .B.EDEPTH=0,
- .B.ERFD=ERFD_VAL+2 /* reduce output clock during init */
- },
- { /* esyncr2_final */
- .B.LOCEN=0,
- .B.LOLRE=0,
- .B.LOCRE=0,
- .B.LOLIRQ=0,
- .B.LOCIRQ=0,
- .B.ERATE=0,
-#if MPC55XX_CHIP_TYPE / 10 == 567
- .B.CLKCFG_DIS=1,
-#endif
- .B.EDEPTH=0,
- .B.ERFD=ERFD_VAL /* nominal output clock after init */
- },
- { /* esyncr1_final */
- .B.CLKCFG=7,
- .B.EPREDIV=EPREDIV_VAL,
- .B.EMFD=EMFD_VAL
- }
- };
-#else /* !(MPC55XX_CHIP_TYPE / 10 == 551 || MPC55XX_CHIP_TYPE / 10 == 567) */
-const struct fmpll_syncr_vals_t {
- union FMPLL_SYNCR_tag syncr_temp;
- union FMPLL_SYNCR_tag syncr_final;
-} mpc55xx_fmpll_config =
- {
- { /* syncr_temp */
- .B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
- .B.MFD=MPC55XX_FMPLL_MFD,
- .B.RFD=2,
- .B.LOCEN=1
- },
- { /* syncr_final */
- .B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
- .B.MFD=MPC55XX_FMPLL_MFD,
- .B.RFD=0,
- .B.LOCEN=1
- }
- };
-#endif /* !(MPC55XX_CHIP_TYPE / 10 == 551 || MPC55XX_CHIP_TYPE / 10 == 567) */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/get-system-clock.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/get-system-clock.c
new file mode 100644
index 0000000000..5e0c608d41
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/get-system-clock.c
@@ -0,0 +1,85 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief System clock calculation.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/mpc55xx-config.h>
+
+uint32_t mpc55xx_get_system_clock(void)
+{
+ uint32_t system_clock = 0;
+
+ #ifdef MPC55XX_HAS_FMPLL
+ volatile struct FMPLL_tag *fmpll = &FMPLL;
+ union FMPLL_SYNSR_tag synsr = { .R = fmpll->SYNSR.R };
+ uint32_t reference_clock = MPC55XX_FMPLL_REF_CLOCK;
+ bool pll_clock_mode = synsr.B.MODE != 0;
+ bool crystal_or_external_reference_mode = synsr.B.PLLSEL != 0;
+
+ if (pll_clock_mode) {
+ if (crystal_or_external_reference_mode) {
+ union FMPLL_SYNCR_tag syncr = { .R = fmpll->SYNCR.R };
+ uint32_t prediv = syncr.B.PREDIV;
+ uint32_t mfd = syncr.B.MFD;
+ uint32_t rfd = syncr.B.RFD;
+
+ system_clock = ((reference_clock * (mfd + 4)) >> rfd) / (prediv + 1);
+ } else {
+ system_clock = 2 * reference_clock;
+ }
+ } else {
+ system_clock = reference_clock;
+ }
+ #endif
+
+ #ifdef MPC55XX_HAS_FMPLL_ENHANCED
+ volatile struct FMPLL_tag *fmpll = &FMPLL;
+ union FMPLL_ESYNCR1_tag esyncr1 = { .R = fmpll->ESYNCR1.R };
+ uint32_t reference_clock = MPC55XX_FMPLL_REF_CLOCK;
+ bool normal_mode = (esyncr1.B.CLKCFG & 0x4U) != 0;
+
+ if (normal_mode) {
+ union FMPLL_ESYNCR2_tag esyncr2 = { .R = fmpll->ESYNCR2.R };
+ uint32_t eprediv = esyncr1.B.EPREDIV;
+ uint32_t emfd = esyncr1.B.EMFD;
+ uint32_t erfd = esyncr2.B.ERFD;
+
+ system_clock = (reference_clock * (emfd + 16))
+ / ((erfd + 1) * (eprediv + 1));
+ } else {
+ system_clock = reference_clock;
+ }
+ #endif
+
+ #ifdef MPC55XX_HAS_MODE_CONTROL
+ /* FIXME: Assumes normal mode and external oscillator */
+ PLLD_CR_32B_tag cr = { . R = CGM.FMPLL [0].CR.R };
+ uint32_t xosc = MPC55XX_FMPLL_REF_CLOCK;
+ uint32_t ldf = cr.B.NDIV;
+ uint32_t idf = cr.B.IDF + 1;
+ uint32_t odf = 2U << cr.B.ODF;
+
+ system_clock = (xosc * ldf) / (idf * odf);
+ #endif
+
+ return system_clock;
+}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.xkt564levb b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.xkt564levb
new file mode 100644
index 0000000000..503f52a887
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.xkt564levb
@@ -0,0 +1,36 @@
+MEMORY {
+ ROM : ORIGIN = 0x0, LENGTH = 1M
+ RAM_0 : ORIGIN = 0x40000000, LENGTH = 64K
+ RAM_1 : ORIGIN = 0x50000000, LENGTH = 64K
+ NIRVANA : ORIGIN = 0x0, LENGTH = 0
+}
+
+bsp_ram_start = ORIGIN (RAM_0);
+bsp_ram_size = LENGTH (RAM_0);
+bsp_ram_end = bsp_ram_start + bsp_ram_size;
+
+bsp_ram_1_start = ORIGIN (RAM_1);
+bsp_ram_1_size = LENGTH (RAM_1);
+bsp_ram_1_end = bsp_ram_1_start + bsp_ram_1_size;
+
+bsp_rom_start = ORIGIN (ROM);
+bsp_rom_size = LENGTH (ROM);
+bsp_rom_end = bsp_rom_start + bsp_rom_size;
+
+REGION_ALIAS ("REGION_START", ROM);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_0);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
+REGION_ALIAS ("REGION_TEXT", ROM);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
+REGION_ALIAS ("REGION_RODATA", ROM);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_0);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
+REGION_ALIAS ("REGION_DATA", RAM_0);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM);
+REGION_ALIAS ("REGION_BSS", RAM_0);
+REGION_ALIAS ("REGION_RWEXTRA", RAM_0);
+REGION_ALIAS ("REGION_WORK", RAM_1);
+REGION_ALIAS ("REGION_STACK", RAM_1);
+
+INCLUDE linkcmds.base
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c
index d9a04972ab..e0318fc573 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/reset.c
@@ -31,6 +31,10 @@
void bsp_reset(void)
{
while (true) {
- SIU.SRCR.R = 0x1;
+ #if MPC55XX_CHIP_TYPE / 10 == 564
+ /* TODO */
+ #else
+ SIU.SRCR.R = 1U << (31 - 0);
+ #endif
}
}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c
index 1f756a77b1..316dc81e3e 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c
@@ -28,6 +28,8 @@
#include <rtems/status-checks.h>
+#ifdef MPC55XX_BOARD_MPC5566EVB
+
static rtems_status_code mpc55xx_dspi_init(void)
{
int rv = 0;
@@ -38,10 +40,8 @@ static rtems_status_code mpc55xx_dspi_init(void)
rv = rtems_libi2c_initialize();
RTEMS_CHECK_RV_SC( rv, "rtems_libi2c_initialize");
-#if MPC55XX_CHIP_TYPE / 10 != 551
/* DSPI D inputs are taken from DSPI C */
SIU.DISR.R = 0x000000FC;
-#endif
/* DSPI A signals */
pcr.B.PA = 1;
@@ -158,3 +158,5 @@ rtems_status_code mpc55xx_sd_card_init( bool mount)
return RTEMS_SUCCESSFUL;
}
+
+#endif /* MPC55XX_BOARD_MPC5566EVB */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-cache.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-cache.S
new file mode 100644
index 0000000000..f966ab6665
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-cache.S
@@ -0,0 +1,106 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx_asm
+ *
+ * @brief Cache initialization.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <libcpu/powerpc-utility.h>
+
+#include <mpc55xx/regs.h>
+
+ .globl mpc55xx_start_cache
+
+ .section ".bsp_start_text", "ax"
+
+mpc55xx_start_cache:
+
+ /* Load zero, CINV, and CABT) */
+ li r0, 0
+ li r3, 0x2
+ li r4, 0x4
+
+#ifdef MPC55XX_HAS_INSTRUCTION_CACHE
+
+start_instruction_cache_invalidation:
+
+ /* Clear instruction cache invalidation abort */
+ mtspr FSL_EIS_L1CSR1, r0
+
+ /* Start instruction cache invalidation */
+ mtspr FSL_EIS_L1CSR1, r3
+
+get_instruction_cache_invalidation_status:
+
+ /* Get instruction cache invalidation status */
+ mfspr r5, FSL_EIS_L1CSR1
+
+ /* Check CABT */
+ and. r6, r5, r4
+ bne start_instruction_cache_invalidation
+
+ /* Check CINV */
+ and. r6, r5, r3
+ bne get_instruction_cache_invalidation_status
+
+ /* Save instruction cache settings */
+ LWI r6, 0x00010001
+ isync
+ msync
+ mtspr FSL_EIS_L1CSR1, r6
+
+#endif /* MPC55XX_HAS_INSTRUCTION_CACHE */
+
+#if defined(MPC55XX_HAS_DATA_CACHE) || defined(MPC55XX_HAS_UNIFIED_CACHE)
+
+start_data_cache_invalidation:
+
+ /* Clear data cache invalidation abort */
+ mtspr FSL_EIS_L1CSR0, r0
+
+ /* Start data cache invalidation */
+ mtspr FSL_EIS_L1CSR0, r3
+
+get_data_cache_invalidation_status:
+
+ /* Get data cache invalidation status */
+ mfspr r5, FSL_EIS_L1CSR0
+
+ /* Check CABT */
+ and. r6, r5, r4
+ bne start_data_cache_invalidation
+
+ /* Check CINV */
+ and. r6, r5, r3
+ bne get_data_cache_invalidation_status
+
+ /* Save data cache settings */
+#if MPC55XX_CHIP_TYPE / 10 != 567
+ /* FIXME: CORG??? 0x00180011 */
+ LWI r6, 0x00100001
+#else
+ LWI r6, 0x00190001
+#endif
+ isync
+ msync
+ mtspr FSL_EIS_L1CSR0, r6
+
+#endif /* defined(MPC55XX_HAS_DATA_CACHE) || defined(MPC55XX_HAS_UNIFIED_CACHE) */
+
+ /* Return */
+ blr
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-clock.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-clock.c
new file mode 100644
index 0000000000..6b8ff1eb77
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-clock.c
@@ -0,0 +1,99 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Clock and FMPLL initialization code.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/bootcard.h>
+#include <bsp/mpc55xx-config.h>
+
+#if defined(MPC55XX_HAS_FMPLL) || defined(MPC55XX_HAS_FMPLL_ENHANCED)
+ static BSP_START_TEXT_SECTION void fmpll_wait_for_lock(void)
+ {
+ int i = 0;
+ bool lock = false;
+
+ while (!lock && i < 6000) {
+ lock = FMPLL.SYNSR.B.LOCK != 0;
+ ++i;
+ }
+
+ if (!lock) {
+ bsp_reset();
+ }
+ }
+#endif
+
+BSP_START_TEXT_SECTION void mpc55xx_start_clock(void)
+{
+ const mpc55xx_clock_config *cfg = mpc55xx_start_config_clock;
+
+ #ifdef MPC55XX_HAS_FMPLL
+ volatile struct FMPLL_tag *fmpll = &FMPLL;
+
+ fmpll->SYNCR.R = cfg->syncr_tmp.R;
+ fmpll->SYNCR.R;
+ fmpll_wait_for_lock();
+
+ fmpll->SYNCR.R = cfg->syncr_final.R;
+ fmpll->SYNCR.R;
+ fmpll_wait_for_lock();
+ #endif
+
+ #ifdef MPC55XX_HAS_FMPLL_ENHANCED
+ volatile struct FMPLL_tag *fmpll = &FMPLL;
+
+ fmpll->ESYNCR2.R = cfg->esyncr2_tmp.R;
+ fmpll->ESYNCR2.R;
+ fmpll->ESYNCR1.R = cfg->esyncr1_final.R;
+ fmpll->ESYNCR1.R;
+ fmpll_wait_for_lock();
+
+ fmpll->ESYNCR2.R = cfg->esyncr2_final.R;
+ fmpll->ESYNCR2.R;
+ fmpll_wait_for_lock();
+
+ #if MPC55XX_CHIP_TYPE / 10 == 551
+ /* System clock supplied by PLL */
+ SIU.SYSCLK.B.SYSCLKSEL = 2;
+ #endif
+ #endif
+
+ #ifdef MPC55XX_HAS_MODE_CONTROL
+ volatile CGM_tag *cgm = &CGM;
+ size_t fmpll_count = sizeof(cfg->fmpll) / sizeof(cfg->fmpll [0]);
+ size_t auxclk_count = sizeof(cfg->auxclk) / sizeof(cfg->auxclk [0]);
+ size_t i = 0;
+
+ for (i = 0; i < auxclk_count; ++i) {
+ cgm->AUXCLK [i].AC_SC.R = cfg->auxclk [i].AC_SC.R;
+ cgm->AUXCLK [i].AC_DC0_3.R = cfg->auxclk [i].AC_DC0_3.R;
+ }
+
+ for (i = 0; i < fmpll_count; ++i) {
+ cgm->FMPLL [i].CR.R = cfg->fmpll [i].cr.R;
+ cgm->FMPLL [i].MR.R = cfg->fmpll [i].mr.R;
+ }
+
+ cgm->OC_EN.R = cfg->oc_en.R;
+ cgm->OCDS_SC.R = cfg->ocds_sc.R;
+ #endif
+}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-clock.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-clock.c
new file mode 100644
index 0000000000..0b0d568d8b
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-clock.c
@@ -0,0 +1,122 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Clock and FMPLL configuration.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/mpc55xx-config.h>
+
+BSP_START_TEXT_SECTION const mpc55xx_clock_config
+ mpc55xx_start_config_clock [1] = { {
+ #ifdef MPC55XX_HAS_FMPLL
+ .syncr_tmp = {
+ .B = {
+ .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
+ .MFD = MPC55XX_FMPLL_MFD,
+ .RFD = 2,
+ .LOCEN = 1
+ }
+ },
+ .syncr_final = {
+ .B = {
+ .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
+ .MFD = MPC55XX_FMPLL_MFD,
+ .RFD = 0,
+ .LOCEN = 1,
+ .LOLIRQ = 1,
+ .LOCIRQ = 1
+ }
+ }
+ #endif
+ #ifdef MPC55XX_HAS_FMPLL_ENHANCED
+ #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
+ #define EMFD_VAL (MPC55XX_FMPLL_MFD-16)
+ #define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
+ #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
+ #define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
+
+ .esyncr2_tmp = {
+ .B = {
+ .LOCEN = 0,
+ .LOLRE = 0,
+ .LOCRE = 0,
+ .LOLIRQ = 0,
+ .LOCIRQ = 0,
+ .ERATE = 0,
+ .EDEPTH = 0,
+ .ERFD = ERFD_VAL + 2 /* reduce output clock during init */
+ }
+ },
+ .esyncr2_final = {
+ .B = {
+ .LOCEN = 0,
+ .LOLRE = 0,
+ .LOCRE = 0,
+ .LOLIRQ = 0,
+ .LOCIRQ = 0,
+ .ERATE = 0,
+ #if MPC55XX_CHIP_TYPE / 10 == 567
+ .CLKCFG_DIS = 1,
+ #endif
+ .EDEPTH = 0,
+ .ERFD = ERFD_VAL /* nominal output clock after init */
+ }
+ },
+ .esyncr1_final = {
+ .B = {
+ .CLKCFG = 7,
+ .EPREDIV = EPREDIV_VAL,
+ .EMFD = EMFD_VAL
+ }
+ }
+ #endif
+ #ifdef MPC55XX_HAS_MODE_CONTROL
+ .fmpll = {
+ {
+ .cr = {
+ .B = { .IDF = 3, .ODF = 1, .NDIV = 48, .I_LOCK = 1, .PLL_ON = 1 }
+ }
+ },
+ {
+ .cr = {
+ .B = { .IDF = 3, .ODF = 2, .NDIV = 32, .I_LOCK = 1, .PLL_ON = 1 }
+ }
+ }
+ },
+ .ocds_sc = {
+ .B = { .SELDIV = 2, .SELCTL = 2 }
+ },
+ .auxclk = {
+ [1] = {
+ .AC_SC = { .B = { .SELCTL = 4 } },
+ .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
+ },
+ [2] = {
+ .AC_SC = { .B = { .SELCTL = 4 } },
+ .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
+ },
+ [3] = {
+ .AC_SC = { .B = { .SELCTL = 1 } }
+ },
+ [4] = {
+ .AC_SC = { .B = { .SELCTL = 1 } }
+ }
+ }
+ #endif
+} };
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cal-cs-config.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs-cal.c
index 4496c69eb9..5095252a38 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cal-cs-config.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs-cal.c
@@ -3,7 +3,7 @@
*
* @ingroup mpc55xx
*
- * @brief MPC55XX EBI calibration chip-select configuration.
+ * @brief EBI calibration chip-select configuration.
*/
/*
@@ -19,16 +19,19 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
- * $Id$
+ * $Id: ebi-cal-cs-config.c,v 1.1 2011/08/31 16:03:09 sh Exp $
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
-const BSP_START_TEXT_SECTION struct EBI_CAL_CS_tag
-mpc55xx_ebi_cal_cs_config [] = {
+#ifdef MPC55XX_HAS_EBI
+
+BSP_START_TEXT_SECTION const struct EBI_CAL_CS_tag
+ mpc55xx_start_config_ebi_cal_cs [] = {
#if defined(MPC55XX_BOARD_MPC5674FEVB)
+ /* External SRAM */
{
.BR = {
.B = {
@@ -50,10 +53,35 @@ mpc55xx_ebi_cal_cs_config [] = {
.BSCY = 0
}
}
+ },
+ /* External Ethernet controller */
+ {
+ .BR = {
+ .B = {
+ .BA = 0x3fff8000 >> 15,
+ .PS = 0,
+ .AD_MUX = 1,
+ .BL = 0,
+ .WEBS = 0,
+ .TBDIP = 0,
+ .SETA = 0,
+ .BI = 1,
+ .V = 1
+ }
+ },
+ .OR = {
+ .B = {
+ .AM = 0xfff80000 >> 15,
+ .SCY = 1,
+ .BSCY = 0
+ }
+ }
}
#endif
};
-const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cal_cs_config_count [] = {
- sizeof(mpc55xx_ebi_cal_cs_config) / sizeof(mpc55xx_ebi_cal_cs_config [0])
+BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_ebi_cal_cs_count [] = {
+ sizeof(mpc55xx_start_config_ebi_cal_cs) / sizeof(mpc55xx_start_config_ebi_cal_cs [0])
};
+
+#endif /* MPC55XX_HAS_EBI */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cs-config.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs.c
index a130f6f802..0f4e6184e4 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cs-config.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs.c
@@ -3,7 +3,7 @@
*
* @ingroup mpc55xx
*
- * @brief MPC55XX EBI chip-select configuration.
+ * @brief EBI chip-select configuration.
*/
/*
@@ -19,15 +19,17 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
- * $Id$
+ * $Id: ebi-cs-config.c,v 1.1 2011/08/31 16:03:09 sh Exp $
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
-const BSP_START_TEXT_SECTION struct EBI_CS_tag
-mpc55xx_ebi_cs_config [] = {
+#ifdef MPC55XX_HAS_EBI
+
+BSP_START_TEXT_SECTION const struct EBI_CS_tag
+ mpc55xx_start_config_ebi_cs [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
/* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
{
@@ -87,7 +89,7 @@ mpc55xx_ebi_cs_config [] = {
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
- .B.BI = 1,
+ .B.BI = 1,
.B.V = 1
},
@@ -137,7 +139,7 @@ mpc55xx_ebi_cs_config [] = {
.B.SCY = 0,
.B.BSCY = 0
}
- },
+ },
{ { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */
{ { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */
{ /* CS3: ethernet? */
@@ -160,6 +162,8 @@ mpc55xx_ebi_cs_config [] = {
#endif
};
-const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cs_config_count [] = {
- sizeof(mpc55xx_ebi_cs_config) / sizeof(mpc55xx_ebi_cs_config [0])
+BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_ebi_cs_count [] = {
+ sizeof(mpc55xx_start_config_ebi_cs) / sizeof(mpc55xx_start_config_ebi_cs [0])
};
+
+#endif /* MPC55XX_HAS_EBI */
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu-early.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu-early.c
new file mode 100644
index 0000000000..d243bee245
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu-early.c
@@ -0,0 +1,42 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief MMU early configuration.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp/start.h>
+#include <bsp/mpc55xx-config.h>
+
+BSP_START_TEXT_SECTION const struct MMU_tag
+ mpc55xx_start_config_mmu_early [] = {
+#if MPC55XX_CHIP_TYPE / 10 == 564
+ /* Internal flash 1M */
+ MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 1),
+ /* IO */
+ MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
+ MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
+ /* Internal SRAM 64k */
+ MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 1, 1, 1, 1)
+#endif
+};
+
+BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_mmu_early_count [] = {
+ sizeof(mpc55xx_start_config_mmu_early)
+ / sizeof(mpc55xx_start_config_mmu_early [0])
+};
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/mmu-config.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c
index f4561f620e..d5df9ffbb4 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/mmu-config.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c
@@ -3,7 +3,7 @@
*
* @ingroup mpc55xx
*
- * @brief MPC55XX MMU configuration.
+ * @brief MMU configuration.
*/
/*
@@ -18,21 +18,19 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
- *
- * $Id$
*/
-#include <bsp/mpc55xx-config.h>
-#include <bsp/start.h>
#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/mpc55xx-config.h>
-const BSP_START_TEXT_SECTION struct MMU_tag
-mpc55xx_mmu_config [] = {
+BSP_START_TEXT_SECTION const struct MMU_tag
+ mpc55xx_start_config_mmu [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
/* External Ethernet Controller 64k */
- MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, 6, 0, 1, 1, 1)
+ MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
- /* XXX I'm not using TLB1 entry 2 the same way as
+ /* XXX I'm not using TLB1 entry 2 the same way as
* in the BAM.
*/
/* Set up MMU TLB1 entry 2 for external ram. */
@@ -87,39 +85,50 @@ mpc55xx_mmu_config [] = {
*/
#elif defined(MPC55XX_BOARD_MPC5566EVB)
/* Internal flash 3M */
- MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 6, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, 6, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, 8, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, 8, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, 8, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, 10, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, 10, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0),
/* External SRAM 512k */
- MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 8, 0, 1, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, 8, 0, 1, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0),
/* Internal SRAM 128k */
- MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, 6, 0, 1, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, 6, 0, 1, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
/* External Ethernet Controller 64k */
- MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, 6, 0, 1, 1, 1)
+ MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
#elif defined(MPC55XX_BOARD_MPC5674FEVB)
/* Internal flash 4M */
- MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 7, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, 8, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, 9, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, 10, 1, 0, 1, 0),
- MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, 11, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
/* External SRAM 512k */
- MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 9, 0, 1, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_512K, 0, 1, 1, 0),
/* Internal SRAM 256k */
- MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, 8, 0, 1, 1, 0)
+ MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
+ /* External Ethernet controller */
+ MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
+#elif MPC55XX_CHIP_TYPE / 10 == 564
+ /* Internal flash 1M */
+ MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 0),
+ /* IO */
+ MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
+ MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
+ /* Internal SRAM 64k + 64k */
+ MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
+ MPC55XX_MMU_TAG_INITIALIZER(4, 0x50000000, MPC55XX_MMU_64K, 0, 1, 1, 0)
#endif
};
-const BSP_START_TEXT_SECTION size_t mpc55xx_mmu_config_count [] = {
- sizeof(mpc55xx_mmu_config) / sizeof(mpc55xx_mmu_config [0])
+BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_mmu_count [] = {
+ sizeof(mpc55xx_start_config_mmu) / sizeof(mpc55xx_start_config_mmu [0])
};
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/siu-pcr-config.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-siu-pcr.c
index ab73ccc9b3..f198eaf2ec 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/siu-pcr-config.c
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-siu-pcr.c
@@ -3,7 +3,7 @@
*
* @ingroup mpc55xx
*
- * @brief MPC55XX SIU PCR configuration.
+ * @brief SIU PCR configuration.
*/
/*
@@ -19,15 +19,15 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
- * $Id$
+ * $Id: siu-pcr-config.c,v 1.1 2011/08/31 16:03:10 sh Exp $
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
-const BSP_START_TEXT_SECTION mpc55xx_siu_pcr_config_entry
-mpc55xx_siu_pcr_config [] = {
+BSP_START_TEXT_SECTION const mpc55xx_siu_pcr_config
+ mpc55xx_start_config_siu_pcr [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
{ 0,16,{.B.PA = 1, .B.WPE = 0}}, /* PA[ 0..15] analog input */
{ 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */
@@ -56,15 +56,15 @@ mpc55xx_siu_pcr_config [] = {
{ 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5 ] LS_CAN_RX in */
{ 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6 ] HS_CAN_TX out */
{ 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7 ] HS_CAN_RX in */
- { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
+ { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
/* PD[ 8 ] I2C_SCL in/out */
- { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
+ { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
/* PD[ 9 ] I2C_SDA in/out */
-
+
{ 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN out*/
- { 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
+ { 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
/* PD[11..13] PWO1_OC, MOCO_INT in */
-
+
{ 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B in */
{ 64, 5,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 0.. 4] LED_EXT1-5. out*/
@@ -99,7 +99,7 @@ mpc55xx_siu_pcr_config [] = {
{ 3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [3] */
{ 4,24,{.B.PA = 1,.B.DSC = 1 }}, /* ADDR [8 : 31] */
{ 28,16,{.B.PA = 1,.B.DSC = 1 }}, /* DATA [0 : 15] */
- { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
+ { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
!WE, !OE, !TS */
{ 89, 2,{.B.PA = 1 }} /* ESCI_B */
#elif defined(MPC55XX_BOARD_MPC5674FEVB)
@@ -110,10 +110,11 @@ mpc55xx_siu_pcr_config [] = {
{ 263, 15, { .B = { .PA = 2, .DSC = 1 } } }, /* D_ADD_DAT16 .. D_ADD_DAT30 */
{ 278, 16, { .B = { .PA = 1, .DSC = 1 } } }, /* D_ADD_DAT0 .. D_ADD_DAT15 */
{ 294, 6, { .B = { .PA = 1, .DSC = 1 } } }, /* D_RD_WR, D_WE0, D_WE1, D_OE, D_TS, D_ALE */
+ { 301, 1, { .B = { .PA = 1, .DSC = 1 } } }, /* D_CS1 */
{ 302, 6, { .B = { .PA = 1, .DSC = 1 } } } /* D_BDIP, D_WE2, D_WE3, D_ADD9 .. D_ADD11 */
#endif
};
-const BSP_START_TEXT_SECTION size_t mpc55xx_siu_pcr_config_count [] = {
- sizeof(mpc55xx_siu_pcr_config) / sizeof(mpc55xx_siu_pcr_config [0])
+BSP_START_TEXT_SECTION const size_t mpc55xx_start_config_siu_pcr_count [] = {
+ sizeof(mpc55xx_start_config_siu_pcr) / sizeof(mpc55xx_start_config_siu_pcr [0])
};
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-early.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-early.c
new file mode 100644
index 0000000000..4d0c35da58
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-early.c
@@ -0,0 +1,175 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Early initialization code.
+ */
+
+/*
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/mpc55xx-config.h>
+
+static BSP_START_TEXT_SECTION void mpc55xx_start_mmu(void)
+{
+ #ifdef MPC55XX_BOOTFLAGS
+ /* If the low bit of bootflag 0 is clear don't change the MMU. */
+ bool do_mmu_config = (mpc55xx_bootflag_0 [0] & 1) != 0;
+ #else
+ bool do_mmu_config = true;
+ #endif
+
+ if (do_mmu_config) {
+ mpc55xx_start_mmu_apply_config(
+ &mpc55xx_start_config_mmu [0],
+ mpc55xx_start_config_mmu_count [0]
+ );
+ }
+}
+
+static BSP_START_TEXT_SECTION void mpc55xx_start_internal_ram(void)
+{
+ /* Initialize internal SRAM to zero (ECC) */
+ bsp_start_zero(
+ (char *) bsp_ram_start + MPC55XX_EARLY_STACK_SIZE,
+ (size_t) bsp_ram_size - MPC55XX_EARLY_STACK_SIZE
+ );
+ #ifdef MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA
+ bsp_start_zero(&bsp_ram_1_start [0], (size_t) bsp_ram_1_size);
+ #endif
+}
+
+static BSP_START_TEXT_SECTION void mpc55xx_start_mode_change(void)
+{
+ #ifdef MPC55XX_HAS_MODE_CONTROL
+ uint32_t mctl_key1 = 0x5af0;
+ uint32_t mctl_key2 = 0xa50f;
+ int i = 0;
+
+ /* Clear any pending RGM status */
+ RGM.FES.R = 0xffff;
+ RGM.DES.R = 0xffff;
+
+ /* Make sure XOSC and PLLs are on in RUN0 state */
+ ME.DRUN_MC.R = 0x001f0074;
+ ME.RUN_MC [0].R = 0x001f0074;
+
+ /*
+ * Make sure all peripherals are active in DRUN and RUN0 state.
+ *
+ * FIXME: This might be optimized to reduce power consumtion.
+ */
+ for (i = 0; i < 8; ++i) {
+ ME_RUN_PC_32B_tag run_pc = { .R = ME.RUN_PC [i].R };
+
+ run_pc.B.DRUN = 1;
+ run_pc.B.RUN0 = 1;
+
+ ME.RUN_PC [i].R = run_pc.R;
+ }
+
+ /* Switch to RUN0 state */
+ ME.MCTL.R = 0x40000000 | mctl_key1;
+ ME.MCTL.R = 0x40000000 | mctl_key2;
+
+ while (ME.GS.B.S_MTRANS) {
+ /* Wait for mode switch to be completed */
+ }
+ #endif
+}
+
+static BSP_START_TEXT_SECTION void mpc55xx_start_siu(void)
+{
+ size_t i = 0;
+
+ #ifdef MPC55XX_BOARD_GWLCFM
+ SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */
+ SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */
+ SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */
+ #endif
+
+ for (i = 0; i < mpc55xx_start_config_siu_pcr_count [0]; ++i) {
+ const mpc55xx_siu_pcr_config *e = &mpc55xx_start_config_siu_pcr [i];
+ int j = e->index;
+ int n = j + e->count;
+ uint16_t pcr = e->pcr.R;
+
+ while (j < n) {
+ SIU.PCR [j].R = pcr;
+ ++j;
+ }
+ }
+}
+
+static BSP_START_TEXT_SECTION void mpc55xx_start_ebi_chip_select(void)
+{
+ #ifdef MPC55XX_HAS_EBI
+ size_t i = 0;
+
+ for (i = 0; i < mpc55xx_start_config_ebi_cs_count [0]; ++i) {
+ EBI.CS [i] = mpc55xx_start_config_ebi_cs [i];
+ }
+
+ for (i = 0; i < mpc55xx_start_config_ebi_cal_cs_count [0]; ++i) {
+ EBI.CAL_CS [i] = mpc55xx_start_config_ebi_cal_cs [i];
+ }
+ #endif
+}
+
+static BSP_START_TEXT_SECTION void mpc55xx_start_ebi(void)
+{
+ #if defined(MPC55XX_BOARD_GWLCFM)
+ /*
+ * init EBI for Muxed AD bus
+ */
+ EBI.MCR.B.DBM = 1;
+ EBI.MCR.B.AD_MUX = 1; /* use multiplexed bus */
+ EBI.MCR.B.D16_31 = 1; /* use lower AD bus */
+
+ SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */
+ #elif defined(MPC55XX_BOARD_MPC5674FEVB)
+ struct EBI_tag ebi = {
+ .MCR = {
+ .B = {
+ .ACGE = 0,
+ .MDIS = 0,
+ .D16_31 = 0,
+ .AD_MUX = 0,
+ .DBM = 0
+ }
+ }
+ };
+
+ EBI.MCR.R = ebi.MCR.R;
+ #endif
+}
+
+BSP_START_TEXT_SECTION void mpc55xx_start_early(void)
+{
+ mpc55xx_start_watchdog();
+ mpc55xx_start_clock();
+ mpc55xx_start_flash();
+ #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
+ mpc55xx_start_cache();
+ #endif
+ mpc55xx_start_mmu();
+ mpc55xx_start_internal_ram();
+ mpc55xx_start_mode_change();
+ mpc55xx_start_siu();
+ mpc55xx_start_ebi_chip_select();
+ mpc55xx_start_ebi();
+}
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-flash.S
index c1e75c88b2..a6ed92eda7 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/misc/flash.S
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-flash.S
@@ -19,13 +19,13 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
- * $Id$
+ * $Id: flash.S,v 1.2 2011/08/31 15:50:30 sh Exp $
*/
#include <libcpu/powerpc-utility.h>
#include <mpc55xx/reg-defs.h>
-.section ".bsp_start_text", "ax"
+ .section ".bsp_start_text", "ax"
/* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */
.equ FLASH_SETTINGS_RESET, 0xff00
@@ -35,78 +35,81 @@
.equ FLASH_SETTINGS_264, 0x01716B15
/**
- * @fn void mpc55xx_flash_init()
+ * @fn void mpc55xx_start_flash()
* @brief Optimized flash configuration.
- * @warning Code will be copied and executed on the stack. The stack pointer
- * will not be updated, since this function has to work before memory
- * initialization.
+ * @warning Code will be copied and executed on the stack.
*/
-GLOBAL_FUNCTION mpc55xx_flash_init
- mflr r31
+GLOBAL_FUNCTION mpc55xx_start_flash
+#if MPC55XX_CHIP_TYPE / 10 == 564
+ blr
+#else
+ .equ stack_size, 20
+ .equ lr_offset, 28
+
+ /* Reserve stack frame */
+ stwu r1, -stack_size(r1)
+ mflr r0
+ stw r0, lr_offset(r1)
/* Flash settings dependent on system clock */
- bl mpc55xx_get_system_clock
- LWI r4, 82000000
- cmpw r3, r4
- ble clock_82
- LWI r4, 102000000
- cmpw r3, r4
- ble clock_102
- LWI r4, 132000000
- cmpw r3, r4
- ble clock_132
- LWI r4, 264000000
- cmpw r3, r4
- ble clock_264
- LWI r30, FLASH_SETTINGS_RESET
- b settings_done
+ bl mpc55xx_get_system_clock
+ LWI r4, 82000000
+ cmpw r3, r4
+ ble clock_82
+ LWI r4, 102000000
+ cmpw r3, r4
+ ble clock_102
+ LWI r4, 132000000
+ cmpw r3, r4
+ ble clock_132
+ LWI r4, 264000000
+ cmpw r3, r4
+ ble clock_264
+ LWI r3, FLASH_SETTINGS_RESET
+ b settings_done
clock_82:
- LWI r30, FLASH_SETTINGS_82
- b settings_done
+ LWI r3, FLASH_SETTINGS_82
+ b settings_done
clock_102:
- LWI r30, FLASH_SETTINGS_102
- b settings_done
+ LWI r3, FLASH_SETTINGS_102
+ b settings_done
clock_132:
- LWI r30, FLASH_SETTINGS_132
+ LWI r3, FLASH_SETTINGS_132
b settings_done
clock_264:
- LWI r30, FLASH_SETTINGS_264
- b settings_done
+ LWI r3, FLASH_SETTINGS_264
+ b settings_done
settings_done:
/* Copy store code on the stack */
- LA r3, store_start
- LA r5, store_end
- subf r5, r3, r5
- subf r4, r5, r1
-
- /* Assert: Proper alignment of destination start */
- andi. r6, r4, 0x7
- bne twiddle
-
- /* Copy */
- bl mpc55xx_copy_8
-
- LA r6, FLASH_BIUCR
+ LA r4, store_start
+ lwz r6, 0(r4)
+ lwz r7, 4(r4)
+ lwz r8, 8(r4)
+ stw r6, 8(r1)
+ stw r7, 12(r1)
+ stw r8, 16(r1)
/* Execute store code */
- mtctr r4
+ LA r4, FLASH_BIUCR
+ addi r5, r1, 8
+ mtctr r5
bctrl
- mtlr r31
+ /* Return */
+ lwz r0, lr_offset(r1)
+ addi r1, r1, stack_size
+ mtlr r0
blr
/*
* Store flash settings
*/
- .align 3
- .set store_start, .
- stw r30, 0(r6)
+store_start:
+
+ stw r3, 0(r4)
isync
blr
- .align 3
- .set store_end, .
-twiddle:
- b twiddle
+#endif
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-watchdog.c b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-watchdog.c
new file mode 100644
index 0000000000..209405df0c
--- /dev/null
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-watchdog.c
@@ -0,0 +1,37 @@
+/**
+ * @file
+ *
+ * @ingroup mpc55xx
+ *
+ * @brief Watchdog initialization code.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/mpc55xx-config.h>
+
+BSP_START_TEXT_SECTION void mpc55xx_start_watchdog(void)
+{
+ #ifdef MPC55XX_HAS_SWT
+ /* Write keys to clear soft lock bit */
+ SWT.SR.R = 0x0000c520;
+ SWT.SR.R = 0x0000d928;
+
+ /* Clear watchdog enable (WEN) */
+ SWT.CR.R = 0x8000010A;
+ #endif
+}
diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
index ee18d41a5f..f05e2c7f1c 100644
--- a/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
+++ b/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
@@ -18,134 +18,226 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
- *
- * $Id$
- */
-
-/**
- * @defgroup mpc55xx_asm Assembler files
- *
- * @ingroup mpc55xx
*/
#include <bspopts.h>
#include <libcpu/powerpc-utility.h>
-#include <mpc55xx/reg-defs.h>
+#if MPC55XX_CHIP_TYPE / 10 != 551
+ #define HAS_SPE
+#endif
-#include <bsp/vectors.h>
+#if MPC55XX_CHIP_TYPE / 10 == 564
+ #define INIT_REGISTERS_FOR_LSM
+#endif
-#define HAS_CACHE (BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED)
+#ifdef HAS_SPE
+ #define ZERO_GPR(reg) evxor reg, reg, reg
+#else
+ #define ZERO_GPR(reg) xor reg, reg, reg
+#endif
- .extern mpc55xx_fmpll_config
- .extern mpc55xx_fmpll_init
- .extern mpc55xx_flash_init
- .extern mpc55xx_early_init
- .extern bsp_start_zero
- .extern bsp_ram_start
- .extern bsp_ram_size
- .extern bsp_ram_end
- .extern __eabi
- .extern boot_card
+ .extern __eabi
+ .extern boot_card
+ .extern bsp_ram_start
+ .extern bsp_section_data_begin
+ .extern bsp_section_data_load_begin
+ .extern bsp_section_data_size
+ .extern bsp_section_fast_data_begin
+ .extern bsp_section_fast_data_load_begin
+ .extern bsp_section_fast_data_size
+ .extern bsp_section_fast_text_begin
+ .extern bsp_section_fast_text_load_begin
+ .extern bsp_section_fast_text_size
+ .extern mpc55xx_start_config_mmu_early
+ .extern mpc55xx_start_config_mmu_early_count
+ .extern mpc55xx_start_early
+
+ .globl _start
+ .globl mpc55xx_start_mmu_apply_config
- .globl _start
-
#ifdef MPC55XX_BOOTFLAGS
- .globl mpc55xx_bootflag_0
- .globl mpc55xx_bootflag_1
+ .globl mpc55xx_bootflag_0
+ .globl mpc55xx_bootflag_1
#endif
- .section ".bsp_start_text", "ax"
+ .section ".bsp_start_text", "ax"
/* BAM: RCHW */
- .int 0x005a0000
+ .int 0x005a0000
/* BAM: Address of start instruction */
- .int _start
+ .int _start
#ifdef MPC55XX_BOOTFLAGS
- /*
- * We skip over the next two boot flag words to the next 64-bit
- * aligned start address. It is 64-bit aligned to play well with
- * FLASH programming. These boot flags can be set by debuggers
- * and emulators to customize boot. Currently bit0 of
- * bootflag_0 means to "skip setting up the MMU", allowing
- * external MMU setup in a debugger before branching to 0x10.
- * This can be used e.g., to map FLASH into RAM.
- */
+ /*
+ * We skip over the next two boot flag words to the next 64-bit
+ * aligned start address. It is 64-bit aligned to play well with
+ * FLASH programming. These boot flags can be set by debuggers
+ * and emulators to customize boot. Currently bit0 of
+ * bootflag_0 means to "skip setting up the MMU", allowing
+ * external MMU setup in a debugger before branching to 0x10.
+ * This can be used e.g., to map FLASH into RAM.
+ */
mpc55xx_bootflag_0:
- .int 0xffffffff
+ .int 0xffffffff
mpc55xx_bootflag_1:
- .int 0xffffffff
+ .int 0xffffffff
#endif
_start:
- /* Enable time base */
- li r0, 0
- mtspr TBWU, r0
+ /* Enable SPE */
+#ifdef HAS_SPE
+ mfmsr r3
+ oris r3, r3, MSR_SPE >> 16
+ mtmsr r3
+ isync
+#endif
+
+ /*
+ * Initialization of core registers according to "e200z4 Power
+ * Architecture Core Reference Manual" section 2.6 "Reset Settings"
+ * table 2-16 "Reset Settings of e200 Resources". This is necessary
+ * for lock step mode (LSM).
+ */
+ ZERO_GPR(r0)
+#ifdef INIT_REGISTERS_FOR_LSM
+ ZERO_GPR(r1)
+ ZERO_GPR(r2)
+ ZERO_GPR(r4)
+ ZERO_GPR(r5)
+ ZERO_GPR(r6)
+ ZERO_GPR(r7)
+ ZERO_GPR(r8)
+ ZERO_GPR(r9)
+ ZERO_GPR(r10)
+ ZERO_GPR(r11)
+ ZERO_GPR(r12)
+ ZERO_GPR(r13)
+ ZERO_GPR(r14)
+ ZERO_GPR(r15)
+ ZERO_GPR(r16)
+ ZERO_GPR(r17)
+ ZERO_GPR(r18)
+ ZERO_GPR(r19)
+ ZERO_GPR(r20)
+ ZERO_GPR(r21)
+ ZERO_GPR(r22)
+ ZERO_GPR(r23)
+ ZERO_GPR(r24)
+ ZERO_GPR(r25)
+ ZERO_GPR(r26)
+ ZERO_GPR(r27)
+ ZERO_GPR(r28)
+ ZERO_GPR(r29)
+ ZERO_GPR(r30)
+ ZERO_GPR(r31)
+ mtcrf 0xff, r0
+ mtcsrr0 r0
+ mtcsrr1 r0
+ mtctr r0
+ mtspr FSL_EIS_DBCNT, r0
+ mtspr DEAR_BOOKE, r0
+ mtdec r0
+ mtspr BOOKE_DECAR, r0
+ mtspr FSL_EIS_DSRR0, r0
+ mtspr FSL_EIS_DSRR1, r0
+ mtspr BOOKE_DVC1, r0
+ mtspr BOOKE_DVC2, r0
+ mtspr BOOKE_IVPR, r0
+ mtlr r0
+ mtspr FSL_EIS_MCAR, r0
+ mtmcsrr0 r0
+ mtmcsrr1 r0
+ mtspr SPRG0, r0
+ mtspr SPRG1, r0
+ mtspr SPRG2, r0
+ mtspr SPRG3, r0
+ mtspr SPRG4, r0
+ mtspr SPRG5, r0
+ mtspr SPRG6, r0
+ mtspr SPRG7, r0
+ mtspr FSL_EIS_SPRG8, r0
+ mtspr FSL_EIS_SPRG9, r0
+ mtsrr0 r0
+ mtsrr1 r0
+ mtspr USPRG0, r0
+#ifdef HAS_SPE
+ evmra r0, r0
+#endif
+#endif /* INIT_REGISTERS_FOR_LSM */
mtspr TBWL, r0
- mfspr r2, HID0
- ori r2, r2, 0x4000
- mtspr HID0, r2
+ mtspr TBWU, r0
- /* FMPLL setup */
- LWI r3, mpc55xx_fmpll_config
- bl mpc55xx_fmpll_init
+ /* Enable time base */
+ mfspr r3, HID0
+ ori r3, r3, 0x4000
+ mtspr HID0, r3
/* Enable branch prediction */
- LWI r2, BUCSR_BBFI | BUCSR_BPEN
- mtspr BUCSR, r2
+ LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BPEN
+ mtspr FSL_EIS_BUCSR, r3
- /* Set intermediate stack start to end of internal SRAM */
- LA r1, bsp_ram_end
- subi r1, r1, 16
+ /* MMU early initialization */
+ LA r3, mpc55xx_start_config_mmu_early
+ LW r4, mpc55xx_start_config_mmu_early_count
+ bl mpc55xx_start_mmu_apply_config
- /* Enable SPE */
- mfmsr r2
- oris r2, r2, 0x200
- mtmsr r2
-
- /* Config internal flash */
- bl mpc55xx_flash_init
-
-#if HAS_CACHE
- bl config_cache
-
- /* Enable cache in the MMU for the internal SRAM */
- LWI r3, 0x10030000
- mtspr FSL_EIS_MAS0, r3
- tlbre
- LWI r4, ~0x00000008
- mfspr r3, FSL_EIS_MAS2
- and r3, r3, r4
- mtspr FSL_EIS_MAS2, r3
- tlbwe
-#endif
+ /* Initialize intermediate stack (ECC) */
- /* Zero internal SRAM (needed to get proper ECC) */
LA r3, bsp_ram_start
- LA r4, bsp_ram_size
- bl bsp_start_zero
+ addi r4, r3, MPC55XX_EARLY_STACK_SIZE
- /* Initialize intermediate start stack */
- li r0, 0
- stw r0, 0(r1)
- stw r0, 4(r1)
+zero_intermediate_stack_loop:
- /* Do early initialization */
- bl mpc55xx_early_init
+#ifdef HAS_SPE
+ evstdd r0, 0(r3)
+ evstdd r0, 8(r3)
+ evstdd r0, 16(r3)
+ evstdd r0, 24(r3)
+#else
+ stw r0, 0(r3)
+ stw r0, 4(r3)
+ stw r0, 8(r3)
+ stw r0, 12(r3)
+ stw r0, 16(r3)
+ stw r0, 20(r3)
+ stw r0, 24(r3)
+ stw r0, 28(r3)
+#endif
+ addi r3, r3, 32
+ cmpw cr7, r3, r4
+ bne cr7, zero_intermediate_stack_loop
+ subi r1, r3, 16
- /* Set up EABI and SYSV environment */
- bl __eabi
+ /* Next steps in C */
+ bl mpc55xx_start_early
/* Initialize start stack */
- LWI r1, start_stack_end
+ LA r1, start_stack_end
subi r1, r1, 16
li r0, 0
stw r0, 0(r1)
+ /* Load sections */
+ LA r3, bsp_section_fast_text_begin
+ LA r4, bsp_section_fast_text_load_begin
+ LA r5, bsp_section_fast_text_size
+ bl load_section
+ LA r3, bsp_section_fast_data_begin
+ LA r4, bsp_section_fast_data_load_begin
+ LA r5, bsp_section_fast_data_size
+ bl load_section
+ LA r3, bsp_section_data_begin
+ LA r4, bsp_section_data_load_begin
+ LA r5, bsp_section_data_size
+ bl load_section
+
+ /* Set up EABI and SYSV environment */
+ bl __eabi
+
/* Clear command line */
li r3, 0
@@ -154,83 +246,39 @@ _start:
/* Spin around */
twiddle:
- b twiddle
-
-#if HAS_CACHE
-config_cache:
-
- /* Load zero, CINV, and CABT) */
- li r0, 0
- li r3, 0x2
- li r4, 0x4
-
-#if MPC55XX_CHIP_TYPE / 10 == 567
-start_instruction_cache_invalidation:
-
- /* Clear instruction cache invalidation abort */
- mtspr FSL_EIS_L1CSR1, r0
-
- /* Start instruction cache invalidation */
- mtspr FSL_EIS_L1CSR1, r3
-
-get_instruction_cache_invalidation_status:
-
- /* Get instruction cache invalidation status */
- mfspr r5, FSL_EIS_L1CSR1
- /* Check CABT */
- and. r6, r5, r4
- bne start_instruction_cache_invalidation
-
- /* Check CINV */
- and. r6, r5, r3
- bne get_instruction_cache_invalidation_status
-
- /* Save instruction cache settings */
- LWI r6, 0x00010001
- isync
- msync
- mtspr FSL_EIS_L1CSR1, r6
-#endif /* MPC55XX_CHIP_TYPE / 10 == 567 */
-
-start_data_cache_invalidation:
-
- /* Clear data cache invalidation abort */
- mtspr FSL_EIS_L1CSR0, r0
+ b twiddle
- /* Start data cache invalidation */
- mtspr FSL_EIS_L1CSR0, r3
+mpc55xx_start_mmu_apply_config:
-get_data_cache_invalidation_status:
+ cmpwi cr7, r4, r0
+ beqlr cr7
+ mtctr r4
- /* Get data cache invalidation status */
- mfspr r5, FSL_EIS_L1CSR0
+mmu_init_loop:
- /* Check CABT */
- and. r6, r5, r4
- bne start_data_cache_invalidation
+ lwz r4, 0(r3)
+ lwz r5, 4(r3)
+ lwz r6, 8(r3)
+ lwz r7, 12(r3)
+ mtspr FSL_EIS_MAS0, r4
+ mtspr FSL_EIS_MAS1, r5
+ mtspr FSL_EIS_MAS2, r6
+ mtspr FSL_EIS_MAS3, r7
+ tlbwe
+ addi r3, r3, 16
+ bdnz mmu_init_loop
+ blr
- /* Check CINV */
- and. r6, r5, r3
- bne get_data_cache_invalidation_status
+load_section:
+ cmpw cr7, r3, r4
+ beqlr cr7
+ b memcpy
- /* Save data cache settings */
-#if MPC55XX_CHIP_TYPE / 10 != 567
- /* FIXME: CORG??? 0x00180011 */
- LWI r6, 0x00100001
-#else
- LWI r6, 0x00190001
-#endif
- isync
- msync
- mtspr FSL_EIS_L1CSR0, r6
+ /* Start stack area */
- /* Return */
- blr
-#endif /* HAS_CACHE */
+ .section ".bsp_rwextra", "aw", @nobits
+ .align 4
+ .space 4096
- /* Start stack area */
- .section ".bsp_rwextra", "aw", @nobits
- .align 4
- .space 4096
start_stack_end:
diff --git a/c/src/lib/libcpu/powerpc/Makefile.am b/c/src/lib/libcpu/powerpc/Makefile.am
index 579957b542..67eb8790d2 100644
--- a/c/src/lib/libcpu/powerpc/Makefile.am
+++ b/c/src/lib/libcpu/powerpc/Makefile.am
@@ -418,13 +418,13 @@ include_mpc55xx_HEADERS += mpc55xx/include/dspi.h
include_mpc55xx_HEADERS += mpc55xx/include/edma.h
include_mpc55xx_HEADERS += mpc55xx/include/emios.h
include_mpc55xx_HEADERS += mpc55xx/include/mpc55xx.h
-include_mpc55xx_HEADERS += mpc55xx/include/esci.h
include_mpc55xx_HEADERS += mpc55xx/include/siu.h
include_mpc55xx_HEADERS += mpc55xx/include/irq.h
include_mpc55xx_HEADERS += mpc55xx/include/watchdog.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc551x.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc555x.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc556x.h
+include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc564xL.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc567x.h
include_mpc55xx_HEADERS += mpc55xx/include/regs-edma.h
include_mpc55xx_HEADERS += mpc55xx/include/regs-mmu.h
@@ -462,11 +462,6 @@ noinst_PROGRAMS += mpc55xx/siu.rel
mpc55xx_siu_rel_SOURCES = mpc55xx/siu/siu.c
mpc55xx_siu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-# eSCI
-noinst_PROGRAMS += mpc55xx/esci.rel
-mpc55xx_esci_rel_SOURCES = mpc55xx/esci/esci.c
-mpc55xx_esci_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-
# DSPI
noinst_PROGRAMS += mpc55xx/dspi.rel
mpc55xx_dspi_rel_SOURCES = mpc55xx/dspi/dspi.c
@@ -475,8 +470,6 @@ mpc55xx_dspi_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
# Misc
noinst_PROGRAMS += mpc55xx/misc.rel
mpc55xx_misc_rel_SOURCES = mpc55xx/misc/copy.S \
- mpc55xx/misc/fmpll.S \
- mpc55xx/misc/flash.S \
mpc55xx/misc/flash_support.c
mpc55xx_misc_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c b/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c
index a9498c435e..3a0710dcec 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c
@@ -747,6 +747,7 @@ mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = {
},
.idle_char = 0xffffffff,
.baud = 0
+#ifdef DSPI_D
}, {
/* DSPI D */
.bus = {
@@ -775,5 +776,6 @@ mpc55xx_dspi_bus_entry mpc55xx_dspi_bus_table [MPC55XX_DSPI_NUMBER] = {
},
.idle_char = 0xffffffff,
.baud = 0
+#endif
}
};
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c b/c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c
index 3d276af5f0..cedcb60501 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c
@@ -7,15 +7,17 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems@embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
*/
#include <mpc55xx/regs.h>
@@ -29,6 +31,8 @@
#if MPC55XX_CHIP_TYPE / 10 == 551
#define EDMA_CHANNEL_COUNT 16U
+#elif MPC55XX_CHIP_TYPE / 10 == 564
+ #define EDMA_CHANNEL_COUNT 16U
#elif MPC55XX_CHIP_TYPE / 10 == 567
#define EDMA_CHANNEL_COUNT 96U
#else
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/emios/emios.c b/c/src/lib/libcpu/powerpc/mpc55xx/emios/emios.c
index 90cbcd3664..0f2529e6a4 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/emios/emios.c
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/emios/emios.c
@@ -7,28 +7,22 @@
*/
/*
- * Copyright (c) 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
+ * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
-#include <mpc55xx/regs.h>
#include <mpc55xx/emios.h>
-#include <mpc55xx/mpc55xx.h>
-
-#include <bsp/irq.h>
-#include <bsp/utility.h>
-#define RTEMS_STATUS_CHECKS_USE_PRINTK
-
-#include <rtems/status-checks.h>
+#ifdef MPC55XX_HAS_EMIOS
/**
* @brief Initialize the eMIOS module.
@@ -107,3 +101,5 @@ void mpc55xx_emios_set_global_prescaler( unsigned prescaler)
/* Set MCR */
EMIOS.MCR.R = mcr.R;
}
+
+#endif /* MPC55XX_HAS_EMIOS */
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h
index f6e763c082..0723abb02d 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/emios.h
@@ -7,12 +7,13 @@
*/
/*
- * Copyright (c) 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
+ * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -22,18 +23,14 @@
#ifndef LIBCPU_POWERPC_MPC55XX_EMIOS_H
#define LIBCPU_POWERPC_MPC55XX_EMIOS_H
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <rtems.h>
-#include <rtems/chain.h>
-
-#include <bspopts.h>
+#include <mpc55xx/regs.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
+#ifdef MPC55XX_HAS_EMIOS
+
/**
* @name eMIOS - Modes
*
@@ -191,6 +188,8 @@ unsigned mpc55xx_emios_global_prescaler( void);
void mpc55xx_emios_set_global_prescaler( unsigned prescaler);
+#endif /* MPC55XX_HAS_EMIOS */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h
index 86d4d0c621..48389d85eb 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h
@@ -52,6 +52,8 @@
#ifndef _MPC5510_H_
#define _MPC5510_H_
+#ifndef ASM
+
#include <stdint.h>
#include <mpc55xx/regs-edma.h>
@@ -3969,6 +3971,7 @@ extern "C" {
#ifdef __cplusplus
}
#endif
+#endif /* ASM */
#endif /* ifdef _MPC5510_H */
/*********************************************************************
*
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h
index 6a6a4a8ef5..23066bdecc 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h
@@ -103,6 +103,8 @@
#ifndef _MPC5554_H_
#define _MPC5554_H_
+#ifndef ASM
+
#include <stdint.h>
#include <mpc55xx/regs-edma.h>
@@ -3347,6 +3349,7 @@ union EQADC_WRITE_CONFIGURATION_COMMAND_tag {
#ifdef __cplusplus
}
#endif
+#endif /* ASM */
#endif /* ifdef _MPC5554_H */
/*********************************************************************
*
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h
index 7cdb885b73..70d2536388 100644
--- a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h
@@ -70,6 +70,8 @@
#ifndef _MPC5567_H_
#define _MPC5567_H_
+#ifndef ASM
+
#include <stdint.h>
#include <mpc55xx/regs-edma.h>
@@ -4527,6 +4529,7 @@ extern "C" {
#ifdef __cplusplus
}
#endif
+#endif /* ASM */
#endif /* ifdef _MPC5567_H */
/*********************************************************************
*
diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h
new file mode 100644
index 0000000000..3a363ecaf8
--- /dev/null
+++ b/c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc564xL.h
@@ -0,0 +1,20666 @@
+/*
+ * Modifications of the original file provided by Freescale Semiconductor and
+ * ST Microelectronics are:
+ *
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <info@embedded-brains.de>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/****************************************************************************\
+ * PROJECT : MPC5643L
+ * FILE : mpc5643l.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for the named projects.
+ *
+ * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics
+ *
+ * VERSION : 1.04
+ * RELEASE DATE : Tue Dec 1 2009
+ * CREATION DATE : Thu Oct 8 13:53:51 CEST 2009
+ * AUTHOR : generated from IP-XACT database
+ * HISTORY : Preliminary release.
+\****************************************************************************/
+
+/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */
+
+/****************************************************************************\
+ * Example instantiation and use:
+ *
+ * <MODULE>.<REGISTER>.B.<BIT> = 1;
+ * <MODULE>.<REGISTER>.R = 0x10000000;
+ *
+\****************************************************************************/
+
+/*
+ * LICENSE:
+ * Copyright (c) 2006 Freescale Semiconductor
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice
+ * shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _leopard_H_ /* prevents multiple inclusions of this file */
+#define _leopard_H_
+
+#ifndef ASM
+
+#include <stdint.h>
+
+#include <mpc55xx/regs-edma.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+
+//#define USE_FIELD_ALIASES_CFLASH
+//#define USE_FIELD_ALIASES_SIUL
+//#define USE_FIELD_ALIASES_SSCM
+//#define USE_FIELD_ALIASES_ME
+//#define USE_FIELD_ALIASES_RGM
+//#define USE_FIELD_ALIASES_ADC
+//#define USE_FIELD_ALIASES_CTU
+//#define USE_FIELD_ALIASES_mcTIMER
+//#define USE_FIELD_ALIASES_mcPWM
+//#define USE_FIELD_ALIASES_LINFLEX
+//#define USE_FIELD_ALIASES_SPP_MCM
+#define USE_FIELD_ALIASES_INTC
+#define USE_FIELD_ALIASES_DSPI
+//#define USE_FIELD_ALIASES_FLEXCAN
+//#define USE_FIELD_ALIASES_FR
+//#define USE_FIELD_ALIASES_CMU
+//#define USE_FIELD_ALIASES_PLLD
+//#define USE_FIELD_ALIASES_SPP_DMA2
+
+/* Define memories */
+
+#define SRAM_START 0x40000000
+#define SRAM_SIZE 0x20000
+#define SRAM_END 0x4001FFFF
+
+#define FLASH_START 0x0
+#define FLASH_SIZE 0xC0000
+#define FLASH_END 0xBFFFF
+
+/****************************************************************/
+/* */
+/* Global definitions and aliases */
+/* */
+/****************************************************************/
+
+/*
+ Platform blocks that are only accessible by the second core (core 1) when
+ the device is in DPM mode. The block definition is equivalent to the one
+ for the first core (core 0) and reuses the related block structure.
+
+ NOTE: the <block_name>_1 defines are the preferred method for programming
+ */
+#define PBRIDGE_1 (*(volatile PBRIDGE_tag*) 0x8FF00000UL)
+#define MAX_1 (*(volatile MAX_tag*) 0x8FF04000UL)
+#define MPU_1 (*(volatile MPU_tag*) 0x8FF10000UL)
+#define SEMA4_1 (*(volatile SEMA4_tag*) 0x8FF24000UL)
+#define SWT_1 (*(volatile SWT_tag*) 0x8FF38000UL)
+#define STM_1 (*(volatile STM_tag*) 0x8FF3C000UL)
+#define SPP_MCM_1 (*(volatile SPP_MCM_tag*) 0x8FF40000UL)
+#define SPP_DMA2_1 (*(volatile SPP_DMA2_tag*) 0x8FF44000UL)
+#define INTC_1 (*(volatile INTC_tag*) 0x8FF48000UL)
+
+/*
+ Platform blocks that are only accessible by the second core (core 1) when
+ the device is in DPM mode. The block definition is equivalent to the one
+ for the first core (core 0) and reuses the related block structure.
+
+ NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for
+ programming the corresponding blocks for new code instead.
+ */
+#define PBRIDGE_DPM PBRIDGE_1
+#define MAX_DPM MAX_1
+#define MPU_DPM MPU_1
+#define SEMA4_DPM SEMA4_1
+#define SWT_DPM SWT_1
+#define STM_DPM STM_1
+#define SPP_MCM_DPM SPP_MCM_1
+#define SPP_DMA2_DPM SPP_DMA2_1
+#define INTC_DPM INTC_1
+
+/* Aliases for Pictus Module names */
+#define CAN_0 FLEXCAN_A
+#define CAN_1 FLEXCAN_B
+#define CTU_0 CTU
+#define DFLASH CRC
+#define DMAMUX DMA_CH_MUX
+#define DSPI_0 DSPI_A
+#define DSPI_1 DSPI_B
+#define DSPI_2 DSPI_C
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
+#define ETIMER_0 mcTIMER0
+#define ETIMER_1 mcTIMER1
+#define FLEXPWM_0 mcPWM_A
+#define FLEXPWM_1 mcPWM_B
+#define LINFLEX_0 LINFLEX0
+#define LINFLEX_1 LINFLEX1
+#define MCM_ SPP_MCM
+#define PIT PIT_RTI
+#define SIU SIUL
+#define WKUP WKPU
+#define ADC_0 ADC0
+#define ADC_1 ADC1
+
+/* Other Aliases */
+#define AIPS_DPM PBRIDGE_1
+#define AIPS_1 PBRIDGE_1
+#define AIPS PBRIDGE
+
+/****************************************************************/
+/* */
+/* Module: CFLASH_SHADOW */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers NVPWD... */
+
+ typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
+ uint32_t R;
+ struct {
+ uint32_t PWD:32; /* PassWorD */
+ } B;
+ } CFLASH_SHADOW_NVPWD_32B_tag;
+
+
+ /* Register layout for all registers NVSCI... */
+
+ typedef union { /* NVSCI - Non Volatile System Censoring Information Register */
+ uint32_t R;
+ struct {
+ uint32_t SC:16; /* Serial Censorship Control Word */
+ uint32_t CW:16; /* Censorship Control Word */
+ } B;
+ } CFLASH_SHADOW_NVSCI_32B_tag;
+
+ typedef union { /* Non Volatile LML Default Value */
+ uint32_t R;
+ } CFLASH_SHADOW_NVLML_32B_tag;
+
+ typedef union { /* Non Volatile HBL Default Value */
+ uint32_t R;
+ } CFLASH_SHADOW_NVHBL_32B_tag;
+
+ typedef union { /* Non Volatile SLL Default Value */
+ uint32_t R;
+ } CFLASH_SHADOW_NVSLL_32B_tag;
+
+
+ /* Register layout for all registers NVBIU... */
+
+ typedef union { /* Non Volatile Bus Interface Unit Register */
+ uint32_t R;
+ struct {
+ uint32_t BI:32; /* Bus interface Unit */
+ } B;
+ } CFLASH_SHADOW_NVBIU_32B_tag;
+
+ typedef union { /* NVUSRO - Non Volatile USeR Options Register */
+ uint32_t R;
+ struct {
+ uint32_t UO:32; /* User Options */
+ } B;
+ } CFLASH_SHADOW_NVUSRO_32B_tag;
+
+
+ typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag {
+
+ /* Non Volatile Bus Interface Unit Register */
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */
+ int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4];
+
+ } CFLASH_SHADOW_BIU_DEFAULTS_tag;
+
+
+ typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */
+ int8_t CFLASH_SHADOW_reserved_0000_C[15832];
+ union {
+ /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
+ CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */
+
+ struct {
+ /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
+ CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */
+ CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */
+ };
+
+ };
+ union {
+ /* NVSCI - Non Volatile System Censoring Information Register */
+ CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */
+
+ struct {
+ /* NVSCI - Non Volatile System Censoring Information Register */
+ CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */
+ CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */
+ };
+
+ };
+ /* Non Volatile LML Default Value */
+ CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3DEC[4];
+ /* Non Volatile HBL Default Value */
+ CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3DF4[4];
+ /* Non Volatile SLL Default Value */
+ CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3DFC_C[4];
+ union {
+ /* Register set BIU_DEFAULTS */
+ CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */
+
+ struct {
+ /* Non Volatile Bus Interface Unit Register */
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3E04_I1[4];
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3E0C_I1[4];
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3E14_E1[4];
+ };
+
+ };
+ /* NVUSRO - Non Volatile USeR Options Register */
+ CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */
+ } CFLASH_SHADOW_tag;
+
+
+#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CFLASH */
+/* */
+/****************************************************************/
+
+ typedef union { /* MCR - Module Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:5;
+ uint32_t SIZE:3; /* Array Space Size */
+ uint32_t:1;
+ uint32_t LAS:3; /* Low Address Space */
+ uint32_t:3;
+ uint32_t MAS:1; /* Mid Address Space Configuration */
+ uint32_t EER:1; /* ECC Event Error */
+ uint32_t RWE:1; /* Read-while-Write Event Error */
+ uint32_t SBC:1; /* Single Bit Correction */
+ uint32_t:1;
+ uint32_t PEAS:1; /* Program/Erase Access Space */
+ uint32_t DONE:1; /* modify operation DONE */
+ uint32_t PEG:1; /* Program/Erase Good */
+ uint32_t:4;
+ uint32_t PGM:1; /* Program Bit */
+ uint32_t PSUS:1; /* Program Suspend */
+ uint32_t ERS:1; /* Erase Bit */
+ uint32_t ESUS:1; /* Erase Suspend */
+ uint32_t EHV:1; /* Enable High Voltage */
+ } B;
+ } CFLASH_MCR_32B_tag;
+
+ typedef union { /* LML - Low/Mid Address Space Block Locking Register */
+ uint32_t R;
+ struct {
+ uint32_t LME:1; /* Low/Mid Address Space Block Enable */
+ uint32_t:10;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t SLOCK:1; /* Shadow Address Space Block Lock */
+#else
+ uint32_t TSLK:1; /* deprecated name - please avoid */
+#endif
+ uint32_t:2;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t MLOCK:2; /* Mid Address Space Block Lock */
+#else
+ uint32_t MLK:2; /* deprecated name - please avoid */
+#endif
+ uint32_t:6;
+ uint32_t LLOCK:10; /* Low Address Space Block Lock */
+ } B;
+ } CFLASH_LML_32B_tag;
+
+ typedef union { /* HBL - High Address Space Block Locking Register */
+ uint32_t R;
+ struct {
+ uint32_t HBE:1; /* High Address Space Block Enable */
+ uint32_t:25;
+ uint32_t HLOCK:6; /* High Address Space Block Lock */
+ } B;
+ } CFLASH_HBL_32B_tag;
+
+ typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */
+ uint32_t R;
+ struct {
+ uint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */
+ uint32_t:10;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */
+#else
+ uint32_t STSLK:1; /* deprecated name - please avoid */
+#endif
+ uint32_t:2;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */
+#else
+ uint32_t SMK:2; /* deprecated name - please avoid */
+#endif
+ uint32_t:6;
+ uint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */
+ } B;
+ } CFLASH_SLL_32B_tag;
+
+ typedef union { /* LMS - Low/Mid Address Space Block Select Register */
+ uint32_t R;
+ struct {
+ uint32_t:14;
+ uint32_t MSL:2; /* Mid Address Space Block Select */
+ uint32_t:6;
+ uint32_t LSL:10; /* Low Address Space Block Select */
+ } B;
+ } CFLASH_LMS_32B_tag;
+
+ typedef union { /* HBS - High Address Space Block Select Register */
+ uint32_t R;
+ struct {
+ uint32_t:26;
+ uint32_t HSL:6; /* High Address Space Block Select */
+ } B;
+ } CFLASH_HBS_32B_tag;
+
+ typedef union { /* ADR - Address Register */
+ uint32_t R;
+ struct {
+ uint32_t SAD:1; /* Shadow Address */
+ uint32_t:10;
+ uint32_t ADDR:18; /* Address */
+ uint32_t:3;
+ } B;
+ } CFLASH_ADR_32B_tag;
+
+ typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
+ uint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */
+#else
+ uint32_t BK0_APC:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */
+#else
+ uint32_t BK0_WWSC:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */
+#else
+ uint32_t BK0_RWSC:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */
+#else
+ uint32_t BK0_RWWC2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */
+#else
+ uint32_t BK0_RWWC1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */
+#else
+ uint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */
+#else
+ uint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */
+#else
+ uint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */
+#else
+ uint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */
+#else
+ uint32_t B0_P1_BFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */
+#else
+ uint32_t BK0_RWWC0:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */
+#else
+ uint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */
+#else
+ uint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */
+#else
+ uint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */
+#else
+ uint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */
+#else
+ uint32_t B0_P0_BFE:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } CFLASH_PFCR0_32B_tag;
+
+
+ /* Register layout for all registers BIU... */
+
+ typedef union { /* Bus Interface Unit Register */
+ uint32_t R;
+ } CFLASH_BIU_32B_tag;
+
+ typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
+ uint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */
+ uint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */
+ uint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */
+ uint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */
+ uint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */
+ uint32_t:6;
+ uint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */
+ uint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */
+ uint32_t:6;
+ uint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */
+#else
+ uint32_t BK1_APC:5;
+ uint32_t BK1_WWSC:5;
+ uint32_t BK1_RWSC:5;
+ uint32_t BK1_RWWC2:1;
+ uint32_t BK1_RWWC1:1;
+ uint32_t:6;
+ uint32_t B0_P1_BFE:1;
+ uint32_t BK1_RWWC0:1;
+ uint32_t:6;
+ uint32_t B1_P0_BFE:1;
+#endif
+ } B;
+ } CFLASH_PFCR1_32B_tag;
+
+ typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
+ uint32_t R;
+ struct {
+ uint32_t:6;
+ uint32_t ARBM:2; /* Arbitration Mode */
+ uint32_t M7PFD:1; /* Master x Prefetch Disable */
+ uint32_t M6PFD:1; /* Master x Prefetch Disable */
+ uint32_t M5PFD:1; /* Master x Prefetch Disable */
+ uint32_t M4PFD:1; /* Master x Prefetch Disable */
+ uint32_t M3PFD:1; /* Master x Prefetch Disable */
+ uint32_t M2PFD:1; /* Master x Prefetch Disable */
+ uint32_t M1PFD:1; /* Master x Prefetch Disable */
+ uint32_t M0PFD:1; /* Master x Prefetch Disable */
+ uint32_t M7AP:2; /* Master 7 Access Protection */
+ uint32_t M6AP:2; /* Master 6 Access Protection */
+ uint32_t M5AP:2; /* Master 5 Access Protection */
+ uint32_t M4AP:2; /* Master 4 Access Protection */
+ uint32_t M3AP:2; /* Master 3 Access Protection */
+ uint32_t M2AP:2; /* Master 2 Access Protection */
+ uint32_t M1AP:2; /* Master 1 Access Protection */
+ uint32_t M0AP:2; /* Master 0 Access Protection */
+ } B;
+ } CFLASH_PFAPR_32B_tag;
+
+ typedef union { /* UT0 - User Test Register */
+ uint32_t R;
+ struct {
+ uint32_t UTE:1; /* User Test Enable */
+ uint32_t SBCE:1; /* Single Bit Correction Enable */
+ uint32_t:6;
+ uint32_t DSI:8; /* Data Syndrome Input */
+ uint32_t:10;
+ uint32_t MRE:1; /* Margin Read Enable */
+ uint32_t MRV:1; /* Margin Read Value */
+ uint32_t EIE:1; /* ECC Data Input Enable */
+ uint32_t AIS:1; /* Array Integrity Sequence */
+ uint32_t AIE:1; /* Array Integrity Enable */
+ uint32_t AID:1; /* Array Integrity Done */
+ } B;
+ } CFLASH_UT0_32B_tag;
+
+ typedef union { /* UT1 - User Test Register */
+ uint32_t R;
+ } CFLASH_UT1_32B_tag;
+
+ typedef union { /* UT2 - User Test Register */
+ uint32_t R;
+ } CFLASH_UT2_32B_tag;
+
+
+ /* Register layout for all registers UM... */
+
+ typedef union { /* UM - User Multiple Input Signature Register */
+ uint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CFLASH
+ uint32_t MISR:32; /* Multiple Input Signature */
+#else
+ uint32_t MS:32; /* deprecated - please avoid */
+#endif
+ } B;
+ } CFLASH_UM_32B_tag;
+
+
+ /* Register layout for generated register(s) UT... */
+
+ typedef union { /* */
+ uint32_t R;
+ } CFLASH_UT_32B_tag;
+
+
+ /* Register layout for generated register(s) PFCR... */
+
+ typedef union { /* */
+ uint32_t R;
+ } CFLASH_PFCR_32B_tag;
+
+
+
+ typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */
+ /* MCR - Module Configuration Register */
+ CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
+ /* LML - Low/Mid Address Space Block Locking Register */
+ CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */
+ /* HBL - High Address Space Block Locking Register */
+ CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */
+ /* SLL - Secondary Low/Mid Address Space Block Locking Register */
+ CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */
+ /* LMS - Low/Mid Address Space Block Select Register */
+ CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */
+ /* HBS - High Address Space Block Select Register */
+ CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */
+ /* ADR - Address Register */
+ CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */
+ union {
+ struct {
+ /* */
+ CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */
+ int8_t CFLASH_reserved_0024_E0[12];
+ };
+
+ /* Bus Interface Unit Register */
+ CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */
+
+ struct {
+ /* Bus Interface Unit Register */
+ CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */
+ CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */
+ CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */
+ CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */
+ CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */
+ };
+
+ struct {
+ int8_t CFLASH_reserved_001C_I3[8];
+ CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */
+ int8_t CFLASH_reserved_0028_E3[8];
+ };
+
+ struct {
+ /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
+ CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */
+ /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
+ CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */
+ /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
+ CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */
+ int8_t CFLASH_reserved_0028_E4[8];
+ };
+
+ };
+ int8_t CFLASH_reserved_0030_C[12];
+ union {
+ CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */
+
+ struct {
+ /* UT0 - User Test Register */
+ CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */
+ /* UT1 - User Test Register */
+ CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */
+ /* UT2 - User Test Register */
+ CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */
+ };
+
+ };
+ union {
+ CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */
+
+ /* UM - User Multiple Input Signature Register */
+ CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */
+
+ struct {
+ /* UM - User Multiple Input Signature Register */
+ CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */
+ CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */
+ CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */
+ CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */
+ CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */
+ };
+
+ };
+ } CFLASH_tag;
+
+
+#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SIUL */
+/* */
+/****************************************************************/
+
+ typedef union { /* MIDR1 - MCU ID Register #1 */
+ uint32_t R;
+ struct {
+ uint32_t PARTNUM:16; /* MCU Part Number */
+ uint32_t CSP:1; /* CSP Package */
+ uint32_t PKG:5; /* Package Settings */
+ uint32_t:2;
+#ifndef USE_FIELD_ALIASES_SIUL
+ uint32_t MAJOR_MASK:4; /* Major Mask Revision */
+#else
+ uint32_t MAJORMASK:4; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SIUL
+ uint32_t MINOR_MASK:4; /* Minor Mask Revision */
+#else
+ uint32_t MINORMASK:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SIUL_MIDR1_32B_tag;
+
+ typedef union { /* MIDR2 - MCU ID Register #2 */
+ uint32_t R;
+ struct {
+ uint32_t SF:1; /* Manufacturer */
+ uint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */
+ uint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */
+ uint32_t:7;
+#ifndef USE_FIELD_ALIASES_SIUL
+ uint32_t PARTNUM2:8; /* MCU Part Number */
+#else
+ uint32_t PARTNUM:8; /* deprecated name - please avoid */
+#endif
+ uint32_t TBD:1; /* Optional Bit */
+ uint32_t:2;
+ uint32_t EE:1; /* Data Flash Present */
+ uint32_t:3;
+ uint32_t FR:1; /* Flexray Present */
+ } B;
+ } SIUL_MIDR2_32B_tag;
+
+ typedef union { /* ISR - Interrupt Status Flag Register */
+ uint32_t R;
+ struct {
+ uint32_t EIF31:1; /* External Interrupt Status Flag */
+ uint32_t EIF30:1; /* External Interrupt Status Flag */
+ uint32_t EIF29:1; /* External Interrupt Status Flag */
+ uint32_t EIF28:1; /* External Interrupt Status Flag */
+ uint32_t EIF27:1; /* External Interrupt Status Flag */
+ uint32_t EIF26:1; /* External Interrupt Status Flag */
+ uint32_t EIF25:1; /* External Interrupt Status Flag */
+ uint32_t EIF24:1; /* External Interrupt Status Flag */
+ uint32_t EIF23:1; /* External Interrupt Status Flag */
+ uint32_t EIF22:1; /* External Interrupt Status Flag */
+ uint32_t EIF21:1; /* External Interrupt Status Flag */
+ uint32_t EIF20:1; /* External Interrupt Status Flag */
+ uint32_t EIF19:1; /* External Interrupt Status Flag */
+ uint32_t EIF18:1; /* External Interrupt Status Flag */
+ uint32_t EIF17:1; /* External Interrupt Status Flag */
+ uint32_t EIF16:1; /* External Interrupt Status Flag */
+ uint32_t EIF15:1; /* External Interrupt Status Flag */
+ uint32_t EIF14:1; /* External Interrupt Status Flag */
+ uint32_t EIF13:1; /* External Interrupt Status Flag */
+ uint32_t EIF12:1; /* External Interrupt Status Flag */
+ uint32_t EIF11:1; /* External Interrupt Status Flag */
+ uint32_t EIF10:1; /* External Interrupt Status Flag */
+ uint32_t EIF9:1; /* External Interrupt Status Flag */
+ uint32_t EIF8:1; /* External Interrupt Status Flag */
+ uint32_t EIF7:1; /* External Interrupt Status Flag */
+ uint32_t EIF6:1; /* External Interrupt Status Flag */
+ uint32_t EIF5:1; /* External Interrupt Status Flag */
+ uint32_t EIF4:1; /* External Interrupt Status Flag */
+ uint32_t EIF3:1; /* External Interrupt Status Flag */
+ uint32_t EIF2:1; /* External Interrupt Status Flag */
+ uint32_t EIF1:1; /* External Interrupt Status Flag */
+ uint32_t EIF0:1; /* External Interrupt Status Flag */
+ } B;
+ } SIUL_ISR_32B_tag;
+
+ typedef union { /* IRER - Interrupt Request Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t EIRE31:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE30:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE29:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE28:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE27:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE26:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE25:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE24:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE23:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE22:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE21:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE20:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE19:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE18:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE17:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE16:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE15:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE14:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE13:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE12:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE11:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE10:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE9:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE8:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE7:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE6:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE5:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE4:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE3:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE2:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE1:1; /* Enable External Interrupt Requests */
+ uint32_t EIRE0:1; /* Enable External Interrupt Requests */
+ } B;
+ } SIUL_IRER_32B_tag;
+
+ typedef union { /* IREER - Interrupt Rising Edge Event Enable */
+ uint32_t R;
+ struct {
+ uint32_t IREE31:1; /* Enable rising-edge events */
+ uint32_t IREE30:1; /* Enable rising-edge events */
+ uint32_t IREE29:1; /* Enable rising-edge events */
+ uint32_t IREE28:1; /* Enable rising-edge events */
+ uint32_t IREE27:1; /* Enable rising-edge events */
+ uint32_t IREE26:1; /* Enable rising-edge events */
+ uint32_t IREE25:1; /* Enable rising-edge events */
+ uint32_t IREE24:1; /* Enable rising-edge events */
+ uint32_t IREE23:1; /* Enable rising-edge events */
+ uint32_t IREE22:1; /* Enable rising-edge events */
+ uint32_t IREE21:1; /* Enable rising-edge events */
+ uint32_t IREE20:1; /* Enable rising-edge events */
+ uint32_t IREE19:1; /* Enable rising-edge events */
+ uint32_t IREE18:1; /* Enable rising-edge events */
+ uint32_t IREE17:1; /* Enable rising-edge events */
+ uint32_t IREE16:1; /* Enable rising-edge events */
+ uint32_t IREE15:1; /* Enable rising-edge events */
+ uint32_t IREE14:1; /* Enable rising-edge events */
+ uint32_t IREE13:1; /* Enable rising-edge events */
+ uint32_t IREE12:1; /* Enable rising-edge events */
+ uint32_t IREE11:1; /* Enable rising-edge events */
+ uint32_t IREE10:1; /* Enable rising-edge events */
+ uint32_t IREE9:1; /* Enable rising-edge events */
+ uint32_t IREE8:1; /* Enable rising-edge events */
+ uint32_t IREE7:1; /* Enable rising-edge events */
+ uint32_t IREE6:1; /* Enable rising-edge events */
+ uint32_t IREE5:1; /* Enable rising-edge events */
+ uint32_t IREE4:1; /* Enable rising-edge events */
+ uint32_t IREE3:1; /* Enable rising-edge events */
+ uint32_t IREE2:1; /* Enable rising-edge events */
+ uint32_t IREE1:1; /* Enable rising-edge events */
+ uint32_t IREE0:1; /* Enable rising-edge events */
+ } B;
+ } SIUL_IREER_32B_tag;
+
+ typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */
+ uint32_t R;
+ struct {
+ uint32_t IFEE31:1; /* Enable Falling Edge Events */
+ uint32_t IFEE30:1; /* Enable Falling Edge Events */
+ uint32_t IFEE29:1; /* Enable Falling Edge Events */
+ uint32_t IFEE28:1; /* Enable Falling Edge Events */
+ uint32_t IFEE27:1; /* Enable Falling Edge Events */
+ uint32_t IFEE26:1; /* Enable Falling Edge Events */
+ uint32_t IFEE25:1; /* Enable Falling Edge Events */
+ uint32_t IFEE24:1; /* Enable Falling Edge Events */
+ uint32_t IFEE23:1; /* Enable Falling Edge Events */
+ uint32_t IFEE22:1; /* Enable Falling Edge Events */
+ uint32_t IFEE21:1; /* Enable Falling Edge Events */
+ uint32_t IFEE20:1; /* Enable Falling Edge Events */
+ uint32_t IFEE19:1; /* Enable Falling Edge Events */
+ uint32_t IFEE18:1; /* Enable Falling Edge Events */
+ uint32_t IFEE17:1; /* Enable Falling Edge Events */
+ uint32_t IFEE16:1; /* Enable Falling Edge Events */
+ uint32_t IFEE15:1; /* Enable Falling Edge Events */
+ uint32_t IFEE14:1; /* Enable Falling Edge Events */
+ uint32_t IFEE13:1; /* Enable Falling Edge Events */
+ uint32_t IFEE12:1; /* Enable Falling Edge Events */
+ uint32_t IFEE11:1; /* Enable Falling Edge Events */
+ uint32_t IFEE10:1; /* Enable Falling Edge Events */
+ uint32_t IFEE9:1; /* Enable Falling Edge Events */
+ uint32_t IFEE8:1; /* Enable Falling Edge Events */
+ uint32_t IFEE7:1; /* Enable Falling Edge Events */
+ uint32_t IFEE6:1; /* Enable Falling Edge Events */
+ uint32_t IFEE5:1; /* Enable Falling Edge Events */
+ uint32_t IFEE4:1; /* Enable Falling Edge Events */
+ uint32_t IFEE3:1; /* Enable Falling Edge Events */
+ uint32_t IFEE2:1; /* Enable Falling Edge Events */
+ uint32_t IFEE1:1; /* Enable Falling Edge Events */
+ uint32_t IFEE0:1; /* Enable Falling Edge Events */
+ } B;
+ } SIUL_IFEER_32B_tag;
+
+ typedef union { /* IFER Interrupt Filter Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t IFE31:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE30:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE29:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE28:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE27:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE26:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE25:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE24:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE23:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE22:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE21:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE20:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE19:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE18:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE17:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE16:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE15:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE14:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE13:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE12:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE11:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE10:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE9:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE8:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE7:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE6:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE5:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE4:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE3:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE2:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE1:1; /* Enable Digital Glitch Filter */
+ uint32_t IFE0:1; /* Enable Digital Glitch Filter */
+ } B;
+ } SIUL_IFER_32B_tag;
+
+
+ /* Register layout for all registers PCR... */
+
+ typedef union SIU_PCR_tag { /* PCR - Pad Configuration Register */
+ uint16_t R;
+ struct {
+ uint16_t:1;
+#ifndef USE_FIELD_ALIASES_SIUL
+ uint16_t SMC:1; /* Safe Mode Control */
+#else
+ uint16_t SME:1; /* deprecated name - please avoid */
+#endif
+ uint16_t APC:1; /* Analog Pad Control */
+ uint16_t:1;
+ uint16_t PA:2; /* Pad Output Assignment */
+ uint16_t OBE:1; /* Output Buffer Enable */
+ uint16_t IBE:1; /* Input Buffer Enable */
+#ifndef USE_FIELD_ALIASES_SIUL
+ uint16_t DSC:2; /* Drive Strength Control */
+#else
+ uint16_t DCS:2; /* deprecated name - please avoid */
+#endif
+ uint16_t ODE:1; /* Open Drain Output Enable */
+ uint16_t HYS:1; /* Input Hysteresis */
+ uint16_t SRC:2; /* Slew Rate Control */
+ uint16_t WPE:1; /* Weak Pull Up/Down Enable */
+ uint16_t WPS:1; /* Weak Pull Up/Down Select */
+ } B;
+ } SIU_PCR_tag;
+
+
+ /* Register layout for all registers PSMI... */
+
+ typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
+ uint8_t R;
+ struct {
+ uint8_t:4;
+ uint8_t PADSEL:4; /* Pad selection for pin */
+ } B;
+ } SIUL_PSMI_8B_tag;
+
+
+ /* Register layout for all registers PSMI... */
+
+ typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t PADSEL0:4; /* Pad selection for pin */
+ uint32_t:4;
+ uint32_t PADSEL1:4; /* Pad selection for pin */
+ uint32_t:4;
+ uint32_t PADSEL2:4; /* Pad selection for pin */
+ uint32_t:4;
+ uint32_t PADSEL3:4; /* Pad selection for pin */
+ } B;
+ } SIUL_PSMI_32B_tag;
+
+
+ /* Register layout for all registers GPDO... */
+
+ typedef union { /* GPDO - GPIO Pad Data Output Register */
+ uint8_t R;
+ struct {
+ uint8_t:7;
+ uint8_t PDO:1; /* Pad Data Out */
+ } B;
+ } SIUL_GPDO_8B_tag;
+
+
+ /* Register layout for all registers GPDO... */
+
+ typedef union { /* GPDO - GPIO Pad Data Output Register */
+ uint32_t R;
+ struct {
+ uint32_t:7;
+ uint32_t PDO0:1; /* Pad Data Out */
+ uint32_t:7;
+ uint32_t PDO1:1; /* Pad Data Out */
+ uint32_t:7;
+ uint32_t PDO2:1; /* Pad Data Out */
+ uint32_t:7;
+ uint32_t PDO3:1; /* Pad Data Out */
+ } B;
+ } SIUL_GPDO_32B_tag;
+
+
+ /* Register layout for all registers GPDI... */
+
+ typedef union { /* GPDI - GPIO Pad Data Input Register */
+ uint8_t R;
+ struct {
+ uint8_t:7;
+ uint8_t PDI:1; /* Pad Data In */
+ } B;
+ } SIUL_GPDI_8B_tag;
+
+
+ /* Register layout for all registers GPDI... */
+
+ typedef union { /* GPDI - GPIO Pad Data Input Register */
+ uint32_t R;
+ struct {
+ uint32_t:7;
+ uint32_t PDI0:1; /* Pad Data In */
+ uint32_t:7;
+ uint32_t PDI1:1; /* Pad Data In */
+ uint32_t:7;
+ uint32_t PDI2:1; /* Pad Data In */
+ uint32_t:7;
+ uint32_t PDI3:1; /* Pad Data In */
+ } B;
+ } SIUL_GPDI_32B_tag;
+
+
+ /* Register layout for all registers PGPDO... */
+
+ typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */
+ uint16_t R;
+ } SIUL_PGPDO_16B_tag;
+
+
+ /* Register layout for all registers PGPDI... */
+
+ typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */
+ uint16_t R;
+ } SIUL_PGPDI_16B_tag;
+
+
+ /* Register layout for all registers MPGPDO... */
+
+ typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
+ uint32_t R;
+ struct {
+ uint32_t MASK:16; /* Mask Field */
+ uint32_t MPPDO:16; /* Masked Parallel Pad Data Out */
+ } B;
+ } SIUL_MPGPDO_32B_tag;
+
+
+ /* Register layout for all registers IFMC... */
+
+ typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */
+ } B;
+ } SIUL_IFMC_32B_tag;
+
+ typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */
+ } B;
+ } SIUL_IFCPR_32B_tag;
+
+
+
+ typedef struct SIU_tag { /* start of SIUL_tag */
+ int8_t SIUL_reserved_0000_C[4];
+ union {
+ SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */
+
+ /* MIDR1 - MCU ID Register #1 */
+ SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */
+
+ };
+ /* MIDR2 - MCU ID Register #2 */
+ SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */
+ int8_t SIUL_reserved_000C[8];
+ /* ISR - Interrupt Status Flag Register */
+ SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */
+ /* IRER - Interrupt Request Enable Register */
+ SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
+ int8_t SIUL_reserved_001C[12];
+ /* IREER - Interrupt Rising Edge Event Enable */
+ SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */
+ /* IFEER - Interrupt Falling-Edge Event Enable */
+ SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */
+ /* IFER Interrupt Filter Enable Register */
+ SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */
+ int8_t SIUL_reserved_0034_C[12];
+ union {
+ /* PCR - Pad Configuration Register */
+ SIU_PCR_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */
+
+ struct {
+ /* PCR - Pad Configuration Register */
+ SIU_PCR_tag PCR0; /* offset: 0x0040 size: 16 bit */
+ SIU_PCR_tag PCR1; /* offset: 0x0042 size: 16 bit */
+ SIU_PCR_tag PCR2; /* offset: 0x0044 size: 16 bit */
+ SIU_PCR_tag PCR3; /* offset: 0x0046 size: 16 bit */
+ SIU_PCR_tag PCR4; /* offset: 0x0048 size: 16 bit */
+ SIU_PCR_tag PCR5; /* offset: 0x004A size: 16 bit */
+ SIU_PCR_tag PCR6; /* offset: 0x004C size: 16 bit */
+ SIU_PCR_tag PCR7; /* offset: 0x004E size: 16 bit */
+ SIU_PCR_tag PCR8; /* offset: 0x0050 size: 16 bit */
+ SIU_PCR_tag PCR9; /* offset: 0x0052 size: 16 bit */
+ SIU_PCR_tag PCR10; /* offset: 0x0054 size: 16 bit */
+ SIU_PCR_tag PCR11; /* offset: 0x0056 size: 16 bit */
+ SIU_PCR_tag PCR12; /* offset: 0x0058 size: 16 bit */
+ SIU_PCR_tag PCR13; /* offset: 0x005A size: 16 bit */
+ SIU_PCR_tag PCR14; /* offset: 0x005C size: 16 bit */
+ SIU_PCR_tag PCR15; /* offset: 0x005E size: 16 bit */
+ SIU_PCR_tag PCR16; /* offset: 0x0060 size: 16 bit */
+ SIU_PCR_tag PCR17; /* offset: 0x0062 size: 16 bit */
+ SIU_PCR_tag PCR18; /* offset: 0x0064 size: 16 bit */
+ SIU_PCR_tag PCR19; /* offset: 0x0066 size: 16 bit */
+ SIU_PCR_tag PCR20; /* offset: 0x0068 size: 16 bit */
+ SIU_PCR_tag PCR21; /* offset: 0x006A size: 16 bit */
+ SIU_PCR_tag PCR22; /* offset: 0x006C size: 16 bit */
+ SIU_PCR_tag PCR23; /* offset: 0x006E size: 16 bit */
+ SIU_PCR_tag PCR24; /* offset: 0x0070 size: 16 bit */
+ SIU_PCR_tag PCR25; /* offset: 0x0072 size: 16 bit */
+ SIU_PCR_tag PCR26; /* offset: 0x0074 size: 16 bit */
+ SIU_PCR_tag PCR27; /* offset: 0x0076 size: 16 bit */
+ SIU_PCR_tag PCR28; /* offset: 0x0078 size: 16 bit */
+ SIU_PCR_tag PCR29; /* offset: 0x007A size: 16 bit */
+ SIU_PCR_tag PCR30; /* offset: 0x007C size: 16 bit */
+ SIU_PCR_tag PCR31; /* offset: 0x007E size: 16 bit */
+ SIU_PCR_tag PCR32; /* offset: 0x0080 size: 16 bit */
+ SIU_PCR_tag PCR33; /* offset: 0x0082 size: 16 bit */
+ SIU_PCR_tag PCR34; /* offset: 0x0084 size: 16 bit */
+ SIU_PCR_tag PCR35; /* offset: 0x0086 size: 16 bit */
+ SIU_PCR_tag PCR36; /* offset: 0x0088 size: 16 bit */
+ SIU_PCR_tag PCR37; /* offset: 0x008A size: 16 bit */
+ SIU_PCR_tag PCR38; /* offset: 0x008C size: 16 bit */
+ SIU_PCR_tag PCR39; /* offset: 0x008E size: 16 bit */
+ SIU_PCR_tag PCR40; /* offset: 0x0090 size: 16 bit */
+ SIU_PCR_tag PCR41; /* offset: 0x0092 size: 16 bit */
+ SIU_PCR_tag PCR42; /* offset: 0x0094 size: 16 bit */
+ SIU_PCR_tag PCR43; /* offset: 0x0096 size: 16 bit */
+ SIU_PCR_tag PCR44; /* offset: 0x0098 size: 16 bit */
+ SIU_PCR_tag PCR45; /* offset: 0x009A size: 16 bit */
+ SIU_PCR_tag PCR46; /* offset: 0x009C size: 16 bit */
+ SIU_PCR_tag PCR47; /* offset: 0x009E size: 16 bit */
+ SIU_PCR_tag PCR48; /* offset: 0x00A0 size: 16 bit */
+ SIU_PCR_tag PCR49; /* offset: 0x00A2 size: 16 bit */
+ SIU_PCR_tag PCR50; /* offset: 0x00A4 size: 16 bit */
+ SIU_PCR_tag PCR51; /* offset: 0x00A6 size: 16 bit */
+ SIU_PCR_tag PCR52; /* offset: 0x00A8 size: 16 bit */
+ SIU_PCR_tag PCR53; /* offset: 0x00AA size: 16 bit */
+ SIU_PCR_tag PCR54; /* offset: 0x00AC size: 16 bit */
+ SIU_PCR_tag PCR55; /* offset: 0x00AE size: 16 bit */
+ SIU_PCR_tag PCR56; /* offset: 0x00B0 size: 16 bit */
+ SIU_PCR_tag PCR57; /* offset: 0x00B2 size: 16 bit */
+ SIU_PCR_tag PCR58; /* offset: 0x00B4 size: 16 bit */
+ SIU_PCR_tag PCR59; /* offset: 0x00B6 size: 16 bit */
+ SIU_PCR_tag PCR60; /* offset: 0x00B8 size: 16 bit */
+ SIU_PCR_tag PCR61; /* offset: 0x00BA size: 16 bit */
+ SIU_PCR_tag PCR62; /* offset: 0x00BC size: 16 bit */
+ SIU_PCR_tag PCR63; /* offset: 0x00BE size: 16 bit */
+ SIU_PCR_tag PCR64; /* offset: 0x00C0 size: 16 bit */
+ SIU_PCR_tag PCR65; /* offset: 0x00C2 size: 16 bit */
+ SIU_PCR_tag PCR66; /* offset: 0x00C4 size: 16 bit */
+ SIU_PCR_tag PCR67; /* offset: 0x00C6 size: 16 bit */
+ SIU_PCR_tag PCR68; /* offset: 0x00C8 size: 16 bit */
+ SIU_PCR_tag PCR69; /* offset: 0x00CA size: 16 bit */
+ SIU_PCR_tag PCR70; /* offset: 0x00CC size: 16 bit */
+ SIU_PCR_tag PCR71; /* offset: 0x00CE size: 16 bit */
+ SIU_PCR_tag PCR72; /* offset: 0x00D0 size: 16 bit */
+ SIU_PCR_tag PCR73; /* offset: 0x00D2 size: 16 bit */
+ SIU_PCR_tag PCR74; /* offset: 0x00D4 size: 16 bit */
+ SIU_PCR_tag PCR75; /* offset: 0x00D6 size: 16 bit */
+ SIU_PCR_tag PCR76; /* offset: 0x00D8 size: 16 bit */
+ SIU_PCR_tag PCR77; /* offset: 0x00DA size: 16 bit */
+ SIU_PCR_tag PCR78; /* offset: 0x00DC size: 16 bit */
+ SIU_PCR_tag PCR79; /* offset: 0x00DE size: 16 bit */
+ SIU_PCR_tag PCR80; /* offset: 0x00E0 size: 16 bit */
+ SIU_PCR_tag PCR81; /* offset: 0x00E2 size: 16 bit */
+ SIU_PCR_tag PCR82; /* offset: 0x00E4 size: 16 bit */
+ SIU_PCR_tag PCR83; /* offset: 0x00E6 size: 16 bit */
+ SIU_PCR_tag PCR84; /* offset: 0x00E8 size: 16 bit */
+ SIU_PCR_tag PCR85; /* offset: 0x00EA size: 16 bit */
+ SIU_PCR_tag PCR86; /* offset: 0x00EC size: 16 bit */
+ SIU_PCR_tag PCR87; /* offset: 0x00EE size: 16 bit */
+ SIU_PCR_tag PCR88; /* offset: 0x00F0 size: 16 bit */
+ SIU_PCR_tag PCR89; /* offset: 0x00F2 size: 16 bit */
+ SIU_PCR_tag PCR90; /* offset: 0x00F4 size: 16 bit */
+ SIU_PCR_tag PCR91; /* offset: 0x00F6 size: 16 bit */
+ SIU_PCR_tag PCR92; /* offset: 0x00F8 size: 16 bit */
+ SIU_PCR_tag PCR93; /* offset: 0x00FA size: 16 bit */
+ SIU_PCR_tag PCR94; /* offset: 0x00FC size: 16 bit */
+ SIU_PCR_tag PCR95; /* offset: 0x00FE size: 16 bit */
+ SIU_PCR_tag PCR96; /* offset: 0x0100 size: 16 bit */
+ SIU_PCR_tag PCR97; /* offset: 0x0102 size: 16 bit */
+ SIU_PCR_tag PCR98; /* offset: 0x0104 size: 16 bit */
+ SIU_PCR_tag PCR99; /* offset: 0x0106 size: 16 bit */
+ SIU_PCR_tag PCR100; /* offset: 0x0108 size: 16 bit */
+ SIU_PCR_tag PCR101; /* offset: 0x010A size: 16 bit */
+ SIU_PCR_tag PCR102; /* offset: 0x010C size: 16 bit */
+ SIU_PCR_tag PCR103; /* offset: 0x010E size: 16 bit */
+ SIU_PCR_tag PCR104; /* offset: 0x0110 size: 16 bit */
+ SIU_PCR_tag PCR105; /* offset: 0x0112 size: 16 bit */
+ SIU_PCR_tag PCR106; /* offset: 0x0114 size: 16 bit */
+ SIU_PCR_tag PCR107; /* offset: 0x0116 size: 16 bit */
+ SIU_PCR_tag PCR108; /* offset: 0x0118 size: 16 bit */
+ SIU_PCR_tag PCR109; /* offset: 0x011A size: 16 bit */
+ SIU_PCR_tag PCR110; /* offset: 0x011C size: 16 bit */
+ SIU_PCR_tag PCR111; /* offset: 0x011E size: 16 bit */
+ SIU_PCR_tag PCR112; /* offset: 0x0120 size: 16 bit */
+ SIU_PCR_tag PCR113; /* offset: 0x0122 size: 16 bit */
+ SIU_PCR_tag PCR114; /* offset: 0x0124 size: 16 bit */
+ SIU_PCR_tag PCR115; /* offset: 0x0126 size: 16 bit */
+ SIU_PCR_tag PCR116; /* offset: 0x0128 size: 16 bit */
+ SIU_PCR_tag PCR117; /* offset: 0x012A size: 16 bit */
+ SIU_PCR_tag PCR118; /* offset: 0x012C size: 16 bit */
+ SIU_PCR_tag PCR119; /* offset: 0x012E size: 16 bit */
+ SIU_PCR_tag PCR120; /* offset: 0x0130 size: 16 bit */
+ SIU_PCR_tag PCR121; /* offset: 0x0132 size: 16 bit */
+ SIU_PCR_tag PCR122; /* offset: 0x0134 size: 16 bit */
+ SIU_PCR_tag PCR123; /* offset: 0x0136 size: 16 bit */
+ SIU_PCR_tag PCR124; /* offset: 0x0138 size: 16 bit */
+ SIU_PCR_tag PCR125; /* offset: 0x013A size: 16 bit */
+ SIU_PCR_tag PCR126; /* offset: 0x013C size: 16 bit */
+ SIU_PCR_tag PCR127; /* offset: 0x013E size: 16 bit */
+ SIU_PCR_tag PCR128; /* offset: 0x0140 size: 16 bit */
+ SIU_PCR_tag PCR129; /* offset: 0x0142 size: 16 bit */
+ SIU_PCR_tag PCR130; /* offset: 0x0144 size: 16 bit */
+ SIU_PCR_tag PCR131; /* offset: 0x0146 size: 16 bit */
+ SIU_PCR_tag PCR132; /* offset: 0x0148 size: 16 bit */
+ SIU_PCR_tag PCR133; /* offset: 0x014A size: 16 bit */
+ SIU_PCR_tag PCR134; /* offset: 0x014C size: 16 bit */
+ SIU_PCR_tag PCR135; /* offset: 0x014E size: 16 bit */
+ SIU_PCR_tag PCR136; /* offset: 0x0150 size: 16 bit */
+ SIU_PCR_tag PCR137; /* offset: 0x0152 size: 16 bit */
+ SIU_PCR_tag PCR138; /* offset: 0x0154 size: 16 bit */
+ SIU_PCR_tag PCR139; /* offset: 0x0156 size: 16 bit */
+ SIU_PCR_tag PCR140; /* offset: 0x0158 size: 16 bit */
+ SIU_PCR_tag PCR141; /* offset: 0x015A size: 16 bit */
+ SIU_PCR_tag PCR142; /* offset: 0x015C size: 16 bit */
+ SIU_PCR_tag PCR143; /* offset: 0x015E size: 16 bit */
+ SIU_PCR_tag PCR144; /* offset: 0x0160 size: 16 bit */
+ SIU_PCR_tag PCR145; /* offset: 0x0162 size: 16 bit */
+ SIU_PCR_tag PCR146; /* offset: 0x0164 size: 16 bit */
+ SIU_PCR_tag PCR147; /* offset: 0x0166 size: 16 bit */
+ SIU_PCR_tag PCR148; /* offset: 0x0168 size: 16 bit */
+ SIU_PCR_tag PCR149; /* offset: 0x016A size: 16 bit */
+ SIU_PCR_tag PCR150; /* offset: 0x016C size: 16 bit */
+ SIU_PCR_tag PCR151; /* offset: 0x016E size: 16 bit */
+ SIU_PCR_tag PCR152; /* offset: 0x0170 size: 16 bit */
+ SIU_PCR_tag PCR153; /* offset: 0x0172 size: 16 bit */
+ SIU_PCR_tag PCR154; /* offset: 0x0174 size: 16 bit */
+ SIU_PCR_tag PCR155; /* offset: 0x0176 size: 16 bit */
+ SIU_PCR_tag PCR156; /* offset: 0x0178 size: 16 bit */
+ SIU_PCR_tag PCR157; /* offset: 0x017A size: 16 bit */
+ SIU_PCR_tag PCR158; /* offset: 0x017C size: 16 bit */
+ SIU_PCR_tag PCR159; /* offset: 0x017E size: 16 bit */
+ SIU_PCR_tag PCR160; /* offset: 0x0180 size: 16 bit */
+ SIU_PCR_tag PCR161; /* offset: 0x0182 size: 16 bit */
+ SIU_PCR_tag PCR162; /* offset: 0x0184 size: 16 bit */
+ SIU_PCR_tag PCR163; /* offset: 0x0186 size: 16 bit */
+ SIU_PCR_tag PCR164; /* offset: 0x0188 size: 16 bit */
+ SIU_PCR_tag PCR165; /* offset: 0x018A size: 16 bit */
+ SIU_PCR_tag PCR166; /* offset: 0x018C size: 16 bit */
+ SIU_PCR_tag PCR167; /* offset: 0x018E size: 16 bit */
+ SIU_PCR_tag PCR168; /* offset: 0x0190 size: 16 bit */
+ SIU_PCR_tag PCR169; /* offset: 0x0192 size: 16 bit */
+ SIU_PCR_tag PCR170; /* offset: 0x0194 size: 16 bit */
+ SIU_PCR_tag PCR171; /* offset: 0x0196 size: 16 bit */
+ SIU_PCR_tag PCR172; /* offset: 0x0198 size: 16 bit */
+ SIU_PCR_tag PCR173; /* offset: 0x019A size: 16 bit */
+ SIU_PCR_tag PCR174; /* offset: 0x019C size: 16 bit */
+ SIU_PCR_tag PCR175; /* offset: 0x019E size: 16 bit */
+ SIU_PCR_tag PCR176; /* offset: 0x01A0 size: 16 bit */
+ SIU_PCR_tag PCR177; /* offset: 0x01A2 size: 16 bit */
+ SIU_PCR_tag PCR178; /* offset: 0x01A4 size: 16 bit */
+ SIU_PCR_tag PCR179; /* offset: 0x01A6 size: 16 bit */
+ SIU_PCR_tag PCR180; /* offset: 0x01A8 size: 16 bit */
+ SIU_PCR_tag PCR181; /* offset: 0x01AA size: 16 bit */
+ SIU_PCR_tag PCR182; /* offset: 0x01AC size: 16 bit */
+ SIU_PCR_tag PCR183; /* offset: 0x01AE size: 16 bit */
+ SIU_PCR_tag PCR184; /* offset: 0x01B0 size: 16 bit */
+ SIU_PCR_tag PCR185; /* offset: 0x01B2 size: 16 bit */
+ SIU_PCR_tag PCR186; /* offset: 0x01B4 size: 16 bit */
+ SIU_PCR_tag PCR187; /* offset: 0x01B6 size: 16 bit */
+ SIU_PCR_tag PCR188; /* offset: 0x01B8 size: 16 bit */
+ SIU_PCR_tag PCR189; /* offset: 0x01BA size: 16 bit */
+ SIU_PCR_tag PCR190; /* offset: 0x01BC size: 16 bit */
+ SIU_PCR_tag PCR191; /* offset: 0x01BE size: 16 bit */
+ SIU_PCR_tag PCR192; /* offset: 0x01C0 size: 16 bit */
+ SIU_PCR_tag PCR193; /* offset: 0x01C2 size: 16 bit */
+ SIU_PCR_tag PCR194; /* offset: 0x01C4 size: 16 bit */
+ SIU_PCR_tag PCR195; /* offset: 0x01C6 size: 16 bit */
+ SIU_PCR_tag PCR196; /* offset: 0x01C8 size: 16 bit */
+ SIU_PCR_tag PCR197; /* offset: 0x01CA size: 16 bit */
+ SIU_PCR_tag PCR198; /* offset: 0x01CC size: 16 bit */
+ SIU_PCR_tag PCR199; /* offset: 0x01CE size: 16 bit */
+ SIU_PCR_tag PCR200; /* offset: 0x01D0 size: 16 bit */
+ SIU_PCR_tag PCR201; /* offset: 0x01D2 size: 16 bit */
+ SIU_PCR_tag PCR202; /* offset: 0x01D4 size: 16 bit */
+ SIU_PCR_tag PCR203; /* offset: 0x01D6 size: 16 bit */
+ SIU_PCR_tag PCR204; /* offset: 0x01D8 size: 16 bit */
+ SIU_PCR_tag PCR205; /* offset: 0x01DA size: 16 bit */
+ SIU_PCR_tag PCR206; /* offset: 0x01DC size: 16 bit */
+ SIU_PCR_tag PCR207; /* offset: 0x01DE size: 16 bit */
+ SIU_PCR_tag PCR208; /* offset: 0x01E0 size: 16 bit */
+ SIU_PCR_tag PCR209; /* offset: 0x01E2 size: 16 bit */
+ SIU_PCR_tag PCR210; /* offset: 0x01E4 size: 16 bit */
+ SIU_PCR_tag PCR211; /* offset: 0x01E6 size: 16 bit */
+ SIU_PCR_tag PCR212; /* offset: 0x01E8 size: 16 bit */
+ SIU_PCR_tag PCR213; /* offset: 0x01EA size: 16 bit */
+ SIU_PCR_tag PCR214; /* offset: 0x01EC size: 16 bit */
+ SIU_PCR_tag PCR215; /* offset: 0x01EE size: 16 bit */
+ SIU_PCR_tag PCR216; /* offset: 0x01F0 size: 16 bit */
+ SIU_PCR_tag PCR217; /* offset: 0x01F2 size: 16 bit */
+ SIU_PCR_tag PCR218; /* offset: 0x01F4 size: 16 bit */
+ SIU_PCR_tag PCR219; /* offset: 0x01F6 size: 16 bit */
+ SIU_PCR_tag PCR220; /* offset: 0x01F8 size: 16 bit */
+ SIU_PCR_tag PCR221; /* offset: 0x01FA size: 16 bit */
+ SIU_PCR_tag PCR222; /* offset: 0x01FC size: 16 bit */
+ SIU_PCR_tag PCR223; /* offset: 0x01FE size: 16 bit */
+ SIU_PCR_tag PCR224; /* offset: 0x0200 size: 16 bit */
+ SIU_PCR_tag PCR225; /* offset: 0x0202 size: 16 bit */
+ SIU_PCR_tag PCR226; /* offset: 0x0204 size: 16 bit */
+ SIU_PCR_tag PCR227; /* offset: 0x0206 size: 16 bit */
+ SIU_PCR_tag PCR228; /* offset: 0x0208 size: 16 bit */
+ SIU_PCR_tag PCR229; /* offset: 0x020A size: 16 bit */
+ SIU_PCR_tag PCR230; /* offset: 0x020C size: 16 bit */
+ SIU_PCR_tag PCR231; /* offset: 0x020E size: 16 bit */
+ SIU_PCR_tag PCR232; /* offset: 0x0210 size: 16 bit */
+ SIU_PCR_tag PCR233; /* offset: 0x0212 size: 16 bit */
+ SIU_PCR_tag PCR234; /* offset: 0x0214 size: 16 bit */
+ SIU_PCR_tag PCR235; /* offset: 0x0216 size: 16 bit */
+ SIU_PCR_tag PCR236; /* offset: 0x0218 size: 16 bit */
+ SIU_PCR_tag PCR237; /* offset: 0x021A size: 16 bit */
+ SIU_PCR_tag PCR238; /* offset: 0x021C size: 16 bit */
+ SIU_PCR_tag PCR239; /* offset: 0x021E size: 16 bit */
+ SIU_PCR_tag PCR240; /* offset: 0x0220 size: 16 bit */
+ SIU_PCR_tag PCR241; /* offset: 0x0222 size: 16 bit */
+ SIU_PCR_tag PCR242; /* offset: 0x0224 size: 16 bit */
+ SIU_PCR_tag PCR243; /* offset: 0x0226 size: 16 bit */
+ SIU_PCR_tag PCR244; /* offset: 0x0228 size: 16 bit */
+ SIU_PCR_tag PCR245; /* offset: 0x022A size: 16 bit */
+ SIU_PCR_tag PCR246; /* offset: 0x022C size: 16 bit */
+ SIU_PCR_tag PCR247; /* offset: 0x022E size: 16 bit */
+ SIU_PCR_tag PCR248; /* offset: 0x0230 size: 16 bit */
+ SIU_PCR_tag PCR249; /* offset: 0x0232 size: 16 bit */
+ SIU_PCR_tag PCR250; /* offset: 0x0234 size: 16 bit */
+ SIU_PCR_tag PCR251; /* offset: 0x0236 size: 16 bit */
+ SIU_PCR_tag PCR252; /* offset: 0x0238 size: 16 bit */
+ SIU_PCR_tag PCR253; /* offset: 0x023A size: 16 bit */
+ SIU_PCR_tag PCR254; /* offset: 0x023C size: 16 bit */
+ SIU_PCR_tag PCR255; /* offset: 0x023E size: 16 bit */
+ SIU_PCR_tag PCR256; /* offset: 0x0240 size: 16 bit */
+ SIU_PCR_tag PCR257; /* offset: 0x0242 size: 16 bit */
+ SIU_PCR_tag PCR258; /* offset: 0x0244 size: 16 bit */
+ SIU_PCR_tag PCR259; /* offset: 0x0246 size: 16 bit */
+ SIU_PCR_tag PCR260; /* offset: 0x0248 size: 16 bit */
+ SIU_PCR_tag PCR261; /* offset: 0x024A size: 16 bit */
+ SIU_PCR_tag PCR262; /* offset: 0x024C size: 16 bit */
+ SIU_PCR_tag PCR263; /* offset: 0x024E size: 16 bit */
+ SIU_PCR_tag PCR264; /* offset: 0x0250 size: 16 bit */
+ SIU_PCR_tag PCR265; /* offset: 0x0252 size: 16 bit */
+ SIU_PCR_tag PCR266; /* offset: 0x0254 size: 16 bit */
+ SIU_PCR_tag PCR267; /* offset: 0x0256 size: 16 bit */
+ SIU_PCR_tag PCR268; /* offset: 0x0258 size: 16 bit */
+ SIU_PCR_tag PCR269; /* offset: 0x025A size: 16 bit */
+ SIU_PCR_tag PCR270; /* offset: 0x025C size: 16 bit */
+ SIU_PCR_tag PCR271; /* offset: 0x025E size: 16 bit */
+ SIU_PCR_tag PCR272; /* offset: 0x0260 size: 16 bit */
+ SIU_PCR_tag PCR273; /* offset: 0x0262 size: 16 bit */
+ SIU_PCR_tag PCR274; /* offset: 0x0264 size: 16 bit */
+ SIU_PCR_tag PCR275; /* offset: 0x0266 size: 16 bit */
+ SIU_PCR_tag PCR276; /* offset: 0x0268 size: 16 bit */
+ SIU_PCR_tag PCR277; /* offset: 0x026A size: 16 bit */
+ SIU_PCR_tag PCR278; /* offset: 0x026C size: 16 bit */
+ SIU_PCR_tag PCR279; /* offset: 0x026E size: 16 bit */
+ SIU_PCR_tag PCR280; /* offset: 0x0270 size: 16 bit */
+ SIU_PCR_tag PCR281; /* offset: 0x0272 size: 16 bit */
+ SIU_PCR_tag PCR282; /* offset: 0x0274 size: 16 bit */
+ SIU_PCR_tag PCR283; /* offset: 0x0276 size: 16 bit */
+ SIU_PCR_tag PCR284; /* offset: 0x0278 size: 16 bit */
+ SIU_PCR_tag PCR285; /* offset: 0x027A size: 16 bit */
+ SIU_PCR_tag PCR286; /* offset: 0x027C size: 16 bit */
+ SIU_PCR_tag PCR287; /* offset: 0x027E size: 16 bit */
+ SIU_PCR_tag PCR288; /* offset: 0x0280 size: 16 bit */
+ SIU_PCR_tag PCR289; /* offset: 0x0282 size: 16 bit */
+ SIU_PCR_tag PCR290; /* offset: 0x0284 size: 16 bit */
+ SIU_PCR_tag PCR291; /* offset: 0x0286 size: 16 bit */
+ SIU_PCR_tag PCR292; /* offset: 0x0288 size: 16 bit */
+ SIU_PCR_tag PCR293; /* offset: 0x028A size: 16 bit */
+ SIU_PCR_tag PCR294; /* offset: 0x028C size: 16 bit */
+ SIU_PCR_tag PCR295; /* offset: 0x028E size: 16 bit */
+ SIU_PCR_tag PCR296; /* offset: 0x0290 size: 16 bit */
+ SIU_PCR_tag PCR297; /* offset: 0x0292 size: 16 bit */
+ SIU_PCR_tag PCR298; /* offset: 0x0294 size: 16 bit */
+ SIU_PCR_tag PCR299; /* offset: 0x0296 size: 16 bit */
+ SIU_PCR_tag PCR300; /* offset: 0x0298 size: 16 bit */
+ SIU_PCR_tag PCR301; /* offset: 0x029A size: 16 bit */
+ SIU_PCR_tag PCR302; /* offset: 0x029C size: 16 bit */
+ SIU_PCR_tag PCR303; /* offset: 0x029E size: 16 bit */
+ SIU_PCR_tag PCR304; /* offset: 0x02A0 size: 16 bit */
+ SIU_PCR_tag PCR305; /* offset: 0x02A2 size: 16 bit */
+ SIU_PCR_tag PCR306; /* offset: 0x02A4 size: 16 bit */
+ SIU_PCR_tag PCR307; /* offset: 0x02A6 size: 16 bit */
+ SIU_PCR_tag PCR308; /* offset: 0x02A8 size: 16 bit */
+ SIU_PCR_tag PCR309; /* offset: 0x02AA size: 16 bit */
+ SIU_PCR_tag PCR310; /* offset: 0x02AC size: 16 bit */
+ SIU_PCR_tag PCR311; /* offset: 0x02AE size: 16 bit */
+ SIU_PCR_tag PCR312; /* offset: 0x02B0 size: 16 bit */
+ SIU_PCR_tag PCR313; /* offset: 0x02B2 size: 16 bit */
+ SIU_PCR_tag PCR314; /* offset: 0x02B4 size: 16 bit */
+ SIU_PCR_tag PCR315; /* offset: 0x02B6 size: 16 bit */
+ SIU_PCR_tag PCR316; /* offset: 0x02B8 size: 16 bit */
+ SIU_PCR_tag PCR317; /* offset: 0x02BA size: 16 bit */
+ SIU_PCR_tag PCR318; /* offset: 0x02BC size: 16 bit */
+ SIU_PCR_tag PCR319; /* offset: 0x02BE size: 16 bit */
+ SIU_PCR_tag PCR320; /* offset: 0x02C0 size: 16 bit */
+ SIU_PCR_tag PCR321; /* offset: 0x02C2 size: 16 bit */
+ SIU_PCR_tag PCR322; /* offset: 0x02C4 size: 16 bit */
+ SIU_PCR_tag PCR323; /* offset: 0x02C6 size: 16 bit */
+ SIU_PCR_tag PCR324; /* offset: 0x02C8 size: 16 bit */
+ SIU_PCR_tag PCR325; /* offset: 0x02CA size: 16 bit */
+ SIU_PCR_tag PCR326; /* offset: 0x02CC size: 16 bit */
+ SIU_PCR_tag PCR327; /* offset: 0x02CE size: 16 bit */
+ SIU_PCR_tag PCR328; /* offset: 0x02D0 size: 16 bit */
+ SIU_PCR_tag PCR329; /* offset: 0x02D2 size: 16 bit */
+ SIU_PCR_tag PCR330; /* offset: 0x02D4 size: 16 bit */
+ SIU_PCR_tag PCR331; /* offset: 0x02D6 size: 16 bit */
+ SIU_PCR_tag PCR332; /* offset: 0x02D8 size: 16 bit */
+ SIU_PCR_tag PCR333; /* offset: 0x02DA size: 16 bit */
+ SIU_PCR_tag PCR334; /* offset: 0x02DC size: 16 bit */
+ SIU_PCR_tag PCR335; /* offset: 0x02DE size: 16 bit */
+ SIU_PCR_tag PCR336; /* offset: 0x02E0 size: 16 bit */
+ SIU_PCR_tag PCR337; /* offset: 0x02E2 size: 16 bit */
+ SIU_PCR_tag PCR338; /* offset: 0x02E4 size: 16 bit */
+ SIU_PCR_tag PCR339; /* offset: 0x02E6 size: 16 bit */
+ SIU_PCR_tag PCR340; /* offset: 0x02E8 size: 16 bit */
+ SIU_PCR_tag PCR341; /* offset: 0x02EA size: 16 bit */
+ SIU_PCR_tag PCR342; /* offset: 0x02EC size: 16 bit */
+ SIU_PCR_tag PCR343; /* offset: 0x02EE size: 16 bit */
+ SIU_PCR_tag PCR344; /* offset: 0x02F0 size: 16 bit */
+ SIU_PCR_tag PCR345; /* offset: 0x02F2 size: 16 bit */
+ SIU_PCR_tag PCR346; /* offset: 0x02F4 size: 16 bit */
+ SIU_PCR_tag PCR347; /* offset: 0x02F6 size: 16 bit */
+ SIU_PCR_tag PCR348; /* offset: 0x02F8 size: 16 bit */
+ SIU_PCR_tag PCR349; /* offset: 0x02FA size: 16 bit */
+ SIU_PCR_tag PCR350; /* offset: 0x02FC size: 16 bit */
+ SIU_PCR_tag PCR351; /* offset: 0x02FE size: 16 bit */
+ SIU_PCR_tag PCR352; /* offset: 0x0300 size: 16 bit */
+ SIU_PCR_tag PCR353; /* offset: 0x0302 size: 16 bit */
+ SIU_PCR_tag PCR354; /* offset: 0x0304 size: 16 bit */
+ SIU_PCR_tag PCR355; /* offset: 0x0306 size: 16 bit */
+ SIU_PCR_tag PCR356; /* offset: 0x0308 size: 16 bit */
+ SIU_PCR_tag PCR357; /* offset: 0x030A size: 16 bit */
+ SIU_PCR_tag PCR358; /* offset: 0x030C size: 16 bit */
+ SIU_PCR_tag PCR359; /* offset: 0x030E size: 16 bit */
+ SIU_PCR_tag PCR360; /* offset: 0x0310 size: 16 bit */
+ SIU_PCR_tag PCR361; /* offset: 0x0312 size: 16 bit */
+ SIU_PCR_tag PCR362; /* offset: 0x0314 size: 16 bit */
+ SIU_PCR_tag PCR363; /* offset: 0x0316 size: 16 bit */
+ SIU_PCR_tag PCR364; /* offset: 0x0318 size: 16 bit */
+ SIU_PCR_tag PCR365; /* offset: 0x031A size: 16 bit */
+ SIU_PCR_tag PCR366; /* offset: 0x031C size: 16 bit */
+ SIU_PCR_tag PCR367; /* offset: 0x031E size: 16 bit */
+ SIU_PCR_tag PCR368; /* offset: 0x0320 size: 16 bit */
+ SIU_PCR_tag PCR369; /* offset: 0x0322 size: 16 bit */
+ SIU_PCR_tag PCR370; /* offset: 0x0324 size: 16 bit */
+ SIU_PCR_tag PCR371; /* offset: 0x0326 size: 16 bit */
+ SIU_PCR_tag PCR372; /* offset: 0x0328 size: 16 bit */
+ SIU_PCR_tag PCR373; /* offset: 0x032A size: 16 bit */
+ SIU_PCR_tag PCR374; /* offset: 0x032C size: 16 bit */
+ SIU_PCR_tag PCR375; /* offset: 0x032E size: 16 bit */
+ SIU_PCR_tag PCR376; /* offset: 0x0330 size: 16 bit */
+ SIU_PCR_tag PCR377; /* offset: 0x0332 size: 16 bit */
+ SIU_PCR_tag PCR378; /* offset: 0x0334 size: 16 bit */
+ SIU_PCR_tag PCR379; /* offset: 0x0336 size: 16 bit */
+ SIU_PCR_tag PCR380; /* offset: 0x0338 size: 16 bit */
+ SIU_PCR_tag PCR381; /* offset: 0x033A size: 16 bit */
+ SIU_PCR_tag PCR382; /* offset: 0x033C size: 16 bit */
+ SIU_PCR_tag PCR383; /* offset: 0x033E size: 16 bit */
+ SIU_PCR_tag PCR384; /* offset: 0x0340 size: 16 bit */
+ SIU_PCR_tag PCR385; /* offset: 0x0342 size: 16 bit */
+ SIU_PCR_tag PCR386; /* offset: 0x0344 size: 16 bit */
+ SIU_PCR_tag PCR387; /* offset: 0x0346 size: 16 bit */
+ SIU_PCR_tag PCR388; /* offset: 0x0348 size: 16 bit */
+ SIU_PCR_tag PCR389; /* offset: 0x034A size: 16 bit */
+ SIU_PCR_tag PCR390; /* offset: 0x034C size: 16 bit */
+ SIU_PCR_tag PCR391; /* offset: 0x034E size: 16 bit */
+ SIU_PCR_tag PCR392; /* offset: 0x0350 size: 16 bit */
+ SIU_PCR_tag PCR393; /* offset: 0x0352 size: 16 bit */
+ SIU_PCR_tag PCR394; /* offset: 0x0354 size: 16 bit */
+ SIU_PCR_tag PCR395; /* offset: 0x0356 size: 16 bit */
+ SIU_PCR_tag PCR396; /* offset: 0x0358 size: 16 bit */
+ SIU_PCR_tag PCR397; /* offset: 0x035A size: 16 bit */
+ SIU_PCR_tag PCR398; /* offset: 0x035C size: 16 bit */
+ SIU_PCR_tag PCR399; /* offset: 0x035E size: 16 bit */
+ SIU_PCR_tag PCR400; /* offset: 0x0360 size: 16 bit */
+ SIU_PCR_tag PCR401; /* offset: 0x0362 size: 16 bit */
+ SIU_PCR_tag PCR402; /* offset: 0x0364 size: 16 bit */
+ SIU_PCR_tag PCR403; /* offset: 0x0366 size: 16 bit */
+ SIU_PCR_tag PCR404; /* offset: 0x0368 size: 16 bit */
+ SIU_PCR_tag PCR405; /* offset: 0x036A size: 16 bit */
+ SIU_PCR_tag PCR406; /* offset: 0x036C size: 16 bit */
+ SIU_PCR_tag PCR407; /* offset: 0x036E size: 16 bit */
+ SIU_PCR_tag PCR408; /* offset: 0x0370 size: 16 bit */
+ SIU_PCR_tag PCR409; /* offset: 0x0372 size: 16 bit */
+ SIU_PCR_tag PCR410; /* offset: 0x0374 size: 16 bit */
+ SIU_PCR_tag PCR411; /* offset: 0x0376 size: 16 bit */
+ SIU_PCR_tag PCR412; /* offset: 0x0378 size: 16 bit */
+ SIU_PCR_tag PCR413; /* offset: 0x037A size: 16 bit */
+ SIU_PCR_tag PCR414; /* offset: 0x037C size: 16 bit */
+ SIU_PCR_tag PCR415; /* offset: 0x037E size: 16 bit */
+ SIU_PCR_tag PCR416; /* offset: 0x0380 size: 16 bit */
+ SIU_PCR_tag PCR417; /* offset: 0x0382 size: 16 bit */
+ SIU_PCR_tag PCR418; /* offset: 0x0384 size: 16 bit */
+ SIU_PCR_tag PCR419; /* offset: 0x0386 size: 16 bit */
+ SIU_PCR_tag PCR420; /* offset: 0x0388 size: 16 bit */
+ SIU_PCR_tag PCR421; /* offset: 0x038A size: 16 bit */
+ SIU_PCR_tag PCR422; /* offset: 0x038C size: 16 bit */
+ SIU_PCR_tag PCR423; /* offset: 0x038E size: 16 bit */
+ SIU_PCR_tag PCR424; /* offset: 0x0390 size: 16 bit */
+ SIU_PCR_tag PCR425; /* offset: 0x0392 size: 16 bit */
+ SIU_PCR_tag PCR426; /* offset: 0x0394 size: 16 bit */
+ SIU_PCR_tag PCR427; /* offset: 0x0396 size: 16 bit */
+ SIU_PCR_tag PCR428; /* offset: 0x0398 size: 16 bit */
+ SIU_PCR_tag PCR429; /* offset: 0x039A size: 16 bit */
+ SIU_PCR_tag PCR430; /* offset: 0x039C size: 16 bit */
+ SIU_PCR_tag PCR431; /* offset: 0x039E size: 16 bit */
+ SIU_PCR_tag PCR432; /* offset: 0x03A0 size: 16 bit */
+ SIU_PCR_tag PCR433; /* offset: 0x03A2 size: 16 bit */
+ SIU_PCR_tag PCR434; /* offset: 0x03A4 size: 16 bit */
+ SIU_PCR_tag PCR435; /* offset: 0x03A6 size: 16 bit */
+ SIU_PCR_tag PCR436; /* offset: 0x03A8 size: 16 bit */
+ SIU_PCR_tag PCR437; /* offset: 0x03AA size: 16 bit */
+ SIU_PCR_tag PCR438; /* offset: 0x03AC size: 16 bit */
+ SIU_PCR_tag PCR439; /* offset: 0x03AE size: 16 bit */
+ SIU_PCR_tag PCR440; /* offset: 0x03B0 size: 16 bit */
+ SIU_PCR_tag PCR441; /* offset: 0x03B2 size: 16 bit */
+ SIU_PCR_tag PCR442; /* offset: 0x03B4 size: 16 bit */
+ SIU_PCR_tag PCR443; /* offset: 0x03B6 size: 16 bit */
+ SIU_PCR_tag PCR444; /* offset: 0x03B8 size: 16 bit */
+ SIU_PCR_tag PCR445; /* offset: 0x03BA size: 16 bit */
+ SIU_PCR_tag PCR446; /* offset: 0x03BC size: 16 bit */
+ SIU_PCR_tag PCR447; /* offset: 0x03BE size: 16 bit */
+ SIU_PCR_tag PCR448; /* offset: 0x03C0 size: 16 bit */
+ SIU_PCR_tag PCR449; /* offset: 0x03C2 size: 16 bit */
+ SIU_PCR_tag PCR450; /* offset: 0x03C4 size: 16 bit */
+ SIU_PCR_tag PCR451; /* offset: 0x03C6 size: 16 bit */
+ SIU_PCR_tag PCR452; /* offset: 0x03C8 size: 16 bit */
+ SIU_PCR_tag PCR453; /* offset: 0x03CA size: 16 bit */
+ SIU_PCR_tag PCR454; /* offset: 0x03CC size: 16 bit */
+ SIU_PCR_tag PCR455; /* offset: 0x03CE size: 16 bit */
+ SIU_PCR_tag PCR456; /* offset: 0x03D0 size: 16 bit */
+ SIU_PCR_tag PCR457; /* offset: 0x03D2 size: 16 bit */
+ SIU_PCR_tag PCR458; /* offset: 0x03D4 size: 16 bit */
+ SIU_PCR_tag PCR459; /* offset: 0x03D6 size: 16 bit */
+ SIU_PCR_tag PCR460; /* offset: 0x03D8 size: 16 bit */
+ SIU_PCR_tag PCR461; /* offset: 0x03DA size: 16 bit */
+ SIU_PCR_tag PCR462; /* offset: 0x03DC size: 16 bit */
+ SIU_PCR_tag PCR463; /* offset: 0x03DE size: 16 bit */
+ SIU_PCR_tag PCR464; /* offset: 0x03E0 size: 16 bit */
+ SIU_PCR_tag PCR465; /* offset: 0x03E2 size: 16 bit */
+ SIU_PCR_tag PCR466; /* offset: 0x03E4 size: 16 bit */
+ SIU_PCR_tag PCR467; /* offset: 0x03E6 size: 16 bit */
+ SIU_PCR_tag PCR468; /* offset: 0x03E8 size: 16 bit */
+ SIU_PCR_tag PCR469; /* offset: 0x03EA size: 16 bit */
+ SIU_PCR_tag PCR470; /* offset: 0x03EC size: 16 bit */
+ SIU_PCR_tag PCR471; /* offset: 0x03EE size: 16 bit */
+ SIU_PCR_tag PCR472; /* offset: 0x03F0 size: 16 bit */
+ SIU_PCR_tag PCR473; /* offset: 0x03F2 size: 16 bit */
+ SIU_PCR_tag PCR474; /* offset: 0x03F4 size: 16 bit */
+ SIU_PCR_tag PCR475; /* offset: 0x03F6 size: 16 bit */
+ SIU_PCR_tag PCR476; /* offset: 0x03F8 size: 16 bit */
+ SIU_PCR_tag PCR477; /* offset: 0x03FA size: 16 bit */
+ SIU_PCR_tag PCR478; /* offset: 0x03FC size: 16 bit */
+ SIU_PCR_tag PCR479; /* offset: 0x03FE size: 16 bit */
+ SIU_PCR_tag PCR480; /* offset: 0x0400 size: 16 bit */
+ SIU_PCR_tag PCR481; /* offset: 0x0402 size: 16 bit */
+ SIU_PCR_tag PCR482; /* offset: 0x0404 size: 16 bit */
+ SIU_PCR_tag PCR483; /* offset: 0x0406 size: 16 bit */
+ SIU_PCR_tag PCR484; /* offset: 0x0408 size: 16 bit */
+ SIU_PCR_tag PCR485; /* offset: 0x040A size: 16 bit */
+ SIU_PCR_tag PCR486; /* offset: 0x040C size: 16 bit */
+ SIU_PCR_tag PCR487; /* offset: 0x040E size: 16 bit */
+ SIU_PCR_tag PCR488; /* offset: 0x0410 size: 16 bit */
+ SIU_PCR_tag PCR489; /* offset: 0x0412 size: 16 bit */
+ SIU_PCR_tag PCR490; /* offset: 0x0414 size: 16 bit */
+ SIU_PCR_tag PCR491; /* offset: 0x0416 size: 16 bit */
+ SIU_PCR_tag PCR492; /* offset: 0x0418 size: 16 bit */
+ SIU_PCR_tag PCR493; /* offset: 0x041A size: 16 bit */
+ SIU_PCR_tag PCR494; /* offset: 0x041C size: 16 bit */
+ SIU_PCR_tag PCR495; /* offset: 0x041E size: 16 bit */
+ SIU_PCR_tag PCR496; /* offset: 0x0420 size: 16 bit */
+ SIU_PCR_tag PCR497; /* offset: 0x0422 size: 16 bit */
+ SIU_PCR_tag PCR498; /* offset: 0x0424 size: 16 bit */
+ SIU_PCR_tag PCR499; /* offset: 0x0426 size: 16 bit */
+ SIU_PCR_tag PCR500; /* offset: 0x0428 size: 16 bit */
+ SIU_PCR_tag PCR501; /* offset: 0x042A size: 16 bit */
+ SIU_PCR_tag PCR502; /* offset: 0x042C size: 16 bit */
+ SIU_PCR_tag PCR503; /* offset: 0x042E size: 16 bit */
+ SIU_PCR_tag PCR504; /* offset: 0x0430 size: 16 bit */
+ SIU_PCR_tag PCR505; /* offset: 0x0432 size: 16 bit */
+ SIU_PCR_tag PCR506; /* offset: 0x0434 size: 16 bit */
+ SIU_PCR_tag PCR507; /* offset: 0x0436 size: 16 bit */
+ SIU_PCR_tag PCR508; /* offset: 0x0438 size: 16 bit */
+ SIU_PCR_tag PCR509; /* offset: 0x043A size: 16 bit */
+ SIU_PCR_tag PCR510; /* offset: 0x043C size: 16 bit */
+ SIU_PCR_tag PCR511; /* offset: 0x043E size: 16 bit */
+ };
+
+ };
+ int8_t SIUL_reserved_0440_C[192];
+ union {
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */
+
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */
+
+ struct {
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */
+ };
+
+ struct {
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */
+ };
+
+ };
+ union {
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */
+
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */
+
+ struct {
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */
+ };
+
+ struct {
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */
+ };
+
+ };
+ union {
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */
+
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */
+
+ struct {
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */
+ };
+
+ struct {
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */
+ };
+
+ };
+ int8_t SIUL_reserved_0A00_C[512];
+ union {
+ /* PGPDO - Parallel GPIO Pad Data Out Register */
+ SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */
+
+ struct {
+ /* PGPDO - Parallel GPIO Pad Data Out Register */
+ SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */
+ };
+
+ };
+ union {
+ /* PGPDI - Parallel GPIO Pad Data In Register */
+ SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */
+
+ struct {
+ /* PGPDI - Parallel GPIO Pad Data In Register */
+ SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */
+ };
+
+ };
+ union {
+ /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
+ SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */
+
+ struct {
+ /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
+ SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */
+ };
+
+ };
+ int8_t SIUL_reserved_0D00_C[768];
+ union {
+ /* IFMC - Interrupt Filter Maximum Counter Register */
+ SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */
+
+ struct {
+ /* IFMC - Interrupt Filter Maximum Counter Register */
+ SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */
+ };
+
+ };
+ /* IFCPR - Inerrupt Filter Clock Prescaler Register */
+ SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */
+ } SIU_tag;
+
+
+#define SIUL (*(volatile SIU_tag *) 0xC3F90000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: WKPU */
+/* */
+/****************************************************************/
+
+ typedef union { /* WKPU_NSR - NMI Status Flag Register */
+ uint32_t R;
+ struct {
+ uint32_t NIF0:1; /* NMI Status Flag 0 */
+ uint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */
+ uint32_t:6;
+ uint32_t NIF1:1; /* NMI Status Flag 1 */
+ uint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */
+ uint32_t:6;
+ uint32_t NIF2:1; /* NMI Status Flag 2 */
+ uint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */
+ uint32_t:6;
+ uint32_t NIF3:1; /* NMI Status Flag 3 */
+ uint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */
+ uint32_t:6;
+ } B;
+ } WKPU_NSR_32B_tag;
+
+ typedef union { /* WKPU_NCR - NMI Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */
+ uint32_t NDSS0:2; /* NMI Desination Source Select 0 */
+ uint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */
+ uint32_t:1;
+ uint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */
+ uint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */
+ uint32_t NFE0:1; /* NMI Filter Enable 0 */
+ uint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */
+ uint32_t NDSS1:2; /* NMI Desination Source Select 1 */
+ uint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */
+ uint32_t:1;
+ uint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */
+ uint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */
+ uint32_t NFE1:1; /* NMI Filter Enable 1 */
+ uint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */
+ uint32_t NDSS2:2; /* NMI Desination Source Select 2 */
+ uint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */
+ uint32_t:1;
+ uint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */
+ uint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */
+ uint32_t NFE2:1; /* NMI Filter Enable 2 */
+ uint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */
+ uint32_t NDSS3:2; /* NMI Desination Source Select 3 */
+ uint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */
+ uint32_t:1;
+ uint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */
+ uint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */
+ uint32_t NFE3:1; /* NMI Filter Enable 3 */
+ } B;
+ } WKPU_NCR_32B_tag;
+
+ typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
+ uint32_t R;
+ struct {
+ uint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */
+ } B;
+ } WKPU_WISR_32B_tag;
+
+ typedef union { /* WKPU_IRER - Interrupt Request Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t EIRE:32; /* Enable External Interrupt Requests */
+ } B;
+ } WKPU_IRER_32B_tag;
+
+ typedef union { /* WKPU_WRER - Wakeup Request Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */
+ } B;
+ } WKPU_WRER_32B_tag;
+
+ typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */
+ } B;
+ } WKPU_WIREER_32B_tag;
+
+ typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */
+ } B;
+ } WKPU_WIFEER_32B_tag;
+
+ typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */
+ } B;
+ } WKPU_WIFER_32B_tag;
+
+ typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */
+ } B;
+ } WKPU_WIPUER_32B_tag;
+
+
+
+ typedef struct WKPU_struct_tag { /* start of WKPU_tag */
+ /* WKPU_NSR - NMI Status Flag Register */
+ WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */
+ int8_t WKPU_reserved_0004[4];
+ /* WKPU_NCR - NMI Configuration Register */
+ WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */
+ int8_t WKPU_reserved_000C[8];
+ /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
+ WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */
+ /* WKPU_IRER - Interrupt Request Enable Register */
+ WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
+ /* WKPU_WRER - Wakeup Request Enable Register */
+ WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */
+ int8_t WKPU_reserved_0020[8];
+ /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
+ WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */
+ /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
+ WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */
+ /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
+ WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */
+ /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
+ WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */
+ } WKPU_tag;
+
+
+#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SSCM */
+/* */
+/****************************************************************/
+
+ typedef union { /* SSCM_STATUS - System Status Register */
+ uint16_t R;
+ struct {
+ uint16_t LSM:1; /* Lock Step Mode */
+ uint16_t:2;
+ uint16_t NXEN1:1; /* Processor 1 Nexus enabled */
+ uint16_t NXEN:1; /* Processor 0 Nexus enabled */
+ uint16_t PUB:1; /* Public Serial Access Status */
+ uint16_t SEC:1; /* Security Status */
+ uint16_t:1;
+ uint16_t BMODE:3; /* Device Boot Mode */
+ uint16_t VLE:1; /* Variable Length Instruction Mode */
+ uint16_t ABD:1; /* Autobaud detection */
+ uint16_t:3;
+ } B;
+ } SSCM_STATUS_16B_tag;
+
+ typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */
+ uint16_t R;
+ struct {
+ uint16_t JPIN:10; /* JTAG Part ID Number */
+ uint16_t IVLD:1; /* Instruction Flash Valid */
+ uint16_t MREV:4; /* Minor Mask Revision */
+ uint16_t DVLD:1; /* Data Flash Valid */
+ } B;
+ } SSCM_MEMCONFIG_16B_tag;
+
+ typedef union { /* SSCM_ERROR - Error Configuration */
+ uint16_t R;
+ struct {
+ uint16_t:14;
+ uint16_t PAE:1; /* Peripheral Bus Abort Enable */
+ uint16_t RAE:1; /* Register Bus Abort Enable */
+ } B;
+ } SSCM_ERROR_16B_tag;
+
+ typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */
+ uint16_t R;
+ struct {
+ uint16_t:13;
+ uint16_t DEBUG_MODE:3; /* Debug Status Port Mode */
+ } B;
+ } SSCM_DEBUGPORT_16B_tag;
+
+ typedef union { /* SSCM_PWCMPH - Password Comparison Register High */
+ uint32_t R;
+ struct {
+ uint32_t PWD_HI:32; /* Password High */
+ } B;
+ } SSCM_PWCMPH_32B_tag;
+
+ typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */
+ uint32_t R;
+ struct {
+ uint32_t PWD_LO:32; /* Password Low */
+ } B;
+ } SSCM_PWCMPL_32B_tag;
+
+ typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
+ uint32_t R;
+ struct {
+ uint32_t P2BOOT:30; /* boot location 2nd processor */
+ uint32_t DVLE:1; /* VLE mode for 2nd processor */
+ uint32_t:1;
+ } B;
+ } SSCM_DPMBOOT_32B_tag;
+
+ typedef union { /* SSCM_DPMKEY - Boot Key Register */
+ uint32_t R;
+ struct {
+ uint32_t KEY:32; /* Boot Control Key */
+ } B;
+ } SSCM_DPMKEY_32B_tag;
+
+ typedef union { /* SSCM_UOPS - User Option Status Register */
+ uint32_t R;
+ struct {
+ uint32_t UOPT:32; /* User Option Bits */
+ } B;
+ } SSCM_UOPS_32B_tag;
+
+ typedef union { /* SSCM_SCTR - SSCM Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:29;
+ uint32_t TFE:1; /* Test Flash Enable */
+ uint32_t DSL:1; /* Disable Software-Controlled MBIST */
+ uint32_t DSM:1; /* Disable Software-Controlled LBIST */
+ } B;
+ } SSCM_SCTR_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
+ uint32_t R;
+ struct {
+ uint32_t TINFO0:32; /* General purpose TestFlash word 0 */
+ } B;
+ } SSCM_TF_INFO0_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
+ uint32_t R;
+ struct {
+ uint32_t TINFO1:32; /* General purpose TestFlash word 1 */
+ } B;
+ } SSCM_TF_INFO1_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
+ uint32_t R;
+ struct {
+ uint32_t TINFO2:32; /* General purpose TestFlash word 2 */
+ } B;
+ } SSCM_TF_INFO2_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
+ uint32_t R;
+ struct {
+ uint32_t TINFO3:32; /* General purpose TestFlash word */
+ } B;
+ } SSCM_TF_INFO3_32B_tag;
+
+
+
+ typedef struct SSCM_struct_tag { /* start of SSCM_tag */
+ /* SSCM_STATUS - System Status Register */
+ SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */
+ /* SSCM_MEMCONFIG - System Memory Configuration Register */
+ SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */
+ int8_t SSCM_reserved_0004[2];
+ /* SSCM_ERROR - Error Configuration */
+ SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */
+ /* SSCM_DEBUGPORT - Debug Status Port Register */
+ SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */
+ int8_t SSCM_reserved_000A[2];
+ /* SSCM_PWCMPH - Password Comparison Register High */
+ SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */
+ /* SSCM_PWCMPL - Password Comparison Register Low */
+ SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */
+ int8_t SSCM_reserved_0014[4];
+ /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
+ SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */
+ /* SSCM_DPMKEY - Boot Key Register */
+ SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */
+ /* SSCM_UOPS - User Option Status Register */
+ SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */
+ /* SSCM_SCTR - SSCM Control Register */
+ SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */
+ /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
+ SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */
+ /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
+ SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */
+ /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
+ SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */
+ /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
+ SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */
+ } SSCM_tag;
+
+
+#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: ME */
+/* */
+/****************************************************************/
+
+ typedef union { /* ME_GS - Global Status Register */
+ uint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t S_CURRENT_MODE:4; /* Current device mode status */
+#else
+ uint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */
+#endif
+ uint32_t S_MTRANS:1; /* Mode transition status */
+ uint32_t:3;
+ uint32_t S_PDO:1; /* Output power-down status */
+ uint32_t:2;
+ uint32_t S_MVR:1; /* Main voltage regulator status */
+ uint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t S_FLA:2; /* Flash availability status */
+#else
+ uint32_t S_CFLA:2; /* deprecated name - please avoid */
+#endif
+ uint32_t:8;
+ uint32_t S_PLL1:1; /* Secondary PLL status */
+ uint32_t S_PLL0:1; /* System PLL status */
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t S_XOSC:1; /* System crystal oscillator status */
+#else
+ uint32_t S_OSC:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t S_IRCOSC:1; /* System RC oscillator status */
+#else
+ uint32_t S_RC:1; /* deprecated name - please avoid */
+#endif
+ uint32_t S_SYSCLK:4; /* System clock switch status */
+ } B;
+ } ME_GS_32B_tag;
+
+ typedef union { /* ME_MCTL - Mode Control Register */
+ uint32_t R;
+ struct {
+ uint32_t TARGET_MODE:4; /* Target device mode */
+ uint32_t:12;
+ uint32_t KEY:16; /* Control key */
+ } B;
+ } ME_MCTL_32B_tag;
+
+ typedef union { /* ME_MEN - Mode Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:21;
+ uint32_t STOP0:1; /* STOP0 mode enable */
+ uint32_t:1;
+ uint32_t HALT0:1; /* HALT0 mode enable */
+ uint32_t RUN3:1; /* RUN3 mode enable */
+ uint32_t RUN2:1; /* RUN2 mode enable */
+ uint32_t RUN1:1; /* RUN1 mode enable */
+ uint32_t RUN0:1; /* RUN0 mode enable */
+ uint32_t DRUN:1; /* DRUN mode enable */
+ uint32_t SAFE:1; /* SAFE mode enable */
+ uint32_t:1;
+ uint32_t RESET:1; /* RESET mode enable */
+ } B;
+ } ME_MEN_32B_tag;
+
+ typedef union { /* ME_IS - Interrupt Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t I_ICONF:1; /* Invalid mode config interrupt */
+#else
+ uint32_t I_CONF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t I_IMODE:1; /* Invalid mode interrupt */
+#else
+ uint32_t I_MODE:1; /* deprecated name - please avoid */
+#endif
+ uint32_t I_SAFE:1; /* SAFE mode interrupt */
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t I_MTC:1; /* Mode transition complete interrupt */
+#else
+ uint32_t I_TC:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ME_IS_32B_tag;
+
+ typedef union { /* ME_IM - Interrupt Mask Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t M_ICONF:1; /* Invalid mode config interrupt mask */
+#else
+ uint32_t M_CONF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t M_IMODE:1; /* Invalid mode interrupt mask */
+#else
+ uint32_t M_MODE:1; /* deprecated name - please avoid */
+#endif
+ uint32_t M_SAFE:1; /* SAFE mode interrupt mask */
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t M_MTC:1; /* Mode transition complete interrupt mask */
+#else
+ uint32_t M_TC:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ME_IM_32B_tag;
+
+ typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:27;
+ uint32_t S_MTI:1; /* Mode Transition Illegal status */
+ uint32_t S_MRI:1; /* Mode Request Illegal status */
+ uint32_t S_DMA:1; /* Disabled Mode Access status */
+ uint32_t S_NMA:1; /* Non-existing Mode Access status */
+ uint32_t S_SEA:1; /* Safe Event Active status */
+ } B;
+ } ME_IMTS_32B_tag;
+
+ typedef union { /* ME_DMTS - Debug Mode Transition Status Register */
+ uint32_t R;
+ struct {
+ uint32_t PREVIOUS_MODE:4; /* Previous Device Mode */
+ uint32_t:4;
+ uint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */
+ uint32_t:2;
+ uint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */
+ uint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */
+ uint32_t:2;
+ uint32_t SMR:1; /* SAFE Mode Request */
+ uint32_t:1;
+ uint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */
+ uint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */
+ uint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */
+ uint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */
+ uint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */
+ uint32_t:1;
+ uint32_t FLASH_SC:1; /* FLASH State Change Indicator */
+ uint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */
+ uint32_t:4;
+ uint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */
+ uint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */
+ uint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */
+ } B;
+ } ME_DMTS_32B_tag;
+
+ typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_RESET_MC_32B_tag;
+
+ typedef union { /* ME_SAFE_MC - Mode Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_SAFE_MC_32B_tag;
+
+ typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_DRUN_MC_32B_tag;
+
+
+ /* Register layout for all registers RUN_MC... */
+
+ typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_RUN_MC_32B_tag;
+
+ typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_HALT0_MC_32B_tag;
+
+ typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_STOP0_MC_32B_tag;
+
+ typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t PDO:1; /* IOs output power-down control */
+ uint32_t:2;
+ uint32_t MVRON:1; /* Main voltage regulator control */
+ uint32_t:2;
+ uint32_t FLAON:2; /* Flash power-down control */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ uint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t PLL0ON:1; /* System PLL control */
+#else
+ uint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ uint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ uint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ uint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ uint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_STANDBY0_MC_32B_tag;
+
+ typedef union { /* ME_PS0 - Peripheral Status Register 0 */
+ uint32_t R;
+ struct {
+ uint32_t:7;
+ uint32_t S_FLEXRAY:1; /* FlexRay status */
+ uint32_t:6;
+ uint32_t S_FLEXCAN1:1; /* FlexCAN1 status */
+ uint32_t S_FLEXCAN0:1; /* FlexCAN0 status */
+ uint32_t:9;
+ uint32_t S_DSPI2:1; /* DSPI2 status */
+ uint32_t S_DSPI1:1; /* DSPI1 status */
+ uint32_t S_DSPI0:1; /* DSPI0 status */
+ uint32_t:4;
+ } B;
+ } ME_PS0_32B_tag;
+
+ typedef union { /* ME_PS1 - Peripheral Status Register 1 */
+ uint32_t R;
+ struct {
+ uint32_t:1;
+ uint32_t S_SWG:1; /* SWG status */
+ uint32_t:3;
+ uint32_t S_CRC:1; /* CRC status */
+ uint32_t:8;
+ uint32_t S_LIN_FLEX1:1; /* LinFlex1 status */
+ uint32_t S_LIN_FLEX0:1; /* LinFlex0 status */
+ uint32_t:5;
+ uint32_t S_FLEXPWM1:1; /* FlexPWM1 status */
+ uint32_t S_FLEXPWM0:1; /* FlexPWM0 status */
+ uint32_t S_ETIMER2:1; /* eTimer2 status */
+ uint32_t S_ETIMER1:1; /* eTimer1 status */
+ uint32_t S_ETIMER0:1; /* eTimer0 status */
+ uint32_t:2;
+ uint32_t S_CTU:1; /* CTU status */
+ uint32_t:1;
+ uint32_t S_ADC1:1; /* ADC1 status */
+ uint32_t S_ADC0:1; /* ADC0 status */
+ } B;
+ } ME_PS1_32B_tag;
+
+ typedef union { /* ME_PS2 - Peripheral Status Register 2 */
+ uint32_t R;
+ struct {
+ uint32_t:3;
+ uint32_t S_PIT:1; /* PIT status */
+ uint32_t:28;
+ } B;
+ } ME_PS2_32B_tag;
+
+
+ /* Register layout for all registers RUN_PC... */
+
+ typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t RUN3:1; /* Peripheral control during RUN3 */
+ uint32_t RUN2:1; /* Peripheral control during RUN2 */
+ uint32_t RUN1:1; /* Peripheral control during RUN1 */
+ uint32_t RUN0:1; /* Peripheral control during RUN0 */
+ uint32_t DRUN:1; /* Peripheral control during DRUN */
+ uint32_t SAFE:1; /* Peripheral control during SAFE */
+ uint32_t TEST:1; /* Peripheral control during TEST */
+ uint32_t RESET:1; /* Peripheral control during RESET */
+ } B;
+ } ME_RUN_PC_32B_tag;
+
+
+ /* Register layout for all registers LP_PC... */
+
+ typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
+ uint32_t R;
+ struct {
+ uint32_t:21;
+ uint32_t STOP0:1; /* Peripheral control during STOP0 */
+ uint32_t:1;
+ uint32_t HALT0:1; /* Peripheral control during HALT0 */
+ uint32_t:8;
+ } B;
+ } ME_LP_PC_32B_tag;
+
+
+ /* Register layout for all registers PCTL... */
+
+ typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */
+ uint8_t R;
+ struct {
+ uint8_t:1;
+ uint8_t DBG_F:1; /* Peripheral control in debug mode */
+ uint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */
+ uint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */
+ } B;
+ } ME_PCTL_8B_tag;
+
+
+
+
+ /* Register layout for generated register(s) PS... */
+
+ typedef union { /* */
+ uint32_t R;
+ } ME_PS_32B_tag;
+
+
+
+
+
+
+ typedef struct ME_struct_tag { /* start of ME_tag */
+ /* ME_GS - Global Status Register */
+ ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */
+ /* ME_MCTL - Mode Control Register */
+ ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */
+ union {
+ ME_MEN_32B_tag MER; /* deprecated - please avoid */
+
+ /* ME_MEN - Mode Enable Register */
+ ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */
+
+ };
+ /* ME_IS - Interrupt Status Register */
+ ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */
+ /* ME_IM - Interrupt Mask Register */
+ ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */
+ /* ME_IMTS - Invalid Mode Transition Status Register */
+ ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */
+ /* ME_DMTS - Debug Mode Transition Status Register */
+ ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */
+ int8_t ME_reserved_001C_C[4];
+ union {
+ /* ME_RESET_MC - RESET Mode Configuration Register */
+ ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */
+
+ ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_0024_C[4];
+ union {
+ /* ME_SAFE_MC - Mode Configuration Register */
+ ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */
+
+ ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */
+
+ };
+ union {
+ /* ME_DRUN_MC - DRUN Mode Configuration Register */
+ ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */
+
+ ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */
+
+ };
+ union {
+ /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
+ ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */
+
+ ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */
+
+ struct {
+ /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
+ ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */
+ ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */
+ ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */
+ ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */
+ };
+
+ };
+ union {
+ /* ME_HALT0_MC - HALT0 Mode Configuration Register */
+ ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */
+
+ ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_0044_C[4];
+ union {
+ /* ME_STOP0_MC - STOP0 Mode Configration Register */
+ ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */
+
+ ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_004C_C[8];
+ union {
+ /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
+ ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */
+
+ ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_0058_C[8];
+ union {
+ ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */
+
+ struct {
+ /* ME_PS0 - Peripheral Status Register 0 */
+ ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */
+ /* ME_PS1 - Peripheral Status Register 1 */
+ ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */
+ /* ME_PS2 - Peripheral Status Register 2 */
+ ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */
+ };
+
+ };
+ int8_t ME_reserved_006C_C[20];
+ union {
+ ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
+ ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ struct {
+ /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
+ ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */
+ };
+
+ };
+ union {
+ ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
+ ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ struct {
+ /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
+ ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */
+ };
+
+ };
+ union {
+ /* ME_PCTL[0...143] - Peripheral Control Registers */
+ ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */
+
+ struct {
+ /* ME_PCTL[0...143] - Peripheral Control Registers */
+ ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */
+ ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */
+ ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */
+ ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */
+ ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */
+ ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */
+ ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */
+ ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */
+ ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */
+ ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */
+ ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */
+ ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */
+ ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */
+ ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */
+ ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */
+ ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */
+ ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */
+ ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */
+ ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */
+ ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */
+ ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */
+ ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */
+ ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */
+ ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */
+ ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */
+ ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */
+ ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */
+ ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */
+ ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */
+ ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */
+ ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */
+ ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */
+ ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */
+ ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */
+ ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */
+ ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */
+ ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */
+ ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */
+ ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */
+ ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */
+ ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */
+ ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */
+ ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */
+ ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */
+ ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */
+ ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */
+ ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */
+ ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */
+ ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */
+ ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */
+ ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */
+ ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */
+ ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */
+ ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */
+ ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */
+ ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */
+ ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */
+ ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */
+ ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */
+ ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */
+ ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */
+ ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */
+ ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */
+ ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */
+ ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */
+ ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */
+ ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */
+ ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */
+ ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */
+ ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */
+ ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */
+ ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */
+ ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */
+ ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */
+ ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */
+ ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */
+ ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */
+ ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */
+ ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */
+ ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */
+ ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */
+ ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */
+ ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */
+ ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */
+ ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */
+ ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */
+ ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */
+ ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */
+ ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */
+ ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */
+ ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */
+ ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */
+ ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */
+ ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */
+ ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */
+ ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */
+ ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */
+ ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */
+ ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */
+ ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */
+ ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */
+ ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */
+ ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */
+ ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */
+ };
+
+ };
+ } ME_tag;
+
+
+#define ME (*(volatile ME_tag *) 0xC3FDC000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: OSC */
+/* */
+/****************************************************************/
+
+ typedef union { /* OSC_CTL - Control Register */
+ uint32_t R;
+ struct {
+ uint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */
+ uint32_t:7;
+ uint32_t EOCV:8; /* End of Count Value */
+ uint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */
+ uint32_t:2;
+ uint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */
+ uint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */
+ uint32_t:5;
+ uint32_t S_OSC:1;
+ uint32_t OSCON:1; } B;
+ } OSC_CTL_32B_tag;
+
+
+
+ typedef struct OSC_struct_tag { /* start of OSC_tag */
+ /* OSC_CTL - Control Register */
+ OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
+ } OSC_tag;
+
+
+#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: RC */
+/* */
+/****************************************************************/
+
+ typedef union { /* RC_CTL - Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:10;
+ uint32_t RCTRIM:6; /* Main RC Trimming Bits */
+ uint32_t:3;
+ uint32_t RCDIV:5; /* Main RC Clock Division Factor */
+ uint32_t:2;
+ uint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */
+ uint32_t:5;
+ } B;
+ } RC_CTL_32B_tag;
+
+
+
+ typedef struct RC_struct_tag { /* start of RC_tag */
+ /* RC_CTL - Control Register */
+ RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
+ } RC_tag;
+
+
+#define RC (*(volatile RC_tag *) 0xC3FE0060UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PLLD */
+/* */
+/****************************************************************/
+
+ typedef union { /* PLLD_CR - Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:2;
+ uint32_t IDF:4; /* PLL Input Division Factor */
+ uint32_t ODF:2; /* PLL Output Division Factor */
+ uint32_t:1;
+ uint32_t NDIV:7; /* PLL Loop Division Factor */
+ uint32_t:7;
+ uint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */
+ uint32_t MODE:1; /* Activate 1:1 Mode */
+ uint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */
+ uint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */
+ uint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */
+ uint32_t S_LOCK:1; /* PLL has Aquired Lock */
+ uint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */
+ uint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */
+ uint32_t PLL_ON:1; /* PLL ON Bit */
+ } B;
+ } PLLD_CR_32B_tag;
+
+ typedef union { /* PLLD_MR - PLLD Modulation Register */
+ uint32_t R;
+ struct {
+ uint32_t STRB_BYPASS:1; /* Strobe Bypass */
+ uint32_t:1;
+ uint32_t SPRD_SEL:1; /* Spread Type Selection */
+ uint32_t MOD_PERIOD:13; /* Modulation Period */
+#ifndef USE_FIELD_ALIASES_PLLD
+ uint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */
+#else
+ uint32_t FM_EN:1; /* deprecated name - please avoid */
+#endif
+ uint32_t INC_STEP:15; /* Increment Step */
+ } B;
+ } PLLD_MR_32B_tag;
+
+
+
+ typedef struct PLLD_struct_tag { /* start of PLLD_tag */
+ /* PLLD_CR - Control Register */
+ PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
+ /* PLLD_MR - PLLD Modulation Register */
+ PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */
+
+ uint32_t plld_reserved[6];
+ } PLLD_tag;
+
+
+#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL)
+#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CMU */
+/* */
+/****************************************************************/
+
+ typedef union { /* CMU_CSR - Control Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:8;
+ uint32_t SFM:1; /* Start Frequency Measure */
+ uint32_t:13;
+#ifndef USE_FIELD_ALIASES_RGM
+ uint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */
+#else
+ uint32_t CLKSEL1:2; /* deprecated name - please avoid */
+#endif
+ uint32_t:5;
+ uint32_t RCDIV:2; /* RCfast Clock Division Factor */
+ uint32_t CME_A:1; /* PLL_A Clock Monitor Enable */
+ } B;
+ } CMU_CSR_32B_tag;
+
+ typedef union { /* CMU_FDR - Frequency Display Register */
+ uint32_t R;
+ struct {
+ uint32_t:12;
+ uint32_t FD:20; /* Measured Frequency Bits */
+ } B;
+ } CMU_FDR_32B_tag;
+
+ typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */
+ uint32_t R;
+ struct {
+ uint32_t:20;
+ uint32_t HFREF_A:12; /* High Frequency Reference Value */
+ } B;
+ } CMU_HFREFR_A_32B_tag;
+
+ typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */
+ uint32_t R;
+ struct {
+ uint32_t:20;
+ uint32_t LFREF_A:12; /* Low Frequency Reference Value */
+ } B;
+ } CMU_LFREFR_A_32B_tag;
+
+ typedef union { /* CMU_ISR - Interrupt Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */
+#else
+ uint32_t FHHI_A:1; /* deprecated name - please avoid */
+#endif
+ uint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */
+ uint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */
+ } B;
+ } CMU_ISR_32B_tag;
+
+ typedef union { /* CMU_IMR - Interrupt Mask Register */
+ uint32_t R;
+ } CMU_IMR_32B_tag;
+
+ typedef union { /* CMU_MDR - Measurement Duration Register */
+ uint32_t R;
+ struct {
+ uint32_t:12;
+ uint32_t MD:20; /* Measurment Duration Bits */
+ } B;
+ } CMU_MDR_32B_tag;
+
+
+
+ typedef struct CMU_struct_tag { /* start of CMU_tag */
+ /* CMU_CSR - Control Status Register */
+ CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */
+ /* CMU_FDR - Frequency Display Register */
+ CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */
+ /* CMU_HFREFR_A - High Frequency Reference Register */
+ CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */
+ /* CMU_LFREFR_A - Low Frequency Reference Register */
+ CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */
+ /* CMU_ISR - Interrupt Status Register */
+ CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
+ /* CMU_IMR - Interrupt Mask Register */
+ CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */
+ /* CMU_MDR - Measurement Duration Register */
+ CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */
+ } CMU_tag;
+
+
+#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL)
+#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL)
+#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CGM */
+/* */
+/****************************************************************/
+
+ typedef union { /* Output Clock Enable Register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ struct {
+ uint32_t:31;
+ uint32_t EN:1; /* Clock Enable Bit */
+ } B;
+ } CGM_OC_EN_32B_tag;
+
+ typedef union { /* Output Clock Division Select Register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ struct {
+ uint32_t:2;
+ uint32_t SELDIV:2; /* Output Clock Division Select */
+ uint32_t SELCTL:4; /* Output Clock Source Selection Control */
+ uint32_t:24;
+ } B;
+ } CGM_OCDS_SC_32B_tag;
+
+ typedef union { /* System Clock Select Status Register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ struct {
+ uint32_t:4;
+ uint32_t SELSTAT:4; /* System Clock Source Selection Status */
+ uint32_t:24;
+ } B;
+ } CGM_SC_SS_32B_tag;
+
+ typedef union { /* System Clock Divider Configuration Register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ struct {
+ uint32_t DE0:1; /* Divider 0 Enable */
+ uint32_t:3;
+ uint32_t DIV0:4; /* Divider 0 Value */
+ uint32_t:24;
+ } B;
+ } CGM_SC_DC0_3_32B_tag;
+
+
+ /* Register layout for all registers SC_DC... */
+
+ typedef union { /* System Clock Divider Configuration Register */
+ uint8_t R;
+ struct {
+ uint8_t DE:1; /* Divider Enable */
+ uint8_t:3;
+ uint8_t DIV:4; /* Divider Division Value */
+ } B;
+ } CGM_SC_DC_8B_tag;
+
+
+ /* Register layout for all registers AC_SC... */
+
+ typedef union { /* Auxiliary Clock Select Control Registers */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ struct {
+ uint32_t:4;
+ uint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */
+ uint32_t:24;
+ } B;
+ } CGM_AC_SC_32B_tag;
+
+
+ /* Register layout for all registers AC_DC0_3... */
+
+ typedef union { /* Auxiliary Clock Divider Configuration Registers */
+ uint32_t R;
+ struct {
+ uint32_t DE0:1; /* Divider 0 Enable */
+ uint32_t:3;
+ uint32_t DIV0:4; /* Divider 0 Value */
+ uint32_t DE1:1; /* Divider 1 Enable */
+ uint32_t:3;
+ uint32_t DIV1:4; /* Divider 1 Value */
+ uint32_t:16;
+ } B;
+ } CGM_AC_DC0_3_32B_tag;
+
+
+ typedef struct CGM_AUXCLK_struct_tag {
+
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */
+
+ } CGM_AUXCLK_tag;
+
+
+ typedef struct CGM_struct_tag { /* start of CGM_tag */
+ OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */
+ int8_t CGM_reserved_0004[92];
+ RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */
+ int8_t CGM_reserved_0064[60];
+ PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */
+ int8_t CGM_reserved_00E0[32];
+ CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */
+ CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */
+ CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */
+ CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */
+ CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */
+ CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */
+ CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */
+ int8_t CGM_reserved_011C[4];
+ CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */
+ int8_t CGM_reserved_0124[4];
+ CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */
+ CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */
+ CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */
+ int8_t CGM_reserved_0134[572];
+ union {
+ /* Output Clock Enable Register */
+ CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */
+
+ CGM_OC_EN_32B_tag OCEN; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Output Clock Division Select Register */
+ CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */
+
+ CGM_OCDS_SC_32B_tag OCDSSC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Output Clock Division Select Register */
+ CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */
+
+ CGM_SC_SS_32B_tag SCSS; /* deprecated - please avoid */
+
+ }; /* System Clock Select Status Register */
+ union {
+ struct {
+ /* System Clock Divider Configuration Register */
+ CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */
+ int8_t CGM_reserved_037E_E0[2];
+ };
+
+ struct {
+ /* System Clock Divider Configuration Register */
+ CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */
+ CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */
+ int8_t CGM_reserved_037E_E1[2];
+ };
+
+ /* System Clock Divider Configuration Register */
+ union {
+ CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */
+ CGM_SC_DC0_3_32B_tag SCDC; /* deprecated - please avoid */
+ };
+ };
+ union {
+ /* Register set AUXCLK */
+ CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */
+
+ struct {
+ union {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */
+
+ CGM_AC_SC_32B_tag AC0SC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */
+
+ CGM_AC_DC0_3_32B_tag AC0DC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */
+
+ CGM_AC_SC_32B_tag AC1SC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */
+
+ CGM_AC_DC0_3_32B_tag AC1DC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */
+
+ CGM_AC_SC_32B_tag AC2SC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */
+
+ CGM_AC_DC0_3_32B_tag AC2DC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */
+
+ CGM_AC_SC_32B_tag AC3SC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */
+
+ CGM_AC_DC0_3_32B_tag AC3DC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */
+
+ CGM_AC_SC_32B_tag AC4SC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */
+
+ CGM_AC_DC0_3_32B_tag AC4DC; /* deprecated - please avoid */
+ };
+ union {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */
+
+ CGM_AC_SC_32B_tag AC5SC; /* deprecated - please avoid */
+
+ };
+ union {
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */
+
+ CGM_AC_DC0_3_32B_tag AC5DC; /* deprecated - please avoid */
+
+ };
+ };
+
+ };
+ } CGM_tag;
+
+
+#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: RGM */
+/* */
+/****************************************************************/
+
+ typedef union { /* Functional Event Status Register */
+ uint16_t R;
+ struct {
+ uint16_t F_EXR:1; /* Flag for External Reset */
+ uint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */
+ uint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */
+ uint16_t F_ST_DONE:1; /* Flag for self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */
+#else
+ uint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ uint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */
+ uint16_t F_PLL1:1; /* Flag for PLL1 fail */
+ uint16_t F_SWT:1; /* Flag for Software Watchdog Timer */
+ uint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */
+ uint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */
+ uint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */
+ uint16_t F_PLL0:1; /* Flag for PLL0 fail */
+ uint16_t F_CWD:1; /* Flag for Core Watchdog Reset */
+ uint16_t F_SOFT:1; /* Flag for software reset */
+ uint16_t F_CORE:1; /* Flag for core reset */
+ uint16_t F_JTAG:1; /* Flag for JTAG initiated reset */
+ } B;
+ } RGM_FES_16B_tag;
+
+ typedef union { /* Destructive Event Status Register */
+ uint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t F_POR:1; /* Flag for Power on Reset */
+#else
+ uint16_t POR:1; /* deprecated name - please avoid */
+#endif
+ uint16_t:7;
+ uint16_t F_COMP:1; /* Flag for comparator error */
+ uint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */
+ uint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */
+ uint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */
+ uint16_t:2;
+ uint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */
+#else
+ uint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } RGM_DES_16B_tag;
+
+ typedef union { /* Functional Event Reset Disable Register */
+ uint16_t R;
+ struct {
+ uint16_t D_EXR:1; /* Disable External Pad Event Reset */
+ uint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */
+ uint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */
+ uint16_t D_ST_DONE:1; /* Disable self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */
+#else
+ uint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ uint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */
+ uint16_t D_PLL1:1; /* Disable PLL1 fail */
+ uint16_t D_SWT:1; /* Disable Software Watchdog Timer */
+ uint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */
+ uint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */
+ uint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */
+ uint16_t D_PLL0:1; /* Disable PLL0 fail */
+ uint16_t D_CWD:1; /* Disable Core Watchdog Reset */
+ uint16_t D_SOFT:1; /* Disable software reset */
+ uint16_t D_CORE:1; /* Disable core reset */
+ uint16_t D_JTAG:1; /* Disable JTAG initiated reset */
+ } B;
+ } RGM_FERD_16B_tag;
+
+ typedef union { /* Destructive Event Reset Disable Register */
+ uint16_t R;
+ struct {
+ uint16_t:8;
+ uint16_t D_COMP:1; /* Disable comparator error */
+ uint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */
+ uint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */
+ uint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */
+ uint16_t:2;
+ uint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */
+#else
+ uint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } RGM_DERD_16B_tag;
+
+ typedef union { /* Functional Event Alternate Request Register */
+ uint16_t R;
+ struct {
+ uint16_t:4;
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */
+#else
+ uint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ uint16_t:1;
+ uint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */
+ uint16_t:1;
+ uint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */
+ uint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq.
+ too high/low */
+ uint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */
+ uint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */
+ uint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */
+ uint16_t:3;
+ } B;
+ } RGM_FEAR_16B_tag;
+
+ typedef union { /* Functional Event Short Sequence Register */
+ uint16_t R;
+ struct {
+ uint16_t SS_EXR:1; /* Short Sequence for External Reset */
+ uint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */
+ uint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */
+ uint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */
+#else
+ uint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ uint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */
+ uint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */
+ uint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */
+ uint16_t:1;
+ uint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */
+ uint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */
+ uint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */
+ uint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */
+ uint16_t SS_SOFT:1; /* Short Sequence for software reset */
+ uint16_t SS_CORE:1; /* Short Sequence for core reset */
+ uint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */
+ } B;
+ } RGM_FESS_16B_tag;
+
+ typedef union { /* Functional Bidirectional Reset Enable Register */
+ uint16_t R;
+ struct {
+ uint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */
+ uint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */
+ uint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */
+ uint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ uint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */
+#else
+ uint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ uint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */
+ uint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */
+ uint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */
+ uint16_t:1;
+ uint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */
+ uint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */
+ uint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */
+ uint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */
+ uint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */
+ uint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */
+ uint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */
+ } B;
+ } RGM_FBRE_16B_tag;
+
+
+
+ typedef struct RGM_struct_tag { /* start of RGM_tag */
+ /* Functional Event Status Register */
+ RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */
+ /* Destructive Event Status Register */
+ RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */
+ /* Functional Event Reset Disable Register */
+ RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */
+ /* Destructive Event Reset Disable Register */
+ RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */
+ int8_t RGM_reserved_0008[8];
+ /* Functional Event Alternate Request Register */
+ RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */
+ int8_t RGM_reserved_0012[6];
+ /* Functional Event Short Sequence Register */
+ RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */
+ int8_t RGM_reserved_001A[2];
+ /* Functional Bidirectional Reset Enable Register */
+ RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */
+ } RGM_tag;
+
+
+#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PCU */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers PCONF... */
+
+ typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:18;
+ uint32_t STBY0:1; /* Power domain control during STBY0 */
+ uint32_t:2;
+ uint32_t STOP0:1; /* Power domain control during STOP0 */
+ uint32_t:1;
+ uint32_t HALT0:1; /* Power domain control during HALT0 */
+ uint32_t RUN3:1; /* Power domain control during RUN3 */
+ uint32_t RUN2:1; /* Power domain control during RUN2 */
+ uint32_t RUN1:1; /* Power domain control during RUN1 */
+ uint32_t RUN0:1; /* Power domain control during RUN0 */
+ uint32_t DRUN:1; /* Power domain control during DRUN */
+ uint32_t SAFE:1; /* Power domain control during SAFE */
+ uint32_t TEST:1; /* Power domain control during TEST */
+ uint32_t RST:1; /* Power domain control during RST */
+ } B;
+ } PCU_PCONF_32B_tag;
+
+ typedef union { /* PCU_PSTAT - Power Domain Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t PD15:1; /* Power Status for Power Domain 15 */
+ uint32_t PD14:1; /* Power Status for Power Domain 14 */
+ uint32_t PD13:1; /* Power Status for Power Domain 13 */
+ uint32_t PD12:1; /* Power Status for Power Domain 12 */
+ uint32_t PD11:1; /* Power Status for Power Domain 11 */
+ uint32_t PD10:1; /* Power Status for Power Domain 10 */
+ uint32_t PD9:1; /* Power Status for Power Domain 9 */
+ uint32_t PD8:1; /* Power Status for Power Domain 8 */
+ uint32_t PD7:1; /* Power Status for Power Domain 7 */
+ uint32_t PD6:1; /* Power Status for Power Domain 6 */
+ uint32_t PD5:1; /* Power Status for Power Domain 5 */
+ uint32_t PD4:1; /* Power Status for Power Domain 4 */
+ uint32_t PD3:1; /* Power Status for Power Domain 3 */
+ uint32_t PD2:1; /* Power Status for Power Domain 2 */
+ uint32_t PD1:1; /* Power Status for Power Domain 1 */
+ uint32_t PD0:1; /* Power Status for Power Domain 0 */
+ } B;
+ } PCU_PSTAT_32B_tag;
+
+
+
+ typedef struct PCU_struct_tag { /* start of PCU_tag */
+ union {
+ /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
+ PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */
+
+ struct {
+ /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
+ PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */
+ PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */
+ PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */
+ PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */
+ };
+
+ };
+ /* PCU_PSTAT - Power Domain Status Register */
+ PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */
+ } PCU_tag;
+
+
+#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PMUCTRL */
+/* */
+/****************************************************************/
+
+ typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */
+ uint32_t R;
+ struct {
+ uint32_t:11;
+ uint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */
+ uint32_t:6;
+ uint32_t HVD_M:1; /* High Voltage Detector Main */
+ uint32_t HVD_B:1; /* High Voltage Detector Backup */
+ uint32_t:4;
+ uint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */
+ } B;
+ } PMUCTRL_STATHVD_32B_tag;
+
+ typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */
+ uint32_t R;
+ struct {
+ uint32_t:11;
+ uint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */
+ uint32_t:6;
+ uint32_t LVD_M:1; /* Ligh Voltage Detector Main */
+ uint32_t LVD_B:1; /* Ligh Voltage Detector Backup */
+ uint32_t:4;
+ uint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */
+ } B;
+ } PMUCTRL_STATLVD_32B_tag;
+
+ typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
+ } B;
+ } PMUCTRL_STATIREG_32B_tag;
+
+ typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
+ } B;
+ } PMUCTRL_STATEREG_32B_tag;
+
+ typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */
+ uint32_t R;
+ struct {
+ uint32_t EBMM:1; /* External Ballast Management Mode */
+ uint32_t AEBD:1; /* Automatic External Ballast Detection */
+ uint32_t ENPN:1; /* External NPN status flag */
+ uint32_t:13;
+ uint32_t CTB:2; /* Configuration Trace Bits */
+ uint32_t:6;
+ uint32_t CBS:4; /* Current BIST Status */
+ uint32_t CPCS:4; /* Current Pmu Configuration Status */
+ } B;
+ } PMUCTRL_STATUS_32B_tag;
+
+ typedef union { /* PMUCTRL_CTRL - PMU Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:30;
+ uint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */
+ } B;
+ } PMUCTRL_CTRL_32B_tag;
+
+ typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */
+ uint32_t R;
+ struct {
+ uint32_t MF_BB:4; /* Mask Fault Bypass Balast */
+ uint32_t:28;
+ } B;
+ } PMUCTRL_MASKF_32B_tag;
+
+ typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */
+ uint32_t R;
+ struct {
+ uint32_t BB_LV:4; /* Bypass Ballast Low Voltage */
+ uint32_t:9;
+ uint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */
+ uint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */
+ uint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */
+ uint32_t:13;
+ uint32_t LHCF:1; /* Low High voltage detector Critical Fault */
+ uint32_t LNCF:1; /* Low voltage detector Non Critical Fault */
+ uint32_t HNCF:1; /* High voltage detector Non Critical Fault */
+ } B;
+ } PMUCTRL_FAULT_32B_tag;
+
+ typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:10;
+ uint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */
+ uint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */
+ uint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */
+ uint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */
+ uint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */
+ uint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */
+ uint32_t:12;
+ uint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */
+ uint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */
+ uint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */
+ uint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */
+ } B;
+ } PMUCTRL_IRQS_32B_tag;
+
+ typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:10;
+ uint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */
+ uint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */
+ uint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */
+ uint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */
+ uint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */
+ uint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */
+ uint32_t:12;
+ uint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */
+ uint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */
+ uint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */
+ uint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */
+ } B;
+ } PMUCTRL_IRQE_32B_tag;
+
+
+
+ typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */
+ int8_t PMUCTRL_reserved_0000[4];
+ /* PMUCTRL_STATHVD - PMU Status Register HVD */
+ PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */
+ /* PMUCTRL_STATLVD - PMU Status Register LVD */
+ PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */
+ int8_t PMUCTRL_reserved_000C[20];
+ /* PMUCTRL_STATIREG - PMU Status Register IREG */
+ PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */
+ /* PMUCTRL_STATEREG - PMU Status Register EREG */
+ PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */
+ int8_t PMUCTRL_reserved_0028[24];
+ /* PMUCTRL_STATUS - PMU Status Register STATUS */
+ PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */
+ /* PMUCTRL_CTRL - PMU Control Register */
+ PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */
+ int8_t PMUCTRL_reserved_0048[40];
+ /* PMUCTRL_MASKF - PMU Mask Fault Register */
+ PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */
+ /* PMUCTRL_FAULT - PMU Fault Monitor Register */
+ PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */
+ /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
+ PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */
+ /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
+ PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */
+ } PMUCTRL_tag;
+
+
+#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PIT_RTI */
+/* */
+/****************************************************************/
+
+ typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:30;
+ uint32_t MDIS:1; /* Module Disable. Disable the module clock */
+ uint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */
+ } B;
+ } PIT_RTI_PITMCR_32B_tag;
+
+
+ /* Register layout for all registers LDVAL... */
+
+ typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */
+ uint32_t R;
+ struct {
+ uint32_t TSV:32; /* Time Start Value Bits */
+ } B;
+ } PIT_RTI_LDVAL_32B_tag;
+
+
+ /* Register layout for all registers CVAL... */
+
+ typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */
+ uint32_t R;
+ struct {
+ uint32_t TVL:32; /* Current Timer Value Bits */
+ } B;
+ } PIT_RTI_CVAL_32B_tag;
+
+
+ /* Register layout for all registers TCTRL... */
+
+ typedef union { /* PIT_RTI_TCTRL - Timer Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:30;
+ uint32_t TIE:1; /* Timer Interrupt Enable Bit */
+ uint32_t TEN:1; /* Timer Enable Bit */
+ } B;
+ } PIT_RTI_TCTRL_32B_tag;
+
+
+ /* Register layout for all registers TFLG... */
+
+ typedef union { /* PIT_RTI_TFLG - Timer Flag Register */
+ uint32_t R;
+ struct {
+ uint32_t:31;
+ uint32_t TIF:1; /* Timer Interrupt Flag Bit */
+ } B;
+ } PIT_RTI_TFLG_32B_tag;
+
+
+ typedef struct PIT_RTI_CHANNEL_struct_tag {
+
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */
+
+ } PIT_RTI_CHANNEL_tag;
+
+
+ typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */
+ /* PIT_RTI_PITMCR - PIT Module Control Register */
+ PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */
+ int8_t PIT_RTI_reserved_0004_C[252];
+ union {
+ /* Register set CHANNEL */
+ PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */
+
+ PIT_RTI_CHANNEL_tag CH[4]; /* offset: 0x0100 (0x0010 x 4) */
+
+ struct {
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */
+ };
+
+ };
+ } PIT_RTI_tag;
+
+
+#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: ADC */
+/* */
+/****************************************************************/
+
+ typedef union { /* module configuration register */
+ uint32_t R;
+ struct {
+ uint32_t OWREN:1; /* Overwrite enable */
+ uint32_t WLSIDE:1; /* Write Left/right Alligned */
+ uint32_t MODE:1; /* One Shot/Scan Mode Selectiom */
+ uint32_t EDGLEV:1; /* edge or level selection for external start trigger */
+ uint32_t TRGEN:1; /* external trigger enable */
+ uint32_t EDGE:1; /* start trigger egde /level detection */
+ uint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */
+ uint32_t NSTART:1; /* start normal conversion */
+ uint32_t:1;
+ uint32_t JTRGEN:1; /* Injectin External Trigger Enable */
+ uint32_t JEDGE:1; /* start trigger egde /level detection for injected */
+ uint32_t JSTART:1; /* injected conversion start */
+ uint32_t:2;
+ uint32_t CTUEN:1; /* CTU enabaled */
+ uint32_t:8;
+ uint32_t ADCLKSEL:1; /* Select which clock for device */
+ uint32_t ABORTCHAIN:1; /* abort chain conversion */
+ uint32_t ABORT:1; /* abort current conversion */
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t ACKO:1; /* Auto Clock Off Enable */
+#else
+ uint32_t ACK0:1; /* deprecated name - please avoid */
+#endif
+ uint32_t OFFREFRESH:1; /* offset phase selection */
+ uint32_t OFFCANC:1; /* offset phase cancellation selection */
+ uint32_t:2;
+ uint32_t PWDN:1; /* Power Down Enable */
+ } B;
+ } ADC_MCR_32B_tag;
+
+ typedef union { /* module status register */
+ uint32_t R;
+ struct {
+ uint32_t:7;
+ uint32_t NSTART:1; /* normal conversion status */
+ uint32_t JABORT:1; /* Injection chain abort status */
+ uint32_t:2;
+ uint32_t JSTART:1; /* Injection Start status */
+ uint32_t:3;
+ uint32_t CTUSTART:1; /* ctu start status */
+ uint32_t CHADDR:7; /* which address conv is goin on */
+ uint32_t:3;
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t ACKO:1; /* Auto Clock Off Enable status */
+#else
+ uint32_t ACK0:1; /* deprecated name - please avoid */
+#endif
+ uint32_t OFFREFRESH:1; /* offset refresh status */
+ uint32_t OFFCANC:1; /* offset phase cancellation status */
+ uint32_t ADCSTATUS:3; /* status of ADC FSM */
+ } B;
+ } ADC_MSR_32B_tag;
+
+ typedef union { /* Interrupt status register */
+ uint32_t R;
+ struct {
+ uint32_t:25;
+ uint32_t OFFCANCOVR:1; /* Offset cancellation phase over */
+ uint32_t EOFFSET:1; /* error in offset refresh */
+ uint32_t EOCTU:1; /* end of CTU channel conversion */
+ uint32_t JEOC:1; /* end of injected channel conversion */
+ uint32_t JECH:1; /* end ofinjected chain conversion */
+ uint32_t EOC:1; /* end of channel conversion */
+ uint32_t ECH:1; /* end of chain conversion */
+ } B;
+ } ADC_ISR_32B_tag;
+
+ typedef union { /* CHANNEL PENDING REGISTER 0 */
+ uint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH31:1; /* Channel 31 conversion over */
+#else
+ uint32_t EOC31:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH30:1; /* Channel 30 conversion over */
+#else
+ uint32_t EOC30:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH29:1; /* Channel 29 conversion over */
+#else
+ uint32_t EOC29:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH28:1; /* Channel 28 conversion over */
+#else
+ uint32_t EOC28:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH27:1; /* Channel 27 conversion over */
+#else
+ uint32_t EOC27:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH26:1; /* Channel 26 conversion over */
+#else
+ uint32_t EOC26:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH25:1; /* Channel 25 conversion over */
+#else
+ uint32_t EOC25:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH24:1; /* Channel 24 conversion over */
+#else
+ uint32_t EOC24:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH23:1; /* Channel 23 conversion over */
+#else
+ uint32_t EOC23:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH22:1; /* Channel 22 conversion over */
+#else
+ uint32_t EOC22:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH21:1; /* Channel 21 conversion over */
+#else
+ uint32_t EOC21:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH20:1; /* Channel 20 conversion over */
+#else
+ uint32_t EOC20:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH19:1; /* Channel 19 conversion over */
+#else
+ uint32_t EOC19:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH18:1; /* Channel 18 conversion over */
+#else
+ uint32_t EOC18:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH17:1; /* Channel 17 conversion over */
+#else
+ uint32_t EOC17:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH16:1; /* Channel 16 conversion over */
+#else
+ uint32_t EOC16:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH15:1; /* Channel 15 conversion over */
+#else
+ uint32_t EOC15:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH14:1; /* Channel 14 conversion over */
+#else
+ uint32_t EOC14:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH13:1; /* Channel 13 conversion over */
+#else
+ uint32_t EOC13:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH12:1; /* Channel 12 conversion over */
+#else
+ uint32_t EOC12:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH11:1; /* Channel 11 conversion over */
+#else
+ uint32_t EOC11:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH10:1; /* Channel 10 conversion over */
+#else
+ uint32_t EOC10:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH9:1; /* Channel 9 conversion over */
+#else
+ uint32_t EOC9:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH8:1; /* Channel 8 conversion over */
+#else
+ uint32_t EOC8:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH7:1; /* Channel 7 conversion over */
+#else
+ uint32_t EOC7:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH6:1; /* Channel 6 conversion over */
+#else
+ uint32_t EOC6:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH5:1; /* Channel 5 conversion over */
+#else
+ uint32_t EOC5:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH4:1; /* Channel 4 conversion over */
+#else
+ uint32_t EOC4:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH3:1; /* Channel 3 conversion over */
+#else
+ uint32_t EOC3:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH2:1; /* Channel 2 conversion over */
+#else
+ uint32_t EOC2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH1:1; /* Channel 1 conversion over */
+#else
+ uint32_t EOC1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t EOC_CH0:1; /* Channel 0 conversion over */
+#else
+ uint32_t EOC0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ADC_CEOCFR0_32B_tag;
+
+ typedef union { /* CHANNEL PENDING REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t EOC_CH63:1; /* Channel 63 conversion over */
+ uint32_t EOC_CH62:1; /* Channel 62 conversion over */
+ uint32_t EOC_CH61:1; /* Channel 61 conversion over */
+ uint32_t EOC_CH60:1; /* Channel 60 conversion over */
+ uint32_t EOC_CH59:1; /* Channel 59 conversion over */
+ uint32_t EOC_CH58:1; /* Channel 58 conversion over */
+ uint32_t EOC_CH57:1; /* Channel 57 conversion over */
+ uint32_t EOC_CH56:1; /* Channel 56 conversion over */
+ uint32_t EOC_CH55:1; /* Channel 55 conversion over */
+ uint32_t EOC_CH54:1; /* Channel 54 conversion over */
+ uint32_t EOC_CH53:1; /* Channel 53 conversion over */
+ uint32_t EOC_CH52:1; /* Channel 52 conversion over */
+ uint32_t EOC_CH51:1; /* Channel 51 conversion over */
+ uint32_t EOC_CH50:1; /* Channel 50 conversion over */
+ uint32_t EOC_CH49:1; /* Channel 49 conversion over */
+ uint32_t EOC_CH48:1; /* Channel 48 conversion over */
+ uint32_t EOC_CH47:1; /* Channel 47 conversion over */
+ uint32_t EOC_CH46:1; /* Channel 46 conversion over */
+ uint32_t EOC_CH45:1; /* Channel 45 conversion over */
+ uint32_t EOC_CH44:1; /* Channel 44 conversion over */
+ uint32_t EOC_CH43:1; /* Channel 43 conversion over */
+ uint32_t EOC_CH42:1; /* Channel 42 conversion over */
+ uint32_t EOC_CH41:1; /* Channel 41 conversion over */
+ uint32_t EOC_CH40:1; /* Channel 40 conversion over */
+ uint32_t EOC_CH39:1; /* Channel 39 conversion over */
+ uint32_t EOC_CH38:1; /* Channel 38 conversion over */
+ uint32_t EOC_CH37:1; /* Channel 37 conversion over */
+ uint32_t EOC_CH36:1; /* Channel 36 conversion over */
+ uint32_t EOC_CH35:1; /* Channel 35 conversion over */
+ uint32_t EOC_CH34:1; /* Channel 34 conversion over */
+ uint32_t EOC_CH33:1; /* Channel 33 conversion over */
+ uint32_t EOC_CH32:1; /* Channel 32 conversion over */
+ } B;
+ } ADC_CEOCFR1_32B_tag;
+
+ typedef union { /* CHANNEL PENDING REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t EOC_CH95:1; /* Channel 95 conversion over */
+ uint32_t EOC_CH94:1; /* Channel 94 conversion over */
+ uint32_t EOC_CH93:1; /* Channel 93 conversion over */
+ uint32_t EOC_CH92:1; /* Channel 92 conversion over */
+ uint32_t EOC_CH91:1; /* Channel 91 conversion over */
+ uint32_t EOC_CH90:1; /* Channel 90 conversion over */
+ uint32_t EOC_CH89:1; /* Channel 89 conversion over */
+ uint32_t EOC_CH88:1; /* Channel 88 conversion over */
+ uint32_t EOC_CH87:1; /* Channel 87 conversion over */
+ uint32_t EOC_CH86:1; /* Channel 86 conversion over */
+ uint32_t EOC_CH85:1; /* Channel 85 conversion over */
+ uint32_t EOC_CH84:1; /* Channel 84 conversion over */
+ uint32_t EOC_CH83:1; /* Channel 83 conversion over */
+ uint32_t EOC_CH82:1; /* Channel 82 conversion over */
+ uint32_t EOC_CH81:1; /* Channel 81 conversion over */
+ uint32_t EOC_CH80:1; /* Channel 80 conversion over */
+ uint32_t EOC_CH79:1; /* Channel 79 conversion over */
+ uint32_t EOC_CH78:1; /* Channel 78 conversion over */
+ uint32_t EOC_CH77:1; /* Channel 77 conversion over */
+ uint32_t EOC_CH76:1; /* Channel 76 conversion over */
+ uint32_t EOC_CH75:1; /* Channel 75 conversion over */
+ uint32_t EOC_CH74:1; /* Channel 74 conversion over */
+ uint32_t EOC_CH73:1; /* Channel 73 conversion over */
+ uint32_t EOC_CH72:1; /* Channel 72 conversion over */
+ uint32_t EOC_CH71:1; /* Channel 71 conversion over */
+ uint32_t EOC_CH70:1; /* Channel 70 conversion over */
+ uint32_t EOC_CH69:1; /* Channel 69 conversion over */
+ uint32_t EOC_CH68:1; /* Channel 68 conversion over */
+ uint32_t EOC_CH67:1; /* Channel 67 conversion over */
+ uint32_t EOC_CH66:1; /* Channel 66 conversion over */
+ uint32_t EOC_CH65:1; /* Channel 65 conversion over */
+ uint32_t EOC_CH64:1; /* Channel 64 conversion over */
+ } B;
+ } ADC_CEOCFR2_32B_tag;
+
+ typedef union { /* interrupt mask register */
+ uint32_t R;
+ struct {
+ uint32_t:25;
+ uint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */
+ uint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */
+ uint32_t MSKEOCTU:1; /* mask bit for EOCTU */
+ uint32_t MSKJEOC:1; /* mask bit for JEOC */
+ uint32_t MSKJECH:1; /* mask bit for JECH */
+ uint32_t MSKEOC:1; /* mask bit for EOC */
+ uint32_t MSKECH:1; /* mask bit for ECH */
+ } B;
+ } ADC_IMR_32B_tag;
+
+ typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */
+ uint32_t R;
+ struct {
+ uint32_t CIM31:1; /* Channel 31 mask register */
+ uint32_t CIM30:1; /* Channel 30 mask register */
+ uint32_t CIM29:1; /* Channel 29 mask register */
+ uint32_t CIM28:1; /* Channel 28 mask register */
+ uint32_t CIM27:1; /* Channel 27 mask register */
+ uint32_t CIM26:1; /* Channel 26 mask register */
+ uint32_t CIM25:1; /* Channel 25 mask register */
+ uint32_t CIM24:1; /* Channel 24 mask register */
+ uint32_t CIM23:1; /* Channel 23 mask register */
+ uint32_t CIM22:1; /* Channel 22 mask register */
+ uint32_t CIM21:1; /* Channel 21 mask register */
+ uint32_t CIM20:1; /* Channel 20 mask register */
+ uint32_t CIM19:1; /* Channel 19 mask register */
+ uint32_t CIM18:1; /* Channel 18 mask register */
+ uint32_t CIM17:1; /* Channel 17 mask register */
+ uint32_t CIM16:1; /* Channel 16 mask register */
+ uint32_t CIM15:1; /* Channel 15 mask register */
+ uint32_t CIM14:1; /* Channel 14 mask register */
+ uint32_t CIM13:1; /* Channel 13 mask register */
+ uint32_t CIM12:1; /* Channel 12 mask register */
+ uint32_t CIM11:1; /* Channel 11 mask register */
+ uint32_t CIM10:1; /* Channel 10 mask register */
+ uint32_t CIM9:1; /* Channel 9 mask register */
+ uint32_t CIM8:1; /* Channel 8 mask register */
+ uint32_t CIM7:1; /* Channel 7 mask register */
+ uint32_t CIM6:1; /* Channel 6 mask register */
+ uint32_t CIM5:1; /* Channel 5 mask register */
+ uint32_t CIM4:1; /* Channel 4 mask register */
+ uint32_t CIM3:1; /* Channel 3 mask register */
+ uint32_t CIM2:1; /* Channel 2 mask register */
+ uint32_t CIM1:1; /* Channel 1 mask register */
+ uint32_t CIM0:1; /* Channel 0 mask register */
+ } B;
+ } ADC_CIMR0_32B_tag;
+
+ typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t CIM63:1; /* Channel 63 mask register */
+ uint32_t CIM62:1; /* Channel 62 mask register */
+ uint32_t CIM61:1; /* Channel 61 mask register */
+ uint32_t CIM60:1; /* Channel 60 mask register */
+ uint32_t CIM59:1; /* Channel 59 mask register */
+ uint32_t CIM58:1; /* Channel 58 mask register */
+ uint32_t CIM57:1; /* Channel 57 mask register */
+ uint32_t CIM56:1; /* Channel 56 mask register */
+ uint32_t CIM55:1; /* Channel 55 mask register */
+ uint32_t CIM54:1; /* Channel 54 mask register */
+ uint32_t CIM53:1; /* Channel 53 mask register */
+ uint32_t CIM52:1; /* Channel 52 mask register */
+ uint32_t CIM51:1; /* Channel 51 mask register */
+ uint32_t CIM50:1; /* Channel 50 mask register */
+ uint32_t CIM49:1; /* Channel 49 mask register */
+ uint32_t CIM48:1; /* Channel 48 mask register */
+ uint32_t CIM47:1; /* Channel 47 mask register */
+ uint32_t CIM46:1; /* Channel 46 mask register */
+ uint32_t CIM45:1; /* Channel 45 mask register */
+ uint32_t CIM44:1; /* Channel 44 mask register */
+ uint32_t CIM43:1; /* Channel 43 mask register */
+ uint32_t CIM42:1; /* Channel 42 mask register */
+ uint32_t CIM41:1; /* Channel 41 mask register */
+ uint32_t CIM40:1; /* Channel 40 mask register */
+ uint32_t CIM39:1; /* Channel 39 mask register */
+ uint32_t CIM38:1; /* Channel 38 mask register */
+ uint32_t CIM37:1; /* Channel 37 mask register */
+ uint32_t CIM36:1; /* Channel 36 mask register */
+ uint32_t CIM35:1; /* Channel 35 mask register */
+ uint32_t CIM34:1; /* Channel 34 mask register */
+ uint32_t CIM33:1; /* Channel 33 mask register */
+ uint32_t CIM32:1; /* Channel 32 mask register */
+ } B;
+ } ADC_CIMR1_32B_tag;
+
+ typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t CIM95:1; /* Channel 95 mask register */
+ uint32_t CIM94:1; /* Channel 94 mask register */
+ uint32_t CIM93:1; /* Channel 93 mask register */
+ uint32_t CIM92:1; /* Channel 92 mask register */
+ uint32_t CIM91:1; /* Channel 91 mask register */
+ uint32_t CIM90:1; /* Channel 90 mask register */
+ uint32_t CIM89:1; /* Channel 89 mask register */
+ uint32_t CIM88:1; /* Channel 88 mask register */
+ uint32_t CIM87:1; /* Channel 87 mask register */
+ uint32_t CIM86:1; /* Channel 86 mask register */
+ uint32_t CIM85:1; /* Channel 85 mask register */
+ uint32_t CIM84:1; /* Channel 84 mask register */
+ uint32_t CIM83:1; /* Channel 83 mask register */
+ uint32_t CIM82:1; /* Channel 82 mask register */
+ uint32_t CIM81:1; /* Channel 81 mask register */
+ uint32_t CIM80:1; /* Channel 80 mask register */
+ uint32_t CIM79:1; /* Channel 79 mask register */
+ uint32_t CIM78:1; /* Channel 78 mask register */
+ uint32_t CIM77:1; /* Channel 77 mask register */
+ uint32_t CIM76:1; /* Channel 76 mask register */
+ uint32_t CIM75:1; /* Channel 75 mask register */
+ uint32_t CIM74:1; /* Channel 74 mask register */
+ uint32_t CIM73:1; /* Channel 73 mask register */
+ uint32_t CIM72:1; /* Channel 72 mask register */
+ uint32_t CIM71:1; /* Channel 71 mask register */
+ uint32_t CIM70:1; /* Channel 70 mask register */
+ uint32_t CIM69:1; /* Channel 69 mask register */
+ uint32_t CIM68:1; /* Channel 68 mask register */
+ uint32_t CIM67:1; /* Channel 67 mask register */
+ uint32_t CIM66:1; /* Channel 66 mask register */
+ uint32_t CIM65:1; /* Channel 65 mask register */
+ uint32_t CIM64:1; /* Channel 64 mask register */
+ } B;
+ } ADC_CIMR2_32B_tag;
+
+ typedef union { /* Watchdog Threshold interrupt status register */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */
+ uint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */
+ uint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */
+ uint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */
+ uint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */
+ uint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */
+ uint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */
+ uint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */
+ } B;
+ } ADC_WTISR_32B_tag;
+
+ typedef union { /* Watchdog interrupt MASK register */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */
+ uint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */
+ uint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */
+ uint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */
+ uint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */
+ uint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */
+ uint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */
+ uint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */
+ } B;
+ } ADC_WTIMR_32B_tag;
+
+ typedef union { /* DMAE register */
+ uint32_t R;
+ struct {
+ uint32_t:30;
+ uint32_t DCLR:1; /* DMA clear sequence enable */
+ uint32_t DMAEN:1; /* DMA global enable */
+ } B;
+ } ADC_DMAE_32B_tag;
+
+ typedef union { /* DMA REGISTER 0 */
+ uint32_t R;
+ struct {
+ uint32_t DMA31:1; /* Channel 31 DMA Enable */
+ uint32_t DMA30:1; /* Channel 30 DMA Enable */
+ uint32_t DMA29:1; /* Channel 29 DMA Enable */
+ uint32_t DMA28:1; /* Channel 28 DMA Enable */
+ uint32_t DMA27:1; /* Channel 27 DMA Enable */
+ uint32_t DMA26:1; /* Channel 26 DMA Enable */
+ uint32_t DMA25:1; /* Channel 25 DMA Enable */
+ uint32_t DMA24:1; /* Channel 24 DMA Enable */
+ uint32_t DMA23:1; /* Channel 23 DMA Enable */
+ uint32_t DMA22:1; /* Channel 22 DMA Enable */
+ uint32_t DMA21:1; /* Channel 21 DMA Enable */
+ uint32_t DMA20:1; /* Channel 20 DMA Enable */
+ uint32_t DMA19:1; /* Channel 19 DMA Enable */
+ uint32_t DMA18:1; /* Channel 18 DMA Enable */
+ uint32_t DMA17:1; /* Channel 17 DMA Enable */
+ uint32_t DMA16:1; /* Channel 16 DMA Enable */
+ uint32_t DMA15:1; /* Channel 15 DMA Enable */
+ uint32_t DMA14:1; /* Channel 14 DMA Enable */
+ uint32_t DMA13:1; /* Channel 13 DMA Enable */
+ uint32_t DMA12:1; /* Channel 12 DMA Enable */
+ uint32_t DMA11:1; /* Channel 11 DMA Enable */
+ uint32_t DMA10:1; /* Channel 10 DMA Enable */
+ uint32_t DMA9:1; /* Channel 9 DMA Enable */
+ uint32_t DMA8:1; /* Channel 8 DMA Enable */
+ uint32_t DMA7:1; /* Channel 7 DMA Enable */
+ uint32_t DMA6:1; /* Channel 6 DMA Enable */
+ uint32_t DMA5:1; /* Channel 5 DMA Enable */
+ uint32_t DMA4:1; /* Channel 4 DMA Enable */
+ uint32_t DMA3:1; /* Channel 3 DMA Enable */
+ uint32_t DMA2:1; /* Channel 2 DMA Enable */
+ uint32_t DMA1:1; /* Channel 1 DMA Enable */
+ uint32_t DMA0:1; /* Channel 0 DMA Enable */
+ } B;
+ } ADC_DMAR0_32B_tag;
+
+ typedef union { /* DMA REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t DMA63:1; /* Channel 63 DMA Enable */
+ uint32_t DMA62:1; /* Channel 62 DMA Enable */
+ uint32_t DMA61:1; /* Channel 61 DMA Enable */
+ uint32_t DMA60:1; /* Channel 60 DMA Enable */
+ uint32_t DMA59:1; /* Channel 59 DMA Enable */
+ uint32_t DMA58:1; /* Channel 58 DMA Enable */
+ uint32_t DMA57:1; /* Channel 57 DMA Enable */
+ uint32_t DMA56:1; /* Channel 56 DMA Enable */
+ uint32_t DMA55:1; /* Channel 55 DMA Enable */
+ uint32_t DMA54:1; /* Channel 54 DMA Enable */
+ uint32_t DMA53:1; /* Channel 53 DMA Enable */
+ uint32_t DMA52:1; /* Channel 52 DMA Enable */
+ uint32_t DMA51:1; /* Channel 51 DMA Enable */
+ uint32_t DMA50:1; /* Channel 50 DMA Enable */
+ uint32_t DMA49:1; /* Channel 49 DMA Enable */
+ uint32_t DMA48:1; /* Channel 48 DMA Enable */
+ uint32_t DMA47:1; /* Channel 47 DMA Enable */
+ uint32_t DMA46:1; /* Channel 46 DMA Enable */
+ uint32_t DMA45:1; /* Channel 45 DMA Enable */
+ uint32_t DMA44:1; /* Channel 44 DMA Enable */
+ uint32_t DMA43:1; /* Channel 43 DMA Enable */
+ uint32_t DMA42:1; /* Channel 42 DMA Enable */
+ uint32_t DMA41:1; /* Channel 41 DMA Enable */
+ uint32_t DMA40:1; /* Channel 40 DMA Enable */
+ uint32_t DMA39:1; /* Channel 39 DMA Enable */
+ uint32_t DMA38:1; /* Channel 38 DMA Enable */
+ uint32_t DMA37:1; /* Channel 37 DMA Enable */
+ uint32_t DMA36:1; /* Channel 36 DMA Enable */
+ uint32_t DMA35:1; /* Channel 35 DMA Enable */
+ uint32_t DMA34:1; /* Channel 34 DMA Enable */
+ uint32_t DMA33:1; /* Channel 33 DMA Enable */
+ uint32_t DMA32:1; /* Channel 32 DMA Enable */
+ } B;
+ } ADC_DMAR1_32B_tag;
+
+ typedef union { /* DMA REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t DMA95:1; /* Channel 95 DMA Enable */
+ uint32_t DMA94:1; /* Channel 94 DMA Enable */
+ uint32_t DMA93:1; /* Channel 93 DMA Enable */
+ uint32_t DMA92:1; /* Channel 92 DMA Enable */
+ uint32_t DMA91:1; /* Channel 91 DMA Enable */
+ uint32_t DMA90:1; /* Channel 90 DMA Enable */
+ uint32_t DMA89:1; /* Channel 89 DMA Enable */
+ uint32_t DMA88:1; /* Channel 88 DMA Enable */
+ uint32_t DMA87:1; /* Channel 87 DMA Enable */
+ uint32_t DMA86:1; /* Channel 86 DMA Enable */
+ uint32_t DMA85:1; /* Channel 85 DMA Enable */
+ uint32_t DMA84:1; /* Channel 84 DMA Enable */
+ uint32_t DMA83:1; /* Channel 83 DMA Enable */
+ uint32_t DMA82:1; /* Channel 82 DMA Enable */
+ uint32_t DMA81:1; /* Channel 81 DMA Enable */
+ uint32_t DMA80:1; /* Channel 80 DMA Enable */
+ uint32_t DMA79:1; /* Channel 79 DMA Enable */
+ uint32_t DMA78:1; /* Channel 78 DMA Enable */
+ uint32_t DMA77:1; /* Channel 77 DMA Enable */
+ uint32_t DMA76:1; /* Channel 76 DMA Enable */
+ uint32_t DMA75:1; /* Channel 75 DMA Enable */
+ uint32_t DMA74:1; /* Channel 74 DMA Enable */
+ uint32_t DMA73:1; /* Channel 73 DMA Enable */
+ uint32_t DMA72:1; /* Channel 72 DMA Enable */
+ uint32_t DMA71:1; /* Channel 71 DMA Enable */
+ uint32_t DMA70:1; /* Channel 70 DMA Enable */
+ uint32_t DMA69:1; /* Channel 69 DMA Enable */
+ uint32_t DMA68:1; /* Channel 68 DMA Enable */
+ uint32_t DMA67:1; /* Channel 67 DMA Enable */
+ uint32_t DMA66:1; /* Channel 66 DMA Enable */
+ uint32_t DMA65:1; /* Channel 65 DMA Enable */
+ uint32_t DMA64:1; /* Channel 64 DMA Enable */
+ } B;
+ } ADC_DMAR2_32B_tag;
+
+
+ /* Register layout for all registers TRC... */
+
+ typedef union { /* Threshold Control register C */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t THREN:1; /* Threshold enable */
+ uint32_t THRINV:1; /* invert the output pin */
+ uint32_t THROP:1; /* output pin register */
+ uint32_t:6;
+ uint32_t THRCH:7; /* Choose channel for threshold register */
+ } B;
+ } ADC_TRC_32B_tag;
+
+
+ /* Register layout for all registers THRHLR... */
+
+ typedef union { /* Upper Threshold register */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR_32B_tag;
+
+
+ /* Register layout for all registers THRALT... */
+
+ typedef union { /* alternate Upper Threshold register */
+ uint32_t R;
+ struct {
+ uint32_t:6;
+ uint32_t THRH:10; /* high threshold value s */
+ uint32_t:6;
+ uint32_t THRL:10; /* low threshold value s */
+ } B;
+ } ADC_THRALT_32B_tag;
+
+ typedef union { /* PRESAMPLING CONTROL REGISTER */
+ uint32_t R;
+ struct {
+ uint32_t:25;
+ uint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */
+ uint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */
+ uint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t PRECONV:1; /* Presampled value */
+#else
+ uint32_t PREONCE:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ADC_PSCR_32B_tag;
+
+ typedef union { /* Presampling Register 0 */
+ uint32_t R;
+ struct {
+ uint32_t PRES31:1; /* Channel 31 Presampling Enable */
+ uint32_t PRES30:1; /* Channel 30 Presampling Enable */
+ uint32_t PRES29:1; /* Channel 29 Presampling Enable */
+ uint32_t PRES28:1; /* Channel 28 Presampling Enable */
+ uint32_t PRES27:1; /* Channel 27 Presampling Enable */
+ uint32_t PRES26:1; /* Channel 26 Presampling Enable */
+ uint32_t PRES25:1; /* Channel 25 Presampling Enable */
+ uint32_t PRES24:1; /* Channel 24 Presampling Enable */
+ uint32_t PRES23:1; /* Channel 23 Presampling Enable */
+ uint32_t PRES22:1; /* Channel 22 Presampling Enable */
+ uint32_t PRES21:1; /* Channel 21 Presampling Enable */
+ uint32_t PRES20:1; /* Channel 20 Presampling Enable */
+ uint32_t PRES19:1; /* Channel 19 Presampling Enable */
+ uint32_t PRES18:1; /* Channel 18 Presampling Enable */
+ uint32_t PRES17:1; /* Channel 17 Presampling Enable */
+ uint32_t PRES16:1; /* Channel 16 Presampling Enable */
+ uint32_t PRES15:1; /* Channel 15 Presampling Enable */
+ uint32_t PRES14:1; /* Channel 14 Presampling Enable */
+ uint32_t PRES13:1; /* Channel 13 Presampling Enable */
+ uint32_t PRES12:1; /* Channel 12 Presampling Enable */
+ uint32_t PRES11:1; /* Channel 11 Presampling Enable */
+ uint32_t PRES10:1; /* Channel 10 Presampling Enable */
+ uint32_t PRES9:1; /* Channel 9 Presampling Enable */
+ uint32_t PRES8:1; /* Channel 8 Presampling Enable */
+ uint32_t PRES7:1; /* Channel 7 Presampling Enable */
+ uint32_t PRES6:1; /* Channel 6 Presampling Enable */
+ uint32_t PRES5:1; /* Channel 5 Presampling Enable */
+ uint32_t PRES4:1; /* Channel 4 Presampling Enable */
+ uint32_t PRES3:1; /* Channel 3 Presampling Enable */
+ uint32_t PRES2:1; /* Channel 2 Presampling Enable */
+ uint32_t PRES1:1; /* Channel 1presampling Enable */
+ uint32_t PRES0:1; /* Channel 0 Presampling Enable */
+ } B;
+ } ADC_PSR0_32B_tag;
+
+ typedef union { /* Presampling REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t PRES63:1; /* Channel 63 Presampling Enable */
+ uint32_t PRES62:1; /* Channel 62 Presampling Enable */
+ uint32_t PRES61:1; /* Channel 61 Presampling Enable */
+ uint32_t PRES60:1; /* Channel 60 Presampling Enable */
+ uint32_t PRES59:1; /* Channel 59 Presampling Enable */
+ uint32_t PRES58:1; /* Channel 58 Presampling Enable */
+ uint32_t PRES57:1; /* Channel 57 Presampling Enable */
+ uint32_t PRES56:1; /* Channel 56 Presampling Enable */
+ uint32_t PRES55:1; /* Channel 55 Presampling Enable */
+ uint32_t PRES54:1; /* Channel 54 Presampling Enable */
+ uint32_t PRES53:1; /* Channel 53 Presampling Enable */
+ uint32_t PRES52:1; /* Channel 52 Presampling Enable */
+ uint32_t PRES51:1; /* Channel 51 Presampling Enable */
+ uint32_t PRES50:1; /* Channel 50 Presampling Enable */
+ uint32_t PRES49:1; /* Channel 49 Presampling Enable */
+ uint32_t PRES48:1; /* Channel 48 Presampling Enable */
+ uint32_t PRES47:1; /* Channel 47 Presampling Enable */
+ uint32_t PRES46:1; /* Channel 46 Presampling Enable */
+ uint32_t PRES45:1; /* Channel 45 Presampling Enable */
+ uint32_t PRES44:1; /* Channel 44 Presampling Enable */
+ uint32_t PRES43:1; /* Channel 43 Presampling Enable */
+ uint32_t PRES42:1; /* Channel 42 Presampling Enable */
+ uint32_t PRES41:1; /* Channel 41 Presampling Enable */
+ uint32_t PRES40:1; /* Channel 40 Presampling Enable */
+ uint32_t PRES39:1; /* Channel 39 Presampling Enable */
+ uint32_t PRES38:1; /* Channel 38 Presampling Enable */
+ uint32_t PRES37:1; /* Channel 37 Presampling Enable */
+ uint32_t PRES36:1; /* Channel 36 Presampling Enable */
+ uint32_t PRES35:1; /* Channel 35 Presampling Enable */
+ uint32_t PRES34:1; /* Channel 34 Presampling Enable */
+ uint32_t PRES33:1; /* Channel 33 Presampling Enable */
+ uint32_t PRES32:1; /* Channel 32 Presampling Enable */
+ } B;
+ } ADC_PSR1_32B_tag;
+
+ typedef union { /* Presampling REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t PRES95:1; /* Channel 95 Presampling Enable */
+ uint32_t PRES94:1; /* Channel 94 Presampling Enable */
+ uint32_t PRES93:1; /* Channel 93 Presampling Enable */
+ uint32_t PRES92:1; /* Channel 92 Presampling Enable */
+ uint32_t PRES91:1; /* Channel 91 Presampling Enable */
+ uint32_t PRES90:1; /* Channel 90 Presampling Enable */
+ uint32_t PRES89:1; /* Channel 89 Presampling Enable */
+ uint32_t PRES88:1; /* Channel 88 Presampling Enable */
+ uint32_t PRES87:1; /* Channel 87 Presampling Enable */
+ uint32_t PRES86:1; /* Channel 86 Presampling Enable */
+ uint32_t PRES85:1; /* Channel 85 Presampling Enable */
+ uint32_t PRES84:1; /* Channel 84 Presampling Enable */
+ uint32_t PRES83:1; /* Channel 83 Presampling Enable */
+ uint32_t PRES82:1; /* Channel 82 Presampling Enable */
+ uint32_t PRES81:1; /* Channel 81 Presampling Enable */
+ uint32_t PRES80:1; /* Channel 80 Presampling Enable */
+ uint32_t PRES79:1; /* Channel 79 Presampling Enable */
+ uint32_t PRES78:1; /* Channel 78 Presampling Enable */
+ uint32_t PRES77:1; /* Channel 77 Presampling Enable */
+ uint32_t PRES76:1; /* Channel 76 Presampling Enable */
+ uint32_t PRES75:1; /* Channel 75 Presampling Enable */
+ uint32_t PRES74:1; /* Channel 74 Presampling Enable */
+ uint32_t PRES73:1; /* Channel 73 Presampling Enable */
+ uint32_t PRES72:1; /* Channel 72 Presampling Enable */
+ uint32_t PRES71:1; /* Channel 71 Presampling Enable */
+ uint32_t PRES70:1; /* Channel 70 Presampling Enable */
+ uint32_t PRES69:1; /* Channel 69 Presampling Enable */
+ uint32_t PRES68:1; /* Channel 68 Presampling Enable */
+ uint32_t PRES67:1; /* Channel 67 Presampling Enable */
+ uint32_t PRES66:1; /* Channel 66 Presampling Enable */
+ uint32_t PRES65:1; /* Channel 65 Presampling Enable */
+ uint32_t PRES64:1; /* Channel 64 Presampling Enable */
+ } B;
+ } ADC_PSR2_32B_tag;
+
+
+ /* Register layout for all registers CTR... */
+
+ typedef union { /* conversion timing register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */
+ uint32_t:1;
+ uint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */
+ uint32_t:1;
+ uint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */
+ uint32_t:1;
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */
+#else
+ uint32_t INPSAMP:8;
+#endif
+ } B;
+ } ADC_CTR_32B_tag;
+
+ typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */
+ uint32_t R;
+ struct {
+ uint32_t CH31:1; /* Channel 31 Normal Sampling Enable */
+ uint32_t CH30:1; /* Channel 30 Normal Sampling Enable */
+ uint32_t CH29:1; /* Channel 29 Normal Sampling Enable */
+ uint32_t CH28:1; /* Channel 28 Normal Sampling Enable */
+ uint32_t CH27:1; /* Channel 27 Normal Sampling Enable */
+ uint32_t CH26:1; /* Channel 26 Normal Sampling Enable */
+ uint32_t CH25:1; /* Channel 25 Normal Sampling Enable */
+ uint32_t CH24:1; /* Channel 24 Normal Sampling Enable */
+ uint32_t CH23:1; /* Channel 23 Normal Sampling Enable */
+ uint32_t CH22:1; /* Channel 22 Normal Sampling Enable */
+ uint32_t CH21:1; /* Channel 21 Normal Sampling Enable */
+ uint32_t CH20:1; /* Channel 20 Normal Sampling Enable */
+ uint32_t CH19:1; /* Channel 19 Normal Sampling Enable */
+ uint32_t CH18:1; /* Channel 18 Normal Sampling Enable */
+ uint32_t CH17:1; /* Channel 17 Normal Sampling Enable */
+ uint32_t CH16:1; /* Channel 16 Normal Sampling Enable */
+ uint32_t CH15:1; /* Channel 15 Normal Sampling Enable */
+ uint32_t CH14:1; /* Channel 14 Normal Sampling Enable */
+ uint32_t CH13:1; /* Channel 13 Normal Sampling Enable */
+ uint32_t CH12:1; /* Channel 12 Normal Sampling Enable */
+ uint32_t CH11:1; /* Channel 11 Normal Sampling Enable */
+ uint32_t CH10:1; /* Channel 10 Normal Sampling Enable */
+ uint32_t CH9:1; /* Channel 9 Normal Sampling Enable */
+ uint32_t CH8:1; /* Channel 8 Normal Sampling Enable */
+ uint32_t CH7:1; /* Channel 7 Normal Sampling Enable */
+ uint32_t CH6:1; /* Channel 6 Normal Sampling Enable */
+ uint32_t CH5:1; /* Channel 5 Normal Sampling Enable */
+ uint32_t CH4:1; /* Channel 4 Normal Sampling Enable */
+ uint32_t CH3:1; /* Channel 3 Normal Sampling Enable */
+ uint32_t CH2:1; /* Channel 2 Normal Sampling Enable */
+ uint32_t CH1:1; /* Channel 1 Normal Sampling Enable */
+ uint32_t CH0:1; /* Channel 0 Normal Sampling Enable */
+ } B;
+ } ADC_NCMR0_32B_tag;
+
+ typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t CH63:1; /* Channel 63 Normal Sampling Enable */
+ uint32_t CH62:1; /* Channel 62 Normal Sampling Enable */
+ uint32_t CH61:1; /* Channel 61 Normal Sampling Enable */
+ uint32_t CH60:1; /* Channel 60 Normal Sampling Enable */
+ uint32_t CH59:1; /* Channel 59 Normal Sampling Enable */
+ uint32_t CH58:1; /* Channel 58 Normal Sampling Enable */
+ uint32_t CH57:1; /* Channel 57 Normal Sampling Enable */
+ uint32_t CH56:1; /* Channel 56 Normal Sampling Enable */
+ uint32_t CH55:1; /* Channel 55 Normal Sampling Enable */
+ uint32_t CH54:1; /* Channel 54 Normal Sampling Enable */
+ uint32_t CH53:1; /* Channel 53 Normal Sampling Enable */
+ uint32_t CH52:1; /* Channel 52 Normal Sampling Enable */
+ uint32_t CH51:1; /* Channel 51 Normal Sampling Enable */
+ uint32_t CH50:1; /* Channel 50 Normal Sampling Enable */
+ uint32_t CH49:1; /* Channel 49 Normal Sampling Enable */
+ uint32_t CH48:1; /* Channel 48 Normal Sampling Enable */
+ uint32_t CH47:1; /* Channel 47 Normal Sampling Enable */
+ uint32_t CH46:1; /* Channel 46 Normal Sampling Enable */
+ uint32_t CH45:1; /* Channel 45 Normal Sampling Enable */
+ uint32_t CH44:1; /* Channel 44 Normal Sampling Enable */
+ uint32_t CH43:1; /* Channel 43 Normal Sampling Enable */
+ uint32_t CH42:1; /* Channel 42 Normal Sampling Enable */
+ uint32_t CH41:1; /* Channel 41 Normal Sampling Enable */
+ uint32_t CH40:1; /* Channel 40 Normal Sampling Enable */
+ uint32_t CH39:1; /* Channel 39 Normal Sampling Enable */
+ uint32_t CH38:1; /* Channel 38 Normal Sampling Enable */
+ uint32_t CH37:1; /* Channel 37 Normal Sampling Enable */
+ uint32_t CH36:1; /* Channel 36 Normal Sampling Enable */
+ uint32_t CH35:1; /* Channel 35 Normal Sampling Enable */
+ uint32_t CH34:1; /* Channel 34 Normal Sampling Enable */
+ uint32_t CH33:1; /* Channel 33 Normal Sampling Enable */
+ uint32_t CH32:1; /* Channel 32 Normal Sampling Enable */
+ } B;
+ } ADC_NCMR1_32B_tag;
+
+ typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t CH95:1; /* Channel 95 Normal Sampling Enable */
+ uint32_t CH94:1; /* Channel 94 Normal Sampling Enable */
+ uint32_t CH93:1; /* Channel 93 Normal Sampling Enable */
+ uint32_t CH92:1; /* Channel 92 Normal Sampling Enable */
+ uint32_t CH91:1; /* Channel 91 Normal Sampling Enable */
+ uint32_t CH90:1; /* Channel 90 Normal Sampling Enable */
+ uint32_t CH89:1; /* Channel 89 Normal Sampling Enable */
+ uint32_t CH88:1; /* Channel 88 Normal Sampling Enable */
+ uint32_t CH87:1; /* Channel 87 Normal Sampling Enable */
+ uint32_t CH86:1; /* Channel 86 Normal Sampling Enable */
+ uint32_t CH85:1; /* Channel 85 Normal Sampling Enable */
+ uint32_t CH84:1; /* Channel 84 Normal Sampling Enable */
+ uint32_t CH83:1; /* Channel 83 Normal Sampling Enable */
+ uint32_t CH82:1; /* Channel 82 Normal Sampling Enable */
+ uint32_t CH81:1; /* Channel 81 Normal Sampling Enable */
+ uint32_t CH80:1; /* Channel 80 Normal Sampling Enable */
+ uint32_t CH79:1; /* Channel 79 Normal Sampling Enable */
+ uint32_t CH78:1; /* Channel 78 Normal Sampling Enable */
+ uint32_t CH77:1; /* Channel 77 Normal Sampling Enable */
+ uint32_t CH76:1; /* Channel 76 Normal Sampling Enable */
+ uint32_t CH75:1; /* Channel 75 Normal Sampling Enable */
+ uint32_t CH74:1; /* Channel 74 Normal Sampling Enable */
+ uint32_t CH73:1; /* Channel 73 Normal Sampling Enable */
+ uint32_t CH72:1; /* Channel 72 Normal Sampling Enable */
+ uint32_t CH71:1; /* Channel 71 Normal Sampling Enable */
+ uint32_t CH70:1; /* Channel 70 Normal Sampling Enable */
+ uint32_t CH69:1; /* Channel 69 Normal Sampling Enable */
+ uint32_t CH68:1; /* Channel 68 Normal Sampling Enable */
+ uint32_t CH67:1; /* Channel 67 Normal Sampling Enable */
+ uint32_t CH66:1; /* Channel 66 Normal Sampling Enable */
+ uint32_t CH65:1; /* Channel 65 Normal Sampling Enable */
+ uint32_t CH64:1; /* Channel 64 Normal Sampling Enable */
+ } B;
+ } ADC_NCMR2_32B_tag;
+
+ typedef union { /* Injected Conversion Mask Register 0 */
+ uint32_t R;
+ struct {
+ uint32_t CH31:1; /* Channel 31 Injected Sampling Enable */
+ uint32_t CH30:1; /* Channel 30 Injected Sampling Enable */
+ uint32_t CH29:1; /* Channel 29 Injected Sampling Enable */
+ uint32_t CH28:1; /* Channel 28 Injected Sampling Enable */
+ uint32_t CH27:1; /* Channel 27 Injected Sampling Enable */
+ uint32_t CH26:1; /* Channel 26 Injected Sampling Enable */
+ uint32_t CH25:1; /* Channel 25 Injected Sampling Enable */
+ uint32_t CH24:1; /* Channel 24 Injected Sampling Enable */
+ uint32_t CH23:1; /* Channel 23 Injected Sampling Enable */
+ uint32_t CH22:1; /* Channel 22 Injected Sampling Enable */
+ uint32_t CH21:1; /* Channel 21 Injected Sampling Enable */
+ uint32_t CH20:1; /* Channel 20 Injected Sampling Enable */
+ uint32_t CH19:1; /* Channel 19 Injected Sampling Enable */
+ uint32_t CH18:1; /* Channel 18 Injected Sampling Enable */
+ uint32_t CH17:1; /* Channel 17 Injected Sampling Enable */
+ uint32_t CH16:1; /* Channel 16 Injected Sampling Enable */
+ uint32_t CH15:1; /* Channel 15 Injected Sampling Enable */
+ uint32_t CH14:1; /* Channel 14 Injected Sampling Enable */
+ uint32_t CH13:1; /* Channel 13 Injected Sampling Enable */
+ uint32_t CH12:1; /* Channel 12 Injected Sampling Enable */
+ uint32_t CH11:1; /* Channel 11 Injected Sampling Enable */
+ uint32_t CH10:1; /* Channel 10 Injected Sampling Enable */
+ uint32_t CH9:1; /* Channel 9 Injected Sampling Enable */
+ uint32_t CH8:1; /* Channel 8 Injected Sampling Enable */
+ uint32_t CH7:1; /* Channel 7 Injected Sampling Enable */
+ uint32_t CH6:1; /* Channel 6 Injected Sampling Enable */
+ uint32_t CH5:1; /* Channel 5 Injected Sampling Enable */
+ uint32_t CH4:1; /* Channel 4 Injected Sampling Enable */
+ uint32_t CH3:1; /* Channel 3 Injected Sampling Enable */
+ uint32_t CH2:1; /* Channel 2 Injected Sampling Enable */
+ uint32_t CH1:1; /* Channel 1 injected Sampling Enable */
+ uint32_t CH0:1; /* Channel 0 injected Sampling Enable */
+ } B;
+ } ADC_JCMR0_32B_tag;
+
+ typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t CH63:1; /* Channel 63 Injected Sampling Enable */
+ uint32_t CH62:1; /* Channel 62 Injected Sampling Enable */
+ uint32_t CH61:1; /* Channel 61 Injected Sampling Enable */
+ uint32_t CH60:1; /* Channel 60 Injected Sampling Enable */
+ uint32_t CH59:1; /* Channel 59 Injected Sampling Enable */
+ uint32_t CH58:1; /* Channel 58 Injected Sampling Enable */
+ uint32_t CH57:1; /* Channel 57 Injected Sampling Enable */
+ uint32_t CH56:1; /* Channel 56 Injected Sampling Enable */
+ uint32_t CH55:1; /* Channel 55 Injected Sampling Enable */
+ uint32_t CH54:1; /* Channel 54 Injected Sampling Enable */
+ uint32_t CH53:1; /* Channel 53 Injected Sampling Enable */
+ uint32_t CH52:1; /* Channel 52 Injected Sampling Enable */
+ uint32_t CH51:1; /* Channel 51 Injected Sampling Enable */
+ uint32_t CH50:1; /* Channel 50 Injected Sampling Enable */
+ uint32_t CH49:1; /* Channel 49 Injected Sampling Enable */
+ uint32_t CH48:1; /* Channel 48 Injected Sampling Enable */
+ uint32_t CH47:1; /* Channel 47 Injected Sampling Enable */
+ uint32_t CH46:1; /* Channel 46 Injected Sampling Enable */
+ uint32_t CH45:1; /* Channel 45 Injected Sampling Enable */
+ uint32_t CH44:1; /* Channel 44 Injected Sampling Enable */
+ uint32_t CH43:1; /* Channel 43 Injected Sampling Enable */
+ uint32_t CH42:1; /* Channel 42 Injected Sampling Enable */
+ uint32_t CH41:1; /* Channel 41 Injected Sampling Enable */
+ uint32_t CH40:1; /* Channel 40 Injected Sampling Enable */
+ uint32_t CH39:1; /* Channel 39 Injected Sampling Enable */
+ uint32_t CH38:1; /* Channel 38 Injected Sampling Enable */
+ uint32_t CH37:1; /* Channel 37 Injected Sampling Enable */
+ uint32_t CH36:1; /* Channel 36 Injected Sampling Enable */
+ uint32_t CH35:1; /* Channel 35 Injected Sampling Enable */
+ uint32_t CH34:1; /* Channel 34 Injected Sampling Enable */
+ uint32_t CH33:1; /* Channel 33 Injected Sampling Enable */
+ uint32_t CH32:1; /* Channel 32 Injected Sampling Enable */
+ } B;
+ } ADC_JCMR1_32B_tag;
+
+ typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t CH95:1; /* Channel 95 Injected Sampling Enable */
+ uint32_t CH94:1; /* Channel 94 Injected Sampling Enable */
+ uint32_t CH93:1; /* Channel 93 Injected Sampling Enable */
+ uint32_t CH92:1; /* Channel 92 Injected Sampling Enable */
+ uint32_t CH91:1; /* Channel 91 Injected Sampling Enable */
+ uint32_t CH90:1; /* Channel 90 Injected Sampling Enable */
+ uint32_t CH89:1; /* Channel 89 Injected Sampling Enable */
+ uint32_t CH88:1; /* Channel 88 Injected Sampling Enable */
+ uint32_t CH87:1; /* Channel 87 Injected Sampling Enable */
+ uint32_t CH86:1; /* Channel 86 Injected Sampling Enable */
+ uint32_t CH85:1; /* Channel 85 Injected Sampling Enable */
+ uint32_t CH84:1; /* Channel 84 Injected Sampling Enable */
+ uint32_t CH83:1; /* Channel 83 Injected Sampling Enable */
+ uint32_t CH82:1; /* Channel 82 Injected Sampling Enable */
+ uint32_t CH81:1; /* Channel 81 Injected Sampling Enable */
+ uint32_t CH80:1; /* Channel 80 Injected Sampling Enable */
+ uint32_t CH79:1; /* Channel 79 Injected Sampling Enable */
+ uint32_t CH78:1; /* Channel 78 Injected Sampling Enable */
+ uint32_t CH77:1; /* Channel 77 Injected Sampling Enable */
+ uint32_t CH76:1; /* Channel 76 Injected Sampling Enable */
+ uint32_t CH75:1; /* Channel 75 Injected Sampling Enable */
+ uint32_t CH74:1; /* Channel 74 Injected Sampling Enable */
+ uint32_t CH73:1; /* Channel 73 Injected Sampling Enable */
+ uint32_t CH72:1; /* Channel 72 Injected Sampling Enable */
+ uint32_t CH71:1; /* Channel 71 Injected Sampling Enable */
+ uint32_t CH70:1; /* Channel 70 Injected Sampling Enable */
+ uint32_t CH69:1; /* Channel 69 Injected Sampling Enable */
+ uint32_t CH68:1; /* Channel 68 Injected Sampling Enable */
+ uint32_t CH67:1; /* Channel 67 Injected Sampling Enable */
+ uint32_t CH66:1; /* Channel 66 Injected Sampling Enable */
+ uint32_t CH65:1; /* Channel 65 Injected Sampling Enable */
+ uint32_t CH64:1; /* Channel 64 Injected Sampling Enable */
+ } B;
+ } ADC_JCMR2_32B_tag;
+
+ typedef union { /* Offset Word Regsiter */
+ uint32_t R;
+ struct {
+ uint32_t:15;
+ uint32_t OFFSETLOAD:1; /* load_offset */
+ uint32_t:8;
+#ifndef USE_FIELD_ALIASES_ADC
+ uint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */
+#else
+ uint32_t OFFSETWORD:8;
+#endif
+ } B;
+ } ADC_OFFWR_32B_tag;
+
+ typedef union { /* Decode Signal Delay Register */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t DSD:8; /* take into account the settling time of the external mux */
+ } B;
+ } ADC_DSDR_32B_tag;
+
+ typedef union { /* Power Down Dealy Register */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */
+ } B;
+ } ADC_PDEDR_32B_tag;
+
+
+ /* Register layout for all registers CDR... */
+
+ typedef union { /* CHANNEL DATA REGS */
+ uint32_t R;
+ struct {
+ uint32_t:12;
+ uint32_t VALID:1; /* validity of data */
+ uint32_t OVERW:1; /* overwrite data */
+ uint32_t RESULT:2; /* reflects mode conversion */
+ uint32_t:6;
+ uint32_t CDATA:10; /* Channel 0 converted data */
+ } B;
+ } ADC_CDR_32B_tag;
+
+ typedef union { /* Upper Threshold register 4 is not contiguous to 3 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR4_32B_tag;
+
+ typedef union { /* Upper Threshold register 5 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR5_32B_tag;
+
+ typedef union { /* Upper Threshold register 6 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR6_32B_tag;
+
+ typedef union { /* Upper Threshold register 7 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR7_32B_tag;
+
+ typedef union { /* Upper Threshold register 8 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR8_32B_tag;
+
+ typedef union { /* Upper Threshold register 9 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR9_32B_tag;
+
+ typedef union { /* Upper Threshold register 10 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR10_32B_tag;
+
+ typedef union { /* Upper Threshold register 11 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR11_32B_tag;
+
+ typedef union { /* Upper Threshold register 12 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR12_32B_tag;
+
+ typedef union { /* Upper Threshold register 13 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR13_32B_tag;
+
+ typedef union { /* Upper Threshold register 14 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR14_32B_tag;
+
+ typedef union { /* Upper Threshold register 15 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* high threshold value s */
+ uint32_t:4;
+ uint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR15_32B_tag;
+
+
+ /* Register layout for all registers CWSELR... */
+
+ typedef union { /* Channel Watchdog Select register */
+ uint32_t R;
+ struct {
+ uint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */
+ uint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */
+ uint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */
+ uint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */
+ uint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */
+ uint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */
+ uint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */
+ uint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */
+ } B;
+ } ADC_CWSELR_32B_tag;
+
+
+ /* Register layout for all registers CWENR... */
+
+ typedef union { /* Channel Watchdog Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ uint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ } B;
+ } ADC_CWENR_32B_tag;
+
+
+ /* Register layout for all registers AWORR... */
+
+ typedef union { /* Analog Watchdog Out of Range Register */
+ uint32_t R;
+ struct {
+ uint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */
+ uint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */
+ uint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */
+ uint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */
+ uint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */
+ uint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */
+ uint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */
+ uint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */
+ uint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */
+ uint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */
+ uint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */
+ uint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */
+ uint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */
+ uint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */
+ uint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */
+ uint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */
+ uint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */
+ uint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */
+ uint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */
+ uint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */
+ uint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */
+ uint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */
+ uint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */
+ uint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */
+ uint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */
+ uint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */
+ uint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */
+ uint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */
+ uint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */
+ uint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */
+ uint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */
+ uint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */
+ } B;
+ } ADC_AWORR_32B_tag;
+
+ typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */
+ uint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */
+ uint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */
+ uint32_t:5;
+ uint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */
+ uint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */
+ } B;
+ } ADC_STCR1_32B_tag;
+
+ typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t:5;
+ uint32_t SERR:1; /* Error fault injection bit (write only) */
+ uint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */
+ uint32_t:1;
+ uint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */
+ uint32_t:4;
+ uint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */
+ uint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */
+ uint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */
+ uint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */
+ uint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */
+ uint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */
+ uint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */
+ uint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */
+ uint32_t:3;
+ uint32_t EN:1; /* Self testing channel enable */
+ uint32_t:4;
+ uint32_t FMA_C:1; /* Fault mapping for the algorithm C */
+ uint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */
+ uint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */
+ } B;
+ } ADC_STCR2_32B_tag;
+
+ typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */
+ uint32_t R;
+ struct {
+ uint32_t:22;
+ uint32_t ALG:2; /* Algorithm scheduling */
+ uint32_t:8;
+ } B;
+ } ADC_STCR3_32B_tag;
+
+ typedef union { /* SELF TEST BAUD RATE REGISTER */
+ uint32_t R;
+ struct {
+ uint32_t:13;
+ uint32_t WDT:3; /* Watchdog timer value */
+ uint32_t:8;
+ uint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */
+ } B;
+ } ADC_STBRR_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t:6;
+ uint32_t WDTERR:1; /* Watchdog timer error */
+ uint32_t OVERWR:1; /* Overwrite error */
+ uint32_t ST_EOC:1; /* Self test EOC bit */
+ uint32_t:4;
+ uint32_t WDG_EOA_C:1; /* Algorithm C completed without error */
+ uint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */
+ uint32_t WDG_EOA_S:1; /* Algorithm S completed without error */
+ uint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */
+ uint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */
+ uint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */
+ uint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */
+ uint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */
+ uint32_t:1;
+ uint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */
+ uint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */
+ } B;
+ } ADC_STSR1_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t OVFL:1; /* Overflow bit */
+ uint32_t:3;
+ uint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */
+ uint32_t:4;
+ uint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */
+ } B;
+ } ADC_STSR2_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 3 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */
+ uint32_t:4;
+ uint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */
+ } B;
+ } ADC_STSR3_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 4 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */
+ uint32_t:4;
+ uint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */
+ } B;
+ } ADC_STSR4_32B_tag;
+
+ typedef union { /* SELF TEST DATA REGISTER 1 */
+ uint32_t R;
+ struct {
+ uint32_t:12;
+ uint32_t VALID:1; /* Valid data */
+ uint32_t OVERWR:1; /* Overwrite data */
+ uint32_t:6;
+ uint32_t TCDATA:12; /* Test channel converted data */
+ } B;
+ } ADC_STDR1_32B_tag;
+
+ typedef union { /* SELF TEST DATA REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */
+ uint32_t VALID:1; /* Valid data */
+ uint32_t OVERWR:1; /* Overwrite data */
+ uint32_t:6;
+ uint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */
+ } B;
+ } ADC_STDR2_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
+ uint32_t R;
+ struct {
+ uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
+ uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */
+ uint32_t:2;
+ uint32_t THRH:12; /* High threshold value for channel 0 */
+ uint32_t:4;
+ uint32_t THRL:12; /* Low threshold value for channel 0 */
+ } B;
+ } ADC_STAW0R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
+ uint32_t R;
+ struct {
+ uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
+ uint32_t:3;
+ uint32_t THRH:12; /* High threshold value for test channel - algorithm S */
+ uint32_t:4;
+ uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
+ } B;
+ } ADC_STAW1AR_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* High threshold value for test channel - algorithm S */
+ uint32_t:4;
+ uint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
+ } B;
+ } ADC_STAW1BR_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
+ uint32_t R;
+ struct {
+ uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
+ uint32_t:19;
+ uint32_t THRL:12; /* Low threshold value for channel */
+ } B;
+ } ADC_STAW2R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
+ uint32_t R;
+ struct {
+ uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */
+ uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */
+ uint32_t:2;
+ uint32_t THRH:12; /* High threshold value for channel 3 */
+ uint32_t:4;
+ uint32_t THRL:12; /* Low threshold value for channel 3 */
+ } B;
+ } ADC_STAW3R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
+ uint32_t R;
+ struct {
+ uint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */
+ uint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */
+ uint32_t:2;
+ uint32_t THRH:12; /* High threshold value for channel 4 */
+ uint32_t:4;
+ uint32_t THRL:12; /* Low threshold value for channel 4 */
+ } B;
+ } ADC_STAW4R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
+ uint32_t R;
+ struct {
+ uint32_t:4;
+ uint32_t THRH:12; /* High threshold value for algorithm C */
+ uint32_t:4;
+ uint32_t THRL:12; /* Low threshold value for algorithm C */
+ } B;
+ } ADC_STAW5R_32B_tag;
+
+
+
+ typedef struct ADC_struct_tag { /* start of ADC_tag */
+ /* module configuration register */
+ ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
+ /* module status register */
+ ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */
+ int8_t ADC_reserved_0008[8];
+ /* Interrupt status register */
+ ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
+ union {
+ ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */
+
+ struct {
+ /* CHANNEL PENDING REGISTER 0 */
+ ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */
+ /* CHANNEL PENDING REGISTER 1 */
+ ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */
+ /* CHANNEL PENDING REGISTER 2 */
+ ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */
+ };
+
+ };
+ /* interrupt mask register */
+ ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */
+ union {
+ ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */
+
+ struct {
+ /* CHANNEL INTERRUPT MASK REGISTER 0 */
+ ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */
+ /* CHANNEL INTERRUPT MASK REGISTER 1 */
+ ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */
+ /* CHANNEL INTERRUPT MASK REGISTER 2 */
+ ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */
+ };
+
+ };
+ /* Watchdog Threshold interrupt status register */
+ ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */
+ /* Watchdog interrupt MASK register */
+ ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */
+ int8_t ADC_reserved_0038[8];
+ /* DMAE register */
+ ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */
+ union {
+ ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */
+
+ struct {
+ /* DMA REGISTER 0 */
+ ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */
+ /* DMA REGISTER 1 */
+ ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */
+ /* DMA REGISTER 2 */
+ ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */
+ };
+
+ };
+ union {
+ /* Threshold Control register C */
+ ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */
+
+ struct {
+ /* Threshold Control register C */
+ ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */
+ ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */
+ ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */
+ ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */
+ };
+
+ };
+ union {
+ /* Upper Threshold register */
+ ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */
+
+ struct {
+ /* Upper Threshold register */
+ ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */
+ ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */
+ ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */
+ ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */
+ };
+
+ };
+ union {
+ /* alternate Upper Threshold register */
+ ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */
+
+ struct {
+ /* alternate Upper Threshold register */
+ ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */
+ ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */
+ ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */
+ ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */
+ };
+
+ };
+ /* PRESAMPLING CONTROL REGISTER */
+ ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */
+ union {
+ ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */
+
+ struct {
+ /* Presampling Register 0 */
+ ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */
+ /* Presampling REGISTER 1 */
+ ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */
+ /* Presampling REGISTER 2 */
+ ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_0090_C[4];
+ union {
+ /* conversion timing register */
+ ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */
+
+ struct {
+ /* conversion timing register */
+ ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */
+ ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */
+ ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_00A0_C[4];
+ union {
+ ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */
+
+ struct {
+ /* NORMAL CONVERSION MASK REGISTER 0 */
+ ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */
+ /* NORMAL CONVERSION MASK REGISTER 1 */
+ ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */
+ /* NORMAL CONVERSION MASK REGISTER 2 */
+ ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_00B0_C[4];
+ union {
+ ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */
+
+ struct {
+ /* Injected Conversion Mask Register 0 */
+ ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */
+ /* INJECTED CONVERSION MASK REGISTER 1 */
+ ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */
+ /* INJECTED CONVERSION MASK REGISTER 2 */
+ ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */
+ };
+
+ };
+ /* Offset Word Regsiter */
+ ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */
+ /* Decode Signal Delay Register */
+ ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */
+ /* Power Down Dealy Register */
+ ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */
+ int8_t ADC_reserved_00CC_C[52];
+ union {
+ /* CHANNEL DATA REGS */
+ ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */
+
+ struct {
+ /* CHANNEL DATA REGS */
+ ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */
+ ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */
+ ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */
+ ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */
+ ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */
+ ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */
+ ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */
+ ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */
+ ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */
+ ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */
+ ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */
+ ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */
+ ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */
+ ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */
+ ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */
+ ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */
+ ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */
+ ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */
+ ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */
+ ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */
+ ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */
+ ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */
+ ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */
+ ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */
+ ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */
+ ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */
+ ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */
+ ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */
+ ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */
+ ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */
+ ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */
+ ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */
+ ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */
+ ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */
+ ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */
+ ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */
+ ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */
+ ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */
+ ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */
+ ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */
+ ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */
+ ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */
+ ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */
+ ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */
+ ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */
+ ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */
+ ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */
+ ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */
+ ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */
+ ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */
+ ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */
+ ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */
+ ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */
+ ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */
+ ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */
+ ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */
+ ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */
+ ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */
+ ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */
+ ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */
+ ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */
+ ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */
+ ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */
+ ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */
+ ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */
+ ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */
+ ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */
+ ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */
+ ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */
+ ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */
+ ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */
+ ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */
+ ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */
+ ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */
+ ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */
+ ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */
+ ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */
+ ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */
+ ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */
+ ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */
+ ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */
+ ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */
+ ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */
+ ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */
+ ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */
+ ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */
+ ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */
+ ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */
+ ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */
+ ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */
+ ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */
+ ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */
+ ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */
+ ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */
+ ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */
+ ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */
+ };
+
+ };
+ /* Upper Threshold register 4 is not contiguous to 3 */
+ ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */
+ /* Upper Threshold register 5 */
+ ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */
+ /* Upper Threshold register 6 */
+ ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */
+ /* Upper Threshold register 7 */
+ ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */
+ /* Upper Threshold register 8 */
+ ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */
+ /* Upper Threshold register 9 */
+ ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */
+ /* Upper Threshold register 10 */
+ ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */
+ /* Upper Threshold register 11 */
+ ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */
+ /* Upper Threshold register 12 */
+ ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */
+ /* Upper Threshold register 13 */
+ ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */
+ /* Upper Threshold register 14 */
+ ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */
+ /* Upper Threshold register 15 */
+ ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */
+ union {
+ /* Channel Watchdog Select register */
+ ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */
+
+ struct {
+ /* Channel Watchdog Select register */
+ ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */
+ };
+
+ };
+ union {
+ /* Channel Watchdog Enable Register */
+ ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */
+
+ struct {
+ /* Channel Watchdog Enable Register */
+ ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */
+ ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */
+ ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_02EC_C[4];
+ union {
+ /* Analog Watchdog Out of Range Register */
+ ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */
+
+ struct {
+ /* Analog Watchdog Out of Range Register */
+ ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */
+ ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */
+ ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_02FC[68];
+ /* SELF TEST CONFIGURATION REGISTER 1 */
+ ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */
+ /* SELF TEST CONFIGURATION REGISTER 2 */
+ ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */
+ /* SELF TEST CONFIGURATION REGISTER 3 */
+ ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */
+ /* SELF TEST BAUD RATE REGISTER */
+ ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */
+ /* SELF TEST STATUS REGISTER 1 */
+ ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */
+ /* SELF TEST STATUS REGISTER 2 */
+ ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */
+ /* SELF TEST STATUS REGISTER 3 */
+ ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */
+ /* SELF TEST STATUS REGISTER 4 */
+ ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */
+ int8_t ADC_reserved_0360[16];
+ /* SELF TEST DATA REGISTER 1 */
+ ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */
+ /* SELF TEST DATA REGISTER 2 */
+ ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */
+ int8_t ADC_reserved_0378[8];
+ /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
+ ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
+ ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
+ ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
+ ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
+ ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
+ ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
+ ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */
+ } ADC_tag;
+
+
+#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL)
+#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CTU */
+/* */
+/****************************************************************/
+
+ typedef union { /* Trigger Generator Subunit Input Selection register */
+ uint32_t R;
+ struct {
+ uint32_t I15_FE:1; /* ext_signal Falling Edge */
+ uint32_t I15_RE:1; /* ext_signal Rising Edge */
+ uint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */
+ uint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */
+ uint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */
+ uint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */
+ uint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */
+ uint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */
+ uint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */
+ uint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */
+ uint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */
+ uint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */
+ uint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */
+ uint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */
+ uint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */
+ uint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */
+ uint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */
+ uint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */
+ uint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */
+ uint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */
+ uint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */
+ uint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */
+ uint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */
+ uint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */
+ uint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */
+ uint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */
+ uint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */
+ uint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */
+ uint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */
+ uint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */
+ uint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */
+ uint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */
+ } B;
+ } CTU_TGSISR_32B_tag;
+
+ typedef union { /* Trigger Generator Subunit Control Register */
+ uint16_t R;
+ struct {
+ uint16_t:7;
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t ET_TM:1; /* Toggle Mode Enable */
+#else
+ uint16_t ETTM:1; /* deprecated name - please avoid */
+#endif
+ uint16_t PRES:2; /* TGS Prescaler Selection */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */
+#else
+ uint16_t MRSSM:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t TGS_M:1; /* Trigger Generator Subunit Mode */
+#else
+ uint16_t TGSM:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } CTU_TGSCR_16B_tag;
+
+ typedef union { /* */
+ uint16_t R;
+ } CTU_TCR_16B_tag;
+
+ typedef union { /* TGS Counter Compare Register */
+ uint16_t R;
+#ifndef USE_FIELD_ALIASES_CTU
+ struct {
+ uint16_t TGSCCV:16; /* deprecated field -- do not use */
+ } B;
+#endif
+ } CTU_TGSCCR_16B_tag;
+
+ typedef union { /* TGS Counter Reload Register */
+ uint16_t R;
+#ifndef USE_FIELD_ALIASES_CTU
+ struct {
+ uint16_t TGSCRV:16; /* deprecated field -- do not use */
+ } B;
+#endif
+ } CTU_TGSCRR_16B_tag;
+
+ typedef union { /* Commands List Control Register 1 */
+ uint32_t R;
+ struct {
+ uint32_t:3;
+ uint32_t T3INDEX:5; /* Trigger 3 First Command address */
+ uint32_t:3;
+ uint32_t T2INDEX:5; /* Trigger 2 First Command address */
+ uint32_t:3;
+ uint32_t T1INDEX:5; /* Trigger 1 First Command address */
+ uint32_t:3;
+ uint32_t T0INDEX:5; /* Trigger 0 First Command address */
+ } B;
+ } CTU_CLCR1_32B_tag;
+
+ typedef union { /* Commands List Control Register 2 */
+ uint32_t R;
+ struct {
+ uint32_t:3;
+ uint32_t T7INDEX:5; /* Trigger 7 First Command address */
+ uint32_t:3;
+ uint32_t T6INDEX:5; /* Trigger 6 First Command address */
+ uint32_t:3;
+ uint32_t T5INDEX:5; /* Trigger 5 First Command address */
+ uint32_t:3;
+ uint32_t T4INDEX:5; /* Trigger 4 First Command address */
+ } B;
+ } CTU_CLCR2_32B_tag;
+
+ typedef union { /* Trigger Handler Control Register 1 */
+ uint32_t R;
+ struct {
+ uint32_t:1;
+ uint32_t T3_E:1; /* Trigger 3 enable */
+ uint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */
+ uint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */
+ uint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */
+ uint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */
+ uint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */
+ uint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */
+ uint32_t:1;
+ uint32_t T2_E:1; /* Trigger 2 enable */
+ uint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */
+ uint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */
+ uint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */
+ uint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */
+ uint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */
+ uint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */
+ uint32_t:1;
+ uint32_t T1_E:1; /* Trigger 1 enable */
+ uint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */
+ uint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */
+ uint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */
+ uint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */
+ uint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */
+ uint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */
+ uint32_t:1;
+ uint32_t T0_E:1; /* Trigger 0 enable */
+ uint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */
+ uint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */
+ uint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */
+ uint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */
+ uint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */
+ uint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */
+ } B;
+ } CTU_THCR1_32B_tag;
+
+ typedef union { /* Trigger Handler Control Register 2 */
+ uint32_t R;
+ struct {
+ uint32_t:1;
+ uint32_t T7_E:1; /* Trigger 7 enable */
+ uint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */
+ uint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */
+ uint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */
+ uint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */
+ uint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */
+ uint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */
+ uint32_t:1;
+ uint32_t T6_E:1; /* Trigger 6 enable */
+ uint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */
+ uint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */
+ uint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */
+ uint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */
+ uint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */
+ uint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */
+ uint32_t:1;
+ uint32_t T5_E:1; /* Trigger 5 enable */
+ uint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */
+ uint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */
+ uint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */
+ uint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */
+ uint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */
+ uint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */
+ uint32_t:1;
+ uint32_t T4_E:1; /* Trigger 4 enable */
+ uint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */
+ uint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */
+ uint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */
+ uint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */
+ uint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */
+ uint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */
+ } B;
+ } CTU_THCR2_32B_tag;
+
+
+ /* Register layout for all registers CLR_DCM... */
+
+ typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
+ uint16_t R;
+ struct {
+ uint16_t CIR:1; /* Command Interrupt Request */
+ uint16_t LC:1; /* Last Command */
+ uint16_t CMS:1; /* Conversion Mode Selection */
+ uint16_t FIFO:3; /* FIFO for ADC A/B */
+ uint16_t:1;
+ uint16_t CHB:4; /* ADC unit B channel number */
+ uint16_t:1;
+ uint16_t CHA:4; /* ADC unit A channel number */
+ } B;
+ } CTU_CLR_DCM_16B_tag;
+
+
+ /* Register layout for all registers CLR_SCM... */
+
+ typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
+ uint16_t R;
+ struct {
+ uint16_t CIR:1; /* Command Interrupt Request */
+ uint16_t LC:1; /* Last Command */
+ uint16_t CMS:1; /* Conversion Mode Selection */
+ uint16_t FIFO:3; /* FIFO for ADC A/B */
+ uint16_t:4;
+ uint16_t SU:1; /* Selection ADC Unit */
+ uint16_t:1;
+ uint16_t CH:4; /* ADC unit channel number */
+ } B;
+ } CTU_CLR_SCM_16B_tag;
+
+
+ /* Register layout for all registers CLR... */
+
+
+ typedef union { /* Control Register */
+ uint16_t R;
+ struct {
+ uint16_t EMPTY_CLR7:1; /* Empty Clear 7 */
+ uint16_t EMPTY_CLR6:1; /* Empty Clear 6 */
+ uint16_t EMPTY_CLR5:1; /* Empty Clear 5 */
+ uint16_t EMPTY_CLR4:1; /* Empty Clear 4 */
+ uint16_t EMPTY_CLR3:1; /* Empty Clear 3 */
+ uint16_t EMPTY_CLR2:1; /* Empty Clear 2 */
+ uint16_t EMPTY_CLR1:1; /* Empty Clear 1 */
+ uint16_t EMPTY_CLR0:1; /* Empty Clear 0 */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */
+#else
+ uint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */
+#else
+ uint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */
+#else
+ uint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */
+#else
+ uint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */
+#else
+ uint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */
+#else
+ uint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */
+#else
+ uint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */
+#else
+ uint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */
+#endif
+ } B;
+ } CTU_CR_16B_tag;
+
+ typedef union { /* Control Register FIFO */
+ uint32_t R;
+ struct {
+ uint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */
+ uint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */
+ uint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */
+ uint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */
+ uint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */
+ } B;
+ } CTU_FCR_32B_tag;
+
+ typedef union { /* Threshold 1 Register */
+ uint32_t R;
+ struct {
+ uint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */
+ uint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */
+ uint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */
+ uint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */
+ } B;
+ } CTU_TH1_32B_tag;
+
+ typedef union { /* Threshold 2 Register */
+ uint32_t R;
+ struct {
+ uint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */
+ uint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */
+ uint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */
+ uint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */
+ } B;
+ } CTU_TH2_32B_tag;
+
+ typedef union { /* Status Register */
+ uint32_t R;
+ struct {
+ uint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */
+ uint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */
+ uint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */
+ uint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */
+ uint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */
+ uint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */
+ uint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */
+ uint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */
+ uint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */
+ uint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */
+ uint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */
+ uint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */
+ uint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */
+ uint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */
+ uint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */
+ uint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */
+ uint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */
+ uint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */
+ } B;
+ } CTU_STS_32B_tag;
+
+
+ /* Register layout for all registers FR... */
+
+ typedef union { /* FIFO Right Aligned register */
+ uint32_t R;
+ struct {
+ uint32_t:11;
+ uint32_t ADC:1; /* ADC Unit */
+ uint32_t N_CH:4; /* Number Channel */
+ uint32_t:4;
+ uint32_t DATA:12; /* Data Fifo */
+ } B;
+ } CTU_FR_32B_tag;
+
+
+ /* Register layout for all registers FL... */
+
+ typedef union { /* FIFO Left Aligned register */
+ uint32_t R;
+ struct {
+ uint32_t:11;
+ uint32_t ADC:1; /* ADC Unit */
+ uint32_t N_CH:4; /* Number Channel */
+ uint32_t:1;
+ uint32_t DATA:12; /* Data Fifo */
+ uint32_t:3;
+ } B;
+ } CTU_FL_32B_tag;
+
+ typedef union { /* CTU Error Flag Register */
+ uint16_t R;
+ struct {
+ uint16_t:3;
+ uint16_t CS:1; /* Counter Status */
+ uint16_t ET_OE:1; /* ExtTrigger Generation Overrun */
+ uint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */
+ uint16_t T4_OE:1; /* Timer4 Generation Overrun */
+ uint16_t T3_OE:1; /* Timer3 Generation Overrun */
+ uint16_t T2_OE:1; /* Timer2 Generation Overrun */
+ uint16_t T1_OE:1; /* Timer1 Generation Overrun */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t ADC_OE:1; /* ADC Command Generation Overrun */
+#else
+ uint16_t ADCOE:1; /* ADC Command Generation Overrun */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t TGS_OSM:1; /* TGS Overrun */
+#else
+ uint16_t TGSOSM:1; /* TGS Overrun */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_O:1; /* MRS Overrun */
+#else
+ uint16_t MRSO:1; /* TGS Overrun */
+#endif
+ uint16_t ICE:1; /* Invalid Command Error */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t SM_TO:1; /* Trigger Overrun */
+#else
+ uint16_t SMTO:1; /* Trigger Overrun */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_RE:1; /* MRS Reload Error */
+#else
+ uint16_t MRSRE:1; /* MRS Reload Error */
+#endif
+ } B;
+ } CTU_CTUEFR_16B_tag;
+
+ typedef union { /* CTU Interrupt Flag Register */
+ uint16_t R;
+ struct {
+ uint16_t:4;
+ uint16_t S_E_B:1; /* Slice time OK */
+ uint16_t S_E_A:1; /* Slice time OK */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t ADC_I:1; /* ADC Command Interrupt Flag */
+#else
+ uint16_t ADC:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T7_I:1; /* Trigger 7 Interrupt Flag */
+#else
+ uint16_t T7:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T6_I:1; /* Trigger 6 Interrupt Flag */
+#else
+ uint16_t T6:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T5_I:1; /* Trigger 5 Interrupt Flag */
+#else
+ uint16_t T5:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T4_I:1; /* Trigger 4 Interrupt Flag */
+#else
+ uint16_t T4:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T3_I:1; /* Trigger 3 Interrupt Flag */
+#else
+ uint16_t T3:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T2_I:1; /* Trigger 2 Interrupt Flag */
+#else
+ uint16_t T2:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T1_I:1; /* Trigger 1 Interrupt Flag */
+#else
+ uint16_t T1:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T0_I:1; /* Trigger 0 Interrupt Flag */
+#else
+ uint16_t T0:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_I:1; /* MRS Interrupt Flag */
+#else
+ uint16_t MRS:1;
+#endif
+ } B;
+ } CTU_CTUIFR_16B_tag;
+
+ typedef union { /* CTU Interrupt/DMA Register */
+ uint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T7_I:1; /* Trigger 7 Interrupt Enable */
+#else
+ uint16_t T7IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T6_I:1; /* Trigger 6 Interrupt Enable */
+#else
+ uint16_t T6IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T5_I:1; /* Trigger 5 Interrupt Enable */
+#else
+ uint16_t T5IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T4_I:1; /* Trigger 4 Interrupt Enable */
+#else
+ uint16_t T4IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T3_I:1; /* Trigger 3 Interrupt Enable */
+#else
+ uint16_t T3IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T2_I:1; /* Trigger 2 Interrupt Enable */
+#else
+ uint16_t T2IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T1_I:1; /* Trigger 1 Interrupt Enable */
+#else
+ uint16_t T1IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T0_I:1; /* Trigger 0 Interrupt Enable */
+#else
+ uint16_t T0IE:1;
+#endif
+ uint16_t:2;
+ uint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */
+ uint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */
+ uint16_t DMA_DE:1; /* DMA and gre bit */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_DMAE:1; /* DMA Transfer Enable */
+#else
+ uint16_t MRSDMAE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_IE:1; /* MRS Interrupt Enable */
+#else
+ uint16_t MRSIE:1;
+#endif
+ uint16_t IEE:1; /* Interrupt Error Enable */
+ } B;
+ } CTU_CTUIR_16B_tag;
+
+ typedef union { /* Control On-Time Register */
+ uint16_t R;
+ struct {
+ uint16_t:8;
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */
+#else
+ uint16_t COTR:8;
+#endif
+ } B;
+ } CTU_COTR_16B_tag;
+
+ typedef union { /* CTU Control Register */
+ uint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T7_SG:1; /* Trigger 7 Software Generated */
+#else
+ uint16_t T7SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T6_SG:1; /* Trigger 6 Software Generated */
+#else
+ uint16_t T6SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T5_SG:1; /* Trigger 5 Software Generated */
+#else
+ uint16_t T5SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T4_SG:1; /* Trigger 4 Software Generated */
+#else
+ uint16_t T4SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T3_SG:1; /* Trigger 3 Software Generated */
+#else
+ uint16_t T3SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T2_SG:1; /* Trigger 2 Software Generated */
+#else
+ uint16_t T2SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T1_SG:1; /* Trigger 1 Software Generated */
+#else
+ uint16_t T1SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t T0_SG:1; /* Trigger 0 Software Generated */
+#else
+ uint16_t T0SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */
+#else
+ uint16_t CTUADCRESET:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t CTU_ODIS:1; /* CTU Output Disable */
+#else
+ uint16_t CTUODIS:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t FILTER_EN:1; /* Synchronize Filter Register value */
+#else
+ uint16_t FILTERENABLE:1;
+#endif
+ uint16_t CGRE:1; /* Clear GRE */
+ uint16_t FGRE:1; /* GRE Flag */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t MRS_SG:1; /* MRS Software Generated */
+#else
+ uint16_t MRSSG:1;
+#endif
+ uint16_t GRE:1; /* General Reload Enable */
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t TGSISR_RE:1; /* TGSISR Reload Enable */
+#else
+ uint16_t TGSISRRE:1;
+#endif
+ } B;
+ } CTU_CTUCR_16B_tag;
+
+ typedef union { /* CTU Digital Filter Register */
+ uint16_t R;
+ struct {
+ uint16_t:8;
+#ifndef USE_FIELD_ALIASES_CTU
+ uint16_t FILTER_VALUE:8; /* Filter Value */
+#else
+ uint16_t FILTERVALUE:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } CTU_FILTER_16B_tag;
+
+ typedef union { /* CTU Expected A Value Register */
+ uint16_t R;
+ struct {
+ uint16_t EXPECTED_A_VALUE:16; /* Expected A Value */
+ } B;
+ } CTU_EXPECTED_A_16B_tag;
+
+ typedef union { /* CTU Expected B Value Register */
+ uint16_t R;
+ struct {
+ uint16_t EXPECTED_B_VALUE:16; /* Expected B Value */
+ } B;
+ } CTU_EXPECTED_B_16B_tag;
+
+ typedef union { /* CTU Counter Range Register */
+ uint16_t R;
+ struct {
+ uint16_t:8;
+ uint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */
+ } B;
+ } CTU_CNT_RANGE_16B_tag;
+
+
+ /* Register layout for generated register(s) FRA... */
+
+ typedef union { /* */
+ uint32_t R;
+ } CTU_FRA_32B_tag;
+
+
+ /* Register layout for generated register(s) FLA... */
+
+ typedef union { /* */
+ uint32_t R;
+ } CTU_FLA_32B_tag;
+
+
+
+ typedef struct CTU_struct_tag { /* start of CTU_tag */
+ /* Trigger Generator Subunit Input Selection register */
+ CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */
+ /* Trigger Generator Subunit Control Register */
+ CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */
+ union {
+ CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */
+
+ struct {
+ CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */
+ CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */
+ CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */
+ CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */
+ CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */
+ CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */
+ CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */
+ CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */
+ };
+
+ };
+ /* TGS Counter Compare Register */
+ CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */
+ /* TGS Counter Reload Register */
+ CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */
+ int8_t CTU_reserved_001A[2];
+ /* Commands List Control Register 1 */
+ CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */
+ /* Commands List Control Register 2 */
+ CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */
+ /* Trigger Handler Control Register 1 */
+ CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */
+ /* Trigger Handler Control Register 2 */
+ CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */
+ union {
+ /* Command List Register. View: BIT13, BIT9 */
+ CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */
+
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
+ CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */
+
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
+ CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */
+
+ struct {
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
+ CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */
+ };
+
+ struct {
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
+ CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */
+ };
+
+ };
+ int8_t CTU_reserved_005C[16];
+ /* Control Register */
+ CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */
+ int8_t CTU_reserved_006E[2];
+ /* Control Register FIFO */
+ CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */
+ /* Threshold 1 Register */
+ CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */
+ /* Threshold 2 Register */
+ CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */
+ union {
+ /* Status Register */
+ CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */
+
+ CTU_STS_32B_tag STATUS; /* deprecated - please avoid */
+
+ };
+ union {
+ CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ /* FIFO Right Aligned register */
+ CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ struct {
+ /* FIFO Right Aligned register */
+ CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */
+ CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */
+ CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */
+ CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */
+ CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */
+ CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */
+ CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */
+ CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */
+ };
+
+ };
+ union {
+ CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ /* FIFO Left Aligned register */
+ CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ struct {
+ /* FIFO Left Aligned register */
+ CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */
+ CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */
+ CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */
+ CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */
+ CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */
+ CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */
+ CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */
+ CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */
+ };
+
+ };
+ /* CTU Error Flag Register */
+ CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */
+ /* CTU Interrupt Flag Register */
+ CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */
+ /* CTU Interrupt/DMA Register */
+ CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */
+ /* Control On-Time Register */
+ CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */
+ /* CTU Control Register */
+ CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */
+ union {
+ /* CTU Digital Filter Register */
+ CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */
+
+ CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */
+
+ };
+ /* CTU Expected A Value Register */
+ CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */
+
+ /* CTU Expected B Value Register */
+ CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */
+ /* CTU Counter Range Register */
+ CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */
+ } CTU_tag;
+
+
+#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: mcTIMER */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers COMP1... */
+
+ typedef union { /* Compare Register 1 */
+ uint16_t R;
+ struct {
+ uint16_t COMP1:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_COMP1_16B_tag;
+
+
+ /* Register layout for all registers COMP2... */
+
+ typedef union { /* Compare Register 2 */
+ uint16_t R;
+ struct {
+ uint16_t COMP2:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_COMP2_16B_tag;
+
+
+ /* Register layout for all registers CAPT1... */
+
+ typedef union { /* Capture Register 1 */
+ uint16_t R;
+ struct {
+ uint16_t CAPT1:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CAPT1_16B_tag;
+
+
+ /* Register layout for all registers CAPT2... */
+
+ typedef union { /* Capture Register 2 */
+ uint16_t R;
+ struct {
+ uint16_t CAPT2:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CAPT2_16B_tag;
+
+
+ /* Register layout for all registers LOAD... */
+
+ typedef union { /* Load Register */
+ uint16_t R;
+ struct {
+ uint16_t LOAD:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_LOAD_16B_tag;
+
+
+ /* Register layout for all registers HOLD... */
+
+ typedef union { /* Hold Register */
+ uint16_t R;
+ struct {
+ uint16_t HOLD:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_HOLD_16B_tag;
+
+
+ /* Register layout for all registers CNTR... */
+
+ typedef union { /* Counter Register */
+ uint16_t R;
+ struct {
+ uint16_t CNTR:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CNTR_16B_tag;
+
+
+ /* Register layout for all registers CTRL1... */
+
+ typedef union { /* Control Register */
+ uint16_t R;
+ struct {
+ uint16_t CNTMODE:3; /* Count Mode */
+ uint16_t PRISRC:5; /* Primary Count Source */
+ uint16_t ONCE:1; /* Count Once */
+ uint16_t LENGTH:1; /* Count Length */
+ uint16_t DIR:1; /* Count Direction */
+ uint16_t SECSRC:5; /* Secondary Count Source */
+ } B;
+ } mcTIMER_CTRL1_16B_tag;
+
+
+ /* Register layout for all registers CTRL2... */
+
+ typedef union { /* Control Register 2 */
+ uint16_t R;
+ struct {
+ uint16_t OEN:1; /* Output Enable */
+ uint16_t RDNT:1; /* Redundant Channel Enable */
+ uint16_t INPUT:1; /* External Input Signal */
+ uint16_t VAL:1; /* Forced OFLAG Value */
+ uint16_t FORCE:1; /* Force the OFLAG output */
+ uint16_t COFRC:1; /* Co-channel OFLAG Force */
+ uint16_t COINIT:2; /* Co-channel Initialization */
+ uint16_t SIPS:1; /* Secondary Source Input Polarity Select */
+ uint16_t PIPS:1; /* Primary Source Input Polarity Select */
+ uint16_t OPS:1; /* Output Polarity Select */
+ uint16_t MSTR:1; /* Master Mode */
+ uint16_t OUTMODE:4; /* Output Mode */
+ } B;
+ } mcTIMER_CTRL2_16B_tag;
+
+
+ /* Register layout for all registers CTRL3... */
+
+ typedef union { /* Control Register 3 */
+ uint16_t R;
+ struct {
+ uint16_t STPEN:1; /* Stop Action Enable */
+ uint16_t ROC:2; /* Reload On Capture */
+ uint16_t FMODE:1; /* Fault Safing Mode */
+ uint16_t FDIS:4; /* Fault Disable Mask */
+ uint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */
+ uint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */
+ uint16_t DBGEN:2; /* Debug Actions Enable */
+ } B;
+ } mcTIMER_CTRL3_16B_tag;
+
+
+ /* Register layout for all registers STS... */
+
+ typedef union { /* Status Register */
+ uint16_t R;
+ struct {
+ uint16_t:6;
+ uint16_t WDF:1; /* Watchdog Time-out Flag */
+ uint16_t RCF:1; /* Redundant Channel Flag */
+ uint16_t ICF2:1; /* Input Capture 2 Flag */
+ uint16_t ICF1:1; /* Input Capture 1 Flag */
+ uint16_t IEHF:1; /* Input Edge High Flag */
+ uint16_t IELF:1; /* Input Edge Low Flag */
+ uint16_t TOF:1; /* Timer Overflow Flag */
+ uint16_t TCF2:1; /* Timer Compare 2 Flag */
+ uint16_t TCF1:1; /* Timer Compare 1 Flag */
+ uint16_t TCF:1; /* Timer Compare Flag */
+ } B;
+ } mcTIMER_STS_16B_tag;
+
+
+ /* Register layout for all registers INTDMA... */
+
+ typedef union { /* Interrupt and DMA Enable Register */
+ uint16_t R;
+ struct {
+ uint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */
+ uint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */
+ uint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */
+ uint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */
+ uint16_t:2;
+ uint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */
+ uint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */
+ uint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */
+ uint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */
+ uint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */
+ uint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */
+ uint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */
+ uint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */
+ uint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */
+ uint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */
+ } B;
+ } mcTIMER_INTDMA_16B_tag;
+
+
+ /* Register layout for all registers CMPLD1... */
+
+ typedef union { /* Comparator Load Register 1 */
+ uint16_t R;
+ struct {
+ uint16_t CMPLD1:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CMPLD1_16B_tag;
+
+
+ /* Register layout for all registers CMPLD2... */
+
+ typedef union { /* Comparator Load Register 2 */
+ uint16_t R;
+ struct {
+ uint16_t CMPLD2:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CMPLD2_16B_tag;
+
+
+ /* Register layout for all registers CCCTRL... */
+
+ typedef union { /* Compare and Capture Control Register */
+ uint16_t R;
+ struct {
+ uint16_t CLC2:3; /* Compare Load Control 2 */
+ uint16_t CLC1:3; /* Compare Load Control 1 */
+ uint16_t CMPMODE:2; /* Compare Mode */
+ uint16_t CPT2MODE:2; /* Capture 2 Mode Control */
+ uint16_t CPT1MODE:2; /* Capture 1 Mode Control */
+ uint16_t CFWM:2; /* Capture FIFO Water Mark */
+ uint16_t ONESHOT:1; /* One Shot Capture Mode */
+ uint16_t ARM:1; /* Arm Capture */
+ } B;
+ } mcTIMER_CCCTRL_16B_tag;
+
+
+ /* Register layout for all registers FILT... */
+
+ typedef union { /* Input Filter Register */
+ uint16_t R;
+ struct {
+ uint16_t:5;
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ uint16_t FILT_CNT:3; /* Input Filter Sample Count */
+#else
+ uint16_t FILTCNT:3; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ uint16_t FILT_PER:8; /* Input Filter Sample Period */
+#else
+ uint16_t FILTPER:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcTIMER_FILT_16B_tag;
+
+ typedef union { /* Watchdog Time-out Register */
+ uint16_t R;
+ struct {
+ uint16_t WDTOL:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_WDTOL_16B_tag;
+
+ typedef union { /* Watchdog Time-out Register */
+ uint16_t R;
+ struct {
+ uint16_t WDTOH:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_WDTOH_16B_tag;
+
+ typedef union { /* Fault Control Register */
+ uint16_t R;
+ struct {
+ uint16_t:3;
+ uint16_t FTEST:1; /* Fault Test */
+ uint16_t FIE:4; /* Fault Interrupt Enable */
+ uint16_t:4;
+ uint16_t FLVL:4; /* Fault Active Logic Level */
+ } B;
+ } mcTIMER_FCTRL_16B_tag;
+
+ typedef union { /* Fault Status Register */
+ uint16_t R;
+ struct {
+ uint16_t:4;
+ uint16_t FFPIN:4; /* Filtered Fault Pin */
+ uint16_t:4;
+ uint16_t FFLAG:4; /* Fault Flag */
+ } B;
+ } mcTIMER_FSTS_16B_tag;
+
+ typedef union { /* Fault Filter Registers */
+ uint16_t R;
+ struct {
+ uint16_t:5;
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ uint16_t FFPIN:3; /* Fault Filter Sample Count */
+#else
+ uint16_t FFILTCNT:3; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ uint16_t FFILT_PER:8; /* Fault Filter Sample Period */
+#else
+ uint16_t FFILTPER:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcTIMER_FFILT_16B_tag;
+
+ typedef union { /* Channel Enable Registers */
+ uint16_t R;
+ struct {
+ uint16_t:8;
+ uint16_t ENBL:8; /* Timer Channel Enable */
+ } B;
+ } mcTIMER_ENBL_16B_tag;
+
+ typedef union { /* DMA Request 0 Select Registers */
+ uint16_t R;
+ struct {
+ uint16_t:11;
+ uint16_t DREQ0V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ0_16B_tag;
+
+ typedef union { /* DMA Request 1 Select Registers */
+ uint16_t R;
+ struct {
+ uint16_t:11;
+ uint16_t DREQ1V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ1_16B_tag;
+
+ typedef union { /* DMA Request 2 Select Registers */
+ uint16_t R;
+ struct {
+ uint16_t:11;
+ uint16_t DREQ2V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ2_16B_tag;
+
+ typedef union { /* DMA Request 3 Select Registers */
+ uint16_t R;
+ struct {
+ uint16_t:11;
+ uint16_t DREQ3V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ3_16B_tag;
+
+
+ /* Register layout for generated register(s) DREQ... */
+
+ typedef union { /* */
+ uint16_t R;
+ } mcTIMER_DREQ_16B_tag;
+
+
+ typedef struct mcTIMER_CHANNEL_struct_tag {
+
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */
+ union {
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */
+ mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
+ };
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */
+
+ } mcTIMER_CHANNEL_tag;
+
+
+ typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */
+ union {
+ /* Register set CHANNEL */
+ mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */
+
+ struct {
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */
+ };
+
+ };
+ int8_t mcTIMER_reserved_00C0[64];
+ /* Watchdog Time-out Register */
+ mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */
+ /* Watchdog Time-out Register */
+ mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */
+ /* Fault Control Register */
+ mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */
+ /* Fault Status Register */
+ mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */
+ /* Fault Filter Registers */
+ mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */
+ int8_t mcTIMER_reserved_010A[2];
+ /* Channel Enable Registers */
+ mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */
+ int8_t mcTIMER_reserved_010E_C[2];
+ union {
+ mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */
+
+ struct {
+ /* DMA Request 0 Select Registers */
+ mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */
+ /* DMA Request 1 Select Registers */
+ mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */
+ /* DMA Request 2 Select Registers */
+ mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */
+ /* DMA Request 3 Select Registers */
+ mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */
+ };
+
+ };
+ } mcTIMER_tag;
+
+
+#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL)
+#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL)
+#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: mcPWM */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers CNT... */
+
+ typedef union { /* Counter Register */
+ uint16_t R;
+ } mcPWM_CNT_16B_tag;
+
+
+ /* Register layout for all registers INIT... */
+
+ typedef union { /* Initial Counter Register */
+ uint16_t R;
+ } mcPWM_INIT_16B_tag;
+
+
+ /* Register layout for all registers CTRL2... */
+
+ typedef union { /* Control 2 Register */
+ uint16_t R;
+ struct {
+ uint16_t DBGEN:1; /* Debug Enable */
+ uint16_t WAITEN:1; /* Wait Enable */
+ uint16_t INDEP:1; /* Independent or Complementary Pair Operation */
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t PWM23_INIT:1; /* PWM23 Initial Value */
+#else
+ uint16_t PWMA_INIT:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t PWM45_INIT:1; /* PWM23 Initial Value */
+#else
+ uint16_t PWMB_INIT:1; /* deprecated name - please avoid */
+#endif
+ uint16_t PWMX_INIT:1; /* PWMX Initial Value */
+ uint16_t INIT_SEL:2; /* Initialization Control Select */
+ uint16_t FRCEN:1; /* Force Initialization enable */
+ uint16_t FORCE:1; /* Force Initialization */
+ uint16_t FORCE_SEL:3; /* Force Source Select */
+ uint16_t RELOAD_SEL:1; /* Reload Source Select */
+ uint16_t CLK_SEL:2; /* Clock Source Select */
+ } B;
+ } mcPWM_CTRL2_16B_tag;
+
+
+ /* Register layout for all registers CTRL1... */
+
+ typedef union { /* Control Register */
+ uint16_t R;
+ struct {
+ uint16_t LDFQ:4; /* Load Frequency */
+ uint16_t HALF:1; /* Half Cycle Reload */
+ uint16_t FULL:1; /* Full Cycle Reload */
+ uint16_t DT:2; /* Deadtime */
+ uint16_t:1;
+ uint16_t PRSC:3; /* Prescaler */
+ uint16_t:1;
+ uint16_t LDMOD:1; /* Load Mode Select */
+ uint16_t:1;
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t DBL_EN:1; /* Double Switching Enable */
+#else
+ uint16_t DBLEN:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcPWM_CTRL1_16B_tag;
+
+
+ /* Register layout for all registers VAL_0... */
+
+ typedef union { /* Value Register 0 */
+ uint16_t R;
+ } mcPWM_VAL_0_16B_tag;
+
+
+ /* Register layout for all registers VAL_1... */
+
+ typedef union { /* Value Register 1 */
+ uint16_t R;
+ } mcPWM_VAL_1_16B_tag;
+
+
+ /* Register layout for all registers VAL_2... */
+
+ typedef union { /* Value Register 2 */
+ uint16_t R;
+ } mcPWM_VAL_2_16B_tag;
+
+
+ /* Register layout for all registers VAL_3... */
+
+ typedef union { /* Value Register 3 */
+ uint16_t R;
+ } mcPWM_VAL_3_16B_tag;
+
+
+ /* Register layout for all registers VAL_4... */
+
+ typedef union { /* Value Register 4 */
+ uint16_t R;
+ } mcPWM_VAL_4_16B_tag;
+
+
+ /* Register layout for all registers VAL_5... */
+
+ typedef union { /* Value Register 5 */
+ uint16_t R;
+ } mcPWM_VAL_5_16B_tag;
+
+ /* Register layout for all registers OCTRL... */
+
+ typedef union { /* Output Control Register */
+ uint16_t R;
+ struct {
+ uint16_t PWMA_IN:1; /* PWMA Input */
+ uint16_t PWMB_IN:1; /* PWMB Input */
+ uint16_t PWMX_IN:1; /* PWMX Input */
+ uint16_t:2;
+ uint16_t POLA:1; /* PWMA Output Polarity */
+ uint16_t POLB:1; /* PWMB Output Polarity */
+ uint16_t POLX:1; /* PWMX Output Polarity */
+ uint16_t:2;
+ uint16_t PWMAFS:2; /* PWMA Fault State */
+ uint16_t PWMBFS:2; /* PWMB Fault State */
+ uint16_t PWMXFS:2; /* PWMX Fault State */
+ } B;
+ } mcPWM_OCTRL_16B_tag;
+
+
+ /* Register layout for all registers STS... */
+
+ typedef union { /* Status Register */
+ uint16_t R;
+ struct {
+ uint16_t:1;
+ uint16_t RUF:1; /* Registers Updated Flag */
+ uint16_t REF:1; /* Reload Error Flag */
+ uint16_t RF:1; /* Reload Flag */
+ uint16_t CFA1:1; /* Capture Flag A1 */
+ uint16_t CFA0:1; /* Capture Flag A0 */
+ uint16_t CFB1:1; /* Capture Flag B1 */
+ uint16_t CFB0:1; /* Capture Flag B0 */
+ uint16_t CFX1:1; /* Capture Flag X1 */
+ uint16_t CFX0:1; /* Capture Flag X0 */
+ uint16_t CMPF:6; /* Compare Flags */
+ } B;
+ } mcPWM_STS_16B_tag;
+
+
+ /* Register layout for all registers INTEN... */
+
+ typedef union { /* Interrupt Enable Registers */
+ uint16_t R;
+ struct {
+ uint16_t:2;
+ uint16_t REIE:1; /* Reload Error Interrupt Enable */
+ uint16_t RIE:1; /* Reload Interrupt Enable */
+ uint16_t CA1IE:1; /* Capture A1 Interrupt Enable */
+ uint16_t CA0IE:1; /* Capture A0 Interrupt Enable */
+ uint16_t CB1IE:1; /* Capture B1 Interrupt Enable */
+ uint16_t CB0IE:1; /* Capture B0 Interrupt Enable */
+ uint16_t CX1IE:1; /* Capture X1 Interrupt Enable */
+ uint16_t CX0IE:1; /* Capture X0 Interrupt Enable */
+ uint16_t CMPIE:6; /* Compare Interrupt Enables */
+ } B;
+ } mcPWM_INTEN_16B_tag;
+
+
+ /* Register layout for all registers DMAEN... */
+
+ typedef union { /* DMA Enable Registers */
+ uint16_t R;
+ struct {
+ uint16_t:6;
+ uint16_t VALDE:1; /* Value Register DMA Enable */
+ uint16_t FAND:1; /* FIFO Watermark AND Control */
+ uint16_t CAPTDE:2; /* Capture DMA Enable Source Select */
+ uint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */
+ uint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */
+ uint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */
+ uint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */
+ uint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */
+ uint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */
+ } B;
+ } mcPWM_DMAEN_16B_tag;
+
+
+ /* Register layout for all registers TCTRL... */
+
+ typedef union { /* Output Trigger Control Registers */
+ uint16_t R;
+ struct {
+ uint16_t:10;
+ uint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */
+ } B;
+ } mcPWM_TCTRL_16B_tag;
+
+
+ /* Register layout for all registers DISMAP... */
+
+ typedef union { /* Fault Disable Mapping Registers */
+ uint16_t R;
+ struct {
+ uint16_t:4;
+ uint16_t DISX:4; /* PWMX Fault Disable Mask */
+ uint16_t DISB:4; /* PWMB Fault Disable Mask */
+ uint16_t DISA:4; /* PWMA Fault Disable Mask */
+ } B;
+ } mcPWM_DISMAP_16B_tag;
+
+
+ /* Register layout for all registers DTCNT0... */
+
+ typedef union { /* Deadtime Count Register 0 */
+ uint16_t R;
+ struct {
+ uint16_t:5;
+ uint16_t DTCNT0:11; /* Deadtime Count Register 0 */
+ } B;
+ } mcPWM_DTCNT0_16B_tag;
+
+
+ /* Register layout for all registers DTCNT1... */
+
+ typedef union { /* Deadtime Count Register 1 */
+ uint16_t R;
+ struct {
+ uint16_t:5;
+ uint16_t DTCNT1:11; /* Deadtime Count Register 1 */
+ } B;
+ } mcPWM_DTCNT1_16B_tag;
+
+ /* Register layout for all registers CAPTCTRLX... */
+
+ typedef union { /* Capture Control X Register */
+ uint16_t R;
+ struct {
+ uint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */
+ uint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */
+ uint16_t CFXWM:2; /* Capture X FIFOs Water Mark */
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t EDGCNTXEN:1; /* Edge Counter X Enable */
+#else
+ uint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t INPSELX:1; /* Input Select X */
+#else
+ uint16_t INP_SELX:1; /* deprecated name - please avoid */
+#endif
+ uint16_t EDGX1:2; /* Edge X 1 */
+ uint16_t EDGX0:2; /* Edge X 0 */
+ uint16_t ONESHOTX:1; /* One Shot Mode X */
+ uint16_t ARMX:1; /* Arm X */
+ } B;
+ } mcPWM_CAPTCTRLX_16B_tag;
+
+
+ /* Register layout for all registers CAPTCMPX... */
+
+ typedef union { /* Capture Compare X Register */
+ uint16_t R;
+ struct {
+ uint16_t EDGCNTX:8; /* Edge Counter X */
+ uint16_t EDGCMPX:8; /* Edge Compare X */
+ } B;
+ } mcPWM_CAPTCMPX_16B_tag;
+
+
+ /* Register layout for all registers CVAL0... */
+
+ typedef union { /* Capture Value 0 Register */
+ uint16_t R;
+ struct {
+ uint16_t CAPTVAL0:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL0_16B_tag;
+
+
+ /* Register layout for all registers CVAL0CYC... */
+
+ typedef union { /* Capture Value 0 Cycle Register */
+ uint16_t R;
+ struct {
+ uint16_t:12;
+ uint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */
+ } B;
+ } mcPWM_CVAL0CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL1... */
+
+ typedef union { /* Capture Value 1 Register */
+ uint16_t R;
+ struct {
+ uint16_t CAPTVAL1:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL1_16B_tag;
+
+
+ /* Register layout for all registers CVAL1CYC... */
+
+ typedef union { /* Capture Value 1 Cycle Register */
+ uint16_t R;
+ struct {
+ uint16_t:12;
+ uint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */
+ } B;
+ } mcPWM_CVAL1CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL3... */
+
+ typedef union { /* Capture Value 3 Register */
+ uint16_t R;
+ struct {
+ uint16_t CAPTVAL3:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL3_16B_tag;
+
+
+ /* Register layout for all registers CVAL3CYC... */
+
+ typedef union { /* Capture Value 3 Cycle Register */
+ uint16_t R;
+ struct {
+ uint16_t:12;
+ uint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */
+ } B;
+ } mcPWM_CVAL3CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL4... */
+
+ typedef union { /* Capture Value 4 Register */
+ uint16_t R;
+ struct {
+ uint16_t CAPTVAL4:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL4_16B_tag;
+
+
+ /* Register layout for all registers CVAL4CYC... */
+
+ typedef union { /* Capture Value 4 Cycle Register */
+ uint16_t R;
+ struct {
+ uint16_t:12;
+ uint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */
+ } B;
+ } mcPWM_CVAL4CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL5... */
+
+ typedef union { /* Capture Value 5 Register */
+ uint16_t R;
+ struct {
+ uint16_t CAPTVAL5:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL5_16B_tag;
+
+
+ /* Register layout for all registers CVAL5CYC... */
+
+ typedef union { /* Capture Value 5 Cycle Register */
+ uint16_t R;
+ struct {
+ uint16_t:12;
+ uint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */
+ } B;
+ } mcPWM_CVAL5CYC_16B_tag;
+
+ typedef union { /* Output Enable Register */
+ uint16_t R;
+ struct {
+ uint16_t:4;
+ uint16_t PWMA_EN:4; /* PWMA Output Enables */
+ uint16_t PWMB_EN:4; /* PWMB Output Enables */
+ uint16_t PWMX_EN:4; /* PWMX Output Enables */
+ } B;
+ } mcPWM_OUTEN_16B_tag;
+
+ typedef union { /* Mask Register */
+ uint16_t R;
+ struct {
+ uint16_t:4;
+ uint16_t MASKA:4; /* PWMA Masks */
+ uint16_t MASKB:4; /* PWMB Masks */
+ uint16_t MASKX:4; /* PWMX Masks */
+ } B;
+ } mcPWM_MASK_16B_tag;
+
+ typedef union { /* Software Controlled Output Register */
+ uint16_t R;
+ struct {
+ uint16_t:8;
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT23_3:1; /* Software Controlled Output 23_3 */
+#else
+ uint16_t OUTA_3:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT45_3:1; /* Software Controlled Output 45_3 */
+#else
+ uint16_t OUTB_3:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT23_2:1; /* Software Controlled Output 23_2 */
+#else
+ uint16_t OUTA_2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT45_2:1; /* Software Controlled Output 45_2 */
+#else
+ uint16_t OUTB_2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT23_1:1; /* Software Controlled Output 23_1 */
+#else
+ uint16_t OUTA_1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT45_1:1; /* Software Controlled Output 45_1 */
+#else
+ uint16_t OUTB_1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT23_0:1; /* Software Controlled Output 23_0 */
+#else
+ uint16_t OUTA_0:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t OUT45_0:1; /* Software Controlled Output 45_0 */
+#else
+ uint16_t OUTB_0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcPWM_SWCOUT_16B_tag;
+
+ typedef union { /* Deadtime Source Select Register */
+ uint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL23_3:2; /* PWM23_3 Control Select */
+#else
+ uint16_t SELA_3:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL45_3:2; /* PWM45_3 Control Select */
+#else
+ uint16_t SELB_3:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL23_2:2; /* PWM23_2 Control Select */
+#else
+ uint16_t SELA_2:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL45_2:2; /* PWM45_2 Control Select */
+#else
+ uint16_t SELB_2:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL23_1:2; /* PWM23_1 Control Select */
+#else
+ uint16_t SELA_1:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL45_1:2; /* PWM45_1 Control Select */
+#else
+ uint16_t SELB_1:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL23_0:2; /* PWM23_0 Control Select */
+#else
+ uint16_t SELA_0:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t SEL45_0:2; /* PWM45_0 Control Select */
+#else
+ uint16_t SELB_0:2; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcPWM_DTSRCSEL_16B_tag;
+
+ typedef union { /* Master Control Register */
+ uint16_t R;
+ struct {
+ uint16_t IPOL:4; /* Current Polarity */
+ uint16_t RUN:4; /* Run */
+#ifndef USE_FIELD_ALIASES_mcPWM
+ uint16_t CLOK:4; /* Clear Load Okay */
+#else
+ uint16_t CLDOK:4; /* deprecated name - please avoid */
+#endif
+ uint16_t LDOK:4; /* Load Okay */
+ } B;
+ } mcPWM_MCTRL_16B_tag;
+
+ typedef union { /* Fault Control Register */
+ uint16_t R;
+ struct {
+ uint16_t FLVL:4; /* Fault Level */
+ uint16_t FAUTO:4; /* Automatic Fault Clearing */
+ uint16_t FSAFE:4; /* Fault Safety Mode */
+ uint16_t FIE:4; /* Fault Interrupt Enables */
+ } B;
+ } mcPWM_FCTRL_16B_tag;
+
+ typedef union { /* Fault Status Register */
+ uint16_t R;
+ struct {
+ uint16_t:3;
+ uint16_t FTEST:1; /* Fault Test */
+ uint16_t FFPIN:4; /* Filtered Fault Pins */
+ uint16_t:4;
+ uint16_t FFLAG:4; /* Fault Flags */
+ } B;
+ } mcPWM_FSTS_16B_tag;
+
+ typedef union { /* Fault Filter Register */
+ uint16_t R;
+ struct {
+ uint16_t:5;
+ uint16_t FILT_CNT:3; /* Fault Filter Count */
+ uint16_t FILT_PER:8; /* Fault Filter Period */
+ } B;
+ } mcPWM_FFILT_16B_tag;
+
+
+ /* Register layout for generated register(s) VAL... */
+
+ typedef union { /* */
+ uint16_t R;
+ } mcPWM_VAL_16B_tag;
+
+
+ typedef struct mcPWM_SUBMOD_struct_tag {
+
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */
+ union {
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */
+ mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
+ };
+ /* Value Register 0 */
+
+ union {
+
+ struct {
+
+ mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */
+
+ };
+
+ mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */
+
+ };
+ int8_t mcPWM_reserved_0014[4];
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */
+ /* Capture Control A Register */
+ int8_t mcPWM_reserved_0028[8];
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */
+ union {
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */
+ mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */
+ };
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */
+ union {
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */
+ mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */
+ };
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */
+ union {
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */
+ mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */
+ };
+ /* Capture Value 2 Register */
+ int8_t mcPWM_SUBMOD_reserved_003C[16];
+ int8_t mcPWM_SUBMOD_reserved_004C[4];
+
+ } mcPWM_SUBMOD_tag;
+
+
+ typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */
+ union {
+ /* Register set SUBMOD */
+ mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */
+
+ mcPWM_SUBMOD_tag SUB[4]; /* offset: 0x0000 (0x0050 x 4) */
+
+ struct {
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */
+ int8_t mcPWM_reserved_0014[4];
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */
+ int8_t mcPWM_reserved_0028[8];
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */
+ int8_t mcPWM_reserved_003c[16];
+ int8_t mcPWM_reserved_004C_I2[4];
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */
+ int8_t mcPWM_reserved_0064[4];
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */
+ /* Capture Control A Register */
+ int8_t mcPWM_reserved_0078[8];
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */
+ int8_t mcPWM_reserved_008c[16];
+ int8_t mcPWM_reserved_009C_I2[4];
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */
+ int8_t mcPWM_reserved_00b4[4];
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */
+ /* Capture Control A Register */
+ int8_t mcPWM_reserved_00c8[8];
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */
+ int8_t mcPWM_reserved_00dc[16];
+ int8_t mcPWM_reserved_00EC_I2[4];
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */
+ int8_t mcPWM_reserved_00104[4];
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */
+ /* Capture Control A Register */
+ int8_t mcPWM_reserved_00118[8];
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */
+ int8_t mcPWM_reserved_0012c[16];
+ int8_t mcPWM_reserved_013C_E2[4];
+ };
+
+ };
+ /* Output Enable Register */
+ mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */
+ /* Mask Register */
+ mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */
+ /* Software Controlled Output Register */
+ mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */
+ /* Deadtime Source Select Register */
+ mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */
+ /* Master Control Register */
+ mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */
+ int8_t mcPWM_reserved_014A[2];
+ /* Fault Control Register */
+ mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */
+ /* Fault Status Register */
+ mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */
+ /* Fault Filter Register */
+ mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */
+ } mcPWM_tag;
+
+
+#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL)
+#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: LINFLEX */
+/* */
+/****************************************************************/
+
+ typedef union { /* LIN Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t CCD:1; /* Checksum Calculation Disable */
+ uint32_t CFD:1; /* Checksum Field Disable */
+ uint32_t LASE:1; /* LIN Auto Synchronization Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t AUTOWU:1; /* Auto Wake Up */
+#else
+ uint32_t AWUM:1; /* deprecated name - please avoid */
+#endif
+ uint32_t MBL:4; /* Master Break Length */
+ uint32_t BF:1; /* By-Pass Filter */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t SLFM:1; /* Selftest Mode */
+#else
+ uint32_t SFTM:1; /* deprecated name - please avoid */
+#endif
+ uint32_t LBKM:1; /* Loopback Mode */
+ uint32_t MME:1; /* Master Mode Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t SSBL:1; /* Slave Mode Synch Break Length */
+#else
+ uint32_t SSDT:1; /* deprecated name - please avoid */
+#endif
+ uint32_t RBLM:1; /* Receiver Buffer Locked Mode */
+ uint32_t SLEEP:1; /* Sleep Mode Request */
+ uint32_t INIT:1; /* Initialization Mode Request */
+ } B;
+ } LINFLEX_LINCR1_32B_tag;
+
+ typedef union { /* LIN Interrupt Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */
+ uint32_t OCIE:1; /* Output Compare Interrupt Enable */
+ uint32_t BEIE:1; /* Bit Error Interrupt Enable */
+ uint32_t CEIE:1; /* Checksum Error Interrupt Enable */
+ uint32_t HEIE:1; /* Header Error Interrupt Enable */
+ uint32_t:2;
+ uint32_t FEIE:1; /* Frame Error Interrupt Enable */
+ uint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */
+ uint32_t LSIE:1; /* LIN State Interrupt Enable */
+ uint32_t WUIE:1; /* Wakeup Interrupt Enable */
+ uint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */
+#else
+ uint32_t DBEIE:1; /* deprecated name - please avoid */
+#endif
+ uint32_t DRIE:1; /* Data Reception complete Interrupt Enable */
+ uint32_t DTIE:1; /* Data Transmitted Interrupt Enable */
+ uint32_t HRIE:1; /* Header Received Interrupt Enable */
+ } B;
+ } LINFLEX_LINIER_32B_tag;
+
+ typedef union { /* LIN Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t LINS:4; /* LIN State */
+ uint32_t:2;
+ uint32_t RMB:1; /* Release Message Buffer */
+ uint32_t:1;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t RXBUSY:1; /* Receiver Busy Flag */
+#else
+ uint32_t RBSY:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t RDI:1; /* LIN Receive Signal */
+#else
+ uint32_t RPS:1; /* deprecated name - please avoid */
+#endif
+ uint32_t WUF:1; /* Wake Up Flag */
+ uint32_t DBFF:1; /* Data Buffer Full Flag */
+ uint32_t DBEF:1; /* Data Buffer Empty Flag */
+ uint32_t DRF:1; /* Data Reception Completed Flag */
+ uint32_t DTF:1; /* Data Transmission Completed Flag */
+ uint32_t HRF:1; /* Header Received Flag */
+ } B;
+ } LINFLEX_LINSR_32B_tag;
+
+ typedef union { /* LIN Error Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t SZF:1; /* Stuck at Zero Flag */
+ uint32_t OCF:1; /* Output Compare Flag */
+ uint32_t BEF:1; /* Bit Error Flag */
+ uint32_t CEF:1; /* Checksum Error Flag */
+ uint32_t SFEF:1; /* Sync Field Error Flag */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t SDEF:1; /* Sync Delimiter Error Flag */
+#else
+ uint32_t BDEF:1; /* deprecated name - please avoid */
+#endif
+ uint32_t IDPEF:1; /* ID Parity Error Flag */
+ uint32_t FEF:1; /* Framing Error Flag */
+ uint32_t BOF:1; /* Buffer Overrun Flag */
+ uint32_t:6;
+ uint32_t NF:1; /* Noise Flag */
+ } B;
+ } LINFLEX_LINESR_32B_tag;
+
+ typedef union { /* UART Mode Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */
+ uint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */
+ uint32_t RFBM:1; /* RX FIFO/ Buffer Mode */
+ uint32_t TFBM:1; /* TX FIFO/ Buffer Mode */
+ uint32_t WL1:1; /* Word Length in UART mode - bit 1 */
+ uint32_t PC1:1; /* Parity Check - bit 1 */
+ uint32_t RXEN:1; /* Receiver Enable */
+ uint32_t TXEN:1; /* Transmitter Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t PC0:1; /* Parity Check - bit 0 */
+#else
+ uint32_t OP:1; /* deprecated name - please avoid */
+#endif
+ uint32_t PCE:1; /* Parity Control Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t WL0:1; /* Word Length in UART Mode - bit 0 */
+#else
+ uint32_t WL:1; /* deprecated name - please avoid */
+#endif
+ uint32_t UART:1; /* UART Mode */
+ } B;
+ } LINFLEX_UARTCR_32B_tag;
+
+ typedef union { /* UART Mode Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t SZF:1; /* Stuck at Zero Flag */
+ uint32_t OCF:1; /* Output Compare Flag */
+ uint32_t PE:4; /* Parity Error Flag */
+ uint32_t RMB:1; /* Release Message Buffer */
+ uint32_t FEF:1; /* Framing Error Flag */
+ uint32_t BOF:1; /* Buffer Overrun Flag */
+ uint32_t RDI:1; /* Receiver Data Input Signal */
+ uint32_t WUF:1; /* Wakeup Flag */
+ uint32_t:1;
+ uint32_t TO:1; /* Time Out */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */
+#else
+ uint32_t DRF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */
+#else
+ uint32_t DTF:1; /* deprecated name - please avoid */
+#endif
+ uint32_t NF:1; /* Noise Flag */
+ } B;
+ } LINFLEX_UARTSR_32B_tag;
+
+ typedef union { /* LIN Time-Out Control Status Register */
+ uint32_t R;
+ struct {
+ uint32_t:21;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t MODE:1; /* Time-out Counter Mode */
+#else
+ uint32_t LTOM:1; /* deprecated name - please avoid */
+#endif
+ uint32_t IOT:1; /* Idle on Timeout */
+ uint32_t TOCE:1; /* Time-Out Counter Enable */
+ uint32_t CNT:8; /* Counter Value */
+ } B;
+ } LINFLEX_LINTCSR_32B_tag;
+
+ typedef union { /* LIN Output Compare Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t OC2:8; /* Output Compare Value 2 */
+ uint32_t OC1:8; /* Output Compare Value 1 */
+ } B;
+ } LINFLEX_LINOCR_32B_tag;
+
+ typedef union { /* LIN Time-Out Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:20;
+ uint32_t RTO:4; /* Response Time-Out Value */
+ uint32_t:1;
+ uint32_t HTO:7; /* Header Time-Out Value */
+ } B;
+ } LINFLEX_LINTOCR_32B_tag;
+
+ typedef union { /* LIN Fractional Baud Rate Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t FBR:4; /* Fractional Baud Rates */
+#else
+ uint32_t DIV_F:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } LINFLEX_LINFBRR_32B_tag;
+
+ typedef union { /* LIN Integer Baud Rate Register */
+ uint32_t R;
+ struct {
+ uint32_t:13;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ uint32_t IBR:19; /* Integer Baud Rates */
+#else
+ uint32_t DIV_M:19; /* deprecated name - please avoid */
+#endif
+ } B;
+ } LINFLEX_LINIBRR_32B_tag;
+
+ typedef union { /* LIN Checksum Field Register */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t CF:8; /* Checksum Bits */
+ } B;
+ } LINFLEX_LINCFR_32B_tag;
+
+ typedef union { /* LIN Control Register 2 */
+ uint32_t R;
+ struct {
+ uint32_t:17;
+ uint32_t IOBE:1; /* Idle on Bit Error */
+ uint32_t IOPE:1; /* Idle on Identifier Parity Error */
+ uint32_t WURQ:1; /* Wakeup Generate Request */
+ uint32_t DDRQ:1; /* Data Discard Request */
+ uint32_t DTRQ:1; /* Data Transmission Request */
+ uint32_t ABRQ:1; /* Abort Request */
+ uint32_t HTRQ:1; /* Header Transmission Request */
+ uint32_t:8;
+ } B;
+ } LINFLEX_LINCR2_32B_tag;
+
+ typedef union { /* Buffer Identifier Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t DFL:6; /* Data Field Length */
+ uint32_t DIR:1; /* Direction */
+ uint32_t CCS:1; /* Classic Checksum */
+ uint32_t:2;
+ uint32_t ID:6; /* Identifier */
+ } B;
+ } LINFLEX_BIDR_32B_tag;
+
+ typedef union { /* Buffer Data Register Least Significant */
+ uint32_t R;
+ struct {
+ uint32_t DATA3:8; /* Data3 */
+ uint32_t DATA2:8; /* Data2 */
+ uint32_t DATA1:8; /* Data1 */
+ uint32_t DATA0:8; /* Data0 */
+ } B;
+ } LINFLEX_BDRL_32B_tag;
+
+ typedef union { /* Buffer Data Register Most Significant */
+ uint32_t R;
+ struct {
+ uint32_t DATA7:8; /* Data7 */
+ uint32_t DATA6:8; /* Data6 */
+ uint32_t DATA5:8; /* Data5 */
+ uint32_t DATA4:8; /* Data4 */
+ } B;
+ } LINFLEX_BDRM_32B_tag;
+
+ typedef union { /* Identifier Filter Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:24;
+ uint32_t FACT:8; /* Filter Active */
+ } B;
+ } LINFLEX_IFER_32B_tag;
+
+ typedef union { /* Identifier Filter Match Index */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t IFMI_IFMI:4; /* Filter Match Index */
+ } B;
+ } LINFLEX_IFMI_32B_tag;
+
+ typedef union { /* Identifier Filter Mode Register */
+ uint32_t R;
+ struct {
+ uint32_t:28;
+ uint32_t IFM:4; /* Filter Mode */
+ } B;
+ } LINFLEX_IFMR_32B_tag;
+
+
+ /* Register layout for all registers IFCR... */
+
+ typedef union { /* Identifier Filter Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:16;
+ uint32_t DFL:6; /* Data Field Length */
+ uint32_t DIR:1; /* Direction */
+ uint32_t CCS:1; /* Classic Checksum */
+ uint32_t:2;
+ uint32_t ID:6; /* Identifier */
+ } B;
+ } LINFLEX_IFCR_32B_tag;
+
+ typedef union { /* Global Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:26;
+ uint32_t TDFBM:1; /* Transmit Data First Bit MSB */
+ uint32_t RDFBM:1; /* Received Data First Bit MSB */
+ uint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */
+ uint32_t RDLIS:1; /* Received Data Level Inversion Selection */
+ uint32_t STOP:1; /* 1/2 stop bit configuration */
+ uint32_t SR:1; /* Soft Reset */
+ } B;
+ } LINFLEX_GCR_32B_tag;
+
+ typedef union { /* UART Preset Time Out Register */
+ uint32_t R;
+ struct {
+ uint32_t:20;
+ uint32_t PTO:12; /* Preset Time Out */
+ } B;
+ } LINFLEX_UARTPTO_32B_tag;
+
+ typedef union { /* UART Current Time Out Register */
+ uint32_t R;
+ struct {
+ uint32_t:20;
+ uint32_t CTO:12; /* Current Time Out */
+ } B;
+ } LINFLEX_UARTCTO_32B_tag;
+
+ typedef union { /* DMA TX Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:17;
+ uint32_t DTE:15; /* DMA Tx channel Enable */
+ } B;
+ } LINFLEX_DMATXE_32B_tag;
+
+ typedef union { /* DMA RX Enable Register */
+ uint32_t R;
+ struct {
+ uint32_t:17;
+ uint32_t DRE:15; /* DMA Rx channel Enable */
+ } B;
+ } LINFLEX_DMARXE_32B_tag;
+
+
+
+ typedef struct LINFLEX_struct_tag { /* start of LINFLEX_tag */
+ /* LIN Control Register */
+ LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */
+ /* LIN Interrupt Enable Register */
+ LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */
+ /* LIN Status Register */
+ LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */
+ /* LIN Error Status Register */
+ LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */
+ /* UART Mode Control Register */
+ LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */
+ /* UART Mode Status Register */
+ LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */
+ /* LIN Time-Out Control Status Register */
+ LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */
+ /* LIN Output Compare Register */
+ LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */
+ /* LIN Time-Out Control Register */
+ LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */
+ /* LIN Fractional Baud Rate Register */
+ LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */
+ /* LIN Integer Baud Rate Register */
+ LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */
+ /* LIN Checksum Field Register */
+ LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */
+ /* LIN Control Register 2 */
+ LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */
+ /* Buffer Identifier Register */
+ LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */
+ /* Buffer Data Register Least Significant */
+ LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */
+ /* Buffer Data Register Most Significant */
+ LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */
+ /* Identifier Filter Enable Register */
+ LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */
+ /* Identifier Filter Match Index */
+ LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */
+ /* Identifier Filter Mode Register */
+ LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */
+ union {
+ /* Identifier Filter Control Register */
+ LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */
+
+ struct {
+ /* Identifier Filter Control Register */
+ LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */
+ };
+
+ };
+ int8_t LINFLEX_reserved_006C[32];
+ /* Global Control Register */
+ LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */
+ /* UART Preset Time Out Register */
+ LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */
+ /* UART Current Time Out Register */
+ LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */
+ /* DMA TX Enable Register */
+ LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */
+ /* DMA RX Enable Register */
+ LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */
+ } LINFLEX_tag;
+
+
+#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL)
+#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CRC */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers CFG... */
+
+ typedef union { /* CRC_CFG - CRC Configuration register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ struct {
+ uint32_t:29;
+ uint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */
+ uint32_t SWAP:1; /* SWAP selection */
+ uint32_t INV:1; /* INV selection */
+ } B;
+ } CRC_CFG_32B_tag;
+
+
+ /* Register layout for all registers INP... */
+
+ typedef union { /* CRC_INP - CRC Input register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ } CRC_INP_32B_tag;
+
+
+ /* Register layout for all registers CSTAT... */
+
+ typedef union { /* CRC_STATUS - CRC Status register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ } CRC_CSTAT_32B_tag;
+
+
+ /* Register layout for all registers OUTP... */
+
+ typedef union { /* CRC_STATUS - CRC OUTPUT register */
+ uint32_t R;
+ uint8_t BYTE[4]; /* individual bytes can be accessed */
+ uint16_t HALF[2]; /* individual halfwords can be accessed */
+ uint32_t WORD; /* individual words can be accessed */
+ } CRC_OUTP_32B_tag;
+
+
+ typedef struct CRC_CNTX_struct_tag {
+
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP; /* relative offset: 0x0004 */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */
+
+ } CRC_CNTX_tag;
+
+
+ typedef struct CRC_struct_tag { /* start of CRC_tag */
+ union {
+ /* Register set CNTX */
+ CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */
+
+ struct {
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */
+ };
+
+ };
+ } CRC_tag;
+
+
+#define CRC (*(volatile CRC_tag *) 0xFFE68000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: FCCU */
+/* */
+/****************************************************************/
+
+ typedef union { /* FCCU Control Register */
+ uint32_t R;
+ struct {
+ uint32_t:23;
+ uint32_t NVML:1; /* NVM configuration loaded */
+ uint32_t OPS:2; /* Operation status */
+ uint32_t:1;
+ uint32_t OPR:5; /* Operation run */
+ } B;
+ } FCCU_CTRL_32B_tag;
+
+ typedef union { /* FCCU CTRL Key Register */
+ uint32_t R;
+ } FCCU_CTRLK_32B_tag;
+
+ typedef union { /* FCCU Configuration Register */
+ uint32_t R;
+ struct {
+ uint32_t:10;
+ uint32_t RCCE1:1; /* RCC1 enable */
+ uint32_t RCCE0:1; /* RCC0 enable */
+ uint32_t SMRT:4; /* Safe Mode Request Timer */
+ uint32_t:4;
+ uint32_t CM:1; /* Config mode */
+ uint32_t SM:1; /* Switching mode */
+ uint32_t PS:1; /* Polarity Selection */
+ uint32_t FOM:3; /* Fault Output Mode Selection */
+ uint32_t FOP:6; /* Fault Output Prescaler */
+ } B;
+ } FCCU_CFG_32B_tag;
+
+ typedef union { /* FCCU CF Configuration Register 0 */
+ uint32_t R;
+ struct {
+ uint32_t CFC31:1; /* CF 31 configuration */
+ uint32_t CFC30:1; /* CF 30 configuration */
+ uint32_t CFC29:1; /* CF 29 configuration */
+ uint32_t CFC28:1; /* CF 28 configuration */
+ uint32_t CFC27:1; /* CF 27 configuration */
+ uint32_t CFC26:1; /* CF 26 configuration */
+ uint32_t CFC25:1; /* CF 25 configuration */
+ uint32_t CFC24:1; /* CF 24 configuration */
+ uint32_t CFC23:1; /* CF 23 configuration */
+ uint32_t CFC22:1; /* CF 22 configuration */
+ uint32_t CFC21:1; /* CF 21 configuration */
+ uint32_t CFC20:1; /* CF 20 configuration */
+ uint32_t CFC19:1; /* CF 19 configuration */
+ uint32_t CFC18:1; /* CF 18 configuration */
+ uint32_t CFC17:1; /* CF 17 configuration */
+ uint32_t CFC16:1; /* CF 16 configuration */
+ uint32_t CFC15:1; /* CF 15 configuration */
+ uint32_t CFC14:1; /* CF 14 configuration */
+ uint32_t CFC13:1; /* CF 13 configuration */
+ uint32_t CFC12:1; /* CF 12 configuration */
+ uint32_t CFC11:1; /* CF 11 configuration */
+ uint32_t CFC10:1; /* CF 10 configuration */
+ uint32_t CFC9:1; /* CF 9 configuration */
+ uint32_t CFC8:1; /* CF 8 configuration */
+ uint32_t CFC7:1; /* CF 7 configuration */
+ uint32_t CFC6:1; /* CF 6 configuration */
+ uint32_t CFC5:1; /* CF 5 configuration */
+ uint32_t CFC4:1; /* CF 4 configuration */
+ uint32_t CFC3:1; /* CF 3 configuration */
+ uint32_t CFC2:1; /* CF 2 configuration */
+ uint32_t CFC1:1; /* CF 1 configuration */
+ uint32_t CFC0:1; /* CF 0 configuration */
+ } B;
+ } FCCU_CF_CFG0_32B_tag;
+
+ typedef union { /* FCCU CF Configuration Register 1 */
+ uint32_t R;
+ struct {
+ uint32_t CFC63:1; /* CF 63 configuration */
+ uint32_t CFC62:1; /* CF 62 configuration */
+ uint32_t CFC61:1; /* CF 61 configuration */
+ uint32_t CFC60:1; /* CF 60 configuration */
+ uint32_t CFC59:1; /* CF 59 configuration */
+ uint32_t CFC58:1; /* CF 58 configuration */
+ uint32_t CFC57:1; /* CF 57 configuration */
+ uint32_t CFC56:1; /* CF 56 configuration */
+ uint32_t CFC55:1; /* CF 55 configuration */
+ uint32_t CFC54:1; /* CF 54 configuration */
+ uint32_t CFC53:1; /* CF 53 configuration */
+ uint32_t CFC52:1; /* CF 52 configuration */
+ uint32_t CFC51:1; /* CF 51 configuration */
+ uint32_t CFC50:1; /* CF 50 configuration */
+ uint32_t CFC49:1; /* CF 49 configuration */
+ uint32_t CFC48:1; /* CF 48 configuration */
+ uint32_t CFC47:1; /* CF 47 configuration */
+ uint32_t CFC46:1; /* CF 46 configuration */