| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-06-10 | Added simple RISC-V PLIC functionality for NS16550 interrupt | Jiri Gaisler | |
| * RTEMS spconsole01 test now passes | |||
| 2020-12-15 | Added support for RISCV32 systems with CLINT/PLIC | Jiri Gaisler | |
| 2020-10-28 | Add networking support using host tap device2.23 | Jiri Gaisler | |
| * Emulation of GRETH 10/100 Mbit MAC and PHY * Supported only on linux | |||
| 2020-09-09 | Map RISC-V FPU CSR on host cpu using fenv.h | Jiri Gaisler | |
| 2020-02-29 | Fix incorrect operation on big-endian hosts | Jiri Gaisler | |
| 2019-11-09 | Support building on MinGW-W64/MSYS22.19 | Jiri Gaisler | |
| * Depends on MinGW64-readline to build | |||
| 2019-11-08 | Improve gdb watchpoint handling | Jiri Gaisler | |
| * show old/new values * stop at correct instruction | |||
| 2019-06-11 | Fix C formatting with indent | Jiri Gaisler | |
| 2019-06-11 | Avoid array out of bounds warning on RISC-V | Jiri Gaisler | |
| 2019-06-11 | Silence warnings when compiled with LLVM | Jiri Gaisler | |
| 2019-05-28 | Made L1 cache optional through --enable-l1cache | Jiri Gaisler | |
| * Removed stale config.h * Updated autoconf script with relevant checks * Re-implemented leon3/grlib timer with less events * Bumped version to 2.15 | |||
| 2019-05-27 | Add emulated L1 cache to SMP configurations | Jiri Gaisler | |
| * Also improve timing accuracy for certain instructions | |||
| 2019-05-14 | Standalone sis - initial commit | Jiri Gaisler | |
 |
index : sis.git | |
| Clone of master repository. |
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