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authorJiri Gaisler <jiri@gaisler.se>2019-11-04 22:57:29 +0100
committerJiri Gaisler <jiri@gaisler.se>2019-11-08 22:33:05 +0100
commit88b545002e553f1e21fab1aff854a3e325976ad3 (patch)
tree45aaddcb10ccc2d17706e2fee31d367042bbd2f0 /riscv.c
parent4e080cdb1dd910750fb28de1f764934206554301 (diff)
Improve gdb watchpoint handling
* show old/new values * stop at correct instruction
Diffstat (limited to 'riscv.c')
-rw-r--r--riscv.c20
1 files changed, 18 insertions, 2 deletions
diff --git a/riscv.c b/riscv.c
index 450283d..7498fce 100644
--- a/riscv.c
+++ b/riscv.c
@@ -870,6 +870,13 @@ riscv_dispatch_instruction (sregs)
break;
case OP_STORE: /* store instructions */
+ /* skip store if we resume after a write watchpoint */
+ if (sis_gdb_break && ebase.wphit)
+ {
+ ebase.wphit = 0;
+ break;
+ }
+
#if defined(STAT) || defined(ENABLE_L1CACHE)
sregs->nstore++;
#endif
@@ -882,7 +889,10 @@ riscv_dispatch_instruction (sregs)
if ((ebase.wphit = check_wpw (sregs, address, funct3 & 3)))
{
sregs->trap = WPT_TRAP;
- break;
+ /* gdb seems to expect that the write goes trough when the
+ * watchpoint is hit, but PC stays on the store instruction */
+ if (!sis_gdb_break)
+ break;
}
}
@@ -940,6 +950,11 @@ riscv_dispatch_instruction (sregs)
break;
case OP_FSW: /* F store instructions */
+ if (sis_gdb_break && ebase.wphit)
+ {
+ ebase.wphit = 0;
+ break;
+ }
#if defined(STAT) || defined(ENABLE_L1CACHE)
sregs->nstore++;
#endif
@@ -952,7 +967,8 @@ riscv_dispatch_instruction (sregs)
if ((ebase.wphit = check_wpw (sregs, address, funct3 & 3)))
{
sregs->trap = WPT_TRAP;
- break;
+ if (!sis_gdb_break)
+ break;
}
}