Added simple RISC-V PLIC functionality for NS16550 interrupt

	* RTEMS spconsole01 test now passes

1 files changed, 7 insertions, 2 deletions

diff --git a/riscv.c b/riscv.c
index 6d8fa98..b36fa1e 100644
--- a/riscv.c
+++ b/riscv.c
@@ -201,7 +201,9 @@ rv32_check_lirq (int cpu)
   if (sregs[cpu].mstatus & MSTATUS_MIE)
     {
       tmpirq = sregs[cpu].mip & sregs[cpu].mie;
-      if (tmpirq & MIP_MSIP)
+      if (tmpirq & MIP_MEIP)
+	ext_irl[cpu] = 0x1b;
+      else if (tmpirq & MIP_MSIP)
 	ext_irl[cpu] = 0x13;
       else if (tmpirq & MIP_MTIP)
 	ext_irl[cpu] = 0x17;
@@ -2080,7 +2082,8 @@ riscv_execute_trap (sregs)
 	}
 
       if (((sregs->trap >= 16) && (sregs->trap < 32))
-	  || ((sregs->trap == 0x23) || (sregs->trap == 0x27)))
+	  || ((sregs->trap == 0x23) || (sregs->trap == 0x27)
+	      || (sregs->trap == 0x2b)))
 	{
 	  sregs->mcause &= 0x1f;	// filter trap cause
 	  sregs->mcause |= 0x80000000;	// indicate async interrupt
@@ -2093,6 +2096,8 @@ riscv_execute_trap (sregs)
 	sregs->mip &= ~MIP_MSIP;
       if (sregs->trap == 0x27)
 	sregs->mip &= ~MIP_MTIP;
+      if (sregs->trap == 0x2b)
+	sregs->mip &= ~MIP_MEIP;
 
       // save mstatus.mie in mstatus.mpie
       sregs->mstatus |= (sregs->mstatus << 4) & MSTATUS_MPIE;