diff options
| author | Amar Takhar <amar@rtems.org> | 2015-12-11 17:52:17 -0500 |
|---|---|---|
| committer | Amar Takhar <amar@rtems.org> | 2015-12-11 17:52:17 -0500 |
| commit | d267a7a06a4c4f75b646b538abc42fefd47718f5 (patch) | |
| tree | 92a1aee50858090fd9494a7975e4602a227f1d3f /cpukit | |
| parent | f39e6afe753fa0d011524f9c378447ef79dcf0ec (diff) | |
Move headers required by i386 SMP support.include
Diffstat (limited to 'cpukit')
75 files changed, 0 insertions, 25670 deletions
diff --git a/cpukit/libdl/include/arch/arm/machine/elf_machdep.h b/cpukit/libdl/include/arch/arm/machine/elf_machdep.h deleted file mode 100644 index 78c88b5af8..0000000000 --- a/cpukit/libdl/include/arch/arm/machine/elf_machdep.h +++ /dev/null @@ -1,131 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.8 2009/05/30 05:56:52 skrll Exp $ */ - -#if defined(__ARMEB__) -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#else -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB -#endif - -#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ -#define ELF64_MACHDEP_ID_CASES \ - /* no 64-bit ELF machine types supported */ - -/* Processor specific flags for the ELF header e_flags field. */ -#define EF_ARM_RELEXEC 0x00000001 -#define EF_ARM_HASENTRY 0x00000002 -#define EF_ARM_INTERWORK 0x00000004 /* GNU binutils 000413 */ -#define EF_ARM_SYMSARESORTED 0x00000004 /* ARM ELF A08 */ -#define EF_ARM_APCS_26 0x00000008 /* GNU binutils 000413 */ -#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ARM ELF B01 */ -#define EF_ARM_APCS_FLOAT 0x00000010 /* GNU binutils 000413 */ -#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ARM ELF B01 */ -#define EF_ARM_PIC 0x00000020 -#define EF_ARM_ALIGN8 0x00000040 /* 8-bit structure alignment. */ -#define EF_ARM_NEW_ABI 0x00000080 -#define EF_ARM_OLD_ABI 0x00000100 -#define EF_ARM_SOFT_FLOAT 0x00000200 -#define EF_ARM_EABIMASK 0xff000000 - -#define ELF32_MACHDEP_ID_CASES \ - case EM_ARM: \ - break; - -#define ELF32_MACHDEP_ID EM_ARM - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -/* Processor specific relocation types */ - -#define R_ARM_NONE 0 -#define R_ARM_PC24 1 -#define R_ARM_ABS32 2 -#define R_ARM_REL32 3 -#define R_ARM_PC13 4 -#define R_ARM_ABS16 5 -#define R_ARM_ABS12 6 -#define R_ARM_THM_ABS5 7 -#define R_ARM_ABS8 8 -#define R_ARM_SBREL32 9 -#define R_ARM_THM_CALL 10 -#define R_ARM_THM_PC8 11 -#define R_ARM_AMP_VCALL9 12 -#define R_ARM_SWI24 13 -#define R_ARM_THM_SWI8 14 -#define R_ARM_XPC25 15 -#define R_ARM_THM_XPC22 16 - -/* TLS relocations */ -#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ -#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ -#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ - -/* 20-31 are reserved for ARM Linux. */ -#define R_ARM_COPY 20 -#define R_ARM_GLOB_DAT 21 -#define R_ARM_JUMP_SLOT 22 -#define R_ARM_RELATIVE 23 -#define R_ARM_GOTOFF 24 -#define R_ARM_GOTPC 25 -#define R_ARM_GOT32 26 -#define R_ARM_PLT32 27 -#define R_ARM_CALL 28 -#define R_ARM_JUMP24 29 -#define R_ARM_THM_JUMP24 30 -#define R_ARM_BASE_ABS 31 - -#define R_ARM_ALU_PCREL_7_0 32 -#define R_ARM_ALU_PCREL_15_8 33 -#define R_ARM_ALU_PCREL_23_15 34 -#define R_ARM_ALU_SBREL_11_0 35 -#define R_ARM_ALU_SBREL_19_12 36 -#define R_ARM_ALU_SBREL_27_20 37 -#define R_ARM_V4BX 40 -#define R_ARM_PREL31 41 - -#define R_ARM_MOVW_ABS_NC 43 -#define R_ARM_MOVT_ABS 44 - -#define R_ARM_THM_MOVW_ABS_NC 47 -#define R_ARM_THM_MOVT_ABS 48 - -#define R_ARM_THM_JUMP19 51 - -/* 96-111 are reserved to G++. */ -#define R_ARM_GNU_VTENTRY 100 -#define R_ARM_GNU_VTINHERIT 101 -#define R_ARM_THM_JUMP11 102 -#define R_ARM_THM_JUMP8 103 - -/* More TLS relocations */ -#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic */ -#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic */ -#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS */ -#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of */ -#define R_ARM_TLS_LE32 108 -#define R_ARM_TLS_LDO12 109 -#define R_ARM_TLS_LE12 110 -#define R_ARM_TLS_IE12GP 111 - -/* 112-127 are reserved for private experiments. */ - -#define R_ARM_RXPC25 249 -#define R_ARM_RSBREL32 250 -#define R_ARM_THM_RPC22 251 -#define R_ARM_RREL32 252 -#define R_ARM_RABS32 253 -#define R_ARM_RPC24 254 -#define R_ARM_RBASE 255 - -#define R_TYPE(name) __CONCAT(R_ARM_,name) - -/* Processor specific program header flags */ -#define PF_ARM_SB 0x10000000 -#define PF_ARM_PI 0x20000000 -#define PF_ARM_ENTRY 0x80000000 - -/* Processor specific section header flags */ -#define SHF_ENTRYSECT 0x10000000 -#define SHF_COMDEF 0x80000000 - -/* Processor specific symbol types */ -#define STT_ARM_TFUNC STT_LOPROC diff --git a/cpukit/libdl/include/arch/i386/machine/elf_machdep.h b/cpukit/libdl/include/arch/i386/machine/elf_machdep.h deleted file mode 100644 index 442c561a9c..0000000000 --- a/cpukit/libdl/include/arch/i386/machine/elf_machdep.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_386: \ - case EM_486: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ -#define ELF64_MACHDEP_ID_CASES \ - /* no 64-bit ELF machine types supported */ - -#define ELF32_MACHDEP_ID EM_386 - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -/* i386 relocations */ -#define R_386_NONE 0 -#define R_386_32 1 -#define R_386_PC32 2 -#define R_386_GOT32 3 -#define R_386_PLT32 4 -#define R_386_COPY 5 -#define R_386_GLOB_DAT 6 -#define R_386_JMP_SLOT 7 -#define R_386_RELATIVE 8 -#define R_386_GOTOFF 9 -#define R_386_GOTPC 10 - -/* TLS relocations */ -#define R_386_TLS_TPOFF 14 -#define R_386_TLS_IE 15 -#define R_386_TLS_GOTIE 16 -#define R_386_TLS_LE 17 -#define R_386_TLS_GD 18 -#define R_386_TLS_LDM 19 - -/* The following relocations are GNU extensions. */ -#define R_386_16 20 -#define R_386_PC16 21 -#define R_386_8 22 -#define R_386_PC8 23 - -/* More TLS relocations */ -#define R_386_TLS_GD_32 24 -#define R_386_TLS_GD_PUSH 25 -#define R_386_TLS_GD_CALL 26 -#define R_386_TLS_GD_POP 27 -#define R_386_TLS_LDM_32 28 -#define R_386_TLS_LDM_PUSH 29 -#define R_386_TLS_LDM_CALL 30 -#define R_386_TLS_LDM_POP 31 -#define R_386_TLS_LDO_32 32 -#define R_386_TLS_IE_32 33 -#define R_386_TLS_LE_32 34 -#define R_386_TLS_DTPMOD32 35 -#define R_386_TLS_DTPOFF32 36 -#define R_386_TLS_TPOFF32 37 -#define R_386_TLS_GOTDESC 39 -#define R_386_TLS_DESC_CALL 40 -#define R_386_TLS_DESC 41 - -#define R_TYPE(name) __CONCAT(R_386_,name) diff --git a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h b/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h deleted file mode 100644 index 3f531cf901..0000000000 --- a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h +++ /dev/null @@ -1,39 +0,0 @@ -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB - -#define ELF32_MACHDEP_ID_CASES \ - case EM_M32R: \ - break; - -#define ELF32_MACHDEP_ID EM_M32R - -#define ARCH_ELFSIZE 32 - -#define R_M32R_NONE 0 -/*-----------OLD TYPE-------------*/ -#define R_M32R_16 1 -#define R_M32R_32 2 -#define R_M32R_24 3 -#define R_M32R_10_PCREL 4 -#define R_M32R_18_PCREL 5 -#define R_M32R_26_PCREL 6 -#define R_M32R_HI16_ULO 7 -#define R_M32R_HI16_SLO 8 -#define R_M32R_LO16 9 -#define R_M32R_SDA16 10 -#define R_M32R_GNU_VTINHERIT 11 -#define R_M32R_GNU_VTENTRY 12 -/*--------------------------------*/ - -#define R_M32R_16_RELA 33 -#define R_M32R_32_RELA 34 -#define R_M32R_24_RELA 35 -#define R_M32R_18_PCREL_RELA 37 -#define R_M32R_26_PCREL_RELA 38 -#define R_M32R_HI16_ULO_RELA 39 -#define R_M32R_HI16_SLO_RELA 40 -#define R_M32R_LO16_RELA 41 -#define R_M32R_SDA16_RELA 42 -#define R_M32R_RELA_GNU_VTINHERIT 43 -#define R_M32R_RELA_GNU_VTENTRY 44 - -#define R_TYPE(name) __CONCAT(R_M32R_,name) diff --git a/cpukit/libdl/include/arch/m68k/machine/elf_machdep.h b/cpukit/libdl/include/arch/m68k/machine/elf_machdep.h deleted file mode 100644 index 9a987c69b5..0000000000 --- a/cpukit/libdl/include/arch/m68k/machine/elf_machdep.h +++ /dev/null @@ -1,47 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_68K: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ -#define ELF64_MACHDEP_ID_CASES \ - /* no 64-bit ELF machine types supported */ - -#define ELF32_MACHDEP_ID EM_68K - -/* - * Machine-dependent ELF flags. These are defined by the GNU tools. - */ -#define EF_CPU32 0x00810000 -#define EF_M68000 0x01000000 - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -/* m68k relocation types */ -#define R_68K_NONE 0 -#define R_68K_32 1 -#define R_68K_16 2 -#define R_68K_8 3 -#define R_68K_PC32 4 -#define R_68K_PC16 5 -#define R_68K_PC8 6 -#define R_68K_GOT32 7 -#define R_68K_GOT16 8 -#define R_68K_GOT8 9 -#define R_68K_GOT32O 10 -#define R_68K_GOT16O 11 -#define R_68K_GOT8O 12 -#define R_68K_PLT32 13 -#define R_68K_PLT16 14 -#define R_68K_PLT8 15 -#define R_68K_PLT32O 16 -#define R_68K_PLT16O 17 -#define R_68K_PLT8O 18 -#define R_68K_COPY 19 -#define R_68K_GLOB_DAT 20 -#define R_68K_JMP_SLOT 21 -#define R_68K_RELATIVE 22 - -#define R_TYPE(name) __CONCAT(R_68K_,name) diff --git a/cpukit/libdl/include/arch/mips/machine/elf_machdep.h b/cpukit/libdl/include/arch/mips/machine/elf_machdep.h deleted file mode 100644 index 26700ce4ce..0000000000 --- a/cpukit/libdl/include/arch/mips/machine/elf_machdep.h +++ /dev/null @@ -1,199 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */ - -#ifndef _MIPS_ELF_MACHDEP_H_ -#define _MIPS_ELF_MACHDEP_H_ - -#ifdef _LP64 -#define ARCH_ELFSIZE 64 /* MD native binary size */ -#else -#define ARCH_ELFSIZE 32 /* MD native binary size */ -#endif - -#if ARCH_ELFSIZE == 32 -#define ELF32_MACHDEP_ID_CASES \ - case EM_MIPS: \ - break; - -#define ELF32_MACHDEP_ID EM_MIPS - -#elif ARCH_ELFSIZE == 64 -#define ELF64_MACHDEP_ID_CASES \ - case EM_MIPS: \ - break; - -#define ELF64_MACHDEP_ID EM_MIPS - -#endif - - -/* mips relocs. */ - -#define R_MIPS_NONE 0 -#define R_MIPS_16 1 -#define R_MIPS_32 2 -#define R_MIPS_REL32 3 -#define R_MIPS_REL R_MIPS_REL32 -#define R_MIPS_26 4 -#define R_MIPS_HI16 5 /* high 16 bits of symbol value */ -#define R_MIPS_LO16 6 /* low 16 bits of symbol value */ -#define R_MIPS_GPREL16 7 /* GP-relative reference */ -#define R_MIPS_LITERAL 8 /* Reference to literal section */ -#define R_MIPS_GOT16 9 /* Reference to global offset table */ -#define R_MIPS_GOT R_MIPS_GOT16 -#define R_MIPS_PC16 10 /* 16 bit PC relative reference */ -#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */ -#define R_MIPS_CALL R_MIPS_CALL16 -#define R_MIPS_GPREL32 12 - -/* 13, 14, 15 are not defined at this point. */ -#define R_MIPS_UNUSED1 13 -#define R_MIPS_UNUSED2 14 -#define R_MIPS_UNUSED3 15 - -/* - * The remaining relocs are apparently part of the 64-bit Irix ELF ABI. - */ -#define R_MIPS_SHIFT5 16 -#define R_MIPS_SHIFT6 17 - -#define R_MIPS_64 18 -#define R_MIPS_GOT_DISP 19 -#define R_MIPS_GOT_PAGE 20 -#define R_MIPS_GOT_OFST 21 -#define R_MIPS_GOT_HI16 22 -#define R_MIPS_GOT_LO16 23 -#define R_MIPS_SUB 24 -#define R_MIPS_INSERT_A 25 -#define R_MIPS_INSERT_B 26 -#define R_MIPS_DELETE 27 -#define R_MIPS_HIGHER 28 -#define R_MIPS_HIGHEST 29 -#define R_MIPS_CALL_HI16 30 -#define R_MIPS_CALL_LO16 31 -#define R_MIPS_SCN_DISP 32 -#define R_MIPS_REL16 33 -#define R_MIPS_ADD_IMMEDIATE 34 -#define R_MIPS_PJUMP 35 -#define R_MIPS_RELGOT 36 -#define R_MIPS_JALR 37 -/* TLS relocations */ - -#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ -#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ -#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ -#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ -#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ -#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ -#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ -#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ -#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ -#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ -#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ -#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ -#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ - -#define R_MIPS_max 51 - -#define R_TYPE(name) __CONCAT(R_MIPS_,name) - -#define R_MIPS16_min 100 -#define R_MIPS16_26 100 -#define R_MIPS16_GPREL 101 -#define R_MIPS16_GOT16 102 -#define R_MIPS16_CALL16 103 -#define R_MIPS16_HI16 104 -#define R_MIPS16_LO16 105 -#define R_MIPS16_max 106 - - -/* mips dynamic tags */ - -#define DT_MIPS_RLD_VERSION 0x70000001 -#define DT_MIPS_TIME_STAMP 0x70000002 -#define DT_MIPS_ICHECKSUM 0x70000003 -#define DT_MIPS_IVERSION 0x70000004 -#define DT_MIPS_FLAGS 0x70000005 -#define DT_MIPS_BASE_ADDRESS 0x70000006 -#define DT_MIPS_CONFLICT 0x70000008 -#define DT_MIPS_LIBLIST 0x70000009 -#define DT_MIPS_CONFLICTNO 0x7000000b -#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */ -#define DT_MIPS_LIBLISTNO 0x70000010 -#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */ -#define DT_MIPS_UNREFEXTNO 0x70000012 -#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */ -#define DT_MIPS_HIPAGENO 0x70000014 -#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */ - -/* - * ELF Flags - */ -#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */ -#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */ -#define EF_MIPS_ABI2 0x00000020 /* N32 */ - -#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */ -#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */ -#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */ - -#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */ -#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */ -#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */ -#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */ -#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */ -#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */ -#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */ -#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */ -#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */ -#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */ - -#define EF_MIPS_ABI 0x0000f000 -#define EF_MIPS_ABI_O32 0x00001000 -#define EF_MIPS_ABI_O64 0x00002000 -#define EF_MIPS_ABI_EABI32 0x00003000 -#define EF_MIPS_ABI_EABI64 0x00004000 - -#if defined(__MIPSEB__) -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB -#elif defined(__MIPSEL__) -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB -#elif !defined(HAVE_NBTOOL_CONFIG_H) -#error neither __MIPSEL__ nor __MIPSEB__ are defined. -#endif - -#ifdef _KERNEL -#ifdef _KERNEL_OPT -#include "opt_compat_netbsd.h" -#endif -#ifdef COMPAT_16 -/* - * Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable. - * Tell the kernel ELF exec code not to try relocating the interpreter - * for dynamically-linked ELF binaries. - */ -#define ELF_INTERP_NON_RELOCATABLE -#endif /* COMPAT_16 */ - -/* - * We need to be able to include the ELF header so we can pick out the - * ABI being used. - */ -#ifdef ELFSIZE -#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe) -#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup) -#endif - -struct exec_package; - -int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *, - vaddr_t *); -void coredump_elf32_setup(struct lwp *, void *); - -int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *, - vaddr_t *); -void coredump_elf64_setup(struct lwp *, void *); -#endif /* _KERNEL */ - -#endif /* _MIPS_ELF_MACHDEP_H_ */ diff --git a/cpukit/libdl/include/arch/moxie/machine/elf_machdep.h b/cpukit/libdl/include/arch/moxie/machine/elf_machdep.h deleted file mode 100644 index 3f0df23cdc..0000000000 --- a/cpukit/libdl/include/arch/moxie/machine/elf_machdep.h +++ /dev/null @@ -1,15 +0,0 @@ -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB - -#define ELF32_MACHDEP_ID_CASES \ - case EM_MOXIE: \ - break; - -#define ELF32_MACHDEP_ID EM_MOXIE - -#define ARCH_ELFSIZE 32 - -#define R_MOXIE_NONE 0 -#define R_MOXIE_32 1 -#define R_MOXIE_PCREL10 2 - -#define R_TYPE(name) __CONCAT(R_MOXIE_,name) diff --git a/cpukit/libdl/include/arch/powerpc/machine/elf_machdep.h b/cpukit/libdl/include/arch/powerpc/machine/elf_machdep.h deleted file mode 100644 index f0fdb3f33b..0000000000 --- a/cpukit/libdl/include/arch/powerpc/machine/elf_machdep.h +++ /dev/null @@ -1,105 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.9 2011/01/15 10:00:07 matt Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_PPC: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF64_MACHDEP_ID_CASES \ - case EM_PPC64: \ - break; - -#define ELF32_MACHDEP_ID EM_PPC -#define ELF64_MACHDEP_ID EM_PPC64 - -#ifdef _LP64 -#define ARCH_ELFSIZE 64 /* MD native binary size */ -#else -#define ARCH_ELFSIZE 32 /* MD native binary size */ -#endif - -/* Specify the value of _GLOBAL_OFFSET_TABLE_ */ -#define DT_PPC_GOT DT_LOPROC - -#define R_PPC_NONE 0 -#define R_PPC_32 1 -#define R_PPC_24 2 -#define R_PPC_16 3 -#define R_PPC_16_LO 4 -#define R_PPC_16_HI 5 /* R_PPC_ADDIS */ -#define R_PPC_16_HA 6 -#define R_PPC_14 7 -#define R_PPC_14_TAKEN 8 -#define R_PPC_14_NTAKEN 9 -#define R_PPC_REL24 10 /* R_PPC_BRANCH */ -#define R_PPC_REL14 11 -#define R_PPC_REL14_TAKEN 12 -#define R_PPC_REL14_NTAKEN 13 -#define R_PPC_GOT16 14 -#define R_PPC_GOT16_LO 15 -#define R_PPC_GOT16_HI 16 -#define R_PPC_GOT16_HA 17 -#define R_PPC_PLT24 18 -#define R_PPC_COPY 19 -#define R_PPC_GLOB_DAT 20 -#define R_PPC_JMP_SLOT 21 -#define R_PPC_RELATIVE 22 -#define R_PPC_LOCAL24PC 23 -#define R_PPC_U32 24 -#define R_PPC_U16 25 -#define R_PPC_REL32 26 -#define R_PPC_PLT32 27 -#define R_PPC_PLTREL32 28 -#define R_PPC_PLT16_LO 29 -#define R_PPC_PLT16_HI 30 -#define R_PPC_PLT16_HA 31 -#define R_PPC_SDAREL16 32 -#define R_PPC_SECTOFF 33 -#define R_PPC_SECTOFF_LO 34 -#define R_PPC_SECTOFF_HI 35 -#define R_PPC_SECTOFF_HA 36 -#define R_PPC_ADDR30 37 - -/* TLS relocations */ -#define R_PPC_TLS 67 - -#define R_PPC_DTPMOD32 68 -#define R_PPC_TPREL16 69 -#define R_PPC_TPREL16_LO 70 -#define R_PPC_TPREL16_HI 71 -#define R_PPC_TPREL16_HA 72 -#define R_PPC_TPREL32 73 -#define R_PPC_DTPREL16 74 -#define R_PPC_DTPREL16_LO 75 -#define R_PPC_DTPREL16_HI 76 -#define R_PPC_DTPREL16_HA 77 -#define R_PPC_DTPREL32 78 - -#define R_PPC_GOT_TLSGD16 79 -#define R_PPC_GOT_TLSGD16_LO 80 -#define R_PPC_GOT_TLSGD16_HI 81 -#define R_PPC_GOT_TLSGD16_HA 82 -#define R_PPC_GOT_TLSLD16 83 -#define R_PPC_GOT_TLSLD16_LO 84 -#define R_PPC_GOT_TLSLD16_HI 85 -#define R_PPC_GOT_TLSLD16_HA 86 - -#define R_PPC_GOT_TPREL16 87 -#define R_PPC_GOT_TPREL16_LO 88 -#define R_PPC_GOT_TPREL16_HI 89 -#define R_PPC_GOT_TPREL16_HA 90 -#define R_PPC_GOT_DTPREL16 91 -#define R_PPC_GOT_DTPREL16_LO 92 -#define R_PPC_GOT_DTPREL16_HI 93 -#define R_PPC_GOT_DTPREL16_HA 94 -#define R_PPC_TLSGD 95 -#define R_PPC_TLSLD 96 - -/* Used for the secure-plt PIC code sequences */ -#define R_PPC_REL16 249 -#define R_PPC_REL16_LO 250 -#define R_PPC_REL16_HI 251 -#define R_PPC_REL16_HA 252 - -#define R_TYPE(name) __CONCAT(R_PPC_,name) diff --git a/cpukit/libdl/include/arch/sparc/machine/elf_machdep.h b/cpukit/libdl/include/arch/sparc/machine/elf_machdep.h deleted file mode 100644 index e8f2b630c2..0000000000 --- a/cpukit/libdl/include/arch/sparc/machine/elf_machdep.h +++ /dev/null @@ -1,92 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.7 2009/05/30 05:56:53 skrll Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_SPARC: \ - case EM_SPARC32PLUS: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF64_MACHDEP_ID_CASES \ - case EM_SPARC32PLUS: \ - case EM_SPARCV9: \ - /* no 64-bit ELF machine types supported */ - -#define ELF32_MACHDEP_ID EM_SPARC /* XXX right? */ - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -#define R_SPARC_NONE 0 -#define R_SPARC_8 1 -#define R_SPARC_16 2 -#define R_SPARC_32 3 -#define R_SPARC_DISP8 4 -#define R_SPARC_DISP16 5 -#define R_SPARC_DISP32 6 -#define R_SPARC_WDISP30 7 -#define R_SPARC_WDISP22 8 -#define R_SPARC_HI22 9 -#define R_SPARC_22 10 -#define R_SPARC_13 11 -#define R_SPARC_LO10 12 -#define R_SPARC_GOT10 13 -#define R_SPARC_GOT13 14 -#define R_SPARC_GOT22 15 -#define R_SPARC_PC10 16 -#define R_SPARC_PC22 17 -#define R_SPARC_WPLT30 18 -#define R_SPARC_COPY 19 -#define R_SPARC_GLOB_DAT 20 -#define R_SPARC_JMP_SLOT 21 -#define R_SPARC_RELATIVE 22 -#define R_SPARC_UA32 23 -#define R_SPARC_PLT32 24 -#define R_SPARC_HIPLT22 25 -#define R_SPARC_LOPLT10 26 -#define R_SPARC_PCPLT32 27 -#define R_SPARC_PCPLT22 28 -#define R_SPARC_PCPLT10 29 -#define R_SPARC_10 30 -#define R_SPARC_11 31 -#define R_SPARC_64 32 -#define R_SPARC_OLO10 33 -#define R_SPARC_HH22 34 -#define R_SPARC_HM10 35 -#define R_SPARC_LM22 36 -#define R_SPARC_PC_HH22 37 -#define R_SPARC_PC_HM10 38 -#define R_SPARC_PC_LM22 39 -#define R_SPARC_WDISP16 40 -#define R_SPARC_WDISP19 41 -#define R_SPARC_GLOB_JMP 42 -#define R_SPARC_7 43 -#define R_SPARC_5 44 -#define R_SPARC_6 45 - -/* TLS relocations */ -#define R_SPARC_TLS_GD_HI22 56 -#define R_SPARC_TLS_GD_LO10 57 -#define R_SPARC_TLS_GD_ADD 58 -#define R_SPARC_TLS_GD_CALL 59 -#define R_SPARC_TLS_LDM_HI22 60 -#define R_SPARC_TLS_LDM_LO10 61 -#define R_SPARC_TLS_LDM_ADD 62 -#define R_SPARC_TLS_LDM_CALL 63 -#define R_SPARC_TLS_LDO_HIX22 64 -#define R_SPARC_TLS_LDO_LOX10 65 -#define R_SPARC_TLS_LDO_ADD 66 -#define R_SPARC_TLS_IE_HI22 67 -#define R_SPARC_TLS_IE_LO10 68 -#define R_SPARC_TLS_IE_LD 69 -#define R_SPARC_TLS_IE_LDX 70 -#define R_SPARC_TLS_IE_ADD 71 -#define R_SPARC_TLS_LE_HIX22 72 -#define R_SPARC_TLS_LE_LOX10 73 -#define R_SPARC_TLS_DTPMOD32 74 -#define R_SPARC_TLS_DTPMOD64 75 -#define R_SPARC_TLS_DTPOFF32 76 -#define R_SPARC_TLS_DTPOFF64 77 -#define R_SPARC_TLS_TPOFF32 78 -#define R_SPARC_TLS_TPOFF64 79 - -#define R_TYPE(name) __CONCAT(R_SPARC_,name) diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h deleted file mode 100644 index d22514d60a..0000000000 --- a/cpukit/score/cpu/arm/rtems/asm.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - * @file - * - * @brief ARM Assembler Support API - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/percpu.h> - -/** - * @defgroup ScoreCPUARMASM ARM Assembler Support - * - * @ingroup ScoreCPU - * - * @brief ARM Assembler Support - */ -/**@{**/ - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) -#define r14 REG(r14) -#define r15 REG(r15) - -#define CPSR REG(CPSR) - -#define SPSR REG(SPSR) - -#define NUM_IRQ_VECTOR 6 // IRQ number -#define NUM_FIQ_VECTOR 7 // IRQ number - // // -#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1 -#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 -#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 -#define CPSR_FIQ_MODE 0x11 -#define CPSR_IRQ_MODE 0x12 -#define CPSR_SUPERVISOR_MODE 0x13 -#define CPSR_UNDEF_MODE 0x1B - -#define CPSR_MODE_BITS 0x1F - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#define FUNCTION_THUMB_ENTRY(name) \ - .thumb; \ - .thumb_func; \ - .align 2; \ - .globl name; \ - .type name, %function; \ - name: - -#define FUNCTION_ENTRY(name) \ - .align 2; \ - .globl name; \ - .type name, %function; \ - name: - -#define FUNCTION_END(name) \ - .size name, . - name - -#if defined(ARM_MULTILIB_ARCH_V7M) - #define DEFINE_FUNCTION_ARM(name) \ - .thumb_func ; .globl name ; name: -#elif defined(__thumb__) - #define DEFINE_FUNCTION_ARM(name) \ - .thumb_func ; .globl name ; name: ; bx pc ; \ - .arm ; .globl name ## _arm ; name ## _arm: -#else - #define DEFINE_FUNCTION_ARM(name) \ - .globl name ; name: ; .globl name ## _arm ; name ## _arm: -#endif - -.macro SWITCH_FROM_THUMB_TO_ARM -#ifdef __thumb__ -.align 2 - bx pc -.arm -#endif /* __thumb__ */ -.endm - -.macro SWITCH_FROM_ARM_TO_THUMB REG -#ifdef __thumb__ - add \REG, pc, #1 - bx \REG -.thumb -#endif /* __thumb__ */ -.endm - -.macro GET_SELF_CPU_CONTROL REG, TMP - ldr \REG, =_Per_CPU_Information -#ifdef RTEMS_SMP - /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ - mrc p15, 0, \TMP, c0, c0, 5 - - and \TMP, \TMP, #0xff - add \REG, \REG, \TMP, asl #PER_CPU_CONTROL_SIZE_LOG2 -#endif -.endm - -/** @} */ - -#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h deleted file mode 100644 index ae33b572af..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ /dev/null @@ -1,719 +0,0 @@ -/** - * @file - * - * @brief ARM Architecture Support API - */ - -/* - * This include file contains information pertaining to the ARM - * processor. - * - * Copyright (c) 2009-2015 embedded brains GmbH. - * - * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> - * - * Copyright (c) 2006 OAR Corporation - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include <rtems/score/types.h> -#include <rtems/score/arm.h> - -#if defined(ARM_MULTILIB_ARCH_V4) - -/** - * @defgroup ScoreCPUARM ARM Specific Support - * - * @ingroup ScoreCPU - * - * @brief ARM specific support. - */ -/**@{**/ - -#if defined(__thumb__) && !defined(__thumb2__) - #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg - #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" - #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" - #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) - #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT -#else - #define ARM_SWITCH_REGISTERS - #define ARM_SWITCH_TO_ARM - #define ARM_SWITCH_BACK - #define ARM_SWITCH_OUTPUT - #define ARM_SWITCH_ADDITIONAL_OUTPUT -#endif - -/** - * @name Program Status Register - */ -/**@{**/ - -#define ARM_PSR_N (1 << 31) -#define ARM_PSR_Z (1 << 30) -#define ARM_PSR_C (1 << 29) -#define ARM_PSR_V (1 << 28) -#define ARM_PSR_Q (1 << 27) -#define ARM_PSR_J (1 << 24) -#define ARM_PSR_GE_SHIFT 16 -#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) -#define ARM_PSR_E (1 << 9) -#define ARM_PSR_A (1 << 8) -#define ARM_PSR_I (1 << 7) -#define ARM_PSR_F (1 << 6) -#define ARM_PSR_T (1 << 5) -#define ARM_PSR_M_SHIFT 0 -#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) -#define ARM_PSR_M_USR 0x10 -#define ARM_PSR_M_FIQ 0x11 -#define ARM_PSR_M_IRQ 0x12 -#define ARM_PSR_M_SVC 0x13 -#define ARM_PSR_M_ABT 0x17 -#define ARM_PSR_M_UND 0x1b -#define ARM_PSR_M_SYS 0x1f - -/** @} */ - -/** @} */ - -#endif /* defined(ARM_MULTILIB_ARCH_V4) */ - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* If someone uses THUMB we assume she wants minimal code size */ -#ifdef __thumb__ - #define CPU_INLINE_ENABLE_DISPATCH FALSE -#else - #define CPU_INLINE_ENABLE_DISPATCH TRUE -#endif - -#if defined(__ARMEL__) - #define CPU_BIG_ENDIAN FALSE - #define CPU_LITTLE_ENDIAN TRUE -#elif defined(__ARMEB__) - #define CPU_BIG_ENDIAN TRUE - #define CPU_LITTLE_ENDIAN FALSE -#else - #error "unknown endianness" -#endif - -/* - * The ARM uses the PIC interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#if defined(ARM_MULTILIB_HAS_WFI) - #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#else - #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#endif - -#define CPU_STACK_GROWS_UP FALSE - -/* XXX Why 32? */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * The interrupt mask disables only normal interrupts (IRQ). - * - * In order to support fast interrupts (FIQ) such that they can do something - * useful, we have to disable the operating system support for FIQs. Having - * operating system support for them would require that FIQs are disabled - * during critical sections of the operating system and application. At this - * level IRQs and FIQs would be equal. It is true that FIQs could interrupt - * the non critical sections of IRQs, so here they would have a small - * advantage. Without operating system support, the FIQs can execute at any - * time (of course not during the service of another FIQ). If someone needs - * operating system support for a FIQ, she can trigger a software interrupt and - * service the request in a two-step process. - */ -#define CPU_MODES_INTERRUPT_MASK 0x1 - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -#define CPU_STACK_MINIMUM_SIZE (1024 * 4) - -/* AAPCS, section 4.1, Fundamental Data Types */ -#define CPU_SIZEOF_POINTER 4 - -/* AAPCS, section 4.1, Fundamental Data Types */ -#define CPU_ALIGNMENT 8 - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* AAPCS, section 4.3.1, Aggregates */ -#define CPU_PARTITION_ALIGNMENT 4 - -/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ -#define CPU_STACK_ALIGNMENT 8 - -/* - * Bitfield handler macros. - * - * If we had a particularly fast function for finding the first - * bit set in a word, it would go here. Since we don't (*), we'll - * just use the universal macros. - * - * (*) On ARM V5 and later, there's a CLZ function which could be - * used to implement much quicker than the default macro. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/** @} */ - -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 -#endif - -#ifdef ARM_MULTILIB_VFP - #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 -#endif - -#ifdef RTEMS_SMP - #ifdef ARM_MULTILIB_VFP - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 - #else - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 - #endif -#endif - -#define ARM_EXCEPTION_FRAME_SIZE 80 - -#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 - -#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 - -#define ARM_VFP_CONTEXT_SIZE 264 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -typedef struct { -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t register_cpsr; - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_fp; - uint32_t register_sp; - uint32_t register_lr; -#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_r11; - void *register_lr; - void *register_sp; - uint32_t isr_nest_level; -#else - void *register_sp; -#endif -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - uint32_t thread_id; -#endif -#ifdef ARM_MULTILIB_VFP - uint64_t register_d8; - uint64_t register_d9; - uint64_t register_d10; - uint64_t register_d11; - uint64_t register_d12; - uint64_t register_d13; - uint64_t register_d14; - uint64_t register_d15; -#endif -#ifdef RTEMS_SMP - volatile bool is_executing; -#endif -} Context_Control; - -typedef struct { - /* Not supported */ -} Context_Control_fp; - -extern uint32_t arm_cpu_mode; - -static inline void _ARM_Data_memory_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "dmb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline void _ARM_Data_synchronization_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "dsb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline void _ARM_Instruction_synchronization_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "isb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline uint32_t arm_interrupt_disable( void ) -{ - uint32_t level; - -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[level], cpsr\n" - "orr %[arm_switch_reg], %[level], #0x80\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - uint32_t basepri = 0x80; - - __asm__ volatile ( - "mrs %[level], basepri\n" - "msr basepri_max, %[basepri]\n" - : [level] "=&r" (level) - : [basepri] "r" (basepri) - ); -#else - level = 0; -#endif - - return level; -} - -static inline void arm_interrupt_enable( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - ARM_SWITCH_REGISTERS; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "msr cpsr, %[level]\n" - ARM_SWITCH_BACK - : ARM_SWITCH_OUTPUT - : [level] "r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - __asm__ volatile ( - "msr basepri, %[level]\n" - : - : [level] "r" (level) - ); -#endif -} - -static inline void arm_interrupt_flash( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[arm_switch_reg], cpsr\n" - "msr cpsr, %[level]\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg) - : [level] "r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - uint32_t basepri; - - __asm__ volatile ( - "mrs %[basepri], basepri\n" - "msr basepri, %[level]\n" - "msr basepri, %[basepri]\n" - : [basepri] "=&r" (basepri) - : [level] "r" (level) - ); -#endif -} - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - _isr_cookie = arm_interrupt_disable(); \ - } while (0) - -#define _CPU_ISR_Enable( _isr_cookie ) \ - arm_interrupt_enable( _isr_cookie ) - -#define _CPU_ISR_Flash( _isr_cookie ) \ - arm_interrupt_flash( _isr_cookie ) - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -#define _CPU_Fatal_halt( _source, _err ) \ - do { \ - uint32_t _level; \ - uint32_t _error = _err; \ - _CPU_ISR_Disable( _level ); \ - (void) _level; \ - __asm__ volatile ("mov r0, %0\n" \ - : "=r" (_error) \ - : "0" (_error) \ - : "r0" ); \ - while (1); \ - } while (0); - -/** - * @brief CPU initialization. - */ -void _CPU_Initialize( void ); - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief CPU switch context. - */ -void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); - -void _CPU_Context_restore( Context_Control *new_context ) - RTEMS_NO_RETURN; - -#if defined(ARM_MULTILIB_ARCH_V7M) - void _ARMV7M_Start_multitasking( Context_Control *heir ) - RTEMS_NO_RETURN; - #define _CPU_Start_multitasking _ARMV7M_Start_multitasking -#endif - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t mpidr; - - /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ - __asm__ volatile ( - "mrc p15, 0, %[mpidr], c0, c0, 5\n" - : [mpidr] "=&r" (mpidr) - ); - - return mpidr & 0xffU; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _ARM_Send_event( void ) - { - __asm__ volatile ( "sev" : : : "memory" ); - } - - static inline void _ARM_Wait_for_event( void ) - { - __asm__ volatile ( "wfe" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - _ARM_Data_synchronization_barrier(); - _ARM_Send_event(); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - _ARM_Wait_for_event(); - _ARM_Data_memory_barrier(); - } -#endif - - -static inline uint32_t CPU_swap_u32( uint32_t value ) -{ -#if defined(__thumb2__) - __asm__ volatile ( - "rev %0, %0" - : "=r" (value) - : "0" (value) - ); - return value; -#elif defined(__thumb__) - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -#else - uint32_t tmp = value; /* make compiler warnings go away */ - __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" - "BIC %1, %1, #0xff0000\n" - "MOV %0, %0, ROR #8\n" - "EOR %0, %0, %1, LSR #8\n" - : "=r" (value), "=r" (tmp) - : "0" (value), "1" (tmp)); - return value; -#endif -} - -static inline uint16_t CPU_swap_u16( uint16_t value ) -{ -#if defined(__thumb2__) - __asm__ volatile ( - "rev16 %0, %0" - : "=r" (value) - : "0" (value) - ); - return value; -#else - return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); -#endif -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE - void *_CPU_Thread_Idle_body( uintptr_t ignored ); -#endif - -/** @} */ - -/** - * @addtogroup ScoreCPUARM - */ -/**@{**/ - -#if defined(ARM_MULTILIB_ARCH_V4) - -typedef enum { - ARM_EXCEPTION_RESET = 0, - ARM_EXCEPTION_UNDEF = 1, - ARM_EXCEPTION_SWI = 2, - ARM_EXCEPTION_PREF_ABORT = 3, - ARM_EXCEPTION_DATA_ABORT = 4, - ARM_EXCEPTION_RESERVED = 5, - ARM_EXCEPTION_IRQ = 6, - ARM_EXCEPTION_FIQ = 7, - MAX_EXCEPTIONS = 8, - ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff -} Arm_symbolic_exception_name; - -#endif /* defined(ARM_MULTILIB_ARCH_V4) */ - -typedef struct { - uint32_t register_fpexc; - uint32_t register_fpscr; - uint64_t register_d0; - uint64_t register_d1; - uint64_t register_d2; - uint64_t register_d3; - uint64_t register_d4; - uint64_t register_d5; - uint64_t register_d6; - uint64_t register_d7; - uint64_t register_d8; - uint64_t register_d9; - uint64_t register_d10; - uint64_t register_d11; - uint64_t register_d12; - uint64_t register_d13; - uint64_t register_d14; - uint64_t register_d15; - uint64_t register_d16; - uint64_t register_d17; - uint64_t register_d18; - uint64_t register_d19; - uint64_t register_d20; - uint64_t register_d21; - uint64_t register_d22; - uint64_t register_d23; - uint64_t register_d24; - uint64_t register_d25; - uint64_t register_d26; - uint64_t register_d27; - uint64_t register_d28; - uint64_t register_d29; - uint64_t register_d30; - uint64_t register_d31; -} ARM_VFP_context; - -typedef struct { - uint32_t register_r0; - uint32_t register_r1; - uint32_t register_r2; - uint32_t register_r3; - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_r11; - uint32_t register_r12; - uint32_t register_sp; - void *register_lr; - void *register_pc; -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t register_cpsr; - Arm_symbolic_exception_name vector; -#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) - uint32_t register_xpsr; - uint32_t vector; -#endif - const ARM_VFP_context *vfp_context; - uint32_t reserved_for_stack_alignment; -} CPU_Exception_frame; - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -void _ARM_Exception_default( CPU_Exception_frame *frame ); - -/* - * FIXME: In case your BSP uses this function, then convert it to use - * the shared start.S file for ARM. - */ -void rtems_exception_init_mngt( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h deleted file mode 100644 index c430911373..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * - * @ingroup ScoreCPU - * - * @brief ARM Assembler Support API - */ - -/* - * COPYRIGHT (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file is the include file for cpu_asm.S - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - -/* Registers saved in context switch: */ -.set REG_CPSR, 0 -.set REG_R4, 4 -.set REG_R5, 8 -.set REG_R6, 12 -.set REG_R7, 16 -.set REG_R8, 20 -.set REG_R9, 24 -.set REG_R10, 28 -.set REG_R11, 32 -.set REG_SP, 36 -.set REG_LR, 40 -.set REG_PC, 44 -.set SIZE_REGS, REG_PC + 4 - -#endif diff --git a/cpukit/score/cpu/arm/rtems/score/types.h b/cpukit/score/cpu/arm/rtems/score/types.h deleted file mode 100644 index deefd54996..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/types.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * - * @brief ARM Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/avr/rtems/asm.h b/cpukit/score/cpu/avr/rtems/asm.h deleted file mode 100644 index e93841d06e..0000000000 --- a/cpukit/score/cpu/avr/rtems/asm.h +++ /dev/null @@ -1,464 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/avr.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz - Copyright (c) 2006 Dmitry Xmelkov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* - macros.inc - macros for use in assembler sources - - Contributors: - Created by Marek Michalkiewicz <marekm@linux.org.pl> - */ - -#include <avr/common.h> - -/* if not defined, assume old version with underscores */ -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* the assembler line separator (just in case it ever changes) */ -#define _L $ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -#define _U(x) CONCAT1(__USER_LABEL_PREFIX__, x) - -#define _R(x) CONCAT1(__REGISTER_PREFIX__, x) - -/* these should help to fix the "can't have function named r1()" bug - which may require adding '%' in front of register names. */ - -#define r0 _R(r0) -#define r1 _R(r1) -#define r2 _R(r2) -#define r3 _R(r3) -#define r4 _R(r4) -#define r5 _R(r5) -#define r6 _R(r6) -#define r7 _R(r7) -#define r8 _R(r8) -#define r9 _R(r9) -#define r10 _R(r10) -#define r11 _R(r11) -#define r12 _R(r12) -#define r13 _R(r13) -#define r14 _R(r14) -#define r15 _R(r15) -#define r16 _R(r16) -#define r17 _R(r17) -#define r18 _R(r18) -#define r19 _R(r19) -#define r20 _R(r20) -#define r21 _R(r21) -#define r22 _R(r22) -#define r23 _R(r23) -#define r24 _R(r24) -#define r25 _R(r25) -#define r26 _R(r26) -#define r27 _R(r27) -#define r28 _R(r28) -#define r29 _R(r29) -#define r30 _R(r30) -#define r31 _R(r31) - -#ifndef __tmp_reg__ -#define __tmp_reg__ r0 -#endif - -#ifndef __zero_reg__ -#define __zero_reg__ r1 -#endif - -#if __AVR_MEGA__ - #define XJMP jmp - #define XCALL call -#else - #define XJMP rjmp - #define XCALL rcall -#endif - -/* used only by fplib/strtod.S - libgcc internal function calls */ -#define PROLOGUE_SAVES(offset) XJMP (__prologue_saves__ + 2 * (offset)) -#define EPILOGUE_RESTORES(offset) XJMP (__epilogue_restores__ + 2 * (offset)) - -#if FLASHEND > 0x10000 /* ATmega103 */ - #define BIG_CODE 1 -#else - #define BIG_CODE 0 -#endif - -#ifndef __AVR_HAVE_MOVW__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_MOVW__ 1 -# endif -#endif - -#ifndef __AVR_HAVE_LPMX__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_LPMX__ 1 -# endif -#endif - -#ifndef __AVR_HAVE_MUL__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_MUL__ 1 -# endif -#endif - -/* - Smart version of movw: - - uses "movw" if possible (supported by MCU, and both registers even) - - handles overlapping register pairs correctly - - no instruction generated if source and destination are the same - (may expand to 0, 1 or 2 instructions). - */ - -.macro X_movw dst src - .L_movw_dst = -1 - .L_movw_src = -1 - .L_movw_n = 0 - .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ - r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ - r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ - r30,r31 - .ifc \reg,\dst - .L_movw_dst = .L_movw_n - .endif - .ifc \reg,\src - .L_movw_src = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .L_movw_n = 0 - .irp reg, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ - R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ - R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ - R30,R31 - .ifc \reg,\dst - .L_movw_dst = .L_movw_n - .endif - .ifc \reg,\src - .L_movw_src = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .if .L_movw_dst < 0 - .L_movw_n = 0 - .rept 32 - .if \dst == .L_movw_n - .L_movw_dst = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .endif - .if .L_movw_src < 0 - .L_movw_n = 0 - .rept 32 - .if \src == .L_movw_n - .L_movw_src = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .endif - .if (.L_movw_dst < 0) || (.L_movw_src < 0) - .err ; Invalid 'X_movw' arg. - .endif - - .if ((.L_movw_src) - (.L_movw_dst)) /* different registers */ - .if (((.L_movw_src) | (.L_movw_dst)) & 0x01) - .if (((.L_movw_src)-(.L_movw_dst)) & 0x80) /* src < dest */ - mov (.L_movw_dst)+1, (.L_movw_src)+1 - mov (.L_movw_dst), (.L_movw_src) - .else /* src > dest */ - mov (.L_movw_dst), (.L_movw_src) - mov (.L_movw_dst)+1, (.L_movw_src)+1 - .endif - .else /* both even -> overlap not possible */ -#if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ - movw \dst, \src -#else - mov (.L_movw_dst), (.L_movw_src) - mov (.L_movw_dst)+1, (.L_movw_src)+1 -#endif - .endif - .endif -.endm - -/* Macro 'X_lpm' extends enhanced lpm instruction for classic chips. - Usage: - X_lpm reg, dst - where - reg is 0..31, r0..r31 or R0..R31 - dst is z, Z, z+ or Z+ - It is possible to omit both arguments. - - Possible results for classic chips: - lpm - lpm / mov Rd,r0 - lpm / adiw ZL,1 - lpm / mov Rd,r0 / adiw ZL,1 - - For enhanced chips it is one instruction always. - - ATTENTION: unlike enhanced chips SREG (S,V,N,Z,C) flags are - changed in case of 'Z+' dst. R0 is scratch. - */ -.macro X_lpm dst=r0, src=Z - - /* dst evaluation */ - .L_lpm_dst = -1 - - .L_lpm_n = 0 - .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ - r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ - r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ - r30,r31 - .ifc \reg,\dst - .L_lpm_dst = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - - .L_lpm_n = 0 - .irp reg, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ - R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ - R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ - R30,R31 - .ifc \reg,\dst - .L_lpm_dst = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - - .if .L_lpm_dst < 0 - .L_lpm_n = 0 - .rept 32 - .if \dst == .L_lpm_n - .L_lpm_dst = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - .endif - - .if (.L_lpm_dst < 0) - .err ; Invalid dst arg of 'X_lpm' macro. - .endif - - /* src evaluation */ - .L_lpm_src = -1 - .L_lpm_n = 0 - .irp reg, z,Z,z+,Z+ - .ifc \reg,\src - .L_lpm_src = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - - .if (.L_lpm_src < 0) - .err ; Invalid src arg of 'X_lpm' macro. - .endif - - /* instruction(s) */ - .if .L_lpm_src < 2 - .if .L_lpm_dst == 0 - lpm - .else -#if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ - lpm .L_lpm_dst, Z -#else - lpm - mov .L_lpm_dst, r0 -#endif - .endif - .else - .if (.L_lpm_dst >= 30) - .err ; Registers 30 and 31 are inhibited as 'X_lpm *,Z+' dst. - .endif -#if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ - lpm .L_lpm_dst, Z+ -#else - lpm - .if .L_lpm_dst - mov .L_lpm_dst, r0 - .endif - adiw r30, 1 -#endif - .endif -.endm - -/* - LPM_R0_ZPLUS_INIT is used before the loop to initialize RAMPZ - for future devices with RAMPZ:Z auto-increment - [e]lpm r0, Z+. - - LPM_R0_ZPLUS_NEXT is used inside the loop to load a byte from - the program memory at [RAMPZ:]Z to R0, and increment [RAMPZ:]Z. - - The argument in both macros is a register that contains the - high byte (bits 23-16) of the address, bits 15-0 should be in - the Z (r31:r30) register. It can be any register except for: - r0, r1 (__zero_reg__ - assumed to always contain 0), r30, r31. - */ - - .macro LPM_R0_ZPLUS_INIT hhi -#if __AVR_ENHANCED__ - #if BIG_CODE - out AVR_RAMPZ_ADDR, \hhi - #endif -#endif - .endm - - .macro LPM_R0_ZPLUS_NEXT hhi -#if __AVR_ENHANCED__ - #if BIG_CODE - /* ELPM with RAMPZ:Z post-increment, load RAMPZ only once */ - elpm r0, Z+ - #else - /* LPM with Z post-increment, max 64K, no RAMPZ (ATmega83/161/163/32) */ - lpm r0, Z+ - #endif -#else - #if BIG_CODE - /* ELPM without post-increment, load RAMPZ each time (ATmega103) */ - out AVR_RAMPZ_ADDR, \hhi - elpm - adiw r30,1 - adc \hhi, __zero_reg__ - #else - /* LPM without post-increment, max 64K, no RAMPZ (AT90S*) */ - lpm - adiw r30,1 - #endif -#endif - .endm - -#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h deleted file mode 100644 index f3baec4451..0000000000 --- a/cpukit/score/cpu/avr/rtems/score/cpu.h +++ /dev/null @@ -1,1176 +0,0 @@ -/** - * @file - * - * @brief Intel AVR CPU Department Source - * - * This include file contains information pertaining to the AVR - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/avr.h> -#include <avr/common.h> - -/* conditional compilation parameters */ - -#ifndef RTEMS_USE_16_BIT_OBJECT -#define RTEMS_USE_16_BIT_OBJECT -#endif - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "AVR_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if ( AVR_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALL_TASKS_ARE_FP TRUE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - uint16_t stack_pointer; - uint8_t status; /* SREG */ -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->stack_pointer - - - - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -#endif /* ASM */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_MINIMUM_SIZE 512 - -/* - * Maximum priority of a thread. Note based from 0 which is the idle task. - */ -#define CPU_PRIORITY_MAXIMUM 15 - -#define CPU_SIZEOF_POINTER 2 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = SREG; \ - __asm__ volatile ("cli"::); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - SREG = _isr_cookie; \ - __asm__ volatile ("sei"::); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - SREG=(_isr_cookie); \ - __asm__ volatile("sei"::); \ - (_isr_cookie) = SREG; \ - __asm__ volatile("cli"::); \ - } while (0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * AVR Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#ifndef ASM -static inline void _CPU_ISR_Set_level( unsigned int new_level ) -{ -} - - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ -/* -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - \ - do { \ - uint16_t *_stack;\ - _stack = (uint16_t) (_stack_base) + (uint16_t)(_size);\ - (_the_context)->stack_pointer = _stack-1; \ - *(_stack) = *(_entry_point); \ - printk("the ret address is %x\n", *(uint16_t *)(_stack));\ - printk("sp = 0x%x\nep = 0x%x\n",_stack, *(_entry_point)); \ - printk("stack base = 0x%x\n size = 0x%x\n",_stack_base, _size);\ - printk("struct starting address = 0x%x\n", _the_context);\ - printk("struct stack pointer address = 0x%x\n",(_the_context)->stack_pointer);\ - } while ( 0 ) - -*/ -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( _the_context ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/*context_initialize asm-function*/ - -void context_initialize(unsigned short* context, - unsigned short stack_add, - unsigned short entry_point); - -/* - * _CPU_Context_Initialize - * - * This kernel routine initializes the basic non-FP context area associated - * with each thread. - * - * Input parameters: - * the_context - pointer to the context area - * stack_base - address of memory for the SPARC - * size - size in bytes of the stack area - * new_level - interrupt level for this context area - * entry_point - the starting execution point for this this context - * is_fp - TRUE if this context is associated with an FP thread - * - * Output parameters: NONE - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* -* -* _CPU_Push -* -* this routine pushes 2 bytes onto the stack -* -* -* -* -* -* -* -*/ - -void _CPU_Push(uint16_t _SP_, uint16_t entry_point); - - - - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h b/cpukit/score/cpu/avr/rtems/score/cpu_asm.h deleted file mode 100644 index af920d143e..0000000000 --- a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief Intel AVR Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/avr/rtems/score/types.h b/cpukit/score/cpu/avr/rtems/score/types.h deleted file mode 100644 index f63f5d5a3b..0000000000 --- a/cpukit/score/cpu/avr/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Intel AVR CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * avr processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void avr_isr; -typedef void ( *avr_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/asm.h b/cpukit/score/cpu/bfin/rtems/asm.h deleted file mode 100644 index 5d133ddbdd..0000000000 --- a/cpukit/score/cpu/bfin/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/bfin.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h deleted file mode 100644 index ebcfe1e15e..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpu.h +++ /dev/null @@ -1,1278 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Department Source - * - * This include file contains information pertaining to the Blackfin - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch> - * and Antonio Giovanini <antonio@atos.com.br> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/bfin.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * BFIN Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( BLACKFIN_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN FALSE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN TRUE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ - -/* make sure this stays in sync with the assembly function - __CPU_Context_switch in cpu_asm.S */ -typedef struct { - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - - uint32_t register_p3; - uint32_t register_p4; - uint32_t register_p5; - uint32_t register_fp; - uint32_t register_sp; - - uint32_t register_rets; - - uint32_t imask; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /* FPU registers are listed here */ - /* Blackfin has no Floating Point */ -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - /*uint32_t special_interrupt_register;*/ -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif /* ASM */ - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 - -/** - * @ingroup CPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 8 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _level ) \ - { \ - __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ - } - - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _level ) { \ - __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ - } - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _level ) { \ - __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ - : : "d"(_level) : "R0" ); \ - } - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ - } - -#ifndef ASM - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * See implementation in cpu.c - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - __asm__ volatile ( "cli R1; \ - R1 = %0; \ - _halt: \ - idle; \ - jump _halt;"\ - : : "r" (_error) ); \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - __asm__ ("bit(1);"): - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** @} */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h deleted file mode 100644 index 4f78c9d358..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h +++ /dev/null @@ -1,27 +0,0 @@ -/** - * @file - * - * @brief Blackfin Assembly File - * - * Defines a couple of Macros used in cpu_asm.S - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer <alain.schaefer@easc.ch> - * and Antonio Giovanini <antonio@atos.com.br> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/bfin/rtems/score/types.h b/cpukit/score/cpu/bfin/rtems/score/types.h deleted file mode 100644 index eaa8de6bd9..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/types.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Blackfin processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -/** This defines the return type for an ISR entry point. */ -typedef void blackfin_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef blackfin_isr ( *blackfin_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/asm.h b/cpukit/score/cpu/epiphany/rtems/asm.h deleted file mode 100644 index 87e0cca1cb..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef __EPIPHANY_ASM_H -#define __EPIPHANY_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/epiphany.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .extern SYM (sym) -#define TYPE_FUNC(sym) .type SYM (sym), %function - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h b/cpukit/score/cpu/epiphany/rtems/score/cpu.h deleted file mode 100644 index d0cbb64b44..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h +++ /dev/null @@ -1,1163 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _EPIPHANY_CPU_H -#define _EPIPHANY_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/epiphany.h> /* pick up machine definitions */ -#include <rtems/score/types.h> -#ifndef ASM -#include <rtems/bspIo.h> -#include <stdint.h> -#include <stdio.h> /* for printk */ -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Currently, for epiphany port, _ISR_Handler is responsible for switching to - * RTEMS dedicated interrupt task. - * - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "epiphany_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * epiphany Specific Information: - * - * At this time there are no implementations of Epiphany that are - * expected to implement floating point. - */ - -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - */ - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * epiphany Specific Information: - * - * This version of RTEMS is designed specifically to run with - * big endian architectures. If you want little endian, you'll - * have to make the appropriate adjustments here and write - * efficient routines for byte swapping. The epiphany architecture - * doesn't do this very well. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * - */ -#ifndef ASM - -typedef struct { - uint32_t r[64]; - - uint32_t status; - uint32_t config; - uint32_t iret; - -#ifdef RTEMS_SMP - /** - * @brief On SMP configurations the thread context must contain a boolean - * indicator to signal if this context is executing on a processor. - * - * This field must be updated during a context switch. The context switch - * to the heir must wait until the heir context indicates that it is no - * longer executing on a processor. The context switch must also check if - * a thread dispatch is necessary to honor updates of the heir thread for - * this processor. This indicator must be updated using an atomic test and - * set operation to ensure that at most one processor uses the heir - * context at the same time. - * - * @code - * void _CPU_Context_switch( - * Context_Control *executing, - * Context_Control *heir - * ) - * { - * save( executing ); - * - * executing->is_executing = false; - * memory_barrier(); - * - * if ( test_and_set( &heir->is_executing ) ) { - * do { - * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); - * - * if ( cpu_self->dispatch_necessary ) { - * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); - * } - * } while ( test_and_set( &heir->is_executing ) ); - * } - * - * restore( heir ); - * } - * @endcode - */ - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r[13] - -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * epiphany Specific Information: - * - */ - -#define CPU_CONTEXT_FP_SIZE 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - */ - -#define CPU_ALIGNMENT 8 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - */ - -#define CPU_STACK_ALIGNMENT 8 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline uint32_t epiphany_interrupt_disable( void ) -{ - uint32_t sr; - __asm__ __volatile__ ("movfs %[sr], status \n" : [sr] "=r" (sr):); - __asm__ __volatile__("gid \n"); - return sr; -} - -static inline void epiphany_interrupt_enable(uint32_t level) -{ - __asm__ __volatile__("gie \n"); - __asm__ __volatile__ ("movts status, %[level] \n" :: [level] "r" (level):); -} - -#define _CPU_ISR_Disable( _level ) \ - _level = epiphany_interrupt_disable() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - */ - -#define _CPU_ISR_Enable( _level ) \ - epiphany_interrupt_enable( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - */ - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - if ( (_level & 0x2) != 0 ) \ - _CPU_ISR_Enable( _level ); \ - epiphany_interrupt_disable(); \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - */ - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - */ - -/** - * @brief Account for GCC red-zone - * - * The following macro is used when initializing task's stack - * to account for GCC red-zone. - */ - -#define EPIPHANY_GCC_RED_ZONE_SIZE 128 - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ) - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - */ - -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - asm("trap 3" :: "r" (_error)); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - */ - - /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - (1 << _bit_number) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { -/* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; -#endif /* ASM */ - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 -#define CPU_EXCEPTION_FRAME_SIZE 260 -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM -typedef uint16_t Priority_bit_map_Word; - -typedef struct { - uint32_t r[62]; - uint32_t status; - uint32_t config; - uint32_t iret; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * epiphany Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef RTEMS_SMP - /** - * @brief Performs CPU specific SMP initialization in the context of the boot - * processor. - * - * This function is invoked on the boot processor during system - * initialization. All interrupt stacks are allocated at this point in case - * the CPU port allocates the interrupt stacks. This function is called - * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is - * used. - * - * @return The count of physically or virtually available processors. - * Depending on the configuration the application may use not all processors. - */ - uint32_t _CPU_SMP_Initialize( void ); - - /** - * @brief Starts a processor specified by its index. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after _CPU_SMP_Initialize(). - * - * @param[in] cpu_index The processor index. - * - * @retval true Successful operation. - * @retval false Unable to start this processor. - */ - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - /** - * @brief Performs final steps of CPU specific SMP initialization in the - * context of the boot processor. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after all processors requested by the - * application have been started. - * - * @param[in] cpu_count The minimum value of the count of processors - * requested by the application configuration and the count of physically or - * virtually available processors. - */ - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - /** - * @brief Returns the index of the current processor. - * - * An architecture specific method must be used to obtain the index of the - * current processor in the system. The set of processor indices is the - * range of integers starting with zero up to the processor count minus one. - */ - uint32_t _CPU_SMP_Get_current_processor( void ); - - /** - * @brief Sends an inter-processor interrupt to the specified target - * processor. - * - * This operation is undefined for target processor indices out of range. - * - * @param[in] target_processor_index The target processor index. - */ - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - /** - * @brief Broadcasts a processor event. - * - * Some architectures provide a low-level synchronization primitive for - * processors in a multi-processor environment. Processors waiting for this - * event may go into a low-power state and stop generating system bus - * transactions. This function must ensure that preceding store operations - * can be observed by other processors. - * - * @see _CPU_SMP_Processor_event_receive(). - */ - void _CPU_SMP_Processor_event_broadcast( void ); - - /** - * @brief Receives a processor event. - * - * This function will wait for the processor event and may wait forever if no - * such event arrives. - * - * @see _CPU_SMP_Processor_event_broadcast(). - */ - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - /** - * @brief Gets the is executing indicator of the thread context. - * - * @param[in] context The context. - */ - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - /** - * @brief Sets the is executing indicator of the thread context. - * - * @param[in] context The context. - * @param[in] is_executing The new value for the is executing indicator. - */ - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif /* RTEMS_SMP */ - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h b/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h deleted file mode 100644 index cc091fa909..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief Epiphany Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/types.h b/cpukit/score/cpu/epiphany/rtems/score/types.h deleted file mode 100644 index 5b6c503739..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/types.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * - * @brief Epiphany Architecture Types API - */ - -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - #ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void epiphany_isr; -typedef void ( *epiphany_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/h8300/rtems/asm.h b/cpukit/score/cpu/h8300/rtems/asm.h deleted file mode 100644 index 6c1a643db4..0000000000 --- a/cpukit/score/cpu/h8300/rtems/asm.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#include <rtems/score/h8300.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) - -#define er0 REG(er0) -#define er1 REG(er1) -#define er2 REG(er2) -#define er3 REG(er3) -#define er4 REG(er4) -#define er5 REG(er5) -#define er6 REG(er6) -#define er7 REG(er7) - -#define sp REG(sp) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE __asm__ ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h deleted file mode 100644 index 8b34bb4c7f..0000000000 --- a/cpukit/score/cpu/h8300/rtems/score/cpu.h +++ /dev/null @@ -1,1176 +0,0 @@ -/** - * @file - * - * @brief Hitachi H8300 CPU Department Source - * - * This include file contains information pertaining to the H8300 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/h8300.h> -#ifndef ASM - #include <rtems/bspIo.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should this target use 16 or 32 bit object Ids? - * - */ -#define RTEMS_USE_16_BIT_OBJECT - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * H8300 Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "H8300_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * H8300 Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * H8300 Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * H8300 Specific Information: - * - * XXX - */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -#define nogap __attribute__ ((packed)) - -typedef struct { - uint16_t ccr nogap; - void *er7 nogap; - void *er6 nogap; - uint32_t er5 nogap; - uint32_t er4 nogap; - uint32_t er3 nogap; - uint32_t er2 nogap; - uint32_t er1 nogap; - uint32_t er0 nogap; - uint32_t xxx nogap; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->er7 - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * H8300 Specific Information: - * - * XXX - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif /* ASM */ - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * H8300 Specific Information: - * - * It is highly unlikely the H8300 will get used in a multiprocessor system. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_MINIMUM_SIZE (1536) - -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) - #define CPU_SIZEOF_POINTER 4 -#else - #define CPU_SIZEOF_POINTER 2 -#endif - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_ALIGNMENT 2 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. - Note requires ISR_Level be uint16_t or assembler croaks. -*/ - -#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 ) - - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \ - } while (0) - -/* end of ISR handler macros */ - -#else /* modern gcc version */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * H8300 Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented for the SX. - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned char __ccr; \ - __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \ - : "=m" (__ccr) /* : "0" (__ccr) */ ); \ - (_isr_cookie) = __ccr; \ - } while (0) -#else -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) -#endif - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * H8300 Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented for the SX. - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - __asm__ volatile( "ldc %0, ccr" : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) -#endif - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * H8300 Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented for the SX. - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) -#endif - -#endif /* end of old gcc */ - - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \ - else __asm__ volatile ( "andc #0x7f,ccr\n" ); \ - } - -#ifndef ASM - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * H8300 Specific Information: - * - * XXX - */ - - -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - /* Locate Me */ \ - do { \ - uintptr_t _stack; \ - \ - if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ - else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ - \ - (void) _is_fp; /* to eliminate set but not used warning */ \ - _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->er7 = (void *) _stack; \ - (_the_context)->er6 = (void *) _stack; \ - (_the_context)->er5 = 0; \ - (_the_context)->er4 = 1; \ - (_the_context)->er3 = 2; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - for(;;) - - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void *_CPU_Thread_Idle_body( uint32_t ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * H8300 Specific Information: - * - * This is the generic implementation. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -/* to be provided by the BSP */ -extern void H8BD_Install_IRQ( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler ); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/h8300/rtems/score/types.h b/cpukit/score/cpu/h8300/rtems/score/types.h deleted file mode 100644 index 7fcac8b552..0000000000 --- a/cpukit/score/cpu/h8300/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Hitachi H8300 CPU Type Definitions - * - * This include file contains type definitions pertaining to the Hitachi - * h8300 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void h8300_isr; -typedef void ( *h8300_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/i386/rtems/asm.h b/cpukit/score/cpu/i386/rtems/asm.h deleted file mode 100644 index 50b0fd71a0..0000000000 --- a/cpukit/score/cpu/i386/rtems/asm.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/i386.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -/* - * Looks like there is a bug in gcc 2.6.2 where this is not - * defined correctly when configured as i386-coff and - * i386-aout. - */ - -#undef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ % - -/* -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif -*/ - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) - -#define eax REG (eax) -#define ebx REG (ebx) -#define ecx REG (ecx) -#define edx REG (edx) -#define esi REG (esi) -#define edi REG (edi) -#define esp REG (esp) -#define ebp REG (ebp) -#define cr0 REG (cr0) -#define cr4 REG (cr4) - -#define ax REG (ax) -#define bx REG (bx) -#define cx REG (cx) -#define dx REG (dx) -#define si REG (si) -#define di REG (di) -#define sp REG (sp) -#define bp REG (bp) - -#define ah REG (ah) -#define bh REG (bh) -#define ch REG (ch) -#define dh REG (dh) - -#define al REG (al) -#define bl REG (bl) -#define cl REG (cl) -#define dl REG (dl) - -#define cs REG (cs) -#define ds REG (ds) -#define es REG (es) -#define fs REG (fs) -#define gs REG (gs) -#define ss REG (ss) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h deleted file mode 100644 index 4f0cd6e6b0..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/cpu.h +++ /dev/null @@ -1,748 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Dependent Source - * - * This include file contains information pertaining to the Intel - * i386 processor. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifndef ASM -#include <string.h> /* for memcpy */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/i386.h> - -#ifndef ASM -#include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ -#include <rtems/score/registers.h> /* formerly part of libcpu */ -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * i386 has an RTEMS allocated and managed interrupt stack. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the i387 - * for the i386, others have it built in (i486DX, Pentium). - */ - -#ifdef __SSE__ -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP TRUE -#define CPU_IDLE_TASK_IS_FP TRUE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else /* __SSE__ */ - -#if ( I386_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE /* i387 for i386 */ -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#if defined(RTEMS_SMP) - #define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else - #define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif -#endif /* __SSE__ */ - -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 -#define I386_CONTEXT_CONTROL_ESP_OFFSET 4 -#define I386_CONTEXT_CONTROL_EBP_OFFSET 8 -#define I386_CONTEXT_CONTROL_EBX_OFFSET 12 -#define I386_CONTEXT_CONTROL_ESI_OFFSET 16 -#define I386_CONTEXT_CONTROL_EDI_OFFSET 20 - -#ifdef RTEMS_SMP - #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 24 -#endif - -/* structures */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Basic integer context for the i386 family. - */ - -typedef struct { - uint32_t eflags; /* extended flags register */ - void *esp; /* extended stack pointer register */ - void *ebp; /* extended base pointer register */ - uint32_t ebx; /* extended bx register */ - uint32_t esi; /* extended source index register */ - uint32_t edi; /* extended destination index flags register */ -#ifdef RTEMS_SMP - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->esp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -/* - * FP context save area for the i387 numeric coprocessors. - */ -#ifdef __SSE__ -/* All FPU and SSE registers are volatile; hence, as long - * as we are within normally executing C code (including - * a task switch) there is no need for saving/restoring - * any of those registers. - * We must save/restore the full FPU/SSE context across - * interrupts and exceptions, however: - * - after ISR execution a _Thread_Dispatch() may happen - * and it is therefore necessary to save the FPU/SSE - * registers to be restored when control is returned - * to the interrupted task. - * - gcc may implicitly use FPU/SSE instructions in - * an ISR. - * - * Even though there is no explicit mentioning of the FPU - * control word in the SYSV ABI (i386) being non-volatile - * we maintain MXCSR and the FPU control-word for each task. - */ -typedef struct { - uint32_t mxcsr; - uint16_t fpucw; -} Context_Control_fp; - -#else - -typedef struct { - uint8_t fp_save_area[108]; /* context size area for I80387 */ - /* 28 bytes for environment */ -} Context_Control_fp; - -#endif - - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of execptions. - * - * idtIndex is either the interrupt number or the trap/exception number. - * faultCode is the code pushed by the processor on some exceptions. - * - * Since the first registers are directly pushed by the CPU they - * may not respect 16-byte stack alignment, which is, however, - * mandatory for the SSE register area. - * Therefore, these registers are stored at an aligned address - * and a pointer is stored in the CPU_Exception_frame. - * If the executive was compiled without SSE support then - * this pointer is NULL. - */ - -struct Context_Control_sse; - -typedef struct { - struct Context_Control_sse *fp_ctxt; - uint32_t edi; - uint32_t esi; - uint32_t ebp; - uint32_t esp0; - uint32_t ebx; - uint32_t edx; - uint32_t ecx; - uint32_t eax; - uint32_t idtIndex; - uint32_t faultCode; - uint32_t eip; - uint32_t cs; - uint32_t eflags; -} CPU_Exception_frame; - -#ifdef __SSE__ -typedef struct Context_Control_sse { - uint16_t fcw; - uint16_t fsw; - uint8_t ftw; - uint8_t res_1; - uint16_t fop; - uint32_t fpu_ip; - uint16_t cs; - uint16_t res_2; - uint32_t fpu_dp; - uint16_t ds; - uint16_t res_3; - uint32_t mxcsr; - uint32_t mxcsr_mask; - struct { - uint8_t fpreg[10]; - uint8_t res_4[ 6]; - } fp_mmregs[8]; - uint8_t xmmregs[8][16]; - uint8_t res_5[224]; -} Context_Control_sse -__attribute__((aligned(16))) -; -#endif - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(void); - -/* - * This port does not pass any frame info to the - * interrupt handler. - */ - -typedef void CPU_Interrupt_frame; - -typedef enum { - I386_EXCEPTION_DIVIDE_BY_ZERO = 0, - I386_EXCEPTION_DEBUG = 1, - I386_EXCEPTION_NMI = 2, - I386_EXCEPTION_BREAKPOINT = 3, - I386_EXCEPTION_OVERFLOW = 4, - I386_EXCEPTION_BOUND = 5, - I386_EXCEPTION_ILLEGAL_INSTR = 6, - I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, - I386_EXCEPTION_DOUBLE_FAULT = 8, - I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, - I386_EXCEPTION_INVALID_TSS = 10, - I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, - I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, - I386_EXCEPTION_GENERAL_PROT_ERR = 13, - I386_EXCEPTION_PAGE_FAULT = 14, - I386_EXCEPTION_INTEL_RES15 = 15, - I386_EXCEPTION_FLOAT_ERROR = 16, - I386_EXCEPTION_ALIGN_CHECK = 17, - I386_EXCEPTION_MACHINE_CHECK = 18, - I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ - -} Intel_symbolic_exception_name; - - -/* - * context size area for floating point - * - * NOTE: This is out of place on the i386 to avoid a forward reference. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On i386 thread stacks require no further alignment after allocation - * from the Workspace. However, since gcc maintains 16-byte alignment - * we try to respect that. If you find an option to let gcc squeeze - * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still - * doesn't waste much space since this only determines the *initial* - * alignment. - */ - -#define CPU_STACK_ALIGNMENT 16 - -/* macros */ - -#ifndef ASM -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) __asm__ volatile ( "cli" ); \ - else __asm__ volatile ( "sti" ); \ - } - -uint32_t _CPU_ISR_Get_level( void ); - -/* Make sure interrupt stack has space for ISR - * 'vector' arg at the top and that it is aligned - * properly. - */ - -#define _CPU_Interrupt_stack_setup( _lo, _hi ) \ - do { \ - _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ - } while (0) - -#endif /* ASM */ - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 -#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 - -#ifndef ASM - -/* - * Stack alignment note: - * - * We want the stack to look to the '_entry_point' routine - * like an ordinary stack frame as if '_entry_point' was - * called from C-code. - * Note that '_entry_point' is jumped-to by the 'ret' - * instruction returning from _CPU_Context_switch() or - * _CPU_Context_restore() thus popping the _entry_point - * from the stack. - * However, _entry_point expects a frame to look like this: - * - * args [_Thread_Handler expects no args, however] - * ------ (alignment boundary) - * SP-> return_addr return here when _entry_point returns which (never happens) - * - * - * Hence we must initialize the stack as follows - * - * [arg1 ]: n/a - * [arg0 (aligned)]: n/a - * [ret. addr ]: NULL - * SP-> [jump-target ]: _entry_point - * - * When Context_switch returns it pops the _entry_point from - * the stack which then finds a standard layout. - */ - - - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - do { \ - uint32_t _stack; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ - else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ - \ - _stack = ((uint32_t)(_stack_base)) + (_size); \ - _stack &= ~ (CPU_STACK_ALIGNMENT - 1); \ - _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->ebp = (void *) 0; \ - (_the_context)->esp = (void *) _stack; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#if defined(RTEMS_SMP) - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - uint32_t _CPU_SMP_Get_current_processor( void ); - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ - } - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - uint32_t _error_lvalue = ( _error ); \ - __asm__ volatile ( "cli ; \ - movl %0,%%eax ; \ - hlt" \ - : "=r" ((_error_lvalue)) : "0" ((_error_lvalue)) \ - ); \ - } - -#endif /* ASM */ - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register uint16_t __value_in_register = (_value); \ - \ - _output = 0; \ - \ - __asm__ volatile ( "bsfw %0,%1 " \ - : "=r" (__value_in_register), "=r" (_output) \ - : "0" (__value_in_register), "1" (_output) \ - ); \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* functions */ - -#ifndef ASM -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * Use the halt instruction of low power mode of a particular i386 model. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -#ifdef __SSE__ -#define _CPU_Context_save_fp(fp_context_pp) \ - do { \ - __asm__ __volatile__( \ - "fstcw %0" \ - :"=m"((*(fp_context_pp))->fpucw) \ - ); \ - __asm__ __volatile__( \ - "stmxcsr %0" \ - :"=m"((*(fp_context_pp))->mxcsr) \ - ); \ - } while (0) -#else -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ -#ifdef __SSE__ -#define _CPU_Context_restore_fp(fp_context_pp) \ - do { \ - __asm__ __volatile__( \ - "fldcw %0" \ - ::"m"((*(fp_context_pp))->fpucw) \ - :"fpcr" \ - ); \ - __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ - } while (0) -#else -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -#ifdef __SSE__ -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ __volatile__( \ - "finit" \ - : \ - : \ - :"st","st(1)","st(2)","st(3)", \ - "st(4)","st(5)","st(6)","st(7)", \ - "fpsr","fpcr" \ - ); \ - if ( _Thread_Executing->fp_context ) { \ - _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ - } \ - } while (0) -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/types.h b/cpukit/score/cpu/i386/rtems/score/types.h deleted file mode 100644 index 40ccecb1f8..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * i386 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void i386_isr; -typedef i386_isr ( *i386_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/asm.h b/cpukit/score/cpu/lm32/rtems/asm.h deleted file mode 100644 index 15046df81c..0000000000 --- a/cpukit/score/cpu/lm32/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/lm32.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h deleted file mode 100644 index e783331cc7..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpu.h +++ /dev/null @@ -1,1281 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Department Source - * - * This include file contains information pertaining to the LM32 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/lm32.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * L2 cache lines are 32 bytes in Milkymist SoC - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t ie; - uint32_t epc; -} Context_Control; - -/** - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t ra; - uint32_t ba; - uint32_t ea; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * The LM32 architecture manual simply states: "All memory accesses must be - * aligned to the size of the access", and there is no hardware support - * whatsoever for 64-bit numbers. - * (lm32_archman.pdf, July 2009, p. 15) - */ -#define CPU_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. - * - * - * Port Specific Information: - * - * Stack is software-managed - */ -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - lm32_disable_interrupts( _isr_cookie ); - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - lm32_enable_interrupts( _isr_cookie ); - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - lm32_flash_interrupts( _isr_cookie ); - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \ - } - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -extern char _gp[]; - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - do { \ - uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - (void) _isr; /* avoid warning for being unused */ \ - (_the_context)->gp = (uint32_t)_gp; \ - (_the_context)->fp = (uint32_t)_stack; \ - (_the_context)->sp = (uint32_t)_stack; \ - (_the_context)->ra = (uint32_t)(_entry_point); \ - } while ( 0 ) - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) -#if 0 - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) -#if 0 - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** @} */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** @} */ - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -static inline uint16_t CPU_swap_u16(uint16_t v) -{ - return v << 8 | v >> 8; -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h b/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h deleted file mode 100644 index 3909c1d608..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/lm32/rtems/score/types.h b/cpukit/score/cpu/lm32/rtems/score/types.h deleted file mode 100644 index c0fc8a8a89..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/types.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Lattice lm32 processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, - * Micro-Research Finland Oy - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/asm.h b/cpukit/score/cpu/m32c/rtems/asm.h deleted file mode 100644 index f3f244d066..0000000000 --- a/cpukit/score/cpu/m32c/rtems/asm.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/m32c.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * @see __USER_LABEL_PREFIX__ - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** - * This macro is used to denote the beginning of a data declaration section. - */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @see PUBLIC(sym) .globl SYM (sym) - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h b/cpukit/score/cpu/m32c/rtems/score/cpu.h deleted file mode 100644 index fdee5729ed..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpu.h +++ /dev/null @@ -1,1229 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Dependent Source - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/m32c.h> - -/* conditional compilation parameters */ - -#define RTEMS_USE_16_BIT_OBJECT - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "M32C_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( M32C_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_CONTEXT_FP_SIZE 0 - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (2))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * @ingroup Management - * - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - /** This will contain the stack pointer. */ - uint32_t sp; - /** This will contain the frame base pointer. */ - uint32_t fb; -} Context_Control; - -/** - * @ingroup Management - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * @ingroup Management - * - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** - * This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - * - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** This defines the highest interrupt vector number for this port. */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (2048L) - -#ifdef __m32cm_cpu__ - #define CPU_SIZEOF_POINTER 4 -#else - #define CPU_SIZEOF_POINTER 2 -#endif - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 2 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - int _flg; \ - m32c_get_flg( _flg ); \ - _isr_cookie = _flg; \ - __asm__ volatile( "fclr I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable(_isr_cookie) \ - do { \ - int _flg = (int) (_isr_cookie); \ - m32c_set_flg( _flg ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - int _flg = (int) (_isr_cookie); \ - m32c_set_flg( _flg ); \ - __asm__ volatile( "fclr I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - *This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - do { \ - if (_new_level) __asm__ volatile( "fclr I" ); \ - else __asm__ volatile( "fset I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/** - * @ingroup CPUContext - * - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/** @} */ - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h deleted file mode 100644 index 451c022d75..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/m32c/rtems/score/types.h b/cpukit/score/cpu/m32c/rtems/score/types.h deleted file mode 100644 index 11e0a0ceb4..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/types.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * m32c processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -/** This defines the return type for an ISR entry point. */ -typedef void m32c_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef m32c_isr ( *m32c_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m32r/rtems/asm.h b/cpukit/score/cpu/m32r/rtems/asm.h deleted file mode 100644 index 11f5b876b9..0000000000 --- a/cpukit/score/cpu/m32r/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/m32r.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu.h b/cpukit/score/cpu/m32r/rtems/score/cpu.h deleted file mode 100644 index 9ad41cd2c6..0000000000 --- a/cpukit/score/cpu/m32r/rtems/score/cpu.h +++ /dev/null @@ -1,1272 +0,0 @@ -/** - * @file - * - * @brief Intel M32R CPU Dependent Source - * - * This include file contains information pertaining to the XXX - * processor. - * - * NOTE: This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/m32r.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "M32R_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( M32R_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - /** r8 -- temporary register */ - uint32_t r8; - /** r9 -- temporary register */ - uint32_t r9; - /** r10 -- temporary register */ - uint32_t r10; - /** r11 -- temporary register */ - uint32_t r11; - /** r12 -- may be global pointer */ - uint32_t r12; - /** r13 -- frame pointer */ - uint32_t r13_fp; - /** r14 -- link register (aka return pointer */ - uint32_t r14_lr; - /** r15 -- stack pointer */ - uint32_t r15_sp; - /** dsp accumulator low order 32-bits */ - uint32_t acc_low; - /** dsp accumulator high order 32-bits */ - uint32_t acc_high; -} Context_Control; - -/** - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r15_sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -static inline void _CPU_ISR_Set_level( unsigned int new_level ) -{ -} - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @brief Initialize CPU context. - * - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/** @} */ - -/* functions */ - -/** - * @brief CPU initialization. - * - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h deleted file mode 100644 index ac6aac41a8..0000000000 --- a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief Intel M32R Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/m32r/rtems/score/types.h b/cpukit/score/cpu/m32r/rtems/score/types.h deleted file mode 100644 index 3ee57f2e57..0000000000 --- a/cpukit/score/cpu/m32r/rtems/score/types.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @brief Intel M32R CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * m32r processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -/** This defines the return type for an ISR entry point. */ -typedef void m32r_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef m32r_isr ( *m32r_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/asm.h b/cpukit/score/cpu/m68k/rtems/asm.h deleted file mode 100644 index cbd2a7f8b2..0000000000 --- a/cpukit/score/cpu/m68k/rtems/asm.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) -#define sp REG (sp) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) -#define vbr REG (vbr) -#define dfc REG (dfc) -#define sfc REG (sfc) - -/* mcf52xx special regs */ -#define cacr REG (cacr) -#define acr0 REG (acr0) -#define acr1 REG (acr1) -#define rambar0 REG (rambar0) -#define mbar REG (mbar) - -/* additional v4e special regs */ -#define rambar1 REG (rambar1) -#define macsr REG (macsr) -#define acc0 REG (acc0) -#define acc1 REG (acc1) -#define acc2 REG (acc2) -#define acc3 REG (acc3) -#define accext01 REG (accext01) -#define accext23 REG (accext23) -#define mask REG (mask) - - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) -#define fpsr REG (fpsr) - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h deleted file mode 100644 index 7fcbac54a8..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ /dev/null @@ -1,780 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Dependent Source - * - * This include file contains information pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/m68k.h> - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * M68K Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Use the m68k's hardware interrupt stack support and have the - * interrupt manager allocate the memory for it. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1) -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 -#else -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 -#endif -#define CPU_ALLOCATE_INTERRUPT_STACK 1 - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the - * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). - * - * NOTE: If on a CPU without hardware FP, then one can use software - * emulation. The gcc software FP emulation code has data which - * must be contexted switched on a per task basis. - */ - -#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) - #define CPU_HARDWARE_FP TRUE - #define CPU_SOFTWARE_FP FALSE -#else - #define CPU_HARDWARE_FP FALSE - #if defined( __GNUC__ ) - #define CPU_SOFTWARE_FP TRUE - #else - #define CPU_SOFTWARE_FP FALSE - #endif -#endif - -/* - * All tasks are not by default floating point tasks on this CPU. - * The IDLE task does not have a floating point context on this CPU. - * It is safe to use the deferred floating point context switch - * algorithm on this CPU. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (4))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) - #if defined( __mc68060__ ) - #define M68K_FP_STATE_SIZE 16 - #else - #define M68K_FP_STATE_SIZE 216 - #endif -#endif - -#ifndef ASM - -/* structures */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Basic integer context for the m68k family. - */ - -typedef struct { - uint32_t sr; /* (sr) status register */ - uint32_t d2; /* (d2) data register 2 */ - uint32_t d3; /* (d3) data register 3 */ - uint32_t d4; /* (d4) data register 4 */ - uint32_t d5; /* (d5) data register 5 */ - uint32_t d6; /* (d6) data register 6 */ - uint32_t d7; /* (d7) data register 7 */ - void *a2; /* (a2) address register 2 */ - void *a3; /* (a3) address register 3 */ - void *a4; /* (a4) address register 4 */ - void *a5; /* (a5) address register 5 */ - void *a6; /* (a6) address register 6 */ - void *a7_msp; /* (a7) master stack pointer */ - #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) - uint8_t fpu_dis; - #endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->a7_msp - -/* - * Floating point context areas and support routines - */ - -#if ( CPU_SOFTWARE_FP == TRUE ) - /* - * This is the same as gcc's view of the software FP condition code - * register _fpCCR. The implementation of the emulation code is - * in the gcc-VERSION/config/m68k directory. This structure is - * correct as of gcc 2.7.2.2. - */ - typedef struct { - uint16_t _exception_bits; - uint16_t _trap_enable_bits; - uint16_t _sticky_bits; - uint16_t _rounding_mode; - uint16_t _format; - uint16_t _last_operation; - union { - float sf; - double df; - } _operand1; - union { - float sf; - double df; - } _operand2; - } Context_Control_fp; - - /* - * This software FP implementation is only for GCC. - */ - #define _CPU_Context_Fp_start( _base, _offset ) \ - ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) - - #define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - Context_Control_fp *_fp; \ - _fp = *(Context_Control_fp **)_fp_area; \ - _fp->_exception_bits = 0; \ - _fp->_trap_enable_bits = 0; \ - _fp->_sticky_bits = 0; \ - _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ - _fp->_format = 0; /* NIL */ \ - _fp->_last_operation = 0; /* NOOP */ \ - _fp->_operand1.df = 0; \ - _fp->_operand2.df = 0; \ - } -#endif - -#if ( CPU_HARDWARE_FP == TRUE ) - #if defined( __mcoldfire__ ) - /* We need memset() to initialize the FP context */ - #include <string.h> - - #if ( M68K_HAS_FPU == 1 ) - /* - * The Cache Control Register (CACR) has write-only access. It is also - * used to enable and disable the FPU. We need to maintain a copy of - * this register to allow per thread values. - */ - extern uint32_t _CPU_cacr_shadow; - #endif - - /* We assume that each ColdFire core with a FPU has also an EMAC unit */ - typedef struct { - uint32_t emac_macsr; - uint32_t emac_acc0; - uint32_t emac_acc1; - uint32_t emac_acc2; - uint32_t emac_acc3; - uint32_t emac_accext01; - uint32_t emac_accext23; - uint32_t emac_mask; - #if ( M68K_HAS_FPU == 1 ) - uint16_t fp_state_format; - uint16_t fp_state_fpcr; - double fp_state_op; - uint32_t fp_state_fpsr; - - /* - * We need to save the FP Instruction Address Register (FPIAR), because - * a context switch can occur within a FP exception before the handler - * was able to save this register. - */ - uint32_t fp_fpiar; - - double fp_data [8]; - #endif - } Context_Control_fp; - - #define _CPU_Context_Fp_start( _base, _offset ) \ - ((void *) _Addresses_Add_offset( (_base), (_offset) )) - - /* - * The reset value for all context relevant registers except the FP data - * registers is zero. The reset value of the FP data register is NAN. The - * restore of the reset FP state will reset the FP data registers, so the - * initial value of them can be arbitrary here. - */ - #define _CPU_Context_Initialize_fp( _fp_area ) \ - memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) - #else - /* - * FP context save area for the M68881/M68882 and 68060 numeric - * coprocessors. - */ - typedef struct { - /* - * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE - * 96 bytes for FMOVEM FP0-7 - * 12 bytes for FMOVEM CREGS - * 4 bytes for non-null flag - */ - uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112]; - } Context_Control_fp; - - #define _CPU_Context_Fp_start( _base, _offset ) \ - ( \ - (void *) _Addresses_Add_offset( \ - (_base), \ - (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ - ) \ - ) - - #define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - uint32_t *_fp_context = (uint32_t *)*(_fp_area); \ - *(--(_fp_context)) = 0; \ - *(_fp_area) = (void *)(_fp_context); \ - } - #endif -#endif - -/* - * The following structures define the set of information saved - * on the current stack by RTEMS upon receipt of each exc/interrupt. - * These are not used by m68k handlers. - * The exception frame is for rdbg. - */ - -typedef struct { - uint32_t vecnum; /* vector number */ -} CPU_Interrupt_frame; - -typedef struct { - uint32_t vecnum; /* vector number */ - uint32_t sr; /* status register */ - uint32_t pc; /* program counter */ - uint32_t d0, d1, d2, d3, d4, d5, d6, d7; - uint32_t a0, a1, a2, a3, a4, a5, a6, a7; -} CPU_Exception_frame; - -/* variables */ - -extern void* _VBR; - -#if ( M68K_HAS_VBR == 0 ) - -/* - * Table of ISR handler entries that resides in RAM. The FORMAT/ID is - * pushed onto the stack. This is not is the same order as VBR processors. - * The ISR handler takes the format and uses it for dispatching the user - * handler. - * - * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS - * - */ - -typedef struct { - uint16_t move_a7; /* move #FORMAT_ID,%a7@- */ - uint16_t format_id; - uint16_t jmp; /* jmp _ISR_Handlers */ - uint32_t isr_handler; -} _CPU_ISR_handler_entry; - -#define M68K_MOVE_A7 0x3F3C -#define M68K_JMP 0x4EF9 - - /* points to jsr-exception-table in targets wo/ VBR register */ -SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; - -#endif /* M68K_HAS_VBR */ - -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ - -/* - * context size area for floating point - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * m68k family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE - -/* - * Maximum priority of a thread. Note based from 0 which is the idle task. - */ -#define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM - -#define CPU_SIZEOF_POINTER 4 - -/* - * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On m68k thread stacks require no further alignment after allocation - * from the Workspace. - */ - -#define CPU_STACK_ALIGNMENT 0 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() - -#define _CPU_ISR_Disable( _level ) \ - m68k_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) \ - m68k_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) \ - m68k_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _newlevel ) \ - m68k_set_interrupt_level( _newlevel ) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* end of Context handler macros */ - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#if ( defined(__mcoldfire__) ) -#define _CPU_Fatal_halt( _source, _error ) \ - { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ - "or.l %2,%%d0\n\t" \ - "move.w %%d0,%%sr\n\t" \ - "move.l %1,%%d0\n\t" \ - "move.l #0xDEADBEEF,%%d1\n\t" \ - "halt" \ - : "=g" (_error) \ - : "0" (_error), "d"(0x0700) \ - : "d0", "d1" ); \ - } -#else -#define _CPU_Fatal_halt( _source, _error ) \ - { __asm__ volatile( "movl %0,%%d0; " \ - "orw #0x0700,%%sr; " \ - "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ - } -#endif - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * It appears that on the M68020 bitfield are always 32 bits wide - * when in a register. This code forces the bitfield to be in - * memory (it really always is anyway). This allows us to - * have a real 16 bit wide bitfield which operates "correctly." - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#if ( M68K_HAS_BFFFO != 1 ) -/* - * Lookup table for BFFFO simulation - */ -extern const unsigned char _CPU_m68k_BFFFO_table[256]; -#endif - -#if ( M68K_HAS_BFFFO == 1 ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); - -#elif ( __mcfisaaplus__ ) - /* This is simplified by the fact that RTEMS never calls it with _value=0 */ -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - __asm__ volatile ( \ - " swap %0\n" \ - " ff1.l %0\n" \ - : "=d" ((_output)) \ - : "0" ((_value)) \ - : "cc" ) ; - -#else -/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in - _CPU_Priority_bits_index is not needed), handles the 0 case, and - does not molest _value -- jsg */ -#if ( defined(__mcoldfire__) ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( \ - " clr.l %1\n" \ - " move.w %2,%1\n" \ - " lsr.l #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1),%0\n" \ - " bra.s 0f\n" \ - "1: move.w %2,%1\n" \ - " move.b (%3,%1),%0\n" \ - " addq.l #8,%0\n" \ - "0: and.l #0xff,%0\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#elif ( M68K_HAS_EXTB_L == 1 ) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " extb.l %0\n" \ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#else -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " and.l #0x000000ff,%0\n"\ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#endif - -#endif - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000 >> (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** - * This method prints the CPU exception frame. - * - * @param[in] frame points to the frame to be printed - */ -void _CPU_Exception_frame_print( - const CPU_Exception_frame *frame -); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#if (M68K_HAS_FPSP_PACKAGE == 1) -/* - * Hooks for the Floating Point Support Package (FPSP) provided by Motorola - * - * NOTES: - * - * Motorola 68k family CPU's before the 68040 used a coprocessor - * (68881 or 68882) to handle floating point. The 68040 has internal - * floating point support -- but *not* the complete support provided by - * the 68881 or 68882. The leftover functions are taken care of by the - * M68040 Floating Point Support Package. Quoting from the MC68040 - * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): - * - * "When used with the M68040FPSP, the MC68040 FPU is fully - * compliant with IEEE floating-point standards." - * - * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and - * is invoked early in the application code to ensure that proper FP - * behavior is installed. This is not left to the BSP to call, since - * this would force all applications using that BSP to use FPSP which - * is not necessarily desirable. - * - * There is a similar package for the 68060 but RTEMS does not yet - * support the 68060. - */ - -void M68KFPSPInstallExceptionHandlers (void); - -SCORE_EXTERN int (*_FPSP_install_raw_handler)( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#endif - - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/score/types.h b/cpukit/score/cpu/m68k/rtems/score/types.h deleted file mode 100644 index 96f9a4c37e..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/types.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Type Definitions - * - * This include file contains type definitions pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h deleted file mode 100644 index 9c84f61990..0000000000 --- a/cpukit/score/cpu/mips/rtems/asm.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/system.h> -#include <rtems/score/cpuopts.h> -#include <rtems/score/mips.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Debugger macros for assembly language routines. Allows the - * programmer to set up the necessary stack frame info - * required by debuggers to do stack traces. - */ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif /* XDS */ - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -#endif -/* end of include file */ - diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h deleted file mode 100644 index ac589d2a68..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ /dev/null @@ -1,1181 +0,0 @@ -/** - * @file - * - * @brief Mips CPU Dependent Header File - */ - -/* - * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and - * Joel Sherrill <joel@OARcorp.com>. - * - * These changes made the code conditional on standard cpp predefines, - * merged the mips1 and mips3 code sequences as much as possible, - * and moved some of the assembly code to C. Alan did much of the - * initial analysis and rework. Joel took over from there and - * wrote the JMR3904 BSP so this could be tested. Joel also - * added the new interrupt vectoring support in libcpu and - * tried to better support the various interrupt controllers. - * - */ - -/* - * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -/** - * @defgroup ScoreCPU CPU CPU - * - * @ingroup Score - * - */ -/**@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/mips.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * MIPS Specific Information: - * - * Up to and including RTEMS 4.10, the MIPS port used simple vectored - * interrupts. But this was changed to the PIC model after 4.10. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - - - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MIPS_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( MIPS_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Mips Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -/* we can use the low power wait instruction for the IDLE thread */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -/* our stack grows down */ -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -/* our cache line size is 16 bytes */ -#if __GNUC__ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) -#else -#define CPU_STRUCTURE_ALIGNMENT -#endif - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */ -#if defined(__MIPSEB__) -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#elif defined(__MIPSEL__) -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#else -#error "Unknown endianness" -#endif - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000ff - -#define CPU_SIZEOF_POINTER 4 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ -#if (__mips == 1) || (__mips == 32) -#define __MIPS_REGISTER_TYPE uint32_t -#define __MIPS_FPU_REGISTER_TYPE uint32_t -#elif __mips == 3 -#define __MIPS_REGISTER_TYPE uint64_t -#define __MIPS_FPU_REGISTER_TYPE uint64_t -#else -#error "mips register size: unknown architecture level!!" -#endif -typedef struct { - __MIPS_REGISTER_TYPE s0; - __MIPS_REGISTER_TYPE s1; - __MIPS_REGISTER_TYPE s2; - __MIPS_REGISTER_TYPE s3; - __MIPS_REGISTER_TYPE s4; - __MIPS_REGISTER_TYPE s5; - __MIPS_REGISTER_TYPE s6; - __MIPS_REGISTER_TYPE s7; - __MIPS_REGISTER_TYPE sp; - __MIPS_REGISTER_TYPE fp; - __MIPS_REGISTER_TYPE ra; - __MIPS_REGISTER_TYPE c0_sr; - __MIPS_REGISTER_TYPE c0_epc; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (uintptr_t) (_context)->sp - -/* WARNING: If this structure is modified, the constants in cpu.h - * must also be updated. - */ - -typedef struct { -#if ( CPU_HARDWARE_FP == TRUE ) - __MIPS_FPU_REGISTER_TYPE fp0; - __MIPS_FPU_REGISTER_TYPE fp1; - __MIPS_FPU_REGISTER_TYPE fp2; - __MIPS_FPU_REGISTER_TYPE fp3; - __MIPS_FPU_REGISTER_TYPE fp4; - __MIPS_FPU_REGISTER_TYPE fp5; - __MIPS_FPU_REGISTER_TYPE fp6; - __MIPS_FPU_REGISTER_TYPE fp7; - __MIPS_FPU_REGISTER_TYPE fp8; - __MIPS_FPU_REGISTER_TYPE fp9; - __MIPS_FPU_REGISTER_TYPE fp10; - __MIPS_FPU_REGISTER_TYPE fp11; - __MIPS_FPU_REGISTER_TYPE fp12; - __MIPS_FPU_REGISTER_TYPE fp13; - __MIPS_FPU_REGISTER_TYPE fp14; - __MIPS_FPU_REGISTER_TYPE fp15; - __MIPS_FPU_REGISTER_TYPE fp16; - __MIPS_FPU_REGISTER_TYPE fp17; - __MIPS_FPU_REGISTER_TYPE fp18; - __MIPS_FPU_REGISTER_TYPE fp19; - __MIPS_FPU_REGISTER_TYPE fp20; - __MIPS_FPU_REGISTER_TYPE fp21; - __MIPS_FPU_REGISTER_TYPE fp22; - __MIPS_FPU_REGISTER_TYPE fp23; - __MIPS_FPU_REGISTER_TYPE fp24; - __MIPS_FPU_REGISTER_TYPE fp25; - __MIPS_FPU_REGISTER_TYPE fp26; - __MIPS_FPU_REGISTER_TYPE fp27; - __MIPS_FPU_REGISTER_TYPE fp28; - __MIPS_FPU_REGISTER_TYPE fp29; - __MIPS_FPU_REGISTER_TYPE fp30; - __MIPS_FPU_REGISTER_TYPE fp31; - uint32_t fpcs; -#endif -} Context_Control_fp; - -/* - * This struct reflects the stack frame employed in ISR_Handler. Note - * that the ISR routine save some of the registers to this frame for - * all interrupts and exceptions. Other registers are saved only on - * exceptions, while others are not touched at all. The untouched - * registers are not normally disturbed by high-level language - * programs so they can be accessed when required. - * - * The registers and their ordering in this struct must directly - * correspond to the layout and ordering of * shown in iregdef.h, - * as cpu_asm.S uses those definitions to fill the stack frame. - * This struct provides access to the stack frame for C code. - * - * Similarly, this structure is used by debugger stubs and exception - * processing routines so be careful when changing the format. - * - * NOTE: The comments with this structure and cpu_asm.S should be kept - * in sync. When in doubt, look in the code to see if the - * registers you're interested in are actually treated as expected. - * The order of the first portion of this structure follows the - * order of registers expected by gdb. - */ - -typedef struct -{ - __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ - __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ - __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ - __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ - __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ - __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ - __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ - __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ - __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ - __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ - __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ - __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ - __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ - __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ - __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ - __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ - __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ - __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ - __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ - __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ - __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ - __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ - __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ - /* manipulated per-thread */ - __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ - __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ - __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ - __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ - __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ - /* but logically restored */ - __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ - __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - - /* GDB does not seem to care about anything past this point */ - - __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#if __mips == 1 - __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif -#if (__mips == 3) || (__mips == 32) - __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif - - __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ - __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ - /* end of __mips == 1 so NREGS == 81 */ -#if (__mips == 3) || (__mips == 32) - __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ - /* end of __mips == 3 so NREGS == 96 */ -#endif - -} CPU_Interrupt_frame; - -typedef CPU_Interrupt_frame CPU_Exception_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (8 * 1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -void mips_vector_exceptions( CPU_Interrupt_frame *frame ); - -/* - * ISR handler macros - */ - -/* - * Declare the function that is present in the shared libcpu directory, - * that returns the processor dependent interrupt mask. - */ - -uint32_t mips_interrupt_mask( void ); - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ - _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ - } while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ - } while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _xlevel ) \ - do { \ - unsigned int _scratch2 = _xlevel; \ - _CPU_ISR_Enable( _scratch2 ); \ - _CPU_ISR_Disable( _scratch2 ); \ - _xlevel = _scratch2; \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * On the MIPS, 0 is all on. Non-zero is all off. This only - * manipulates the IEC. - */ - -uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ - -void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * The per-thread status register holds the interrupt enable, FP enable - * and global interrupt enable for that thread. It means each thread can - * enable its own set of interrupts. If interrupts are disabled, RTEMS - * can still dispatch via blocking calls. This is the function of the - * "Interrupt Level", and on the MIPS, it controls the IEC bit and all - * the hardware interrupts as defined in the SR. Software ints - * are automatically enabled for all threads, as they will only occur under - * program control anyhow. Besides, the interrupt level parm is only 8 bits, - * and controlling the software ints plus the others would require 9. - * - * If the Interrupt Level is 0, all ints are on. Otherwise, the - * Interrupt Level should supply a bit pattern to impose on the SR - * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 - * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of - * the Interrupt Level parameter is unused at this time. - * - * These are the only per-thread SR bits, the others are maintained - * globally & explicitly preserved by the Context Switch code in cpu_asm.s - */ - - -#if (__mips == 3) || (__mips == 32) -#define _INTON SR_IE -#if __mips_fpr==64 -#define _EXTRABITS SR_FR -#else -#define _EXTRABITS 0 -#endif /* __mips_fpr==64 */ -#endif /* __mips == 3 */ -#if __mips == 1 -#define _INTON SR_IEC -#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ -#endif /* __mips == 1 */ - - -void _CPU_Context_Initialize( - Context_Control *the_context, - uintptr_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * A floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - unsigned int _level; \ - _CPU_ISR_Disable(_level); \ - (void)_level; \ - loop: goto loop; \ - } while (0) - - -extern void mips_break( int error ); - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif - - - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/mips/rtems/score/types.h b/cpukit/score/cpu/mips/rtems/score/types.h deleted file mode 100644 index 01950cecef..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file rtems/score/types.h - * - * @brief Type Definitions Pertaining to the MIPS Processor Family - * - * This include file contains type definitions pertaining to the MIPS - * processor family. - */ - -/* - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -/* @(#)mipstypes.h 08/20/96 1.4 */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -/** - * @defgroup ScoreTypes MIPS Processor Family Type Definitions - * - * @ingroup Score - * - */ -/**@{*/ - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void mips_isr; -typedef void ( *mips_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/moxie/rtems/asm.h b/cpukit/score/cpu/moxie/rtems/asm.h deleted file mode 100644 index fdb182f32f..0000000000 --- a/cpukit/score/cpu/moxie/rtems/asm.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2011 - * Anthony Green - * - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * $Id: asm.h,v 1.9 2010/06/29 00:31:09 joel Exp $ - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#include <rtems/score/moxie.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ "$" -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define fp REG(fp) -#define sp REG(sp) -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE asm ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/cpu.h b/cpukit/score/cpu/moxie/rtems/score/cpu.h deleted file mode 100644 index 297316bfeb..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/cpu.h +++ /dev/null @@ -1,1058 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the Moxie - * processor. - * - * Copyright (c) 2013 Anthony Green - * - * Based on code with the following copyright.. - * COPYRIGHT (c) 1989-2006, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/moxie.h> /* pick up machine definitions */ - -#include <rtems/bspIo.h> /* printk */ - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should this target use 16 or 32 bit object Ids? - * - */ -#define RTEMS_USE_32_BIT_OBJECT - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * MOXIE Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MOXIE_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * MOXIE Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE -#define CPU_TIMESTAMP_USE_INT64 FALSE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * MOXIE Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * MOXIE Specific Information: - * - * XXX - */ - -#define nogap __attribute__ ((packed)) - -typedef struct { - void *fp nogap; - void *sp nogap; - uint32_t r0 nogap; - uint32_t r1 nogap; - uint32_t r2 nogap; - uint32_t r3 nogap; - uint32_t r4 nogap; - uint32_t r5 nogap; - uint32_t r6 nogap; - uint32_t r7 nogap; - uint32_t r8 nogap; - uint32_t r9 nogap; - uint32_t r10 nogap; - uint32_t r11 nogap; - uint32_t r12 nogap; - uint32_t r13 nogap; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * MOXIE Specific Information: - * - * XXX - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * MOXIE Specific Information: - * - * XXX - */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * MOXIE Specific Information: - * - * It is highly unlikely the MOXIE will get used in a multiprocessor system. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \ - (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_MINIMUM_SIZE (1536) - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if (_new_level) asm volatile ( "nop\n" ); \ - else asm volatile ( "nop\n" ); \ - } - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method does not ensure that the context - * is set up with interrupts disabled/enabled as requested. - */ -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - /* Locate Me */ \ - do { \ - uintptr_t _stack; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - (void) _isr; /* avoid warning for being unused */ \ - _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - _stack -= 4; \ - (_the_context)->fp = (void *)_stack; \ - (_the_context)->sp = (void *)_stack; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Fatal_halt( _source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source,_error); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * MOXIE Specific Information: - * - * XXX - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * MOXIE Specific Information: - * - * XXX - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -void *_CPU_Thread_Idle_body( uint32_t ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** - * @brief The set of registers that specifies the complete processor state. - * - * The CPU exception frame may be available in fatal error conditions like for - * example illegal opcodes, instruction fetch errors, or data access errors. - * - * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and - * rtems_exception_frame_print(). - */ -typedef struct { - uint32_t integer_registers [16]; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * MOXIE Specific Information: - * - * This is the generic implementation. - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/types.h b/cpukit/score/cpu/moxie/rtems/score/types.h deleted file mode 100644 index 64427a831a..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file rtems/score/types.h - */ - -/* - * This file contains information pertaining to the Moxie processor. - * - * COPYRIGHT (c) 2011 - * Anthony Green - * - * Based on code with the following copyright... - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#include <stdbool.h> -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void moxie_isr; -typedef void ( *moxie_isr_entry )( void ); - -#ifdef RTEMS_DEPRECATED_TYPES -typedef bool boolean; /* Boolean value */ -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/asm.h b/cpukit/score/cpu/nios2/rtems/asm.h deleted file mode 100644 index 45ccd8b050..0000000000 --- a/cpukit/score/cpu/nios2/rtems/asm.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/nios2.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h deleted file mode 100644 index fdb9d8aaef..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ /dev/null @@ -1,381 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II CPU Department Source - */ - -/* - * Copyright (c) 2011 embedded brains GmbH - * - * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) - * - * COPYRIGHT (c) 1989-2004. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/nios2.h> - -/* - * TODO: Run the timing tests and figure out what is better. - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_CONTEXT_FP_SIZE 0 - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -#define CPU_STACK_GROWS_UP FALSE - -#define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -#define CPU_BIG_ENDIAN FALSE - -#define CPU_LITTLE_ENDIAN TRUE - -#define CPU_STACK_MINIMUM_SIZE (4 * 1024) - -#define CPU_SIZEOF_POINTER 4 - -/* - * Alignment value according to "Nios II Processor Reference" chapter 7 - * "Application Binary Interface" section "Memory Alignment". - */ -#define CPU_ALIGNMENT 4 - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * Alignment value according to "Nios II Processor Reference" chapter 7 - * "Application Binary Interface" section "Stacks". - */ -#define CPU_STACK_ALIGNMENT 4 - -/* - * A Nios II configuration with an external interrupt controller (EIC) supports - * up to 64 interrupt levels. A Nios II configuration with an internal - * interrupt controller (IIC) has only two interrupt levels (enabled and - * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will - * take care about configuration specific mappings. - */ -#define CPU_MODES_INTERRUPT_MASK 0x3f - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @brief Thread register context. - * - * The thread register context covers the non-volatile registers, the thread - * stack pointer, the return address, and the processor status. - * - * There is no need to save the global pointer (gp) since it is a system wide - * constant and set-up with the C runtime environment. - * - * The @a thread_dispatch_disabled field is used for the external interrupt - * controller (EIC) support. - * - * @see _Nios2_Thread_dispatch_disabled - */ -typedef struct { - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t fp; - uint32_t status; - uint32_t sp; - uint32_t ra; - uint32_t thread_dispatch_disabled; - uint32_t stack_mpubase; - uint32_t stack_mpuacc; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef void CPU_Interrupt_frame; - -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t et; - uint32_t ea; - uint32_t status; - uint32_t ienable; - uint32_t ipending; -} CPU_Exception_frame; - -#define _CPU_Initialize_vectors() - -/** - * @brief Macro to disable interrupts. - * - * The processor status before disabling the interrupts will be stored in - * @a _isr_cookie. This value will be used in _CPU_ISR_Flash() and - * _CPU_ISR_Enable(). - * - * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in - * the status register representing the interrupt level. The global symbol - * _Nios2_ISR_Status_bits will be used to set the bits representing an - * interrupt level that disables interrupts. Both global symbols must be - * provided by the board support package. - * - * In case the Nios II uses the internal interrupt controller (IIC), then only - * the PIE status bit is used. - * - * In case the Nios II uses the external interrupt controller (EIC), then the - * RSIE status bit or the IL status field is used depending on the interrupt - * handling variant and the shadow register usage. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - int _tmp; \ - __asm__ volatile ( \ - "rdctl %0, status\n" \ - "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ - "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ - "and %1, %0, %1\n" \ - "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ - "wrctl status, %1" \ - : "=&r" (_isr_cookie), "=&r" (_tmp) \ - ); \ - } while ( 0 ) - -/** - * @brief Macro to restore the processor status. - * - * The @a _isr_cookie must contain the processor status returned by - * _CPU_ISR_Disable(). The value is not modified. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - __builtin_wrctl( 0, (int) _isr_cookie ) - -/** - * @brief Macro to restore the processor status and disable the interrupts - * again. - * - * The @a _isr_cookie must contain the processor status returned by - * _CPU_ISR_Disable(). The value is not modified. - * - * This flash code is optimal for all Nios II configurations. The rdctl does - * not flush the pipeline and has only a late result penalty. The wrctl on - * the other hand leads to a pipeline flush. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - int _status = __builtin_rdctl( 0 ); \ - __builtin_wrctl( 0, (int) _isr_cookie ); \ - __builtin_wrctl( 0, _status ); \ - } while ( 0 ) - -/** - * @brief Sets the interrupt level for the executing thread. - * - * The valid values of @a new_level depend on the Nios II configuration. A - * value of zero represents enabled interrupts in all configurations. - * - * @see _CPU_ISR_Get_level() - */ -void _CPU_ISR_Set_level( uint32_t new_level ); - -/** - * @brief Returns the interrupt level of the executing thread. - * - * @retval 0 Interrupts are enabled. - * @retval otherwise The value depends on the Nios II configuration. In case - * of an internal interrupt controller (IIC) the only valid value is one which - * indicates disabled interrupts. In case of an external interrupt controller - * (EIC) there are two possibilities. Firstly if the RSIE status bit is used - * to disable interrupts, then one is the only valid value indicating disabled - * interrupts. Secondly if the IL status field is used to disable interrupts, - * then this value will be returned. Interrupts are disabled at the maximum - * level specified by the _Nios2_ISR_Status_bits. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -void _CPU_Fatal_halt( uint32_t _source, uint32_t _error ) - RTEMS_NO_RETURN; - -/** - * @brief CPU initialization. - */ -void _CPU_Initialize( void ); - -/** - * @brief CPU ISR install raw handler. - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief CPU ISR install vector. - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -static inline uint32_t CPU_swap_u32( uint32_t value ) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - - return swapped; -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h deleted file mode 100644 index 81a19c8d69..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h deleted file mode 100644 index 6eaee5c829..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Altera Nios II processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void nios2_isr; -typedef void ( *nios2_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/asm.h b/cpukit/score/cpu/or1k/rtems/asm.h deleted file mode 100644 index 4d2c22698b..0000000000 --- a/cpukit/score/cpu/or1k/rtems/asm.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - */ - -#ifndef __OR1K_ASM_h -#define __OR1K_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/or1k.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h b/cpukit/score/cpu/or1k/rtems/score/cpu.h deleted file mode 100644 index 7d07de34b0..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpu.h +++ /dev/null @@ -1,1035 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains macros pertaining to the Opencores - * or1k processor family. - * - * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file adapted from no_cpu example of the RTEMS distribution. - * The body has been modified for the Opencores OR1k implementation by - * Chris Ziomkowski. <chris@asics.ws> - * - */ - -#ifndef _OR1K_CPU_H -#define _OR1K_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#include <rtems/score/or1k.h> /* pick up machine definitions */ -#include <rtems/score/or1k-utility.h> -#include <rtems/score/types.h> -#ifndef ASM -#include <rtems/bspIo.h> -#include <stdint.h> -#include <stdio.h> /* for printk */ -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Currently, for or1k port, _ISR_Handler is responsible for switching to - * RTEMS dedicated interrupt task. - * - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "OR1K_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Or1k Specific Information: - * - * At this time there are no implementations of Or1k that are - * expected to implement floating point. More importantly, the - * floating point architecture is expected to change significantly - * before such chips are fabricated. - */ - -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * Or1k Specific Information: - * - * This version of RTEMS is designed specifically to run with - * big endian architectures. If you want little endian, you'll - * have to make the appropriate adjustments here and write - * efficient routines for byte swapping. The Or1k architecture - * doesn't do this very well. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - */ - - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * - */ -#ifndef ASM -#ifdef OR1K_64BIT_ARCH -#define or1kreg uint64_t -#else -#define or1kreg uint32_t -#endif - -typedef struct { - uint32_t r1; /* Stack pointer */ - uint32_t r2; /* Frame pointer */ - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t r28; - uint32_t r29; - uint32_t r30; - uint32_t r31; - - uint32_t sr; /* Current supervision register non persistent values */ - uint32_t epcr; - uint32_t eear; - uint32_t esr; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r1 - -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Or1k Specific Information: - * - */ - -#define CPU_CONTEXT_FP_SIZE 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - */ - -#define CPU_ALIGNMENT 8 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline uint32_t or1k_interrupt_disable( void ) -{ - uint32_t sr; - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - - _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); - - return sr; -} - -static inline void or1k_interrupt_enable(uint32_t level) -{ - uint32_t sr; - - /* Enable interrupts and restore rs */ - sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; - _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); - -} - -#define _CPU_ISR_Disable( _level ) \ - _level = or1k_interrupt_disable() - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - */ - -#define _CPU_ISR_Enable( _level ) \ - or1k_interrupt_enable( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - */ - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - _CPU_ISR_Enable( _level ); \ - _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - */ - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - */ - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - */ - -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - _OR1KSIM_CPU_Halt(); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - */ - - /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - - /* Get a value between 0 and N where N is the bit size */ - /* This routine makes use of the fact that CPUCFGR defines - OB32S to have value 32, and OB64S to have value 64. If - this ever changes then this routine will fail. */ -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - asm volatile ("l.mfspr %0,r0,0x2 \n\t"\ - "l.andi %0,%0,0x60 \n\t"\ - "l.ff1 %1,%1,r0 \n\t"\ - "l.sub %0,%0,%1 \n\t" : "=&r" (_output), "+r" (_value)); - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - (1 << _bit_number) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { -/* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; -#endif /* ASM */ - -#define CPU_SIZEOF_POINTER 4 -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM -typedef uint32_t CPU_Counter_ticks; -typedef uint16_t Priority_bit_map_Word; - -typedef struct { - uint32_t r[32]; - - /* The following registers must be saved if we have - fast context switch disabled and nested interrupt - levels are enabled. - */ -#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED - uint32_t epcr; /* exception PC register */ - uint32_t eear; /* exception effective address register */ - uint32_t esr; /* exception supervision register */ -#endif - -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * Or1k Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h deleted file mode 100644 index a5659f35ce..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief OR1K Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/or1k/rtems/score/types.h b/cpukit/score/cpu/or1k/rtems/score/types.h deleted file mode 100644 index b3beb8371f..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/types.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * @file - * - * @brief OR1K Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - - #ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void or1k_isr; -typedef void ( *or1k_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h deleted file mode 100644 index 192a00687d..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/asm.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1995. - * i-cubed ltd. - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/powerpc.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#ifndef __FLOAT_REGISTER_PREFIX__ -#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ -#endif - -#ifndef __PROC_LABEL_PREFIX__ -#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for procedure labels. */ - -#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* Use the right prefix for floating point registers. */ - -#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(0) -#define r1 REG(1) -#define r2 REG(2) -#define r3 REG(3) -#define r4 REG(4) -#define r5 REG(5) -#define r6 REG(6) -#define r7 REG(7) -#define r8 REG(8) -#define r9 REG(9) -#define r10 REG(10) -#define r11 REG(11) -#define r12 REG(12) -#define r13 REG(13) -#define r14 REG(14) -#define r15 REG(15) -#define r16 REG(16) -#define r17 REG(17) -#define r18 REG(18) -#define r19 REG(19) -#define r20 REG(20) -#define r21 REG(21) -#define r22 REG(22) -#define r23 REG(23) -#define r24 REG(24) -#define r25 REG(25) -#define r26 REG(26) -#define r27 REG(27) -#define r28 REG(28) -#define r29 REG(29) -#define r30 REG(30) -#define r31 REG(31) -#define f0 FREG(0) -#define f1 FREG(1) -#define f2 FREG(2) -#define f3 FREG(3) -#define f4 FREG(4) -#define f5 FREG(5) -#define f6 FREG(6) -#define f7 FREG(7) -#define f8 FREG(8) -#define f9 FREG(9) -#define f10 FREG(10) -#define f11 FREG(11) -#define f12 FREG(12) -#define f13 FREG(13) -#define f14 FREG(14) -#define f15 FREG(15) -#define f16 FREG(16) -#define f17 FREG(17) -#define f18 FREG(18) -#define f19 FREG(19) -#define f20 FREG(20) -#define f21 FREG(21) -#define f22 FREG(22) -#define f23 FREG(23) -#define f24 FREG(24) -#define f25 FREG(25) -#define f26 FREG(26) -#define f27 FREG(27) -#define f28 FREG(28) -#define f29 FREG(29) -#define f30 FREG(30) -#define f31 FREG(31) -#define v0 0 -#define v1 1 -#define v2 2 -#define v3 3 -#define v4 4 -#define v5 5 -#define v6 6 -#define v7 7 -#define v8 8 -#define v9 9 -#define v10 10 -#define v11 11 -#define v12 12 -#define v13 13 -#define v14 14 -#define v15 15 -#define v16 16 -#define v17 17 -#define v18 18 -#define v19 19 -#define v20 20 -#define v21 21 -#define v22 22 -#define v23 23 -#define v24 24 -#define v25 25 -#define v26 26 -#define v27 27 -#define v28 28 -#define v29 29 -#define v30 30 -#define v31 31 - -/* - * Some special purpose registers (SPRs). - */ -#define srr0 0x01a -#define srr1 0x01b -#define srr2 0x3de /* IBM 400 series only */ -#define srr3 0x3df /* IBM 400 series only */ -#define csrr0 58 /* Book E */ -#define csrr1 59 /* Book E */ -#define mcsrr0 570 /* e500 */ -#define mcsrr1 571 /* e500 */ -#define dsrr0 574 /* e200 */ -#define dsrr1 575 /* e200 */ - -#define sprg0 0x110 -#define sprg1 0x111 -#define sprg2 0x112 -#define sprg3 0x113 -#define sprg4 276 -#define sprg5 277 -#define sprg6 278 -#define sprg7 279 - -#define usprg0 256 - -#define dar 0x013 /* Data Address Register */ -#define dec 0x016 /* Decrementer Register */ - -#if defined(ppc403) || defined(ppc405) -/* the following SPR/DCR registers exist only in IBM 400 series */ -#define dear 0x3d5 -#define evpr 0x3d6 /* SPR: exception vector prefix register */ -#define iccr 0x3fb /* SPR: instruction cache control reg. */ -#define dccr 0x3fa /* SPR: data cache control reg. */ - -#if defined (ppc403) -#define exisr 0x040 /* DCR: external interrupt status register */ -#define exier 0x042 /* DCR: external interrupt enable register */ -#endif /* ppc403 */ -#if defined(ppc405) -#define exisr 0x0C0 /* DCR: external interrupt status register */ -#define exier 0x0C2 /* DCR: external interrupt enable register */ -#endif /* ppc405 */ - -#define br0 0x080 /* DCR: memory bank register 0 */ -#define br1 0x081 /* DCR: memory bank register 1 */ -#define br2 0x082 /* DCR: memory bank register 2 */ -#define br3 0x083 /* DCR: memory bank register 3 */ -#define br4 0x084 /* DCR: memory bank register 4 */ -#define br5 0x085 /* DCR: memory bank register 5 */ -#define br6 0x086 /* DCR: memory bank register 6 */ -#define br7 0x087 /* DCR: memory bank register 7 */ - -/* end of IBM400 series register definitions */ - -#elif defined(mpc555) -/* The following registers are for the MPC5xx */ -#define eie 0x050 /* External Interrupt Enable Register */ -#define eid 0x051 /* External Interrupt Disable Register */ -#define nri 0x052 /* Non-Recoverable Interrupt Register */ - -#elif defined(mpc860) || defined(mpc821) -/* The following registers are for the MPC8x0 */ -#define der 0x095 /* Debug Enable Register */ -#define ictrl 0x09E /* Instruction Support Control Register */ -#define immr 0x27E /* Internal Memory Map Register */ -/* end of MPC8x0 registers */ -#endif - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC_VAR(sym) .globl SYM (sym) -#define EXTERN_VAR(sym) .extern SYM (sym) -#define PUBLIC_PROC(sym) .globl PROC (sym) -#define EXTERN_PROC(sym) .extern PROC (sym) - -/* Other potentially assembler specific operations */ -#if PPC_ASM == PPC_ASM_ELF -#define ALIGN(n,p) .align p -#define DESCRIPTOR(x) \ - .section .descriptors,"aw"; \ - PUBLIC_VAR (x); \ -SYM (x):; \ - .long PROC (x); \ - .long s.got; \ - .long 0 - -#define EXT_SYM_REF(x) .long x -#define EXT_PROC_REF(x) .long x - -/* - * Define macros to handle section beginning and ends. - */ - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -#else -#error "PPC_ASM_TYPE is not properly defined" -#endif -#ifndef PPC_ASM -#error "PPC_ASM_TYPE is not properly defined" -#endif - - -#endif diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h deleted file mode 100644 index c30b9dc967..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ /dev/null @@ -1,1311 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Department Source - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * COPYRIGHT (c) 1995 i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. - * - * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). - * - * Copyright (c) 2010-2013 embedded brains GmbH. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include <rtems/score/types.h> -#include <rtems/score/powerpc.h> -#include <rtems/powerpc/registers.h> - -#ifndef ASM - #include <string.h> /* for memset() */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT \ - __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#else -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#endif - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * PowerPC Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef __SPE__ - #define PPC_GPR_TYPE uint32_t - #define PPC_GPR_SIZE 4 - #define PPC_GPR_LOAD lwz - #define PPC_GPR_STORE stw -#else - #define PPC_GPR_TYPE uint64_t - #define PPC_GPR_SIZE 8 - #define PPC_GPR_LOAD evldd - #define PPC_GPR_STORE evstdd -#endif - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according - * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - - * Linux and Embedded") - */ -typedef struct { - uint32_t gpr1; - uint32_t msr; - uint32_t lr; - uint32_t cr; - PPC_GPR_TYPE gpr14; - PPC_GPR_TYPE gpr15; - PPC_GPR_TYPE gpr16; - PPC_GPR_TYPE gpr17; - PPC_GPR_TYPE gpr18; - PPC_GPR_TYPE gpr19; - PPC_GPR_TYPE gpr20; - PPC_GPR_TYPE gpr21; - PPC_GPR_TYPE gpr22; - PPC_GPR_TYPE gpr23; - PPC_GPR_TYPE gpr24; - PPC_GPR_TYPE gpr25; - PPC_GPR_TYPE gpr26; - PPC_GPR_TYPE gpr27; - PPC_GPR_TYPE gpr28; - PPC_GPR_TYPE gpr29; - PPC_GPR_TYPE gpr30; - PPC_GPR_TYPE gpr31; - uint32_t gpr2; - #if defined(PPC_MULTILIB_ALTIVEC) - uint32_t reserved_for_alignment; - uint8_t v20[16]; - uint8_t v21[16]; - uint8_t v22[16]; - uint8_t v23[16]; - uint8_t v24[16]; - uint8_t v25[16]; - uint8_t v26[16]; - uint8_t v27[16]; - uint8_t v28[16]; - uint8_t v29[16]; - uint8_t v30[16]; - uint8_t v31[16]; - uint32_t vrsave; - #elif defined(__ALTIVEC__) - /* - * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave - * and padding to ensure cache-alignment. Unfortunately, we can't verify - * the cache line size here in the cpukit but altivec support code will - * produce an error if this is ever different from 32 bytes. - * - * Note: it is the BSP/CPU-support's responsibility to save/restore - * volatile vregs across interrupts and exceptions. - */ - uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; - #endif - #if defined(PPC_MULTILIB_FPU) - double f14; - double f15; - double f16; - double f17; - double f18; - double f19; - double f20; - double f21; - double f22; - double f23; - double f24; - double f25; - double f26; - double f27; - double f28; - double f29; - double f30; - double f31; - #endif - #if defined(RTEMS_SMP) - /* - * This item is at the structure end, so that we can use dcbz for the - * previous items to optimize the context switch. We must not set this - * item to zero via the dcbz. - */ - volatile uint32_t is_executing; - #endif -} ppc_context; - -typedef struct { - uint8_t context [ - PPC_DEFAULT_CACHE_LINE_SIZE - + sizeof(ppc_context) - + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 - ? 0 - : PPC_DEFAULT_CACHE_LINE_SIZE - - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) - ]; -} Context_Control; - -static inline ppc_context *ppc_get_context( const Context_Control *context ) -{ - uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; - uintptr_t mask = clsz - 1; - uintptr_t addr = (uintptr_t) context; - - return (ppc_context *) ((addr & ~mask) + clsz); -} - -#define _CPU_Context_Get_SP( _context ) \ - ppc_get_context(_context)->gpr1 - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return ppc_get_context(context)->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - ppc_get_context(context)->is_executing = is_executing; - } -#endif -#endif /* ASM */ - -#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0) -#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) -#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8) -#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12) - -#define PPC_CONTEXT_GPR_OFFSET( gpr ) \ - (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16) - -#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) -#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) -#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) -#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) -#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) -#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) -#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) -#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) -#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) -#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) -#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) -#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) -#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) -#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) -#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) -#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) -#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) -#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) -#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 ) - -#ifdef PPC_MULTILIB_ALTIVEC - #define PPC_CONTEXT_OFFSET_V( v ) \ - ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) - #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) - #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) - #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) - #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) - #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) - #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) - #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) - #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) - #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) - #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) - #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) - #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) - #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 ) -#else - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) -#endif - -#ifdef PPC_MULTILIB_FPU - #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) - #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) - #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) - #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) - #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) - #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) - #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) - #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) - #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) - #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) - #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) - #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) - #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) - #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) - #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) - #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) - #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) - #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) -#endif - -#if defined(PPC_MULTILIB_FPU) - #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) -#elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) -#else - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4) -#endif - -#ifdef RTEMS_SMP - #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE -#endif - -#ifndef ASM -typedef struct { -#if (PPC_HAS_FPU == 1) - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - uint64_t fpscr; -#else - float f[32]; - uint32_t fpscr; -#endif -#endif /* (PPC_HAS_FPU == 1) */ -} Context_Control_fp; - -typedef struct CPU_Interrupt_frame { - uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ - uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ - - /* This is what is left out of the primary contexts */ - uint32_t gpr0; - uint32_t gpr2; /* play safe */ - uint32_t gpr3; - uint32_t gpr4; - uint32_t gpr5; - uint32_t gpr6; - uint32_t gpr7; - uint32_t gpr8; - uint32_t gpr9; - uint32_t gpr10; - uint32_t gpr11; - uint32_t gpr12; - uint32_t gpr13; /* Play safe */ - uint32_t gpr28; /* For internal use by the IRQ handler */ - uint32_t gpr29; /* For internal use by the IRQ handler */ - uint32_t gpr30; /* For internal use by the IRQ handler */ - uint32_t gpr31; /* For internal use by the IRQ handler */ - uint32_t cr; /* Bits of this are volatile, so no-one may save */ - uint32_t ctr; - uint32_t xer; - uint32_t lr; - uint32_t pc; - uint32_t msr; - uint32_t pad[3]; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Note, however that compilers may use floating point registers/ - * instructions for optimization or they may save/restore FP registers - * on the stack. You must not use deferred switching in these cases - * and on the PowerPC attempting to do so will raise a "FP unavailable" - * exception. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -/* conservative setting (FALSE); probably doesn't affect performance too much */ -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Processor defined structures required for cpukit/score. - */ - -#ifndef ASM - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -#endif /* ndef ASM */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (128) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. Note that - * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level - * being maintained (e.g. watchdog queues). - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * ISR handler macros - */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#ifndef ASM - -static inline uint32_t _CPU_ISR_Get_level( void ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (msr & MSR_EE) return 0; - else return 1; -} - -static inline void _CPU_ISR_Set_level( uint32_t level ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (!(level & CPU_MODES_INTERRUPT_MASK)) { - msr |= ppc_interrupt_get_disable_mask(); - } - else { - msr &= ~ppc_interrupt_get_disable_mask(); - } - _CPU_MSR_SET(msr); -} - -void BSP_panic(char *); - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -void _BSP_Fatal_error(unsigned int); - -#endif /* ASM */ - -#define _CPU_Fatal_halt( _source, _error ) \ - _BSP_Fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -#ifndef ASM -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t swapped; - - __asm__ volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=&r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - CPU_Counter_ticks value; - -#if defined(__PPC_CPU_E6500__) - /* Use Alternate Time Base */ - __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); -#else - __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); -#endif - - return value; -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - - -#ifndef ASM -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *(_destination), 0, sizeof( **(_destination) ) ) - -/* end of Context handler macros */ -#endif /* ASM */ - -#ifndef ASM -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x80000000 >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ -#endif /* ASM */ - -/* functions */ - -#ifndef ASM - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t pir; - - /* Use Book E Processor ID Register (PIR) */ - __asm__ volatile ( - "mfspr %[pir], 286" - : [pir] "=&r" (pir) - ); - - return pir; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -typedef struct { - uint32_t EXC_SRR0; - uint32_t EXC_SRR1; - uint32_t _EXC_number; - uint32_t EXC_CR; - uint32_t EXC_CTR; - uint32_t EXC_XER; - uint32_t EXC_LR; - #ifdef __SPE__ - uint32_t EXC_SPEFSCR; - uint64_t EXC_ACC; - #endif - PPC_GPR_TYPE GPR0; - PPC_GPR_TYPE GPR1; - PPC_GPR_TYPE GPR2; - PPC_GPR_TYPE GPR3; - PPC_GPR_TYPE GPR4; - PPC_GPR_TYPE GPR5; - PPC_GPR_TYPE GPR6; - PPC_GPR_TYPE GPR7; - PPC_GPR_TYPE GPR8; - PPC_GPR_TYPE GPR9; - PPC_GPR_TYPE GPR10; - PPC_GPR_TYPE GPR11; - PPC_GPR_TYPE GPR12; - PPC_GPR_TYPE GPR13; - PPC_GPR_TYPE GPR14; - PPC_GPR_TYPE GPR15; - PPC_GPR_TYPE GPR16; - PPC_GPR_TYPE GPR17; - PPC_GPR_TYPE GPR18; - PPC_GPR_TYPE GPR19; - PPC_GPR_TYPE GPR20; - PPC_GPR_TYPE GPR21; - PPC_GPR_TYPE GPR22; - PPC_GPR_TYPE GPR23; - PPC_GPR_TYPE GPR24; - PPC_GPR_TYPE GPR25; - PPC_GPR_TYPE GPR26; - PPC_GPR_TYPE GPR27; - PPC_GPR_TYPE GPR28; - PPC_GPR_TYPE GPR29; - PPC_GPR_TYPE GPR30; - PPC_GPR_TYPE GPR31; - #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU) - uint32_t reserved_for_alignment; - #endif - #ifdef PPC_MULTILIB_ALTIVEC - uint32_t VRSAVE; - - /* This field must take stvewx/lvewx requirements into account */ - uint32_t VSCR; - - uint8_t V0[16]; - uint8_t V1[16]; - uint8_t V2[16]; - uint8_t V3[16]; - uint8_t V4[16]; - uint8_t V5[16]; - uint8_t V6[16]; - uint8_t V7[16]; - uint8_t V8[16]; - uint8_t V9[16]; - uint8_t V10[16]; - uint8_t V11[16]; - uint8_t V12[16]; - uint8_t V13[16]; - uint8_t V14[16]; - uint8_t V15[16]; - uint8_t V16[16]; - uint8_t V17[16]; - uint8_t V18[16]; - uint8_t V19[16]; - uint8_t V20[16]; - uint8_t V21[16]; - uint8_t V22[16]; - uint8_t V23[16]; - uint8_t V24[16]; - uint8_t V25[16]; - uint8_t V26[16]; - uint8_t V27[16]; - uint8_t V28[16]; - uint8_t V29[16]; - uint8_t V30[16]; - uint8_t V31[16]; - #endif - #ifdef PPC_MULTILIB_FPU - double F0; - double F1; - double F2; - double F3; - double F4; - double F5; - double F6; - double F7; - double F8; - double F9; - double F10; - double F11; - double F12; - double F13; - double F14; - double F15; - double F16; - double F17; - double F18; - double F19; - double F20; - double F21; - double F22; - double F23; - double F24; - double F25; - double F26; - double F27; - double F28; - double F29; - double F30; - double F31; - uint64_t FPSCR; - #endif -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * _CPU_Initialize_altivec() - * - * Global altivec-related initialization. - */ -void -_CPU_Initialize_altivec(void); - -/* - * _CPU_Context_switch_altivec - * - * This routine switches the altivec contexts passed to it. - */ - -void -_CPU_Context_switch_altivec( - ppc_context *from, - ppc_context *to -); - -/* - * _CPU_Context_restore_altivec - * - * This routine restores the altivec context passed to it. - */ - -void -_CPU_Context_restore_altivec( - ppc_context *ctxt -); - -/* - * _CPU_Context_initialize_altivec - * - * This routine initializes the altivec context passed to it. - */ - -void -_CPU_Context_initialize_altivec( - ppc_context *ctxt -); - -void _CPU_Fatal_error( - uint32_t _error -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/types.h b/cpukit/score/cpu/powerpc/rtems/score/types.h deleted file mode 100644 index f36038fe09..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/types.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Type Definitions - * - * This include file contains type definitions pertaining to the PowerPC - * processor family. - */ - -/* - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint32_t Priority_bit_map_Word; -typedef void ppc_isr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sh/rtems/asm.h b/cpukit/score/cpu/sh/rtems/asm.h deleted file mode 100644 index ac730310cd..0000000000 --- a/cpukit/score/cpu/sh/rtems/asm.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/sh.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG (r0) -#define r1 REG (r1) -#define r2 REG (r2) -#define r3 REG (r3) -#define r4 REG (r4) -#define r5 REG (r5) -#define r6 REG (r6) -#define r7 REG (r7) -#define r8 REG (r8) -#define r9 REG (r9) -#define r10 REG (r10) -#define r11 REG (r11) -#define r12 REG (r12) -#define r13 REG (r13) -#define r14 REG (r14) -#define r15 REG (r15) -#define vbr REG (vbr) -#define gbr REG (gbr) -#define pr REG (pr) -#define mach REG (mach) -#define macl REG (macl) -#define sr REG (sr) -#define pc REG (pc) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h deleted file mode 100644 index 6ae0a83771..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/cpu.h +++ /dev/null @@ -1,909 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/sh.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SH Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * We define the interrupt stack in the linker script - */ -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * We currently support sh1 only, which has no FPU, other SHes have an FPU - * - * The macro name "SH_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if SH_HAS_FPU -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_SOFTWARE_FP FALSE -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#if SH_HAS_FPU -#define CPU_ALL_TASKS_ARE_FP TRUE -#else -#define CPU_ALL_TASKS_ARE_FP FALSE -#endif - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#if SH_HAS_FPU -#define CPU_IDLE_TASK_IS_FP TRUE -#else -#define CPU_IDLE_TASK_IS_FP FALSE -#endif - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#if SH_HAS_FPU -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else -#define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: SHes can be big or little endian, the default is big endian - */ - -/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */ -#if defined(__LITTLE_ENDIAN__) -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#else -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#endif - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000f - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - uint32_t *r15; /* stack pointer */ - - uint32_t macl; - uint32_t mach; - uint32_t *pr; - - uint32_t *r14; /* frame pointer/call saved */ - - uint32_t r13; /* call saved */ - uint32_t r12; /* call saved */ - uint32_t r11; /* call saved */ - uint32_t r10; /* call saved */ - uint32_t r9; /* call saved */ - uint32_t r8; /* call saved */ - - uint32_t *r7; /* arg in */ - uint32_t *r6; /* arg in */ - -#if 0 - uint32_t *r5; /* arg in */ - uint32_t *r4; /* arg in */ -#endif - - uint32_t *r3; /* scratch */ - uint32_t *r2; /* scratch */ - uint32_t *r1; /* scratch */ - - uint32_t *r0; /* arg return */ - - uint32_t gbr; - uint32_t sr; - -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r15 - -typedef struct { -#if SH_HAS_FPU -#ifdef SH4_USE_X_REGISTERS - union { - float f[16]; - double d[8]; - } x; -#endif - union { - float f[16]; - double d[8]; - } r; - float fpul; /* fp communication register */ - uint32_t fpscr; /* fp control register */ -#endif /* SH_HAS_FPU */ -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -#if SH_HAS_FPU -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ -SCORE_EXTERN void CPU_delay( uint32_t microseconds ); - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * We have been able to run the sptests with this value, but have not - * been able to run the tmtest suite. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ -#if defined(__SH4__) -/* FIXME: sh3 and SH3E? */ -#define CPU_ALIGNMENT 8 -#else -#define CPU_ALIGNMENT 4 -#endif - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * SH Specific Information: NONE - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level) \ - sh_disable_interrupts( _level ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level) \ - sh_enable_interrupts( _level) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level) \ - sh_flash_interrupts( _level) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( _newlevel) \ - sh_set_interrupt_level(_newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -/* - * FIXME: defined as a function for debugging - should be a macro - */ -SCORE_EXTERN void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp, - void *_tls_area ); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. - */ - -#if SH_HAS_FPU -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context;\ - } while(0) -#else -#define _CPU_Context_Initialize_fp( _destination ) \ - { } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * FIXME: Trap32 ??? - * - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * invokes a Trap32 Instruction which returns to the breakpoint - * routine of cmon. - */ - -#ifdef BSP_FATAL_HALT - /* we manage the fatal error in the board support package */ - void bsp_fatal_halt( uint32_t _error); -#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) -#else -#define _CPU_Fatal_halt( _source, _error)\ -{ \ - __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ - __asm__ volatile("mov #1, r4"); \ - __asm__ volatile("trapa #34"); \ -} -#endif - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -extern uint8_t _bit_set_table[]; - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - _output = 0;\ - if(_value > 0x00ff) \ - { _value >>= 8; _output = 8; } \ - if(_value > 0x000f) \ - { _output += 4; _value >>= 4; } \ - _output += _bit_set_table[ _value]; } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * @brief CPU Initialize - * - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * @brief This routine saves the floating point context passed to it. - * - * _CPU_Context_save_fp - * - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * @brief This routine restores the floating point context passed to it. - * - * _CPU_Context_restore_fp - * - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/types.h b/cpukit/score/cpu/sh/rtems/score/types.h deleted file mode 100644 index d740b2f901..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/types.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file - * - * @brief Hitachi SH CPU Type Definitions - * - * This include file contains information pertaining to the Hitachi SH - * processor. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; - -typedef void sh_isr; -typedef void ( *sh_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/asm.h b/cpukit/score/cpu/sparc/rtems/asm.h deleted file mode 100644 index a2b11f63fc..0000000000 --- a/cpukit/score/cpu/sparc/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Entry for traps which jump to a programmer-specified trap handler. - */ - -#define TRAP(_vector, _handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -/* - * Used for the reset trap to avoid a supervisor instruction - */ - -#define RTRAP(_vector, _handler) \ - mov %g0, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h deleted file mode 100644 index b73a56e0c0..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ /dev/null @@ -1,1383 +0,0 @@ -/** - * @file - * - * @brief SPARC CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC processor. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/sparc.h> - -/* conditional compilation parameters */ - -#if defined(RTEMS_SMP) - /* - * The SPARC ABI is a bit special with respect to the floating point context. - * The complete floating point context is volatile. Thus from an ABI point - * of view nothing needs to be saved and restored during a context switch. - * Instead the floating point context must be saved and restored during - * interrupt processing. Historically the deferred floating point switch is - * used for SPARC and the complete floating point context is saved and - * restored during a context switch to the new floating point unit owner. - * This is a bit dangerous since post-switch actions (e.g. signal handlers) - * and context switch extensions may silently corrupt the floating point - * context. The floating point unit is disabled for interrupt handlers. - * Thus in case an interrupt handler uses the floating point unit then this - * will result in a trap. - * - * On SMP configurations the deferred floating point switch is not - * supported in principle. So use here a safe floating point support. Safe - * means that the volatile floating point context is saved and restored - * around a thread dispatch issued during interrupt processing. Thus - * post-switch actions and context switch extensions may safely use the - * floating point unit. - */ - #define SPARC_USE_SAFE_FP_SUPPORT -#endif - -/** - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * - If TRUE, then they are inlined. - * - If FALSE, then a subroutine call is made. - * - * On this port, it is faster to inline _Thread_Enable_dispatch. - */ -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/** - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * - If TRUE, then RTEMS allocates the vector table it internally manages. - * - If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * THe SPARC is a simple vectored architecture. Usually there is no - * PIC and the CPU directly vectors the interrupts. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * - If TRUE, then it must be installed during initialization. - * - If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * - If TRUE, then the memory is allocated during initialization. - * - If FALSE, then the memory is allocated during initialization. - * - * The SPARC does not have hardware support for switching to a - * dedicated interrupt stack. The port includes support for doing this - * in software. - * - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * The SPARC port does not pass an Interrupt Stack Frame pointer to - * interrupt handlers. - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * Does the CPU have hardware floating point? - * - * - If TRUE, then the FLOATING_POINT task attribute is supported. - * - If FALSE, then the FLOATING_POINT task attribute is ignored. - * - * This is set based upon the multilib settings. - */ -#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SAFE_FP_SUPPORT) - #define CPU_HARDWARE_FP TRUE -#else - #define CPU_HARDWARE_FP FALSE -#endif - -/** - * The SPARC GCC port does not have a software floating point library - * that requires RTEMS assistance. - */ -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks FLOATING_POINT tasks implicitly? - * - * - If TRUE, then the FLOATING_POINT task attribute is assumed. - * - If FALSE, then the FLOATING_POINT task attribute is followed. - * - * The SPARC GCC port does not implicitly use floating point registers. - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * - If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * - If FALSE, then the IDLE task does not have a floating point context. - * - * The IDLE task does not have to be floating point on the SPARC. - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * - If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * - If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * On the SPARC, we can disable the FPU for integer only tasks so - * it is safe to defer floating point context switches. - */ -#if defined(SPARC_USE_SAFE_FP_SUPPORT) - #define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else - #define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * - If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * - If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * The SPARC architecture does not have a low power or halt instruction. - * It is left to the BSP and/or CPU specific code to provide an IDLE - * thread body which is aware of low power modes. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * - If TRUE, then the grows upward. - * - If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value was chosen to take advantages of caches. - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * The SPARC is big endian. - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * The SPARC is NOT little endian. - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC has 16 interrupt levels in the PIL field of the PSR. - */ -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#ifndef ASM -/** - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ -typedef struct { - /** This is the offset of the l0 register. */ - uint32_t l0; - /** This is the offset of the l1 register. */ - uint32_t l1; - /** This is the offset of the l2 register. */ - uint32_t l2; - /** This is the offset of the l3 register. */ - uint32_t l3; - /** This is the offset of the l4 register. */ - uint32_t l4; - /** This is the offset of the l5 register. */ - uint32_t l5; - /** This is the offset of the l6 register. */ - uint32_t l6; - /** This is the offset of the l7 register. */ - uint32_t l7; - /** This is the offset of the l0 register. */ - uint32_t i0; - /** This is the offset of the i1 register. */ - uint32_t i1; - /** This is the offset of the i2 register. */ - uint32_t i2; - /** This is the offset of the i3 register. */ - uint32_t i3; - /** This is the offset of the i4 register. */ - uint32_t i4; - /** This is the offset of the i5 register. */ - uint32_t i5; - /** This is the offset of the i6 register. */ - uint32_t i6_fp; - /** This is the offset of the i7 register. */ - uint32_t i7; - /** This is the offset of the register used to return structures. */ - void *structure_return_address; - - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - /** This is the offset of the register for saved argument 0. */ - uint32_t saved_arg0; - /** This is the offset of the register for saved argument 1. */ - uint32_t saved_arg1; - /** This is the offset of the register for saved argument 2. */ - uint32_t saved_arg2; - /** This is the offset of the register for saved argument 3. */ - uint32_t saved_arg3; - /** This is the offset of the register for saved argument 4. */ - uint32_t saved_arg4; - /** This is the offset of the register for saved argument 5. */ - uint32_t saved_arg5; - /** This field pads the structure so ldd and std instructions can be used. */ - uint32_t pad0; -} CPU_Minimum_stack_frame; - -#endif /* ASM */ - -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L1_OFFSET 0x04 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L2_OFFSET 0x08 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L3_OFFSET 0x0c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L4_OFFSET 0x10 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L5_OFFSET 0x14 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L6_OFFSET 0x18 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L7_OFFSET 0x1c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I0_OFFSET 0x20 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I1_OFFSET 0x24 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I2_OFFSET 0x28 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I3_OFFSET 0x2c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I4_OFFSET 0x30 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I5_OFFSET 0x34 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I7_OFFSET 0x3c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c - -/** This defines the size of the minimum stack frame. */ -#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 - -#if ( SPARC_HAS_FPU == 1 ) - #define CPU_PER_CPU_CONTROL_SIZE 8 -#else - #define CPU_PER_CPU_CONTROL_SIZE 4 -#endif - -/** - * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field - * relative to the Per_CPU_Control begin. - */ -#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 - -#if ( SPARC_HAS_FPU == 1 ) - /** - * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the - * Per_CPU_Control begin. - */ - #define SPARC_PER_CPU_FSR_OFFSET 4 -#endif - -/** - * @defgroup Contexts SPARC Context Structures - * - * @ingroup Score - * - * Generally there are 2 types of context to save. - * + Interrupt registers to save - * + Task level registers to save - * - * This means we have the following 3 context items: - * + task level context stuff:: Context_Control - * + floating point task stuff:: Context_Control_fp - * + special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ -/**@{**/ - -#ifndef ASM - -typedef struct { - /** - * This flag is context switched with each thread. It indicates - * that THIS thread has an _ISR_Dispatch stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ - uint32_t isr_dispatch_disable; - -#if ( SPARC_HAS_FPU == 1 ) - /** - * @brief Memory location to store the FSR register during interrupt - * processing. - * - * This is a write-only field. The FSR is written to force a completion of - * floating point operations in progress. - */ - uint32_t fsr; -#endif -} CPU_Per_CPU_control; - -/** - * @brief SPARC basic context. - * - * This structure defines the non-volatile integer and processor state context - * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY - * INTERFACE - SPARC Processor Supplement", Third Edition. - * - * The registers g2 through g4 are reserved for applications. GCC uses them as - * volatile registers by default. So they are treated like volatile registers - * in RTEMS as well. - * - * The register g6 contains the per-CPU control of the current processor. It - * is an invariant of the processor context. This register must not be saved - * and restored during context switches or interrupt services. - */ -typedef struct { - /** This will contain the contents of the g5 register. */ - uint32_t g5; - /** This will contain the contents of the g7 register. */ - uint32_t g7; - - /** - * This will contain the contents of the l0 and l1 registers. - * - * Using a double l0_and_l1 will put everything in this structure on a double - * word boundary which allows us to use double word loads and stores safely - * in the context switch. - */ - double l0_and_l1; - /** This will contain the contents of the l2 register. */ - uint32_t l2; - /** This will contain the contents of the l3 register. */ - uint32_t l3; - /** This will contain the contents of the l4 register. */ - uint32_t l4; - /** This will contain the contents of the l5 registeer.*/ - uint32_t l5; - /** This will contain the contents of the l6 register. */ - uint32_t l6; - /** This will contain the contents of the l7 register. */ - uint32_t l7; - - /** This will contain the contents of the i0 register. */ - uint32_t i0; - /** This will contain the contents of the i1 register. */ - uint32_t i1; - /** This will contain the contents of the i2 register. */ - uint32_t i2; - /** This will contain the contents of the i3 register. */ - uint32_t i3; - /** This will contain the contents of the i4 register. */ - uint32_t i4; - /** This will contain the contents of the i5 register. */ - uint32_t i5; - /** This will contain the contents of the i6 (e.g. frame pointer) register. */ - uint32_t i6_fp; - /** This will contain the contents of the i7 register. */ - uint32_t i7; - - /** This will contain the contents of the o6 (e.g. frame pointer) register. */ - uint32_t o6_sp; - /** - * This will contain the contents of the o7 (e.g. address of CALL - * instruction) register. - */ - uint32_t o7; - - /** This will contain the contents of the processor status register. */ - uint32_t psr; - /** - * This field is used to prevent heavy nesting of calls to _Thread_Dispatch - * on an interrupted task's stack. This is problematic on the slower - * SPARC CPU models at high interrupt rates. - */ - uint32_t isr_dispatch_disable; - -#if defined(RTEMS_SMP) - volatile uint32_t is_executing; -#endif -} Context_Control; - -/** - * This macro provides a CPU independent way for RTEMS to access the - * stack pointer in a context structure. The actual name and offset is - * CPU architecture dependent. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -/** This macro defines an offset into the context for use in assembly. */ -#define G5_OFFSET 0x00 -/** This macro defines an offset into the context for use in assembly. */ -#define G7_OFFSET 0x04 - -/** This macro defines an offset into the context for use in assembly. */ -#define L0_OFFSET 0x08 -/** This macro defines an offset into the context for use in assembly. */ -#define L1_OFFSET 0x0C -/** This macro defines an offset into the context for use in assembly. */ -#define L2_OFFSET 0x10 -/** This macro defines an offset into the context for use in assembly. */ -#define L3_OFFSET 0x14 -/** This macro defines an offset into the context for use in assembly. */ -#define L4_OFFSET 0x18 -/** This macro defines an offset into the context for use in assembly. */ -#define L5_OFFSET 0x1C -/** This macro defines an offset into the context for use in assembly. */ -#define L6_OFFSET 0x20 -/** This macro defines an offset into the context for use in assembly. */ -#define L7_OFFSET 0x24 - -/** This macro defines an offset into the context for use in assembly. */ -#define I0_OFFSET 0x28 -/** This macro defines an offset into the context for use in assembly. */ -#define I1_OFFSET 0x2C -/** This macro defines an offset into the context for use in assembly. */ -#define I2_OFFSET 0x30 -/** This macro defines an offset into the context for use in assembly. */ -#define I3_OFFSET 0x34 -/** This macro defines an offset into the context for use in assembly. */ -#define I4_OFFSET 0x38 -/** This macro defines an offset into the context for use in assembly. */ -#define I5_OFFSET 0x3C -/** This macro defines an offset into the context for use in assembly. */ -#define I6_FP_OFFSET 0x40 -/** This macro defines an offset into the context for use in assembly. */ -#define I7_OFFSET 0x44 - -/** This macro defines an offset into the context for use in assembly. */ -#define O6_SP_OFFSET 0x48 -/** This macro defines an offset into the context for use in assembly. */ -#define O7_OFFSET 0x4C - -/** This macro defines an offset into the context for use in assembly. */ -#define PSR_OFFSET 0x50 -/** This macro defines an offset into the context for use in assembly. */ -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 - -#if defined(RTEMS_SMP) - #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 -#endif - -#ifndef ASM -/** - * @brief SPARC basic context. - * - * This structure defines floating point context area. - */ -typedef struct { - /** This will contain the contents of the f0 and f1 register. */ - double f0_f1; - /** This will contain the contents of the f2 and f3 register. */ - double f2_f3; - /** This will contain the contents of the f4 and f5 register. */ - double f4_f5; - /** This will contain the contents of the f6 and f7 register. */ - double f6_f7; - /** This will contain the contents of the f8 and f9 register. */ - double f8_f9; - /** This will contain the contents of the f10 and f11 register. */ - double f10_f11; - /** This will contain the contents of the f12 and f13 register. */ - double f12_f13; - /** This will contain the contents of the f14 and f15 register. */ - double f14_f15; - /** This will contain the contents of the f16 and f17 register. */ - double f16_f17; - /** This will contain the contents of the f18 and f19 register. */ - double f18_f19; - /** This will contain the contents of the f20 and f21 register. */ - double f20_f21; - /** This will contain the contents of the f22 and f23 register. */ - double f22_f23; - /** This will contain the contents of the f24 and f25 register. */ - double f24_f25; - /** This will contain the contents of the f26 and f27 register. */ - double f26_f27; - /** This will contain the contents of the f28 and f29 register. */ - double f28_f29; - /** This will contain the contents of the f30 and f31 register. */ - double f30_f31; - /** This will contain the contents of the floating point status register. */ - uint32_t fsr; -} Context_Control_fp; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -/** This macro defines an offset into the FPU context for use in assembly. */ -#define FO_F1_OFFSET 0x00 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F2_F3_OFFSET 0x08 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F4_F5_OFFSET 0x10 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F6_F7_OFFSET 0x18 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F8_F9_OFFSET 0x20 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F1O_F11_OFFSET 0x28 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F12_F13_OFFSET 0x30 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F14_F15_OFFSET 0x38 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F16_F17_OFFSET 0x40 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F18_F19_OFFSET 0x48 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F2O_F21_OFFSET 0x50 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F22_F23_OFFSET 0x58 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F24_F25_OFFSET 0x60 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F26_F27_OFFSET 0x68 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F28_F29_OFFSET 0x70 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F3O_F31_OFFSET 0x78 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define FSR_OFFSET 0x80 - -/** This defines the size of the FPU context area for use in assembly. */ -#define CONTEXT_CONTROL_FP_SIZE 0x84 - -#ifndef ASM - -/** @} */ - -/** - * @brief Interrupt stack frame (ISF). - * - * Context saved on stack for an interrupt. - * - * NOTE: The PSR, PC, and NPC are only saved in this structure for the - * benefit of the user's handler. - */ -typedef struct { - /** On an interrupt, we must save the minimum stack frame. */ - CPU_Minimum_stack_frame Stack_frame; - /** This is the offset of the PSR on an ISF. */ - uint32_t psr; - /** This is the offset of the XXX on an ISF. */ - uint32_t pc; - /** This is the offset of the XXX on an ISF. */ - uint32_t npc; - /** This is the offset of the g1 register on an ISF. */ - uint32_t g1; - /** This is the offset of the g2 register on an ISF. */ - uint32_t g2; - /** This is the offset of the g3 register on an ISF. */ - uint32_t g3; - /** This is the offset of the g4 register on an ISF. */ - uint32_t g4; - /** This is the offset of the g5 register on an ISF. */ - uint32_t g5; - /** This is the offset is reserved for alignment on an ISF. */ - uint32_t reserved_for_alignment; - /** This is the offset of the g7 register on an ISF. */ - uint32_t g7; - /** This is the offset of the i0 register on an ISF. */ - uint32_t i0; - /** This is the offset of the i1 register on an ISF. */ - uint32_t i1; - /** This is the offset of the i2 register on an ISF. */ - uint32_t i2; - /** This is the offset of the i3 register on an ISF. */ - uint32_t i3; - /** This is the offset of the i4 register on an ISF. */ - uint32_t i4; - /** This is the offset of the i5 register on an ISF. */ - uint32_t i5; - /** This is the offset of the i6 register on an ISF. */ - uint32_t i6_fp; - /** This is the offset of the i7 register on an ISF. */ - uint32_t i7; - /** This is the offset of the y register on an ISF. */ - uint32_t y; - /** This is the offset of the tpc register on an ISF. */ - uint32_t tpc; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c - -/** This defines the size of the ISF area for use in assembly. */ -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \ - CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 - -#ifndef ASM -/** - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; - -/** - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -typedef struct { - /** This will contain a "mov %psr, %l0" instruction. */ - uint32_t mov_psr_l0; - /** This will contain a "sethi %hi(_handler), %l4" instruction. */ - uint32_t sethi_of_handler_to_l4; - /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ - uint32_t jmp_to_low_of_handler_plus_l4; - /** This will contain a " mov _vector, %l3" instruction. */ - uint32_t mov_vector_l3; -} CPU_Trap_table_entry; - -/** - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/** - * The size of the floating point context area. - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/** - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 - -/** - * The SPARC has 256 vectors but the port treats 256-512 as synchronous - * traps. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 - -/** - * This is the bit step in a vector number to indicate it is being installed - * as a synchronous trap. - */ -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 - -/** - * This macro indicates that @a _trap as an asynchronous trap. - */ -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) - -/** - * This macro indicates that @a _trap as a synchronous trap. - */ -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) - -/** - * This macro returns the real hardware vector number associated with @a _trap. - */ -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/** - * What is the size of a pointer on this architecture? - */ -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -/* - * ISR handler macros - */ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ -#define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/** - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -/** - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel << 8) - -/** - * @brief Obtain the current interrupt disable level. - * - * This method is invoked to return the current interrupt disable level. - * - * @return This method returns the current interrupt disable level. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * @param[in] the_context points to the context area - * @param[in] stack_base is the low address of the allocated stack area - * @param[in] size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to TRUE if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/** - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * The FP context area for the SPARC is a simple structure and nothing - * special is required to find the "starting load point" - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ -extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) - RTEMS_NO_RETURN; - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -#if ( SPARC_HAS_BITSCAN == 0 ) - /** - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - #define CPU_USE_GENERIC_BITFIELD_CODE TRUE - /** - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. Thus is needs the generic - * data table used by that algorithm. - */ - #define CPU_USE_GENERIC_BITFIELD_DATA TRUE -#else - #error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* functions */ - -/** - * @brief SPARC specific initialization. - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -/** - * @brief SPARC specific raw ISR installer. - * - * This routine installs @a new_handler to be directly called from the trap - * table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the new ISR handler - * @param[in] old_handler will contain the old ISR handler - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief SPARC specific RTEMS ISR installer. - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the new ISR handler - * @param[in] old_handler will contain the old ISR handler - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief SPARC specific context switch. - * - * This routine switches from the run context to the heir context. - * - * @param[in] run is the currently executing thread - * @param[in] heir will become the currently executing thread - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @brief SPARC specific context restore. - * - * This routine is generally used only to restart self in an - * efficient manner. - * - * @param[in] new_context is the context to restore - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * @brief The pointer to the current per-CPU control is available via register - * g6. - */ -register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); - -#define _CPU_Get_current_per_CPU_control() ( _SPARC_Per_CPU_current ) - -#if defined(RTEMS_SMP) - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - #if defined(__leon__) && !defined(RTEMS_PARAVIRT) - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - return _LEON3_Get_current_processor(); - } - #else - uint32_t _CPU_SMP_Get_current_processor( void ); - #endif - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -/** - * @brief SPARC specific save FPU method. - * - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is the area to save into - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @brief SPARC specific restore FPU method. - * - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is the area to restore from - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -typedef struct { - uint32_t trap; - CPU_Interrupt_frame *isf; -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @brief SPARC specific method to endian swap an uint32_t. - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * @param[in] value is the value to endian swap - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * - swap least significant two bytes with 16-bit rotate - * - swap upper and lower 16-bits - * - swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @brief SPARC specific method to endian swap an uint16_t. - * - * The following routine swaps the endian format of a uint16_t. - * - * @param[in] value is the value to endian swap - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -typedef CPU_Counter_ticks (*SPARC_Counter_difference)( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -/* - * The SPARC processors supported by RTEMS have no built-in CPU counter - * support. We have to use some hardware counter module for this purpose. The - * BSP must provide a 32-bit register which contains the current CPU counter - * value and a function for the difference calculation. It can use for example - * the GPTIMER instance used for the clock driver. - */ -typedef struct { - volatile const CPU_Counter_ticks *counter_register; - SPARC_Counter_difference counter_difference; -} SPARC_Counter; - -extern SPARC_Counter _SPARC_Counter; - -/* - * Returns always a value of one regardless of the parameters. This prevents - * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe - * default. - */ -CPU_Counter_ticks _SPARC_Counter_difference_default( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -static inline bool _SPARC_Counter_is_default( void ) -{ - return _SPARC_Counter.counter_difference - == _SPARC_Counter_difference_default; -} - -static inline void _SPARC_Counter_initialize( - volatile const CPU_Counter_ticks *counter_register, - SPARC_Counter_difference counter_difference -) -{ - _SPARC_Counter.counter_register = counter_register; - _SPARC_Counter.counter_difference = counter_difference; -} - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - return *_SPARC_Counter.counter_register; -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return (*_SPARC_Counter.counter_difference)( second, first ); -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/types.h b/cpukit/score/cpu/sparc/rtems/score/types.h deleted file mode 100644 index 4186012589..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/types.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file - * - * @brief SPARC CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * SPARC processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** - * @brief Priority bit map type. - * - * On the SPARC, there is no bitscan instruction and no penalty associated - * for using 16-bit variables. With no overriding architectural factors, - * just using a uint16_t. - */ -typedef uint16_t Priority_bit_map_Word; - -/** - * @brief SPARC ISR handler return type. - * - * This is the type which SPARC ISR Handlers return. - */ -typedef void sparc_isr; - -/** - * @brief SPARC ISR handler prototype. - * - * This is the prototype for SPARC ISR Handlers. - */ -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/asm.h b/cpukit/score/cpu/sparc64/rtems/asm.h deleted file mode 100644 index f4448b03a5..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/asm.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#ifndef __ASM__ -#define __ASM__ -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/rtems/score/cpu.h deleted file mode 100644 index ff56c7121a..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h +++ /dev/null @@ -1,1073 +0,0 @@ -/** - * @file - * - * @brief SPARC64 CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC64 processor. - */ - -/* - * - * - * COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC cpu.h file. Modifications are made - * to support the SPARC64 processor. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/sparc64.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SPARC Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the FLOATING_POINT task attribute is supported. - * If FALSE, then the FLOATING_POINT task attribute is ignored. - */ - -#if ( SPARC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks FLOATING_POINT tasks implicitly? - * - * If TRUE, then the FLOATING_POINT task attribute is assumed. - * If FALSE, then the FLOATING_POINT task attribute is followed. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value (16) was chosen to take advantages of caches. - * - * SPARC 64 requirements on floating point alignment is at least 8, - * and is 16 if quad-word fp instructions are available (e.g. LDQF). - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC v9 has 16 interrupt levels in the PIL field of the PSR. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -typedef struct { - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - void *structure_return_address; - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - uint64_t saved_arg0; - uint64_t saved_arg1; - uint64_t saved_arg2; - uint64_t saved_arg3; - uint64_t saved_arg4; - uint64_t saved_arg5; - uint64_t pad0; -} CPU_Minimum_stack_frame; - -#endif /* !ASM */ - -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -#define CPU_STACK_FRAME_L1_OFFSET 0x08 -#define CPU_STACK_FRAME_L2_OFFSET 0x10 -#define CPU_STACK_FRAME_L3_OFFSET 0x18 -#define CPU_STACK_FRAME_L4_OFFSET 0x20 -#define CPU_STACK_FRAME_L5_OFFSET 0x28 -#define CPU_STACK_FRAME_L6_OFFSET 0x30 -#define CPU_STACK_FRAME_L7_OFFSET 0x38 -#define CPU_STACK_FRAME_I0_OFFSET 0x40 -#define CPU_STACK_FRAME_I1_OFFSET 0x48 -#define CPU_STACK_FRAME_I2_OFFSET 0x50 -#define CPU_STACK_FRAME_I3_OFFSET 0x58 -#define CPU_STACK_FRAME_I4_OFFSET 0x60 -#define CPU_STACK_FRAME_I5_OFFSET 0x68 -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70 -#define CPU_STACK_FRAME_I7_OFFSET 0x78 -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 -#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8 - -#define CPU_MINIMUM_STACK_FRAME_SIZE 0xC0 - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ - -#ifndef ASM - -typedef struct { - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - - uint32_t isr_dispatch_disable; - uint32_t pad; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -#define G1_OFFSET 0x00 -#define G2_OFFSET 0x08 -#define G3_OFFSET 0x10 -#define G4_OFFSET 0x18 -#define G5_OFFSET 0x20 -#define G6_OFFSET 0x28 -#define G7_OFFSET 0x30 - -#define L0_OFFSET 0x38 -#define L1_OFFSET 0x40 -#define L2_OFFSET 0x48 -#define L3_OFFSET 0x50 -#define L4_OFFSET 0x58 -#define L5_OFFSET 0x60 -#define L6_OFFSET 0x68 -#define L7_OFFSET 0x70 - -#define I0_OFFSET 0x78 -#define I1_OFFSET 0x80 -#define I2_OFFSET 0x88 -#define I3_OFFSET 0x90 -#define I4_OFFSET 0x98 -#define I5_OFFSET 0xA0 -#define I6_FP_OFFSET 0xA8 -#define I7_OFFSET 0xB0 - -#define O0_OFFSET 0xB8 -#define O1_OFFSET 0xC0 -#define O2_OFFSET 0xC8 -#define O3_OFFSET 0xD0 -#define O4_OFFSET 0xD8 -#define O5_OFFSET 0xE0 -#define O6_SP_OFFSET 0xE8 -#define O7_OFFSET 0xF0 - -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 -#define ISR_PAD_OFFSET 0xFC - -/* - * The floating point context area. - */ - -#ifndef ASM - -typedef struct { - double f0; /* f0-f1 */ - double f2; /* f2-f3 */ - double f4; /* f4-f5 */ - double f6; /* f6-f7 */ - double f8; /* f8-f9 */ - double f10; /* f10-f11 */ - double f12; /* f12-f13 */ - double f14; /* f14-f15 */ - double f16; /* f16-f17 */ - double f18; /* f18-f19 */ - double f20; /* f20-f21 */ - double f22; /* f22-f23 */ - double f24; /* f24-f25 */ - double f26; /* f26-f27 */ - double f28; /* f28-f29 */ - double f30; /* f30-f31 */ - double f32; - double f34; - double f36; - double f38; - double f40; - double f42; - double f44; - double f46; - double f48; - double f50; - double f52; - double f54; - double f56; - double f58; - double f60; - double f62; - uint64_t fsr; -} Context_Control_fp; - -#endif /* !ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -#define FO_OFFSET 0x00 -#define F2_OFFSET 0x08 -#define F4_OFFSET 0x10 -#define F6_OFFSET 0x18 -#define F8_OFFSET 0x20 -#define F1O_OFFSET 0x28 -#define F12_OFFSET 0x30 -#define F14_OFFSET 0x38 -#define F16_OFFSET 0x40 -#define F18_OFFSET 0x48 -#define F2O_OFFSET 0x50 -#define F22_OFFSET 0x58 -#define F24_OFFSET 0x60 -#define F26_OFFSET 0x68 -#define F28_OFFSET 0x70 -#define F3O_OFFSET 0x78 -#define F32_OFFSET 0x80 -#define F34_OFFSET 0x88 -#define F36_OFFSET 0x90 -#define F38_OFFSET 0x98 -#define F4O_OFFSET 0xA0 -#define F42_OFFSET 0xA8 -#define F44_OFFSET 0xB0 -#define F46_OFFSET 0xB8 -#define F48_OFFSET 0xC0 -#define F5O_OFFSET 0xC8 -#define F52_OFFSET 0xD0 -#define F54_OFFSET 0xD8 -#define F56_OFFSET 0xE0 -#define F58_OFFSET 0xE8 -#define F6O_OFFSET 0xF0 -#define F62_OFFSET 0xF8 -#define FSR_OFFSET 0x100 - -#define CONTEXT_CONTROL_FP_SIZE 0x108 - -#ifndef ASM - -/* - * Context saved on stack for an interrupt. - * - * NOTE: The tstate, tpc, and tnpc are saved in this structure - * to allow resetting the TL while still being able to return - * from a trap later. The PIL is saved because - * if this is an external interrupt, we will mask lower - * priority interrupts until finishing. Even though the y register - * is deprecated, gcc still uses it. - */ - -typedef struct { - CPU_Minimum_stack_frame Stack_frame; - uint64_t tstate; - uint64_t tpc; - uint64_t tnpc; - uint64_t pil; - uint64_t y; - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - uint64_t tvec; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -#define ISF_TSTATE_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 -#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 -#define ISF_TNPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 -#define ISF_PIL_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 -#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 -#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 -#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 -#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 -#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 -#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 -#define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 -#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x58 -#define ISF_O0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x60 -#define ISF_O1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x68 -#define ISF_O2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x70 -#define ISF_O3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x78 -#define ISF_O4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x80 -#define ISF_O5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x88 -#define ISF_O6_SP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x90 -#define ISF_O7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x98 -#define ISF_TVEC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0 - -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8 -#ifndef ASM -/* - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; - -/* - * This flag is context switched with each thread. It indicates - * that THIS thread has an _ISR_Dispatch stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ - -SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable; - -/* - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -/* For SPARC V9, we must use 6 of these instructions to perform a long - * jump, because the _handler value is now 64-bits. We also need to store - * temporary values in the global register set at this trap level. Because - * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3 - * to pass parameters to ISR_Handler. - * - * The instruction sequence is now more like: - * rdpr %tstate, %g4 - * setx _handler, %g2, %g3 - * jmp %g3+0 - * mov _vector, %g2 - */ -typedef struct { - uint32_t rdpr_tstate_g4; /* rdpr %tstate, %g4 */ - uint32_t sethi_of_hh_handler_to_g2; /* sethi %hh(_handler), %g2 */ - uint32_t or_g2_hm_handler_to_g2; /* or %l3, %hm(_handler), %g2 */ - uint32_t sllx_g2_by_32_to_g2; /* sllx %g2, 32, %g2 */ - uint32_t sethi_of_handler_to_g3; /* sethi %hi(_handler), %g3 */ - uint32_t or_g3_g2_to_g3; /* or %g3, %g2, %g3 */ - uint32_t jmp_to_low_of_handler_plus_g3; /* jmp %g3 + %lo(_handler) */ - uint32_t mov_vector_g2; /* mov _vector, %g2 */ -} CPU_Trap_table_entry; - -/* - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/* - * The size of the floating point context area. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -/* On SPARC v9, there are 512 vectors. The same philosophy applies to - * vector installation and use, we just provide a larger table. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 - -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 ) - -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 8 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - * - * Note: quad-word loads/stores need alignment of 16, but currently supported - * architectures do not provide HW implemented quad-word operations. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ - -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ - - #define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ - -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ - -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The FP context area for the SPARC is a simple structure and nothing - * special is required to find the "starting load point" - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - uint32_t level; \ - \ - level = sparc_disable_interrupts(); \ - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 0 ) -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE -#else -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 1 ) -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs new_handler to be directly called from the trap - * table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint64_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -/* - * _CPU_Thread_Idle_body - * - * Some SPARC implementations have low power, sleep, or idle modes. This - * tries to take advantage of those models. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * CPU_swap_u32 - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/score/types.h b/cpukit/score/cpu/sparc64/rtems/score/types.h deleted file mode 100644 index c4d1c7f85e..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief SPARC64 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * SPARC-v9 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void sparc_isr; -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/v850/rtems/asm.h b/cpukit/score/cpu/v850/rtems/asm.h deleted file mode 100644 index 265e4967ae..0000000000 --- a/cpukit/score/cpu/v850/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2012. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/no_cpu.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h deleted file mode 100644 index c531d0c131..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpu.h +++ /dev/null @@ -1,1209 +0,0 @@ -/** - * @file - * - * @brief V850 CPU Department Source - * - * This include file contains information pertaining to the v850 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/v850.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * The v850 is a RISC CPU which typically has enough memory to justify - * the inlining of this method. - */ -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * The v850 does not have support for a hardware interrupt stack. - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * This port uses the Progammable Interrupt Controller interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * The v850 does not have support for a hardware interrupt stack. - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "V850_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * Some v850 models do have IEEE hardware floating point support but - * they do not have any special registers to save or bit(s) which - * determine if the FPU is enabled. In short, there appears to be nothing - * related to the floating point operations which impact the RTEMS - * thread context switch. Thus from an RTEMS perspective, there is really - * no FPU to manage. - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * This should be false until it has been demonstrated that gcc for the - * v850 generates FPU code when it is unexpected. But even this would - * not matter since there are no FP specific registers or bits which - * would be corrupted if an FP operation occurred in an integer only - * thread. - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * The IDLE thread should not be using the FPU. Leave this off. - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * See earlier comments. There is no FPU state to manage. - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * There does not appear to be a reason for the v850 port itself to provide - * a special idle task. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * The v850 stack grows from high addresses to low addresses. - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * Until proven otherwise, use the compiler default. - */ -#define CPU_STRUCTURE_ALIGNMENT - -/** - * The v850 should use 64-bit timestamps and inline them. - */ -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * The v850 is little endian. - */ -#define CPU_BIG_ENDIAN FALSE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * The v850 is little endian. - */ -#define CPU_LITTLE_ENDIAN TRUE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * The v850 only has a single bit in the CPU for interrupt disable/enable. - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * On the v850, this port saves special registers and those that are - * callee saved. - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r1; - /** This field is the stack pointer (e.g. r3). */ - uint32_t r3_stack_pointer; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t r28; - uint32_t r29; - uint32_t r31; - uint32_t psw; -} Context_Control; - -/** - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r3_stack_pointer - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * The v850 does not need a floating point context but this needs to be - * defined so confdefs.h. - */ -/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */ -#define CPU_CONTEXT_FP_SIZE 0 - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * There is no reason to think the v850 needs extra MPCI receive - * server stack. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * This should be very conservative on the v850. - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than 8. - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than CPU_ALIGNMENT. - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than CPU_ALIGNMENT. - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * The v850 has enough RAM where alignment to 16 may be desirable depending - * on the cache properties. But this remains to be demonstrated. - */ -#define CPU_STACK_ALIGNMENT 4 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * On the v850, we need to save the PSW and use "di" to disable interrupts. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned int _psw; \ - \ - v850_get_psw( _psw ); \ - __asm__ __volatile__( "di" ); \ - _isr_cookie = _psw; \ - } while (0) - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * On the v850, we simply need to restore the PSW. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned int _psw = (_isr_cookie); \ - \ - v850_set_psw( _psw ); \ - } while (0) - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * This saves at least one instruction over using enable/disable back to back. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned int _psw = (_isr_cookie); \ - v850_set_psw( _psw ); \ - __asm__ __volatile__( "di" ); \ - } while (0) - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * On the v850, level 0 is enabled. Non-zero is disabled. - */ -#define _CPU_ISR_Set_level( new_level ) \ - do { \ - if ( new_level ) \ - __asm__ __volatile__( "di" ); \ - else \ - __asm__ __volatile__( "ei" ); \ - } while (0) - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * This method is implemented in C on the v850. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * This method is implemented in C on the v850. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * On the v850, we require a special entry point to restart a task. - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* XXX this should be possible to remove */ -#if 0 -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * Move the error code into r10, disable interrupts and halt. - */ -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - __asm__ __volatile__ ( "di" ); \ - __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \ - __asm__ __volatile__ ( "halt" ); \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. The empty - * stub routines are left as a place holder in case someone figures - * out how to do a v850 implementation better than the generic algorithm. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/** @} */ - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * This is implemented in C. - * - * v850 CPU Dependent Source - */ -void _CPU_Initialize(void); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * This is implemented in assembly on the v850. - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * This is implemented in assembly on the v850. - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * The v850 has a single instruction to swap endianness on a 32 bit quantity. - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - unsigned int swapped; - - #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) - unsigned int v; - - v = value; - __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) ); - #else - uint32_t byte1, byte2, byte3, byte4; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - #endif - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * The v850 has a single instruction to swap endianness on a 16 bit quantity. - */ -static inline uint16_t CPU_swap_u16( uint16_t value ) -{ - unsigned int swapped; - - #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) - unsigned int v; - - v = value; - __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) ); - #else - swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff); - #endif - return swapped; -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h deleted file mode 100644 index 8a74cc6410..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * @brief V850 Assembly File - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/v850/rtems/score/types.h b/cpukit/score/cpu/v850/rtems/score/types.h deleted file mode 100644 index a209d091f3..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief V850 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * v850 processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif |