diff options
| author | Amar Takhar <amar@rtems.org> | 2015-12-11 17:52:17 -0500 |
|---|---|---|
| committer | Amar Takhar <amar@rtems.org> | 2015-12-11 17:52:17 -0500 |
| commit | d267a7a06a4c4f75b646b538abc42fefd47718f5 (patch) | |
| tree | 92a1aee50858090fd9494a7975e4602a227f1d3f | |
| parent | f39e6afe753fa0d011524f9c378447ef79dcf0ec (diff) | |
Move headers required by i386 SMP support.include
384 files changed, 0 insertions, 62705 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h deleted file mode 100644 index 833a63c9c0..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H -#define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000 - -#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 ) - -#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 ) - -#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 ) - -#define BSP_ARM_L2C_310_BASE 0xfffef000 - -#define BSP_ARM_L2C_310_ID 0x410000c9 - -/* Forward declaration */ -struct rtems_bsdnet_ifconfig; - -/** @brief Network interface attach detach - * - * Attaches a network interface tp the network stack. - * NOTE: Detaching is not supported! - */ -int altera_cyclone_v_network_if_attach_detach( - struct rtems_bsdnet_ifconfig *config, - int attaching ); - -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH altera_cyclone_v_network_if_attach_detach -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h deleted file mode 100644 index 9a4411d637..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/include/i2cdrv.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef I2CDRV_H -#define I2CDRV_H - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -rtems_device_driver i2cdrv_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -rtems_device_driver i2cdrv_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -rtems_device_driver i2cdrv_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -rtems_device_driver i2cdrv_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -rtems_device_driver i2cdrv_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -rtems_device_driver i2cdrv_ioctl( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -#define I2C_DRIVER_TABLE_ENTRY \ - { \ - i2cdrv_initialize, \ - i2cdrv_open, \ - i2cdrv_close, \ - i2cdrv_read, \ - i2cdrv_write, \ - i2cdrv_ioctl \ - } - -#define I2C_IOC_SET_SLAVE_ADDRESS 1 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* I2CDRV_H */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/irq.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/irq.h deleted file mode 100644 index c136500415..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/include/irq.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H -#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H - -#ifndef ASM - -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#include <bsp/arm-a9mpcore-irq.h> -#include <bsp/arm-gic-irq.h> -#include <bsp/alt_interrupt_common.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Use interrupt IDs as defined in alt_interrupt_common.h */ -#define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0 -#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */
\ No newline at end of file diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h deleted file mode 100644 index c17c0107b4..0000000000 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/arm-gic-tm27.h> - -#endif /* __tm27_h */ diff --git a/c/src/lib/libbsp/arm/beagle/include/bsp.h b/c/src/lib/libbsp/arm/beagle/include/bsp.h deleted file mode 100644 index d9fd2ae7fb..0000000000 --- a/c/src/lib/libbsp/arm/beagle/include/bsp.h +++ /dev/null @@ -1,360 +0,0 @@ -/** - * @file - * - * @ingroup arm_beagle - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2012 Claas Ziemke. All rights reserved. - * - * Claas Ziemke - * Kernerstrasse 11 - * 70182 Stuttgart - * Germany - * <claas.ziemke@gmx.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified by Ben Gras <beng@shrike-systems.com> to add lots - * of beagleboard/beaglebone definitions, delete lpc32xx specific - * ones, and merge with some other header files. - */ - -#ifndef LIBBSP_ARM_BEAGLE_BSP_H -#define LIBBSP_ARM_BEAGLE_BSP_H - -#include <bspopts.h> -#include <stdint.h> -#include <bsp/start.h> -#include <bsp/default-initial-extension.h> -#include <bsp/beagleboneblack.h> - -#include <rtems.h> -#include <rtems/irq-extension.h> - -#include <libcpu/omap3.h> -#include <libcpu/am335x.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -/* UART base clock frequency */ -#define UART_CLOCK 48000000 - -/* Access memory-mapped I/O devices */ -#define mmio_read(a) (*(volatile uint32_t *)(a)) -#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v)) -#define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v)) -#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v)) - -#define REG16(x)(*((volatile uint16_t *)(x))) -#define REG(x)(*((volatile uint32_t *)(x))) -#define BIT(x)(0x1 << x) - -#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick())) - -/* Write a uint32_t value to a memory address. */ -static inline void -write32(uint32_t address, uint32_t value) -{ - REG(address) = value; -} - -/* Read an uint32_t from a memory address */ -static inline uint32_t -read32(uint32_t address) -{ - return REG(address); -} - -/* Set a 32 bits value depending on a mask */ -static inline void -set32(uint32_t address, uint32_t mask, uint32_t value) -{ - uint32_t val; - val = read32(address); - /* clear the bits */ - val &= ~(mask); - /* apply the value using the mask */ - val |= (value & mask); - write32(address, val); -} - -/* Write a uint16_t value to a memory address. */ -static inline void -write16(uint32_t address, uint16_t value) -{ - REG16(address) = value; -} - -/* Read an uint16_t from a memory address */ -static inline uint16_t -read16(uint32_t address) -{ - return REG16(address); -} - -/* Data synchronization barrier */ -static inline void dsb(void) -{ - asm volatile("dsb" : : : "memory"); -} - -/* Instruction synchronization barrier */ -static inline void isb(void) -{ - asm volatile("isb" : : : "memory"); -} - -/* flush data cache */ -static inline void flush_data_cache(void) -{ - asm volatile( - "mov r0, #0\n" - "mcr p15, #0, r0, c7, c10, #4\n" - : /* No outputs */ - : /* No inputs */ - : "r0","memory" - ); -} - -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; }) - -#define readb(c) ({ unsigned char __v = __arch_getb(c); __v; }) -#define readw(c) ({ unsigned short __v = __arch_getw(c); __v; }) -#define readl(c) ({ unsigned int __v = __arch_getl(c); __v; }) - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -#if !defined(IS_DM3730) && !defined(IS_AM335X) -#error Unrecognized BSP configured. -#endif - -#if IS_DM3730 -#define BSP_DEVICEMEM_START 0x48000000 -#define BSP_DEVICEMEM_END 0x5F000000 -#endif - -#if IS_AM335X -#define BSP_DEVICEMEM_START 0x44000000 -#define BSP_DEVICEMEM_END 0x57000000 -#endif - -/* per-target uart config */ -#if IS_AM335X -#define BSP_CONSOLE_UART 1 -#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1 -#define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ -#define BEAGLE_BASE_UART_1 0x44E09000 -#define BEAGLE_BASE_UART_2 0x48022000 -#define BEAGLE_BASE_UART_3 0x48024000 -#endif - -/* per-target uart config */ -#if IS_DM3730 -#define BSP_CONSOLE_UART 3 -#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3 -#define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ -#define BEAGLE_BASE_UART_1 0x4806A000 -#define BEAGLE_BASE_UART_2 0x4806C000 -#define BEAGLE_BASE_UART_3 0x49020000 -#endif - -/* GPIO pin config */ -#if IS_AM335X -#define BSP_GPIO_PIN_COUNT 128 -#define BSP_GPIO_PINS_PER_BANK 32 -#endif - -#if IS_DM3730 -#define BSP_GPIO_PIN_COUNT 192 -#define BSP_GPIO_PINS_PER_BANK 32 -#endif - -/* i2c stuff */ -typedef struct { - uint32_t rx_or_tx; - uint32_t stat; - uint32_t ctrl; - uint32_t clk_hi; - uint32_t clk_lo; - uint32_t adr; - uint32_t rxfl; - uint32_t txfl; - uint32_t rxb; - uint32_t txb; - uint32_t s_tx; - uint32_t s_txfl; -} beagle_i2c; - -/* sctlr */ -/* Read System Control Register */ -static inline uint32_t read_sctlr() -{ - uint32_t ctl; - - asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t" - : [ctl] "=r" (ctl)); - return ctl; -} - -/* Write System Control Register */ -static inline void write_sctlr(uint32_t ctl) -{ - asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t" - : : [ctl] "r" (ctl)); - isb(); -} - -/* Read Auxiliary Control Register */ -static inline uint32_t read_actlr() -{ - uint32_t ctl; - - asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t" - : [ctl] "=r" (ctl)); - return ctl; -} - -/* Write Auxiliary Control Register */ -static inline void write_actlr(uint32_t ctl) -{ - asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t" - : : [ctl] "r" (ctl)); - isb(); -} - -/* Write Translation Table Base Control Register */ -static inline void write_ttbcr(uint32_t bcr) -{ - asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t" - : : [bcr] "r" (bcr)); - - isb(); -} - -/* Read Domain Access Control Register */ -static inline uint32_t read_dacr() -{ - uint32_t dacr; - - asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t" - : [dacr] "=r" (dacr)); - - return dacr; -} - - -/* Write Domain Access Control Register */ -static inline void write_dacr(uint32_t dacr) -{ - asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t" - : : [dacr] "r" (dacr)); - - isb(); -} - -static inline void refresh_tlb(void) -{ - dsb(); - - /* Invalidate entire unified TLB */ - asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t" - : : [zero] "r" (0)); - - /* Invalidate all instruction caches to PoU. - * Also flushes branch target cache. */ - asm volatile("mcr p15, 0, %[zero], c7, c5, 0" - : : [zero] "r" (0)); - - /* Invalidate entire branch predictor array */ - asm volatile("mcr p15, 0, %[zero], c7, c5, 6" - : : [zero] "r" (0)); /* flush BTB */ - - dsb(); - isb(); -} - -/* Read Translation Table Base Register 0 */ -static inline uint32_t read_ttbr0() -{ - uint32_t bar; - - asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" - : [bar] "=r" (bar)); - - return bar & ARM_TTBR_ADDR_MASK; -} - - -/* Read Translation Table Base Register 0 */ -static inline uint32_t read_ttbr0_unmasked() -{ - uint32_t bar; - - asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t" - : [bar] "=r" (bar)); - - return bar; -} - -/* Write Translation Table Base Register 0 */ -static inline void write_ttbr0(uint32_t bar) -{ - dsb(); - isb(); - /* In our setup TTBR contains the base address *and* the flags - but other pieces of the kernel code expect ttbr to be the - base address of the l1 page table. We therefore add the - flags here and remove them in the read_ttbr0 */ - uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED; - asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t" - : : [bar] "r" (v)); - - refresh_tlb(); -} - -/* Behaviour on fatal error; default: test-friendly. - * set breakpoint to bsp_fatal_extension. - */ -/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */ -/*#define BSP_PRESS_KEY_FOR_RESET 1 */ -#define BSP_PRINT_EXCEPTION_CONTEXT 1 - /* human-readable exception info */ -#define BSP_RESET_BOARD_AT_EXIT 1 - /* causes qemu to exit, signaling end of test */ - - -/** - * @defgroup arm_beagle Beaglebone, Beagleboard Support - * - * @ingroup bsp_arm - * - * @brief Beaglebones and beagleboards support package - * - */ - -/** - * @brief Beagleboard specific set up of the MMU. - * - * Provide in the application to override. - */ -BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void); - -#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
\ No newline at end of file diff --git a/c/src/lib/libbsp/arm/beagle/include/i2c.h b/c/src/lib/libbsp/arm/beagle/include/i2c.h deleted file mode 100644 index e7d17163f4..0000000000 --- a/c/src/lib/libbsp/arm/beagle/include/i2c.h +++ /dev/null @@ -1,368 +0,0 @@ -/** - * @file - * - * @ingroup arm_beagle - * - * @brief I2C support API. - */ - -/* - * Copyright (c) 2012 Claas Ziemke. All rights reserved. - * - * Claas Ziemke - * Kernerstrasse 11 - * 70182 Stuttgart - * Germany - * <claas.ziemke@gmx.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_BEAGLE_I2C_H -#define LIBBSP_ARM_BEAGLE_I2C_H - -#include <rtems.h> - -#include <bsp.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ - /* (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ -/* - * The equation for the low and high time is - * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed - * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed - * - * If the duty cycle is 50% - * - * tlow = scll + scll_trim = sampling clock / (2 * speed) - * thigh = sclh + sclh_trim = sampling clock / (2 * speed) - * - * In TRM - * scll_trim = 7 - * sclh_trim = 5 - * - * The linux 2.6.30 kernel uses - * scll_trim = 6 - * sclh_trim = 6 - * - * These are the trim values for standard and fast speed - */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - - -/* Use the reference value of 96MHz if not explicitly set by the board */ -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -/* - * The reference minimum clock for high speed is 19.2MHz. - * The linux 2.6.30 kernel uses this value. - * The reference minimum clock for fast mode is 9.6MHz - * The reference minimum clock for standard mode is 4MHz - * In TRM, the value of 12MHz is used. - */ -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - - -#define DISP_LINE_LEN 128 -#define I2C_TIMEOUT 1000 - -#define I2C_BUS_MAX 3 - -#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x070000) - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 - -struct i2c { - unsigned short rev; /* 0x00 */ - unsigned short res1; - unsigned short ie; /* 0x04 */ - unsigned short res2; - unsigned short stat; /* 0x08 */ - unsigned short res3; - unsigned short iv; /* 0x0C */ - unsigned short res4; - unsigned short syss; /* 0x10 */ - unsigned short res4a; - unsigned short buf; /* 0x14 */ - unsigned short res5; - unsigned short cnt; /* 0x18 */ - unsigned short res6; - unsigned short data; /* 0x1C */ - unsigned short res7; - unsigned short sysc; /* 0x20 */ - unsigned short res8; - unsigned short con; /* 0x24 */ - unsigned short res9; - unsigned short oa; /* 0x28 */ - unsigned short res10; - unsigned short sa; /* 0x2C */ - unsigned short res11; - unsigned short psc; /* 0x30 */ - unsigned short res12; - unsigned short scll; /* 0x34 */ - unsigned short res13; - unsigned short sclh; /* 0x38 */ - unsigned short res14; - unsigned short systest; /* 0x3c */ - unsigned short res15; -}; - -static unsigned short wait_for_pin( void ); - -static void wait_for_bb( void ); - -static void flush_fifo( void ); - -void i2c_init( int speed, int slaveadd ); - -static int i2c_read_byte( - unsigned char devaddr, - unsigned char regoffset, - unsigned char *value -); - -int i2c_write( - unsigned char chip, - unsigned int addr, - int alen, - unsigned char *buffer, - int len -); - -int i2c_read( - unsigned char chip, - uint addr, - int alen, - unsigned char *buffer, - int len -); - -static int imw ( unsigned char chip, unsigned long addr, unsigned char byte ); - -static int imd( unsigned char chip, unsigned int addr, unsigned int length ); - -/** - * @brief Initializes the I2C module @a i2c. - * - * Valid @a clock_in_hz values are 100000 and 400000. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_ID Invalid @a i2c value. - * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. - */ -rtems_status_code beagle_i2c_init( - volatile beagle_i2c *i2c, - unsigned clock_in_hz -); - -/** - * @brief Resets the I2C module @a i2c. - */ -void beagle_i2c_reset(volatile beagle_i2c *i2c); - -/** - * @brief Sets the I2C module @a i2c clock. - * - * Valid @a clock_in_hz values are 100000 and 400000. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. - */ -rtems_status_code beagle_i2c_clock( - volatile beagle_i2c *i2c, - unsigned clock_in_hz -); - -/** - * @brief Starts a write transaction on the I2C module @a i2c. - * - * The address parameter @a addr must not contain the read/write bit. - * - * The error status may be delayed to the next - * beagle_i2c_write_with_optional_stop() due to controller flaws. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code beagle_i2c_write_start( - volatile beagle_i2c *i2c, - unsigned addr -); - -/** - * @brief Writes data via the I2C module @a i2c with optional stop. - * - * The error status may be delayed to the next - * beagle_i2c_write_with_optional_stop() due to controller flaws. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code beagle_i2c_write_with_optional_stop( - volatile beagle_i2c *i2c, - const uint8_t *out, - size_t n, - bool stop -); - -/** - * @brief Starts a read transaction on the I2C module @a i2c. - * - * The address parameter @a addr must not contain the read/write bit. - * - * The error status may be delayed to the next - * beagle_i2c_read_with_optional_stop() due to controller flaws. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code beagle_i2c_read_start( - volatile beagle_i2c *i2c, - unsigned addr -); - -/** - * @brief Reads data via the I2C module @a i2c with optional stop. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false. - */ -rtems_status_code beagle_i2c_read_with_optional_stop( - volatile beagle_i2c *i2c, - uint8_t *in, - size_t n, - bool stop -); - -/** - * @brief Writes and reads data via the I2C module @a i2c. - * - * This will be one bus transaction. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code beagle_i2c_write_and_read( - volatile beagle_i2c *i2c, - unsigned addr, - const uint8_t *out, - size_t out_size, - uint8_t *in, - size_t in_size -); - -/** - * @brief Writes data via the I2C module @a i2c. - * - * This will be one bus transaction. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -static inline rtems_status_code beagle_i2c_write( - volatile beagle_i2c *i2c, - unsigned addr, - const uint8_t *out, - size_t out_size -) -{ - return beagle_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0); -} - -/** - * @brief Reads data via the I2C module @a i2c. - * - * This will be one bus transaction. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -static inline rtems_status_code beagle_i2c_read( - volatile beagle_i2c *i2c, - unsigned addr, - uint8_t *in, - size_t in_size -) -{ - return beagle_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size); -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_BEAGLE_I2C_H */ diff --git a/c/src/lib/libbsp/arm/beagle/include/irq.h b/c/src/lib/libbsp/arm/beagle/include/irq.h deleted file mode 100644 index 4cbf3a271f..0000000000 --- a/c/src/lib/libbsp/arm/beagle/include/irq.h +++ /dev/null @@ -1,23 +0,0 @@ -/** - * @file - * - * @ingroup arm_beagle - * - * @brief Basic BSP IRQ info. - */ - -#ifndef LIBBSP_ARM_BEAGLE_IRQ_H -#define LIBBSP_ARM_BEAGLE_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 127 - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_BEAGLE_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/csb336/include/bsp.h b/c/src/lib/libbsp/arm/csb336/include/bsp.h deleted file mode 100644 index ec79476963..0000000000 --- a/c/src/lib/libbsp/arm/csb336/include/bsp.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * @file - * - * @ingroup arm_csb336 - * - * @brief Global BSP definitions. - */ - -/* - * BSP CSB336 header file - * - * Copyright (c) 2004 Cogent Computer Systems - * Written by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ -#ifndef LIBBSP_ARM_CSB336_BSP_H -#define LIBBSP_ARM_CSB336_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <mc9328mxl.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup arm_csb336 CSB336 Support - * - * @ingroup bsp_arm - * - * @brief CSB336 support package. - * - * @{ - */ - -#define BSP_FEATURE_IRQ_EXTENSION - -/* What is the input clock freq in hertz? */ -#define BSP_OSC_FREQ 16000000 /* 16 MHz oscillator */ -#define BSP_XTAL_FREQ 32768 /* 32.768 KHz crystal */ - -int get_perclk1_freq(void); - -/** - * @brief Network driver configuration - */ -extern struct rtems_bsdnet_ifconfig *config; - -/* Change these to match your board */ -int rtems_mc9328mxl_enet_attach(struct rtems_bsdnet_ifconfig *config, - void *chip); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mc9328mxl_enet_attach - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ - diff --git a/c/src/lib/libbsp/arm/csb337/include/bsp.h b/c/src/lib/libbsp/arm/csb337/include/bsp.h deleted file mode 100644 index 7f9d3c60ca..0000000000 --- a/c/src/lib/libbsp/arm/csb337/include/bsp.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * @file - * - * @ingroup arm_csb337 - * - * @brief Global BSP definitions. - */ - -/* - * CSB337 BSP header file - * - * Copyright (c) 2004 by Cogent Computer Systems - * Writtent by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef LIBBSP_ARM_CSB337_BSP_H -#define LIBBSP_ARM_CSB337_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup arm_csb337 CSB337 Support - * - * @ingroup bsp_arm - * - * @brief CSB337 support package. - * - * @{ - */ - -#define BSP_FEATURE_IRQ_EXTENSION - -/* What is the input clock freq in hertz? */ -#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ -#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ - -/* What is the last interrupt? */ -#define BSP_MAX_INT AT91RM9200_MAX_INT - -/* - * forward reference the type to avoid conflicts between libchip serial - * and libchip rtc get and set register types. - */ -typedef struct _console_tbl console_tbl; -console_tbl *BSP_get_uart_from_minor(int minor); - -static inline int32_t BSP_get_baud(void) {return 38400;} - -#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ - -/** - * @brief Network driver configuration - */ -extern struct rtems_bsdnet_ifconfig *config; - -/* Change these to match your board */ -int rtems_at91rm9200_emac_attach(struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_at91rm9200_emac_attach - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ - diff --git a/c/src/lib/libbsp/arm/edb7312/include/bsp.h b/c/src/lib/libbsp/arm/edb7312/include/bsp.h deleted file mode 100644 index 47a17559da..0000000000 --- a/c/src/lib/libbsp/arm/edb7312/include/bsp.h +++ /dev/null @@ -1,75 +0,0 @@ -/** - * @file - * @ingroup arm_edb7312 - * @brief Global BSP definitions. - */ - -/* - * Cirrus EP7312 BSP header file - * - * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ -#ifndef LIBBSP_ARM_EDB7312_BSP_H -#define LIBBSP_ARM_EDB7312_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION - -/** - * @defgroup arm_edb7312 EDB7312 Support - * @ingroup bsp_arm - * @brief EDB7312 Support Package - * @{ - */ - -/** - * @brief Define the interrupt mechanism for Time Test 27 - * - * NOTE: Following are not defined and are board independent - * - */ -struct rtems_bsdnet_ifconfig; -int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attaching); - -/** - * @name Network driver configuration - * @{ - */ - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach - -/** @} */ - -/* - * Prototypes for methods called from .S but implemented in C - */ -void edb7312_interrupt_dispatch(rtems_vector_number vector); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif /* _BSP_H */ diff --git a/c/src/lib/libbsp/arm/edb7312/irq/irq.h b/c/src/lib/libbsp/arm/edb7312/irq/irq.h deleted file mode 100644 index 04579a7c6f..0000000000 --- a/c/src/lib/libbsp/arm/edb7312/irq/irq.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * @file - * @ingroup edb7312_interrupt - * @brief Interrupt definitions. - */ - -/* - * Cirrus EP7312 Intererrupt handler - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com> - * - * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#endif /* __asm__ */ - -/** - * @defgroup edb7312_interrupt Interrupt Support - * @ingroup arm_edb7312 - * @brief Interrupt Support - * @{ - */ - -/** - * @name int interrupt status/mask register 1 - * @{ - */ - -#define BSP_EXTFIQ 0 -#define BSP_BLINT 1 -#define BSP_WEINT 2 -#define BSP_MCINT 3 -#define BSP_CSINT 4 -#define BSP_EINT1 5 -#define BSP_EINT2 6 -#define BSP_EINT3 7 -#define BSP_TC1OI 8 -#define BSP_TC2OI 9 -#define BSP_RTCMI 10 -#define BSP_TINT 11 -#define BSP_UTXINT1 12 -#define BSP_URXINT1 13 -#define BSP_UMSINT 14 -#define BSP_SSEOTI 15 - -/** @} */ - -/** - * @name int interrupt status/mask register 2 - * @{ - */ - -#define BSP_KBDINT 16 -#define BSP_SS2RX 17 -#define BSP_SS2TX 18 -#define BSP_UTXINT2 19 -#define BSP_URXINT2 20 - -/** @} */ - -/** - * @name int interrupt status/mask register 3 - * @{ - */ - -#define BSP_DAIINT 21 -#define BSP_MAX_INT 22 - -/** @} */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) - -/** @} */ - -#endif /* __IRQ_H__ */ diff --git a/c/src/lib/libbsp/arm/gba/include/bsp.h b/c/src/lib/libbsp/arm/gba/include/bsp.h deleted file mode 100644 index fa7df74d5b..0000000000 --- a/c/src/lib/libbsp/arm/gba/include/bsp.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * @file - * - * @ingroup arm_gba - * - * @brief Global BSP definitions. - */ - -/* - * RTEMS GBA BSP - * - * Copyright (c) 2004 - * Markku Puro <markku.puro@kopteri.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_GBA_H -#define LIBBSP_ARM_GBA_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION - -/** Define operation count for Tests */ -#define OPERATION_COUNT 10 - -/** gba_zero_memory library function in start.S */ -extern void gba_zero_memory(int start, int stop); -/** gba_move_memory library function in start.S */ -extern void gba_move_memory(int from, int toStart, int toEnd); -/** gba_set_memory library function in start.S */ -extern void gba_set_memory(int start, int stop, int data); - - -#ifdef __cplusplus -} -#endif - - -#endif /* __BSP_H_ */ -/** - * @defgroup arm_gba GBA Support - * - * @ingroup bsp_arm - * - * @brief GBA support package. - */ - diff --git a/c/src/lib/libbsp/arm/gba/irq/irq.h b/c/src/lib/libbsp/arm/gba/irq/irq.h deleted file mode 100644 index 37ae527912..0000000000 --- a/c/src/lib/libbsp/arm/gba/irq/irq.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @ingroup gba_interrupt - * - * @brief Interrupt definitions. - */ - -/* - * RTEMS GBA BSP - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2004 Markku Puro <markku.puro@kopteri.net> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#endif /* __asm__ */ - -#ifndef _IRQ_H_ -#define _IRQ_H_ - -/** - * @defgroup gba_interrupt Interrupt Support - * - * @ingroup arm_gba - * - * @brief Interrupt support. - */ - -/*---------------------------------------------------------------------------* - * MACROS * - *---------------------------------------------------------------------------*/ - -#define ENABLE_IRQ() GBA_REG_IME = 1; -#define DISABLE_IRQ() GBA_REG_IME = 0; - - -/*-------------------------------------------------------------------------+ -| Constants -+--------------------------------------------------------------------------*/ - -#define BSP_IRQ_VBLANK 0 -#define BSP_IRQ_HBLANK 1 -#define BSP_IRQ_VCOUNTER 2 -#define BSP_IRQ_TIMER0 3 -#define BSP_IRQ_TIMER1 4 -#define BSP_IRQ_TIMER2 5 -#define BSP_IRQ_TIMER3 6 -#define BSP_IRQ_SERIAL 7 -#define BSP_IRQ_DMA0 8 -#define BSP_IRQ_DMA1 9 -#define BSP_IRQ_DMA2 10 -#define BSP_IRQ_DMA3 11 -#define BSP_IRQ_KEY 12 -#define BSP_IRQ_CART 13 -#define BSP_IRQ_NA14 14 -#define BSP_IRQ_NA15 15 -#define BSP_MAX_INT 16 - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) - -#endif /* _IRQ_H_ */ diff --git a/c/src/lib/libbsp/arm/gdbarmsim/include/bsp.h b/c/src/lib/libbsp/arm/gdbarmsim/include/bsp.h deleted file mode 100644 index be69b6cd46..0000000000 --- a/c/src/lib/libbsp/arm/gdbarmsim/include/bsp.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file - * - * @ingroup arm_gdbarmsim - * - * @brief Global BSP definitions. - */ - -/* - * COPYRIGHT (c) 1989-2009. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_GDBARMSIM_BSP_H -#define LIBBSP_ARM_GDBARMSIM_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup arm_gdbarmsim GDBARMSIM Support - * - * @ingroup bsp_arm - * - * @brief GDBARMSIM support package. - * - * @{ - */ - -//#define BSP_GET_WORK_AREA_DEBUG 1 - -/** - * @brief Support for simulated clock tick - */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -/* - * Access to the GDB simulator. - */ -int gdbarmsim_system(const char *); -int gdbarmsim_rename(const char *, const char *); -int gdbarmsim__isatty(int); -clock_t gdbarmsim_times(struct tms *); -int gdbarmsim_gettimeofday(struct timeval *, void *); -int gdbarmsim_unlink(const char *); -int gdbarmsim_link(void); -int gdbarmsim_stat(const char *, struct stat *); -int gdbarmsim_fstat(int, struct stat *); -int gdbarmsim_swistat(int fd, struct stat * st); -int gdbarmsim_close(int); -clock_t gdbarmsim_clock(void); -int gdbarmsim_swiclose(int); -int gdbarmsim_open(const char *, int, ...); -int gdbarmsim_swiopen(const char *, int); -int gdbarmsim_writec(const char c); -int gdbarmsim_write(int, char *, int); -int gdbarmsim_swiwrite(int, char *, int); -int gdbarmsim_lseek(int, int, int); -int gdbarmsim_swilseek(int, int, int); -int gdbarmsim_read(int, char *, int); -int gdbarmsim_swiread(int, char *, int); -void initialise_monitor_handles(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ - diff --git a/c/src/lib/libbsp/arm/gdbarmsim/include/irq.h b/c/src/lib/libbsp/arm/gdbarmsim/include/irq.h deleted file mode 100644 index 3c86d22797..0000000000 --- a/c/src/lib/libbsp/arm/gdbarmsim/include/irq.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief Dummy interrupt definitions. - */ - -/* - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_DUMMY_IRQ_H -#define LIBBSP_ARM_DUMMY_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define DUMMY_IRQ_WDT 0 -#define DUMMY_IRQ_SOFTWARE 1 -#define DUMMY_IRQ_ARM_CORE_0 2 -#define DUMMY_IRQ_ARM_CORE_1 3 -#define DUMMY_IRQ_TIMER_0 4 -#define DUMMY_IRQ_TIMER_1 5 -#define DUMMY_IRQ_UART_0 6 -#define DUMMY_IRQ_UART_1 7 -#define DUMMY_IRQ_PWM 8 -#define DUMMY_IRQ_I2C_0 9 -#define DUMMY_IRQ_SPI_SSP_0 10 -#define DUMMY_IRQ_SSP_1 11 -#define DUMMY_IRQ_PLL 12 -#define DUMMY_IRQ_RTC 13 -#define DUMMY_IRQ_EINT_0 14 -#define DUMMY_IRQ_EINT_1 15 -#define DUMMY_IRQ_EINT_2 16 -#define DUMMY_IRQ_EINT_3 17 -#define DUMMY_IRQ_ADC_0 18 -#define DUMMY_IRQ_I2C_1 19 -#define DUMMY_IRQ_BOD 20 -#define DUMMY_IRQ_ETHERNET 21 -#define DUMMY_IRQ_USB 22 -#define DUMMY_IRQ_CAN 23 -#define DUMMY_IRQ_SD_MMC 24 -#define DUMMY_IRQ_DMA 25 -#define DUMMY_IRQ_TIMER_2 26 -#define DUMMY_IRQ_TIMER_3 27 -#define DUMMY_IRQ_UART_2 28 -#define DUMMY_IRQ_UART_3 29 -#define DUMMY_IRQ_I2C_2 30 -#define DUMMY_IRQ_I2S 31 - -#define DUMMY_IRQ_PRIORITY_VALUE_MIN 0U -#define DUMMY_IRQ_PRIORITY_VALUE_MAX 15U - -/** - * @brief Minimum vector number. - */ -#define BSP_INTERRUPT_VECTOR_MIN DUMMY_IRQ_WDT - -/** - * @brief Maximum vector number. - */ -#define BSP_INTERRUPT_VECTOR_MAX DUMMY_IRQ_I2S - -void bsp_interrupt_dispatch(void); - -#if 0 -void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority); - -unsigned lpc24xx_irq_priority( rtems_vector_number vector); -#endif - -/** @} */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_DUMMY_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/gp32/include/bsp.h b/c/src/lib/libbsp/arm/gp32/include/bsp.h deleted file mode 100644 index 7c8903f6e7..0000000000 --- a/c/src/lib/libbsp/arm/gp32/include/bsp.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * @ingroup arm_gp32 - * @brief Global BSP definitons. - */ - -/* - * Copyright (c) Canon Research France SA.] - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_GP32_BSP_H -#define LIBBSP_ARM_GP32_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <s3c24xx.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION - -#define gp32_initButtons() {rPBCON=0x0;} -#define gp32_getButtons() \ - ( (((~rPEDAT >> 6) & 0x3 )<<8) | (((~rPBDAT >> 8) & 0xFF)<<0) ) - -/** - * @defgroup arm_gp32 GP32 Support - * @ingroup bsp_arm - * @brief GP32 Support Pacakge - * @{ - */ - -/** - * @brief functions to get the differents s3c2400 clks - * @{ - */ - -uint32_t get_FCLK(void); -uint32_t get_HCLK(void); -uint32_t get_PCLK(void); -uint32_t get_UCLK(void); - -/** @} */ - -void gp32_setPalette( unsigned char pos, uint16_t color); - -/* What is the input clock freq in hertz? */ -/** @brief 12 MHz oscillator */ -#define BSP_OSC_FREQ 12000000 -/** @brief FCLK=133Mhz */ -#define M_MDIV 81 -#define M_PDIV 2 -#define M_SDIV 1 -/** @brief HCLK=FCLK/2, PCLK=FCLK/2 */ -#define M_CLKDIVN 2 -/** @brief enable refresh */ -#define REFEN 0x1 -/** @brief CBR(CAS before RAS)/auto refresh */ -#define TREFMD 0x0 -/** @brief 2 clk */ -#define Trp 0x0 -/** @brief 7 clk */ -#define Trc 0x3 -/** @brief 3 clk */ -#define Tchr 0x2 - -/** - * @brief This BSP provides its own IDLE thread to override the RTEMS one. - * - * So we prototype it and define the constant confdefs.h expects - * to configure a BSP specific one. - */ -void *bsp_idle_thread(uintptr_t ignored); - -/** @} */ - -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ - diff --git a/c/src/lib/libbsp/arm/gumstix/include/bsp.h b/c/src/lib/libbsp/arm/gumstix/include/bsp.h deleted file mode 100644 index fb21e13e92..0000000000 --- a/c/src/lib/libbsp/arm/gumstix/include/bsp.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * @file - * @ingroup arm_gumstix - * @brief Global BSP definitions. - */ - -/* - * By Yang Xi <hiyangxi@gmail.com>. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_GUMSTIX_BSP_H -#define LIBBSP_ARM_GUMSTIX_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup arm_gumstix Gumstix Support - * @ingroup bsp_arm - * @brief Gumstix support package - * @{ - */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_HAS_FRAME_BUFFER 1 - -/** @brief What is the input clock freq in hertz */ -#define BSP_MAIN_FREQ 3686400 /* 3.6864 MHz */ -#define BSP_SLCK_FREQ 32768 /* 32.768 KHz */ - -/** @brief What is the last interrupt */ -#define BSP_MAX_INT AT91RM9200_MAX_INT - -/* - * forward reference the type to avoid conflicts between libchip serial - * and libchip rtc get and set register types. - */ -typedef struct _console_tbl console_tbl; -console_tbl *BSP_get_uart_from_minor(int minor); - -static inline int32_t BSP_get_baud(void) {return 115200;} - -/** @brief How big should the interrupt stack be? */ -#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) - -#define ST_PIMR_PIV 33 /* 33 ticks of the 32.768Khz clock ~= 1msec */ - -#define outport_byte(port,val) *((unsigned char volatile*)(port)) = (val) -#define inport_byte(port,val) (val) = *((unsigned char volatile*)(port)) -#define outport_word(port,val) *((unsigned short volatile*)(port)) = (val) -#define inport_word(port,val) (val) = *((unsigned short volatile*)(port)) - -struct rtems_bsdnet_ifconfig; -extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int); -#define BSP_NE2000_NETWORK_DRIVER_NAME "ne1" -#define BSP_NE2000_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach - -#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME -#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_NE2000_NETWORK_DRIVER_NAME -#endif - -#ifndef RTEMS_BSP_NETWORK_DRIVER_ATTACH -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_NE2000_NETWORK_DRIVER_ATTACH -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ - diff --git a/c/src/lib/libbsp/arm/gumstix/include/tm27.h b/c/src/lib/libbsp/arm/gumstix/include/tm27.h deleted file mode 100644 index ed8d73e113..0000000000 --- a/c/src/lib/libbsp/arm/gumstix/include/tm27.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * @ingroup gumstix_tm27 - * @brief tm27 timing test support - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup gumstix_tm27 tm27 Support - * @ingroup arm_gumstix - * @brief tm27 Timing Test Support - * @{ - */ - -/** - * @name Interrupt mechanisms for Time Test 27 - * @{ - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) /* empty */ - -#define Cause_tm27_intr() /* empty */ - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/** @} */ - -/** @} */ - -#endif diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h b/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h deleted file mode 100644 index 8b94f9754d..0000000000 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/bsp.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * @file - * - * @ingroup arm_lm3s69xx - * - * @brief Global BSP Definitions - */ - -/* - * Copyright (c) 2011-2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LM3S69XX_BSP_H -#define LIBBSP_ARM_LM3S69XX_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (5 << 5) - -#define BSP_ARMV7M_SYSTICK_PRIORITY (6 << 5) - -#define BSP_ARMV7M_SYSTICK_FREQUENCY LM3S69XX_SYSTEM_CLOCK - -#ifndef ASM - -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_LM3S69XX_BSP_H */ - -/** - * @defgroup arm_lm3s69xx LM3S69XX Support - * - * @ingroup bsp_arm - * - * @brief LM3S69XX Support Package - */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/io.h b/c/src/lib/libbsp/arm/lm3s69xx/include/io.h deleted file mode 100644 index f9ddf4c8ee..0000000000 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/io.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * @file - * - * @ingroup lm3s69xx_io - * - * @brief IO definitions. - */ - -/* - * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LM3S69XX_IO_H -#define LIBBSP_ARM_LM3S69XX_IO_H -#include <bspopts.h> -#include <stdbool.h> - -/** - * @defgroup lm3s69xx_io IO Support - * - * @ingroup arm_lm3s69xx - * - * @brief IO support. - */ - -typedef enum { - LM3S69XX_GPIO_DIRECTION_INPUT, - LM3S69XX_GPIO_DIRECTION_OUTPUT -} lm3s69xx_gpio_direction; - -typedef enum { - LM3S69XX_GPIO_OTYPE_PUSH_PULL, - LM3S69XX_GPIO_OTYPE_OPEN_DRAIN -} lm3s69xx_gpio_otype; - -typedef enum { - LM3S69XX_GPIO_DRIVE_2MA, - LM3S69XX_GPIO_DRIVE_4MA, - LM3S69XX_GPIO_DRIVE_8MA -} lm3s69xx_gpio_drive; - -typedef enum { - LM3S69XX_GPIO_NO_PULL, - LM3S69XX_GPIO_PULL_UP, - LM3S69XX_GPIO_PULL_DOWN -} lm3s69xx_gpio_pull; - -typedef enum { - LM3S69XX_GPIO_DIGITAL_DISABLE, - LM3S69XX_GPIO_DIGITAL_ENABLE, -} lm3s69xx_gpio_digital; - -typedef enum { - LM3S69XX_GPIO_AF_DISABLE, - LM3S69XX_GPIO_AF_ENABLE -} lm3s69xx_gpio_af; - -typedef enum { - LM3S69XX_GPIO_ANALOG_DISABLE, - LM3S69XX_GPIO_ANALOG_ENABLE -} lm3s69xx_gpio_analog; - -typedef enum { - LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL, - LM3S69XX_GPIO_SLEW_RATE_CONTROL -} lm3s69xx_gpio_slew_rate_control; - -typedef struct { - unsigned int pin_first : 8; - unsigned int pin_last : 8; - unsigned int digital : 1; - unsigned int alternate : 1; - unsigned int analog : 1; - unsigned int dir : 1; - unsigned int otype : 1; - unsigned int drive : 2; - unsigned int pull : 2; - unsigned int slr : 1; -} lm3s69xx_gpio_config; - -typedef enum { - LM3S69XX_PORT_A, - LM3S69XX_PORT_B, - LM3S69XX_PORT_C, - LM3S69XX_PORT_D, - LM3S69XX_PORT_E, - LM3S69XX_PORT_F, - LM3S69XX_PORT_G, -#if LM3S69XX_NUM_GPIO_BLOCKS > 7 - LM3S69XX_PORT_H -#endif -} lm3s69xx_gpio_port; - -#define LM3S69XX_GPIO_PIN(port, idx) (((port) << 3) | (idx)) -#define LM3S69XX_GPIO_PORT_OF_PIN(pin) (((pin) >> 3) & 0xf) -#define LM3S69XX_GPIO_INDEX_OF_PIN(pin) ((pin) & 0x7) - -#define LM3S69XX_PIN_UART_TX(port, idx) \ - { \ - .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ - .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ - .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ - .alternate = LM3S69XX_GPIO_AF_ENABLE, \ - .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ - .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ - .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ - .drive = LM3S69XX_GPIO_DRIVE_2MA, \ - .pull = LM3S69XX_GPIO_NO_PULL, \ - .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ - } - -#define LM3S69XX_PIN_UART_RX(port, idx) \ - { \ - .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ - .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ - .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ - .alternate = LM3S69XX_GPIO_AF_ENABLE, \ - .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ - .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ - .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ - .drive = LM3S69XX_GPIO_DRIVE_2MA, \ - .pull = LM3S69XX_GPIO_PULL_UP, \ - .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ - } - -#define LM3S69XX_PIN_UART_RTS(port, idx) \ - { \ - .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ - .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ - .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ - .alternate = LM3S69XX_GPIO_AF_ENABLE, \ - .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ - .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ - .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ - .drive = LM3S69XX_GPIO_DRIVE_2MA, \ - .pull = LM3S69XX_GPIO_NO_PULL, \ - .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ - } - -#define LM3S69XX_PIN_UART_CTS(port, idx) \ - { \ - .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ - .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ - .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ - .alternate = LM3S69XX_GPIO_AF_ENABLE, \ - .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ - .dir = LM3S69XX_GPIO_DIRECTION_INPUT, \ - .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ - .drive = LM3S69XX_GPIO_DRIVE_2MA, \ - .pull = LM3S69XX_GPIO_PULL_UP, \ - .slr = LM3S69XX_GPIO_NO_SLEW_RATE_CONTROL \ - } - -#define LM3S69XX_PIN_LED(port, idx) \ - { \ - .pin_first = LM3S69XX_GPIO_PIN(port, idx), \ - .pin_last = LM3S69XX_GPIO_PIN(port, idx), \ - .digital = LM3S69XX_GPIO_DIGITAL_ENABLE, \ - .alternate = LM3S69XX_GPIO_AF_DISABLE, \ - .analog = LM3S69XX_GPIO_ANALOG_DISABLE, \ - .dir = LM3S69XX_GPIO_DIRECTION_OUTPUT, \ - .otype = LM3S69XX_GPIO_OTYPE_PUSH_PULL, \ - .drive = LM3S69XX_GPIO_DRIVE_8MA, \ - .pull = LM3S69XX_GPIO_NO_PULL, \ - .slr = LM3S69XX_GPIO_SLEW_RATE_CONTROL \ - } - -#define LM3S69XX_PIN_SSI_TX(port, idx) LM3S69XX_PIN_UART_TX(port, idx) -#define LM3S69XX_PIN_SSI_RX(port, idx) LM3S69XX_PIN_UART_RX(port, idx) - -#ifdef __cplusplus -extern "C" { -#endif - -void lm3s69xx_gpio_set_config(const lm3s69xx_gpio_config *config); -void lm3s69xx_gpio_set_config_array(const lm3s69xx_gpio_config *configs, unsigned int count); -void lm3s69xx_gpio_digital_enable(unsigned int pin, bool enable); -void lm3s69xx_gpio_analog_mode_select(unsigned int pin, bool enable); - -void lm3s69xx_gpio_set_pin(unsigned int pin, bool set); -bool lm3s69xx_gpio_get_pin(unsigned int pin); - -#ifdef __cplusplus -} -#endif - -#endif /* LIBBSP_ARM_LM3S69XX_IO_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h b/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h deleted file mode 100644 index 0b380c2ce2..0000000000 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/irq.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file - * - * @ingroup lm3s69xx_interrupt - * - * @brief Interrupt definitions. - */ - -/* - * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org> - * - * Copyright (c) 2011 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LM3S69XX_IRQ_H -#define LIBBSP_ARM_LM3S69XX_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <bspopts.h> - -/** - * @defgroup lm3s69xx_interrupt Interrupt Support - * - * @ingroup arm_lm3s69xx - * - * @brief Interrupt support. - */ - -#endif /* ASM */ - -#define LM3S69XX_IRQ_GPIO_PORT_A 0 -#define LM3S69XX_IRQ_GPIO_PORT_B 1 -#define LM3S69XX_IRQ_GPIO_PORT_C 2 -#define LM3S69XX_IRQ_GPIO_PORT_D 3 -#define LM3S69XX_IRQ_GPIO_PORT_E 4 -#define LM3S69XX_IRQ_UART_0 5 -#define LM3S69XX_IRQ_UART_1 6 -#define LM3S69XX_IRQ_SSI_0 7 -#define LM3S69XX_IRQ_I2C_0 8 -#define LM3S69XX_IRQ_PWM_FAULT 9 -#define LM3S69XX_IRQ_PWM_GENERATOR_0 10 -#define LM3S69XX_IRQ_PWM_GENERATOR_1 11 -#define LM3S69XX_IRQ_PWM_GENERATOR_2 12 -#define LM3S69XX_IRQ_QEI_0 13 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_0 14 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_1 15 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_2 16 -#define LM3S69XX_IRQ_ADC0_SEQUENCE_3 17 -#define LM3S69XX_IRQ_WATCHDOG_TIMER_0 18 -#define LM3S69XX_IRQ_TIMER_0_A 19 -#define LM3S69XX_IRQ_TIMER_0_B 20 -#define LM3S69XX_IRQ_TIMER_1_A 21 -#define LM3S69XX_IRQ_TIMER_1_B 22 -#define LM3S69XX_IRQ_TIMER_2_A 23 -#define LM3S69XX_IRQ_TIMER_2_B 24 -#define LM3S69XX_IRQ_ANALOG_COMPARATOR_0 25 -#define LM3S69XX_IRQ_ANALOG_COMPARATOR_1 26 -#define LM3S69XX_IRQ_SYSTEM_CONTROL 28 -#define LM3S69XX_IRQ_FLASH_MEMORY_CONTROL 29 -#define LM3S69XX_IRQ_GPIO_PORT_F 30 -#define LM3S69XX_IRQ_GPIO_PORT_G 31 -/* NOTE: lm3s3749 */ -#define LM3S69XX_IRQ_GPIO_PORT_H 32 -#define LM3S69XX_IRQ_UART_2 33 -/* NOTE: lm3s3749 */ -#define LM3S69XX_IRQ_SSI_1 34 -#define LM3S69XX_IRQ_TIMER_3_A 35 -#define LM3S69XX_IRQ_TIMER_3_B 36 -#define LM3S69XX_IRQ_I2C_1 37 - -/* NOTE: lm3s6965 */ -#define LM3S69XX_IRQ_QEI_1 38 -#define LM3S69XX_IRQ_ETHERNET_CONTROLLER 42 - -#define LM3S69XX_IRQ_HIBERNATION_MODULE 43 - -/* NOTE: lm3s3749 */ -#define LM3S69XX_IRQ_USB 44 -#define LM3S69XX_IRQ_PWM_GENERATOR_3 45 -#define LM3S69XX_IRQ_UDMA_SOFTWARE 46 -#define LM3S69XX_IRQ_UDMA_ERROR 47 - -#define LM3S69XX_IRQ_PRIORITY_VALUE_MIN 0 -#define LM3S69XX_IRQ_PRIORITY_VALUE_MAX 7 -#define LM3S69XX_IRQ_PRIORITY_COUNT (LM3S69XX_IRQ_PRIORITY_VALUE_MAX + 1) -#define LM3S69XX_IRQ_PRIORITY_HIGHEST LM3S69XX_IRQ_PRIORITY_VALUE_MIN -#define LM3S69XX_IRQ_PRIORITY_LOWEST LM3S69XX_IRQ_PRIORITY_VALUE_MAX - -#define BSP_INTERRUPT_VECTOR_MIN 0 -/* NOTE: for lm3s6965 - 43 */ -#define BSP_INTERRUPT_VECTOR_MAX 47 - -#endif /* LIBBSP_ARM_LM3S69XX_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h b/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h deleted file mode 100644 index 544fed55eb..0000000000 --- a/c/src/lib/libbsp/arm/lm3s69xx/include/uart.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @ingroup lm3s69xx_uart - * - * brief UART support. - */ - -/* - * Copyright (c) 2011 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LM3S69XX_UART_H -#define LIBBSP_ARM_LM3S69XX_UART_H - -#include <libchip/serial.h> - -/** - * defgroup lm3s69xx_uart UART Support - * - * @ingroup arm_lm3s69xx - * - * @brief UART support. - */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -extern const console_fns lm3s69xx_uart_fns; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LM3S69XX_UART_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/bsp.h b/c/src/lib/libbsp/arm/lpc176x/include/bsp.h deleted file mode 100644 index 6fb7c7cc57..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/bsp.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_BSP_H -#define LIBBSP_ARM_LPC176X_BSP_H - -#include <bspopts.h> - -#define LPC176X_PCLK ( LPC176X_CCLK / LPC176X_PCLKDIV ) -#define LPC176X_MPU_REGION_COUNT 8u - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT ( 29u << 3u ) -#define BSP_ARMV7M_SYSTICK_PRIORITY ( 30u << 3u ) -#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC176X_CCLK - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/default-initial-extension.h> - -/** Define operation count for Tests */ -#define OPERATION_COUNT 4 - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct rtems_bsdnet_ifconfig; - -/** - * @defgroup lpc176x LPC176X Support - * - * @ingroup bsp_arm - * - * @brief LPC176X support package. - * - * @{ - */ - -/** - * @brief Optimized idle task. - * - * This idle task sets the power mode to idle. This causes the processor - * clock to be stopped, while on-chip peripherals remain active. - * Any enabled interrupt from a peripheral or an external interrupt source - * will cause the processor to resume execution. - * - * To enable the idle task use the following in the system configuration: - * - * @code - * #include <bsp.h> - * - * #define CONFIGURE_INIT - * - * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread - * - * #include <confdefs.h> - * @endcode - */ -void*bsp_idle_thread( uintptr_t ignored ); - -#define BSP_CONSOLE_UART_BASE 0x4000C000U - -/** - * @brief Restarts the bsp with "addr" address - * @param addr Address used to restart the bsp - */ -void bsp_restart( const void *addr ); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_LPC176X_BSP_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/dma.h b/c/src/lib/libbsp/arm/lpc176x/include/dma.h deleted file mode 100644 index 65edfc4e30..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/dma.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x_dma - * - * @brief Direct memory access (DMA) support. - */ - -/* - * Copyright (c) 2008, 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_DMA_H -#define LIBBSP_ARM_LPC176X_DMA_H - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc176x_dma DMA Support - * - * @ingroup lpc176x - * - * @brief Direct memory access (DMA) support. - * - * @{ - */ - -/** - * @brief Initializes the general purpose DMA. - */ -void lpc176x_dma_initialize( void ); - -/** - * @brief Tries to obtain the DMA channel @a channel. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_ID Invalid channel number. - * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. - */ -rtems_status_code lpc176x_dma_channel_obtain( unsigned channel ); - -/** - * @brief Releases the DMA channel @a channel. - * - * You must have obtained this channel with lpc176x_dma_channel_obtain() - * previously. - * - * If the channel number @a channel is out of range nothing will happen. - */ -void lpc176x_dma_channel_release( unsigned channel ); - -/** - * @brief Disables the DMA channel @a channel. - * - * If @a force is @c false the channel will be halted and disabled when the - * channel is inactive otherwise it will be disabled immediately. - * - * If the channel number @a channel is out of range nothing will happen. - */ -void lpc176x_dma_channel_disable( - unsigned channel, - bool force -); - -rtems_status_code lpc176x_dma_copy_initialize( void ); - -rtems_status_code lpc176x_dma_copy_release( void ); - -rtems_status_code lpc176x_dma_copy( - unsigned channel, - const void *dest, - const void *src, - size_t n, - size_t width -); - -rtems_status_code lpc176x_dma_copy_wait( unsigned channel ); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_DMA_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/io.h b/c/src/lib/libbsp/arm/lpc176x/include/io.h deleted file mode 100644 index 4a8510479c..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/io.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file io.h - * - * @ingroup lpc176x - * - * @brief Input/output module methods definitions. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_IO_H -#define LIBBSP_ARM_LPC176X_IO_H - -#include <assert.h> -#include <rtems.h> -#include <bsp/io-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Sets pin to the selected function. - * - * @param pin The pin to set. - * @param function Defines the function to set. - */ -void lpc176x_pin_select( - uint32_t pin, - lpc176x_pin_function function -); - -/** - * @brief Sets pin to the selected mode. - * - * @param pin The pin to set. - * @param mode Defines the mode to set. - */ -void lpc176x_pin_set_mode( - const uint32_t pin, - const lpc176x_pin_mode mode -); - -/** - * @brief Enables the module power and clock. - * - * @param module Represents the module to be enabled. - * @param clock Represents the clock to set for this module. - * @return RTEMS_SUCCESFULL if the module was enabled succesfully. - */ -rtems_status_code lpc176x_module_enable( - lpc176x_module module, - lpc176x_module_clock clock -); - -/** - * @brief Checks if the current module is turned off and disables a module. - * - * @param module Represents the module to be disabled. - * @return RTEMS_SUCCESFULL if the module was disabled succesfully. - */ -rtems_status_code lpc176x_module_disable( lpc176x_module module ); - -/** - * @brief Checks if the current module is enabled or not. - * - * @param module Represents the module to be checked. - * @return TRUE if the module is enabled. - * FALSE otherwise. - */ -bool lpc176x_module_is_enabled( lpc176x_module module ); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_IO_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/irq.h b/c/src/lib/libbsp/arm/lpc176x/include/irq.h deleted file mode 100644 index 719608c8f7..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/irq.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief LPC176X interrupt definitions. - */ - -/* - * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_IRQ_H -#define LIBBSP_ARM_LPC176X_IRQ_H - -#ifndef ASM -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0U - -#define LPC176X_IRQ_WDT 0U -#define LPC176X_IRQ_TIMER_0 1U -#define LPC176X_IRQ_TIMER_1 2U -#define LPC176X_IRQ_TIMER_2 3U -#define LPC176X_IRQ_TIMER_3 4U -#define LPC176X_IRQ_UART_0 5U -#define LPC176X_IRQ_UART_1 6U -#define LPC176X_IRQ_UART_2 7U -#define LPC176X_IRQ_UART_3 8U -#define LPC176X_IRQ_PWM_1 9U -#define LPC176X_IRQ_PLL 16U -#define LPC176X_IRQ_RTC 17U -#define LPC176X_IRQ_EINT_0 18U -#define LPC176X_IRQ_EINT_1 19U -#define LPC176X_IRQ_EINT_2 20U -#define LPC176X_IRQ_EINT_3 21U -#define LPC176X_IRQ_ADC_0 22U -#define LPC176X_IRQ_BOD 23U -#define LPC176X_IRQ_USB 24U -#define LPC176X_IRQ_CAN 25U -#define LPC176X_IRQ_DMA 26U -#define LPC176X_IRQ_I2S 27U -#define LPC176X_IRQ_SD_MMC 29U -#define LPC176X_IRQ_MCPWM 30U -#define LPC176X_IRQ_QEI 31U -#define LPC176X_IRQ_PLL_ALT 32U -#define LPC176X_IRQ_USB_ACTIVITY 33U -#define LPC176X_IRQ_CAN_ACTIVITY 34U -#define LPC176X_IRQ_UART_4 35U -#define LPC176X_IRQ_GPIO 38U -#define LPC176X_IRQ_PWM 39U -#define LPC176X_IRQ_EEPROM 40U - -#define BSP_INTERRUPT_VECTOR_MAX 40 - -#define LPC176X_IRQ_PRIORITY_VALUE_MIN 0U - -#define LPC176X_IRQ_PRIORITY_VALUE_MAX 31U - -#define LPC176X_IRQ_PRIORITY_COUNT ( LPC176X_IRQ_PRIORITY_VALUE_MAX + 1U ) -#define LPC176X_IRQ_PRIORITY_HIGHEST LPC176X_IRQ_PRIORITY_VALUE_MIN -#define LPC176X_IRQ_PRIORITY_LOWEST LPC176X_IRQ_PRIORITY_VALUE_MAX - -#ifndef ASM - -/** - * @brief Sets the priority according to the current interruption. - * - * @param vector Interrupt to be attended. - * @param priority Interrupts priority. - */ -void lpc176x_irq_set_priority( - rtems_vector_number vector, - unsigned priority -); - -/** - * @brief Gets the priority number according to the current interruption. - * - * @param vector Interrupts to be attended. - * @return The priority number according to the current interruption. - */ -unsigned lpc176x_irq_get_priority( rtems_vector_number vector ); - -#endif /* ASM */ - -/** @} */ - -#endif /* LIBBSP_ARM_LPC176X_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc176x/include/lpc-clock-config.h deleted file mode 100644 index 3eef02152e..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/lpc-clock-config.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x - * - * @brief Clock driver configuration. - */ - -/* - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H -#define LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H - -#include <bsp.h> -#include <bsp/irq.h> -#include <bsp/lpc176x.h> -#include <bsp/io.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LPC_CLOCK_INTERRUPT LPC176X_IRQ_TIMER_0 -#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR -#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR -#define LPC_CLOCK_REFERENCE LPC176X_PCLK -#define LPC_CLOCK_MODULE_ENABLE() \ - lpc176x_module_enable( LPC176X_MODULE_TIMER_0, LPC176X_MODULE_PCLK_DEFAULT ) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/system-clocks.h b/c/src/lib/libbsp/arm/lpc176x/include/system-clocks.h deleted file mode 100644 index 26087ff3e9..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/system-clocks.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x_clocks - * - * @brief System clocks. - */ - -/* - * Copyright (c) 2008, 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H -#define LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H - -#include <bsp/lpc176x.h> -#include <bsp/timer-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc176x_clock System Clocks - * - * @ingroup lpc176x - * - * @brief System clocks. - * - * @{ - */ - -/** - * @brief Initializes the standard timer. - * - * This function uses Timer 1. - */ -void lpc176x_timer_initialize( void ); - -/** - * @brief Returns current standard timer value in CPU clocks. - * - * @return This function uses Timer 1. - */ -static inline unsigned lpc176x_get_timer1( void ) -{ - return LPC176X_T1TC; -} - -/** - * @brief Delay for @a us micro seconds. - * - * This function uses the standard timer and assumes that the CPU - * frequency is in whole MHz numbers. The delay value @a us will be - * converted to CPU ticks and there is no protection against integer - * overflows. - * - * This function uses Timer 1. - */ -void lpc176x_micro_seconds_delay( unsigned us ); - -/** - * @brief Returns the PLL output clock frequency in [Hz]. - * - * @return Returns zero in case of an unexpected PLL input frequency. - */ -unsigned lpc176x_pllclk( void ); - -/** - * @brief Returns the CPU clock frequency in [Hz]. - * - * @return Returns zero in case of an unexpected PLL input frequency. - */ -unsigned lpc176x_cclk( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/watchdog.h b/c/src/lib/libbsp/arm/lpc176x/include/watchdog.h deleted file mode 100644 index 8b5f033605..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/watchdog.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file watchdog.h - * - * @ingroup lpc176x - * - * @brief API of the Watchdog driver for the lpc176x bsp in RTEMS. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_H -#define LIBBSP_ARM_LPC176X_WATCHDOG_H - -#include <bsp/watchdog-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Checks if the watchdog was executed by software or not. Set when - * the watchdog timer times out, cleared by software. - * - * @return TRUE if the watchdog was executed. - * FALSE otherwise. - */ -bool lpc176x_been_reset_by_watchdog( void ); - -/** - * @brief Resets the watchdog timer. - */ -void lpc176x_watchdog_reset( void ); - -/** - * @brief Configures the watchdog's timer. - * - * @param tcount Timer's out value. - * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully. - */ -rtems_status_code lpc176x_watchdog_config( lpc176x_microseconds tcount ); - -/** - * @brief Configures the timer watchdog using interrupt. - * - * @param tcount Timer's out value. - * @param interrupt Interrupt to register. - * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully - * with interrupts. - */ -rtems_status_code lpc176x_watchdog_config_with_interrupt( - lpc176x_wd_isr_funct interrupt, - lpc176x_microseconds tcount -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h deleted file mode 100644 index e8c5d9ac12..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_BSP_H -#define LIBBSP_ARM_LPC24XX_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#define LPC24XX_PCLK (LPC24XX_CCLK / LPC24XX_PCLKDIV) - -#define LPC24XX_EMCCLK (LPC24XX_CCLK / LPC24XX_EMCCLKDIV) - -#define LPC24XX_MPU_REGION_COUNT 8 - -#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (29 << 3) - -#define BSP_ARMV7M_SYSTICK_PRIORITY (30 << 3) - -#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC24XX_CCLK - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct rtems_bsdnet_ifconfig; - -struct rtems_termios_device_context; - -/** - * @defgroup lpc24xx LPC24XX Support - * - * @ingroup bsp_arm - * - * @brief LPC24XX support package. - * - * @{ - */ - -/** - * @brief Network driver attach and detach function. - */ -int lpc_eth_attach_detach( - struct rtems_bsdnet_ifconfig *config, - int attaching -); - -/** - * @brief Standard network driver attach and detach function. - */ -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach - -/** - * @brief Standard network driver name. - */ -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" - -/** - * @brief Optimized idle task. - * - * This idle task sets the power mode to idle. This causes the processor clock - * to be stopped, while on-chip peripherals remain active. Any enabled - * interrupt from a peripheral or an external interrupt source will cause the - * processor to resume execution. - * - * To enable the idle task use the following in the system configuration: - * - * @code - * #include <bsp.h> - * - * #define CONFIGURE_INIT - * - * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread - * - * #include <confdefs.h> - * @endcode - */ -void *bsp_idle_thread(uintptr_t ignored); - -#ifdef ARM_MULTILIB_ARCH_V4 - #define BSP_CONSOLE_UART_BASE 0xe000c000 -#else - #define BSP_CONSOLE_UART_BASE 0x4000c000 -#endif - -void bsp_restart(void *addr); - -bool lpc24xx_uart_probe_1(struct rtems_termios_device_context *context); - -bool lpc24xx_uart_probe_2(struct rtems_termios_device_context *context); - -bool lpc24xx_uart_probe_3(struct rtems_termios_device_context *context); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_LPC24XX_BSP_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/dma.h b/c/src/lib/libbsp/arm/lpc24xx/include/dma.h deleted file mode 100644 index b2e6c3e665..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/dma.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx_dma - * - * @brief Direct memory access (DMA) support. - */ - -/* - * Copyright (c) 2008, 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_DMA_H -#define LIBBSP_ARM_LPC24XX_DMA_H - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc24xx_dma DMA Support - * - * @ingroup lpc24xx - * - * @brief Direct memory access (DMA) support. - * - * @{ - */ - -/** - * @brief Initializes the general purpose DMA. - */ -void lpc24xx_dma_initialize(void); - -/** - * @brief Tries to obtain the DMA channel @a channel. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_ID Invalid channel number. - * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. - */ -rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel); - -/** - * @brief Releases the DMA channel @a channel. - * - * You must have obtained this channel with lpc24xx_dma_channel_obtain() - * previously. - * - * If the channel number @a channel is out of range nothing will happen. - */ -void lpc24xx_dma_channel_release(unsigned channel); - -/** - * @brief Disables the DMA channel @a channel. - * - * If @a force is @c false the channel will be halted and disabled when the - * channel is inactive otherwise it will be disabled immediately. - * - * If the channel number @a channel is out of range nothing will happen. - */ -void lpc24xx_dma_channel_disable(unsigned channel, bool force); - -rtems_status_code lpc24xx_dma_copy_initialize(void); - -rtems_status_code lpc24xx_dma_copy_release(void); - -rtems_status_code lpc24xx_dma_copy( - unsigned channel, - void *dest, - const void *src, - size_t n, - size_t width -); - -rtems_status_code lpc24xx_dma_copy_wait(unsigned channel); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC24XX_DMA_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/i2c.h b/c/src/lib/libbsp/arm/lpc24xx/include/i2c.h deleted file mode 100644 index 42836ddfa8..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/i2c.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx_libi2c - * - * @brief LibI2C bus driver for the I2C modules. - */ - -/* - * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_I2C_H -#define LIBBSP_ARM_LPC24XX_I2C_H - -#include <rtems.h> -#include <rtems/libi2c.h> - -#include <bsp/io.h> -#include <bsp/lpc24xx.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc24xx_libi2c LPC24XX Bus Drivers - * - * @ingroup libi2c - * - * @brief LibI2C bus drivers for LPC24XX. - * - * @{ - */ - -typedef struct { - rtems_libi2c_bus_t bus; - volatile lpc24xx_i2c *regs; - size_t index; - const lpc24xx_pin_range *pins; - rtems_vector_number vector; - rtems_id state_update; - uint8_t *volatile data; - uint8_t *volatile end; -} lpc24xx_i2c_bus_entry; - -extern const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops; - -extern rtems_libi2c_bus_t *const lpc24xx_i2c_0; - -extern rtems_libi2c_bus_t *const lpc24xx_i2c_1; - -extern rtems_libi2c_bus_t *const lpc24xx_i2c_2; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC24XX_I2C_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/io.h b/c/src/lib/libbsp/arm/lpc24xx/include/io.h deleted file mode 100644 index 9f58ee8efb..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/io.h +++ /dev/null @@ -1,1154 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx_io - * - * @brief Input and output module. - */ - -/* - * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_IO_H -#define LIBBSP_ARM_LPC24XX_IO_H - -#include <rtems.h> - -#include <bsp/lpc24xx.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc24xx_io IO Support and Configuration - * - * @ingroup lpc24xx - * - * @brief Input and output module. - * - * @{ - */ - -#define LPC24XX_IO_PORT_COUNT 5U - -#define LPC24XX_IO_INDEX_MAX (LPC24XX_IO_PORT_COUNT * 32U) - -#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit)) - -#define LPC24XX_IO_PORT(index) ((index) >> 5U) - -#define LPC24XX_IO_PORT_BIT(index) ((index) & 0x1fU) - -typedef enum { - #ifdef ARM_MULTILIB_ARCH_V4 - LPC24XX_MODULE_ACF, - #endif - LPC24XX_MODULE_ADC, - #ifdef ARM_MULTILIB_ARCH_V4 - LPC24XX_MODULE_BAT_RAM, - #endif - LPC24XX_MODULE_CAN_0, - LPC24XX_MODULE_CAN_1, - LPC24XX_MODULE_DAC, - LPC24XX_MODULE_EMC, - LPC24XX_MODULE_ETHERNET, - LPC24XX_MODULE_GPDMA, - LPC24XX_MODULE_GPIO, - LPC24XX_MODULE_I2C_0, - LPC24XX_MODULE_I2C_1, - LPC24XX_MODULE_I2C_2, - LPC24XX_MODULE_I2S, - LPC24XX_MODULE_LCD, - LPC24XX_MODULE_MCI, - #ifdef ARM_MULTILIB_ARCH_V7M - LPC24XX_MODULE_MCPWM, - #endif - LPC24XX_MODULE_PCB, - LPC24XX_MODULE_PWM_0, - LPC24XX_MODULE_PWM_1, - #ifdef ARM_MULTILIB_ARCH_V7M - LPC24XX_MODULE_QEI, - #endif - LPC24XX_MODULE_RTC, - #ifdef ARM_MULTILIB_ARCH_V4 - LPC24XX_MODULE_SPI, - #endif - LPC24XX_MODULE_SSP_0, - LPC24XX_MODULE_SSP_1, - #ifdef ARM_MULTILIB_ARCH_V7M - LPC24XX_MODULE_SSP_2, - #endif - LPC24XX_MODULE_SYSCON, - LPC24XX_MODULE_TIMER_0, - LPC24XX_MODULE_TIMER_1, - LPC24XX_MODULE_TIMER_2, - LPC24XX_MODULE_TIMER_3, - LPC24XX_MODULE_UART_0, - LPC24XX_MODULE_UART_1, - LPC24XX_MODULE_UART_2, - LPC24XX_MODULE_UART_3, - #ifdef ARM_MULTILIB_ARCH_V7M - LPC24XX_MODULE_UART_4, - #endif - #ifdef ARM_MULTILIB_ARCH_V4 - LPC24XX_MODULE_WDT, - #endif - LPC24XX_MODULE_USB -} lpc24xx_module; - -#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_USB + 1) - -typedef enum { - LPC24XX_MODULE_PCLK_DEFAULT = 0x4U, - LPC24XX_MODULE_CCLK = 0x1U, - LPC24XX_MODULE_CCLK_2 = 0x2U, - LPC24XX_MODULE_CCLK_4 = 0x0U, - LPC24XX_MODULE_CCLK_6 = 0x3U, - LPC24XX_MODULE_CCLK_8 = 0x3U -} lpc24xx_module_clock; - -#define LPC24XX_MODULE_CLOCK_MASK 0x3U - -typedef enum { - LPC24XX_GPIO_DEFAULT = 0x0U, - LPC24XX_GPIO_RESISTOR_PULL_UP = 0x0U, - LPC24XX_GPIO_RESISTOR_NONE = 0x1U, - LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x2U, - LPC24XX_GPIO_INPUT = 0x0U, - #ifdef ARM_MULTILIB_ARCH_V7M - LPC17XX_GPIO_REPEATER = 0x3U, - LPC17XX_GPIO_HYSTERESIS = IOCON_HYS, - LPC17XX_GPIO_INPUT_INVERT = IOCON_INV, - LPC17XX_GPIO_FAST_MODE = IOCON_SLEW, - LPC17XX_GPIO_OPEN_DRAIN = IOCON_OD, - LPC17XX_GPIO_INPUT_FILTER = IOCON_FILTER, - #endif - LPC24XX_GPIO_OUTPUT = 0x8000U -} lpc24xx_gpio_settings; - -rtems_status_code lpc24xx_module_enable( - lpc24xx_module module, - lpc24xx_module_clock clock -); - -rtems_status_code lpc24xx_module_disable( - lpc24xx_module module -); - -bool lpc24xx_module_is_enabled(lpc24xx_module module); - -rtems_status_code lpc24xx_gpio_config( - unsigned index, - lpc24xx_gpio_settings settings -); - -static inline void lpc24xx_gpio_set(unsigned index) -{ - if (index <= LPC24XX_IO_INDEX_MAX) { - unsigned port = LPC24XX_IO_PORT(index); - unsigned bit = LPC24XX_IO_PORT_BIT(index); - - LPC24XX_FIO [port].set = 1U << bit; - } -} - -static inline void lpc24xx_gpio_clear(unsigned index) -{ - if (index <= LPC24XX_IO_INDEX_MAX) { - unsigned port = LPC24XX_IO_PORT(index); - unsigned bit = LPC24XX_IO_PORT_BIT(index); - - LPC24XX_FIO [port].clr = 1U << bit; - } -} - -static inline void lpc24xx_gpio_write(unsigned index, bool value) -{ - if (value) { - lpc24xx_gpio_set(index); - } else { - lpc24xx_gpio_clear(index); - } -} - -static inline bool lpc24xx_gpio_get(unsigned index) -{ - if (index <= LPC24XX_IO_INDEX_MAX) { - unsigned port = LPC24XX_IO_PORT(index); - unsigned bit = LPC24XX_IO_PORT_BIT(index); - - return (LPC24XX_FIO [port].pin & (1U << bit)) != 0; - } else { - return false; - } -} - -typedef enum { - /** - * @brief Sets the pin function. - */ - LPC24XX_PIN_SET_FUNCTION, - - /** - * @brief Checks if all pins are configured with the specified function. - */ - LPC24XX_PIN_CHECK_FUNCTION, - - /** - * @brief Configures the pins as input. - */ - LPC24XX_PIN_SET_INPUT, - - /** - * @brief Checks if all pins are configured as input. - */ - LPC24XX_PIN_CHECK_INPUT -} lpc24xx_pin_action; - -typedef union { - struct { - uint16_t port : 3; - uint16_t port_bit : 5; - uint16_t function : 3; - uint16_t type : 4; - uint16_t range : 1; - } fields; - uint16_t value; -} lpc24xx_pin_range; - -typedef enum { - LPC24XX_PIN_FUNCTION_00, - LPC24XX_PIN_FUNCTION_01, - LPC24XX_PIN_FUNCTION_10, - LPC24XX_PIN_FUNCTION_11 -} lpc24xx_pin_function; - -typedef enum { - LPC17XX_PIN_TYPE_DEFAULT, - LPC17XX_PIN_TYPE_ADC, - LPC17XX_PIN_TYPE_DAC, - LPC17XX_PIN_TYPE_I2C, - LPC17XX_PIN_TYPE_I2C_FAST_PLUS, - LPC17XX_PIN_TYPE_OPEN_DRAIN -} lpc17xx_pin_type; - -#ifdef ARM_MULTILIB_ARCH_V4 - #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f0, 0, 0 } } - #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f0, t, 0 } } - #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \ - { { p, i, f0, 0, 0 } }, { { p, j, f0, 0, 1 } } -#else - #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f1, 0, 0 } } - #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f1, t, 0 } } - #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \ - { { p, i, f1, 0, 0 } }, { { p, j, f1, 0, 1 } } -#endif - -#define LPC24XX_PIN_TERMINAL { { 0x7, 0x1f, 0x7, 0xf, 0x1 } } - -/** - * @brief Performs the @a action with the @a pins - * - * @code - * #include <assert.h> - * #include <bsp/io.h> - * - * void example(void) - * { - * static const lpc24xx_pin_range pins [] = { - * LPC24XX_PIN_I2S_RX_CLK_P0_4, - * LPC24XX_PIN_I2S_RX_WS_P0_5, - * LPC24XX_PIN_I2S_RX_SDA_P0_6, - * LPC24XX_PIN_I2S_TX_CLK_P0_7, - * LPC24XX_PIN_I2S_TX_WS_P0_8, - * LPC24XX_PIN_I2S_TX_SDA_P0_9, - * LPC24XX_PIN_TERMINAL - * }; - * rtems_status_code sc = RTEMS_SUCCESSFUL; - * - * sc = lpc24xx_module_enable(LPC24XX_MODULE_I2S, LPC24XX_MODULE_CCLK_8); - * assert(sc == RTEMS_SUCCESSFUL); - * sc = lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); - * assert(sc == RTEMS_SUCCESSFUL); - * } - * @endcode - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Check failed. - * @retval RTEMS_NOT_DEFINED Invalid action. - */ -rtems_status_code lpc24xx_pin_config( - const lpc24xx_pin_range *pins, - lpc24xx_pin_action action -); - -/** - * @brief Returns the first pin index of a pin range. - */ -static inline unsigned lpc24xx_pin_get_first_index( - const lpc24xx_pin_range *range -) -{ - return LPC24XX_IO_INDEX_BY_PORT(range->fields.port, range->fields.port_bit); -} - -/** - * @name ADC Pins - * - * @{ - */ - -#define LPC24XX_PIN_ADC_CHANNEL_0 \ - LPC24XX_PIN_WITH_TYPE(0, 23, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_1 \ - LPC24XX_PIN_WITH_TYPE(0, 24, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_2 \ - LPC24XX_PIN_WITH_TYPE(0, 25, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_3 \ - LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_4 \ - LPC24XX_PIN_WITH_TYPE(1, 30, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_5 \ - LPC24XX_PIN_WITH_TYPE(1, 31, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_6 \ - LPC24XX_PIN_WITH_TYPE(0, 12, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) -#define LPC24XX_PIN_ADC_CHANNEL_7 \ - LPC24XX_PIN_WITH_TYPE(0, 13, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC) - -/** @} */ - -/** - * @name CAN 0 Pins - * - * @{ - */ - -#define LPC24XX_PIN_CAN_0_RD_P0_0 \ - LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_CAN_0_RD_P0_21 \ - LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_11, 4) - -#define LPC24XX_PIN_CAN_0_TD_P0_1 \ - LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_CAN_0_TD_P0_22 \ - LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_11, 4) - -/** @} */ - -/** - * @name CAN 1 Pins - * - * @{ - */ - -#define LPC24XX_PIN_CAN_1_RD_P0_4 \ - LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_CAN_1_RD_P2_7 \ - LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_CAN_1_TD_P0_5 \ - LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_CAN_1_TD_P2_8 \ - LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** - * @name DAC Pins - * - * @{ - */ - -#define LPC24XX_PIN_DAC \ - LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_DAC) - -/** @} */ - -/** - * @name Ethernet Pins - * - * @{ - */ - -#define LPC24XX_PIN_ETHERNET_MII \ - LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_ETHERNET_RMII_0 \ - LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_ETHERNET_RMII_1 \ - LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_ETHERNET_RMII_2 \ - LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_ETHERNET_RMII_3 \ - LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** - * @name External Interrupt Pins - * - * @{ - */ - -#define LPC24XX_PIN_EINT_0 \ - LPC24XX_PIN(2, 10, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EINT_1 \ - LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EINT_2 \ - LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EINT_3 \ - LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** - * @name External Memory Controller (EMC) Pins - * - * @{ - */ - -#define LPC24XX_PIN_EMC_CS_0 \ - LPC24XX_PIN(4, 30, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CS_1 \ - LPC24XX_PIN(4, 31, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CS_2 \ - LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CS_3 \ - LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_DYCS_0 \ - LPC24XX_PIN(2, 20, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_DYCS_1 \ - LPC24XX_PIN(2, 21, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_DYCS_2 \ - LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_DYCS_3 \ - LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_OE \ - LPC24XX_PIN(4, 24, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_WE \ - LPC24XX_PIN(4, 25, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CAS \ - LPC24XX_PIN(2, 16, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_RAS \ - LPC24XX_PIN(2, 17, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_CLK_0 \ - LPC24XX_PIN(2, 18, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CLK_1 \ - LPC24XX_PIN(2, 19, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_CKE_0 \ - LPC24XX_PIN(2, 24, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CKE_1 \ - LPC24XX_PIN(2, 25, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CKE_2 \ - LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_CKE_3 \ - LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_DQM_0 \ - LPC24XX_PIN(2, 28, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_DQM_1 \ - LPC24XX_PIN(2, 29, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_DQM_2 \ - LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_DQM_3 \ - LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_BLS0 \ - LPC24XX_PIN(4, 26, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_BLS1 \ - LPC24XX_PIN(4, 27, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_BLS2 \ - LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_BLS3 \ - LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_D_0_15 \ - LPC24XX_PIN_RANGE(3, 0, 15, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_D_15_31 \ - LPC24XX_PIN_RANGE(3, 15, 31, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_D_0_31 \ - LPC24XX_PIN_RANGE(3, 0, 31, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_EMC_A_0_12 \ - LPC24XX_PIN_RANGE(4, 0, 12, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_13 \ - LPC24XX_PIN_RANGE(4, 0, 13, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_14 \ - LPC24XX_PIN_RANGE(4, 0, 14, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_15 \ - LPC24XX_PIN_RANGE(4, 0, 15, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_16 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN(4, 16, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_17 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 17, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_18 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 18, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_19 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 19, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_20 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 20, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_21 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 21, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_22 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 22, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_23 \ - LPC24XX_PIN_EMC_A_0_15, \ - LPC24XX_PIN_RANGE(4, 16, 23, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_24 \ - LPC24XX_PIN_EMC_A_0_23, \ - LPC24XX_PIN(5, 24, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_EMC_A_0_25 \ - LPC24XX_PIN_EMC_A_0_23, \ - LPC24XX_PIN_RANGE(5, 24, 25, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** - * @name I2C 0 Pins - * - * @{ - */ - -#define LPC24XX_PIN_I2C_0_SDA \ - LPC24XX_PIN_WITH_TYPE(0, 27, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_0_SCL \ - LPC24XX_PIN_WITH_TYPE(0, 28, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C) - -/** @} */ - -/** - * @name I2C 1 Pins - * - * @{ - */ - -#define LPC24XX_PIN_I2C_1_SDA_P0_0 \ - LPC24XX_PIN_WITH_TYPE(0, 0, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_1_SDA_P0_19 \ - LPC24XX_PIN_WITH_TYPE(0, 19, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_1_SDA_P2_14 \ - LPC24XX_PIN_WITH_TYPE(2, 14, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) - -#define LPC24XX_PIN_I2C_1_SCL_P0_1 \ - LPC24XX_PIN_WITH_TYPE(0, 1, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_1_SCL_P0_20 \ - LPC24XX_PIN_WITH_TYPE(0, 20, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_1_SCL_P2_15 \ - LPC24XX_PIN_WITH_TYPE(2, 15, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) - -/** @} */ - -/** - * @name I2C 2 Pins - * - * @{ - */ - -#define LPC24XX_PIN_I2C_2_SDA_P0_10 \ - LPC24XX_PIN_WITH_TYPE(0, 10, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_2_SDA_P2_30 \ - LPC24XX_PIN_WITH_TYPE(2, 30, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_2_SDA_P4_20 \ - LPC24XX_PIN_WITH_TYPE(4, 20, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) - -#define LPC24XX_PIN_I2C_2_SCL_P0_11 \ - LPC24XX_PIN_WITH_TYPE(0, 11, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_2_SCL_P2_31 \ - LPC24XX_PIN_WITH_TYPE(2, 31, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C) -#define LPC24XX_PIN_I2C_2_SCL_P4_21 \ - LPC24XX_PIN_WITH_TYPE(4, 21, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C) - -/** @} */ - -/** - * @name I2S Pins - * - * @{ - */ - -#define LPC24XX_PIN_I2S_RX_CLK_P0_4 \ - LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_I2S_RX_CLK_P0_23 \ - LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_I2S_RX_WS_P0_5 \ - LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_I2S_RX_WS_P0_24 \ - LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_I2S_RX_SDA_P0_6 \ - LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_I2S_RX_SDA_P0_25 \ - LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_I2S_TX_CLK_P0_7 \ - LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_I2S_TX_CLK_P2_11 \ - LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11, 3) - -#define LPC24XX_PIN_I2S_TX_WS_P0_8 \ - LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_I2S_TX_WS_P2_12 \ - LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11, 3) - -#define LPC24XX_PIN_I2S_TX_SDA_P0_9 \ - LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_I2S_TX_SDA_P2_13 \ - LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11, 3) - -/** @} */ - -/** - * @name LCD Pins - * - * @{ - */ - -#define LPC24XX_PIN_LCD_PWR \ - LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_LE \ - LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_DCLK \ - LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_FP \ - LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_ENAB_M \ - LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_LP \ - LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_CLKIN \ - LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 7) - -#define LPC24XX_PIN_LCD_VD_0_P0_4 \ - LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_0_P2_6 \ - LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 6) -#define LPC24XX_PIN_LCD_VD_1_P0_5 \ - LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_1_P2_7 \ - LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 6) -#define LPC24XX_PIN_LCD_VD_2_P2_8 \ - LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 6) -#define LPC24XX_PIN_LCD_VD_2_P4_28 \ - LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 7) -#define LPC24XX_PIN_LCD_VD_3_P2_9 \ - LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 6) -#define LPC24XX_PIN_LCD_VD_3_P2_12 \ - LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 5) -#define LPC24XX_PIN_LCD_VD_3_P4_29 \ - LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 7) -#define LPC24XX_PIN_LCD_VD_4_P2_6 \ - LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_VD_4_P2_12 \ - LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 4) -#define LPC24XX_PIN_LCD_VD_5_P2_7 \ - LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_VD_5_P2_13 \ - LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 5) -#define LPC24XX_PIN_LCD_VD_6_P1_20 \ - LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_6_P2_8 \ - LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_VD_6_P4_28 \ - LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 5) -#define LPC24XX_PIN_LCD_VD_7_P1_21 \ - LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_7_P2_9 \ - LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 7) -#define LPC24XX_PIN_LCD_VD_7_P4_29 \ - LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 5) -#define LPC24XX_PIN_LCD_VD_8_P0_6 \ - LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_8_P1_22 \ - LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_8_P2_12 \ - LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_9_P0_7 \ - LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_9_P1_23 \ - LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_9_P2_13 \ - LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_10_P1_20 \ - LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_10_P1_24 \ - LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_10_P4_28 \ - LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 6) -#define LPC24XX_PIN_LCD_VD_11_P1_21 \ - LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_11_P1_25 \ - LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_11_P4_29 \ - LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 6) -#define LPC24XX_PIN_LCD_VD_12_P1_22 \ - LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_12_P1_26 \ - LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_13_P1_23 \ - LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_13_P1_27 \ - LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_14_P1_24 \ - LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_14_P1_28 \ - LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_15_P1_25 \ - LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_15_P1_29 \ - LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 6) -#define LPC24XX_PIN_LCD_VD_16_P0_8 \ - LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_17_P0_9 \ - LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_18_P2_12 \ - LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_19_P2_13 \ - LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_20_P1_26 \ - LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_21_P1_27 \ - LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_22_P1_28 \ - LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 7) -#define LPC24XX_PIN_LCD_VD_23_P1_29 \ - LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 7) - -/** @} */ - -/** - * @name PWM 0 Pins - * - * @{ - */ - -#define LPC24XX_PIN_PWM_0_CHANNEL_1_P1_2 \ - LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CHANNEL_1_P3_16 \ - LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_PWM_0_CHANNEL_2_P1_3 \ - LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CHANNEL_2_P3_17 \ - LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_PWM_0_CHANNEL_3_P1_5 \ - LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CHANNEL_3_P3_18 \ - LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_PWM_0_CHANNEL_4_P1_6 \ - LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CHANNEL_4_P3_19 \ - LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_PWM_0_CHANNEL_5_P1_7 \ - LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CHANNEL_5_P3_20 \ - LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_PWM_0_CHANNEL_6_P1_11 \ - LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CHANNEL_6_P3_21 \ - LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_PWM_0_CAPTURE_0_P1_12 \ - LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_PWM_0_CAPTURE_0_P3_22 \ - LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10, 2) - -/** @} */ - -/** - * @name PWM 1 Pins - * - * @{ - */ - -#define LPC24XX_PIN_PWM_1_CHANNEL_1_P1_18 \ - LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CHANNEL_1_P2_0 \ - LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CHANNEL_1_P3_24 \ - LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_PWM_1_CHANNEL_2_P1_20 \ - LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CHANNEL_2_P2_1 \ - LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CHANNEL_2_P3_25 \ - LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_PWM_1_CHANNEL_3_P1_21 \ - LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CHANNEL_3_P2_2 \ - LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CHANNEL_3_P3_26 \ - LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_PWM_1_CHANNEL_4_P1_23 \ - LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CHANNEL_4_P2_3 \ - LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CHANNEL_4_P3_27 \ - LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_PWM_1_CHANNEL_5_P1_24 \ - LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CHANNEL_5_P2_4 \ - LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CHANNEL_5_P3_28 \ - LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_PWM_1_CHANNEL_6_P1_26 \ - LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CHANNEL_6_P2_5 \ - LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CHANNEL_6_P3_29 \ - LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11, 2) - -#define LPC24XX_PIN_PWM_1_CAPTURE_0_P1_28 \ - LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_PWM_1_CAPTURE_0_P2_7 \ - LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_PWM_1_CAPTURE_0_P3_23 \ - LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_PWM_1_CAPTURE_1_P1_29 \ - LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10, 2) - -/** @} */ - -#ifdef ARM_MULTILIB_ARCH_V4 - -/** - * @name SPI Pins - * - * @{ - */ - -#define LPC24XX_PIN_SPI_SCK \ - LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_11) -#define LPC24XX_PIN_SPI_SSEL \ - LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_11) -#define LPC24XX_PIN_SPI_MISO \ - LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_11) -#define LPC24XX_PIN_SPI_MOSI \ - LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_11) - -/** @} */ - -#endif /* ARM_MULTILIB_ARCH_V4 */ - -/** - * @name SSP 0 Pins - * - * @{ - */ - -#define LPC24XX_PIN_SSP_0_SCK_P0_15 \ - LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_0_SCK_P1_20 \ - LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11, 5) -#define LPC24XX_PIN_SSP_0_SCK_P2_22 \ - LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_SSP_0_SSEL_P0_16 \ - LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_0_SSEL_P1_21 \ - LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_SSP_0_SSEL_P2_23 \ - LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_SSP_0_MISO_P0_17 \ - LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_0_MISO_P1_23 \ - LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11, 5) -#define LPC24XX_PIN_SSP_0_MISO_P2_26 \ - LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_SSP_0_MOSI_P0_18 \ - LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_0_MOSI_P1_24 \ - LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11, 5) -#define LPC24XX_PIN_SSP_0_MOSI_P2_27 \ - LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11, 2) - -/** @} */ - -/** - * @name SSP 1 Pins - * - * @{ - */ - -#define LPC24XX_PIN_SSP_1_SCK_P0_6 \ - LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_SCK_P0_12 \ - LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_SCK_P4_20 \ - LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11, 3) - -#define LPC24XX_PIN_SSP_1_SSEL_P0_7 \ - LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_SSEL_P0_13 \ - LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11, 2) -#define LPC24XX_PIN_SSP_1_SSEL_P4_21 \ - LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11, 3) - -#define LPC24XX_PIN_SSP_1_MISO_P0_8 \ - LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_MISO_P0_14 \ - LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_MISO_P4_22 \ - LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11, 3) - -#define LPC24XX_PIN_SSP_1_MOSI_P0_9 \ - LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_MOSI_P1_31 \ - LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_SSP_1_MOSI_P4_23 \ - LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11, 3) - -/** @} */ - -#ifdef ARM_MULTILIB_ARCH_V7M - -/** - * @name SSP 2 Pins - * - * @{ - */ - -#define LPC24XX_PIN_SSP_2_SCK_P1_0 \ - LPC24XX_PIN(1, 0, LPC24XX_PIN_FUNCTION_00, 4) - -#define LPC24XX_PIN_SSP_2_SSEL_P1_8 \ - LPC24XX_PIN(1, 8, LPC24XX_PIN_FUNCTION_00, 4) - -#define LPC24XX_PIN_SSP_2_MISO_P1_4 \ - LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_00, 4) - -#define LPC24XX_PIN_SSP_2_MOSI_P1_1 \ - LPC24XX_PIN(1, 1, LPC24XX_PIN_FUNCTION_00, 4) - -/** @} */ - -#endif /* ARM_MULTILIB_ARCH_V7M */ - -/** - * @name UART 0 Pins - * - * @{ - */ - -#define LPC24XX_PIN_UART_0_TXD \ - LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01, 1) - -#define LPC24XX_PIN_UART_0_RXD \ - LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** - * @name UART 1 Pins - * - * @{ - */ - -#define LPC24XX_PIN_UART_1_TXD_P0_15 \ - LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_UART_1_TXD_P2_0 \ - LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_UART_1_TXD_P3_16 \ - LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11, 3) - -#define LPC24XX_PIN_UART_1_RXD_P0_16 \ - LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_UART_1_RXD_P2_1 \ - LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_UART_1_RXD_P3_17 \ - LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11, 3) - -/** @} */ - -/** - * @name UART 2 Pins - * - * @{ - */ - -#define LPC24XX_PIN_UART_2_TXD_P0_10 \ - LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_UART_2_TXD_P2_8 \ - LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_UART_2_TXD_P4_22 \ - LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10, 2) - -#define LPC24XX_PIN_UART_2_RXD_P0_11 \ - LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_UART_2_RXD_P2_9 \ - LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_UART_2_RXD_P4_23 \ - LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10, 2) - -/** @} */ - -/** - * @name UART 3 Pins - * - * @{ - */ - -#define LPC24XX_PIN_UART_3_TXD_P0_0 \ - LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_UART_3_TXD_P0_25 \ - LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_UART_3_TXD_P4_28 \ - LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11, 2) - -#define LPC24XX_PIN_UART_3_RXD_P0_1 \ - LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_UART_3_RXD_P0_26 \ - LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11, 3) -#define LPC24XX_PIN_UART_3_RXD_P4_29 \ - LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11, 2) - -/** @} */ - -#ifdef ARM_MULTILIB_ARCH_V7M - -/** - * @name UART 4 Pins - * - * @{ - */ - -#define LPC24XX_PIN_UART_4_TXD_P0_22 \ - LPC24XX_PIN(0, 22, LPC24XX_PIN_FUNCTION_00, 3) -#define LPC24XX_PIN_UART_4_TXD_P1_29 \ - LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_00, 5) -#define LPC24XX_PIN_UART_4_TXD_P5_4 \ - LPC24XX_PIN(5, 4, LPC24XX_PIN_FUNCTION_00, 4) - -#define LPC24XX_PIN_UART_4_RXD_P2_9 \ - LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_00, 3) -#define LPC24XX_PIN_UART_4_RXD_P5_3 \ - LPC24XX_PIN(5, 3, LPC24XX_PIN_FUNCTION_00, 4) - -#define LPC24XX_PIN_UART_4_OE_P0_21 \ - LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 3) - -#define LPC24XX_PIN_UART_4_SCLK_P0_21 \ - LPC24XX_PIN(0, 21, LPC24XX_PIN_FUNCTION_00, 5) - -#endif /* ARM_MULTILIB_ARCH_V7M */ - -/** @} */ - -/** - * @name USB Port 1 Pins - * - * @{ - */ - -#define LPC24XX_PIN_USB_D_PLUS_1\ - LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_D_MINUS_1\ - LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_UP_LED_1\ - LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_TX_E_1\ - LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_PPWR_1\ - LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_USB_TX_DP_1\ - LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_TX_DM_1\ - LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_RCV_1\ - LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_PWRD_1\ - LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_USB_RX_DP_1\ - LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_RX_DM_1\ - LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_LS_1\ - LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_HSTEN_1\ - LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_USB_SSPND_1\ - LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_INT_1\ - LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_OVRCR_1\ - LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10, 2) -#define LPC24XX_PIN_USB_SCL_1\ - LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_SDA_1 \ - LPC24XX_PIN_WITH_TYPE( \ - 1, 29, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_OPEN_DRAIN \ - ) -#define LPC24XX_PIN_USB_CONNECT_1\ - LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** - * @name USB Port 2 Pins - * - * @{ - */ - -#define LPC24XX_PIN_USB_PPWR_2\ - LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_UP_LED_2\ - LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_HSTEN_2\ - LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_CONNECT_2\ - LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 3) -#define LPC24XX_PIN_USB_D_PLUS_2\ - LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_PWRD_2\ - LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01, 1) -#define LPC24XX_PIN_USB_OVRCR_2\ - LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01, 1) - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC24XX_IO_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/irq.h b/c/src/lib/libbsp/arm/lpc24xx/include/irq.h deleted file mode 100644 index 0f0e473a0c..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/irq.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief LPC24XX interrupt definitions. - */ - -/* - * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_IRQ_H -#define LIBBSP_ARM_LPC24XX_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#ifdef ARM_MULTILIB_ARCH_V4 - #define LPC24XX_IRQ_WDT 0 - #define LPC24XX_IRQ_SOFTWARE 1 - #define LPC24XX_IRQ_ARM_CORE_0 2 - #define LPC24XX_IRQ_ARM_CORE_1 3 - #define LPC24XX_IRQ_TIMER_0 4 - #define LPC24XX_IRQ_TIMER_1 5 - #define LPC24XX_IRQ_UART_0 6 - #define LPC24XX_IRQ_UART_1 7 - #define LPC24XX_IRQ_PWM 8 - #define LPC24XX_IRQ_I2C_0 9 - #define LPC24XX_IRQ_SPI_SSP_0 10 - #define LPC24XX_IRQ_SSP_1 11 - #define LPC24XX_IRQ_PLL 12 - #define LPC24XX_IRQ_RTC 13 - #define LPC24XX_IRQ_EINT_0 14 - #define LPC24XX_IRQ_EINT_1 15 - #define LPC24XX_IRQ_EINT_2 16 - #define LPC24XX_IRQ_EINT_3 17 - #define LPC24XX_IRQ_ADC_0 18 - #define LPC24XX_IRQ_I2C_1 19 - #define LPC24XX_IRQ_BOD 20 - #define LPC24XX_IRQ_ETHERNET 21 - #define LPC24XX_IRQ_USB 22 - #define LPC24XX_IRQ_CAN 23 - #define LPC24XX_IRQ_SD_MMC 24 - #define LPC24XX_IRQ_DMA 25 - #define LPC24XX_IRQ_TIMER_2 26 - #define LPC24XX_IRQ_TIMER_3 27 - #define LPC24XX_IRQ_UART_2 28 - #define LPC24XX_IRQ_UART_3 29 - #define LPC24XX_IRQ_I2C_2 30 - #define LPC24XX_IRQ_I2S 31 - - #define BSP_INTERRUPT_VECTOR_MAX 31 -#else - #define LPC24XX_IRQ_WDT 0 - #define LPC24XX_IRQ_TIMER_0 1 - #define LPC24XX_IRQ_TIMER_1 2 - #define LPC24XX_IRQ_TIMER_2 3 - #define LPC24XX_IRQ_TIMER_3 4 - #define LPC24XX_IRQ_UART_0 5 - #define LPC24XX_IRQ_UART_1 6 - #define LPC24XX_IRQ_UART_2 7 - #define LPC24XX_IRQ_UART_3 8 - #define LPC24XX_IRQ_PWM_1 9 - #define LPC24XX_IRQ_I2C_0 10 - #define LPC24XX_IRQ_I2C_1 11 - #define LPC24XX_IRQ_I2C_2 12 - #define LPC24XX_IRQ_SPI_SSP_0 14 - #define LPC24XX_IRQ_SSP_1 15 - #define LPC24XX_IRQ_PLL 16 - #define LPC24XX_IRQ_RTC 17 - #define LPC24XX_IRQ_EINT_0 18 - #define LPC24XX_IRQ_EINT_1 19 - #define LPC24XX_IRQ_EINT_2 20 - #define LPC24XX_IRQ_EINT_3 21 - #define LPC24XX_IRQ_ADC_0 22 - #define LPC24XX_IRQ_BOD 23 - #define LPC24XX_IRQ_USB 24 - #define LPC24XX_IRQ_CAN 25 - #define LPC24XX_IRQ_DMA 26 - #define LPC24XX_IRQ_I2S 27 - #define LPC24XX_IRQ_ETHERNET 28 - #define LPC24XX_IRQ_SD_MMC 29 - #define LPC24XX_IRQ_MCPWM 30 - #define LPC24XX_IRQ_QEI 31 - #define LPC24XX_IRQ_PLL_ALT 32 - #define LPC24XX_IRQ_USB_ACTIVITY 33 - #define LPC24XX_IRQ_CAN_ACTIVITY 34 - #define LPC24XX_IRQ_UART_4 35 - #define LPC24XX_IRQ_SSP_2 36 - #define LPC24XX_IRQ_LCD 37 - #define LPC24XX_IRQ_GPIO 38 - #define LPC24XX_IRQ_PWM 39 - #define LPC24XX_IRQ_EEPROM 40 - - #define BSP_INTERRUPT_VECTOR_MAX 40 -#endif - -#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0 -#ifdef ARM_MULTILIB_ARCH_V4 - #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15 -#else - #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 31 -#endif -#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1) -#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN -#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX - -#ifndef ASM - -void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority); - -unsigned lpc24xx_irq_get_priority(rtems_vector_number vector); - -#endif /* ASM */ - -/** @} */ - -#endif /* LIBBSP_ARM_LPC24XX_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h deleted file mode 100644 index 5e6b469e0f..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx - * - * @brief Clock driver configuration. - */ - -/* - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H -#define LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H - -#include <bsp.h> -#include <bsp/irq.h> -#include <bsp/lpc24xx.h> -#include <bsp/io.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LPC_CLOCK_INTERRUPT LPC24XX_IRQ_TIMER_0 - -#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR - -#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR - -#define LPC_CLOCK_REFERENCE LPC24XX_PCLK - -#define LPC_CLOCK_MODULE_ENABLE() \ - lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_PCLK_DEFAULT) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC24XX_LPC_CLOCK_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc-ethernet-config.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc-ethernet-config.h deleted file mode 100644 index d24f132567..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc-ethernet-config.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx - * - * @brief Ethernet driver configuration. - */ - -/* - * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H -#define LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H - -#include <bsp.h> -#include <bsp/io.h> -#include <bsp/lpc24xx.h> - -#include <limits.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LPC_ETH_CONFIG_INTERRUPT LPC24XX_IRQ_ETHERNET - -#define LPC_ETH_CONFIG_REG_BASE MAC_BASE_ADDR - -#ifdef ARM_MULTILIB_ARCH_V4 - #define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 - #define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX 54 - - #define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 10 - #define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX 10 - - #define LPC_ETH_CONFIG_UNIT_MULTIPLE 1U - - #define LPC24XX_ETH_RAM_BEGIN 0x7fe00000U - #define LPC24XX_ETH_RAM_SIZE (16U * 1024U) -#else - #define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 - #define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX INT_MAX - - #define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 32 - #define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX INT_MAX - - #define LPC_ETH_CONFIG_UNIT_MULTIPLE 8U - - #define LPC_ETH_CONFIG_USE_TRANSMIT_DMA - - #define LPC24XX_ETH_RAM_BEGIN 0x20000000U - #define LPC24XX_ETH_RAM_SIZE (32U * 1024U) -#endif - -#ifdef LPC24XX_ETHERNET_RMII - #define LPC_ETH_CONFIG_RMII - - static void lpc_eth_config_module_enable(void) - { - static const lpc24xx_pin_range pins [] = { - #ifdef LPC24XX_PIN_ETHERNET_POWER_DOWN - LPC24XX_PIN_ETHERNET_POWER_DOWN, - #endif - LPC24XX_PIN_ETHERNET_RMII_0, - LPC24XX_PIN_ETHERNET_RMII_1, - LPC24XX_PIN_ETHERNET_RMII_2, - LPC24XX_PIN_ETHERNET_RMII_3, - LPC24XX_PIN_TERMINAL - }; - - lpc24xx_module_enable(LPC24XX_MODULE_ETHERNET, LPC24XX_MODULE_PCLK_DEFAULT); - lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); - - #ifdef LPC24XX_PIN_ETHERNET_POWER_DOWN - { - unsigned pin = lpc24xx_pin_get_first_index(&pins[0]); - - lpc24xx_gpio_config(pin, LPC24XX_GPIO_OUTPUT); - lpc24xx_gpio_set(pin); - } - #endif - } -#else - static void lpc_eth_config_module_enable(void) - { - static const lpc24xx_pin_range pins [] = { - LPC24XX_PIN_ETHERNET_MII, - LPC24XX_PIN_TERMINAL - }; - - lpc24xx_module_enable(LPC24XX_MODULE_ETHERNET, LPC24XX_MODULE_PCLK_DEFAULT); - lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION); - } -#endif - -static void lpc_eth_config_module_disable(void) -{ - lpc24xx_module_disable(LPC24XX_MODULE_ETHERNET); -} - -static char *lpc_eth_config_alloc_table_area(size_t size) -{ - if (size < LPC24XX_ETH_RAM_SIZE) { - return (char *) LPC24XX_ETH_RAM_BEGIN; - } else { - return NULL; - } -} - -static void lpc_eth_config_free_table_area(char *table_area) -{ - /* Do nothing */ -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC24XX_LPC_ETHERNET_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/system-clocks.h b/c/src/lib/libbsp/arm/lpc24xx/include/system-clocks.h deleted file mode 100644 index 564d12ec10..0000000000 --- a/c/src/lib/libbsp/arm/lpc24xx/include/system-clocks.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * @file - * - * @ingroup lpc24xx_clocks - * - * @brief System clocks. - */ - -/* - * Copyright (c) 2008, 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H -#define LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H - -#include <bsp/lpc24xx.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc24xx_clock System Clocks - * - * @ingroup lpc24xx - * - * @brief System clocks. - * - * @{ - */ - -/** - * @brief Initializes the standard timer. - * - * This function uses Timer 1. - */ -void lpc24xx_timer_initialize(void); - -/** - * @brief Returns current standard timer value in CPU clocks. - * - * This function uses Timer 1. - */ -static inline unsigned lpc24xx_timer(void) -{ - return T1TC; -} - -/** - * @brief Delay for @a us micro seconds. - * - * This function uses the standard timer and assumes that the CPU frequency is - * in whole MHz numbers. The delay value @a us will be converted to CPU ticks - * and there is no protection against integer overflows. - * - * This function uses Timer 1. - */ -void lpc24xx_micro_seconds_delay(unsigned us); - -/** - * @brief Returns the PLL output clock frequency in [Hz]. - * - * Returns zero in case of an unexpected PLL input frequency. - */ -unsigned lpc24xx_pllclk(void); - -/** - * @brief Returns the CPU clock frequency in [Hz]. - * - * Returns zero in case of an unexpected PLL input frequency. - */ -unsigned lpc24xx_cclk(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC24XX_SYSTEM_CLOCKS_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h deleted file mode 100644 index c36dafd43d..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h +++ /dev/null @@ -1,261 +0,0 @@ -/** - * @file - * - * @ingroup arm_lpc32xx - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC32XX_BSP_H -#define LIBBSP_ARM_LPC32XX_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <bsp/lpc32xx.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct rtems_bsdnet_ifconfig; - -/** - * @defgroup arm_lpc32xx LPC32XX Support - * - * @ingroup bsp_arm - * - * @brief LPC32XX support package. - * - * @{ - */ - -/** - * @brief Network driver attach and detach function. - */ -int lpc_eth_attach_detach( - struct rtems_bsdnet_ifconfig *config, - int attaching -); - -/** - * @brief Standard network driver attach and detach function. - */ -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach - -/** - * @brief Standard network driver name. - */ -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" - -/** - * @brief Optimized idle task. - * - * This idle task sets the power mode to idle. This causes the processor clock - * to be stopped, while on-chip peripherals remain active. Any enabled - * interrupt from a peripheral or an external interrupt source will cause the - * processor to resume execution. - * - * To enable the idle task use the following in the system configuration: - * - * @code - * #include <bsp.h> - * - * #define CONFIGURE_INIT - * - * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle - * - * #include <confdefs.h> - * @endcode - */ -void *lpc32xx_idle(uintptr_t ignored); - -#define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1) - -static inline unsigned lpc32xx_timer(void) -{ - volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; - - return timer->tc; -} - -static inline void lpc32xx_micro_seconds_delay(unsigned us) -{ - unsigned start = lpc32xx_timer(); - unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000); - unsigned elapsed = 0; - - do { - elapsed = lpc32xx_timer() - start; - } while (elapsed < delay); -} - -#if LPC32XX_OSCILLATOR_MAIN == 13000000U - #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \ - (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1)) - #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \ - (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0)) -#else - #error "unexpected main oscillator frequency" -#endif - -bool lpc32xx_start_pll_setup( - uint32_t hclkpll_ctrl, - uint32_t hclkdiv_ctrl, - bool force -); - -uint32_t lpc32xx_sysclk(void); - -uint32_t lpc32xx_hclkpll_clk(void); - -uint32_t lpc32xx_periph_clk(void); - -uint32_t lpc32xx_hclk(void); - -uint32_t lpc32xx_arm_clk(void); - -uint32_t lpc32xx_ddram_clk(void); - -typedef enum { - LPC32XX_NAND_CONTROLLER_NONE, - LPC32XX_NAND_CONTROLLER_MLC, - LPC32XX_NAND_CONTROLLER_SLC -} lpc32xx_nand_controller; - -void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller); - -void bsp_restart(void *addr); - -void *bsp_idle_thread(uintptr_t arg); - -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -#define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5 - -/** - * @brief Begin of magic zero area. - * - * A read from this area returns zero. Writes have no effect. - */ -extern uint32_t lpc32xx_magic_zero_begin []; - -/** - * @brief End of magic zero area. - * - * A read from this area returns zero. Writes have no effect. - */ -extern uint32_t lpc32xx_magic_zero_end []; - -/** - * @brief Size of magic zero area. - * - * A read from this area returns zero. Writes have no effect. - */ -extern uint32_t lpc32xx_magic_zero_size []; - -#ifdef LPC32XX_SCRATCH_AREA_SIZE - /** - * @rief Scratch area. - * - * The usage is application specific. - */ - extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE] - __attribute__((aligned(32))); -#endif - -#define LPC32XX_DO_STOP_GPDMA \ - do { \ - if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \ - if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \ - int i = 0; \ - for (i = 0; i < 8; ++i) { \ - lpc32xx.dma.channels [i].cfg = 0; \ - } \ - lpc32xx.dma.cfg &= ~DMA_CFG_E; \ - } \ - LPC32XX_DMACLK_CTRL = 0; \ - } \ - } while (0) - -#define LPC32XX_DO_STOP_ETHERNET \ - do { \ - if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \ - lpc32xx.eth.command = 0x38; \ - lpc32xx.eth.mac1 = 0xcf00; \ - lpc32xx.eth.mac1 = 0; \ - LPC32XX_MAC_CLK_CTRL = 0; \ - } \ - } while (0) - -#define LPC32XX_DO_STOP_USB \ - do { \ - if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \ - LPC32XX_OTG_CLK_CTRL = 0; \ - LPC32XX_USB_CTRL = 0x80000; \ - } \ - } while (0) - -#define LPC32XX_DO_RESTART(addr) \ - do { \ - ARM_SWITCH_REGISTERS; \ - rtems_interrupt_level level; \ - uint32_t ctrl = 0; \ - \ - rtems_interrupt_disable(level); \ - \ - arm_cp15_data_cache_test_and_clean(); \ - arm_cp15_instruction_cache_invalidate(); \ - \ - ctrl = arm_cp15_get_control(); \ - ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \ - arm_cp15_set_control(ctrl); \ - \ - __asm__ volatile ( \ - ARM_SWITCH_TO_ARM \ - "mov pc, %[addr]\n" \ - ARM_SWITCH_BACK \ - : ARM_SWITCH_OUTPUT \ - : [addr] "r" (addr) \ - ); \ - } while (0) - -/** @} */ - -/** - * @defgroup lpc LPC Support - * - * @ingroup arm_lpc32xx - * - * @brief LPC support package. - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_LPC32XX_BSP_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h b/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h deleted file mode 100644 index e0bf8349ac..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h +++ /dev/null @@ -1,269 +0,0 @@ -/** - * @file - * - * @ingroup lpc32xx_i2c - * - * @brief I2C support API. - */ - -/* - * Copyright (c) 2010 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC32XX_I2C_H -#define LIBBSP_ARM_LPC32XX_I2C_H - -#include <rtems.h> - -#include <bsp/lpc32xx.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc32xx_i2c I2C Support - * - * @ingroup arm_lpc32xx - * - * @brief I2C Support - * - * All writes and reads will be performed in master mode. Exclusive bus access - * will be assumed. - * - * @{ - */ - -/** - * @name I2C Clock Control Register (I2CCLK_CTRL) - * - * @{ - */ - -#define I2CCLK_1_EN BSP_BIT32(0) -#define I2CCLK_2_EN BSP_BIT32(1) -#define I2CCLK_1_HIGH_DRIVE BSP_BIT32(2) -#define I2CCLK_2_HIGH_DRIVE BSP_BIT32(3) -#define I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4) - -/** @} */ - -/** - * @name I2C TX Data FIFO Register (I2Cn_TX) - * - * @{ - */ - -#define I2C_TX_READ BSP_BIT32(0) -#define I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7) -#define I2C_TX_START BSP_BIT32(8) -#define I2C_TX_STOP BSP_BIT32(9) - -/** @} */ - -/** - * @name I2C Status Register (I2Cn_STAT) - * - * @{ - */ - -#define I2C_STAT_TDI BSP_BIT32(0) -#define I2C_STAT_AFI BSP_BIT32(1) -#define I2C_STAT_NAI BSP_BIT32(2) -#define I2C_STAT_DRMI BSP_BIT32(3) -#define I2C_STAT_DRSI BSP_BIT32(4) -#define I2C_STAT_ACTIVE BSP_BIT32(5) -#define I2C_STAT_SCL BSP_BIT32(6) -#define I2C_STAT_SDA BSP_BIT32(7) -#define I2C_STAT_RFF BSP_BIT32(8) -#define I2C_STAT_RFE BSP_BIT32(9) -#define I2C_STAT_TFF BSP_BIT32(10) -#define I2C_STAT_TFE BSP_BIT32(11) -#define I2C_STAT_TFFS BSP_BIT32(12) -#define I2C_STAT_TFES BSP_BIT32(13) - -/** @} */ - -/** - * @name I2C Control Register (I2Cn_CTRL) - * - * @{ - */ - -#define I2C_CTRL_TDIE BSP_BIT32(0) -#define I2C_CTRL_AFIE BSP_BIT32(1) -#define I2C_CTRL_NAIE BSP_BIT32(2) -#define I2C_CTRL_DRMIE BSP_BIT32(3) -#define I2C_CTRL_DRSIE BSP_BIT32(4) -#define I2C_CTRL_RFFIE BSP_BIT32(5) -#define I2C_CTRL_RFDAIE BSP_BIT32(6) -#define I2C_CTRL_TFFIO BSP_BIT32(7) -#define I2C_CTRL_RESET BSP_BIT32(8) -#define I2C_CTRL_SEVEN BSP_BIT32(9) -#define I2C_CTRL_TFFSIE BSP_BIT32(10) - -/** @} */ - -/** - * @brief Initializes the I2C module @a i2c. - * - * Valid @a clock_in_hz values are 100000 and 400000. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_ID Invalid @a i2c value. - * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. - */ -rtems_status_code lpc32xx_i2c_init( - volatile lpc32xx_i2c *i2c, - unsigned clock_in_hz -); - -/** - * @brief Resets the I2C module @a i2c. - */ -void lpc32xx_i2c_reset(volatile lpc32xx_i2c *i2c); - -/** - * @brief Sets the I2C module @a i2c clock. - * - * Valid @a clock_in_hz values are 100000 and 400000. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. - */ -rtems_status_code lpc32xx_i2c_clock( - volatile lpc32xx_i2c *i2c, - unsigned clock_in_hz -); - -/** - * @brief Starts a write transaction on the I2C module @a i2c. - * - * The address parameter @a addr must not contain the read/write bit. - * - * The error status may be delayed to the next - * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code lpc32xx_i2c_write_start( - volatile lpc32xx_i2c *i2c, - unsigned addr -); - -/** - * @brief Writes data via the I2C module @a i2c with optional stop. - * - * The error status may be delayed to the next - * lpc32xx_i2c_write_with_optional_stop() due to controller flaws. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code lpc32xx_i2c_write_with_optional_stop( - volatile lpc32xx_i2c *i2c, - const uint8_t *out, - size_t n, - bool stop -); - -/** - * @brief Starts a read transaction on the I2C module @a i2c. - * - * The address parameter @a addr must not contain the read/write bit. - * - * The error status may be delayed to the next - * lpc32xx_i2c_read_with_optional_stop() due to controller flaws. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code lpc32xx_i2c_read_start( - volatile lpc32xx_i2c *i2c, - unsigned addr -); - -/** - * @brief Reads data via the I2C module @a i2c with optional stop. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false. - */ -rtems_status_code lpc32xx_i2c_read_with_optional_stop( - volatile lpc32xx_i2c *i2c, - uint8_t *in, - size_t n, - bool stop -); - -/** - * @brief Writes and reads data via the I2C module @a i2c. - * - * This will be one bus transaction. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -rtems_status_code lpc32xx_i2c_write_and_read( - volatile lpc32xx_i2c *i2c, - unsigned addr, - const uint8_t *out, - size_t out_size, - uint8_t *in, - size_t in_size -); - -/** - * @brief Writes data via the I2C module @a i2c. - * - * This will be one bus transaction. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -static inline rtems_status_code lpc32xx_i2c_write( - volatile lpc32xx_i2c *i2c, - unsigned addr, - const uint8_t *out, - size_t out_size -) -{ - return lpc32xx_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0); -} - -/** - * @brief Reads data via the I2C module @a i2c. - * - * This will be one bus transaction. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_IO_ERROR Received a NACK from the slave. - */ -static inline rtems_status_code lpc32xx_i2c_read( - volatile lpc32xx_i2c *i2c, - unsigned addr, - uint8_t *in, - size_t in_size -) -{ - return lpc32xx_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC32XX_I2C_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/irq.h b/c/src/lib/libbsp/arm/lpc32xx/include/irq.h deleted file mode 100644 index fbb13b5262..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/irq.h +++ /dev/null @@ -1,179 +0,0 @@ -/** - * @file - * - * @ingroup lpc32xx_interrupt - * - * @brief Interrupt definitions. - */ - -/* - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC32XX_IRQ_H -#define LIBBSP_ARM_LPC32XX_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc32xx_interrupt Interrupt Support - * - * @ingroup arm_lpc32xx - * - * @ingroup bsp_interrupt - * - * @{ - */ - -#define LPC32XX_IRQ_INDEX(module, subindex) ((module) + (subindex)) - -#define LPC32XX_IRQ_MODULE_MIC 0U -#define LPC32XX_IRQ_MODULE_SIC_1 32U -#define LPC32XX_IRQ_MODULE_SIC_2 64U -#define LPC32XX_IRQ_MODULE_COUNT 3U - -/* MIC interrupts */ -#define LPC32XX_IRQ_SIC_1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 0) -#define LPC32XX_IRQ_SIC_2_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 1) -#define LPC32XX_IRQ_TIMER_4_OR_MCPWM LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 3) -#define LPC32XX_IRQ_TIMER_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 4) -#define LPC32XX_IRQ_TIMER_HS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 5) -#define LPC32XX_IRQ_WDG LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 6) -#define LPC32XX_IRQ_UART_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 7) -#define LPC32XX_IRQ_UART_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 8) -#define LPC32XX_IRQ_UART_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 9) -#define LPC32XX_IRQ_UART_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 10) -#define LPC32XX_IRQ_NAND_FLASH LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 11) -#define LPC32XX_IRQ_SDCARD_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 13) -#define LPC32XX_IRQ_LCD LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 14) -#define LPC32XX_IRQ_SDCARD_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 15) -#define LPC32XX_IRQ_TIMER_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 16) -#define LPC32XX_IRQ_TIMER_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 17) -#define LPC32XX_IRQ_TIMER_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 18) -#define LPC32XX_IRQ_TIMER_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 19) -#define LPC32XX_IRQ_SSP_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 20) -#define LPC32XX_IRQ_SSP_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 21) -#define LPC32XX_IRQ_I2S_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 22) -#define LPC32XX_IRQ_I2S_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 23) -#define LPC32XX_IRQ_UART_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 24) -#define LPC32XX_IRQ_UART_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 25) -#define LPC32XX_IRQ_UART_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 26) -#define LPC32XX_IRQ_TIMER_MS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 27) -#define LPC32XX_IRQ_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 28) -#define LPC32XX_IRQ_ETHERNET LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 29) -#define LPC32XX_IRQ_SIC_1_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 30) -#define LPC32XX_IRQ_SIC_2_FIQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_MIC, 31) - -/* SIC 1 interrupts */ -#define LPC32XX_IRQ_JTAG_COMM_TX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 1) -#define LPC32XX_IRQ_JTAG_COMM_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 2) -#define LPC32XX_IRQ_GPI_28 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 4) -#define LPC32XX_IRQ_TS_P LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 6) -#define LPC32XX_IRQ_TS_IRQ_OR_ADC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 7) -#define LPC32XX_IRQ_TS_AUX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 8) -#define LPC32XX_IRQ_SPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 12) -#define LPC32XX_IRQ_PLL_USB LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 13) -#define LPC32XX_IRQ_PLL_HCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 14) -#define LPC32XX_IRQ_PLL_397 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 17) -#define LPC32XX_IRQ_I2C_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 18) -#define LPC32XX_IRQ_I2C_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 19) -#define LPC32XX_IRQ_RTC LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 20) -#define LPC32XX_IRQ_KEYSCAN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 22) -#define LPC32XX_IRQ_SPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 23) -#define LPC32XX_IRQ_SW LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 24) -#define LPC32XX_IRQ_USB_OTG_TIMER LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 25) -#define LPC32XX_IRQ_USB_OTG_ATX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 26) -#define LPC32XX_IRQ_USB_HOST LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 27) -#define LPC32XX_IRQ_USB_DEV_DMA LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 28) -#define LPC32XX_IRQ_USB_DEV_LP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 29) -#define LPC32XX_IRQ_USB_DEV_HP LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 30) -#define LPC32XX_IRQ_USB_I2C LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_1, 31) - -/* SIC 2 interrupts */ -#define LPC32XX_IRQ_GPIO_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 0) -#define LPC32XX_IRQ_GPIO_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 1) -#define LPC32XX_IRQ_GPIO_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 2) -#define LPC32XX_IRQ_GPIO_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 3) -#define LPC32XX_IRQ_GPIO_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 4) -#define LPC32XX_IRQ_GPIO_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 5) -#define LPC32XX_IRQ_SPI_2_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 6) -#define LPC32XX_IRQ_UART_2_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 7) -#define LPC32XX_IRQ_GPIO_P0_P1_IRQ LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 8) -#define LPC32XX_IRQ_GPI_8 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 9) -#define LPC32XX_IRQ_GPI_9 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 10) -#define LPC32XX_IRQ_GPI_19 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 11) -#define LPC32XX_IRQ_UART_7_HCTS LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 12) -#define LPC32XX_IRQ_GPI_7 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 15) -#define LPC32XX_IRQ_SDIO LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 18) -#define LPC32XX_IRQ_UART_5_RX LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 19) -#define LPC32XX_IRQ_SPI_1_DATAIN LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 20) -#define LPC32XX_IRQ_GPI_0 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 22) -#define LPC32XX_IRQ_GPI_1 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 23) -#define LPC32XX_IRQ_GPI_2 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 24) -#define LPC32XX_IRQ_GPI_3 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 25) -#define LPC32XX_IRQ_GPI_4 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 26) -#define LPC32XX_IRQ_GPI_5 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 27) -#define LPC32XX_IRQ_GPI_6 LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 28) -#define LPC32XX_IRQ_SYSCLK LPC32XX_IRQ_INDEX(LPC32XX_IRQ_MODULE_SIC_2, 31) - -#define LPC32XX_IRQ_PRIORITY_VALUE_MIN 0U -#define LPC32XX_IRQ_PRIORITY_VALUE_MAX 15U -#define LPC32XX_IRQ_PRIORITY_COUNT (LPC32XX_IRQ_PRIORITY_VALUE_MAX + 1U) -#define LPC32XX_IRQ_PRIORITY_HIGHEST LPC32XX_IRQ_PRIORITY_VALUE_MIN -#define LPC32XX_IRQ_PRIORITY_LOWEST LPC32XX_IRQ_PRIORITY_VALUE_MAX - -#define BSP_INTERRUPT_VECTOR_MIN LPC32XX_IRQ_SIC_1_IRQ -#define BSP_INTERRUPT_VECTOR_MAX LPC32XX_IRQ_SYSCLK - -#define LPC32XX_IRQ_COUNT (BSP_INTERRUPT_VECTOR_MAX + 1) - -void lpc32xx_irq_set_priority(rtems_vector_number vector, unsigned priority); - -unsigned lpc32xx_irq_get_priority(rtems_vector_number vector); - -typedef enum { - LPC32XX_IRQ_ACTIVE_LOW_OR_FALLING_EDGE, - LPC32XX_IRQ_ACTIVE_HIGH_OR_RISING_EDGE -} lpc32xx_irq_activation_polarity; - -void lpc32xx_irq_set_activation_polarity(rtems_vector_number vector, lpc32xx_irq_activation_polarity activation_polarity); - -lpc32xx_irq_activation_polarity lpc32xx_irq_get_activation_polarity(rtems_vector_number vector); - -typedef enum { - LPC32XX_IRQ_LEVEL_SENSITIVE, - LPC32XX_IRQ_EDGE_SENSITIVE -} lpc32xx_irq_activation_type; - -void lpc32xx_irq_set_activation_type(rtems_vector_number vector, lpc32xx_irq_activation_type activation_type); - -lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector); - -void lpc32xx_set_exception_handler(Arm_symbolic_exception_name exception, void (*handler)(void)); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_LPC32XX_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h deleted file mode 100644 index 2b676b433f..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-clock-config.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * @file - * - * @ingroup lpc_clock - * - * @brief Clock driver configuration. - */ - -/* - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H -#define LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H - -#include <bsp.h> -#include <bsp/irq.h> -#include <bsp/lpc32xx.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc_clock Clock Support - * - * @ingroup lpc - * - * @brief Clock support. - * - * @{ - */ - -#define LPC_CLOCK_INTERRUPT LPC32XX_IRQ_TIMER_0 - -#define LPC_CLOCK_TIMER_BASE LPC32XX_BASE_TIMER_0 - -#define LPC_CLOCK_TIMECOUNTER_BASE LPC32XX_BASE_TIMER_1 - -#define LPC_CLOCK_REFERENCE LPC32XX_PERIPH_CLK - -#define LPC_CLOCK_MODULE_ENABLE() - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC32XX_LPC_CLOCK_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-ethernet-config.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc-ethernet-config.h deleted file mode 100644 index 53e9e8415d..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/lpc-ethernet-config.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @ingroup lpc_eth - * - * @brief Ethernet driver configuration. - */ - -/* - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H -#define LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H - -#include <stdlib.h> -#include <limits.h> - -#include <rtems.h> -#include <rtems/malloc.h> - -#include <bsp.h> -#include <bsp/lpc32xx.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc_eth Ethernet Support - * - * @ingroup lpc - * - * @brief Ethernet support. - * - * @{ - */ - -#define LPC_ETH_CONFIG_INTERRUPT LPC32XX_IRQ_ETHERNET - -#define LPC_ETH_CONFIG_REG_BASE LPC32XX_BASE_ETHERNET - -#define LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT 16 -#define LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX INT_MAX - -#define LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT 32 -#define LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX INT_MAX - -#define LPC_ETH_CONFIG_UNIT_MULTIPLE 8U - -#ifdef LPC32XX_ETHERNET_RMII - #define LPC_ETH_CONFIG_RMII - - static void lpc_eth_config_module_enable(void) - { - LPC32XX_MAC_CLK_CTRL = 0x1f; - } -#else - static void lpc_eth_config_module_enable(void) - { - LPC32XX_MAC_CLK_CTRL = 0x0f; - } -#endif - -static void lpc_eth_config_module_disable(void) -{ - LPC32XX_MAC_CLK_CTRL = 0; -} - -#define LPC_ETH_CONFIG_USE_TRANSMIT_DMA - -static char *lpc_eth_config_alloc_table_area(size_t size) -{ - return rtems_heap_allocate_aligned_with_boundary(size, 32, 0); -} - -static void lpc_eth_config_free_table_area(char *table_area) -{ - /* FIXME: Type */ - free(table_area, (int) 0xdeadbeef); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC32XX_LPC_ETHERNET_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h b/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h deleted file mode 100644 index 32352b5ed9..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/mmu.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * @file - * - * @ingroup lpc32xx_mmu - * - * @brief MMU support API. - */ - -/* - * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC32XX_MMU_H -#define LIBBSP_ARM_LPC32XX_MMU_H - -#include <libcpu/arm-cp15.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc32xx_mmu MMU Support - * - * @ingroup arm_lpc32xx - * - * @brief MMU support. - * - * @{ - */ - -#define LPC32XX_MMU_CLIENT_DOMAIN 15U - -#define LPC32XX_MMU_READ_ONLY \ - ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ - | ARM_MMU_SECT_DEFAULT) - -#define LPC32XX_MMU_READ_ONLY_CACHED \ - (LPC32XX_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B) - -#define LPC32XX_MMU_READ_WRITE \ - ((LPC32XX_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ - | ARM_MMU_SECT_AP_0 \ - | ARM_MMU_SECT_DEFAULT) - -#define LPC32XX_MMU_READ_WRITE_CACHED \ - (LPC32XX_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) - -/** - * @brief Sets the @a section_flags for the address range [@a begin, @a end). - * - * @return Previous section flags of the first modified entry. - */ -static inline uint32_t lpc32xx_set_translation_table_entries( - const void *begin, - const void *end, - uint32_t section_flags -) -{ - return arm_cp15_set_translation_table_entries(begin, end, section_flags); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC32XX_MMU_H */ diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/tm27.h b/c/src/lib/libbsp/arm/lpc32xx/include/tm27.h deleted file mode 100644 index 4cbc17a085..0000000000 --- a/c/src/lib/libbsp/arm/lpc32xx/include/tm27.h +++ /dev/null @@ -1,72 +0,0 @@ -/* @file - * - * @ingroup arm_lpc32xx - * - * @brief Implementations of interrupt mechanisms for Time Test 27 - */ - -/* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <assert.h> - -#include <rtems.h> - -#include <bsp/lpc32xx.h> -#include <bsp/irq.h> -#include <bsp/irq-generic.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -static void Install_tm27_vector(void (*handler)(rtems_vector_number)) -{ - rtems_status_code sc = RTEMS_SUCCESSFUL; - - LPC32XX_SW_INT = 0; - - sc = rtems_interrupt_handler_install( - LPC32XX_IRQ_SW, - "SW", - RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL - ); - assert(sc == RTEMS_SUCCESSFUL); -} - -static void Cause_tm27_intr(void) -{ - LPC32XX_SW_INT = 0x1; -} - -static void Clear_tm27_intr(void) -{ - LPC32XX_SW_INT = 0; - lpc32xx_irq_set_priority(LPC32XX_IRQ_SW, LPC32XX_IRQ_PRIORITY_LOWEST); -} - -static void Lower_tm27_intr(void) -{ - bsp_interrupt_vector_enable(LPC32XX_IRQ_SW); - lpc32xx_irq_set_priority(LPC32XX_IRQ_SW, LPC32XX_IRQ_PRIORITY_HIGHEST); -} - -#endif /* __tm27_h */ diff --git a/c/src/lib/libbsp/arm/nds/include/bsp.h b/c/src/lib/libbsp/arm/nds/include/bsp.h deleted file mode 100644 index 8b795e288f..0000000000 --- a/c/src/lib/libbsp/arm/nds/include/bsp.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2008 by Matthieu Bucchianeri <mbucchia@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE - */ - -#ifndef LIBBSP_ARM_NDS_H -#define LIBBSP_ARM_NDS_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -struct rtems_bsdnet_ifconfig; - -int rtems_wifi_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attach); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "dswifi0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_wifi_driver_attach - -#define RTC_DRIVER_TABLE_ENTRY \ - { rtc_initialize, NULL, NULL, NULL, NULL, NULL } -extern rtems_device_driver rtc_initialize (rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/arm/nds/irq/irq.h b/c/src/lib/libbsp/arm/nds/irq/irq.h deleted file mode 100644 index aeaccef298..0000000000 --- a/c/src/lib/libbsp/arm/nds/irq/irq.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE - */ - -#ifndef __BSP_IRQ_H_ -#define __BSP_IRQ_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -extern void BSP_rtems_irq_mngt_init (void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/bsp.h b/c/src/lib/libbsp/arm/raspberrypi/include/bsp.h deleted file mode 100644 index 5379b13511..0000000000 --- a/c/src/lib/libbsp/arm/raspberrypi/include/bsp.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * - * @ingroup arm_raspberrypi - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2013 Alan Cudmore - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE - * - */ - -#ifndef LIBBSP_ARM_RASPBERRYPI_BSP_H -#define LIBBSP_ARM_RASPBERRYPI_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/raspberrypi.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_GPIO_PIN_COUNT 32 -#define BSP_GPIO_PINS_PER_BANK 32 -#define BSP_GPIO_PINS_PER_SELECT_BANK 10 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_RASPBERRYPI_BSP_H */ - -/** - * @defgroup arm_raspberrypi Raspberry Pi Support - * - * @ingroup bsp_arm - * - * @brief Raspberry Pi support package - * - */ diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/i2c.h b/c/src/lib/libbsp/arm/raspberrypi/include/i2c.h deleted file mode 100644 index 4a8dbbf2ac..0000000000 --- a/c/src/lib/libbsp/arm/raspberrypi/include/i2c.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * @file i2c.h - * - * @ingroup raspberrypi_i2c - * - * @brief Raspberry Pi specific I2C definitions. - */ - -/* - * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_RASPBERRYPI_I2C_H -#define LIBBSP_ARM_RASPBERRYPI_I2C_H - -#include <dev/i2c/i2c.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @name I2C constants. - * - * @{ - */ - -/** - * @brief BSC controller core clock rate in Hz. - * - * This is set to 150 MHz as per the BCM2835 datasheet. - */ -#define BSC_CORE_CLK_HZ 150000000 - -/** - * @brief Default bus clock. - * - * This sets the bus with a 100 kHz clock speed. - */ -#define DEFAULT_BUS_CLOCK 100000 - -/** @} */ - -/** - * @name I2C directives. - * - * @{ - */ - -/** - * @brief Setups the Raspberry Pi GPIO header to activate the BSC I2C bus. - */ -extern void rpi_i2c_init(void); - -/** - * @brief Registers the Raspberry Pi BSC I2C bus with the - * Linux I2C User-Space API. - * - * @param[in] bus_path Path to the bus device file. - * @param[in] bus_clock Bus clock in Hz. - * - * @retval 0 Bus registered successfully. - * @retval <0 Could not register the bus. The return value is a negative - * errno code. - */ -extern int rpi_i2c_register_bus( - const char *bus_path, - uint32_t bus_clock -); - -/** - * @brief Setups the Raspberry Pi BSC I2C bus (located on the GPIO header) - * on the "/dev/i2c" device file, using the default bus clock. - * - * @retval 0 Bus configured and registered successfully. - * @retval <0 See @see rpi_i2c_register_bus(). - */ -static inline int rpi_setup_i2c_bus(void) -{ - rpi_i2c_init(); - - return rpi_i2c_register_bus("/dev/i2c", DEFAULT_BUS_CLOCK); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_RASPBERRYPI_I2C_H */ diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/irq.h b/c/src/lib/libbsp/arm/raspberrypi/include/irq.h deleted file mode 100644 index 8436c2dfc6..0000000000 --- a/c/src/lib/libbsp/arm/raspberrypi/include/irq.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * @ingroup raspberrypi_interrupt - * - * @brief Interrupt definitions. - */ - -/** - * Copyright (c) 2013 Alan Cudmore - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE - * - */ - -#ifndef LIBBSP_ARM_RASBPERRYPI_IRQ_H -#define LIBBSP_ARM_RASPBERRYPI_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -/** - * @defgroup raspberrypi_interrupt Interrrupt Support - * - * @ingroup arm_raspberrypi - * - * @brief Interrupt support. - */ - -#define BCM2835_INTC_TOTAL_IRQ 64 + 8 - - -#define BCM2835_IRQ_ID_AUX 29 -#define BCM2835_IRQ_ID_SPI_SLAVE 43 -#define BCM2835_IRQ_ID_PWA0 45 -#define BCM2835_IRQ_ID_PWA1 46 -#define BCM2835_IRQ_ID_SMI 48 -#define BCM2835_IRQ_ID_GPIO_0 49 -#define BCM2835_IRQ_ID_GPIO_1 50 -#define BCM2835_IRQ_ID_GPIO_2 51 -#define BCM2835_IRQ_ID_GPIO_3 52 -#define BCM2835_IRQ_ID_I2C 53 -#define BCM2835_IRQ_ID_SPI 54 -#define BCM2835_IRQ_ID_PCM 55 -#define BCM2835_IRQ_ID_UART 57 - - -#define BCM2835_IRQ_ID_TIMER_0 64 -#define BCM2835_IRQ_ID_MAILBOX_0 65 -#define BCM2835_IRQ_ID_DOORBELL_0 66 -#define BCM2835_IRQ_ID_DOORBELL_1 67 -#define BCM2835_IRQ_ID_GPU0_HALTED 68 - -#define BSP_INTERRUPT_VECTOR_MIN (0) -#define BSP_INTERRUPT_VECTOR_MAX (BCM2835_INTC_TOTAL_IRQ - 1) - -#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ) - - -void raspberrypi_set_exception_handler(Arm_symbolic_exception_name exception, - void (*handler)(void)); - -#endif /* ASM */ -#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/mmu.h b/c/src/lib/libbsp/arm/raspberrypi/include/mmu.h deleted file mode 100644 index 45ecc5a2a4..0000000000 --- a/c/src/lib/libbsp/arm/raspberrypi/include/mmu.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * - * @ingroup rapberrypi_mmu - * - * @brief MMU API. - */ - -/* - * Copyright (c) 2013 Alan Cudmore. - * based on work by: - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE - * - */ - -#ifndef LIBBSP_ARM_RASPBERRYPI_MMU_H -#define LIBBSP_ARM_RASPBERRYPI_MMU_H - -#include <libcpu/arm-cp15.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup raspberrypi_mmu MMU Support - * - * @ingroup arm_raspberrypi - * - * @brief MMU support. - * - * @{ - */ - -#define RASPBERRYPI_MMU_CLIENT_DOMAIN 15U - -#define RASPBERRYPI_MMU_READ_ONLY \ - ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ - | ARM_MMU_SECT_DEFAULT) - -#define RASPBERRYPI_MMU_READ_ONLY_CACHED \ - (RASPBERRYPI_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B) - -#define RASPBERRYPI_MMU_READ_WRITE \ - ((RASPBERRYPI_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ - | ARM_MMU_SECT_AP_0 \ - | ARM_MMU_SECT_DEFAULT) - -#define RASPBERRYPI_MMU_READ_WRITE_CACHED \ - (RASPBERRYPI_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B) - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_RASPBERRYPI_MMU_H */ diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/spi.h b/c/src/lib/libbsp/arm/raspberrypi/include/spi.h deleted file mode 100644 index 1bbbc6d2a4..0000000000 --- a/c/src/lib/libbsp/arm/raspberrypi/include/spi.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * @file spi.h - * - * @ingroup raspberrypi_spi - * - * @brief Raspberry Pi specific SPI definitions. - */ - -/* - * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_RASPBERRYPI_SPI_H -#define LIBBSP_ARM_RASPBERRYPI_SPI_H - -#include <rtems/libi2c.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @name SPI constants. - * - * @{ - */ - -/** - * @brief GPU processor core clock rate in Hz. - * - * Unless configured otherwise on a "config.txt" file present on the SD card - * the GPU defaults to 250 MHz. Currently only 250 MHz is supported. - */ - -/* TODO: It would be nice if this value could be probed at startup, probably - * using the Mailbox interface since the usual way of setting this on - * the hardware is through a "config.txt" text file on the SD card. - * Having this setup on the configure.ac script would require changing - * the same setting on two different places. */ -#define GPU_CORE_CLOCK_RATE 250000000 - -/** @} */ - -/** - * @name SPI directives. - * - * @{ - */ - -/** - * @brief Setups the Raspberry Pi SPI bus (located on the GPIO header) - * on the "/dev/spi" device file, and registers the bus on the - * libi2c API. - * - * @param[in] bidirectional_mode If TRUE sets the SPI bus to use 2-wire SPI, - * where the MOSI data line doubles as the - * slave out (SO) and slave in (SI) data lines. - * If FALSE the bus defaults to the usual - * 3-wire SPI, with 2 separate data lines - * (MOSI and MISO). - * - * @retval Returns libi2c bus number. - * @retval <0 Could not register the bus. See @see rtems_libi2c_register_bus(). - */ -extern int rpi_spi_init(bool bidirectional_mode); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_RASPBERRYPI_SPI_H */ diff --git a/c/src/lib/libbsp/arm/raspberrypi/include/usart.h b/c/src/lib/libbsp/arm/raspberrypi/include/usart.h deleted file mode 100644 index 491392b1f7..0000000000 --- a/c/src/lib/libbsp/arm/raspberrypi/include/usart.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file - * - * @ingroup raspberrypi_usart - * - * @brief USART support. - */ - - -/** - * @defgroup raspberrypi_usart USART Support - * - * @ingroup arm_raspberrypi - * - * @brief Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Support - */ - -/* - * Copyright (c) 2013 Alan Cudmore. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE - */ - -#ifndef LIBBSP_ARM_RASPBERRYPI_USART_H -#define LIBBSP_ARM_RASPBERRYPI_USART_H - -#include <libchip/serial.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define USART0_DEFAULT_BAUD 115000 - -extern const console_fns bcm2835_usart_fns; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_RASPBERRYPI_USART_H */ diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h b/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h deleted file mode 100644 index b670b1174d..0000000000 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * - * @ingroup arm_realview-pbx-a9 - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H -#define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_HAS_FRAME_BUFFER 1 - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_ARM_A9MPCORE_SCU_BASE 0x1f000000 - -#define BSP_ARM_GIC_CPUIF_BASE 0x1f000100 - -#define BSP_ARM_A9MPCORE_GT_BASE 0x1f000200 - -#define BSP_ARM_A9MPCORE_PT_BASE 0x1f000600 - -#define BSP_ARM_GIC_DIST_BASE 0x1f001000 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H */ - -/** - * @defgroup arm_realview-pbx-a9 Realview PBX-A9 - * - * @ingroup bsp_arm - * - * @brief Realview PBX-A9 support package - * - */ diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/include/irq.h b/c/src/lib/libbsp/arm/realview-pbx-a9/include/irq.h deleted file mode 100644 index 3c9790e9ef..0000000000 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/include/irq.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * @file - * - * @ingroup realview-pbx-a9_interrupt - * - * @brief Interrupt definitions. - */ - -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H -#define LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H - -#ifndef ASM - -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#include <bsp/arm-a9mpcore-irq.h> -#include <bsp/arm-gic-irq.h> - -/** - * @defgroup realview-pbx-a9_interrupt Interrrupt Support - * - * @ingroup arm_realview-pbx-a9 - * - * @brief Interrupt support. - */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define RVPBXA9_IRQ_WATCHDOG_0 32 -#define RVPBXA9_IRQ_SW_IRQ 33 -#define RVPBXA9_IRQ_TIMER_0_1 36 -#define RVPBXA9_IRQ_TIMER_2_3 37 -#define RVPBXA9_IRQ_GPIO_0 38 -#define RVPBXA9_IRQ_GPIO_1 39 -#define RVPBXA9_IRQ_GPIO_2 40 -#define RVPBXA9_IRQ_RTC 42 -#define RVPBXA9_IRQ_SSP 43 -#define RVPBXA9_IRQ_UART_0 44 -#define RVPBXA9_IRQ_UART_1 45 -#define RVPBXA9_IRQ_UART_2 46 -#define RVPBXA9_IRQ_UART_3 47 -#define RVPBXA9_IRQ_SCI 48 -#define RVPBXA9_IRQ_MCI_A 49 -#define RVPBXA9_IRQ_MCI_B 50 -#define RVPBXA9_IRQ_AACI 51 -#define RVPBXA9_IRQ_KMI0 52 -#define RVPBXA9_IRQ_KMI1 53 -#define RVPBXA9_IRQ_CLCD 55 -#define RVPBXA9_IRQ_DMAC 56 -#define RVPBXA9_IRQ_PWRFAIL 57 -#define RVPBXA9_IRQ_CF_INT 59 -#define RVPBXA9_IRQ_ETHERNET 60 -#define RVPBXA9_IRQ_USB 61 -#define RVPBXA9_IRQ_T1_INT_0 64 -#define RVPBXA9_IRQ_T1_INT_1 65 -#define RVPBXA9_IRQ_T1_INT_2 66 -#define RVPBXA9_IRQ_T1_INT_3 67 -#define RVPBXA9_IRQ_T1_INT_4 68 -#define RVPBXA9_IRQ_T1_INT_5 69 -#define RVPBXA9_IRQ_T1_INT_6 70 -#define RVPBXA9_IRQ_T1_INT_7 71 -#define RVPBXA9_IRQ_WATCHDOG_1 72 -#define RVPBXA9_IRQ_TIMER_4_5 73 -#define RVPBXA9_IRQ_TIMER_6_7 74 -#define RVPBXA9_IRQ_PCI_INTR 80 -#define RVPBXA9_IRQ_P_NMI 81 -#define RVPBXA9_IRQ_P_NINT_0 82 -#define RVPBXA9_IRQ_P_NINT_1 83 -#define RVPBXA9_IRQ_P_NINT_2 84 -#define RVPBXA9_IRQ_P_NINT_3 85 -#define RVPBXA9_IRQ_P_NINT_4 86 -#define RVPBXA9_IRQ_P_NINT_5 87 -#define RVPBXA9_IRQ_P_NINT_6 88 -#define RVPBXA9_IRQ_P_NINT_7 89 - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 89 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_REALVIEW_PBX_A9_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/include/tm27.h b/c/src/lib/libbsp/arm/realview-pbx-a9/include/tm27.h deleted file mode 100644 index c336d8d310..0000000000 --- a/c/src/lib/libbsp/arm/realview-pbx-a9/include/tm27.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - * @file - * - * @ingroup realview-pbx-a9_tm27 - * - * @brief GIC tmtests/tm27 support. - */ - - -/** - * @defgroup realview-pbx-a9_tm27 GIC tmtests/tm27 - * - * @ingroup arm_realview-pbx-a9 - * - * @brief GIC tmtests/tm27 support. - */ - -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/arm-gic-tm27.h> - -#endif /* __tm27_h */ diff --git a/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h b/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h deleted file mode 100644 index 51ed025c6f..0000000000 --- a/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h +++ /dev/null @@ -1,229 +0,0 @@ -/** - * @file - * @ingroup arm_rtl22xx - * @brief Global BSP definitions. - */ - -/* - * Philips LPC22XX/LPC21xx BSP header file - * - * by Ray,Xu <Rayx.cn@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. -*/ -#ifndef LIBBSP_ARM_RTL22XX_BSP_H -#define LIBBSP_ARM_RTL22XX_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -/** - * @defgroup arm_rtl22xx RTL22XX Support - * @ingroup bsp_arm - * @brief RTL22XX Support Package - * @{ - */ - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION - -#define CONFIG_ARM_CLK 60000000L -/* cclk=cco/(2*P) */ -/* cco = cclk*2*P */ - -/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ -#define LPC22xx_Fcclk CONFIG_ARM_CLK - -/* Fcco 156M~320Mhz*/ -/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ -#define LPC22xx_Fcclk CONFIG_ARM_CLK -#define LPC22xx_Fcco LPC22xx_Fcclk * 4 -/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */ -#define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1 - - - -/** - * @name Fcclk range: 10MHz ~ MCU allowed frequency - * @{ - */ - -#define Fcclk_MIN 10000000L -#define Fcclk_MAX 60000000L - -/** @} */ - -/** - * @name Fcco range: 156MHz ~ 320MHz - * @{ - */ - -#define Fcco_MIN 156000000L -#define Fcco_MAX 320000000L - -/** @} */ - -#define PLLFEED_DATA1 0xAA -#define PLLFEED_DATA2 0x55 - -/** - * @name PLL PLLCON register bit descriptions - * @{ - */ - -#define PLLCON_ENABLE_BIT 0 -#define PLLCON_CONNECT_BIT 1 - -/** @} */ - -/** - * @name PLL PLLSTAT register bit descriptions - * @{ - */ - -#define PLLSTAT_ENABLE_BIT 8 -#define PLLSTAT_CONNECT_BIT 9 -#define PLLSTAT_LOCK_BIT 10 - -/** @} */ - -/** - * @name PM Peripheral Type - * @{ - */ - -#define PC_TIMER0 0x2 -#define PC_TIMER1 0x4 -#define PC_UART0 0x8 -#define PC_UART1 0x10 -#define PC_PWM0 0x20 -#define PC_I2C 0x80 -#define PC_SPI0 0x100 -#define PC_RTC 0x200 - -/** @} */ - -/** @brief OSC [Hz] */ -#define FOSC 11059200 -/** @brief Core clk [Hz] */ -#define FCCLK FOSC<<2 - -/** - * @name System Configure - * @{ - */ - -/** @brief osc freq,10MHz~25MHz, change to a real one if needed */ -#define Fosc 11059200 -/** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */ -#define Fcclk (Fosc << 2) -/** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */ -#define Fcco (Fcclk <<2) -/** @brief VPB freq only(Fcclk / 4) 1~4 */ -#define Fpclk (Fcclk >>2) * 1 -/* This was M. That is a BAD BAD public constant. I renamed it to - * JOEL_M so it wouldn't conflict with user code. If you can find - * a better name, fix this. But nothing I found uses it. - */ - -/** @} */ - -#define JOEL_M Fcclk / Fosc -#define P_min Fcco_MIN / (2*Fcclk) + 1; -#define P_max Fcco_MAX / (2*Fcclk); - -#define UART_BPS 115200 - -/** @brief Time Precision time [us] */ -#define TIMER_PRECISION 10 - -/** @brief I2C Speed [bit/s] */ -#define I2CSPEED 20000 // 20 Kbit/s - -/** - * @name Uarts buffers size - * @{ - */ - -#define RXBUFSIZE 32 -#define TXBUFSIZE 32 - -/** @} */ - -/** @brief SPI Speed [bit/s] */ -#define SPISPEED 1500000 // 1.5 Mbit/s -/** @brief SPI EEPROM CS pin - * - * (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) - */ -#define SPI_CS_PIN P0_13 -#define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN - -/** - * @name Flash definition - * @{ - */ - -//#define RTL22XX_FLASH_SIZE (0x200000-RTL22XX_FLASH_BOOT) // Total area of Flash region in words 8 bit -/** @brief Total area of Flash region in words 8 bit */ -#define RTL22XX_FLASH_SIZE (0x80000-RTL22XX_FLASH_BOOT) -//#define RTL22XX_FLASH_SIZE (0x80000-RTL22XX_FLASH_BOOT) // Total area of Flash region in words 8 bit -#define RTL22XX_FLASH_BEGIN 0x80000000 -/** @brief First 0x8000 bytes reserved for boot loader etc. */ -#define RTL22XX_FLASH_BASE (RTL22XX_FLASH_BEGIN+RTL22XX_FLASH_BOOT) - -/** @} */ - -/** - * @name SRAM definition - * @{ - */ - -/** @brief Total area of Flash region in words 8 bit */ -#define SRAM_SIZE 0x100000 -/** @brief First 0x8000 bytes reserved for boot loader etc. */ -#define SRAM_BASE 0x81000000 - -/** @} */ - -/** @brief CS8900A definition */ -#define CS8900A_BASE 0x82000000 -/** @brief RTL8019AS definition */ -#define RTL8019AS_BASE 0x82000000 - -struct rtems_bsdnet_ifconfig; -int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attaching); - -/** - * @name Network driver configuration - * @{ - */ - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach - -/** @} */ - -/* - * Prototypes for methods used across file boundaries in the BSP. - */ -extern void UART0_Ini(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSP_H */ diff --git a/c/src/lib/libbsp/arm/shared/comm/uart.h b/c/src/lib/libbsp/arm/shared/comm/uart.h deleted file mode 100644 index 2f69d57a74..0000000000 --- a/c/src/lib/libbsp/arm/shared/comm/uart.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * @file - * - * @ingroup arm_comm - * - * @brief UART Support - */ - -/* - * This software is Copyright (C) 1998 by T.sqware - all rights limited - * It is provided in to the public domain "as is", can be freely modified - * as far as this copyight notice is kept unchanged, but does not imply - * an endorsement by T.sqware of the product in which it is included. - * - * Copyright (c) Canon Research France SA.] - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _BSPUART_H -#define _BSPUART_H - -void BSP_uart_init(int uart, int baud, int hwFlow); -void BSP_uart_set_baud(int aurt, int baud); -void BSP_uart_intr_ctrl(int uart, int cmd); -void BSP_uart_throttle(int uart); -void BSP_uart_unthrottle(int uart); -int BSP_uart_polled_status(int uart); -void BSP_uart_polled_write(int uart, int val); -int BSP_uart_polled_read(int uart); -void BSP_uart_termios_set(int uart, void *ttyp); -int BSP_uart_termios_write_com1(int minor, const char *buf, int len); -int BSP_uart_termios_write_com2(int minor, const char *buf, int len); -void BSP_uart_termios_isr_com1(); -void BSP_uart_termios_isr_com2(); -void BSP_uart_dbgisr_com1(void); -void BSP_uart_dbgisr_com2(void); -extern unsigned BSP_poll_char_via_serial(void); -extern void BSP_output_char_via_serial(int val); -extern int BSPConsolePort; -extern int BSPBaseBaud; -/* - * Command values for BSP_uart_intr_ctrl(), - * values are strange in order to catch errors - * with assert - */ -#define BSP_UART_INTR_CTRL_DISABLE (0) -#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ -#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ -#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ - -/* Return values for uart_polled_status() */ -#define BSP_UART_STATUS_ERROR (-1) /* No character */ -#define BSP_UART_STATUS_NOCHAR (0) /* No character */ -#define BSP_UART_STATUS_CHAR (1) /* Character present */ -#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ - -/* PC UART definitions */ -#define BSP_UART_COM1 (0) -#define BSP_UART_COM2 (1) - -/* - * Base IO for UART - */ - -#define COM1_BASE_IO 0x3F8 -#define COM2_BASE_IO 0x2F8 - -/* - * Offsets from base - */ - -/* DLAB 0 */ -#define RBR RSRBR /* Rx Buffer Register (read) */ -#define THR RSTHR /* Tx Buffer Register (write) */ -#define IER RSIER /* Interrupt Enable Register */ - -/* DLAB X */ -#define IIR RSIIR /* Interrupt Ident Register (read) */ -#define FCR RSFCR /* FIFO Control Register (write) */ -#define LCR RSLCR /* Line Control Register */ -#define LSR RSLSR /* Line Status Register */ - -/* DLAB 1 */ -#define DLL RSDLL /* Divisor Latch, LSB */ -#define DLM RSDLH /* Divisor Latch, MSB */ - -/* Uart control */ -#define CNT RSCNT /* General Control register */ - -/* - * define bit for CNT - */ -#define UART_ENABLE 1 -#define PAD_ENABLE 2 - -/* - * Interrupt source definition via IIR - */ -#define NO_MORE_INTR 1 -#define TRANSMITTER_HODING_REGISTER_EMPTY 2 -#define RECEIVER_DATA_AVAIL 4 -#define RECEIVER_ERROR 6 -#define CHARACTER_TIMEOUT_INDICATION 12 - -/* - * Bits definition of IER - */ -#define RECEIVE_ENABLE 0x1 -#define TRANSMIT_ENABLE 0x2 -#define RECEIVER_LINE_ST_ENABLE 0x4 -#define INTERRUPT_DISABLE 0x0 - -/* - * Bits definition of the Line Status Register (LSR) - */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* Transmitter Holding Register Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define ERFIFO 0x80 /* Error receive Fifo */ - -/* - * Bits definition of the Line Control Register (LCR) - */ -#define CHR_5_BITS 0 -#define CHR_6_BITS 1 -#define CHR_7_BITS 2 -#define CHR_8_BITS 3 - -#define WL 0x03 /* Word length mask */ -#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ -#define PEN 0x08 /* Parity Enabled */ -#define EPS 0x10 /* Even Parity Select, otherwise Odd */ -#define SP 0x20 /* Stick Parity */ -#define BCB 0x40 /* Break Control Bit */ -#define DLAB 0x80 /* Enable Divisor Latch Access */ - -/* - * Bits definition of the FIFO Control Register : WD16C552 or NS16550 - */ - -#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ -#define FIFO_EN 0x01 /* Enable the FIFO */ -#define XMIT_RESET 0x04 /* Transmit FIFO Reset */ -#define RCV_RESET 0x02 /* Receive FIFO Reset */ -#define FCR3 0x08 /* do not understand manual! */ - -#define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */ -#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */ -#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */ -#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 14 byte */ -#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ - -#endif /* _BSPUART_H */ diff --git a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h deleted file mode 100644 index a4df81ab71..0000000000 --- a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h +++ /dev/null @@ -1,157 +0,0 @@ -/** - * @file - * - * @ingroup arm_linker - * - * @brief Symbols defined in linker command base file. - */ - -/* - * Copyright (c) 2008-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H -#define LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup arm_linker Linker Support - * - * @ingroup arm_shared - * - * @brief Linker support. - * - * @{ - */ - -#ifndef ASM - #define LINKER_SYMBOL(sym) extern char sym []; -#else - #define LINKER_SYMBOL(sym) .extern sym -#endif - -LINKER_SYMBOL(bsp_stack_irq_begin) -LINKER_SYMBOL(bsp_stack_irq_end) -LINKER_SYMBOL(bsp_stack_irq_size) - -LINKER_SYMBOL(bsp_stack_fiq_begin) -LINKER_SYMBOL(bsp_stack_fiq_end) -LINKER_SYMBOL(bsp_stack_irq_size) - -LINKER_SYMBOL(bsp_stack_abt_begin) -LINKER_SYMBOL(bsp_stack_abt_end) -LINKER_SYMBOL(bsp_stack_abt_size) - -LINKER_SYMBOL(bsp_stack_und_begin) -LINKER_SYMBOL(bsp_stack_und_end) -LINKER_SYMBOL(bsp_stack_und_size) - -LINKER_SYMBOL(bsp_stack_svc_begin) -LINKER_SYMBOL(bsp_stack_svc_end) -LINKER_SYMBOL(bsp_stack_svc_size) - -LINKER_SYMBOL(bsp_section_start_begin) -LINKER_SYMBOL(bsp_section_start_end) -LINKER_SYMBOL(bsp_section_start_size) - -LINKER_SYMBOL(bsp_section_vector_begin) -LINKER_SYMBOL(bsp_section_vector_end) -LINKER_SYMBOL(bsp_section_vector_size) - -LINKER_SYMBOL(bsp_section_text_begin) -LINKER_SYMBOL(bsp_section_text_end) -LINKER_SYMBOL(bsp_section_text_size) -LINKER_SYMBOL(bsp_section_text_load_begin) -LINKER_SYMBOL(bsp_section_text_load_end) - -LINKER_SYMBOL(bsp_section_rodata_begin) -LINKER_SYMBOL(bsp_section_rodata_end) -LINKER_SYMBOL(bsp_section_rodata_size) -LINKER_SYMBOL(bsp_section_rodata_load_begin) -LINKER_SYMBOL(bsp_section_rodata_load_end) - -LINKER_SYMBOL(bsp_section_data_begin) -LINKER_SYMBOL(bsp_section_data_end) -LINKER_SYMBOL(bsp_section_data_size) -LINKER_SYMBOL(bsp_section_data_load_begin) -LINKER_SYMBOL(bsp_section_data_load_end) - -LINKER_SYMBOL(bsp_section_fast_text_begin) -LINKER_SYMBOL(bsp_section_fast_text_end) -LINKER_SYMBOL(bsp_section_fast_text_size) -LINKER_SYMBOL(bsp_section_fast_text_load_begin) -LINKER_SYMBOL(bsp_section_fast_text_load_end) - -LINKER_SYMBOL(bsp_section_fast_data_begin) -LINKER_SYMBOL(bsp_section_fast_data_end) -LINKER_SYMBOL(bsp_section_fast_data_size) -LINKER_SYMBOL(bsp_section_fast_data_load_begin) -LINKER_SYMBOL(bsp_section_fast_data_load_end) - -LINKER_SYMBOL(bsp_section_bss_begin) -LINKER_SYMBOL(bsp_section_bss_end) -LINKER_SYMBOL(bsp_section_bss_size) - -LINKER_SYMBOL(bsp_section_work_begin) -LINKER_SYMBOL(bsp_section_work_end) -LINKER_SYMBOL(bsp_section_work_size) - -LINKER_SYMBOL(bsp_section_stack_begin) -LINKER_SYMBOL(bsp_section_stack_end) -LINKER_SYMBOL(bsp_section_stack_size) - -LINKER_SYMBOL(bsp_section_nocache_begin) -LINKER_SYMBOL(bsp_section_nocache_end) -LINKER_SYMBOL(bsp_section_nocache_size) -LINKER_SYMBOL(bsp_section_nocache_load_begin) -LINKER_SYMBOL(bsp_section_nocache_load_end) - -LINKER_SYMBOL(bsp_section_nocachenoload_begin) -LINKER_SYMBOL(bsp_section_nocachenoload_end) -LINKER_SYMBOL(bsp_section_nocachenoload_size) - -LINKER_SYMBOL(bsp_section_nocacheheap_begin) -LINKER_SYMBOL(bsp_section_nocacheheap_end) -LINKER_SYMBOL(bsp_section_nocacheheap_size) - -LINKER_SYMBOL(bsp_vector_table_begin) -LINKER_SYMBOL(bsp_vector_table_end) -LINKER_SYMBOL(bsp_vector_table_size) - -LINKER_SYMBOL(bsp_start_vector_table_begin) -LINKER_SYMBOL(bsp_start_vector_table_end) -LINKER_SYMBOL(bsp_start_vector_table_size) - -LINKER_SYMBOL(bsp_translation_table_base) -LINKER_SYMBOL(bsp_translation_table_end) - -#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) - -#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) - -#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) - -#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) - -LINKER_SYMBOL(bsp_processor_count) - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/arm/shared/include/start.h b/c/src/lib/libbsp/arm/shared/include/start.h deleted file mode 100644 index 9df6df4f3f..0000000000 --- a/c/src/lib/libbsp/arm/shared/include/start.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * @file - * - * @ingroup arm_start - * - * @brief ARM system low level start. - */ - -/* - * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_SHARED_START_H -#define LIBBSP_ARM_SHARED_START_H - -#include <string.h> - -#include <bsp/linker-symbols.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup arm_start System Start - * - * @ingroup arm_shared - * - * @brief ARM system low level start. - * - * @{ - */ - -#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) - -#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) - -/** -* @brief System start entry. -*/ -void _start(void); - -/** -* @brief Start entry hook 0. -* -* This hook will be called from the start entry code after all modes and -* stack pointers are initialized but before the copying of the exception -* vectors. -*/ -void bsp_start_hook_0(void); - -/** -* @brief Start entry hook 1. -* -* This hook will be called from the start entry code after copying of the -* exception vectors but before the call to boot_card(). -*/ -void bsp_start_hook_1(void); - -/** - * @brief Similar to standard memcpy(). - * - * The memory areas must be word aligned. Copy code will be executed from the - * stack. If @a dest equals @a src nothing will be copied. - */ -void bsp_start_memcpy(int *dest, const int *src, size_t n); - -/** - * @brief ARM entry point to bsp_start_memcpy(). - */ -void bsp_start_memcpy_arm(int *dest, const int *src, size_t n); - -/** - * @brief Copies all standard sections from the load to the runtime area. - */ -BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections(void) -{ - /* Copy .text section */ - bsp_start_memcpy( - (int *) bsp_section_text_begin, - (const int *) bsp_section_text_load_begin, - (size_t) bsp_section_text_size - ); - - /* Copy .rodata section */ - bsp_start_memcpy( - (int *) bsp_section_rodata_begin, - (const int *) bsp_section_rodata_load_begin, - (size_t) bsp_section_rodata_size - ); - - /* Copy .data section */ - bsp_start_memcpy( - (int *) bsp_section_data_begin, - (const int *) bsp_section_data_load_begin, - (size_t) bsp_section_data_size - ); - - /* Copy .fast_text section */ - bsp_start_memcpy( - (int *) bsp_section_fast_text_begin, - (const int *) bsp_section_fast_text_load_begin, - (size_t) bsp_section_fast_text_size - ); - - /* Copy .fast_data section */ - bsp_start_memcpy( - (int *) bsp_section_fast_data_begin, - (const int *) bsp_section_fast_data_load_begin, - (size_t) bsp_section_fast_data_size - ); -} - -BSP_START_TEXT_SECTION static inline void bsp_start_clear_bss(void) -{ - memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_SHARED_START_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/bsp.h b/c/src/lib/libbsp/arm/stm32f4/include/bsp.h deleted file mode 100644 index a5e7e60484..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/bsp.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file - * @ingroup arm_stm34f4 - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/** - * @defgroup arm_stm32f4 STM32F4 Support - * @ingroup bsp_arm - * @brief STM32f4 Support Package - * @{ - */ - -#ifndef LIBBSP_ARM_STM32F4_BSP_H -#define LIBBSP_ARM_STM32F4_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) - -#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) - -#define BSP_ARMV7M_SYSTICK_FREQUENCY STM32F4_HCLK - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_BSP_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/i2c.h b/c/src/lib/libbsp/arm/stm32f4/include/i2c.h deleted file mode 100644 index fa18b1f92f..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/i2c.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * @ingroup stm32f4_i2c I2C Support - * @brief I2C-module. - */ - -/* - * Copyright (c) 2013 Christian Mauderer. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* The I2C-module can not run with libi2c. The reason for this is, that libi2c - * needs a possibility to generate a stop condition separately. This controller - * wants to generate the condition automatically when sending or receiving data. - */ - -#ifndef LIBBSP_ARM_STM32F4_I2C_H -#define LIBBSP_ARM_STM32F4_I2C_H - -#include <rtems.h> - -#include <bsp/io.h> -#include <bsp/stm32f4.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup stm32f4_i2c I2C Support - * @ingroup arm_stm32f4 - * @brief I2C Module - * @{ - */ - -typedef struct { - /** - * @brief The address of the slave without the read write bit. - * A 7-Bit address should be placed in the bits [6..0] - */ - uint16_t addr; - /** @brief Read (true) or write (false) data */ - bool read; - /** @brief Size of data to read or write */ - size_t len; - /** @brief Buffer for data */ - uint8_t *buf; -} stm32f4_i2c_message; - -typedef struct { - volatile stm32f4_i2c *regs; - size_t index; - rtems_vector_number vector; - rtems_id mutex; - rtems_id task_id; - uint8_t *data; - uint8_t *last; - size_t len; - bool read; - uint8_t addr_with_rw; -} stm32f4_i2c_bus_entry; - -/** @brief Initialise the i2c module. */ -rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e); - -/** @brief Process a i2c message */ -rtems_status_code stm32f4_i2c_process_message( - stm32f4_i2c_bus_entry *e, - stm32f4_i2c_message *msg -); - -/** @brief Set another baud rate than the default one */ -rtems_status_code stm32f4_i2c_set_bitrate( - stm32f4_i2c_bus_entry *e, - uint32_t br -); - -extern stm32f4_i2c_bus_entry *const stm32f4_i2c1; -extern stm32f4_i2c_bus_entry *const stm32f4_i2c2; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_I2C_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/io.h b/c/src/lib/libbsp/arm/stm32f4/include/io.h deleted file mode 100644 index b7f8669cba..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/io.h +++ /dev/null @@ -1,416 +0,0 @@ -/** - * @file - * @ingroup stm32f4_io - * @brief IO support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_IO_H -#define LIBBSP_ARM_STM32F4_IO_H - -#include <stdbool.h> -#include <stdint.h> -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup stm32f4_io IO Support - * @ingroup arm_stm32f4 - * @brief IO Support - * @{ - */ - -#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff) - -#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf) - -#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf) - -#ifdef STM32F4_FAMILY_F4XXXX - -/** - * @name Family F4XXXX - * @{ - */ - -typedef enum { - STM32F4_GPIO_MODE_INPUT, - STM32F4_GPIO_MODE_OUTPUT, - STM32F4_GPIO_MODE_AF, - STM32F4_GPIO_MODE_ANALOG -} stm32f4_gpio_mode; - -typedef enum { - STM32F4_GPIO_OTYPE_PUSH_PULL, - STM32F4_GPIO_OTYPE_OPEN_DRAIN -} stm32f4_gpio_otype; - -typedef enum { - STM32F4_GPIO_OSPEED_2_MHZ, - STM32F4_GPIO_OSPEED_25_MHZ, - STM32F4_GPIO_OSPEED_50_MHZ, - STM32F4_GPIO_OSPEED_100_MHZ -} stm32f4_gpio_ospeed; - -typedef enum { - STM32F4_GPIO_NO_PULL, - STM32F4_GPIO_PULL_UP, - STM32F4_GPIO_PULL_DOWN -} stm32f4_gpio_pull; - -typedef enum { - STM32F4_GPIO_AF_SYSTEM = 0, - STM32F4_GPIO_AF_TIM1 = 1, - STM32F4_GPIO_AF_TIM2 = 1, - STM32F4_GPIO_AF_TIM3 = 2, - STM32F4_GPIO_AF_TIM4 = 2, - STM32F4_GPIO_AF_TIM5 = 2, - STM32F4_GPIO_AF_TIM8 = 3, - STM32F4_GPIO_AF_TIM9 = 3, - STM32F4_GPIO_AF_TIM10 = 3, - STM32F4_GPIO_AF_TIM11 = 3, - STM32F4_GPIO_AF_I2C1 = 4, - STM32F4_GPIO_AF_I2C2 = 4, - STM32F4_GPIO_AF_I2C3 = 4, - STM32F4_GPIO_AF_SPI1 = 5, - STM32F4_GPIO_AF_SPI2 = 5, - STM32F4_GPIO_AF_SPI3 = 6, - STM32F4_GPIO_AF_USART1 = 7, - STM32F4_GPIO_AF_USART2 = 7, - STM32F4_GPIO_AF_USART3 = 7, - STM32F4_GPIO_AF_UART4 = 8, - STM32F4_GPIO_AF_UART5 = 8, - STM32F4_GPIO_AF_USART6 = 8, - STM32F4_GPIO_AF_CAN1 = 9, - STM32F4_GPIO_AF_CAN2 = 9, - STM32F4_GPIO_AF_TIM12 = 9, - STM32F4_GPIO_AF_TIM13 = 9, - STM32F4_GPIO_AF_TIM14 = 9, - STM32F4_GPIO_AF_OTG_FS = 10, - STM32F4_GPIO_AF_OTG_HS = 10, - STM32F4_GPIO_AF_ETH = 11, - STM32F4_GPIO_AF_FSMC = 12, - STM32F4_GPIO_AF_OTG_HS_FS = 12, - STM32F4_GPIO_AF_SDIO = 12, - STM32F4_GPIO_AF_DCMI = 13, - STM32F4_GPIO_AF_EVENTOUT = 15 -} stm32f4_gpio_af; - -typedef union { - struct { - uint32_t pin_first : 8; - uint32_t pin_last : 8; - uint32_t mode : 2; - uint32_t otype : 1; - uint32_t ospeed : 2; - uint32_t pupd : 2; - uint32_t output : 1; - uint32_t af : 4; - uint32_t reserved : 4; - } fields; - - uint32_t value; -} stm32f4_gpio_config; - -#define STM32F4_GPIO_CONFIG_TERMINAL \ - { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } } - -/** @} */ - -#endif /* STM32F4_FAMILY_F4XXXX */ -#ifdef STM32F4_FAMILY_F10XXX - -/** - * @name Family F10XXX - * @{ - */ - -typedef enum { - STM32F4_GPIO_MODE_INPUT, - STM32F4_GPIO_MODE_OUTPUT_10MHz, - STM32F4_GPIO_MODE_OUTPUT_2MHz, - STM32F4_GPIO_MODE_OUTPUT_50MHz -} stm32f4_gpio_mode; - -typedef enum { - STM32F4_GPIO_CNF_IN_ANALOG = 0, - STM32F4_GPIO_CNF_IN_FLOATING = 1, - STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2, - - STM32F4_GPIO_CNF_OUT_GPIO_PP = 0, - STM32F4_GPIO_CNF_OUT_GPIO_OD = 1, - STM32F4_GPIO_CNF_OUT_AF_PP = 2, - STM32F4_GPIO_CNF_OUT_AF_OD = 3, -} stm32f4_gpio_cnf; - -typedef enum { - STM32F4_GPIO_REMAP_DONT_CHANGE, - STM32F4_GPIO_REMAP_SPI1_0, - STM32F4_GPIO_REMAP_SPI1_1, - STM32F4_GPIO_REMAP_I2C1_0, - STM32F4_GPIO_REMAP_I2C1_1, - STM32F4_GPIO_REMAP_USART1_0, - STM32F4_GPIO_REMAP_USART1_1, - STM32F4_GPIO_REMAP_USART2_0, - STM32F4_GPIO_REMAP_USART2_1, - STM32F4_GPIO_REMAP_USART3_0, - STM32F4_GPIO_REMAP_USART3_1, - STM32F4_GPIO_REMAP_USART3_3, - STM32F4_GPIO_REMAP_TIM1_0, - STM32F4_GPIO_REMAP_TIM1_1, - STM32F4_GPIO_REMAP_TIM1_3, - STM32F4_GPIO_REMAP_TIM2_0, - STM32F4_GPIO_REMAP_TIM2_1, - STM32F4_GPIO_REMAP_TIM2_2, - STM32F4_GPIO_REMAP_TIM2_3, - STM32F4_GPIO_REMAP_TIM3_0, - STM32F4_GPIO_REMAP_TIM3_2, - STM32F4_GPIO_REMAP_TIM3_3, - STM32F4_GPIO_REMAP_TIM4_0, - STM32F4_GPIO_REMAP_TIM4_1, - STM32F4_GPIO_REMAP_CAN1_0, - STM32F4_GPIO_REMAP_CAN1_2, - STM32F4_GPIO_REMAP_CAN1_3, - STM32F4_GPIO_REMAP_PD01_0, - STM32F4_GPIO_REMAP_PD01_1, - STM32F4_GPIO_REMAP_TIM5CH4_0, - STM32F4_GPIO_REMAP_TIM5CH4_1, - STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, - STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, - STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, - STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, - STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, - STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, - STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, - STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, - STM32F4_GPIO_REMAP_ETH_0, - STM32F4_GPIO_REMAP_ETH_1, - STM32F4_GPIO_REMAP_CAN2_0, - STM32F4_GPIO_REMAP_CAN2_1, - STM32F4_GPIO_REMAP_MII_RMII_0, - STM32F4_GPIO_REMAP_MII_RMII_1, - STM32F4_GPIO_REMAP_SWJ_0, - STM32F4_GPIO_REMAP_SWJ_1, - STM32F4_GPIO_REMAP_SWJ_2, - STM32F4_GPIO_REMAP_SWJ_4, - STM32F4_GPIO_REMAP_SPI3_0, - STM32F4_GPIO_REMAP_SPI3_1, - STM32F4_GPIO_REMAP_TIM2ITR1_0, - STM32F4_GPIO_REMAP_TIM2ITR1_1, - STM32F4_GPIO_REMAP_PTP_PPS_0, - STM32F4_GPIO_REMAP_PTP_PPS_1, - STM32F4_GPIO_REMAP_TIM15_0, - STM32F4_GPIO_REMAP_TIM15_1, - STM32F4_GPIO_REMAP_TIM16_0, - STM32F4_GPIO_REMAP_TIM16_1, - STM32F4_GPIO_REMAP_TIM17_0, - STM32F4_GPIO_REMAP_TIM17_1, - STM32F4_GPIO_REMAP_CEC_0, - STM32F4_GPIO_REMAP_CEC_1, - STM32F4_GPIO_REMAP_TIM1_DMA_0, - STM32F4_GPIO_REMAP_TIM1_DMA_1, - STM32F4_GPIO_REMAP_TIM9_0, - STM32F4_GPIO_REMAP_TIM9_1, - STM32F4_GPIO_REMAP_TIM10_0, - STM32F4_GPIO_REMAP_TIM10_1, - STM32F4_GPIO_REMAP_TIM11_0, - STM32F4_GPIO_REMAP_TIM11_1, - STM32F4_GPIO_REMAP_TIM13_0, - STM32F4_GPIO_REMAP_TIM13_1, - STM32F4_GPIO_REMAP_TIM14_0, - STM32F4_GPIO_REMAP_TIM14_1, - STM32F4_GPIO_REMAP_FSMC_0, - STM32F4_GPIO_REMAP_FSMC_1, - STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, - STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, - STM32F4_GPIO_REMAP_TIM12_0, - STM32F4_GPIO_REMAP_TIM12_1, - STM32F4_GPIO_REMAP_MISC_0, - STM32F4_GPIO_REMAP_MISC_1, -} stm32f4_gpio_remap; - -typedef union { - struct { - uint32_t pin_first : 8; - uint32_t pin_last : 8; - uint32_t mode : 2; - uint32_t cnf : 2; - uint32_t output : 1; - uint32_t remap : 8; - uint32_t reserved : 3; - } fields; - - uint32_t value; -} stm32f4_gpio_config; - -#define STM32F4_GPIO_CONFIG_TERMINAL \ - { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } } - -/** @} */ - -#endif /* STM32F4_FAMILY_F10XXX */ - -extern const stm32f4_gpio_config stm32f4_start_config_gpio []; - -void stm32f4_gpio_set_clock(int pin, bool set); - -void stm32f4_gpio_set_config(const stm32f4_gpio_config *config); - -/** - * @brief Sets the GPIO configuration of an array terminated by - * STM32F4_GPIO_CONFIG_TERMINAL. - */ -void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs); - -void stm32f4_gpio_set_output(int pin, bool set); - -bool stm32f4_gpio_get_input(int pin); - -#ifdef STM32F4_FAMILY_F4XXXX - -/** - * @name Family F4XXXX - * @{ - */ - -#define STM32F4_PIN_USART(port, idx, altfunc) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_AF, \ - .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \ - .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \ - .pupd = STM32F4_GPIO_PULL_UP, \ - .af = altfunc \ - } \ - } - -#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1) -#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1) -#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1) -#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1) - -#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2) -#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2) -#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2) -#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2) - -#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3) -#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3) -#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3) -#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3) - -#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4) -#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4) -#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4) -#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4) - -#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5) -#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5) - -#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6) -#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6) - -/** @} */ - -#endif /* STM32F4_FAMILY_F4XXXX */ -#ifdef STM32F4_FAMILY_F10XXX - -/** - * @name Family F10XXX - * @{ - */ - -#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ - .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \ - .output = 0, \ - .remap = remapvalue \ - } \ - } - -#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_INPUT, \ - .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \ - .output = 0, \ - .remap = remapvalue \ - } \ - } - -#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0) -#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0) -#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1) -#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1) - -#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0) -#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0) -#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1) -#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1) - -#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0) -#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0) -#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1) -#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1) -#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3) -#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3) - -#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) -#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) - -#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE) -#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE) - -#define STM32F4_PIN_I2C(port, idx, remapvalue) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ - .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \ - .output = 0, \ - .remap = remapvalue \ - } \ - } - -#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0) -#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0) -#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1) -#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1) - -#define STM32F4_PIN_I2C2_SCL STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) -#define STM32F4_PIN_I2C2_SDA STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) - -/** @} */ - -#endif /* STM32F4_FAMILY_F10XXX */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_IO_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/irq.h b/c/src/lib/libbsp/arm/stm32f4/include/irq.h deleted file mode 100644 index 4771f521fe..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/irq.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file - * @ingroup stm32f4_interrupt - * @brief Interrupt definitions. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_IRQ_H -#define LIBBSP_ARM_STM32F4_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -/** - * @defgroup stm32f4_interrupt Interrupt Support - * @ingroup arm_stm32f4 - * @brief Interrupt Support - * @{ - */ - -#define STM32F4_IRQ_WWDG 0 -#define STM32F4_IRQ_PVD 1 -#define STM32F4_IRQ_TAMP_STAMP 2 -#define STM32F4_IRQ_RTC_WKUP 3 -#define STM32F4_IRQ_FLASH 4 -#define STM32F4_IRQ_RCC 5 -#define STM32F4_IRQ_EXTI0 6 -#define STM32F4_IRQ_EXTI1 7 -#define STM32F4_IRQ_EXTI2 8 -#define STM32F4_IRQ_EXTI3 9 -#define STM32F4_IRQ_EXTI4 10 -#define STM32F4_IRQ_DMA1_STREAM0 11 -#define STM32F4_IRQ_DMA1_STREAM1 12 -#define STM32F4_IRQ_DMA1_STREAM2 13 -#define STM32F4_IRQ_DMA1_STREAM3 14 -#define STM32F4_IRQ_DMA1_STREAM4 15 -#define STM32F4_IRQ_DMA1_STREAM5 16 -#define STM32F4_IRQ_DMA1_STREAM6 17 -#define STM32F4_IRQ_ADC 18 -#define STM32F4_IRQ_CAN1_TX 19 -#define STM32F4_IRQ_CAN1_RX0 20 -#define STM32F4_IRQ_CAN1_RX1 21 -#define STM32F4_IRQ_CAN1_SCE 22 -#define STM32F4_IRQ_EXTI9_5 23 -#define STM32F4_IRQ_TIM1_BRK_TIM9 24 -#define STM32F4_IRQ_TIM1_UP_TIM10 25 -#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26 -#define STM32F4_IRQ_TIM1_CC 27 -#define STM32F4_IRQ_TIM2 28 -#define STM32F4_IRQ_TIM3 29 -#define STM32F4_IRQ_TIM4 30 -#define STM32F4_IRQ_I2C1_EV 31 -#define STM32F4_IRQ_I2C1_ER 32 -#define STM32F4_IRQ_I2C2_EV 33 -#define STM32F4_IRQ_I2C2_ER 34 -#define STM32F4_IRQ_SPI1 35 -#define STM32F4_IRQ_SPI2 36 -#define STM32F4_IRQ_USART1 37 -#define STM32F4_IRQ_USART2 38 -#define STM32F4_IRQ_USART3 39 -#define STM32F4_IRQ_EXTI15_10 40 -#define STM32F4_IRQ_RTC_ALARM 41 -#define STM32F4_IRQ_OTG_FS_WKUP 42 -#define STM32F4_IRQ_TIM8_BRK_TIM12 43 -#define STM32F4_IRQ_TIM8_UP_TIM13 44 -#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45 -#define STM32F4_IRQ_TIM8_CC 46 -#define STM32F4_IRQ_DMA1_STREAM7 47 -#define STM32F4_IRQ_FSMC 48 -#define STM32F4_IRQ_SDIO 49 -#define STM32F4_IRQ_TIM5 50 -#define STM32F4_IRQ_SPI3 51 -#define STM32F4_IRQ_UART4 52 -#define STM32F4_IRQ_UART5 53 -#define STM32F4_IRQ_TIM6_DAC 54 -#define STM32F4_IRQ_TIM7 55 -#define STM32F4_IRQ_DMA2_STREAM0 56 -#define STM32F4_IRQ_DMA2_STREAM1 57 -#define STM32F4_IRQ_DMA2_STREAM2 58 -#define STM32F4_IRQ_DMA2_STREAM3 59 -#define STM32F4_IRQ_DMA2_STREAM4 60 -#define STM32F4_IRQ_ETH 61 -#define STM32F4_IRQ_ETH_WKUP 62 -#define STM32F4_IRQ_CAN2_TX 63 -#define STM32F4_IRQ_CAN2_RX0 64 -#define STM32F4_IRQ_CAN2_RX1 65 -#define STM32F4_IRQ_CAN2_SCE 66 -#define STM32F4_IRQ_OTG_FS 67 -#define STM32F4_IRQ_DMA2_STREAM5 68 -#define STM32F4_IRQ_DMA2_STREAM6 69 -#define STM32F4_IRQ_DMA2_STREAM7 70 -#define STM32F4_IRQ_USART6 71 -#define STM32F4_IRQ_I2C3_EV 72 -#define STM32F4_IRQ_I2C3_ER 73 -#define STM32F4_IRQ_OTG_HS_EP1_OUT 74 -#define STM32F4_IRQ_OTG_HS_EP1_IN 75 -#define STM32F4_IRQ_OTG_HS_WKUP 76 -#define STM32F4_IRQ_OTG_HS 77 -#define STM32F4_IRQ_DCMI 78 -#define STM32F4_IRQ_CRYP 79 -#define STM32F4_IRQ_HASH_RNG 80 -#define STM32F4_IRQ_FPU 81 - -#define STM32F4_IRQ_PRIORITY_VALUE_MIN 0 -#define STM32F4_IRQ_PRIORITY_VALUE_MAX 15 -#define STM32F4_IRQ_PRIORITY_COUNT (STM32F4_IRQ_PRIORITY_VALUE_MAX + 1) -#define STM32F4_IRQ_PRIORITY_HIGHEST STM32F4_IRQ_PRIORITY_VALUE_MIN -#define STM32F4_IRQ_PRIORITY_LOWEST STM32F4_IRQ_PRIORITY_VALUE_MAX - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 81 - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/usart.h b/c/src/lib/libbsp/arm/stm32f4/include/usart.h deleted file mode 100644 index bac0f6845a..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/usart.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * @ingroup stm32f4_usart - * @brief USART (universal synchronous/asynchronous receiver/transmitter) support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_USART_H -#define LIBBSP_ARM_STM32F4_USART_H - -#include <libchip/serial.h> - -/** - * @defgroup stm32f4_usart USART Support - * @ingroup arm_stm32f4 - * @brief USART Support - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -extern const console_fns stm32f4_usart_fns; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_USART_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/bsp.h b/c/src/lib/libbsp/arm/tms570/include/bsp.h deleted file mode 100644 index 81bc4cd9cf..0000000000 --- a/c/src/lib/libbsp/arm/tms570/include/bsp.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * @file bsp.h - * - * @ingroup tms570 - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> - * - * Google Summer of Code 2014 at - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * Based on LPC24xx and LPC1768 BSP - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_TMS570_BSP_H -#define LIBBSP_ARM_TMS570_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/default-initial-extension.h> - -#define BSP_OSCILATOR_CLOCK 8000000 -#define BSP_PLL_OUT_CLOCK 160000000 - -/** Define operation count for Tests */ -#define OPERATION_COUNT 4 - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct rtems_bsdnet_ifconfig; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_TMS570_BSP_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/irq.h b/c/src/lib/libbsp/arm/tms570/include/irq.h deleted file mode 100644 index 2952582453..0000000000 --- a/c/src/lib/libbsp/arm/tms570/include/irq.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * @file irq.h - * - * @ingroup tms570 - * - * @brief TMS570 interrupt definitions. - */ - -/* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> - * - * Google Summer of Code 2014 at - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_TMS570_IRQ_H -#define LIBBSP_ARM_TMS570_IRQ_H - -#ifndef ASM -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#endif - -#define BSP_INTERRUPT_VECTOR_MIN 0U -#define TMS570_IRQ_ESM_HIGH 0 -#define TMS570_IRQ_RESERVED 1 -#define TMS570_IRQ_TIMER_0 2 -#define TMS570_IRQ_TIMER_1 3 -#define TMS570_IRQ_TIMER_2 4 -#define TMS570_IRQ_TIMER_3 5 -#define TMS570_IRQ_RTI_OVERFLOW_0 6 -#define TMS570_IRQ_RTI_OVERFLOW_1 7 -#define TMS570_IRQ_RTI_TIMEBASE 8 -#define TMS570_IRQ_GIO_HIGH 9 -#define TMS570_IRQ_HET_HIGH 10 -#define TMS570_IRQ_HET_TU_HIGH 11 -#define TMS570_IRQ_MIBSPI1_HIGH 12 -#define TMS570_IRQ_SCI_LEVEL_0 13 -#define TMS570_IRQ_ADC1_EVENT 14 -#define TMS570_IRQ_ADC1_GROUP_1 15 -#define TMS570_IRQ_CAN1_HIGH 16 -#define TMS570_IRQ_RESERVED 17 -#define TMS570_IRQ_FLEXRAY_HIGH 18 -#define TMS570_IRQ_CRC_1 19 -#define TMS570_IRQ_ESM_LOW 20 -#define TMS570_IRQ_SSI 21 -#define TMS570_IRQ_PMU 22 -#define TMS570_IRQ_GIO_LOW 23 -#define TMS570_IRQ_HET_LOW 24 -#define TMS570_IRQ_HET_TU_LOW 25 -#define TMS570_IRQ_MIBSPI1_LOW 26 -#define TMS570_IRQ_SCI_LEVEL_1 27 -#define TMS570_IRQ_ADC1_GROUP_2 28 -#define TMS570_IRQ_CAN1_LOW 29 -#define TMS570_IRQ_RESERVED -#define TMS570_IRQ_ADC1_MAG 31 -#define TMS570_IRQ_FLEXRAY_LOW 32 -#define TMS570_IRQ_DMA_FTCA 33 -#define TMS570_IRQ_DMA_LFSA 34 -#define TMS570_IRQ_CAN2_HIGH 35 -#define TMS570_IRQ_DMM_HIGH 36 -#define TMS570_IRQ_MIBSPI3_HIGH 37 -#define TMS570_IRQ_MIBSPI3_LOW 38 -#define TMS570_IRQ_DMA_HBCA 39 -#define TMS570_IRQ_DMA_BTCA 40 -#define TMS570_IRQ_DMA_BERA 41 -#define TMS570_IRQ_CAN2_LOW 42 -#define TMS570_IRQ_DMM_LOW 43 -#define TMS570_IRQ_CAN1_IF3 44 -#define TMS570_IRQ_CAN3_HIGH 45 -#define TMS570_IRQ_CAN2_IF3 46 -#define TMS570_IRQ_FPU 47 -#define TMS570_IRQ_FLEXRAY_TU 48 -#define TMS570_IRQ_SPI4_HIGH 49 -#define TMS570_IRQ_ADC2_EVENT 50 -#define TMS570_IRQ_ADC2_GROUP_1 51 -#define TMS570_IRQ_FLEXRAY_T0C 52 -#define TMS570_IRQ_MIBSPIP5_HIGH 53 -#define TMS570_IRQ_SPI4_LOW 54 -#define TMS570_IRQ_CAN3_LOW 55 -#define TMS570_IRQ_MIBSPIP5_LOW 56 -#define TMS570_IRQ_ADC2_GROUP_2 57 -#define TMS570_IRQ_FLEXRAY_TU_ERROR 58 -#define TMS570_IRQ_ADC2_MAG 59 -#define TMS570_IRQ_CAN3_IF3 60 -#define TMS570_IRQ_FSM_DONE 61 -#define TMS570_IRQ_FLEXRAY_T1C 62 -#define TMS570_IRQ_HET2_LEVEL_0 63 -#define TMS570_IRQ_SCI2_LEVEL_0 64 -#define TMS570_IRQ_HET_TU2_LEVEL_0 65 -#define TMS570_IRQ_IC2_INTERRUPT 66 -#define TMS570_IRQ_HET2_LEVEL_1 73 -#define TMS570_IRQ_SCI2_LEVEL_1 74 -#define TMS570_IRQ_HET_TU2_LEVEL_1 75 -#define TMS570_IRQ_EMAC_MISC 76 -#define TMS570_IRQ_EMAC_TX 77 -#define TMS570_IRQ_EMAC_THRESH 78 -#define TMS570_IRQ_EMAC_RX 79 -#define TMS570_IRQ_HWA_INT_REQ_H 80 -#define TMS570_IRQ_HWA_INT_REQ_H 81 -#define TMS570_IRQ_DCC_DONE_INTERRUPT 82 -#define TMS570_IRQ_DCC2_DONE_INTERRUPT 83 -#define TMS570_IRQ_HWAG1_INT_REQ_L 88 -#define TMS570_IRQ_HWAG2_INT_REQ_L 89 -#define BSP_INTERRUPT_VECTOR_MAX 94 - -#define TMS570_IRQ_PRIORITY_VALUE_MIN 0U -#define TMS570_IRQ_PRIORITY_VALUE_MAX 0U - -#define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U ) -#define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN -#define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX - -#ifndef ASM - -/** - * @brief Set priority of the interrupt vector. - * - * This function is here because of compability. It should set - * priority of the interrupt vector. - * @warning It does not set any priority at HW layer. It is nearly imposible to - * @warning set priority of the interrupt on TMS570 in a nice way. - * @param[in] vector vector of isr - * @param[in] priority new priority assigned to the vector - * @return Void - */ -void tms570_irq_set_priority( - rtems_vector_number vector, - unsigned priority -); - -/** - * @brief Gets priority of the interrupt vector. - * - * This function is here because of compability. It returns priority - * of the isr vector last set by tms570_irq_set_priority function. - * - * @warning It does not return any real priority of the HW layer. - * @param[in] vector vector of isr - * @retval 0 vector is invalid. - * @retval priority priority of the interrupt - */ -unsigned tms570_irq_get_priority( rtems_vector_number vector ); - -#endif /* ASM */ - -/** @} */ - -#endif /* LIBBSP_ARM_TMS570_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/tms570/include/system-clocks.h b/c/src/lib/libbsp/arm/tms570/include/system-clocks.h deleted file mode 100644 index 0e1d1301d4..0000000000 --- a/c/src/lib/libbsp/arm/tms570/include/system-clocks.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file benchmark_timer.c - * - * @ingroup tms570 - * - * @brief System clocks. - */ - -/* - * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH and others - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H -#define LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H - -#include <bsp/tms570-rti.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup tms570_clock System Clocks - * - * @ingroup tms570 - * - * @brief System clocks. - * - * @{ - */ - -/** - * @brief Returns current standard timer value in microseconds. - * - * This function uses RTI module free running counter 0 used - * which is used as system tick timebase as well. - */ -static inline unsigned tms570_timer(void) -{ - uint32_t actual_fcr0 = TMS570_RTI.CNT[0].FRCx; - return actual_fcr0; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_TMS570_SYSTEM_CLOCKS_H */ diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h deleted file mode 100644 index bf3ad92b96..0000000000 --- a/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * @file - * @ingroup arm_zynq - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H -#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H - -#include <bspopts.h> - -#define BSP_FEATURE_IRQ_EXTENSION - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <bsp/default-initial-extension.h> -#include <bsp/start.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup arm_zynq Xilinx-Zynq Support - * @ingroup bsp_arm - * @brief Xilinz-Zynq Board Support Package - * @{ - */ - -#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000 - -#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100 - -#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200 - -#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600 - -#define BSP_ARM_GIC_DIST_BASE 0xf8f01000 - -#define BSP_ARM_L2C_310_BASE 0xf8f02000 - -#define BSP_ARM_L2C_310_ID 0x410000c8 - -/** - * @brief Zynq specific set up of the MMU. - * - * Provide in the application to override - * the defaults in the BSP. Note the defaults do not map in the GP0 and GP1 - * AXI ports. You should add the specific regions that map into your - * PL rather than just open the whole of the GP[01] address space up. - */ -BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void); - -uint32_t zynq_clock_cpu_1x(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/i2c.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/i2c.h deleted file mode 100644 index 709ea0178e..0000000000 --- a/c/src/lib/libbsp/arm/xilinx-zynq/include/i2c.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H -#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H - -#include <bsp/cadence-i2c.h> -#include <bsp/irq.h> -#include <bsp.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -static inline int zynq_register_i2c_0(void) -{ - return i2c_bus_register_cadence( - "/dev/i2c-0", - 0xe0004000, - zynq_clock_cpu_1x(), - ZYNQ_IRQ_I2C_0 - ); -} - -static inline int zynq_register_i2c_1(void) -{ - return i2c_bus_register_cadence( - "/dev/i2c-1", - 0xe0005000, - zynq_clock_cpu_1x(), - ZYNQ_IRQ_I2C_1 - ); -} - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */ diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h deleted file mode 100644 index e8288938fe..0000000000 --- a/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * @file - * @ingroup zynq_interrupt - * @brief Interrupt definitions. - */ - -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H -#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H - -#ifndef ASM - -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#include <bsp/arm-a9mpcore-irq.h> -#include <bsp/arm-gic-irq.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup zynq_interrupt Interrupt Support - * @ingroup arm_zynq - * @brief Interrupt Support - * @{ - */ - -#define ZYNQ_IRQ_CPU_0 32 -#define ZYNQ_IRQ_CPU_1 33 -#define ZYNQ_IRQ_L2_CACHE 34 -#define ZYNQ_IRQ_OCM 35 -#define ZYNQ_IRQ_PMU_0 37 -#define ZYNQ_IRQ_PMU_1 38 -#define ZYNQ_IRQ_XADC 39 -#define ZYNQ_IRQ_DVI 40 -#define ZYNQ_IRQ_SWDT 41 -#define ZYNQ_IRQ_TTC_0_0 42 -#define ZYNQ_IRQ_TTC_1_0 43 -#define ZYNQ_IRQ_TTC_2_0 44 -#define ZYNQ_IRQ_DMAC_ABORT 45 -#define ZYNQ_IRQ_DMAC_0 46 -#define ZYNQ_IRQ_DMAC_1 47 -#define ZYNQ_IRQ_DMAC_2 48 -#define ZYNQ_IRQ_DMAC_3 49 -#define ZYNQ_IRQ_SMC 50 -#define ZYNQ_IRQ_QUAD_SPI 51 -#define ZYNQ_IRQ_GPIO 52 -#define ZYNQ_IRQ_USB_0 53 -#define ZYNQ_IRQ_ETHERNET_0 54 -#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55 -#define ZYNQ_IRQ_SDIO_0 56 -#define ZYNQ_IRQ_I2C_0 57 -#define ZYNQ_IRQ_SPI_0 58 -#define ZYNQ_IRQ_UART_0 59 -#define ZYNQ_IRQ_CAN_0 60 -#define ZYNQ_IRQ_FPGA_0 61 -#define ZYNQ_IRQ_FPGA_1 62 -#define ZYNQ_IRQ_FPGA_2 63 -#define ZYNQ_IRQ_FPGA_3 64 -#define ZYNQ_IRQ_FPGA_4 65 -#define ZYNQ_IRQ_FPGA_5 66 -#define ZYNQ_IRQ_FPGA_6 67 -#define ZYNQ_IRQ_FPGA_7 68 -#define ZYNQ_IRQ_TTC_0_1 69 -#define ZYNQ_IRQ_TTC_1_1 70 -#define ZYNQ_IRQ_TTC_2_1 71 -#define ZYNQ_IRQ_DMAC_4 72 -#define ZYNQ_IRQ_DMAC_5 73 -#define ZYNQ_IRQ_DMAC_6 74 -#define ZYNQ_IRQ_DMAC_7 75 -#define ZYNQ_IRQ_USB_1 76 -#define ZYNQ_IRQ_ETHERNET_1 77 -#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78 -#define ZYNQ_IRQ_SDIO_1 79 -#define ZYNQ_IRQ_I2C_1 80 -#define ZYNQ_IRQ_SPI_1 81 -#define ZYNQ_IRQ_UART_1 82 -#define ZYNQ_IRQ_CAN_1 83 -#define ZYNQ_IRQ_FPGA_8 84 -#define ZYNQ_IRQ_FPGA_9 85 -#define ZYNQ_IRQ_FPGA_10 86 -#define ZYNQ_IRQ_FPGA_11 87 -#define ZYNQ_IRQ_FPGA_12 88 -#define ZYNQ_IRQ_FPGA_13 89 -#define ZYNQ_IRQ_FPGA_14 90 -#define ZYNQ_IRQ_FPGA_15 91 -#define ZYNQ_IRQ_PARITY 92 - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 92 - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h deleted file mode 100644 index 39b8ecafec..0000000000 --- a/c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h +++ /dev/null @@ -1,36 +0,0 @@ -/** - * @file - * @ingroup zynq_tm27 - * @brief Interrupt mechanisms for tm27 test. - */ - -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup zynq_tm27 TM27 Test Support - * @ingroup arm_zynq - * @brief Interrupt Mechanisms for tm27 test - */ - -#include <bsp/arm-gic-tm27.h> - -#endif /* __tm27_h */ diff --git a/c/src/lib/libbsp/avr/avrtest/include/bsp.h b/c/src/lib/libbsp/avr/avrtest/include/bsp.h deleted file mode 100644 index 1a1613981d..0000000000 --- a/c/src/lib/libbsp/avr/avrtest/include/bsp.h +++ /dev/null @@ -1,37 +0,0 @@ -/* bsp.h - * - * This include file contains some definitions specific to the - * h8 simulator in gdb. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_AVR_AVRTEST_BSP_H -#define LIBBSP_AVR_AVRTEST_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h b/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h deleted file mode 100644 index a8c4eb8ad5..0000000000 --- a/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file bsp.h - * @ingroup bfin_tll6527m - * @brief Global BSP definitions. - * - * This include file contains all board IO definitions for TLL6527M. - */ - -/* - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - */ - -#ifndef LIBBSP_BFIN_TLL6527M_BSP_H -#define LIBBSP_BFIN_TLL6527M_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/score/bfin.h> -#include <rtems/bfin/bf52x.h> -#include <bf52x.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup bfin_tll6527m TLL6527M Support - * @ingroup bsp_bfin - * @brief TLL6527M Support Package - * @{ - */ - -/* - * PLL and clock setup values: - */ - -/* - * PLL configuration for TLL6527M - * - * XTL = 27 MHz - * CLKIN = 13 MHz - * VCO = 391 MHz - * CCLK = 391 MHz - * SCLK = 130 MHz - */ - -/** - * @name PLL Configuration - * @{ - */ - -#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ -#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ -#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ - -/** @} */ - -/** - * @name Clock setup values - * @{ - */ - -#define CLKIN (25000000) ///< @brief Input clock to the PLL */ -#define CCLK (600000000) ///< @brief CORE CLOCK */ -#define SCLK (100000000) ///< @brief SYSTEM CLOCK */ - -/** @} */ - -/** - * @name UART setup values - * @{ - */ - -#define BAUDRATE 57600 ///< @brief Console Baudrate */ -#define WORD_5BITS 0x00 ///< @brief 5 bits word */ -#define WORD_6BITS 0x01 ///< @brief 6 bits word */ -#define WORD_7BITS 0x02 ///< @brief 7 bits word */ -#define WORD_8BITS 0x03 ///< @brief 8 bits word */ -#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ -#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ -#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ - -/** @} */ - -/** - * @brief Install an interrupt handler - * - * This method installs an interrupt handle. - * - * @param[in] handler is the isr routine - * @param[in] vector is the vector number - * @param[in] type indicates whether RTEMS or RAW intr - * - * @return returns old vector - */ -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Internal BSP methods that are used across file boundaries - */ -void Init_RTC(void); - -/* - * Prototype for methods in .S files that are referenced from C. - */ -void bfin_null_isr(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h b/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h deleted file mode 100644 index b6035ca142..0000000000 --- a/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * @ingroup tll6527m_cplb - * @brief CPLB configurations. - */ - -/* cplb.h - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer <alain.schaefer@easc.ch> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef _CPLB_H -#define _CPLB_H - -/** - * @defgroup tll6527m_cplb CPLB Configuration - * @ingroup bfin_tll6527m - * @brief CPLB Configuration - * @{ - */ - -/* CPLB configurations */ -#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT -#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL -#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY - -#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - -#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID -#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID - -#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID -#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL - -#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT -#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB - -/** @} */ - -#endif /* _CPLB_H */ diff --git a/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h b/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h deleted file mode 100644 index 787004f8a6..0000000000 --- a/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * @ingroup tll6527m_tm27 - * @brief Interrupt mechanisms for tm27 test. - */ - -/* - * tm27.h - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup tll6527m_tm27 TM27 Test Support - * @ingroup bfin_tll6527m - * @brief Interrupt Mechanisms for TM27 - * @{ - */ - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector(handler) \ -{ \ - set_vector( handler, 0x06, 1 ); \ -} - -#define Cause_tm27_intr() asm volatile("raise 0x06;" : :); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/** @} */ - -#endif diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/include/bsp.h b/c/src/lib/libbsp/bfin/bf537Stamp/include/bsp.h deleted file mode 100644 index 93f43e86d9..0000000000 --- a/c/src/lib/libbsp/bfin/bf537Stamp/include/bsp.h +++ /dev/null @@ -1,124 +0,0 @@ -/* bsp.h - * - * This include file contains all board IO definitions for bf537Stamp. - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer <alain.schaefer@easc.ch> - * and Antonio Giovanini <antonio@atos.com.br> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef LIBBSP_BFIN_BF537STAMP_BSP_H -#define LIBBSP_BFIN_BF537STAMP_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <libcpu/bf537.h> -#include <libcpu/memoryRegs.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* configure data cache to use 16K of each SRAM bank when enabled */ -#define BSP_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT) - - -/* - * PLL and clock setup values: - */ - -/* - * PLL configuration for bf533Stamp - * - * XTL = 27 MHz - * CLKIN = 13 MHz - * VCO = 391 MHz - * CCLK = 391 MHz - * SCLK = 130 MHz - */ - -#define PLL_CSEL 0x0000 /* CCLK = VCO */ -#define PLL_SSEL 0x0003 /* SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 /* VCO = 29xCLKIN */ -#define PLL_DF 0x0001 /* CLKIN = XTL/2 */ - -#define CCLK 500000000 /* CORE CLOCK */ -#define SCLK 100000000 /* SYSTEM CLOCK */ - -#define CONSOLE_FORCE_BAUD 57600 - -/* - * Blackfin environment memory map - */ -#define L1_DATA_SRAM_A 0xff800000L - -#define FIFOLENGTH 0x100 - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define rtems_bsp_delay( microseconds ) \ - { \ - } - -/* Constants */ - -#define RAM_START 0 -#define RAM_END 0x4000000 - -/* functions */ - -/* - * Helper Function to use the EzKits LEDS. - * Can be used by the Application. - */ -void setLED(uint8_t value); - -/* - * Helper Function to use the EzKits LEDS - */ -uint8_t getLEDs(void); -void setLEDs(uint8_t value); -uint8_t getButtons(void); - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -/* - * Internal BSP methods that are used across file boundaries - */ -void Init_RTC(void); - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int bf537Stamp_network_driver_attach(struct rtems_bsdnet_ifconfig *, int); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH bf537Stamp_network_driver_attach - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h b/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h deleted file mode 100644 index 9265f0e176..0000000000 --- a/c/src/lib/libbsp/bfin/eZKit533/include/bsp.h +++ /dev/null @@ -1,168 +0,0 @@ -/** - * @file - * @ingroup bfin_ezkit533 - * @brief Global BSP definitions. - */ - -/* bsp.h - * - * This include file contains all board IO definitions for eZKit533. - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer <alain.schaefer@easc.ch> - * and Antonio Giovanini <antonio@atos.com.br> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef LIBBSP_BFIN_EZKIT533_BSP_H -#define LIBBSP_BFIN_EZKIT533_BSP_H - -#ifndef ASM - -#include <libcpu/bf533.h> - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/score/bfin.h> -#include <rtems/bfin/bf533.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup bfin_ezkit533 eZKit533 Support - * @ingroup bsp_bfin - * @brief eZKit533 Board Support Package - * @{ - */ - -/** - * @name PLL and clock setup values: - * @brief PLL configuration for ezkit533 - * - * XTL = 27 MHz - * CLKIN = 13 MHz - * VCO = 391 MHz - * CCLK = 391 MHz - * SCLK = 130 MHz - * - * @{ - * - */ - -#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ -#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ -#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ - -#define CCLK 391000000 ///< @brief CORE CLOCK */ -#define SCLK 130000000 ///< @brief SYSTEM CLOCK */ - -/** @} */ - -/** - * @name UART setup values - * @{ - */ - -#define BAUDRATE 57600 ///< @brief Console Baudrate */ -#define WORD_5BITS 0x00 ///< @brief 5 bits word */ -#define WORD_6BITS 0x01 ///< @brief 6 bits word */ -#define WORD_7BITS 0x02 ///< @brief 7 bits word */ -#define WORD_8BITS 0x03 ///< @brief 8 bits word */ -#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ -#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ -#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ - -/** @} */ - -/** - * @name Ezkit flash ports - * @{ - */ - -#define FlashA_PortB_Dir 0x20270007L -#define FlashA_PortB_Data 0x20270005L - -/** @} */ - -/** - * @brief Blackfin environment memory map - */ -#define L1_DATA_SRAM_A 0xff800000L - -#define FIFOLENGTH 0x100 - -/** - * @name Constants - * @{ - */ - -#define RAM_START 0 -#define RAM_END 0x100000 - -/** @} */ - -/** - * @name functions - * @{ - */ - -/** - * @brief Helper Function to use the EzKits LEDS. - * Can be used by the Application. - */ -void setLED (uint8_t value); - -/** - * @brief Helper Function to use the EzKits LEDS - */ -uint8_t getLED (void); - -/** - * @brief Install an interrupt handler - * - * This method installs an interrupt handle. - * - * @param[in] handler is the isr routine - * @param[in] vector is the vector number - * @param[in] type indicates whether RTEMS or RAW intr - * - * @return returns old vector - */ -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Internal BSP methods that are used across file boundaries - */ -void Init_RTC(void); - -/* - * Prototype for methods in .S files that are referenced from C. - */ -void bfin_null_isr(void); - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h b/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h deleted file mode 100644 index 2c215e8954..0000000000 --- a/c/src/lib/libbsp/bfin/eZKit533/include/cplb.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * @ingroup ezkit533_cplb - * @brief CPLB configurations. - */ - -/* cplb.h - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer <alain.schaefer@easc.ch> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef _CPLB_H -#define _CPLB_H - -/** - * @defgroup ezkit533_cplb CPLB Configuration - * @ingroup bfin_ezkit533 - * @brief CPLB Configuration - * @{ - */ - -/* CPLB configurations */ -#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT -#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL -#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY - -#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - -#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID -#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID - -#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID -#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL - -#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT -#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB - -/** @} */ - -#endif /* _CPLB_H */ diff --git a/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h b/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h deleted file mode 100644 index 6aaf4cfa1d..0000000000 --- a/c/src/lib/libbsp/bfin/eZKit533/include/tm27.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * @ingroup ezkit533_tm27 - * @brief Interrupt mechanisms for the tm27 test. - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup ezkit533_tm27 TM27 Test Support - * @ingroup bfin_ezkit533 - * @brief Interrupt Mechanisms for TM27 - * @{ - */ - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector(handler) \ -{ \ - set_vector( handler, 0x06, 1 ); \ -} - -#define Cause_tm27_intr() __asm__ volatile("raise 0x06;" : :); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/** @} */ - -#endif diff --git a/c/src/lib/libbsp/epiphany/epiphany_sim/include/bsp.h b/c/src/lib/libbsp/epiphany/epiphany_sim/include/bsp.h deleted file mode 100644 index 1eb91ce8d6..0000000000 --- a/c/src/lib/libbsp/epiphany/epiphany_sim/include/bsp.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef LIBBSP_EPIPHANY_EPIPHANY_SIM_H -#define LIBBSP_EPIPHANY_EPIPHANY_SIM_H - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems/devnull.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -#ifdef __cplusplus -} -#endif - -#endif /* LIBBSP_EPIPHANY_PARALLELLA_H */ diff --git a/c/src/lib/libbsp/epiphany/epiphany_sim/include/irq.h b/c/src/lib/libbsp/epiphany/epiphany_sim/include/irq.h deleted file mode 100644 index 2b15a4536c..0000000000 --- a/c/src/lib/libbsp/epiphany/epiphany_sim/include/irq.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @ingroup Epiphany_IRQ - * - * @brief Interrupt definitions. - */ - -/* - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef LIBBSP_GENERIC_EPIPHANY_IRQ_H -#define LIBBSP_GENERIC_EPIPHANY_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#define BSP_INTERRUPT_VECTOR_MIN 0x0 -#define BSP_INTERRUPT_VECTOR_MAX 0x24 - -#endif /* ASM */ -#endif /* LIBBSP_GENERIC_OR1K_IRQ_H */ diff --git a/c/src/lib/libbsp/epiphany/epiphany_sim/include/tm27.h b/c/src/lib/libbsp/epiphany/epiphany_sim/include/tm27.h deleted file mode 100644 index 10dac820f1..0000000000 --- a/c/src/lib/libbsp/epiphany/epiphany_sim/include/tm27.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @name Interrupt mechanisms for Time Test 27 - * @{ - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) /* empty */ - -#define Cause_tm27_intr() /* empty */ - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/epiphany/shared/include/linker-symbols.h b/c/src/lib/libbsp/epiphany/shared/include/linker-symbols.h deleted file mode 100644 index c218b7ff99..0000000000 --- a/c/src/lib/libbsp/epiphany/shared/include/linker-symbols.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef LIBBSP_EPIPHANY_SHARED_LINKER_SYMBOLS_H -#define LIBBSP_EPIPHANY_SHARED_LINKER_SYMBOLS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup epiphany_linker Linker Support - * - * @ingroup epiphany_shared - * - * @brief Linker support. - * - * @{ - */ - -#ifndef ASM - #define LINKER_SYMBOL(sym) extern char sym []; -#else - #define LINKER_SYMBOL(sym) .extern sym -#endif - -LINKER_SYMBOL(bsp_section_start_begin) -LINKER_SYMBOL(bsp_section_start_end) -LINKER_SYMBOL(bsp_section_start_size) - -LINKER_SYMBOL(bsp_section_vector_begin) -LINKER_SYMBOL(bsp_section_vector_end) -LINKER_SYMBOL(bsp_section_vector_size) - -LINKER_SYMBOL(bsp_section_text_begin) -LINKER_SYMBOL(bsp_section_text_end) -LINKER_SYMBOL(bsp_section_text_size) -LINKER_SYMBOL(bsp_section_text_load_begin) -LINKER_SYMBOL(bsp_section_text_load_end) - -LINKER_SYMBOL(bsp_section_rodata_begin) -LINKER_SYMBOL(bsp_section_rodata_end) -LINKER_SYMBOL(bsp_section_rodata_size) -LINKER_SYMBOL(bsp_section_rodata_load_begin) -LINKER_SYMBOL(bsp_section_rodata_load_end) - -LINKER_SYMBOL(bsp_section_data_begin) -LINKER_SYMBOL(bsp_section_data_end) -LINKER_SYMBOL(bsp_section_data_size) -LINKER_SYMBOL(bsp_section_data_load_begin) -LINKER_SYMBOL(bsp_section_data_load_end) - -LINKER_SYMBOL(bsp_section_bss_begin) -LINKER_SYMBOL(bsp_section_bss_end) -LINKER_SYMBOL(bsp_section_bss_size) - -LINKER_SYMBOL(bsp_section_work_begin) -LINKER_SYMBOL(bsp_section_work_end) -LINKER_SYMBOL(bsp_section_work_size) - -LINKER_SYMBOL(bsp_section_stack_begin) -LINKER_SYMBOL(bsp_section_stack_end) -LINKER_SYMBOL(bsp_section_stack_size) - -LINKER_SYMBOL(bsp_vector_table_begin) -LINKER_SYMBOL(bsp_vector_table_end) -LINKER_SYMBOL(bsp_vector_table_size) - -LINKER_SYMBOL(bsp_start_vector_table_begin) -LINKER_SYMBOL(bsp_start_vector_table_end) -LINKER_SYMBOL(bsp_start_vector_table_size) - -LINKER_SYMBOL(bsp_translation_table_base) -LINKER_SYMBOL(bsp_translation_table_end) - -LINKER_SYMBOL(_bsp_processor_count) - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_EPIPHANY_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/h8300/h8sim/include/bsp.h b/c/src/lib/libbsp/h8300/h8sim/include/bsp.h deleted file mode 100644 index 6c45dc6abe..0000000000 --- a/c/src/lib/libbsp/h8300/h8sim/include/bsp.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * - * @ingroup h8300_bsp - * - * @brief h8 simulator definitions in gdb - * - * This include file contains some definitions specific to the - * h8 simulator in gdb. - */ - -/* - * COPYRIGHT (c) 1989-2013. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_H8300_H8SIM_BSP_H -#define LIBBSP_H8300_H8SIM_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup h8300_bsp Clock Tick Support - * - * @ingroup h8300_h8sim - * - * @brief Clock Tick Support Package - */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/i386/pc386/include/bsp.h b/c/src/lib/libbsp/i386/pc386/include/bsp.h deleted file mode 100644 index 5a82ac2122..0000000000 --- a/c/src/lib/libbsp/i386/pc386/include/bsp.h +++ /dev/null @@ -1,283 +0,0 @@ -/** - * @file - * - * @ingroup i386_pc386 - * - * @brief Global BSP definitions. - */ - -/*-------------------------------------------------------------------------+ -| bsp.h v1.1 - PC386 BSP - 1997/08/07 -+--------------------------------------------------------------------------+ -| This include file contains definitions related to the PC386 BSP. -+--------------------------------------------------------------------------+ -| (C) Copyright 1997 - -| - NavIST Group - Real-Time Distributed Systems and Industrial Automation -| -| http://pandora.ist.utl.pt -| -| Instituto Superior Tecnico * Lisboa * PORTUGAL -+--------------------------------------------------------------------------+ -| Modified by Eric Valette the 20/05/98 in order to add definitions used -| to enhance video putchar capabilities. -| -| Copyright (C) 1998 valette@crf.canon.fr -| -| Canon Centre Recherche France. -| -+--------------------------------------------------------------------------+ -| Disclaimer: -| -| This file is provided "AS IS" without warranty of any kind, either -| expressed or implied. -+--------------------------------------------------------------------------+ -| This code is based on: -| bsp.h,v 1.5 1995/12/19 20:07:30 joel Exp - go32 BSP -| With the following copyright notice: -| ************************************************************************** -| * COPYRIGHT (c) 1989-1999. -| * On-Line Applications Research Corporation (OAR). -| * -| * The license and distribution terms for this file may be -| * found in the file LICENSE in this distribution or at -| * http://www.rtems.org/license/LICENSE. -| ************************************************************************** -+--------------------------------------------------------------------------*/ - -#ifndef LIBBSP_I386_PC386_BSP_H -#define LIBBSP_I386_PC386_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <bsp/tblsizes.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/cpu.h> -#include <rtems/bspIo.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @degroup pc386_i386 PC386 Support - * - * @ingroup bsp_i386 - * - * @brief PC386 support. - */ - -#define BSP_HAS_FRAME_BUFFER 1 - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; - -/* app. may provide a routine (called _very_ early) to tell us - * which ports to use for printk / console. BSP provides a default - * implementation (weak alias) which does nothing (use BSP default - * ports). - */ -extern void -BSP_runtime_console_select(int *pPrintkPort, int *pConsolePort); - -extern int rtems_ne_driver_attach(struct rtems_bsdnet_ifconfig *, int); -#define BSP_NE2000_NETWORK_DRIVER_NAME "ne1" -#define BSP_NE2000_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach - -extern int rtems_wd_driver_attach(struct rtems_bsdnet_ifconfig *, int); -#define BSP_WD8003_NETWORK_DRIVER_NAME "wd1" -#define BSP_WD8003_NETWORK_DRIVER_ATTACH rtems_wd_driver_attach - -extern int rtems_dec21140_driver_attach(struct rtems_bsdnet_ifconfig *, int); -#define BSP_DEC21140_NETWORK_DRIVER_NAME "dc1" -#define BSP_DEC21140_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach - -extern int rtems_3c509_driver_attach(struct rtems_bsdnet_ifconfig *config); -#define BSP_3C509_NETWORK_DRIVER_NAME "3c1" -#define BSP_3C509_NETWORK_DRIVER_ATTACH rtems_3c509_driver_attach - -#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME -#define RTEMS_BSP_NETWORK_DRIVER_NAME BSP_DEC21140_NETWORK_DRIVER_NAME -#endif - -#ifndef RTEMS_BSP_NETWORK_DRIVER_ATTACH -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_DEC21140_NETWORK_DRIVER_ATTACH -#endif - -/*-------------------------------------------------------------------------+ -| Constants -+--------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------+ -| Constants relating to the 8254 (or 8253) programmable interval timers. -+--------------------------------------------------------------------------*/ -#define IO_TIMER1 0x40 - /* Port address of the control port and timer channels */ -#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ -#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ -#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ -#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ -#define TIMER_SEL0 0x00 /* select counter 0 */ -#define TIMER_SEL1 0x40 /* select counter 1 */ -#define TIMER_SEL2 0x80 /* select counter 2 */ -#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ -#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ -#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ -#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ -#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ -#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ -#define TIMER_LATCH 0x00 /* latch counter for reading */ -#define TIMER_LSB 0x10 /* r/w counter LSB */ -#define TIMER_MSB 0x20 /* r/w counter MSB */ -#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ -#define TIMER_BCD 0x01 /* count in BCD */ -#define TIMER_RD_BACK 0xc0 /* Read Back Command */ - /* READ BACK command layout in the Command Register */ -#define RB_NOT_COUNT 0x40 /* Don't select counter latch */ -#define RB_NOT_STATUS 0x20 /* Don't select status latch */ -#define RB_COUNT_0 0x02 /* Counter 0 latch */ -#define RB_COUNT_1 0x04 /* Counter 1 latch */ -#define RB_COUNT_2 0x08 /* Counter 2 latch */ -#define RB_OUTPUT 0x80 /* Output of the counter is 1 */ - -#define TIMER_TICK 1193182 /* The internal tick rate in ticks per second */ - -/*-------------------------------------------------------------------------+ -| Console Defines -| WARNING: These Values MUST match the order in -| Console_Configuration_Ports -+--------------------------------------------------------------------------*/ -#define BSP_CONSOLE_VGA 0 -#define BSP_CONSOLE_COM1 1 -#define BSP_CONSOLE_COM2 2 - -/*-------------------------------------------------------------------------+ -| Convert microseconds to ticks and ticks to microseconds. -+--------------------------------------------------------------------------*/ -#define US_TO_TICK(us) (((us)*105+44)/88) -#define TICK_TO_US(tk) (((tk)*88+52)/105) - -/*-------------------------------------------------------------------------+ -| External Variables. -+--------------------------------------------------------------------------*/ -extern interrupt_gate_descriptor Interrupt_descriptor_table[IDT_SIZE]; -extern segment_descriptors _Global_descriptor_table [GDT_SIZE]; - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ -void _IBMPC_initVideo(void); /* from 'outch.c' */ -void _IBMPC_outch (char); /* from 'outch.c' */ -char _IBMPC_inch (void); /* from 'inch.c' */ -char _IBMPC_inch_sleep (void); /* from 'inch.c' */ -int BSP_wait_polled_input(void); /* from 'inch.c' */ -int rtems_kbpoll( void ); /* from 'inch.c' */ -int getch( void ); /* from 'inch.c' */ -void add_to_queue( unsigned short b ); /* from 'inch.c' */ - -void Wait_X_ms(unsigned int timeToWait); /* from 'timer.c' */ -void Calibrate_loop_1ms(void); /* from 'timer.c' */ - -void rtems_irq_mngt_init(void); /* from 'irq_init.c' */ - -void bsp_size_memory(void); /* from 'bspstart.c' */ - -#if (BSP_IS_EDISON == 0) - void Clock_driver_install_handler(void); /* from 'ckinit.c' */ - void Clock_driver_support_initialize_hardware(void); /* from 'ckinit.c' */ -#else - /** - * @defgroup edison_bsp Clock Tick Support - * - * @ingroup i386_pc386 - * - * @brief Clock Tick Support Package - */ - Thread clock_driver_sim_idle_body(uintptr_t); - #define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - /* - * hack to kill some time. Hopefully hitting a hardware register is slower - * than an empty loop. - */ - #define BSP_CLOCK_DRIVER_DELAY() \ - do { \ - uint64_t _i = 2500000; \ - while (_i) { \ - _i--; \ - } \ - } while ( 0 ) -#endif /* edison */ - -void kbd_reset_setup(char *str, int *ints); /* from 'pc_keyb.c' */ -size_t read_aux(char * buffer, size_t count); /* from 'ps2_mouse.c' */ - -bool bsp_get_serial_mouse_device( /* from 'serial_mouse.c' */ - const char **name, - const char **type -); - -void register_leds( /* from 'keyboard.c' */ - int console, - unsigned int led, - unsigned int *addr, - unsigned int mask -); - -/* Definitions for BSPConsolePort */ -#define BSP_CONSOLE_PORT_CONSOLE (-1) -#define BSP_CONSOLE_PORT_COM1 (BSP_UART_COM1) -#define BSP_CONSOLE_PORT_COM2 (BSP_UART_COM2) - -/* - * Command line. - */ -const char* bsp_cmdline(void); -const char* bsp_cmdline_arg(const char* arg); - -#if BSP_ENABLE_IDE -/* - * IDE command line parsing. - */ -void bsp_ide_cmdline_init(void); - -/* - * indicate, that BSP has IDE driver - */ -#define RTEMS_BSP_HAS_IDE_DRIVER -#endif - -/* GDB stub stuff */ -void init_remote_gdb( void ); -void i386_stub_glue_init(int uart); -void i386_stub_glue_init_breakin(void); -void breakpoint(void); - -#define BSP_MAXIMUM_DEVICES 6 - -/* - * Debug helper methods - */ -typedef __FILE FILE; -uint32_t BSP_irq_count_dump(FILE *f); - -/* - * Prototypes just called from .S files. This lets the .S file include - * bsp.h just to establish the dependency. - */ -void raw_idt_notify(void); -void C_dispatch_isr(int vector); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif /* _BSP_H */ diff --git a/c/src/lib/libbsp/i386/pc386/include/tm27.h b/c/src/lib/libbsp/i386/pc386/include/tm27.h deleted file mode 100644 index b53ab8e97a..0000000000 --- a/c/src/lib/libbsp/i386/pc386/include/tm27.h +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file - * - * @ingroup i386_pc386 - * - * @brief Implementation of interrupt mechanisms for Time Test 27. - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector(handler) - -#define Cause_tm27_intr() __asm__ volatile("int $0x90" : :); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/i386/shared/comm/uart.h b/c/src/lib/libbsp/i386/shared/comm/uart.h deleted file mode 100644 index 96e4a312b4..0000000000 --- a/c/src/lib/libbsp/i386/shared/comm/uart.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * @file - * @ingroup i386_uart - * @brief i386 UART definitions - */ - -/* - * This software is Copyright (C) 1998 by T.sqware - all rights limited - * It is provided in to the public domain "as is", can be freely modified - * as far as this copyight notice is kept unchanged, but does not imply - * an endorsement by T.sqware of the product in which it is included. - */ - -/** - * @defgroup i386_uart UART - * @ingroup i386_comm - * @brief i386 UART definitions - * @{ - */ - -#ifndef _BSPUART_H -#define _BSPUART_H - -#ifdef __cplusplus -extern "C" { -#endif - -void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow); -void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits); -void BSP_uart_set_baud(int uart, unsigned long baud); -void BSP_uart_intr_ctrl(int uart, int cmd); -void BSP_uart_throttle(int uart); -void BSP_uart_unthrottle(int uart); -int BSP_uart_polled_status(int uart); -void BSP_uart_polled_write(int uart, int val); -int BSP_uart_polled_read(int uart); -void BSP_uart_termios_set(int uart, void *ttyp); -int BSP_uart_termios_read_com1(int uart); -int BSP_uart_termios_read_com2(int uart); -ssize_t BSP_uart_termios_write_com1(int minor, const char *buf, size_t len); -ssize_t BSP_uart_termios_write_com2(int minor, const char *buf, size_t len); -void BSP_uart_termios_isr_com1(void *); -void BSP_uart_termios_isr_com2(void *); -void BSP_uart_dbgisr_com1(void); -void BSP_uart_dbgisr_com2(void); -extern int BSP_poll_char_via_serial(void); -extern void BSP_output_char_via_serial(char val); -extern int BSPConsolePort; -extern int BSPBaseBaud; - -/** @brief - * Command values for BSP_uart_intr_ctrl(), - * values are strange in order to catch errors - * with assert - */ -#define BSP_UART_INTR_CTRL_DISABLE (0) -#define BSP_UART_INTR_CTRL_GDB (0xaa) ///< RX only -#define BSP_UART_INTR_CTRL_ENABLE (0xbb) ///< Normal operations -#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) ///< RX & line status - -/** @brief Return values for uart_polled_status() */ -#define BSP_UART_STATUS_ERROR (-1) ///< No character -#define BSP_UART_STATUS_NOCHAR (0) ///< No character -#define BSP_UART_STATUS_CHAR (1) ///< Character present -#define BSP_UART_STATUS_BREAK (2) ///< Break point is detected - -/** @brief PC UART definitions */ -#define BSP_UART_COM1 (0) -#define BSP_UART_COM2 (1) - -/** @brief - * Base IO for UART - */ - -#define COM1_BASE_IO 0x3F8 -#define COM2_BASE_IO 0x2F8 - -/** @brief - * Offsets from base - */ - -/** @brief DLAB 0 */ -#define RBR (0) ///< Rx Buffer Register (read) -#define THR (0) ///< Tx Buffer Register (write) -#define IER (1) ///< Interrupt Enable Register - -/** @brief DLAB X */ -#define IIR (2) ///< Interrupt Ident Register (read) -#define FCR (2) ///< FIFO Control Register (write) -#define LCR (3) ///< Line Control Register -#define MCR (4) ///< Modem Control Register -#define LSR (5) ///< Line Status Register -#define MSR (6) ///< Modem Status Register -#define SCR (7) ///< Scratch register - -/** @brief DLAB 1 */ -#define DLL (0) ///< Divisor Latch, LSB -#define DLM (1) ///< Divisor Latch, MSB -#define AFR (2) ///< Alternate Function register - -/** @brief - * Interrupt source definition via IIR - */ -#define MODEM_STATUS 0 -#define NO_MORE_INTR 1 -#define TRANSMITTER_HODING_REGISTER_EMPTY 2 -#define RECEIVER_DATA_AVAIL 4 -#define RECEIVER_ERROR 6 -#define CHARACTER_TIMEOUT_INDICATION 12 - -/** @brief - * Bits definition of IER - */ -#define RECEIVE_ENABLE 0x1 -#define TRANSMIT_ENABLE 0x2 -#define RECEIVER_LINE_ST_ENABLE 0x4 -#define MODEM_ENABLE 0x8 -#define INTERRUPT_DISABLE 0x0 - -/** @brief - * Bits definition of the Line Status Register (LSR) - */ -#define DR 0x01 ///< Data Ready -#define OE 0x02 ///< Overrun Error -#define PE 0x04 ///< Parity Error -#define FE 0x08 ///< Framing Error -#define BI 0x10 ///< Break Interrupt -#define THRE 0x20 ///< Transmitter Holding Register Empty -#define TEMT 0x40 ///< Transmitter Empty -#define ERFIFO 0x80 ///< Error receive Fifo - -/** @brief - * Bits definition of the MODEM Control Register (MCR) - */ -#define DTR 0x01 ///< Data Terminal Ready -#define RTS 0x02 ///< Request To Send -#define OUT_1 0x04 ///< Output 1, (reserved on COMPAQ I/O Board) -#define OUT_2 0x08 ///< Output 2, Enable Asynchronous Port Interrupts -#define LB 0x10 ///< Enable Internal Loop Back - -/** @brief - * Bits definition of the Line Control Register (LCR) - */ -#define CHR_5_BITS 0 -#define CHR_6_BITS 1 -#define CHR_7_BITS 2 -#define CHR_8_BITS 3 - -#define WL 0x03 ///< Word length mask -#define STB 0x04 ///< 1 Stop Bit, otherwise 2 Stop Bits -#define PEN 0x08 ///< Parity Enabled -#define EPS 0x10 ///< Even Parity Select, otherwise Odd -#define SP 0x20 ///< Stick Parity -#define BCB 0x40 ///< Break Control Bit -#define DLAB 0x80 ///< Enable Divisor Latch Access - -/** @brief - * Bits definition of the MODEM Status Register (MSR) - */ -#define DCTS 0x01 ///< Delta Clear To Send -#define DDSR 0x02 ///< Delta Data Set Ready -#define TERI 0x04 ///< Trailing Edge Ring Indicator -#define DDCD 0x08 ///< Delta Carrier Detect Indicator -#define CTS 0x10 ///< Clear To Send (when loop back is active) -#define DSR 0x20 ///< Data Set Ready (when loop back is active) -#define RI 0x40 ///< Ring Indicator (when loop back is active) -#define DCD 0x80 ///< Data Carrier Detect (when loop back is active) - -/** @brief - * Bits definition of the FIFO Control Register : WD16C552 or NS16550 - */ - -#define FIFO_CTRL 0x01 ///< Set to 1 permit access to other bits -#define FIFO_EN 0x01 ///< Enable the FIFO -#define XMIT_RESET 0x02 ///< Transmit FIFO Reset -#define RCV_RESET 0x04 ///< Receive FIFO Reset -#define FCR3 0x08 ///< do not understand manual! - -#define RECEIVE_FIFO_TRIGGER1 0x0 ///< trigger recieve interrupt after 1 byte -#define RECEIVE_FIFO_TRIGGER4 0x40 ///< trigger recieve interrupt after 4 byte -#define RECEIVE_FIFO_TRIGGER8 0x80 ///< trigger recieve interrupt after 8 byte -#define RECEIVE_FIFO_TRIGGER12 0xc0 ///< trigger recieve interrupt after 12 byte -#define TRIG_LEVEL 0xc0 ///< Mask for the trigger level - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _BSPUART_H */ diff --git a/c/src/lib/libbsp/i386/shared/irq/irq.h b/c/src/lib/libbsp/i386/shared/irq/irq.h deleted file mode 100644 index 095af423cf..0000000000 --- a/c/src/lib/libbsp/i386/shared/irq/irq.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * @file - * @ingroup i386_irq - * @brief Interrupt handlers - */ - -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1998 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/** - * @defgroup i386_irq Interrupt handlers - * @ingroup i386_shared - * @brief Data structure and the functions to write interrupt handlers - * @{ - */ - -#ifndef _IRQ_H_ -#define _IRQ_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief - * Include some preprocessor value also used by assember code - */ - -#include <bsp/irq_asm.h> -#include <rtems.h> -#define BSP_SHARED_HANDLER_SUPPORT 1 -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -/*-------------------------------------------------------------------------+ -| Constants -+--------------------------------------------------------------------------*/ - - /** @brief Base vector for our IRQ handlers. */ -#define BSP_IRQ_VECTOR_BASE BSP_ASM_IRQ_VECTOR_BASE -#define BSP_IRQ_LINES_NUMBER 17 -#define BSP_LOWEST_OFFSET 0 -#define BSP_MAX_ON_i8259S (BSP_IRQ_LINES_NUMBER - 2) -#define BSP_MAX_OFFSET (BSP_IRQ_LINES_NUMBER - 1) - /** @brief - * Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE - * NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE - * 2) The same name should be defined on all architecture - * so that handler connection can be unchanged. - */ -#define BSP_PERIODIC_TIMER 0 -#define BSP_KEYBOARD 1 -#define BSP_UART_COM2_IRQ 3 -#define BSP_UART_COM1_IRQ 4 -#define BSP_UART_COM3_IRQ 5 -#define BSP_UART_COM4_IRQ 6 -#define BSP_RT_TIMER1 8 -#define BSP_RT_TIMER3 10 -#define BSP_SMP_IPI 16 - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -/** @brief - * Type definition for RTEMS managed interrupts - */ -typedef unsigned short rtems_i8259_masks; - -/** - * @brief Contains the current IMR of both i8259s. - */ -extern rtems_i8259_masks i8259s_cache; - -/** - * @brief Contains the super IMR of both i8259s to overrule i8259s_cache during - * interrupt exit. - * - * This enables a bsp_interrupt_vector_disable() in interrupt handlers. This - * is required for the interrupt server support used by the new network stack. - */ -extern rtems_i8259_masks i8259s_super_imr; - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ -/* - * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- - */ - -/** @brief - * function to disable a particular irq at 8259 level. After calling - * this function, even if the device asserts the interrupt line it will - * not be propagated further to the processor - */ -int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); -/** @brief - * function to enable a particular irq at 8259 level. After calling - * this function, if the device asserts the interrupt line it will - * be propagated further to the processor - */ -int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); -/** @brief - * function to acknoledge a particular irq at 8259 level. After calling - * this function, if a device asserts an enabled interrupt line it will - * be propagated further to the processor. Mainly usefull for people - * writting raw handlers as this is automagically done for rtems managed - * handlers. - */ -int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); -/** @brief - * function to check if a particular irq is enabled at 8259 level. After calling - */ -int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* _IRQ_H_ */ diff --git a/c/src/lib/libbsp/lm32/lm32_evr/include/bsp.h b/c/src/lib/libbsp/lm32/lm32_evr/include/bsp.h deleted file mode 100644 index bee40d650f..0000000000 --- a/c/src/lib/libbsp/lm32/lm32_evr/include/bsp.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file - * - * @ingroup lm32_evr - * - * @brief Global BSP definitions. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, - * Micro-Research Finland Oy - */ - -#ifndef LIBBSP_LM32_LM32_EVR_BSP_H -#define LIBBSP_LM32_LM32_EVR_BSP_H - -#include <stdint.h> -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -/** - * @defgroup lm32_evr EVR Support - * - * @ingroup bsp_lm32 - * - * @brief EVR support package. - */ - -#if defined(RTEMS_NETWORKING) -#include <rtems/rtems_bsdnet.h> -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_DIRTY_MEMORY 1 - - /* - * lm32 requires certain aligment of mbuf because unaligned uint32_t - * accesses are not handled properly. - */ - -#define CPU_U32_FIX - -#if defined(RTEMS_NETWORKING) -extern int rtems_tsmac_driver_attach(struct rtems_bsdnet_ifconfig *config, - int attaching); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "TSMAC0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsmac_driver_attach - - /* - * Due to a hardware design error (RJ45 connector with 10baseT magnetics) - * we are forced to use 10baseT mode. - */ - -#define TSMAC_FORCE_10BASET -#endif - -/* functions */ -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -/* - * Prototypes for BSP methods that cross file boundaries - */ -void BSP_uart_polled_write(char ch); -int BSP_uart_polled_read( void ); -char BSP_uart_is_character_ready(char *ch); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libbsp/lm32/lm32_evr/include/coverhd.h b/c/src/lib/libbsp/lm32/lm32_evr/include/coverhd.h deleted file mode 100644 index bdef537e71..0000000000 --- a/c/src/lib/libbsp/lm32/lm32_evr/include/coverhd.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * @file - * - * @ingroup lm32_evr - * - * @brief C overhead definitions. - */ - -/* coverhd.h - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 0 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 0 -#define CALLING_OVERHEAD_CLOCK_SET 0 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 0 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 0 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 0 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#endif diff --git a/c/src/lib/libbsp/lm32/lm32_evr/include/system_conf.h b/c/src/lib/libbsp/lm32/lm32_evr/include/system_conf.h deleted file mode 100644 index 41f17e2be0..0000000000 --- a/c/src/lib/libbsp/lm32/lm32_evr/include/system_conf.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - * @file - * - * @ingroup lm32_evr - * - * @brief System configuration. - */ - -#ifndef __SYSTEM_CONFIG_H_ -#define __SYSTEM_CONFIG_H_ - - -#define FPGA_DEVICE_FAMILY "ECP2M" -#define PLATFORM_NAME "platform1" -#define USE_PLL (0) -#define CPU_FREQUENCY (75000000) - - -/* FOUND 1 CPU UNIT(S) */ - -/* - * CPU Instance LM32 component configuration - */ -#define CPU_NAME "LM32" -#define CPU_EBA (0x04000000) -#define CPU_DIVIDE_ENABLED (1) -#define CPU_SIGN_EXTEND_ENABLED (1) -#define CPU_MULTIPLIER_ENABLED (1) -#define CPU_SHIFT_ENABLED (1) -#define CPU_DEBUG_ENABLED (1) -#define CPU_HW_BREAKPOINTS_ENABLED (0) -#define CPU_NUM_HW_BREAKPOINTS (0) -#define CPU_NUM_WATCHPOINTS (0) -#define CPU_ICACHE_ENABLED (1) -#define CPU_ICACHE_SETS (512) -#define CPU_ICACHE_ASSOC (1) -#define CPU_ICACHE_BYTES_PER_LINE (16) -#define CPU_DCACHE_ENABLED (1) -#define CPU_DCACHE_SETS (512) -#define CPU_DCACHE_ASSOC (1) -#define CPU_DCACHE_BYTES_PER_LINE (16) -#define CPU_DEBA (0x0C000000) -#define CPU_CHARIO_IN (1) -#define CPU_CHARIO_OUT (1) -#define CPU_CHARIO_TYPE "JTAG UART" - -/* - * gpio component configuration - */ -#define GPIO_NAME "gpio" -#define GPIO_BASE_ADDRESS (0x80004000) -#define GPIO_SIZE (128) -#define GPIO_CHARIO_IN (0) -#define GPIO_CHARIO_OUT (0) -#define GPIO_ADDRESS_LOCK (1) -#define GPIO_DISABLE (0) -#define GPIO_OUTPUT_PORTS_ONLY (1) -#define GPIO_INPUT_PORTS_ONLY (0) -#define GPIO_TRISTATE_PORTS (0) -#define GPIO_BOTH_INPUT_AND_OUTPUT (0) -#define GPIO_DATA_WIDTH (4) -#define GPIO_INPUT_WIDTH (1) -#define GPIO_OUTPUT_WIDTH (1) -#define GPIO_IRQ_MODE (0) -#define GPIO_LEVEL (0) -#define GPIO_EDGE (0) -#define GPIO_EITHER_EDGE_IRQ (0) -#define GPIO_POSE_EDGE_IRQ (0) -#define GPIO_NEGE_EDGE_IRQ (0) - -/* - * uart component configuration - */ -#define UART_NAME "uart" -#define UART_BASE_ADDRESS (0x80006000) -#define UART_SIZE (128) -#define UART_IRQ (0) -#define UART_CHARIO_IN (1) -#define UART_CHARIO_OUT (1) -#define UART_CHARIO_TYPE "RS-232" -#define UART_ADDRESS_LOCK (1) -#define UART_DISABLE (0) -#define UART_MODEM (0) -#define UART_ADDRWIDTH (5) -#define UART_DATAWIDTH (8) -#define UART_BAUD_RATE (115200) -#define UART_IB_SIZE (4) -#define UART_OB_SIZE (4) -#define UART_BLOCK_WRITE (1) -#define UART_BLOCK_READ (1) -#define UART_DATA_BITS (8) -#define UART_STOP_BITS (1) -#define UART_FIFO (0) -#define UART_INTERRUPT_DRIVEN (1) - -/* - * ebr component configuration - */ -#define EBR_NAME "ebr" -#define EBR_BASE_ADDRESS (0x04000000) -#define EBR_SIZE (32768) -#define EBR_IS_READABLE (1) -#define EBR_IS_WRITABLE (1) -#define EBR_ADDRESS_LOCK (1) -#define EBR_DISABLE (0) -#define EBR_EBR_DATA_WIDTH (32) -#define EBR_INIT_FILE_NAME "none" -#define EBR_INIT_FILE_FORMAT "hex" - -/* - * ts_mac_core component configuration - */ -#define TS_MAC_CORE_NAME "ts_mac_core" -#define TS_MAC_CORE_BASE_ADDRESS (0x80008000) -#define TS_MAC_CORE_SIZE (8192) -#define TS_MAC_CORE_IRQ (2) -#define TS_MAC_CORE_CHARIO_IN (0) -#define TS_MAC_CORE_CHARIO_OUT (0) -#define TS_MAC_CORE_ADDRESS_LOCK (1) -#define TS_MAC_CORE_DISABLE (0) -#define TS_MAC_CORE_STAT_REGS (1) -#define TS_MAC_CORE_TXRX_FIFO_DEPTH (512) -#define TS_MAC_CORE_MIIM_MODULE (1) -#define TS_MAC_CORE_NGO "l:/mrf/lattice/crio-lm32/platform1/components/ts_mac_top_v27/ipexpress/ts_mac_core/ts_mac_core.ngo" -#define TS_MAC_CORE_ISPLEVER_PRJ "l:/mrf/lattice/crio-lm32/criomico.syn" - -/* - * timer0 component configuration - */ -#define TIMER0_NAME "timer0" -#define TIMER0_BASE_ADDRESS (0x80002000) -#define TIMER0_SIZE (128) -#define TIMER0_IRQ (1) -#define TIMER0_CHARIO_IN (0) -#define TIMER0_CHARIO_OUT (0) -#define TIMER0_ADDRESS_LOCK (1) -#define TIMER0_DISABLE (0) -#define TIMER0_PERIOD_NUM (20) -#define TIMER0_PERIOD_WIDTH (32) -#define TIMER0_WRITEABLE_PERIOD (1) -#define TIMER0_READABLE_SNAPSHOT (1) -#define TIMER0_START_STOP_CONTROL (1) -#define TIMER0_WATCHDOG (0) - -/* - * timer1 component configuration - */ -#define TIMER1_NAME "timer1" -#define TIMER1_BASE_ADDRESS (0x8000A000) -#define TIMER1_SIZE (128) -#define TIMER1_IRQ (3) -#define TIMER1_CHARIO_IN (0) -#define TIMER1_CHARIO_OUT (0) -#define TIMER1_ADDRESS_LOCK (1) -#define TIMER1_DISABLE (0) -#define TIMER1_PERIOD_NUM (20) -#define TIMER1_PERIOD_WIDTH (32) -#define TIMER1_WRITEABLE_PERIOD (1) -#define TIMER1_READABLE_SNAPSHOT (1) -#define TIMER1_START_STOP_CONTROL (1) -#define TIMER1_WATCHDOG (0) - -/* - * ddr2_sdram component configuration - */ -#define DDR2_SDRAM_NAME "ddr2_sdram" -#define DDR2_SDRAM_BASE_ADDRESS (0x08000000) -#define DDR2_SDRAM_SIZE (33554432) -#define DDR2_SDRAM_IS_READABLE (1) -#define DDR2_SDRAM_IS_WRITABLE (1) -#define DDR2_SDRAM_BST_CNT_READ (1) -#define DDR2_SDRAM_ADDRESS_LOCK (1) -#define DDR2_SDRAM_DISABLE (0) -#define DDR2_SDRAM_NGO "L:/mrf/lattice/cRIO-LM32/platform1/components/wb_ddr2_ctl_v65/ipexpress/ddr2_sdram/ddr2_sdram.ngo" -#define DDR2_SDRAM_ISPLEVER_PRJ "l:/mrf/lattice/crio-lm32/criomico.syn" -#define DDR2_SDRAM_PARAM_FILE "ddr_p_eval/$/src/params/ddr_sdram_mem_params.v" -#define DDR2_SDRAM_MEM_TOP "ddr_p_eval/$/src/rtl/top/@/ddr_sdram_mem_top.v" - - -#endif /* __SYSTEM_CONFIG_H_ */ diff --git a/c/src/lib/libbsp/lm32/lm32_evr/include/tm27.h b/c/src/lib/libbsp/lm32/lm32_evr/include/tm27.h deleted file mode 100644 index f62e62e73f..0000000000 --- a/c/src/lib/libbsp/lm32/lm32_evr/include/tm27.h +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file - * - * @ingroup lm32_evr - * - * @brief TM27 timing test routines. - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) - -#define Cause_tm27_intr() /* empty */ - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/lm32/milkymist/include/bsp.h b/c/src/lib/libbsp/lm32/milkymist/include/bsp.h deleted file mode 100644 index 3813a03551..0000000000 --- a/c/src/lib/libbsp/lm32/milkymist/include/bsp.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * @file - * - * @ingroup lm32_milkymist - * - * @brief Global BSP definitions. - */ - -/* bsp.h - * - * This include file contains all board IO definitions. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * COPYRIGHT (c) 2011 Sebastien Bourdeauducq - */ - -#ifndef LIBBSP_LM32_MILKYMIST_BSP_H -#define LIBBSP_LM32_MILKYMIST_BSP_H - -#include <stdint.h> -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -/** - * @defgroup lm32_milkymist Milkymist Support - * - * @ingroup bsp_lm32 - * - * @brief Milkymist support package. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_HAS_FRAME_BUFFER 1 - -/* - * lm32 requires certain aligment of mbuf because unaligned uint32_t - * accesses are not handled properly. - */ - -#define CPU_U32_FIX - -#if defined(RTEMS_NETWORKING) -#include <rtems/rtems_bsdnet.h> -struct rtems_bsdnet_ifconfig; -extern int rtems_minimac_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_minimac_driver_attach -#define RTEMS_BSP_NETWORK_DRIVER_NAME "minimac0" -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h b/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h deleted file mode 100644 index 8ba4a1cf43..0000000000 --- a/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h +++ /dev/null @@ -1,329 +0,0 @@ -/** - * @file - * - * @ingroup lm32_milkymist - * - * @brief System configuration. - */ - -/* system_conf.h - * Global System conf - * - * Milkymist port of RTEMS - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * COPYRIGHT (c) 2010, 2011 Sebastien Bourdeauducq - */ - -#ifndef __SYSTEM_CONFIG_H_ -#define __SYSTEM_CONFIG_H_ - -#define UART_BAUD_RATE (115200) - -/* Clock frequency */ -#define MM_FREQUENCY (0xe0001074) - -/* FML bridge */ -#define FMLBRG_FLUSH_BASE (0xc8000000) -#define FMLBRG_LINE_LENGTH (32) -#define FMLBRG_LINE_COUNT (512) - -/* UART */ -#define MM_UART_RXTX (0xe0000000) -#define MM_UART_DIV (0xe0000004) -#define MM_UART_STAT (0xe0000008) -#define MM_UART_CTRL (0xe000000c) - -#define UART_STAT_THRE (0x1) -#define UART_STAT_RX_EVT (0x2) -#define UART_STAT_TX_EVT (0x4) - -#define UART_CTRL_RX_INT (0x1) -#define UART_CTRL_TX_INT (0x2) -#define UART_CTRL_THRU (0x4) - -/* Timers */ -#define MM_TIMER1_COMPARE (0xe0001024) -#define MM_TIMER1_COUNTER (0xe0001028) -#define MM_TIMER1_CONTROL (0xe0001020) - -#define MM_TIMER0_COMPARE (0xe0001014) -#define MM_TIMER0_COUNTER (0xe0001018) -#define MM_TIMER0_CONTROL (0xe0001010) - -#define TIMER_ENABLE (0x01) -#define TIMER_AUTORESTART (0x02) - -/* GPIO */ -#define MM_GPIO_IN (0xe0001000) -#define MM_GPIO_OUT (0xe0001004) -#define MM_GPIO_INTEN (0xe0001008) - -#define GPIO_BTN1 (0x00000001) -#define GPIO_BTN2 (0x00000002) -#define GPIO_BTN3 (0x00000004) -#define GPIO_PCBREV0 (0x00000008) -#define GPIO_PCBREV1 (0x00000010) -#define GPIO_PCBREV2 (0x00000020) -#define GPIO_PCBREV3 (0x00000040) -#define GPIO_LED1 (0x00000001) -#define GPIO_LED2 (0x00000002) - -/* System ID and reset */ -#define MM_SYSTEM_ID (0xe000107c) - -/* ICAP */ -#define MM_ICAP (0xe0001040) - -#define ICAP_READY (0x01) -#define ICAP_CE (0x10000) -#define ICAP_WRITE (0x20000) - -/* VGA */ -#define MM_VGA_RESET (0xe0003000) - -#define MM_VGA_HRES (0xe0003004) -#define MM_VGA_HSYNC_START (0xe0003008) -#define MM_VGA_HSYNC_END (0xe000300C) -#define MM_VGA_HSCAN (0xe0003010) - -#define MM_VGA_VRES (0xe0003014) -#define MM_VGA_VSYNC_START (0xe0003018) -#define MM_VGA_VSYNC_END (0xe000301C) -#define MM_VGA_VSCAN (0xe0003020) - -#define MM_VGA_BASEADDRESS (0xe0003024) -#define MM_VGA_BASEADDRESS_ACT (0xe0003028) - -#define MM_VGA_BURST_COUNT (0xe000302C) - -#define MM_VGA_DDC (0xe0003030) - -#define MM_VGA_CLKSEL (0xe0003034) - -#define VGA_RESET (0x01) -#define VGA_DDC_SDAIN (0x1) -#define VGA_DDC_SDAOUT (0x2) -#define VGA_DDC_SDAOE (0x4) -#define VGA_DDC_SDC (0x8) - -/* Ethernet */ -#define MM_MINIMAC_SETUP (0xe0008000) -#define MM_MINIMAC_MDIO (0xe0008004) - -#define MM_MINIMAC_STATE0 (0xe0008008) -#define MM_MINIMAC_COUNT0 (0xe000800C) -#define MM_MINIMAC_STATE1 (0xe0008010) -#define MM_MINIMAC_COUNT1 (0xe0008014) - -#define MM_MINIMAC_TXCOUNT (0xe0008018) - -#define MINIMAC_RX0_BASE (0xb0000000) -#define MINIMAC_RX1_BASE (0xb0000800) -#define MINIMAC_TX_BASE (0xb0001000) - -#define MINIMAC_SETUP_PHYRST (0x1) - -#define MINIMAC_STATE_EMPTY (0x0) -#define MINIMAC_STATE_LOADED (0x1) -#define MINIMAC_STATE_PENDING (0x2) - -/* AC97 */ -#define MM_AC97_CRCTL (0xe0005000) - -#define AC97_CRCTL_RQEN (0x01) -#define AC97_CRCTL_WRITE (0x02) - -#define MM_AC97_CRADDR (0xe0005004) -#define MM_AC97_CRDATAOUT (0xe0005008) -#define MM_AC97_CRDATAIN (0xe000500C) - -#define MM_AC97_DCTL (0xe0005010) -#define MM_AC97_DADDRESS (0xe0005014) -#define MM_AC97_DREMAINING (0xe0005018) - -#define MM_AC97_UCTL (0xe0005020) -#define MM_AC97_UADDRESS (0xe0005024) -#define MM_AC97_UREMAINING (0xe0005028) - -#define AC97_SCTL_EN (0x01) - -#define AC97_MAX_DMASIZE (0x3fffc) - -/* SoftUSB */ -#define MM_SOFTUSB_CONTROL (0xe000f000) - -#define SOFTUSB_CONTROL_RESET (0x1) - -#define MM_SOFTUSB_PMEM_BASE (0xa0000000) -#define MM_SOFTUSB_DMEM_BASE (0xa0020000) - -#define SOFTUSB_PMEM_SIZE (1 << 13) -#define SOFTUSB_DMEM_SIZE (1 << 13) - -/* PFPU */ -#define MM_PFPU_CTL (0xe0006000) -#define PFPU_CTL_START (0x01) -#define PFPU_CTL_BUSY (0x01) - -#define MM_PFPU_MESHBASE (0xe0006004) -#define MM_PFPU_HMESHLAST (0xe0006008) -#define MM_PFPU_VMESHLAST (0xe000600C) - -#define MM_PFPU_CODEPAGE (0xe0006010) - -#define MM_PFPU_DREGBASE (0xe0006400) -#define MM_PFPU_CODEBASE (0xe0006800) - -#define PFPU_PAGESIZE (512) -#define PFPU_SPREG_COUNT (2) -#define PFPU_REG_X (0) -#define PFPU_REG_Y (1) - -/* TMU */ -#define MM_TMU_CTL (0xe0007000) -#define TMU_CTL_START (0x01) -#define TMU_CTL_BUSY (0x01) -#define TMU_CTL_CHROMAKEY (0x02) - -#define MM_TMU_HMESHLAST (0xe0007004) -#define MM_TMU_VMESHLAST (0xe0007008) -#define MM_TMU_BRIGHTNESS (0xe000700C) -#define MM_TMU_CHROMAKEY (0xe0007010) - -#define MM_TMU_VERTICESADR (0xe0007014) -#define MM_TMU_TEXFBUF (0xe0007018) -#define MM_TMU_TEXHRES (0xe000701C) -#define MM_TMU_TEXVRES (0xe0007020) -#define MM_TMU_TEXHMASK (0xe0007024) -#define MM_TMU_TEXVMASK (0xe0007028) - -#define MM_TMU_DSTFBUF (0xe000702C) -#define MM_TMU_DSTHRES (0xe0007030) -#define MM_TMU_DSTVRES (0xe0007034) -#define MM_TMU_DSTHOFFSET (0xe0007038) -#define MM_TMU_DSTVOFFSET (0xe000703C) -#define MM_TMU_DSTSQUAREW (0xe0007040) -#define MM_TMU_DSTSQUAREH (0xe0007044) - -#define MM_TMU_ALPHA (0xe0007048) - -/* Memory card */ -#define MM_MEMCARD_CLK2XDIV (0xe0004000) - -#define MM_MEMCARD_ENABLE (0xe0004004) - -#define MEMCARD_ENABLE_CMD_TX (0x1) -#define MEMCARD_ENABLE_CMD_RX (0x2) -#define MEMCARD_ENABLE_DAT_TX (0x4) -#define MEMCARD_ENABLE_DAT_RX (0x8) - -#define MM_MEMCARD_PENDING (0xe0004008) - -#define MEMCARD_PENDING_CMD_TX (0x1) -#define MEMCARD_PENDING_CMD_RX (0x2) -#define MEMCARD_PENDING_DAT_TX (0x4) -#define MEMCARD_PENDING_DAT_RX (0x8) - -#define MM_MEMCARD_START (0xe000400c) - -#define MEMCARD_START_CMD_RX (0x1) -#define MEMCARD_START_DAT_RX (0x2) - -#define MM_MEMCARD_CMD (0xe0004010) -#define MM_MEMCARD_DAT (0xe0004014) - -/* DMX */ -#define MM_DMX_TX(x) (0xe000c000+4*(x)) -#define MM_DMX_THRU (0xe000c800) -#define MM_DMX_RX(x) (0xe000d000+4*(x)) - -/* MIDI */ -#define MM_MIDI_RXTX (0xe000b000) -#define MM_MIDI_DIV (0xe000b004) -#define MM_MIDI_STAT (0xe000b008) -#define MM_MIDI_CTRL (0xe000b00c) - -#define MIDI_STAT_THRE (0x1) -#define MIDI_STAT_RX_EVT (0x2) -#define MIDI_STAT_TX_EVT (0x4) - -#define MIDI_CTRL_RX_INT (0x1) -#define MIDI_CTRL_TX_INT (0x2) -#define MIDI_CTRL_THRU (0x4) - -/* IR */ -#define MM_IR_RX (0xe000e000) - -/* Video input */ -#define MM_BT656_I2C (0xe000a000) -#define MM_BT656_FILTERSTATUS (0xe000a004) -#define MM_BT656_BASE (0xe000a008) -#define MM_BT656_MAXBURSTS (0xe000a00c) -#define MM_BT656_DONEBURSTS (0xe000a010) - -#define BT656_I2C_SDAIN (0x1) -#define BT656_I2C_SDAOUT (0x2) -#define BT656_I2C_SDAOE (0x4) -#define BT656_I2C_SDC (0x8) - -#define BT656_FILTER_FIELD1 (0x1) -#define BT656_FILTER_FIELD2 (0x2) -#define BT656_FILTER_INFRAME (0x4) - -/* Interrupts */ -#define MM_IRQ_UART (0) -#define MM_IRQ_GPIO (1) -#define MM_IRQ_TIMER0 (2) -#define MM_IRQ_TIMER1 (3) -#define MM_IRQ_AC97CRREQUEST (4) -#define MM_IRQ_AC97CRREPLY (5) -#define MM_IRQ_AC97DMAR (6) -#define MM_IRQ_AC97DMAW (7) -#define MM_IRQ_PFPU (8) -#define MM_IRQ_TMU (9) -#define MM_IRQ_ETHRX (10) -#define MM_IRQ_ETHTX (11) -#define MM_IRQ_VIDEOIN (12) -#define MM_IRQ_MIDI (13) -#define MM_IRQ_IR (14) -#define MM_IRQ_USB (15) - -/* Flash layout */ -#define FLASH_BASE (0x80000000) - -#define FLASH_OFFSET_STANDBY_BITSTREAM (0x80000000) - -#define FLASH_OFFSET_RESCUE_BITSTREAM (0x800A0000) -#define FLASH_OFFSET_RESCUE_BIOS (0x80220000) -#define FLASH_OFFSET_MAC_ADDRESS (0x802200E0) -#define FLASH_OFFSET_RESCUE_SPLASH (0x80240000) -#define FLASH_OFFSET_RESCUE_APP (0x802E0000) - -#define FLASH_OFFSET_REGULAR_BITSTREAM (0x806E0000) -#define FLASH_OFFSET_REGULAR_BIOS (0x80860000) -#define FLASH_OFFSET_REGULAR_SPLASH (0x80880000) -#define FLASH_OFFSET_REGULAR_APP (0x80920000) - -/* MMIO */ -#define MM_READ(reg) (*((volatile unsigned int *)(reg))) -#define MM_WRITE(reg, val) *((volatile unsigned int *)(reg)) = val - -/* Flash partitions */ - -#define FLASH_SECTOR_SIZE (128*1024) - -#define FLASH_PARTITION_COUNT (5) - -#define FLASH_PARTITIONS { \ - { .start_address = 0x806E0000, .length = 0x0180000 }, \ - { .start_address = 0x80860000, .length = 0x0020000 }, \ - { .start_address = 0x80880000, .length = 0x00A0000 }, \ - { .start_address = 0x80920000, .length = 0x0400000 }, \ - { .start_address = 0x80D20000, .length = 0x12E0000 }, \ -} - -#endif /* __SYSTEM_CONFIG_H_ */ diff --git a/c/src/lib/libbsp/lm32/shared/include/irq.h b/c/src/lib/libbsp/lm32/shared/include/irq.h deleted file mode 100644 index b1ccd66339..0000000000 --- a/c/src/lib/libbsp/lm32/shared/include/irq.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief BSP interrupt support for LM32. - */ - -/* - * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. - * - * Copyright (c) 2008, 2009, 2010 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_LM32_IRQ_CONFIG_H -#define LIBBSP_LM32_IRQ_CONFIG_H - -#include <stdint.h> - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -/** - * @brief Minimum vector number. - */ -#define BSP_INTERRUPT_VECTOR_MIN 0 - -/** - * @brief Maximum vector number. - */ -#define BSP_INTERRUPT_VECTOR_MAX 31 - -/** @} */ - -#endif /* LIBBSP_LM32_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/m32c/m32cbsp/include/bsp.h b/c/src/lib/libbsp/m32c/m32cbsp/include/bsp.h deleted file mode 100644 index 2889808fd8..0000000000 --- a/c/src/lib/libbsp/m32c/m32cbsp/include/bsp.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @ingroup m32c_bsp - * - * @brief m32c simulator definitions in gdb - */ - -/* bsp.h - * - * This include file contains some definitions specific to the - * h8 simulator in gdb. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M32C_M32CBSP_BSP_H -#define LIBBSP_M32C_M32CBSP_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup m32c_bsp Clock Tick Support - * - * @ingroup m32c_m32cbsp - * - * @brief Clock Tick Support Package - */ - -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m32r/m32rsim/include/bsp.h b/c/src/lib/libbsp/m32r/m32rsim/include/bsp.h deleted file mode 100644 index 1a30ce658c..0000000000 --- a/c/src/lib/libbsp/m32r/m32rsim/include/bsp.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * - * @ingroup m32r_bsp - * - * @brief m32r definitions in gdb - */ - -/* bsp.h - * - * This include file contains some definitions specific to the - * h8 simulator in gdb. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M32R_M32RSIM_BSP_H -#define LIBBSP_M32R_M32RSIM_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup m32r_bsp Clock Tick Support - * - * @ingroup m32r_m32rsim - * - * @brief Clock Tick Support Package - */ - -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -/* Trap support interface from Newlib 1.16.0 */ -#define SYS_exit 1 -#define SYS_open 2 -#define SYS_close 3 -#define SYS_read 4 -#define SYS_write 5 -#define SYS_lseek 6 -#define SYS_unlink 7 -#define SYS_getpid 8 -#define SYS_kill 9 -#define SYS_fstat 10 - -int __trap0 (int function, int p1, int p2, int p3, struct _reent *r); - -#define TRAP0(f, p1, p2, p3) \ - __trap0 (f, (int) (p1), (int) (p2), (int) (p3), _REENT) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m32r/m32rsim/include/tm27.h b/c/src/lib/libbsp/m32r/m32rsim/include/tm27.h deleted file mode 100644 index a775386b9e..0000000000 --- a/c/src/lib/libbsp/m32r/m32rsim/include/tm27.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * @file - * - * @ingroup m32r_tm27 - * - * @brief Time Test 27 - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup m32r_tm27 Time Test 27 - * - * @ingroup m32r_m32rsim - * - * @brief Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ - -#define Cause_tm27_intr() /* XXX */ - -#define Clear_tm27_intr() /* XXX */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/av5282/include/bsp.h b/c/src/lib/libbsp/m68k/av5282/include/bsp.h deleted file mode 100644 index d663df674d..0000000000 --- a/c/src/lib/libbsp/m68k/av5282/include/bsp.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * @file - * - * @ingroup m68k_av5282 - * - * @brief Global BSP definitions. - */ - -/* - * av5282 BSP header file - */ - -/** - * @defgroup m68k_av5282 AV5282 Support - * - * @ingroup bsp_m68k - * - * @brief AV5282 support. - */ - -#ifndef LIBBSP_M68K_AV5282_BSP_H -#define LIBBSP_M68K_AV5282_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************/ -/** Network driver configuration **/ -struct rtems_bsdnet_ifconfig; -extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define which port the console should use - all other ports are then defined as general purpose */ -#define CONSOLE_PORT 0 - -/* externals */ - -/* constants */ - -/* miscellaneous stuff assumed to exist */ - -/* functions */ - -uint32_t get_CPU_clock_speed(void); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ -#define FEC_IRQ_LEVEL 4 -#define FEC_IRQ_RX_PRIORITY 7 -#define FEC_IRQ_TX_PRIORITY 6 - -#define PIT3_IRQ_LEVEL 4 -#define PIT3_IRQ_PRIORITY 0 - -#define UART0_IRQ_LEVEL 3 -#define UART0_IRQ_PRIORITY 7 -#define UART1_IRQ_LEVEL 3 -#define UART1_IRQ_PRIORITY 6 -#define UART2_IRQ_LEVEL 3 -#define UART2_IRQ_PRIORITY 5 - -/* - * Prototypes for methods called from .S to alow dependency tracking - */ -void Init5282(void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ -#endif diff --git a/c/src/lib/libbsp/m68k/av5282/include/tm27.h b/c/src/lib/libbsp/m68k/av5282/include/tm27.h deleted file mode 100644 index 1e1dc77e59..0000000000 --- a/c/src/lib/libbsp/m68k/av5282/include/tm27.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * @file - * - * @ingroup m68k_av5282 - * - * @brief Time Test 27 routines. - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/csb360/include/bsp.h b/c/src/lib/libbsp/m68k/csb360/include/bsp.h deleted file mode 100644 index 7217d160ca..0000000000 --- a/c/src/lib/libbsp/m68k/csb360/include/bsp.h +++ /dev/null @@ -1,192 +0,0 @@ -/** - * @file - * - * @ingroup m68k_csb360 - * - * @brief Global BSP definitions. - */ - -/* - * Board Support Package for CSB360 evaluation board - * BSP definitions - * - * Copyright 2004 Cogent Computer Systems - * Author: Jay Monkman <jtm@lopingdog.com> - * - * Derived from mcf5206elite BSP: - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_CSB360_BSP_H -#define LIBBSP_M68K_CSB360_BSP_H - -#include <mcf5272/mcf5272.h> - -/** - * @defgroup m68k_csb360 CSB360 Support - * - * @ingroup bsp_m68k - * - * @brief CSB360 support. - */ - - -/*** Board resources allocation ***/ -#define BSP_MEM_ADDR_SRAM 0x20000000 -#define BSP_MEM_SIZE_SRAM 4096 - -/* Location and size of sdram. Note this includes space used by - * umon. - */ -#define BSP_MEM_ADDR_SDRAM 0x00000000 -#define BSP_MEM_MASK_SDRAM 0x01ffffff -#define BSP_MEM_SIZE_SDRAM (32 * 1024 * 1024) - -/* Address to put SIM Modules */ -#define BSP_MBAR 0x10000000 - -/* Address to put SRAM */ -#define BSP_RAMBAR BSP_MEM_ADDR_SRAM - -/* Interrupt Vectors */ -#define BSP_INTVEC_INT1 65 -#define BSP_INTVEC_INT2 66 -#define BSP_INTVEC_INT3 67 -#define BSP_INTVEC_INT4 68 -#define BSP_INTVEC_TMR0 69 -#define BSP_INTVEC_TMR1 70 -#define BSP_INTVEC_TMR2 71 -#define BSP_INTVEC_TMR3 72 -#define BSP_INTVEC_UART1 73 -#define BSP_INTVEC_UART2 74 -#define BSP_INTVEC_PLIP 75 -#define BSP_INTVEC_PLIA 76 -#define BSP_INTVEC_USB0 77 -#define BSP_INTVEC_USB1 78 -#define BSP_INTVEC_USB2 79 -#define BSP_INTVEC_USB3 80 -#define BSP_INTVEC_USB4 81 -#define BSP_INTVEC_USB5 82 -#define BSP_INTVEC_USB6 83 -#define BSP_INTVEC_USB7 84 -#define BSP_INTVEC_DMA 85 -#define BSP_INTVEC_ERX 86 -#define BSP_INTVEC_ETX 87 -#define BSP_INTVEC_ENTC 88 -#define BSP_INTVEC_QSPI 89 -#define BSP_INTVEC_INT5 90 -#define BSP_INTVEC_INT6 91 -#define BSP_INTVEC_SWTO 92 - -#define BSP_INTLVL_INT1 1 -#define BSP_INTLVL_INT2 1 -#define BSP_INTLVL_INT3 1 -#define BSP_INTLVL_INT4 1 -#define BSP_INTLVL_TMR0 1 -#define BSP_INTLVL_TMR1 1 -#define BSP_INTLVL_TMR2 1 -#define BSP_INTLVL_TMR3 1 -#define BSP_INTLVL_UART1 1 -#define BSP_INTLVL_UART2 1 -#define BSP_INTLVL_PLIP 1 -#define BSP_INTLVL_PLIA 1 -#define BSP_INTLVL_USB0 1 -#define BSP_INTLVL_USB1 1 -#define BSP_INTLVL_USB2 1 -#define BSP_INTLVL_USB3 1 -#define BSP_INTLVL_USB4 1 -#define BSP_INTLVL_USB5 1 -#define BSP_INTLVL_USB6 1 -#define BSP_INTLVL_USB7 1 -#define BSP_INTLVL_DMA 1 -#define BSP_INTLVL_ERX 1 -#define BSP_INTLVL_ETX 1 -#define BSP_INTLVL_ENTC 1 -#define BSP_INTLVL_QSPI 1 -#define BSP_INTLVL_INT5 1 -#define BSP_INTLVL_INT6 1 -#define BSP_INTLVL_SWTO 1 - - - -#ifndef ASM - -#include <bspopts.h> -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/clockdrv.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -struct rtems_bsdnet_ifconfig; -extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach - -/* System frequency */ -#define BSP_SYSTEM_FREQUENCY (66 * 1000 * 1000) - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define delay( microseconds ) \ - { register uint32_t _delay=(microseconds); \ - register uint32_t _tmp=123; \ - __asm__ volatile( "0: \ - nbcd %0 ; \ - nbcd %0 ; \ - dbf %1,0b" \ - : "=d" (_tmp), "=d" (_delay) \ - : "0" (_tmp), "1" (_delay) ); \ - } - -/* - * Real-Time Clock Driver Table Entry - * NOTE: put this entry to the device driver table AFTER I2C bus driver! - */ -#define RTC_DRIVER_TABLE_ENTRY \ - { rtc_initialize, NULL, NULL, NULL, NULL, NULL } -extern rtems_device_driver rtc_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -); - -/* miscellaneous stuff assumed to exist */ - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void init5272(void); - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif diff --git a/c/src/lib/libbsp/m68k/csb360/include/coverhd.h b/c/src/lib/libbsp/m68k/csb360/include/coverhd.h deleted file mode 100644 index c5ff33b21d..0000000000 --- a/c/src/lib/libbsp/m68k/csb360/include/coverhd.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file - * - * @ingroup m68k_csb360 - * - * @brief C Overhead definitions. - */ - -/* - * This file based on output of tmoverhd test. - */ - -#ifndef __COVERHD_H__ -#define __COVERHD_H__ - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 2 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 2 -#define CALLING_OVERHEAD_CLOCK_SET 2 -#define CALLING_OVERHEAD_CLOCK_TICK 0 -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 2 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 1 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 1 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#endif /* __COVERHD_H__ */ diff --git a/c/src/lib/libbsp/m68k/csb360/include/tm27.h b/c/src/lib/libbsp/m68k/csb360/include/tm27.h deleted file mode 100644 index 5f2fd8a383..0000000000 --- a/c/src/lib/libbsp/m68k/csb360/include/tm27.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * - * @ingroup m68k_csb360 - * - * @brief Time Test 27 routines. - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #2"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/gen68302/include/bsp.h b/c/src/lib/libbsp/m68k/gen68302/include/bsp.h deleted file mode 100644 index 3cf37f61ab..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/include/bsp.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @ingroup m68k_gen68302 - * - * @brief Global BSP definitions. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_GEN68302_BSP_H -#define LIBBSP_M68K_GEN68302_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup m68k_gen68302 GEN68302 Support - * - * @ingroup bsp_m68k - * - * @brief GEN68302 support. - */ - -/* Constants */ - -#define RAM_START 0 -#define RAM_END 0x040000 - -/* Structures */ - -#ifdef GEN68302_INIT -#undef EXTERN -#define EXTERN -#else -#undef EXTERN -#define EXTERN extern -#endif - -/* miscellaneous stuff assumed to exist */ - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h b/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h deleted file mode 100644 index 65d586c0fc..0000000000 --- a/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * @file - * - * @ingroup m68k_gen68302 - * - * @brief C overhead definitions. - */ - -/* coverhd.h - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 14 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 11 -#define CALLING_OVERHEAD_TASK_CREATE 22 -#define CALLING_OVERHEAD_TASK_IDENT 17 -#define CALLING_OVERHEAD_TASK_START 18 -#define CALLING_OVERHEAD_TASK_RESTART 15 -#define CALLING_OVERHEAD_TASK_DELETE 12 -#define CALLING_OVERHEAD_TASK_SUSPEND 12 -#define CALLING_OVERHEAD_TASK_RESUME 12 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 16 -#define CALLING_OVERHEAD_TASK_MODE 15 -#define CALLING_OVERHEAD_TASK_GET_NOTE 16 -#define CALLING_OVERHEAD_TASK_SET_NOTE 16 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 31 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 11 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 17 -#define CALLING_OVERHEAD_CLOCK_GET 32 -#define CALLING_OVERHEAD_CLOCK_SET 31 -#define CALLING_OVERHEAD_CLOCK_TICK 8 - -#define CALLING_OVERHEAD_TIMER_CREATE 13 -#define CALLING_OVERHEAD_TIMER_IDENT 12 -#define CALLING_OVERHEAD_TIMER_DELETE 14 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 19 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 39 -#define CALLING_OVERHEAD_TIMER_RESET 12 -#define CALLING_OVERHEAD_TIMER_CANCEL 12 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 18 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 12 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 17 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 17 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 12 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 18 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 17 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 12 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 14 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 14 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 17 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 19 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 14 - -#define CALLING_OVERHEAD_EVENT_SEND 15 -#define CALLING_OVERHEAD_EVENT_RECEIVE 18 -#define CALLING_OVERHEAD_SIGNAL_CATCH 14 -#define CALLING_OVERHEAD_SIGNAL_SEND 14 -#define CALLING_OVERHEAD_PARTITION_CREATE 23 -#define CALLING_OVERHEAD_PARTITION_IDENT 17 -#define CALLING_OVERHEAD_PARTITION_DELETE 12 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 15 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 15 -#define CALLING_OVERHEAD_REGION_CREATE 23 -#define CALLING_OVERHEAD_REGION_IDENT 14 -#define CALLING_OVERHEAD_REGION_DELETE 12 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 21 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 15 -#define CALLING_OVERHEAD_PORT_CREATE 20 -#define CALLING_OVERHEAD_PORT_IDENT 14 -#define CALLING_OVERHEAD_PORT_DELETE 12 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 18 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 18 - -#define CALLING_OVERHEAD_IO_INITIALIZE 18 -#define CALLING_OVERHEAD_IO_OPEN 18 -#define CALLING_OVERHEAD_IO_CLOSE 18 -#define CALLING_OVERHEAD_IO_READ 18 -#define CALLING_OVERHEAD_IO_WRITE 18 -#define CALLING_OVERHEAD_IO_CONTROL 18 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 11 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 13 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 14 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 12 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 12 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 14 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 8 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/gen68340/include/bsp.h b/c/src/lib/libbsp/m68k/gen68340/include/bsp.h deleted file mode 100644 index 44dafbd77b..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/include/bsp.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * - * @ingroup m68k_gen68340 - * - * @brief Global BSP definitions. - */ - -/* - * Board Support Package for `Generic' Motorola MC68340 - * - * Based on the `gen68360' board support package, and covered by the - * original distribution terms. - */ - -/* bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_GEN68340_BSP_H -#define LIBBSP_M68K_GEN68340_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup m68k_gen68340 Motorola MC68340 Support - * - * @ingroup bsp_m68k - * - * @brief Motorola MC68340 support. - */ - -/* Constants */ - -/* Structures */ - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Methods used across files inside the BSP - */ -int dbug_in_char( int minor ); -void dbug_out_char( int minor, int ch ); -int dbug_char_present( int minor ); -void _dbug_dumpanic(void); - -/* - * Only called from .S but prototyped here to capture the dependecy. - */ -void _Init68340 (void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/m68k/gen68340/include/coverhd.h b/c/src/lib/libbsp/m68k/gen68340/include/coverhd.h deleted file mode 100644 index 9e8796b38a..0000000000 --- a/c/src/lib/libbsp/m68k/gen68340/include/coverhd.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * @file - * - * @ingroup m68k_gen68340 - * - * @brief C overhead definitions. - */ - -/* - * This file was machine-generated from the tmoverhd.exe output - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 -#define CALLING_OVERHEAD_TASK_CREATE 8 -#define CALLING_OVERHEAD_TASK_IDENT 6 -#define CALLING_OVERHEAD_TASK_START 6 -#define CALLING_OVERHEAD_TASK_RESTART 5 -#define CALLING_OVERHEAD_TASK_DELETE 4 -#define CALLING_OVERHEAD_TASK_SUSPEND 4 -#define CALLING_OVERHEAD_TASK_RESUME 4 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 6 -#define CALLING_OVERHEAD_TASK_MODE 6 -#define CALLING_OVERHEAD_TASK_GET_NOTE 6 -#define CALLING_OVERHEAD_TASK_SET_NOTE 6 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 12 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 6 -#define CALLING_OVERHEAD_CLOCK_GET 12 -#define CALLING_OVERHEAD_CLOCK_SET 12 -#define CALLING_OVERHEAD_CLOCK_TICK 3 -#define CALLING_OVERHEAD_TIMER_CREATE 5 -#define CALLING_OVERHEAD_TIMER_DELETE 4 -#define CALLING_OVERHEAD_TIMER_IDENT 5 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 14 -#define CALLING_OVERHEAD_TIMER_RESET 4 -#define CALLING_OVERHEAD_TIMER_CANCEL 4 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 7 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 6 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 6 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5 -#define CALLING_OVERHEAD_EVENT_SEND 6 -#define CALLING_OVERHEAD_EVENT_RECEIVE 6 -#define CALLING_OVERHEAD_SIGNAL_CATCH 5 -#define CALLING_OVERHEAD_SIGNAL_SEND 5 -#define CALLING_OVERHEAD_PARTITION_CREATE 8 -#define CALLING_OVERHEAD_PARTITION_IDENT 6 -#define CALLING_OVERHEAD_PARTITION_DELETE 5 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 6 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 6 -#define CALLING_OVERHEAD_REGION_CREATE 8 -#define CALLING_OVERHEAD_REGION_IDENT 5 -#define CALLING_OVERHEAD_REGION_DELETE 4 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 7 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 6 -#define CALLING_OVERHEAD_PORT_CREATE 7 -#define CALLING_OVERHEAD_PORT_IDENT 5 -#define CALLING_OVERHEAD_PORT_DELETE 5 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 6 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 6 -#define CALLING_OVERHEAD_IO_INITIALIZE 6 -#define CALLING_OVERHEAD_IO_OPEN 6 -#define CALLING_OVERHEAD_IO_CLOSE 6 -#define CALLING_OVERHEAD_IO_READ 6 -#define CALLING_OVERHEAD_IO_WRITE 6 -#define CALLING_OVERHEAD_IO_CONTROL 6 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 5 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 diff --git a/c/src/lib/libbsp/m68k/gen68360/include/bsp.h b/c/src/lib/libbsp/m68k/gen68360/include/bsp.h deleted file mode 100644 index 67babe6172..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/include/bsp.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * @file - * - * @ingroup gen68360_bsp - * - * @brief Board Support Package for `Generic' Motorola MC68360 - */ - -/* - * - * Based on the `gen68302' board support package, and covered by the - * original distribution terms. - * - * W. Eric Norum - * Saskatchewan Accelerator Laboratory - * University of Saskatchewan - * Saskatoon, Saskatchewan, CANADA - * eric@skatter.usask.ca - */ - -/* bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_GEN68360_BSP_H -#define LIBBSP_M68K_GEN68360_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup gen68360_bsp Network driver - * - * @ingroup m68k_gen68360 - * - * @brief Network driver configuration - */ - -struct rtems_bsdnet_ifconfig; -extern int rtems_scc1_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "scc1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_scc1_driver_attach - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -void M360ExecuteRISC( uint16_t command ); -void *M360AllocateBufferDescriptors( int count ); -void *M360AllocateRiscTimers( int count ); -extern char M360DefaultWatchdogFeeder; - -extern int m360_clock_rate; /* BRG clock rate, defined in console.c */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB) - */ -#define ATLASHSB_ESR 0x20010000L -#define ATLASHSB_USICR 0x20010001L -#define ATLASHSB_DSRR 0x20010002L -#define ATLASHSB_LED4 0x20010004L -#define ATLASHSB_ROM_U6 0xFF080000L /* U6 flash ROM socket */ - - -/* - * definitions for PGH360 board - */ -#if defined(PGH360) -/* - * logical SPI addresses of SPI slaves available - */ -#define PGH360_SPI_ADDR_EEPROM 0 -#define PGH360_SPI_ADDR_DISP4_DATA 1 -#define PGH360_SPI_ADDR_DISP4_CTRL 2 - -/* - * Port B bit locations of SPI slave selects - */ -#define PGH360_PB_SPI_DISP4_RS_MSK (1<<15) -#define PGH360_PB_SPI_DISP4_CE_MSK (1<<14) -#define PGH360_PB_SPI_EEP_CE_MSK (1<< 0) -#endif /* defined(PGH360) */ - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void _Init68360(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/gen68360/include/coverhd.h b/c/src/lib/libbsp/m68k/gen68360/include/coverhd.h deleted file mode 100644 index c199d6212c..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/include/coverhd.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * @file - * - * @ingroup m68k_coverhd - * - * @brief This file was machine-generated from the tmoverhd.exe output - */ - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 2 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 2 -#define CALLING_OVERHEAD_TASK_CREATE 4 -#define CALLING_OVERHEAD_TASK_IDENT 3 -#define CALLING_OVERHEAD_TASK_START 3 -#define CALLING_OVERHEAD_TASK_RESTART 2 -#define CALLING_OVERHEAD_TASK_DELETE 2 -#define CALLING_OVERHEAD_TASK_SUSPEND 2 -#define CALLING_OVERHEAD_TASK_RESUME 2 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 3 -#define CALLING_OVERHEAD_TASK_MODE 3 -#define CALLING_OVERHEAD_TASK_GET_NOTE 3 -#define CALLING_OVERHEAD_TASK_SET_NOTE 3 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 6 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 2 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 3 -#define CALLING_OVERHEAD_CLOCK_GET 6 -#define CALLING_OVERHEAD_CLOCK_SET 6 -#define CALLING_OVERHEAD_CLOCK_TICK 1 -#define CALLING_OVERHEAD_TIMER_CREATE 2 -#define CALLING_OVERHEAD_TIMER_DELETE 2 -#define CALLING_OVERHEAD_TIMER_IDENT 2 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 3 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 7 -#define CALLING_OVERHEAD_TIMER_RESET 2 -#define CALLING_OVERHEAD_TIMER_CANCEL 2 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 3 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 3 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 2 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 2 -#define CALLING_OVERHEAD_EVENT_SEND 3 -#define CALLING_OVERHEAD_EVENT_RECEIVE 3 -#define CALLING_OVERHEAD_SIGNAL_CATCH 2 -#define CALLING_OVERHEAD_SIGNAL_SEND 2 -#define CALLING_OVERHEAD_PARTITION_CREATE 4 -#define CALLING_OVERHEAD_PARTITION_IDENT 3 -#define CALLING_OVERHEAD_PARTITION_DELETE 2 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 3 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 3 -#define CALLING_OVERHEAD_REGION_CREATE 4 -#define CALLING_OVERHEAD_REGION_IDENT 2 -#define CALLING_OVERHEAD_REGION_DELETE 2 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 3 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 2 -#define CALLING_OVERHEAD_PORT_CREATE 4 -#define CALLING_OVERHEAD_PORT_IDENT 2 -#define CALLING_OVERHEAD_PORT_DELETE 2 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 3 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 3 -#define CALLING_OVERHEAD_IO_INITIALIZE 3 -#define CALLING_OVERHEAD_IO_OPEN 3 -#define CALLING_OVERHEAD_IO_CLOSE 3 -#define CALLING_OVERHEAD_IO_READ 3 -#define CALLING_OVERHEAD_IO_WRITE 3 -#define CALLING_OVERHEAD_IO_CONTROL 3 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 2 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 diff --git a/c/src/lib/libbsp/m68k/gen68360/include/tm27.h b/c/src/lib/libbsp/m68k/gen68360/include/tm27.h deleted file mode 100644 index c71eed3897..0000000000 --- a/c/src/lib/libbsp/m68k/gen68360/include/tm27.h +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file - * - * @ingroup m68k_tm27 - * - * @brief Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup m68k_tm27 Stuff for Time Test 27 - * - * @ingroup m68k_gen68360 - * - * @brief Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #2"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h b/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h deleted file mode 100644 index 61b3cedc32..0000000000 --- a/c/src/lib/libbsp/m68k/genmcf548x/include/bsp.h +++ /dev/null @@ -1,138 +0,0 @@ -/** - * @file - * - * @ingroup m68k_genmcf548x - * - * @brief Global BSP definitions. - */ - -/*===============================================================*\ -| Project: RTEMS generic mcf548x BSP | -+-----------------------------------------------------------------+ -| File: bsp.h | -+-----------------------------------------------------------------+ -| The file contains the BSP header of generic MCF548x BSP. | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| | -| Parts of the code has been derived from the "dBUG source code" | -| package Freescale is providing for M548X EVBs. The usage of | -| the modified or unmodified code and it's integration into the | -| generic mcf548x BSP has been done according to the Freescale | -| license terms. | -| | -| The Freescale license terms can be reviewed in the file | -| | -| Freescale_license.txt | -| | -+-----------------------------------------------------------------+ -| | -| The generic mcf548x BSP has been developed on the basic | -| structures and modules of the av5282 BSP. | -| | -+-----------------------------------------------------------------+ -| | -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| | -| date history ID | -| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | -| 12.11.07 1.0 ras | -| | -\*===============================================================*/ - -#ifndef LIBBSP_M68K_GENMCF548X_BSP_H -#define LIBBSP_M68K_GENMCF548X_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -/** - * @defgroup m68k_genmcf548x MCF548X Support - * - * @ingroup bsp_m68k - * - * @brief MCT548X support. - */ - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf548x/mcf548x.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define which port the console should use - all other ports are then defined as general purpose */ -#define CONSOLE_PORT 0 - -/* functions */ - -uint32_t get_CPU_clock_speed(void); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* Initial values for the interrupt level and priority registers (INTC_ICRn) */ -extern const uint8_t mcf548x_intc_icr_init_values[64]; - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_mcf548x_fec_driver_attach_detach(struct rtems_bsdnet_ifconfig *config,int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mcf548x_fec_driver_attach_detach - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec1" -#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "fec2" - -#ifdef HAS_DBUG - typedef struct { - uint32_t console_baudrate; - uint8_t server_ip [4]; - uint8_t client_ip [4]; - uint8_t gateway_ip[4]; - uint8_t netmask [4]; - uint8_t spare[4]; - uint8_t macaddr [6]; - uint32_t ethport; /* default fec port: 1 = fec1, 2 = fec2 */ - uint32_t uartport; /* default fec port: 1 = psc0, 2 = psc1... */ - } dbug_settings_t; - -#define DBUG_SETTINGS (*(const dbug_settings_t *)0xFC020000) -#endif /* HAS_DBUG */ - -void bsp_cacr_set_flags(uint32_t flags); - -void bsp_cacr_set_self_clear_flags(uint32_t flags); - -void bsp_cacr_clear_flags(uint32_t flags); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/genmcf548x/include/irq.h b/c/src/lib/libbsp/m68k/genmcf548x/include/irq.h deleted file mode 100644 index 825cc0d104..0000000000 --- a/c/src/lib/libbsp/m68k/genmcf548x/include/irq.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * - * @ingroup genmcf548x_interrupt - * - * @brief Interrupt definitions. - */ - -/* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_MCF548X_IRQ_H -#define LIBBSP_M68K_MCF548X_IRQ_H - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -/** - * @defgroup genmcf548x_interrupt Interrupt Support - * - * @ingroup m68k_genmcf548x - * - * @brief Interrupt support. - */ - - -#define MCF548X_IRQ_EPORT_EPF1 1 -#define MCF548X_IRQ_EPORT_EPF2 2 -#define MCF548X_IRQ_EPORT_EPF3 3 -#define MCF548X_IRQ_EPORT_EPF4 4 -#define MCF548X_IRQ_EPORT_EPF5 5 -#define MCF548X_IRQ_EPORT_EPF6 6 -#define MCF548X_IRQ_EPORT_EPF7 7 -#define MCF548X_IRQ_USB_EP0ISR 15 -#define MCF548X_IRQ_USB_EP1ISR 16 -#define MCF548X_IRQ_USB_EP2ISR 17 -#define MCF548X_IRQ_USB_EP3ISR 18 -#define MCF548X_IRQ_USB_EP4ISR 19 -#define MCF548X_IRQ_USB_EP5ISR 20 -#define MCF548X_IRQ_USB_EP6ISR 21 -#define MCF548X_IRQ_USB_ISR 22 -#define MCF548X_IRQ_USB_AISR 23 -#define MCF548X_IRQ_DSPI_RFOF_TFUF 25 -#define MCF548X_IRQ_DSPI_RFOF 26 -#define MCF548X_IRQ_DSPI_RFDF 27 -#define MCF548X_IRQ_DSPI_TFUF 28 -#define MCF548X_IRQ_DSPI_TCF 29 -#define MCF548X_IRQ_DSPI_TFFF 30 -#define MCF548X_IRQ_DSPI_EOQF 31 -#define MCF548X_IRQ_DSPI 25 -#define MCF548X_IRQ_PSC3 32 -#define MCF548X_IRQ_PSC2 33 -#define MCF548X_IRQ_PSC1 34 -#define MCF548X_IRQ_PSC0 35 -#define MCF548X_IRQ_PSC(i) (35 - (i)) -#define MCF548X_IRQ_COMMTIM 36 -#define MCF548X_IRQ_SEC 37 -#define MCF548X_IRQ_FEC1 38 -#define MCF548X_IRQ_FEC0 39 -#define MCF548X_IRQ_FEC(i) (39 - (i)) -#define MCF548X_IRQ_I2C 40 -#define MCF548X_IRQ_PCIARB 41 -#define MCF548X_IRQ_CBPCI 42 -#define MCF548X_IRQ_XLBPCI 43 -#define MCF548X_IRQ_XLBARB 47 -#define MCF548X_IRQ_DMA 48 -#define MCF548X_IRQ_CAN0_ERROR 49 -#define MCF548X_IRQ_CAN0_BUSOFF 50 -#define MCF548X_IRQ_CAN0_MBOR 51 -#define MCF548X_IRQ_SLT1 53 -#define MCF548X_IRQ_SLT0 54 -#define MCF548X_IRQ_CAN1_ERROR 55 -#define MCF548X_IRQ_CAN1_BUSOFF 56 -#define MCF548X_IRQ_CAN1_MBOR 57 -#define MCF548X_IRQ_GPT3 59 -#define MCF548X_IRQ_GPT2 60 -#define MCF548X_IRQ_GPT1 61 -#define MCF548X_IRQ_GPT0 62 - -#define BSP_INTERRUPT_VECTOR_MIN 1 - -#define BSP_INTERRUPT_VECTOR_MAX 63 - -#endif /* LIBBSP_M68K_MCF548X_IRQ_H */ diff --git a/c/src/lib/libbsp/m68k/genmcf548x/include/tm27.h b/c/src/lib/libbsp/m68k/genmcf548x/include/tm27.h deleted file mode 100644 index 31ea8bca0c..0000000000 --- a/c/src/lib/libbsp/m68k/genmcf548x/include/tm27.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * @file - * - * @ingroup m68k_genmcf548x - * - * @brief Time Test 27 routines. - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/idp/include/bsp.h b/c/src/lib/libbsp/m68k/idp/include/bsp.h deleted file mode 100644 index c7ed37228a..0000000000 --- a/c/src/lib/libbsp/m68k/idp/include/bsp.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * @file - * - * @ingroup idp_bsp - * - * @brief This include file contains all Motorola 680x0 IDP board - * IO definitions. - */ - -#ifndef LIBBSP_M68K_IDP_BSP_H -#define LIBBSP_M68K_IDP_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/motorola/mc68230.h> -#include <rtems/motorola/mc68681.h> - -/** - * @defgroup idp_bsp IO definitions - * - * @ingroup m68k_idp - * - * @brief Motorola 680x0 IDP board IO definitions - */ - -#define DUART_ADDR 0xb00003 /* base address of the MC68681 DUART */ - -/* Constants */ - -#define RAM_START 0 -#define RAM_END 0x200000 - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -void rtems_bsp_delay(int num); - -/* - * Prototypes for methods inside the BSP that cross file boundaries. - */ -void init_pit( void ); -void transmit_char( char ch ); -void transmit_char_portb( char ch ); - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/include/bsp.h b/c/src/lib/libbsp/m68k/mcf5206elite/include/bsp.h deleted file mode 100644 index a9cb868b1b..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5206elite/include/bsp.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Board Support Package for MCF5206eLITE evaluation board - * BSP definitions - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_MCF5206ELITE_BSP_H -#define LIBBSP_M68K_MCF5206ELITE_BSP_H - -#include "mcf5206/mcf5206e.h" - -/*** Board resources allocation ***/ - -/* - * To achieve some compatibility with dBUG monitor, we use the same - * memory resources allocation as it is used in dBUG. - * - * If this definitions will be changed, change the linker script also. - */ - -/* Memory mapping */ -/* CS0: Boot Flash */ -#define BSP_MEM_ADDR_FLASH (0xFFE00000) -#define BSP_MEM_SIZE_FLASH (1*1024*1024) -#define BSP_MEM_MASK_FLASH (MCF5206E_CSMR_MASK_1M) - -/* CS2: External SRAM */ -#define BSP_MEM_ADDR_ESRAM (0x30000000) -#define BSP_MEM_SIZE_ESRAM (1*1024*1024) -#define BSP_MEM_MASK_ESRAM (MCF5206E_CSMR_MASK_1M) - -/* CS3: General-Purpose I/O register */ -#define BSP_MEM_ADDR_GPIO (0x40000000) -#define BSP_MEM_SIZE_GPIO (64*1024) -#define BSP_MEM_MASK_GPIO (MCF5206E_CSMR_MASK_64K) - -/* DRAM0: Dynamic RAM */ -#define BSP_MEM_ADDR_DRAM (0x00000000) -#define BSP_MEM_SIZE_DRAM (16*1024*1024) -#define BSP_MEM_MASK_DRAM (MCF5206E_DCMR_MASK_16M) - -/* On-chip SRAM */ -#define BSP_MEM_ADDR_SRAM (0x20000000) -#define BSP_MEM_SIZE_SRAM (8*1024) - -/* On-chip peripherial registers */ -#define BSP_MEM_ADDR_IMM (0x10000000) -#define BSP_MEM_SIZE_IMM (1*1024) -#define MBAR BSP_MEM_ADDR_IMM - -/* Interrupt vector assignment */ -#define BSP_INTVEC_AVEC1 (25) -#define BSP_INTLVL_AVEC1 (1) -#define BSP_INTPRIO_AVEC1 (3) - -#define BSP_INTVEC_AVEC2 (26) -#define BSP_INTLVL_AVEC2 (2) -#define BSP_INTPRIO_AVEC2 (3) - -#define BSP_INTVEC_AVEC3 (27) -#define BSP_INTLVL_AVEC3 (3) -#define BSP_INTPRIO_AVEC3 (3) - -#define BSP_INTVEC_AVEC4 (28) -#define BSP_INTLVL_AVEC4 (4) -#define BSP_INTPRIO_AVEC4 (3) - -#define BSP_INTVEC_AVEC5 (29) -#define BSP_INTLVL_AVEC5 (5) -#define BSP_INTPRIO_AVEC5 (3) - -#define BSP_INTVEC_AVEC6 (30) -#define BSP_INTLVL_AVEC6 (6) -#define BSP_INTPRIO_AVEC6 (3) - -#define BSP_INTVEC_AVEC7 (31) -#define BSP_INTLVL_AVEC7 (7) -#define BSP_INTPRIO_AVEC7 (3) - -#define BSP_INTVEC_TIMER1 (BSP_INTVEC_AVEC5) -#define BSP_INTLVL_TIMER1 (BSP_INTLVL_AVEC5) -#define BSP_INTPRIO_TIMER1 (2) - -#define BSP_INTVEC_TIMER2 (BSP_INTVEC_AVEC6) -#define BSP_INTLVL_TIMER2 (BSP_INTLVL_AVEC6) -#define BSP_INTPRIO_TIMER2 (2) - -#define BSP_INTVEC_MBUS (BSP_INTVEC_AVEC4) -#define BSP_INTLVL_MBUS (BSP_INTLVL_AVEC4) -#define BSP_INTPRIO_MBUS (2) - -#define BSP_INTVEC_UART1 (64) -#define BSP_INTLVL_UART1 (4) -#define BSP_INTPRIO_UART1 (0) - -#define BSP_INTVEC_UART2 (65) -#define BSP_INTLVL_UART2 (4) -#define BSP_INTPRIO_UART2 (1) - -#define BSP_INTVEC_DMA0 (66) -#define BSP_INTLVL_DMA0 (3) -#define BSP_INTPRIO_DMA0 (1) - -#define BSP_INTVEC_DMA1 (67) -#define BSP_INTLVL_DMA1 (3) -#define BSP_INTPRIO_DMA1 (2) - -/* Location of DS1307 Real-Time Clock/NVRAM chip */ -#define DS1307_I2C_BUS_NUMBER (0) - -#ifndef ASM - -#include <bspopts.h> -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/clockdrv.h> -#include <rtems/rtc.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* System frequency */ -#define BSP_SYSTEM_FREQUENCY ((unsigned int)&_SYS_CLOCK_FREQUENCY) -extern char _SYS_CLOCK_FREQUENCY; /* Don't use this variable directly!!! */ - -/* MBUS I2C bus clock default frequency */ -#define BSP_MBUS_FREQUENCY (16000) - -/* Number of I2C buses supported in this board */ -#define I2C_NUMBER_OF_BUSES (1) - -/* I2C bus selection */ -#define I2C_SELECT_BUS(bus) - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define delay( microseconds ) \ - { register uint32_t _delay=(microseconds); \ - register uint32_t _tmp=123; \ - __asm__ volatile( "0: \ - nbcd %0 ; \ - nbcd %0 ; \ - dbf %1,0b" \ - : "=d" (_tmp), "=d" (_delay) \ - : "0" (_tmp), "1" (_delay) ); \ - } - - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -extern rtems_isr (*rtems_clock_hook)(rtems_vector_number); - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Prototypes for BSP methods that cross file boundaries - */ -void Init5206e(void); - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/include/coverhd.h b/c/src/lib/libbsp/m68k/mcf5206elite/include/coverhd.h deleted file mode 100644 index 1ff260d1a1..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5206elite/include/coverhd.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * @file - * @ingroup m68k_mcf5206elite - * @brief C Overhead definitions - */ - -/* - * This file based on output of tmoverhd test. - */ - -#ifndef __COVERHD_H__ -#define __COVERHD_H__ - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 2 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 2 -#define CALLING_OVERHEAD_CLOCK_SET 2 -#define CALLING_OVERHEAD_CLOCK_TICK 0 -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 2 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 1 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 1 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#endif /* __COVERHD_H__ */ diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/include/i2c.h b/c/src/lib/libbsp/m68k/mcf5206elite/include/i2c.h deleted file mode 100644 index 8bec067a3a..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5206elite/include/i2c.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Generic I2C bus interface for RTEMS - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __RTEMS__I2C_H__ -#define __RTEMS__I2C_H__ - -#include <rtems.h> -#include <bsp.h> -/* This header file define the generic interface to i2c buses available in - * system. This interface may be used by user applications or i2c-device - * drivers (like RTC, NVRAM, etc). - * - * Functions i2c_initialize and i2c_transfer declared in this header usually - * implemented in particular board support package. Usually this - * implementation is a simple wrapper or multiplexor to I2C controller - * driver which is available in system. It may be generic "software - * controller" I2C driver which control SDA and SCL signals directly (if SDA - * and SCL is general-purpose I/O pins), or driver for hardware I2C - * controller (standalone or integrated with processors: MBus controller in - * ColdFire processors, I2C controller in PowerQUICC and so on). - * - * i2c_transfer is a very generic low-level function. Higher-level function - * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too. - */ - -/* I2C Bus Number type */ -typedef uint32_t i2c_bus_number; - -/* I2C device address */ -typedef uint16_t i2c_address; - -/* I2C error codes generated during message transfer */ -typedef enum i2c_message_status { - I2C_SUCCESSFUL = 0, - I2C_TIMEOUT, - I2C_NO_DEVICE, - I2C_ARBITRATION_LOST, - I2C_NO_ACKNOWLEDGE, - I2C_NO_DATA, - I2C_RESOURCE_NOT_AVAILABLE -} i2c_message_status; - -/* I2C Message */ -typedef struct i2c_message { - i2c_address addr; /* I2C slave device address */ - uint16_t flags; /* message flags (see below) */ - i2c_message_status status; /* message transfer status code */ - uint16_t len; /* Number of bytes to read or write */ - uint8_t *buf; /* pointer to data array */ -} i2c_message; - -/* I2C message flag */ -#define I2C_MSG_ADDR_10 (0x01) /* 10-bit address */ -#define I2C_MSG_WR (0x02) /* transfer direction for this message - from master to slave */ -#define I2C_MSG_ERRSKIP (0x04) /* Skip message if last transfered message - is failed */ -/* Type for function which is called when transfer over I2C bus is finished */ -typedef void (*i2c_transfer_done) (void *arg); - -/* i2c_initialize -- - * I2C driver initialization. This function usually called on device - * driver initialization state, before initialization task. All I2C - * buses are initialized; reasonable slow data transfer rate is - * selected for each bus. - * - * PARAMETERS: - * major - I2C device major number - * minor - I2C device minor number - * arg - RTEMS driver initialization argument - * - * RETURNS: - * RTEMS status code - */ -rtems_device_driver -i2c_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -/* i2c_select_clock_rate -- - * select I2C bus clock rate for specified bus. Some bus controller do not - * allow to select arbitrary clock rate; in this case nearest possible - * slower clock rate is selected. - * - * PARAMETERS: - * bus - I2C bus number - * bps - data transfer rate for this bytes in bits per second - * - * RETURNS: - * RTEMS_SUCCESSFUL, if operation performed successfully, - * RTEMS_INVALID_NUMBER, if wrong bus number is specified, - * RTEMS_UNSATISFIED, if bus do not support data transfer rate selection - * or specified data transfer rate could not be used. - */ -rtems_status_code -i2c_select_clock_rate(i2c_bus_number bus, int bps); - -/* i2c_transfer -- - * Initiate multiple-messages transfer over specified I2C bus or - * put request into queue if bus or some other resource is busy. (This - * is non-blocking function). - * - * PARAMETERS: - * bus - I2C bus number - * nmsg - number of messages - * msg - pointer to messages array - * done - function which is called when transfer is finished - * done_arg_ptr - arbitrary argument ptr passed to done funciton - * - * RETURNS: - * RTEMS_SUCCESSFUL if transfer initiated successfully, or error - * code if something failed. - */ -rtems_status_code -i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg, - i2c_transfer_done done, void * done_arg_ptr); - -/* i2c_transfer_wait -- - * Initiate I2C bus transfer and block until this transfer will be - * finished. This function wait the semaphore if system in - * SYSTEM_STATE_UP state, or poll done flag in other states. - * - * PARAMETERS: - * bus - I2C bus number - * msg - pointer to transfer messages array - * nmsg - number of messages in transfer - * - * RETURNS: - * I2C_SUCCESSFUL, if transfer finished successfully, - * I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed, - * value of status field of first error-finished message in transfer, - * if something wrong. - */ -i2c_message_status -i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg); - -/* i2c_poll -- - * Poll I2C bus controller for events and hanle it. This function is - * used when I2C driver operates in poll-driven mode. - * - * PARAMETERS: - * bus - bus number to be polled - * - * RETURNS: - * none - */ -void -i2c_poll(i2c_bus_number bus); - -/* i2c_write -- - * Send single message over specified I2C bus to addressed device and - * wait while transfer is finished. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * buf - data to be sent to device - * size - data buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size); - -/* i2c_wrbyte -- - * Send single one-byte long message over specified I2C bus to - * addressed device and wait while transfer is finished. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * cmd - byte message to be sent to device - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t cmd); - -/* i2c_read -- - * receive single message over specified I2C bus from addressed device. - * This call will wait while transfer is finished. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * buf - buffer for received message - * size - receive buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size); - -/* i2c_wrrd -- - * Send message over I2C bus to specified device and receive message - * from the same device during single transfer. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * bufw - data to be sent to device - * sizew - send data buffer size - * bufr - buffer for received message - * sizer - receive buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew, - void *bufr, int sizer); - -/* i2c_wbrd -- - * Send one-byte message over I2C bus to specified device and receive - * message from the same device during single transfer. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * cmd - one-byte message to be sent over I2C bus - * bufr - buffer for received message - * sizer - receive buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t cmd, - void *bufr, int sizer); - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/include/nvram.h b/c/src/lib/libbsp/m68k/mcf5206elite/include/nvram.h deleted file mode 100644 index fd75db2363..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5206elite/include/nvram.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * nvram.h -- DS1307-based non-volatile memory device driver. - * - * This driver support file-like operations to 56-bytes long non-volatile - * memory of DS1307 I2C real-time clock chip. - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __DRIVER__NVRAM_H__ -#define __DRIVER__NVRAM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define NVRAM_DRIVER_TABLE_ENTRY \ - { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ - nvram_driver_read, nvram_driver_write, NULL } - -/* nvram_driver_initialize -- - * Non-volatile memory device driver initialization. - */ -rtems_device_driver -nvram_driver_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -/* nvram_driver_open -- - * Non-volatile memory device driver open primitive. - */ -rtems_device_driver -nvram_driver_open(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -/* nvram_driver_close -- - * Non-volatile memory device driver close primitive. - */ -rtems_device_driver -nvram_driver_close(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -/* nvram_driver_read -- - * Non-volatile memory device driver read primitive. - */ -rtems_device_driver -nvram_driver_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -/* nvram_driver_write -- - * Non-volatile memory device driver write primitive. - */ -rtems_device_driver -nvram_driver_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -#ifdef __cplusplus -} -#endif - -#endif /* __VFDDRV_H__ */ diff --git a/c/src/lib/libbsp/m68k/mcf5206elite/include/tm27.h b/c/src/lib/libbsp/m68k/mcf5206elite/include/tm27.h deleted file mode 100644 index 2abef68311..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5206elite/include/tm27.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * @file - * @ingroup m68k_mcf5206elite - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 34, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #2"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h b/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h deleted file mode 100644 index 8ef203f61b..0000000000 --- a/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * mcf52235 BSP header file - */ - -#ifndef LIBBSP_M68K_MCF52235_BSP_H -#define LIBBSP_M68K_MCF52235_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf5223x/mcf5223x.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Declare base address of peripherals area */ -#define __IPSBAR ((vuint8 *) 0x40000000) - -/***************************************************************************/ -/** Network driver configuration **/ - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define which port the console should use - all other ports are then defined as general purpose */ -#define CONSOLE_PORT 0 - -/* externals */ - -/* constants */ - -/* functions */ - -uint32_t bsp_get_CPU_clock_speed(void); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ - -#define PIT3_IRQ_LEVEL 4 -#define PIT3_IRQ_PRIORITY 0 - -#define UART0_IRQ_LEVEL 3 -#define UART0_IRQ_PRIORITY 7 -#define UART1_IRQ_LEVEL 3 -#define UART1_IRQ_PRIORITY 6 -#define UART2_IRQ_LEVEL 3 -#define UART2_IRQ_PRIORITY 5 - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void Init52235(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/tm27.h b/c/src/lib/libbsp/m68k/mcf52235/include/tm27.h deleted file mode 100644 index b4b62ef721..0000000000 --- a/c/src/lib/libbsp/m68k/mcf52235/include/tm27.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * @file - * @ingroup m68k_mcf52235 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5225x/include/bsp.h b/c/src/lib/libbsp/m68k/mcf5225x/include/bsp.h deleted file mode 100644 index 42fe654524..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5225x/include/bsp.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_MCF5225X_BSP_H -#define LIBBSP_M68K_MCF5225X_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf5225x/mcf5225x.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Declare base address of peripherals area */ -#define __IPSBAR ((vuint8 *) 0x40000000) - -/***************************************************************************/ -/** Network driver configuration **/ - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define ports for console and DPU specific for BLUETOOTH and STATIONS */ -#define STATIONS_PORT 0 -#define CONSOLE_PORT 1 -#define BLUETOOTH_PORT 2 - -/* externals */ - -/* constants */ - -/* miscellaneous stuff assumed to exist */ - -/* - * Device Driver Table Entries - */ - -/* - * NOTE: Use the standard Console driver entry - */ - -/* - * NOTE: Use the standard Clock driver entry - */ - - -/* functions */ - -uint32_t bsp_get_CPU_clock_speed(void); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ - -#define PIT3_IRQ_LEVEL 4 -#define PIT3_IRQ_PRIORITY 0 - -#define UART0_IRQ_LEVEL 3 -#define UART0_IRQ_PRIORITY 7 -#define UART1_IRQ_LEVEL 3 -#define UART1_IRQ_PRIORITY 6 -#define UART2_IRQ_LEVEL 3 -#define UART2_IRQ_PRIORITY 5 - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void Init5225x(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5225x/include/tm27.h b/c/src/lib/libbsp/m68k/mcf5225x/include/tm27.h deleted file mode 100644 index fcf1c4f8aa..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5225x/include/tm27.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * @file - * @ingroup m68k_mcf5225x - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5235/include/bsp.h b/c/src/lib/libbsp/m68k/mcf5235/include/bsp.h deleted file mode 100644 index a0c4d5c60a..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5235/include/bsp.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * mcf5235 BSP header file - */ - -#ifndef LIBBSP_M68K_MCF5235_BSP_H -#define LIBBSP_M68K_MCF5235_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf5235/mcf5235.h> /* internal MCF5235 modules */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************/ -/** Network driver configuration **/ -struct rtems_bsdnet_ifconfig; -extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define which port the console should use - all other ports are then defined as general purpose */ -#define CONSOLE_PORT 0 - -/* functions */ - -uint32_t get_CPU_clock_speed(void); -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ -#define FEC_IRQ_LEVEL 4 -#define FEC_IRQ_RX_PRIORITY 7 -#define FEC_IRQ_TX_PRIORITY 6 - -#define PIT3_IRQ_LEVEL 4 -#define PIT3_IRQ_PRIORITY 0 - -#define UART0_IRQ_LEVEL 3 -#define UART0_IRQ_PRIORITY 7 -#define UART1_IRQ_LEVEL 3 -#define UART1_IRQ_PRIORITY 6 -#define UART2_IRQ_LEVEL 3 -#define UART2_IRQ_PRIORITY 5 - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void Init5235(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5235/include/tm27.h b/c/src/lib/libbsp/m68k/mcf5235/include/tm27.h deleted file mode 100644 index 92a85c789a..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5235/include/tm27.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * @file - * @ingroup m68k_mcf5235 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5329/include/bsp.h b/c/src/lib/libbsp/m68k/mcf5329/include/bsp.h deleted file mode 100644 index 59b9961586..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5329/include/bsp.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * mcf52235 BSP header file - */ - -#ifndef LIBBSP_M68K_MCF5329_BSP_H -#define LIBBSP_M68K_MCF5329_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf532x/mcf532x.h> - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile unsigned char vuint8; -typedef volatile unsigned short vuint16; -typedef volatile unsigned long vuint32; - -/***************************************************************************/ -/** Network driver configuration **/ -struct rtems_bsdnet_ifconfig; -extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "fec0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define which port the console should use - all other ports are then defined as general purpose */ -#define CONSOLE_PORT 0 - -/* functions */ - -uint32_t bsp_get_CPU_clock_speed(void); -uint32_t bsp_get_BUS_clock_speed(void); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ -#define FEC_IRQ_LEVEL 4 - -#define PIT3_IRQ_LEVEL 4 - -#define UART0_IRQ_LEVEL 3 -#define UART1_IRQ_LEVEL 3 -#define UART2_IRQ_LEVEL 3 - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void Init5329(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mcf5329/include/tm27.h b/c/src/lib/libbsp/m68k/mcf5329/include/tm27.h deleted file mode 100644 index 33376540ac..0000000000 --- a/c/src/lib/libbsp/m68k/mcf5329/include/tm27.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * @file - * @ingroup m68k_mcf5329 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mrm332/include/bsp.h b/c/src/lib/libbsp/m68k/mrm332/include/bsp.h deleted file mode 100644 index a2f6e67d45..0000000000 --- a/c/src/lib/libbsp/m68k/mrm332/include/bsp.h +++ /dev/null @@ -1,93 +0,0 @@ -/* bsp.h - * - * This include file contains all mrm board IO definitions. - */ - -/* - * COPYRIGHT (c) 1989-2009. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_MRM332_BSP_H -#define LIBBSP_M68K_MRM332_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/bspIo.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <mrm332.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define CONSOLE_SCI - -/* externals */ - -extern char _etext[]; -extern char _copy_start[]; -extern char _edata[]; -extern char _clear_start[]; -extern char end[]; -extern bool _copy_data_from_rom; - -/* constants */ - -#ifdef __START_C__ -#define STACK_SIZE "#0x800" -#else -#define STACK_SIZE 0x800 -#endif - -/* macros */ - -#define RAW_PUTS(str) \ - { register char *ptr = str; \ - while (*ptr) SCI_output_char(*ptr++); \ - } - -#define RAW_PUTI(n) { \ - register int i, j; \ - \ - RAW_PUTS("0x"); \ - for (i=28;i>=0;i -= 4) { \ - j = (n>>i) & 0xf; \ - SCI_output_char( (j>9 ? j-10+'a' : j+'0') ); \ - } \ - } - -/* miscellaneous stuff assumed to exist */ - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -extern int stack_size; -extern int stack_start; - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -void Spurious_Initialize(void); - -void _UART_flush(void); - -void outbyte(char); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme136/include/bsp.h b/c/src/lib/libbsp/m68k/mvme136/include/bsp.h deleted file mode 100644 index 3ea2101de6..0000000000 --- a/c/src/lib/libbsp/m68k/mvme136/include/bsp.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This include file contains all MVME136 board IO definitions. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_MVME136_BSP_H -#define LIBBSP_M68K_MVME136_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -#define RAM_START 0 -#define RAM_END 0x100000 - -#define M681ADDR 0xfffb0040 /* address of the M68681 chip */ -#define RXRDYB 0x01 /* status reg recv ready mask */ -#define TXRDYB 0x04 /* status reg trans ready mask */ -#define PARITYERR 0x20 /* status reg parity error mask */ -#define FRAMEERR 0x40 /* status reg frame error mask */ - -#define FOREVER 1 /* infinite loop */ - -/* Structures */ - -struct r_m681_info { - char fill1[ 5 ]; /* channel A regs ( not used ) */ - char isr; /* interrupt status reg */ - char fill2[ 2 ]; /* counter regs (not used) */ - char mr1mr2b; /* MR1B and MR2B regs */ - char srb; /* status reg channel B */ - char fill3; /* do not access */ - char rbb; /* receive buffer channel B */ - char ivr; /* interrupt vector register */ -}; - -struct w_m681_info { - char fill1[ 4 ]; /* channel A regs (not used) */ - char acr; /* auxillary control reg */ - char imr; /* interrupt mask reg */ - char fill2[ 2 ]; /* counter regs (not used) */ - char mr1mr2b; /* MR1B and MR2B regs */ - char csrb; /* clock select reg */ - char crb; /* command reg */ - char tbb; /* transmit buffer channel B */ - char ivr; /* interrupt vector register */ -}; - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handle, - rtems_vector_number vector, - int type -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme136/include/coverhd.h b/c/src/lib/libbsp/m68k/mvme136/include/coverhd.h deleted file mode 100644 index 025b9cdcc9..0000000000 --- a/c/src/lib/libbsp/m68k/mvme136/include/coverhd.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * @ingroup m68k_mvme136 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C on this target. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 2 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 2 -#define CALLING_OVERHEAD_TASK_START 2 -#define CALLING_OVERHEAD_TASK_RESTART 2 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 2 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 2 -#define CALLING_OVERHEAD_TASK_MODE 2 -#define CALLING_OVERHEAD_TASK_GET_NOTE 2 -#define CALLING_OVERHEAD_TASK_SET_NOTE 2 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 2 -#define CALLING_OVERHEAD_CLOCK_GET 5 -#define CALLING_OVERHEAD_CLOCK_SET 4 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 2 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 2 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 3 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 2 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 2 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 2 - -#define CALLING_OVERHEAD_EVENT_SEND 2 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 2 -#define CALLING_OVERHEAD_SIGNAL_SEND 2 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 2 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 2 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 2 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 2 -#define CALLING_OVERHEAD_REGION_DELETE 2 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 3 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 2 -#define CALLING_OVERHEAD_PORT_CREATE 3 -#define CALLING_OVERHEAD_PORT_IDENT 2 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 2 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 3 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 2 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme136/include/tm27.h b/c/src/lib/libbsp/m68k/mvme136/include/tm27.h deleted file mode 100644 index 66771bfdd6..0000000000 --- a/c/src/lib/libbsp/m68k/mvme136/include/tm27.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * @file - * @ingroup m68k_mvme136 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Use the MPCSR vector for the MVME136 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 75, 1 ) - -#define Cause_tm27_intr() (*(volatile uint8_t*)0xfffb006b) = 0x80 - -#define Clear_tm27_intr() (*(volatile uint8_t*)0xfffb006b) = 0x00 - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme147/include/bsp.h b/c/src/lib/libbsp/m68k/mvme147/include/bsp.h deleted file mode 100644 index 8fde25513a..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147/include/bsp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* bsp.h - * - * This include file contains all MVME147 board IO definitions. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * MVME147 port for TNI - Telecom Bretagne - * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) - * May 1996 - */ - -#ifndef LIBBSP_M68K_MVME147_BSP_H -#define LIBBSP_M68K_MVME147_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -#define RAM_START 0x00005000 -#define RAM_END 0x00400000 - - /* MVME 147 Peripheral controller chip - see MVME147/D1, 3.4 */ - -struct pcc_map { - /* 32 bit registers */ - uint32_t dma_table_address; /* 0xfffe1000 */ - uint32_t dma_data_address; /* 0xfffe1004 */ - uint32_t dma_bytecount; /* 0xfffe1008 */ - uint32_t dma_data_holding; /* 0xfffe100c */ - - /* 16 bit registers */ - uint16_t timer1_preload; /* 0xfffe1010 */ - uint16_t timer1_count; /* 0xfffe1012 */ - uint16_t timer2_preload; /* 0xfffe1014 */ - uint16_t timer2_count; /* 0xfffe1016 */ - - /* 8 bit registers */ - uint8_t timer1_int_control; /* 0xfffe1018 */ - uint8_t timer1_control; /* 0xfffe1019 */ - uint8_t timer2_int_control; /* 0xfffe101a */ - uint8_t timer2_control; /* 0xfffe101b */ - - uint8_t acfail_int_control; /* 0xfffe101c */ - uint8_t watchdog_control; /* 0xfffe101d */ - - uint8_t printer_int_control; /* 0xfffe101e */ - uint8_t printer_control; /* 0xfffe102f */ - - uint8_t dma_int_control; /* 0xfffe1020 */ - uint8_t dma_control; /* 0xfffe1021 */ - uint8_t bus_error_int_control; /* 0xfffe1022 */ - uint8_t dma_status; /* 0xfffe1023 */ - uint8_t abort_int_control; /* 0xfffe1024 */ - uint8_t table_address_function_code; /* 0xfffe1025 */ - uint8_t serial_port_int_control; /* 0xfffe1026 */ - uint8_t general_purpose_control; /* 0xfffe1027 */ - uint8_t lan_int_control; /* 0xfffe1028 */ - uint8_t general_purpose_status; /* 0xfffe1029 */ - uint8_t scsi_port_int_control; /* 0xfffe102a */ - uint8_t slave_base_address; /* 0xfffe102b */ - uint8_t software_int_1_control; /* 0xfffe102c */ - uint8_t int_base_vector; /* 0xfffe102d */ - uint8_t software_int_2_control; /* 0xfffe102e */ - uint8_t revision_level; /* 0xfffe102f */ -}; - -#define pcc ((volatile struct pcc_map * const) 0xfffe1000) - -#define z8530 0xfffe3001 - -/* interrupt vectors - see MVME146/D1 4.14 */ -#define PCC_BASE_VECTOR 0x40 /* First user int */ -#define SCC_VECTOR PCC_BASE_VECTOR+3 -#define TIMER_1_VECTOR PCC_BASE_VECTOR+8 -#define TIMER_2_VECTOR PCC_BASE_VECTOR+9 -#define SOFT_1_VECTOR PCC_BASE_VECTOR+10 -#define SOFT_2_VECTOR PCC_BASE_VECTOR+11 - -#define USE_CHANNEL_A 1 /* 1 = use channel A for console */ -#define USE_CHANNEL_B 0 /* 1 = use channel B for console */ - -#if (USE_CHANNEL_A == 1) -#define CONSOLE_CONTROL 0xfffe3002 -#define CONSOLE_DATA 0xfffe3003 -#elif (USE_CHANNEL_B == 1) -#define CONSOLE_CONTROL 0xfffe3000 -#define CONSOLE_DATA 0xfffe3001 -#endif - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme147/include/coverhd.h b/c/src/lib/libbsp/m68k/mvme147/include/coverhd.h deleted file mode 100644 index 9804440497..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147/include/coverhd.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * @ingroup m68k_mvme147 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C on this target. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 2 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 2 -#define CALLING_OVERHEAD_TASK_START 2 -#define CALLING_OVERHEAD_TASK_RESTART 2 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 2 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 2 -#define CALLING_OVERHEAD_TASK_MODE 2 -#define CALLING_OVERHEAD_TASK_GET_NOTE 2 -#define CALLING_OVERHEAD_TASK_SET_NOTE 2 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 2 -#define CALLING_OVERHEAD_CLOCK_GET 5 -#define CALLING_OVERHEAD_CLOCK_SET 4 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 2 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 2 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 3 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 2 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 2 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 2 - -#define CALLING_OVERHEAD_EVENT_SEND 2 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 2 -#define CALLING_OVERHEAD_SIGNAL_SEND 2 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 2 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 2 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 2 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 2 -#define CALLING_OVERHEAD_REGION_DELETE 2 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 3 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 2 -#define CALLING_OVERHEAD_PORT_CREATE 3 -#define CALLING_OVERHEAD_PORT_IDENT 2 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 2 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 3 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 2 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme147/include/tm27.h b/c/src/lib/libbsp/m68k/mvme147/include/tm27.h deleted file mode 100644 index 5b548a888a..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147/include/tm27.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * @file - * @ingroup m68k_mvme147 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Use the MPCSR vector for the MVME147 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), \ - SOFT_1_VECTOR, 1 ) - -#define Cause_tm27_intr() pcc->software_int_1_control = 0x0c - /* generate level 4 sotware int. */ - -#define Clear_tm27_intr() pcc->software_int_1_control = 0x00 - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme147s/include/bsp.h b/c/src/lib/libbsp/m68k/mvme147s/include/bsp.h deleted file mode 100644 index 7f95697c12..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147s/include/bsp.h +++ /dev/null @@ -1,195 +0,0 @@ -/* bsp.h - * - * This include file contains all MVME147 board IO definitions. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * MVME147 port for TNI - Telecom Bretagne - * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) - * May 1996 - */ - -#ifndef LIBBSP_M68K_MVME147S_BSP_H -#define LIBBSP_M68K_MVME147S_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -#define RAM_START 0x00007000 -#define RAM_END 0x003e0000 -#define DRAM_END 0x00400000 - /* We leave 128k for the shared memory */ - - /* MVME 147 Peripheral controller chip - see MVME147/D1, 3.4 */ - -struct pcc_map { - /* 32 bit registers */ - uint32_t dma_table_address; /* 0xfffe1000 */ - uint32_t dma_data_address; /* 0xfffe1004 */ - uint32_t dma_bytecount; /* 0xfffe1008 */ - uint32_t dma_data_holding; /* 0xfffe100c */ - - /* 16 bit registers */ - uint16_t timer1_preload; /* 0xfffe1010 */ - uint16_t timer1_count; /* 0xfffe1012 */ - uint16_t timer2_preload; /* 0xfffe1014 */ - uint16_t timer2_count; /* 0xfffe1016 */ - - /* 8 bit registers */ - uint8_t timer1_int_control; /* 0xfffe1018 */ - uint8_t timer1_control; /* 0xfffe1019 */ - uint8_t timer2_int_control; /* 0xfffe101a */ - uint8_t timer2_control; /* 0xfffe101b */ - - uint8_t acfail_int_control; /* 0xfffe101c */ - uint8_t watchdog_control; /* 0xfffe101d */ - - uint8_t printer_int_control; /* 0xfffe101e */ - uint8_t printer_control; /* 0xfffe102f */ - - uint8_t dma_int_control; /* 0xfffe1020 */ - uint8_t dma_control; /* 0xfffe1021 */ - uint8_t bus_error_int_control; /* 0xfffe1022 */ - uint8_t dma_status; /* 0xfffe1023 */ - uint8_t abort_int_control; /* 0xfffe1024 */ - uint8_t table_address_function_code; /* 0xfffe1025 */ - uint8_t serial_port_int_control; /* 0xfffe1026 */ - uint8_t general_purpose_control; /* 0xfffe1027 */ - uint8_t lan_int_control; /* 0xfffe1028 */ - uint8_t general_purpose_status; /* 0xfffe1029 */ - uint8_t scsi_port_int_control; /* 0xfffe102a */ - uint8_t slave_base_address; /* 0xfffe102b */ - uint8_t software_int_1_control; /* 0xfffe102c */ - uint8_t int_base_vector; /* 0xfffe102d */ - uint8_t software_int_2_control; /* 0xfffe102e */ - uint8_t revision_level; /* 0xfffe102f */ -}; - -#define pcc ((volatile struct pcc_map * const) 0xfffe1000) - -/* VME chip configuration registers */ - -struct vme_lcsr_map { - uint8_t unused_1; - uint8_t system_controller; /* 0xfffe2001 */ - uint8_t unused_2; - uint8_t vme_bus_requester; /* 0xfffe2003 */ - uint8_t unused_3; - uint8_t master_configuration; /* 0xfffe2005 */ - uint8_t unused_4; - uint8_t slave_configuration; /* 0xfffe2007 */ - uint8_t unused_5; - uint8_t timer_configuration; /* 0xfffe2009 */ - uint8_t unused_6; - uint8_t slave_address_modifier; /* 0xfffe200b */ - uint8_t unused_7; - uint8_t master_address_modifier; /* 0xfffe200d */ - uint8_t unused_8; - uint8_t interrupt_handler_mask; /* 0xfffe200f */ - uint8_t unused_9; - uint8_t utility_interrupt_mask; /* 0xfffe2011 */ - uint8_t unused_10; - uint8_t utility_interrupt_vector; /* 0xfffe2013 */ - uint8_t unused_11; - uint8_t interrupt_request; /* 0xfffe2015 */ - uint8_t unused_12; - uint8_t vme_bus_status_id; /* 0xfffe2017 */ - uint8_t unused_13; - uint8_t bus_error_status; /* 0xfffe2019 */ - uint8_t unused_14; - uint8_t gcsr_base_address; /* 0xfffe201b */ -}; - -#define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000) - -struct vme_gcsr_map { - uint8_t unused_1; - uint8_t global_0; /* 0xfffe2021 */ - uint8_t unused_2; - uint8_t global_1; /* 0xfffe2023 */ - uint8_t unused_3; - uint8_t board_identification; /* 0xfffe2025 */ - uint8_t unused_4; - uint8_t general_purpose_0; /* 0xfffe2027 */ - uint8_t unused_5; - uint8_t general_purpose_1; /* 0xfffe2029 */ - uint8_t unused_6; - uint8_t general_purpose_2; /* 0xfffe202b */ - uint8_t unused_7; - uint8_t general_purpose_3; /* 0xfffe202d */ - uint8_t unused_8; - uint8_t general_purpose_4; /* 0xfffe202f */ -}; - -#define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020) - -#define z8530 0xfffe3001 - -/* interrupt vectors - see MVME147/D1 4.14 */ -#define PCC_BASE_VECTOR 0x40 /* First user int */ -#define SCC_VECTOR PCC_BASE_VECTOR+3 -#define TIMER_1_VECTOR PCC_BASE_VECTOR+8 -#define TIMER_2_VECTOR PCC_BASE_VECTOR+9 -#define SOFT_1_VECTOR PCC_BASE_VECTOR+10 -#define SOFT_2_VECTOR PCC_BASE_VECTOR+11 - -#define VME_BASE_VECTOR 0x50 -#define VME_SIGLP_VECTOR VME_BASE_VECTOR+1 - -#define USE_CHANNEL_A 1 /* 1 = use channel A for console */ -#define USE_CHANNEL_B 0 /* 1 = use channel B for console */ - -#if (USE_CHANNEL_A == 1) -#define CONSOLE_CONTROL 0xfffe3002 -#define CONSOLE_DATA 0xfffe3003 -#elif (USE_CHANNEL_B == 1) -#define CONSOLE_CONTROL 0xfffe3000 -#define CONSOLE_DATA 0xfffe3001 -#endif - -#define FOREVER 1 /* infinite loop */ - -#ifdef M147_INIT -#undef EXTERN -#define EXTERN -#else -#undef EXTERN -#define EXTERN extern -#endif - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* - * NOTE: Use the standard Clock driver entry - */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme147s/include/coverhd.h b/c/src/lib/libbsp/m68k/mvme147s/include/coverhd.h deleted file mode 100644 index d4c0d8bca3..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147s/include/coverhd.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * @ingroup m68k_mvme147s - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C on this target. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 2 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 2 -#define CALLING_OVERHEAD_TASK_START 2 -#define CALLING_OVERHEAD_TASK_RESTART 2 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 2 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 2 -#define CALLING_OVERHEAD_TASK_MODE 2 -#define CALLING_OVERHEAD_TASK_GET_NOTE 2 -#define CALLING_OVERHEAD_TASK_SET_NOTE 2 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 2 -#define CALLING_OVERHEAD_CLOCK_GET 5 -#define CALLING_OVERHEAD_CLOCK_SET 4 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 2 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 2 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 3 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 2 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 2 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 3 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 2 - -#define CALLING_OVERHEAD_EVENT_SEND 2 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 2 -#define CALLING_OVERHEAD_SIGNAL_SEND 2 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 2 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 2 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 2 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 2 -#define CALLING_OVERHEAD_REGION_DELETE 2 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 3 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 2 -#define CALLING_OVERHEAD_PORT_CREATE 3 -#define CALLING_OVERHEAD_PORT_IDENT 2 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 2 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 3 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 2 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme147s/include/tm27.h b/c/src/lib/libbsp/m68k/mvme147s/include/tm27.h deleted file mode 100644 index 48ae0f459a..0000000000 --- a/c/src/lib/libbsp/m68k/mvme147s/include/tm27.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * @file - * @ingroup m68k_mvme147s - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Use the MPCSR vector for the MVME147 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), \ - SOFT_1_VECTOR, 1 ) - -#define Cause_tm27_intr() pcc->software_int_1_control = 0x0c - /* generate level 4 sotware int. */ - -#define Clear_tm27_intr() pcc->software_int_1_control = 0x00 - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme162/include/bsp.h b/c/src/lib/libbsp/m68k/mvme162/include/bsp.h deleted file mode 100644 index e16f48e285..0000000000 --- a/c/src/lib/libbsp/m68k/mvme162/include/bsp.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * This include file contains all MVME162fx board IO definitions. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. - * EISCAT Scientific Association. M.Savitski - * - * This material is a part of the MVME162 Board Support Package - * for the RTEMS executive. Its licensing policies are those of the - * RTEMS above. - */ - -#ifndef LIBBSP_M68K_MVME162_BSP_H -#define LIBBSP_M68K_MVME162_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> - -#include <mvme16x_hw.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------------*/ - -typedef volatile struct { - - unsigned char chipID; - unsigned char chipREV; - unsigned char gen_control; - unsigned char vector_base; - - unsigned long timer_cmp_1; - unsigned long timer_cnt_1; - unsigned long timer_cmp_2; - unsigned long timer_cnt_2; - - unsigned char LSB_prescaler_count; - unsigned char prescaler_clock_adjust; - unsigned char time_ctl_2; - unsigned char time_ctl_1; - - unsigned char time_int_ctl_4; - unsigned char time_int_ctl_3; - unsigned char time_int_ctl_2; - unsigned char time_int_ctl_1; - - unsigned char dram_err_int_ctl; - unsigned char SCC_int_ctl; - unsigned char time_ctl_4; - unsigned char time_ctl_3; - - unsigned short DRAM_space_base; - unsigned short SRAM_space_base; - - unsigned char DRAM_size; - unsigned char DRAM_SRAM_opt; - unsigned char SRAM_size; - unsigned char reserved; - - unsigned char LANC_error; - unsigned char reserved1; - unsigned char LANC_int_ctl; - unsigned char LANC_berr_ctl; - - unsigned char SCSI_error; - unsigned char general_inputs; - unsigned char MVME_162_version; - unsigned char SCSI_int_ctl; - - unsigned long timer_cmp_3; - unsigned long timer_cnt_3; - unsigned long timer_cmp_4; - unsigned long timer_cnt_4; - - unsigned char bus_clk; - unsigned char PROM_acc_time_ctl; - unsigned char FLASH_acc_time_ctl; - unsigned char ABORT_int_ctl; - - unsigned char RESET_ctl; - unsigned char watchdog_timer_ctl; - unsigned char acc_watchdog_time_base_sel; - unsigned char reserved2; - - unsigned char DRAM_ctl; - unsigned char reserved4; - unsigned char MPU_status; - unsigned char reserved3; - - unsigned long prescaler_count; - -} mcchip_regs; - -#define mcchip ((mcchip_regs * const) 0xFFF42000) - -/*----------------------------------------------------------------*/ - -/* - * SCC Z8523(0) defines and macros - * ------------------------------- - * Prototypes for the low-level serial io are also included here, - * because such stuff is bsp-specific (yet). The function bodies - * are in console.c - * - * NOTE from Eric Vaitl <evaitl@viasat.com>: - * - * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a - * bug in the MC2 chip (revision 1) such that the SCC data register is - * not accessible, it has to be accessed indirectly through the SCC - * control register. - */ - -enum {portB, portA}; - -extern bool char_ready(int port, char *ch); -extern char char_wait(int port); -extern void char_put(int port, char ch); - -#define TX_BUFFER_EMPTY 0x04 -#define RX_DATA_AVAILABLE 0x01 -#define SCC_VECTOR 0x40 - -typedef volatile struct { - unsigned char pad1; - volatile unsigned char csr; - unsigned char pad2; - volatile unsigned char buf; -} scc_regs; - -#define scc ((scc_regs * const) 0xFFF45000) - -#define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v)) -#define ZREAD0(port) (scc[port].csr) - -#define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr)) -#define ZREADD(port) (scc[port].csr=0x08, scc[port].csr ) - -#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v)) -#define ZWRITED(port, v) (scc[port].csr = 0x08, \ - scc[port].csr = (unsigned char)(v)) -/*----------------------------------------------------------------*/ - -#ifdef M162_INIT -#undef EXTERN -#define EXTERN -#else -#undef EXTERN -#define EXTERN extern -#endif - -/* - * This value is the default address location of the 162Bug vector table - * and is also the default start address of the boards DRAM. This value - * may be different for your specific board based on a number of factors: - * - * Default DRAM address: 0x00000000 - * Default SRAM address: 0xFFE00000 - * - * o If no DRAM can be found by the 162Bug program, it will use SRAM. - * o The default SRAM address may be different if SRAM mezzanine boards - * are installed on the main board. - * o Both the DRAM and SRAM addresses can be modified by changing the - * appropriate values in NVRAM using the ENV command at the 162Bug - * prompt. - * - * If your board has different values than the defaults, change the value - * of the following define. - * - */ -#define MOT_162BUG_VEC_ADDRESS 0x00000000 - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Prototypes for methods in the BSP that cross file boundaries. - */ -bool char_ready(int port, char *ch); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme162/include/coverhd.h b/c/src/lib/libbsp/m68k/mvme162/include/coverhd.h deleted file mode 100644 index 3752286643..0000000000 --- a/c/src/lib/libbsp/m68k/mvme162/include/coverhd.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * @ingroup m68k_mvme162 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C on this target. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 2 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 2 -#define CALLING_OVERHEAD_TASK_START 2 -#define CALLING_OVERHEAD_TASK_RESTART 2 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 2 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 2 -#define CALLING_OVERHEAD_TASK_MODE 2 -#define CALLING_OVERHEAD_TASK_GET_NOTE 2 -#define CALLING_OVERHEAD_TASK_SET_NOTE 2 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 2 -#define CALLING_OVERHEAD_CLOCK_GET 4 -#define CALLING_OVERHEAD_CLOCK_SET 4 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 2 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 2 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 2 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 2 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 2 - -#define CALLING_OVERHEAD_EVENT_SEND 2 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 2 -#define CALLING_OVERHEAD_SIGNAL_SEND 2 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 2 -#define CALLING_OVERHEAD_PARTITION_DELETE 2 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 2 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 2 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 2 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 3 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 2 -#define CALLING_OVERHEAD_PORT_CREATE 3 -#define CALLING_OVERHEAD_PORT_IDENT 2 -#define CALLING_OVERHEAD_PORT_DELETE 2 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 2 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 3 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 2 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 2 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 2 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme162/include/page_table.h b/c/src/lib/libbsp/m68k/mvme162/include/page_table.h deleted file mode 100644 index 09b93a49bd..0000000000 --- a/c/src/lib/libbsp/m68k/mvme162/include/page_table.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file was submitted by Eric Vaitl <vaitl@viasat.com> and - * supports page table initialization. - */ - -#ifndef PAGE_TABLE_H -#define PAGE_TABLE_H - -extern void page_table_teardown(void); -extern void page_table_init(void); -extern int page_table_map(void *addr, unsigned long size, int cache_type); - -enum { - CACHE_WRITE_THROUGH, - CACHE_COPYBACK, - CACHE_NONE_SERIALIZED, - CACHE_NONE -}; -enum { - PTM_SUCCESS, - PTM_BAD_ADDR, - PTM_BAD_SIZE, - PTM_BAD_CACHE, - PTM_NO_TABLE_SPACE -}; - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme162/include/tm27.h b/c/src/lib/libbsp/m68k/mvme162/include/tm27.h deleted file mode 100644 index 750408d009..0000000000 --- a/c/src/lib/libbsp/m68k/mvme162/include/tm27.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * @file - * @ingroup m68k_mvme162 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: We use software interrupt 0 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ - lcsr->intr_level[2] |= 3; \ - lcsr->intr_ena |= 0x100; - -#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 - -#define Clear_tm27_intr() lcsr->intr_clear |= 0x100 - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme167/include/bsp.h b/c/src/lib/libbsp/m68k/mvme167/include/bsp.h deleted file mode 100644 index c9e449d5fa..0000000000 --- a/c/src/lib/libbsp/m68k/mvme167/include/bsp.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - * @file - * - * Following defines must reflect the setup of the particular MVME167. - * All page references are to the MVME166/MVME167/MVME187 Single Board - * Computer Programmer's Reference Guide (MVME187PG/D2) with the April - * 1993 supplements/addenda (MVME187PG/D2A1). - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modifications of respective RTEMS file: - * Copyright (c) 1998, National Research Council of Canada - */ - -#ifndef LIBBSP_M68K_MVME167_BSP_H -#define LIBBSP_M68K_MVME167_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -#include <mvme16x_hw.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* GCSR is in mvme16x_hw.h */ -/* LCSR is in mvme16x_hw.h */ -/* i82596 is in mvme16x_hw.h */ -/* NVRAM is in mvme16x_hw.h */ - -#if 0 -/* - * Representation of the PCCchip2 - */ -typedef volatile struct pccchip2_regs_ { - unsigned char chip_id; /* 0xFFF42000 */ - unsigned char chip_revision; /* 0xFFF42001 */ - unsigned char gen_control; /* 0xFFF42002 */ - unsigned char vector_base; /* 0xFFF42003 */ - unsigned long timer_cmp_1; /* 0xFFF42004 */ - unsigned long timer_cnt_1; /* 0xFFF42008 */ - unsigned long timer_cmp_2; /* 0xFFF4200C */ - unsigned long timer_cnt_2; /* 0xFFF42010 */ - unsigned char LSB_prescaler_count;/* 0xFFF42014 */ - unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ - unsigned char timer_ctl_2; /* 0xFFF42016 */ - unsigned char timer_ctl_1; /* 0xFFF42017 */ - unsigned char gpi_int_ctl; /* 0xFFF42018 */ - unsigned char gpio_ctl; /* 0xFFF42019 */ - unsigned char timer_int_ctl_2; /* 0xFFF4201A */ - unsigned char timer_int_ctl_1; /* 0xFFF4201B */ - unsigned char SCC_error; /* 0xFFF4201C */ - unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ - unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ - unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ - unsigned char reserved1[3]; - unsigned char modem_piack; /* 0xFFF42023 */ - unsigned char reserved2; - unsigned char tx_piack; /* 0xFFF42025 */ - unsigned char reserved3; - unsigned char rx_piack; /* 0xFFF42027 */ - unsigned char LANC_error; /* 0xFFF42028 */ - unsigned char reserved4; - unsigned char LANC_int_ctl; /* 0xFFF4202A */ - unsigned char LANC_berr_ctl; /* 0xFFF4202B */ - unsigned char SCSI_error; /* 0xFFF4202C */ - unsigned char reserved5[2]; - unsigned char SCSI_int_ctl; /* 0xFFF4202F */ - unsigned char print_ack_int_ctl; /* 0xFFF42030 */ - unsigned char print_fault_int_ctl;/* 0xFFF42031 */ - unsigned char print_sel_int_ctl; /* 0xFFF42032 */ - unsigned char print_pe_int_ctl; /* 0xFFF42033 */ - unsigned char print_busy_int_ctl; /* 0xFFF42034 */ - unsigned char reserved6; - unsigned char print_input_status; /* 0xFFF42036 */ - unsigned char print_ctl; /* 0xFFF42037 */ - unsigned char chip_speed; /* 0xFFF42038 */ - unsigned char reserved7; - unsigned char print_data; /* 0xFFF4203A */ - unsigned char reserved8[3]; - unsigned char int_level; /* 0xFFF4203E */ - unsigned char int_mask; /* 0xFFF4203F */ -} pccchip2_regs; - -/* - * Base address of the PCCchip2. - * This is not configurable in the MVME167. - */ -#define pccchip2 ((pccchip2_regs * const) 0xFFF42000) - -#endif -/* - * The MVME167 is equiped with one or two MEMC040 memory controllers at - * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers - * were initialized by 167Bug. - */ -typedef volatile struct memc040_regs_ { - unsigned char chip_id; /* 0xFFF43000/0xFFF43100 */ - unsigned char reserved1[3]; - unsigned char chip_revision; /* 0xFFF43004/0xFFF43104 */ - unsigned char reserved2[3]; - unsigned char mem_config; /* 0xFFF43008/0xFFF43108 */ - unsigned char reserved3[3]; - unsigned char alt_status; /* 0xFFF4300C/0xFFF4310C */ - unsigned char reserved4[3]; - unsigned char alt_ctl; /* 0xFFF43010/0xFFF43110 */ - unsigned char reserved5[3]; - unsigned char base_addr; /* 0xFFF43014/0xFFF43114 */ - unsigned char reserved6[3]; - unsigned char ram_ctl; /* 0xFFF43018/0xFFF43118 */ - unsigned char reserved7[3]; - unsigned char bus_clk; /* 0xFFF4301C/0xFFF4311C */ -} memc040_regs; - -/* - * Base address of the MEMC040s. - * This is not configurable in the MVME167. - */ -#define memc040_1 ((memc040_regs * const) 0xFFF43000) -#define memc040_2 ((memc040_regs * const) 0xFFF43100) - -/* - * The MVME167 may be equiped with error-correcting RAM cards. In this case, - * each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port - * assumes that these controllers, if present, are initialized by 167Bug. - * They do not appear to hold information of interest at this time, so they - * are not described. However, each MCECC pair lives at the same address as - * the MEMC040 is replaces. The first eight registers of the MCECC are - * nearly identical to the ones of the MEMC040, and the memc040_X structures - * can be used to read those first eight registers. - */ - -/* - * Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller - */ -typedef volatile struct cd2401_regs_ { - unsigned char reserved1[7]; - unsigned char cor7; /* 0xFFF45007 - Channel Option 7 */ - unsigned char reserved2; - unsigned char livr; /* 0xFFF45009 - Local Interrupt Vector */ - unsigned char reserved3[6]; - unsigned char cor1; /* 0xFFF45010 - Channel Option 1 */ - unsigned char ier; /* 0xFFF45011 - Interrupt Enable */ - unsigned char stcr; /* 0xFFF45012 - Special Transmit Command */ - unsigned char ccr; /* 0xFFF45013 - Channel Command */ - unsigned char cor5; /* 0xFFF45014 - Channel Option 5 */ - unsigned char cor4; /* 0xFFF45015 - Channel Option 4 */ - unsigned char cor3; /* 0xFFF45016 - Channel Option 3 */ - unsigned char cor2; /* 0xFFF45017 - Channel Option 2 */ - unsigned char cor6; /* 0xFFF45018 - Channel Option 6 */ - unsigned char dmabsts; /* 0xFFF45019 - DMA Buffer Status */ - unsigned char csr; /* 0xFFF4501A - Channel Status */ - unsigned char cmr; /* 0xFFF4501B - Channel Mode */ - union { - struct { - unsigned char schr4; /* 0xFFF4501C - Special Character 4 */ - unsigned char schr3; /* 0xFFF4501D - Special Character 3 */ - unsigned char schr2; /* 0xFFF4501E - Special Character 2 */ - unsigned char schr1; /* 0xFFF4501F - Special Character 1 */ - } async; - struct { - unsigned char rfar4; /* 0xFFF4501C - Receive Frame Address 4 */ - unsigned char rfar3; /* 0xFFF4501D - Receive Frame Address 3 */ - unsigned char rfar2; /* 0xFFF4501E - Receive Frame Address 2 */ - unsigned char rfar1; /* 0xFFF4501F - Receive Frame Address 1 */ - } sync; - } u1; - unsigned char reserved4[2]; - unsigned char scrh; /* 0xFFF45022 - Special Character Range High */ - unsigned char scrl; /* 0xFFF45023 - Special Character Range Low */ - union { - struct { - unsigned short rtpr; /* 0xFFF45024 - Receive Timeout Period */ - } w; - struct { - unsigned char rtprh; /* 0xFFF45024 - Receive Timeout Period High */ - unsigned char rtprl; /* 0xFFF45025 - Receive Timeout Period Low */ - } b; - } u2; - unsigned char licr; /* 0xFFF45026 - Local Interrupt Channel */ - unsigned char reserved5[2]; - union { - struct { - unsigned char ttr; /* 0xFFF45029 - Transmit Timer */ - } async; - struct { - unsigned char gt2; /* 0xFFF45029 - General Timer 2 */ - } sync; - } u3; - union { - struct { - unsigned short gt1; /* 0xFFF4502A - General Timer 1 */ - } w; - struct { - unsigned char gt1h; /* 0xFFF4502A - General Timer 2 High */ - unsigned char gt1l; /* 0xFFF4502B - General Timer 1 Low */ - } b; - } u4; - unsigned char reserved6[2]; - unsigned char lnxt; /* 0xFF4502E - LNext Character */ - unsigned char reserved7; - unsigned char rfoc; /* 0xFFF45030 - Receive FIFO Output Count */ - unsigned char reserved8[7]; - unsigned short tcbadru; /* 0xFF45038 - Transmit Current Buffer Address Upper */ - unsigned short tcbadrl; /* 0xFF4503A - Transmit Current Buffer Address Lower */ - unsigned short rcbadru; /* 0xFF4503C - Receive Current Buffer Address Upper */ - unsigned short rcbadrl; /* 0xFF4503E - Receive Current Buffer Address Lower */ - unsigned short arbadru; /* 0xFF45040 - A Receive Buffer Address Upper */ - unsigned short arbardl; /* 0xFF45042 - A Receive Buffer Address Lower */ - unsigned short brbadru; /* 0xFF45044 - B Receive Buffer Address Upper */ - unsigned short brbadrl; /* 0xFF45046 - B Receive Buffer Address Lower */ - unsigned short brbcnt; /* 0xFF45048 - B Receive Buffer Byte Count */ - unsigned short arbcnt; /* 0xFF4504A - A Receive Buffer Byte Count */ - unsigned short reserved9; - unsigned char brbsts; /* 0xFF4504E - B Receive Buffer Status */ - unsigned char arbsts; /* 0xFF4504F - A Receive Buffer Status */ - unsigned short atbadru; /* 0xFF45050 - A Transmit Buffer Address Upper */ - unsigned short atbadrl; /* 0xFF45052 - A Transmit Buffer Address Lower */ - unsigned short btbadru; /* 0xFF45054 - B Transmit Buffer Address Upper */ - unsigned short btbadrl; /* 0xFF45056 - B Transmit Buffer Address Lower */ - unsigned short btbcnt; /* 0xFF45058 - B Transmit Buffer Byte Count */ - unsigned short atbcnt; /* 0xFF4505A - A Transmit Buffer Byte Count */ - unsigned short reserved10; - unsigned char btbsts; /* 0xFF4505E - B Transmit Buffer Status */ - unsigned char atbsts; /* 0xFF4505F - A Transmit Buffer Status */ - unsigned char reserved11[32]; - unsigned char tftc; /* 0xFFF45080 - Transmit FIFO Transfer Count */ - unsigned char gfrcr; /* 0xFFF45081 - Global Firmware Revision Code */ - unsigned char reserved12[2]; - unsigned char reoir; /* 0xFFF45084 - Receive End Of Interrupt */ - unsigned char teoir; /* 0xFFF45085 - Transmit End Of Interrupt */ - unsigned char meoir; /* 0xFFF45086 - Modem End Of Interrupt */ - union { - struct { - unsigned short risr; /* 0xFFF45088 - Receive Interrupt Status */ - } w; - struct { - unsigned char risrh; /* 0xFFF45088 - Receive Interrupt Status High */ - unsigned char risrl; /* 0xFFF45089 - Receive Interrupt Status Low */ - } b; - } u5; - unsigned char tisr; /* 0xFFF4508A - Transmit Interrupt Status */ - unsigned char misr; /* 0xFFF4508B - Modem/Timer Interrupt Status */ - unsigned char reserved13[2]; - unsigned char bercnt; /* 0xFFF4508E - Bus Error Retry Count */ - unsigned char reserved14[49]; - unsigned char tcor; /* 0xFFF450C0 - Transmit Clock Option */ - unsigned char reserved15[2]; - unsigned char tbpr; /* 0xFFF450C3 - Transmit Baud Rate Period */ - unsigned char reserved16[4]; - unsigned char rcor; /* 0xFFF450C8 - Receive Clock Option */ - unsigned char reserved17[2]; - unsigned char rbpr; /* 0xFFF450CB - Receive Baud Rate Period */ - unsigned char reserved18[10]; - unsigned char cpsr; /* 0xFFF450D6 - CRC Polynomial Select */ - unsigned char reserved19[3]; - unsigned char tpr; /* 0xFFF450DA - Timer Period */ - unsigned char reserved20[3]; - unsigned char msvr_rts; /* 0xFFF450DE - Modem Signal Value - RTS */ - unsigned char msvr_dtr; /* 0xFFF450DF - Modem Signal Value - DTR */ - unsigned char tpilr; /* 0xFFF450E0 - Transmit Priority Interrupt Level */ - unsigned char rpilr; /* 0xFFF450E1 - Receive Priority Interrupt Level */ - unsigned char stk; /* 0xFFF450E2 - Stack */ - unsigned char mpilr; /* 0xFFF450E3 - Modem Priority Interrupt Level */ - unsigned char reserved21[8]; - unsigned char tir; /* 0xFFF450EC - Transmit Interrupt */ - unsigned char rir; /* 0xFFF450ED - Receive Interrupt */ - unsigned char car; /* 0xFFF450EE - Channel Access */ - unsigned char mir; /* 0xFFF450EF - Model Interrupt */ - unsigned char reserved22[6]; - unsigned char dmr; /* 0xFFF450F6 - DMA Mode */ - unsigned char reserved23; - unsigned char dr; /* 0xFFF450F8 - Receive/Transmit Data */ -} cd2401_regs; - -/* - * Base address of the CD2401. - * This is not configurable in the MVME167. - */ -#define cd2401 ((cd2401_regs * const) 0xFFF45000) - -/* CD2401 is clocked at 20 MHz */ -#define CD2401_CLK_RATE 20000000 - -/* BSP-wide functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -#ifdef M167_INIT -#undef EXTERN -#define EXTERN -#else -#undef EXTERN -#define EXTERN extern -#endif - -extern void *M68Kvec[]; /* vector table address */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme167/include/coverhd.h b/c/src/lib/libbsp/m68k/mvme167/include/coverhd.h deleted file mode 100644 index e7b48dcd59..0000000000 --- a/c/src/lib/libbsp/m68k/mvme167/include/coverhd.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * @ingroup m68k_mvme167 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C on this target. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 1 -#define CALLING_OVERHEAD_CLOCK_SET 1 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 1 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 1 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 1 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 1 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 1 - -#define CALLING_OVERHEAD_IO_INITIALIZE 1 -#define CALLING_OVERHEAD_IO_OPEN 1 -#define CALLING_OVERHEAD_IO_CLOSE 1 -#define CALLING_OVERHEAD_IO_READ 1 -#define CALLING_OVERHEAD_IO_WRITE 1 -#define CALLING_OVERHEAD_IO_CONTROL 1 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme167/include/page_table.h b/c/src/lib/libbsp/m68k/mvme167/include/page_table.h deleted file mode 100644 index 2db5591729..0000000000 --- a/c/src/lib/libbsp/m68k/mvme167/include/page_table.h +++ /dev/null @@ -1,43 +0,0 @@ -/* page_table.h - * - * This file was submitted by Eric Vaitl <vaitl@viasat.com> and - * supports page table initialization. - * - * For now, we only use the transparent translation registers. Page tables - * may be set up in the future. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modifications of respective RTEMS files: - * Copyright (c) 1998, National Research Council of Canada - */ - -#ifndef __PAGE_TABLE_H -#define __PAGE_TABLE_H - -#include <rtems.h> - -void page_table_teardown( void ); -void page_table_init( void ); - -enum { - CACHE_WRITE_THROUGH, - CACHE_COPYBACK, - CACHE_NONE_SERIALIZED, - CACHE_NONE -}; - -enum { - PTM_SUCCESS, - PTM_BAD_ADDR, - PTM_BAD_SIZE, - PTM_BAD_CACHE, - PTM_NO_TABLE_SPACE -}; - -#endif diff --git a/c/src/lib/libbsp/m68k/mvme167/include/tm27.h b/c/src/lib/libbsp/m68k/mvme167/include/tm27.h deleted file mode 100644 index 5b65311794..0000000000 --- a/c/src/lib/libbsp/m68k/mvme167/include/tm27.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * @file - * @ingroup m68k_mvme167 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: We use software interrupt 0 - */ -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ - lcsr->intr_level[2] |= 3; \ - lcsr->intr_ena |= 0x100 - -#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 - -#define Clear_tm27_intr() lcsr->intr_clear |= 0x100 - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/m68k/ods68302/include/bsp.h b/c/src/lib/libbsp/m68k/ods68302/include/bsp.h deleted file mode 100644 index 357963c09c..0000000000 --- a/c/src/lib/libbsp/m68k/ods68302/include/bsp.h +++ /dev/null @@ -1,100 +0,0 @@ -/* bsp.h - * - * This include file contains all board IO definitions. - */ - -/* - * COPYRIGHT (c) 1989-2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_ODS68302_BSP_H -#define LIBBSP_M68K_ODS68302_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <rtems/clockdrv.h> -#include <rtems/m68k/m68302.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef VARIANT -#define VARIANT bare -#endif -#if defined(VARIANT) -#define HQUOTE(a) <a.h> -#include HQUOTE(VARIANT) -#undef HQUOTE -#endif - -/* Constants */ - -#define RAM_START RAM_BASE -#define RAM_END (RAM_BASE + RAM_SIZE) - -/* Structures */ - -#ifdef GEN68302_INIT -#undef EXTERN -#define EXTERN -#else -#undef EXTERN -#define EXTERN extern -#endif - -extern rtems_isr_entry M68Kvec[]; /* vector table address */ - -/* functions */ - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Prototypes for methods called only from .S files - */ -void boot_phase_1(void); -void boot_phase_2(void); -void boot_phase_3(void); -void trace_exception( - unsigned long d0, - unsigned long d1, - unsigned long d2, - unsigned long d3, - unsigned long d4, - unsigned long d5, - unsigned long d6, - unsigned long d7, - unsigned long a0, - unsigned long a1, - unsigned long a2, - unsigned long a3, - unsigned long a4, - unsigned long a5, - unsigned long a6, - unsigned long a7, - unsigned long sr_pch, - unsigned long pcl_format -); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/ods68302/include/coverhd.h b/c/src/lib/libbsp/m68k/ods68302/include/coverhd.h deleted file mode 100644 index 84ca3a8f03..0000000000 --- a/c/src/lib/libbsp/m68k/ods68302/include/coverhd.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * @file - * @ingroup m68k_ods68302 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include all - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 14 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 11 -#define CALLING_OVERHEAD_TASK_CREATE 22 -#define CALLING_OVERHEAD_TASK_IDENT 17 -#define CALLING_OVERHEAD_TASK_START 18 -#define CALLING_OVERHEAD_TASK_RESTART 15 -#define CALLING_OVERHEAD_TASK_DELETE 12 -#define CALLING_OVERHEAD_TASK_SUSPEND 12 -#define CALLING_OVERHEAD_TASK_RESUME 12 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 16 -#define CALLING_OVERHEAD_TASK_MODE 15 -#define CALLING_OVERHEAD_TASK_GET_NOTE 16 -#define CALLING_OVERHEAD_TASK_SET_NOTE 16 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 31 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 11 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 17 -#define CALLING_OVERHEAD_CLOCK_GET 32 -#define CALLING_OVERHEAD_CLOCK_SET 31 -#define CALLING_OVERHEAD_CLOCK_TICK 8 - -#define CALLING_OVERHEAD_TIMER_CREATE 13 -#define CALLING_OVERHEAD_TIMER_IDENT 12 -#define CALLING_OVERHEAD_TIMER_DELETE 14 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 19 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 39 -#define CALLING_OVERHEAD_TIMER_RESET 12 -#define CALLING_OVERHEAD_TIMER_CANCEL 12 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 18 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 12 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 17 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 17 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 12 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 18 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 17 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 12 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 14 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 14 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 17 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 19 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 14 - -#define CALLING_OVERHEAD_EVENT_SEND 15 -#define CALLING_OVERHEAD_EVENT_RECEIVE 18 -#define CALLING_OVERHEAD_SIGNAL_CATCH 14 -#define CALLING_OVERHEAD_SIGNAL_SEND 14 -#define CALLING_OVERHEAD_PARTITION_CREATE 23 -#define CALLING_OVERHEAD_PARTITION_IDENT 17 -#define CALLING_OVERHEAD_PARTITION_DELETE 12 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 15 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 15 -#define CALLING_OVERHEAD_REGION_CREATE 23 -#define CALLING_OVERHEAD_REGION_IDENT 14 -#define CALLING_OVERHEAD_REGION_DELETE 12 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 21 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 15 -#define CALLING_OVERHEAD_PORT_CREATE 20 -#define CALLING_OVERHEAD_PORT_IDENT 14 -#define CALLING_OVERHEAD_PORT_DELETE 12 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 18 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 18 - -#define CALLING_OVERHEAD_IO_INITIALIZE 18 -#define CALLING_OVERHEAD_IO_OPEN 18 -#define CALLING_OVERHEAD_IO_CLOSE 18 -#define CALLING_OVERHEAD_IO_READ 18 -#define CALLING_OVERHEAD_IO_WRITE 18 -#define CALLING_OVERHEAD_IO_CONTROL 18 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 11 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 13 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 14 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 12 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 12 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 14 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 8 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/shared/include/linker-symbols.h b/c/src/lib/libbsp/m68k/shared/include/linker-symbols.h deleted file mode 100644 index 8bf5ebfa07..0000000000 --- a/c/src/lib/libbsp/m68k/shared/include/linker-symbols.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * - * @ingroup bsp_linker - * - * @brief Symbols defined in linker command base file. - */ - -/* - * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <info@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H -#define LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup bsp_linker Linker Support - * - * @ingroup bsp_kit - * - * @brief Linker support. - * - * @{ - */ - -#ifndef ASM - #define LINKER_SYMBOL(sym) extern char sym []; -#else - #define LINKER_SYMBOL(sym) .extern sym -#endif - -LINKER_SYMBOL(bsp_vector0_begin) -LINKER_SYMBOL(bsp_vector0_end) -LINKER_SYMBOL(bsp_vector0_size) - -LINKER_SYMBOL(bsp_vector1_begin) -LINKER_SYMBOL(bsp_vector1_end) -LINKER_SYMBOL(bsp_vector1_size) - -LINKER_SYMBOL(bsp_section_text_begin) -LINKER_SYMBOL(bsp_section_text_end) -LINKER_SYMBOL(bsp_section_text_size) -LINKER_SYMBOL(bsp_section_text_load_begin) -LINKER_SYMBOL(bsp_section_text_load_end) - -LINKER_SYMBOL(bsp_section_data_begin) -LINKER_SYMBOL(bsp_section_data_end) -LINKER_SYMBOL(bsp_section_data_size) -LINKER_SYMBOL(bsp_section_data_load_begin) -LINKER_SYMBOL(bsp_section_data_load_end) - -LINKER_SYMBOL(bsp_section_bss_begin) -LINKER_SYMBOL(bsp_section_bss_end) -LINKER_SYMBOL(bsp_section_bss_size) - -LINKER_SYMBOL(bsp_section_work_begin) -LINKER_SYMBOL(bsp_section_work_end) -LINKER_SYMBOL(bsp_section_work_size) - -LINKER_SYMBOL(bsp_initstack_begin) -LINKER_SYMBOL(bsp_initstack_end) -LINKER_SYMBOL(bsp_initstack_size) - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_M68K_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/m68k/uC5282/include/bsp.h b/c/src/lib/libbsp/m68k/uC5282/include/bsp.h deleted file mode 100644 index 05038111a4..0000000000 --- a/c/src/lib/libbsp/m68k/uC5282/include/bsp.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * uC5282 BSP header file - * - * Author: W. Eric Norum <norume@aps.anl.gov> - * - * COPYRIGHT (c) 2005. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_UC5282_BSP_H -#define LIBBSP_M68K_UC5282_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <rtems/bspIo.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************/ -/** BSP Configuration **/ -/* - * Uncomment to use instruction/data cache - * Leave commented to use instruction-only cache - */ -#define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include <mcf5282/mcf5282.h> /* internal MCF5282 modules */ - -/***************************************************************************/ -/** Network driver configuration **/ -struct rtems_bsdnet_ifconfig; -extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define which port the console should use - all other ports are then defined as general purpose */ -#define CONSOLE_PORT 0 - -/* functions */ - -typedef struct { - unsigned int l; - void *v; -} bsp_mnode_t; - -#define RTEMS_BSP_PGM_ERASE_FIRST 0x1 -#define RTEMS_BSP_PGM_RESET_AFTER 0x2 -#define RTEMS_BSP_PGM_EXEC_AFTER 0x4 -#define RTEMS_BSP_PGM_HALT_AFTER 0x8 - -uint32_t bsp_get_CPU_clock_speed(void); -rtems_status_code bsp_allocate_interrupt(int level, int priority); -int bsp_sysReset(int flags); -int bsp_program(bsp_mnode_t *chain, int flags); -unsigned const char *bsp_gethwaddr(int a); -const char *bsp_getbenv(const char *a); -int bsp_flash_erase_range(volatile unsigned short *flashptr, int start, int end); -int bsp_flash_write_range(volatile unsigned short *flashptr, bsp_mnode_t *chain, int offset); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ -#define FEC_IRQ_LEVEL 4 -#define FEC_IRQ_RX_PRIORITY 7 -#define FEC_IRQ_TX_PRIORITY 6 - -#define PIT3_IRQ_LEVEL 4 -#define PIT3_IRQ_PRIORITY 0 - -#define UART0_IRQ_LEVEL 3 -#define UART0_IRQ_PRIORITY 7 -#define UART1_IRQ_LEVEL 3 -#define UART1_IRQ_PRIORITY 6 -#define UART2_IRQ_LEVEL 3 -#define UART2_IRQ_PRIORITY 5 - -/* - * Fake VME support - * This makes it easier to use EPICS driver support on this BSP. - */ -#define VME_AM_STD_SUP_ASCENDING 0x3f -#define VME_AM_STD_SUP_PGM 0x3e -#define VME_AM_STD_USR_ASCENDING 0x3b -#define VME_AM_STD_USR_PGM 0x3a -#define VME_AM_STD_SUP_DATA 0x3d -#define VME_AM_STD_USR_DATA 0x39 -#define VME_AM_EXT_SUP_ASCENDING 0x0f -#define VME_AM_EXT_SUP_PGM 0x0e -#define VME_AM_EXT_USR_ASCENDING 0x0b -#define VME_AM_EXT_USR_PGM 0x0a -#define VME_AM_EXT_SUP_DATA 0x0d -#define VME_AM_EXT_USR_DATA 0x09 -#define VME_AM_SUP_SHORT_IO 0x2d -#define VME_AM_USR_SHORT_IO 0x29 - -/* - * 'Extended' BSP support - */ -rtems_status_code bspExtInit(void); -typedef void (*BSP_VME_ISR_t)(void *usrArg, unsigned long vector); -BSP_VME_ISR_t BSP_getVME_isr(unsigned long vector, void **parg); -int BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg); -int BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg); -int BSP_enableVME_int_lvl(unsigned int level); -int BSP_disableVME_int_lvl(unsigned int level); -int BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr); - -/* - * This BSP provides its own IDLE task to override the RTEMS one. - * So we prototype it and define the constant confdefs.h expects - * to configure a BSP specific one. - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* - * The custom IDLE task keeps some idle statistics. - */ -int bsp_cpu_load_percentage(void); - -/* - * This is a helper method to determine the cause of a reset. - */ -void bsp_reset_cause(char *buf, size_t capacity); - -/* - * SRAM. The BSP uses SRAM for maintaining some clock-driver data - * and for ethernet descriptors (and the initial stack during - * early boot). - */ - -typedef struct mcf5282BufferDescriptor_ { - volatile uint16_t status; - uint16_t length; - volatile void *buffer; -} mcf5282BufferDescriptor_t; - -extern struct { - uint32_t idle_counter; - uint32_t filtered_idle; - uint32_t max_idle_count; - uint32_t pitc_per_tick; - uint32_t nsec_per_pitc; - uint32_t pad[3]; /* align to 16-bytes for descriptors */ - mcf5282BufferDescriptor_t fec_descriptors[]; - /* buffer descriptors are allocated from here */ - - /* initial stack is at top of SRAM (start.S) */ -} __SRAMBASE; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/m68k/uC5282/include/tm27.h b/c/src/lib/libbsp/m68k/uC5282/include/tm27.h deleted file mode 100644 index 9a24da3755..0000000000 --- a/c/src/lib/libbsp/m68k/uC5282/include/tm27.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * @file - * @ingroup m68k_uC5282 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * Author: W. Eric Norum <norume@aps.anl.gov> - * - * COPYRIGHT (c) 2005-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/mips/csb350/include/bsp.h b/c/src/lib/libbsp/mips/csb350/include/bsp.h deleted file mode 100644 index b29df7c753..0000000000 --- a/c/src/lib/libbsp/mips/csb350/include/bsp.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * - * This include file contains some definitions specific to the - * Cogent CSB350 Board. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_CSB350_BSP_H -#define LIBBSP_MIPS_CSB350_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/au1x00.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -/* - * Network driver configuration - */ -extern struct rtems_bsdnet_ifconfig *config; - -int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config, - int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_au1x00_emac_attach - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/mips/csb350/include/irq.h b/c/src/lib/libbsp/mips/csb350/include/irq.h deleted file mode 100644 index 4f006fdd5f..0000000000 --- a/c/src/lib/libbsp/mips/csb350/include/irq.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief interrupt definitions. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_AU1X00_IRQ_H -#define LIBBSP_MIPS_AU1X00_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -/* - * Interrupt Vector Numbers - * - */ -/* MIPS_INTERRUPT_BASE should be 32 (0x20) */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) -#define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) -#define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) -#define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) -#define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) -#define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) -#define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) -#define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) - -#define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) -#define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) -#define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) -#define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) -#define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) -#define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) -#define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) -#define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) -#define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) -#define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) -#define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) -#define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) -#define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) -#define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) -#define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) -#define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) -#define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) -#define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) -#define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) -#define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) -#define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) -#define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) -#define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) -#define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) -#define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) -#define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) -#define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) -#define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) -#define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) -#define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) -#define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) -#define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) -#define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) - -#define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) -#define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) -#define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) -#define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) -#define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) -#define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) -#define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) -#define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) -#define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) -#define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) -#define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) -#define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) -#define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) -#define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) -#define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) -#define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) -#define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) -#define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) -#define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) -#define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) -#define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) -#define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) -#define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) -#define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) -#define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) -#define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) -#define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) -#define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) -#define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) -#define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) -#define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) -#define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) -#define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) - -#define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) - -#define BSP_INTERRUPT_VECTOR_MAX AU1X00_MAXIMUM_VECTORS - -/** @} */ - -#endif /* LIBBSP_MIPS_AU1X00_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/csb350/include/tm27.h b/c/src/lib/libbsp/mips/csb350/include/tm27.h deleted file mode 100644 index 3a8957d698..0000000000 --- a/c/src/lib/libbsp/mips/csb350/include/tm27.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/irq.h> - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -int assert_sw_irw(uint32_t irqnum); -int negate_sw_irw(uint32_t irqnum); - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) \ - rtems_interrupt_handler_install( \ - AU1X00_IRQ_SW0, "benchmark", 0, (rtems_interrupt_handler)handler, NULL ); - -#define Cause_tm27_intr() \ - do { \ - assert_sw_irq(0); \ - } while(0) - -#define Clear_tm27_intr() \ - do { \ - negate_sw_irq(0); \ - } while(0) - -#define Lower_tm27_intr() \ - do { \ - continue;\ - } while(0) - -#endif diff --git a/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h b/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h deleted file mode 100644 index ba0738c2a9..0000000000 --- a/c/src/lib/libbsp/mips/genmongoosev/include/bsp.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @file - * - * This include file contains some definitions specific to a board - * based upon the generic capabilities of a Mongoose-V. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_GENMONGOOSEV_BSP_H -#define LIBBSP_MIPS_GENMONGOOSEV_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/mongoose-v.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#ifndef CPU_CLOCK_RATE -#define CLOCK_RATE 12000000 -#endif - -#define CPU_CLOCK_RATE_HZ CLOCK_RATE -#define CPU_CLOCK_RATE_MHZ (CLOCK_RATE/1000000) - -/* - * Useful defines set here so we can avoid duplicating them all over - * creation. - * - */ - -/* - * assertSoftwareInt defined in vectorisrs.c the prototype is here so - * userspace code can get to it directly. - * */ - -extern void assertSoftwareInterrupt(uint32_t); - -#define CLOCK_VECTOR MONGOOSEV_IRQ_TIMER1 - -/* from start.S */ -extern void promCopyIcacheFlush(void); -extern void promCopyDcacheFlush(void); - -/* - * Called from user programs wanting to use the GDB stub. - */ -void mg5rdbgCloseGDBuart(void); -int mg5rdbgOpenGDBuart(int); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/c/src/lib/libbsp/mips/genmongoosev/include/irq.h b/c/src/lib/libbsp/mips/genmongoosev/include/irq.h deleted file mode 100644 index 7cfca650aa..0000000000 --- a/c/src/lib/libbsp/mips/genmongoosev/include/irq.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief interrupt definitions. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_MONGOOSEV_IRQ_H -#define LIBBSP_MIPS_MONGOOSEV_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -/* - * Interrupt Vector Numbers - * - * NOTE: IRQ INT5 is logical or of peripheral cause register - * per p. 5-22 of Mongoose-V manual. - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define MONGOOSEV_IRQ_INT0 MIPS_INTERRUPT_BASE+0 -#define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0 -#define MONGOOSEV_IRQ_INT1 MIPS_INTERRUPT_BASE+1 -#define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1 -#define MONGOOSEV_IRQ_INT2 MIPS_INTERRUPT_BASE+2 -#define MONGOOSEV_IRQ_INT3 MIPS_INTERRUPT_BASE+3 -#define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3 - -#define MONGOOSEV_IRQ_INT4 MIPS_INTERRUPT_BASE+4 - -/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */ -#define MONGOOSEV_IRQ_PERIPHERAL_BASE MIPS_INTERRUPT_BASE+5 -#define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0 -#define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1 -#define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2 -#define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3 -#define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4 -#define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5 -#define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6 -#define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7 -#define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8 -#define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9 -#define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10 -#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11 -#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12 -#define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13 -#define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14 -#define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15 -#define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16 -#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17 -#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18 -#define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19 -#define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20 -#define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21 -#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22 -#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23 -#define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24 -#define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25 -#define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26 -#define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27 -#define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28 -#define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29 -#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30 -#define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31 - -#define MONGOOSEV_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+37 -#define MONGOOSEV_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+38 -#define MONGOOSEV_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+39 - -#define BSP_INTERRUPT_VECTOR_MAX MONGOOSEV_MAXIMUM_VECTORS - -/** @} */ - -#endif /* LIBBSP_MIPS_MONGOOSEV_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/genmongoosev/include/tm27.h b/c/src/lib/libbsp/mips/genmongoosev/include/tm27.h deleted file mode 100644 index 8c2dd5e481..0000000000 --- a/c/src/lib/libbsp/mips/genmongoosev/include/tm27.h +++ /dev/null @@ -1,36 +0,0 @@ -/** - * @file - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#include <bsp/irq.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - rtems_interrupt_handler_install( \ - MONGOOSEV_IRQ_SOFTWARE_1, "benchmark", 0, \ - (rtems_interrupt_handler)handler, NULL ); - -#define Cause_tm27_intr() assertSoftwareInterrupt(0); - -#define Clear_tm27_intr() /* empty */ -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/mips/genmongoosev/start/regs.h b/c/src/lib/libbsp/mips/genmongoosev/start/regs.h deleted file mode 100644 index e63544f738..0000000000 --- a/c/src/lib/libbsp/mips/genmongoosev/start/regs.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * regs.S -- standard MIPS register names from - * newlib-1.8.2/libgloss/mips and adapted. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/* Standard MIPS register names: */ -#define zero $0 -#define z0 $0 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 /* kernel private register 0 */ -#define k1 $27 /* kernel private register 1 */ -#define gp $28 /* global data pointer */ -#define sp $29 /* stack-pointer */ -#define fp $30 /* frame-pointer */ -#define ra $31 /* return address */ -#define pc $pc /* pc, used on mips16 */ - -#define fp0 $f0 -#define fp1 $f1 - -#define WATCHDOG 0xBE000000 - -/* Useful memory constants: */ -#define K0BASE 0x80000000 -#ifndef __mips64 - #define K1BASE 0xA0000000 -#else -#define K1BASE 0xFFFFFFFFA0000000LL -#endif - -#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) - -/* Standard Co-Processor 0 register numbers: */ -#define C0_DCIC $7 /* debug & cache invalidate control */ -#define C0_COUNT $9 /* Count Register */ -#define C0_SR $12 /* Status Register */ -#define C0_CAUSE $13 /* last exception description */ -#define C0_EPC $14 /* Exception error address */ -#define C0_CONFIG $16 /* CPU configuration */ - -/* Standard Status Register bitmasks: */ -#define SR_CU0 0x10000000 -#define SR_CU1 0x20000000 /* Mark CP1 as usable */ -#define SR_FR 0x04000000 /* Enable MIPS III FP registers */ -#define SR_BEV 0x00400000 /* Controls location of exception vectors */ -#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */ - -/* defined differently for Mongoose5- we don't use these anymore */ -#if UNUSED -#define SR_KX 0x00000080 /* Kernel extended addressing enabled */ -#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */ -#define SR_UX 0x00000020 /* User extended addressing enabled */ -#endif - -/* R3000 */ -#define SR_ISC 0x00010000 /* Isolate data cache */ - -/* Standard (R4000) cache operations. Taken from "MIPS R4000 - Microprocessor User's Manual" 2nd edition: */ - -#define CACHE_I (0) /* primary instruction */ -#define CACHE_D (1) /* primary data */ -#define CACHE_SI (2) /* secondary instruction */ -#define CACHE_SD (3) /* secondary data (or combined instruction/data) */ - -#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */ -#define INDEX_LOAD_TAG (1) -#define INDEX_STORE_TAG (2) -#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */ -#define HIT_INVALIDATE (4) -#define CACHE_FILL (5) /* CACHE_I only */ -#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */ -#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */ -#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */ - -#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) - -/* Individual cache operations: */ -#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) -#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) -#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) -#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) - -#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) -#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) -#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) -#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) - -#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) -#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) -#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) -#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) - -#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) -#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) - -#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) -#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) -#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) -#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) - -#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) -#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) -#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) - -#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) -#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) -#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) - -#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) -#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) - -/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/mips/hurricane/include/bsp.h b/c/src/lib/libbsp/mips/hurricane/include/bsp.h deleted file mode 100644 index 42469057f5..0000000000 --- a/c/src/lib/libbsp/mips/hurricane/include/bsp.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * @file - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_HURRICANE_BSP_H -#define LIBBSP_MIPS_HURRICANE_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/rm5231.h> - -#ifdef __cplusplus -extern "C" { -#endif - -extern void WriteDisplay( char * string ); - -extern uint32_t mips_get_timer( void ); - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#define CPU_CLOCK_RATE_MHZ (200) -#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - * - * NOTE: This macro generates a warning like "integer constant out - * of range" which is safe to ignore. In 64 bit mode, unsigned32 - * types are actually 64 bits long so that comparisons between - * unsigned32 types and pointers are valid. The warning is caused - * by code in the delay macro that is necessary for 64 bit mode. - */ - -#define rtems_bsp_delay( microseconds ) \ - { \ - uint32_t _end_clock = \ - mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \ - _end_clock %= 0x100000000; /* make sure result is 32 bits */ \ - \ - /* handle timer overflow, if necessary */ \ - while ( _end_clock < mips_get_timer() ); \ - \ - while ( _end_clock > mips_get_timer() ); \ - } - -/* Constants */ - -#define RAM_START 0 -#define RAM_END 0x100000 - -/* - * Prototypes for methods called from .S for dependency tracking - */ -void init_tlb(void); -void resettlb(int i); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif /* __HURRICANE_BSP_h */ diff --git a/c/src/lib/libbsp/mips/hurricane/include/irq.h b/c/src/lib/libbsp/mips/hurricane/include/irq.h deleted file mode 100644 index 3347ecb2a6..0000000000 --- a/c/src/lib/libbsp/mips/hurricane/include/irq.h +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief interrupt definitions. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_XXX_IRQ_H -#define LIBBSP_MIPS_XXX_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define RM5231_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE+8) -#define BSP_INTERRUPT_VECTOR_MAX RM5231_MAXIMUM_VECTORS - -/** @} */ - -#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h deleted file mode 100644 index e1771b639b..0000000000 --- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h +++ /dev/null @@ -1,40 +0,0 @@ -/** - * @file - * - * This include file contains some definitions specific to the - * JMR3904 simulator in gdb. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_JMR3904_BSP_H -#define LIBBSP_MIPS_JMR3904_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/tx3904.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/mips/jmr3904/include/irq.h b/c/src/lib/libbsp/mips/jmr3904/include/irq.h deleted file mode 100644 index cdb50e244e..0000000000 --- a/c/src/lib/libbsp/mips/jmr3904/include/irq.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief jmr3904 interrupt definitions. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_JMR3904_IRQ_H -#define LIBBSP_MIPS_JMR3904_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -/* - * Interrupt Vector Numbers - * - * NOTE: Numbers 0-15 directly map to levels on the IRC. - * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. - */ - - #define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0 - #define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1 - #define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2 - #define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3 - #define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4 - #define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5 - #define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6 - #define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7 - #define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8 - #define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9 - #define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10 - #define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11 - #define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12 - #define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13 - #define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14 - #define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15 - #define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16 - #define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17 - #define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18 - #define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19 - -#define BSP_INTERRUPT_VECTOR_MAX TX3904_MAXIMUM_VECTORS - -/** @} */ - -#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/jmr3904/include/tm27.h b/c/src/lib/libbsp/mips/jmr3904/include/tm27.h deleted file mode 100644 index f73ccdea40..0000000000 --- a/c/src/lib/libbsp/mips/jmr3904/include/tm27.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#include <bsp/irq.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - rtems_interrupt_handler_install( \ - TX3904_IRQ_TMR0, "benchmark", 0, \ - (rtems_interrupt_handler)handler, NULL ); - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 20; \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \ - *((volatile uint32_t*) 0xFFFFC01C) = 0x00000700; \ - } while(0) - -#define Clear_tm27_intr() \ - do { \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x0001 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ - } while(0) - -#define Lower_tm27_intr() \ - mips_enable_in_interrupt_mask( 0xff01 ); - -#endif diff --git a/c/src/lib/libbsp/mips/malta/include/bsp.h b/c/src/lib/libbsp/mips/malta/include/bsp.h deleted file mode 100644 index 28063b824a..0000000000 --- a/c/src/lib/libbsp/mips/malta/include/bsp.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file - * - * This include file contains some definitions specific to the - * MIPS Malta Board. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_MALTA_BSP_H -#define LIBBSP_MIPS_MALTA_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#define REVISION_REGISTER_ADDRESS 0x1fc00010 -#define PRORV_MASK 0x0000000f /* 4 bit Product Revision */ -#define PROID_MASK 0x000000f0 /* 4 bit Product ID */ -#define CORRV_MASK 0x00000300 /* 2 bit Core Board Revision */ -#define CORID_MASK 0x0000fc00 /* 6 bit Core Board ID */ -#define FPGRV_MASK 0x00ff0000 /* 8 bit CBUS FPGA Revision */ -#define BSP_8259_BASE_ADDRESS (0x18000000UL | 0xa0000000UL) -#define BSP_PCI_BASE_ADDRESS (0x1be00000UL | 0xa0000000UL) -#define BSP_NIC_IO_BASE (0x10000000UL | 0xa0000000UL) -#define PCI0_IO_BASE (0x18000000UL | 0xa0000000UL) -#define BSP_NIC_MEM_BASE (0x00000000UL | 0xa0000000UL) - -/* functions */ -#define WRITE_PROTECTED_UINT8( _addr, _value ) \ - do { \ - volatile uint8_t *_ptr = _addr | 0x80000000; \ - *_ptr = _value; \ - } -#define WRITE_PROTECTED_UINT16( _addr, _value ) \ - do { \ - volatile uint16_t *_ptr = _addr | 0x80000000; \ - *_ptr = _value; \ - } -#define WRITE_PROTECTED_UINT32( _addr, _value ) \ - do { \ - volatile uint32_t *_ptr = _addr | 0x80000000; \ - *_ptr = _value; \ - } -#define READ_PROTECTED_UINT8( _addr, _value ) \ - do { \ - volatile uint8_t *_ptr = _addr | 0x80000000; \ - _value = *_ptr; \ - } -#define READ_PROTECTED_UINT16( _addr, _value ) \ - do { \ - volatile uint16_t *_ptr = _addr | 0x80000000; \ - _value = *_ptr; \ - } -#define READ_PROTECTED_UINT32( _addr, _value ) \ - do { \ - volatile uint32_t *_ptr = _addr | 0x80000000; \ - _value = *_ptr; \ - } - -#define READ_UINT8( _register_, _value_ ) \ - ((_value_) = *((volatile unsigned char *)(_register_))) - -#define WRITE_UINT8( _register_, _value_ ) \ - (*((volatile unsigned char *)(_register_)) = (_value_)) - -#define READ_UINT16( _register_, _value_ ) \ - ((_value_) = *((volatile unsigned short *)(_register_))) - -#define WRITE_UINT16( _register_, _value_ ) \ - (*((volatile unsigned short *)(_register_)) = (_value_)) - -void simple_out_32(uint32_t base, uint32_t addr, uint32_t val); -void simple_out_le32(uint32_t base, uint32_t addr, uint32_t val); -uint8_t simple_in_8( uint32_t base, uint32_t addr ); -void simple_out_8( uint32_t base, uint32_t addr, uint8_t val ); -int16_t simple_in_le16( uint32_t base, uint32_t addr ); -int16_t simple_in_16( uint32_t base, uint32_t addr ); -uint32_t simple_in_le32( uint32_t base, uint32_t addr ); -uint32_t simple_in_32( uint32_t base, uint32_t addr ); -void simple_out_le16( uint32_t base, uint32_t addr, uint16_t val ); -void simple_out_16( uint32_t base, uint32_t addr, uint16_t val ); - -/* - * Prototypes for methods called from .S for dependency tracking - */ -void init_tlb(void); -void resettlb(int i); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/mips/malta/include/irq.h b/c/src/lib/libbsp/mips/malta/include/irq.h deleted file mode 100644 index 3ca6f964a9..0000000000 --- a/c/src/lib/libbsp/mips/malta/include/irq.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief Malta Interrupt Definitions - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_MALTA_IRQ_H -#define LIBBSP_MIPS_MALTA_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -/* - * Interrupt Vector Numbers - * - * NOTE: Numbers 0-15 directly map to levels on the IRC. - * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. - */ -#define MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0 -#define MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0 -#define MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1 -#define MALTA_CPU_INT0 MALTA_CPU_INT_START+2 -#define MALTA_CPU_INT1 MALTA_CPU_INT_START+3 -#define MALTA_CPU_INT2 MALTA_CPU_INT_START+4 -#define MALTA_CPU_INT3 MALTA_CPU_INT_START+5 -#define MALTA_CPU_INT4 MALTA_CPU_INT_START+6 -#define MALTA_CPU_INT5 MALTA_CPU_INT_START+7 -#define MALTA_CPU_INT_LAST MALTA_CPU_INT5 - -#define MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1 -#define MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0 -#define MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1 -#define MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2 -#define MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3 -#define MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4 -#define MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5 -#define MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6 -#define MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7 -#define MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8 -#define MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9 -#define MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10 -#define MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11 -#define MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12 -#define MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13 -#define MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14 -#define MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15 -#define MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15 - -#define MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1 -#define MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0 -#define MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1 -#define MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2 -#define MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3 -#define MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4 -#define MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5 -#define MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6 -#define MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7 -#define MALTA_PCI_ADP_LAST MALTA_PCI_ADP31 -# - -#define BSP_INTERRUPT_VECTOR_MAX MALTA_PCI_ADP_LAST - -/* - * Redefine interrupts with more descriptive names. - * The Generic ones above match the hardware name, - * where these match the device name. - */ -#define MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0 -#define MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1 -#define MALTA_INT_TTY2 MALTA_CPU_INT2 -#define MALTA_INT_COREHI MALTA_CPU_INT3 -#define MALTA_INT_CORELO MALTA_CPU_INT4 -#define MALTA_INT_TICKER MALTA_CPU_INT5 - -#define MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0 -#define MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1 -#define MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2 -#define MALTA_IRQ_TTY1 MALTA_SB_IRQ_3 -#define MALTA_IRQ_TTY0 MALTA_SB_IRQ_4 -#define MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5 -#define MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6 -#define MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7 -#define MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8 -#define MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9 -/* PCI A, PCI B (including Ethernet) PCI slot 1..4, Ethernet */ -#define MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10 -/* PCI slot 1..4 (audio, USB) */ -#define MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11 -#define MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12 -#define MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13 -#define MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14 -#define MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15 -#define MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20 -#define MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B -#define MALTA_IRQ_AUDIO MALTA_PCI_ADP22 -#define MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27 -#define MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28 -#define MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29 -#define MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30 -#define MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31 - -#ifndef ASM - -#endif /* ASM */ - -/** @} */ - -#endif /* LIBBSP_MIPS_MALTA_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/malta/include/pci.h b/c/src/lib/libbsp/mips/malta/include/pci.h deleted file mode 100644 index ad69e3a592..0000000000 --- a/c/src/lib/libbsp/mips/malta/include/pci.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * @file - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * - * PCI defines and function prototypes - * Copyright 1994, Drew Eckhardt - * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> - * - * For more information, please consult the following manuals (look at - * http://www.pcisig.com/ for how to get them): - * - * PCI BIOS Specification - * PCI Local Bus Specification - * PCI to PCI Bridge Specification - * PCI System Design Guide - */ - -#ifndef BSP_PCI_H -#define BSP_PCI_H - -#include <rtems/pci.h> -#include <bsp.h> -#include <stdio.h> - -struct _pin_routes -{ - int pin, int_name[4]; -}; -struct _int_map -{ - int bus, slot, opts; - struct _pin_routes pin_route[5]; -}; -struct pcibridge -{ - int bus; - int slot; -}; - -/* If there's a conflict between a name in the routing table and - * what's already set on the device, reprogram the device setting - * to reflect int_name[0] for the routing table entry - */ -#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) - -void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); - -/* FIXME: This probably belongs into rtems/pci.h */ -extern unsigned char pci_bus_count(); - -/* FIXME: This also is generic and could go into rtems/pci.h */ - -/* Scan pci config space and run a user callback on each - * device present; the user callback may return 0 to - * continue the scan or a value > 0 to abort the scan. - * Return values < 0 are reserved and must not be used. - * - * RETURNS: a (opaque) handle pointing to the bus/slot/fn-triple - * just after where the scan was aborted by a callback - * returning 1 (see above) or NULL if all devices were - * scanned. - * The handle may be passed to this routine to resume the - * scan continuing with the device after the one causing the - * abort. - * Pass a NULL 'handle' argument to start scanning from - * the beginning (bus/slot/fn = 0/0/0). - */ -typedef void *BSP_PciScanHandle; -typedef int (*BSP_PciScannerCb)(int bus, int slot, int fun, void *uarg); - - -BSP_PciScanHandle -BSP_pciScan(BSP_PciScanHandle handle, BSP_PciScannerCb cb, void *uarg); - -/* Dump basic config. space info to a file. The argument may - * be NULL in which case 'stdout' is used. - * NOTE: the C-library must be functional before you can use - * this routine. - */ -void BSP_pciConfigDump(FILE *fp); - -int indirect_pci_read_config_byte( - unsigned char bus, - unsigned char slot, - unsigned char function, - unsigned char offset, - uint8_t *val -); - -int indirect_pci_read_config_word( - unsigned char bus, - unsigned char slot, - unsigned char function, - unsigned char offset, - uint16_t *val -); - -int indirect_pci_read_config_dword( - unsigned char bus, - unsigned char slot, - unsigned char function, - unsigned char offset, - uint32_t *val -); - -int indirect_pci_write_config_byte( - unsigned char bus, - unsigned char slot, - unsigned char function, - unsigned char offset, - uint8_t val -); - -int indirect_pci_write_config_word( - unsigned char bus, - unsigned char slot, - unsigned char function, - unsigned char offset, - uint16_t val -); - -int indirect_pci_write_config_dword( - unsigned char bus, - unsigned char slot, - unsigned char function, - unsigned char offset, - uint32_t val -); - -/* Can these be moved to the rtems pci.h? */ -int FindPCIbridge( int mybus, struct pcibridge *pb ); -void pci_list_devices( void ); - -const pci_config_access_functions pci_indirect_functions; - -void pci_out_le32( uint32_t base, uint32_t addr, uint32_t val); -void pci_out_32( uint32_t base, uint32_t addr, uint32_t val); -uint8_t pci_in_8 ( uint32_t base, uint32_t addr ); -int16_t pci_in_le16 ( uint32_t base, uint32_t addr ); -uint32_t pci_in_le32 ( uint32_t base, uint32_t addr ); -int16_t pci_in_16 ( uint32_t base, uint32_t addr ); -uint32_t pci_in_32 ( uint32_t base, uint32_t addr ); -void pci_out_8 ( uint32_t base, uint32_t addr, uint8_t val ); -void pci_out_le16( uint32_t base, uint32_t addr, uint16_t val ); -void pci_out_16( uint32_t base, uint32_t addr, uint16_t val ); -void pci_out_32 ( uint32_t base, uint32_t addr, uint32_t val); - -#define out_32(_addr, _val) pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val) -#define out_le32(_addr, _val) pci_out_le32(BSP_PCI_BASE_ADDRESS, _addr, _val) -#define out_32(_addr, _val) pci_out_32(BSP_PCI_BASE_ADDRESS, _addr, _val) -#define in_8(_addr) pci_in_8( BSP_PCI_BASE_ADDRESS, _addr ) -#define in_le16(_addr) pci_in_le16( BSP_PCI_BASE_ADDRESS, _addr ) -#define in_le32(_addr) pci_in_le32( BSP_PCI_BASE_ADDRESS, _addr ) -#define in_16(_addr) pci_in_16( BSP_PCI_BASE_ADDRESS, _addr ) -#define in_32(_addr) pci_in_32( BSP_PCI_BASE_ADDRESS, _addr ) -#define out_8(_addr,_val) pci_out_8( BSP_PCI_BASE_ADDRESS, _addr, _val ) -#define out_le16(_addr,_val) pci_out_le16( BSP_PCI_BASE_ADDRESS, _addr, _val ) -#define out_16(_addr,_val) pci_out_16( BSP_PCI_BASE_ADDRESS, _addr, _val ) - -#endif /* BSP_PCI_H */ diff --git a/c/src/lib/libbsp/mips/rbtx4925/include/bsp.h b/c/src/lib/libbsp/mips/rbtx4925/include/bsp.h deleted file mode 100644 index 8fd766d78a..0000000000 --- a/c/src/lib/libbsp/mips/rbtx4925/include/bsp.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * This include file contains some definitions specific to the RBTX4925. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_RBTX4925_BSP_H -#define LIBBSP_MIPS_RBTX4925_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/tx4925.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -/* - * Prototypes for methods called from .S for dependency tracking - */ -void init_tlb(void); -void resettlb(int i); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/mips/rbtx4925/include/irq.h b/c/src/lib/libbsp/mips/rbtx4925/include/irq.h deleted file mode 100644 index d3987b2d39..0000000000 --- a/c/src/lib/libbsp/mips/rbtx4925/include/irq.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief interrupt definitions. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_TX4925_IRQ_H -#define LIBBSP_MIPS_TX4925_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -/* - * Interrupt Vector Numbers - * - */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0 -#define TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1 -#define TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2 -#define TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3 -#define TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4 -#define TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5 -#define TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6 -#define TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7 -#define TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8 -#define TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9 -#define TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10 -#define TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11 -#define TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12 -#define TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13 -#define TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14 -#define TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15 -#define TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16 -#define TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17 -#define TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18 -#define TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19 -#define TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20 -#define TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21 -#define TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22 -#define TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23 -#define TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24 -#define TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25 -#define TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26 -#define TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 -#define TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28 -#define TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29 -#define TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30 -#define TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31 - -#define TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 -#define TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 -#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 - -#define BSP_INTERRUPT_VECTOR_MAX TX4925_MAXIMUM_VECTORS - -/** @} */ - -#endif /* LIBBSP_MIPS_ TX4925_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/rbtx4938/include/bsp.h b/c/src/lib/libbsp/mips/rbtx4938/include/bsp.h deleted file mode 100644 index a0c5e116ae..0000000000 --- a/c/src/lib/libbsp/mips/rbtx4938/include/bsp.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * This include file contains some definitions specific to the RBTX4938. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_RBTX4938_BSP_H -#define LIBBSP_MIPS_RBTX4938_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/tx4938.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_SHARED_HANDLER_SUPPORT 1 - -/* - * Prototypes for methods called from .S for dependency tracking - */ -void init_tlb(void); -void resettlb(int i); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/mips/rbtx4938/include/irq.h b/c/src/lib/libbsp/mips/rbtx4938/include/irq.h deleted file mode 100644 index bb18dcf86d..0000000000 --- a/c/src/lib/libbsp/mips/rbtx4938/include/irq.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief interrupt definitions. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MIPS_TX4938_IRQ_H -#define LIBBSP_MIPS_TX4938_IRQ_H - -#ifndef ASM - #include <rtems.h> - #include <rtems/irq.h> - #include <rtems/irq-extension.h> - #include <rtems/score/mips.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -/* - * Interrupt Vector Numbers - * - */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0 -#define TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1 -#define TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2 -#define TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3 -#define TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4 -#define TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5 -#define TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6 -#define TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7 -#define TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8 -#define TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9 -#define TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10 -#define TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11 -#define TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12 -#define TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13 -#define TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14 -#define TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15 -#define TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16 -#define TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17 -#define TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18 -#define TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19 -#define TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20 -#define TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21 -#define TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22 -#define TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23 -#define TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24 -#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25 -#define TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26 -#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 -#define TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28 -#define TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29 -#define TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30 -#define TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31 - -#define TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 -#define TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 -#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 - -#define BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS - -/** @} */ - -#endif /* LIBBSP_MIPS_JMR3904_IRQ_H */ diff --git a/c/src/lib/libbsp/mips/shared/liblnk/regs.h b/c/src/lib/libbsp/mips/shared/liblnk/regs.h deleted file mode 100644 index 5cc9fac745..0000000000 --- a/c/src/lib/libbsp/mips/shared/liblnk/regs.h +++ /dev/null @@ -1,187 +0,0 @@ -/** - * @file - * @ingroup mips_regs - * @brief Standard MIPS register names. - */ - -/* - * regs.S -- standard MIPS register names. - * - * Copyright (c) 1995 Cygnus Support - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ - -/** - * @defgroup mips_regs MIPS Registers - * @ingroup mips_shared - * @brief MIPS Registers - * @{ - */ - -/** - * @name Standard MIPS register names: - * @{ - */ - -#define zero $0 -#define z0 $0 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 ///< @brief kernel private register 0 */ -#define k1 $27 ///< @brief kernel private register 1 */ -#define gp $28 ///< @brief global data pointer */ -#define sp $29 ///< @brief stack-pointer */ -#define fp $30 ///< @brief frame-pointer */ -#define ra $31 ///< @brief return address */ -#define pc $pc ///< @brief pc, used on mips16 */ - -#define fp0 $f0 -#define fp1 $f1 - -/** @} */ - -/** - * @name Useful memory constants: - * @{ - */ - -#define K0BASE 0x80000000 -#ifndef __mips64 -#define K1BASE 0xA0000000 -#else -#define K1BASE 0xFFFFFFFFA0000000LL -#endif - -/** @} */ - -#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE) - -/** - * @name Standard Co-Processor 0 register numbers: - * @{ - */ - -#define C0_COUNT $9 ///< @brief Count Register */ -#define C0_SR $12 ///< @brief Status Register */ -#define C0_CAUSE $13 ///< @brief last exception description */ -#define C0_EPC $14 ///< @brief Exception error address */ -#define C0_CONFIG $16 ///< @brief CPU configuration */ - -/** @} */ - -/** - * @name Standard Status Register bitmasks: - * @{ - */ - -#define SR_CU1 0x20000000 ///< @brief Mark CP1 as usable */ -#define SR_FR 0x04000000 ///< @brief Enable MIPS III FP registers */ -#define SR_BEV 0x00400000 ///< @brief Controls location of exception vectors */ -#define SR_PE 0x00100000 ///< @brief Mark soft reset (clear parity error) */ - -#define SR_KX 0x00000080 ///< @brief Kernel extended addressing enabled */ -#define SR_SX 0x00000040 ///< @brief Supervisor extended addressing enabled */ -#define SR_UX 0x00000020 ///< @brief User extended addressing enabled */ - -/** @} */ - -/** - * @name Standard (R4000) cache operations. - * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition: - * @{ - */ - -#define CACHE_I (0) ///< @brief primary instruction */ -#define CACHE_D (1) ///< @brief primary data */ -#define CACHE_SI (2) ///< @brief secondary instruction */ -#define CACHE_SD (3) ///< @brief secondary data (or combined instruction/data) */ - -#define INDEX_INVALIDATE (0) ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */ -#define INDEX_LOAD_TAG (1) -#define INDEX_STORE_TAG (2) -#define CREATE_DIRTY_EXCLUSIVE (3) ///< @brief CACHE_D and CACHE_SD only */ -#define HIT_INVALIDATE (4) -#define CACHE_FILL (5) ///< @brief CACHE_I only */ -#define HIT_WRITEBACK_INVALIDATE (5) ///< @brief CACHE_D and CACHE_SD only */ -#define HIT_WRITEBACK (6) ///< @brief CACHE_I, CACHE_D and CACHE_SD only */ -#define HIT_SET_VIRTUAL (7) ///< @brief CACHE_SI and CACHE_SD only */ - -#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c)) - -/** @} */ - -/** - * @name Individual cache operations: - * @{ - */ - -#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) -#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) -#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) -#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) - -#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) -#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) -#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) -#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) - -#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) -#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) -#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) -#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) - -#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) -#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) - -#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) -#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) -#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) -#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) - -#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) -#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) -#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) - -#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) -#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) -#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) - -#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) -#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) - -/** @} */ - -/** @} */ - -/*> EOF regs.S <*/ diff --git a/c/src/lib/libbsp/moxie/moxiesim/include/bsp.h b/c/src/lib/libbsp/moxie/moxiesim/include/bsp.h deleted file mode 100644 index 7ccc0725b4..0000000000 --- a/c/src/lib/libbsp/moxie/moxiesim/include/bsp.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This include file contains some definitions specific to the - * moxie simulator in gdb. - */ - -/* - * COPYRIGHT (c) 1989-1999, 2010, 2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_MOXIE_MOXIESIM_BSP_H -#define LIBBSP_MOXIE_MOXIESIM_BSP_H - -#include <bspopts.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/nios2/nios2_iss/include/bsp.h b/c/src/lib/libbsp/nios2/nios2_iss/include/bsp.h deleted file mode 100644 index cfc591a9c8..0000000000 --- a/c/src/lib/libbsp/nios2/nios2_iss/include/bsp.h +++ /dev/null @@ -1,132 +0,0 @@ -/* bsp.h - * - * This include file contains all board IO definitions. - * - * XXX : put yours in here - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_NIOS2_NIOS2_ISS_BSP_H -#define LIBBSP_NIOS2_NIOS2_ISS_BSP_H - -#include <stdint.h> -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* ============================================ */ - -/* SOPC-specific Constants */ - -#define SYSTEM_BUS_WIDTH 32 - -#define JTAG_UART_BASE 0x08000000 -#define JTAG_UART_IRQ 2 - -#define CLOCK_BASE 0x08001000 -#define CLOCK_FREQ 50000000 -#define CLOCK_VECTOR 1 - -#define TIMER_BASE 0x08002000 -#define TIMER_FREQ 50000000 -#define TIMER_VECTOR 3 - -/* ============================================ */ - -#define NIOS2_BYPASS_CACHE ((uint32_t)0x80000000ul) -#define NIOS2_IO_BASE(x) ( (void*) ((uint32_t)x | NIOS2_BYPASS_CACHE ) ) -#define NIOS2_IENABLE(x) do{ __builtin_wrctl(3,__builtin_rdctl(3)|x);}while(0) -#define NIOS2_IRQ_ENABLE(x) do {__builtin_wrctl(3,__builtin_rdctl(3)|x);} while(0) - -/* ============================================ */ -/* TODO: Put this in an external header file */ - -#ifndef SYSTEM_BUS_WIDTH -#error SYSTEM_BUS_WIDTH is undefined -#endif - -#if SYSTEM_BUS_WIDTH != 32 -#error Only SYSTEM_BUS_WIDTH 32 is supported -#endif - -typedef struct -{ - volatile uint32_t status; - volatile uint32_t control; - volatile uint32_t period_lo; - volatile uint32_t period_hi; - volatile uint32_t snap_lo; - volatile uint32_t snap_hi; -} -altera_avalon_timer_regs; - -#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1) -#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0) -#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2) -#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1) - -#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1) -#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0) -#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2) -#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1) -#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4) -#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2) -#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8) -#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3) - -typedef struct -{ - volatile uint32_t data; - volatile uint32_t control; -} -altera_avalon_jtag_uart_regs; - -#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FFu) -#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) -#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000u) -#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) -#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000u) -#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) - -#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001u) -#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002u) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) -#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100u) -#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200u) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) -#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400u) -#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000u) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) - -/* ============================================ */ - -/* functions */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libbsp/or1k/generic_or1k/include/bsp.h b/c/src/lib/libbsp/or1k/generic_or1k/include/bsp.h deleted file mode 100644 index 72bb107e55..0000000000 --- a/c/src/lib/libbsp/or1k/generic_or1k/include/bsp.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @ingroup generic_or1k - * - * @brief Global BSP definitions. - */ - -/* - * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE - */ - -#ifndef LIBBSP_GENERIC_OR1K_H -#define LIBBSP_GENERIC_OR1K_H - -#include <bspopts.h> -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/generic_or1k.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_GENERIC_OR1K_H */ - -/** - * @defgroup generic_or1k support - * - * @ingroup bsp_or1k - * - * @brief generic_or1k support package - * - */ diff --git a/c/src/lib/libbsp/or1k/generic_or1k/include/irq.h b/c/src/lib/libbsp/or1k/generic_or1k/include/irq.h deleted file mode 100644 index 791aefcae0..0000000000 --- a/c/src/lib/libbsp/or1k/generic_or1k/include/irq.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @ingroup OR1K_IRQ - * - * @brief Interrupt definitions. - */ - -/** - * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE - */ - -#ifndef LIBBSP_GENERIC_OR1K_IRQ_H -#define LIBBSP_GENERIC_OR1K_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#define BSP_INTERRUPT_VECTOR_MIN 0x100 -#define BSP_INTERRUPT_VECTOR_MAX 0x1F00 - -/* Interrupt Identification Register */ -#define OR1K_BSP_UART_REG_INT_ID_MSI (0x00) -#define OR1K_BSP_UART_REG_INT_ID_NO_INT (0x01) -#define OR1K_BSP_UART_REG_INT_ID_THRI (0x02) -#define OR1K_BSP_UART_REG_INT_ID_RDI (0x04) -#define OR1K_BSP_UART_REG_INT_ID_ID (0x06) -#define OR1K_BSP_UART_REG_INT_ID_RLSI (0x06) -#define OR1K_BSP_UART_REG_INT_ID_TOI (0x0c) - -/* Interrupt Enable Register */ -#define OR1K_BSP_UART_REG_INT_ENABLE_RDI (0x01) -#define OR1K_BSP_UART_REG_INT_ENABLE_THRI (0x02) -#define OR1K_BSP_UART_REG_INT_ENABLE_RLSI (0x04) -#define OR1K_BSP_UART_REG_INT_ENABLE_MSI (0x08) - -#endif /* ASM */ -#endif /* LIBBSP_GENERIC_OR1K_IRQ_H */ diff --git a/c/src/lib/libbsp/or1k/generic_or1k/include/uart.h b/c/src/lib/libbsp/or1k/generic_or1k/include/uart.h deleted file mode 100644 index dbf3bbf9ef..0000000000 --- a/c/src/lib/libbsp/or1k/generic_or1k/include/uart.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * @file - * - * @ingroup generic_or1k_uart - * - * @brief UART support. - */ - -/* - * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE - */ - -/** - * @defgroup generic_or1k_uart UART Support - * - * @ingroup generic_or1k - * - * @brief Universal Asynchronous Receiver/Transmitter (UART) Support - */ - -#ifndef LIBBSP_GENERIC_OR1K_UART_H -#define LIBBSP_GENERIC_OR1K_UART_H - -#include <libchip/serial.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define OR1K_UART_DEFAULT_BAUD 115200 -#define OR1K_BSP_UART_IRQ 2 -extern const console_fns generic_or1k_uart_fns; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_GENERIC_OR1K_UART_H */ diff --git a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h b/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h deleted file mode 100644 index f0f8377892..0000000000 --- a/c/src/lib/libbsp/or1k/shared/include/linker-symbols.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H -#define LIBBSP_OR1k_SHARED_LINKER_SYMBOLS_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup or1k_linker Linker Support - * - * @ingroup or1k_shared - * - * @brief Linker support. - * - * @{ - */ - -#ifndef ASM - #define LINKER_SYMBOL(sym) extern char sym []; -#else - #define LINKER_SYMBOL(sym) .extern sym -#endif - -LINKER_SYMBOL(bsp_section_start_begin) -LINKER_SYMBOL(bsp_section_start_end) -LINKER_SYMBOL(bsp_section_start_size) - -LINKER_SYMBOL(bsp_section_vector_begin) -LINKER_SYMBOL(bsp_section_vector_end) -LINKER_SYMBOL(bsp_section_vector_size) - -LINKER_SYMBOL(bsp_section_text_begin) -LINKER_SYMBOL(bsp_section_text_end) -LINKER_SYMBOL(bsp_section_text_size) -LINKER_SYMBOL(bsp_section_text_load_begin) -LINKER_SYMBOL(bsp_section_text_load_end) - -LINKER_SYMBOL(bsp_section_rodata_begin) -LINKER_SYMBOL(bsp_section_rodata_end) -LINKER_SYMBOL(bsp_section_rodata_size) -LINKER_SYMBOL(bsp_section_rodata_load_begin) -LINKER_SYMBOL(bsp_section_rodata_load_end) - -LINKER_SYMBOL(bsp_section_data_begin) -LINKER_SYMBOL(bsp_section_data_end) -LINKER_SYMBOL(bsp_section_data_size) -LINKER_SYMBOL(bsp_section_data_load_begin) -LINKER_SYMBOL(bsp_section_data_load_end) - -LINKER_SYMBOL(bsp_section_bss_begin) -LINKER_SYMBOL(bsp_section_bss_end) -LINKER_SYMBOL(bsp_section_bss_size) - -LINKER_SYMBOL(bsp_section_work_begin) -LINKER_SYMBOL(bsp_section_work_end) -LINKER_SYMBOL(bsp_section_work_size) - -LINKER_SYMBOL(bsp_section_stack_begin) -LINKER_SYMBOL(bsp_section_stack_end) -LINKER_SYMBOL(bsp_section_stack_size) - -LINKER_SYMBOL(bsp_vector_table_begin) -LINKER_SYMBOL(bsp_vector_table_end) -LINKER_SYMBOL(bsp_vector_table_size) - -LINKER_SYMBOL(bsp_start_vector_table_begin) -LINKER_SYMBOL(bsp_start_vector_table_end) -LINKER_SYMBOL(bsp_start_vector_table_size) - -LINKER_SYMBOL(bsp_translation_table_base) -LINKER_SYMBOL(bsp_translation_table_end) - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_OR1K_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/powerpc/beatnik/include/bsp.h b/c/src/lib/libbsp/powerpc/beatnik/include/bsp.h deleted file mode 100644 index 9cc9ae085f..0000000000 --- a/c/src/lib/libbsp/powerpc/beatnik/include/bsp.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * bsp.h -- contain BSP API definition. - */ - -/* - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. - * - * Modified for the 'beatnik' BSP by T. Straumann, 2005-2007. - */ - -#ifndef LIBBSP_BEATNIK_BSP_H -#define LIBBSP_BEATNIK_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <libcpu/io.h> -#include <rtems/clockdrv.h> -#include <bsp/vectors.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Board type */ -typedef enum { - Unknown = 0, - MVME5500, - MVME6100 -} BSP_BoardType; - -BSP_BoardType BSP_getBoardType(void); - -/* Discovery Version */ - -typedef enum { - unknown = 0, - GT_64260_A, /* Revision 0x10 */ - GT_64260_B, /* Revision 0x20 */ - MV_64360, -} DiscoveryVersion; - -/* Determine the type of discovery chip on this board; info - * is cached and repeated calls just return the cached value. - * - * If a non-zero argument is passed, the routine panics - * (BSP_panic) if no recognized bridge is found; - */ -DiscoveryVersion BSP_getDiscoveryVersion(int assertion); - -/* - * confdefs.h overrides for this BSP: - * - Interrupt stack space is not minimum if defined. - */ -#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) - -/* - * base address definitions for several devices - */ -#define BSP_MV64x60_BASE (0xf1000000) -#define BSP_MV64x60_DEV1_BASE (0xf1100000) -#define BSP_UART_IOBASE_COM1 ((BSP_MV64x60_DEV1_BASE)+0x20000) -#define BSP_UART_IOBASE_COM2 ((BSP_MV64x60_DEV1_BASE)+0x21000) -#define BSP_UART_USE_SHARED_IRQS - -#define BSP_NVRAM_BASE_ADDR (0xf1110000) -#define BSP_NVRAM_END_ADDR (0xf1117fff) -#define BSP_NVRAM_RTC_START (0xf1117ff8) - -#define BSP_NVRAM_BOOTPARMS_START (0xf1111000) -#define BSP_NVRAM_BOOTPARMS_END (0xf1111fff) - - -/* This is only active/used during early init. It defines - * the hose0 base for the shared/generic pci code. - * Our own BSP specific pci initialization will then - * override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize) - */ - -#define PCI_CONFIG_ADDR (BSP_MV64x60_BASE + 0xcf8) -#define PCI_CONFIG_DATA (BSP_MV64x60_BASE + 0xcfc) - -/* our wonderful PCI initialization remaps everything to CPU addresses - * - before calling BSP_pci_initialize() this is NOT VALID, however - * and the deprecated inl()/outl() etc won't work! - */ -#define _IO_BASE 0x00000000 -/* wonderful MotLoad has the base address as seen from the - * CPU programmed into config space :-) - */ -#define PCI_MEM_BASE 0 -#define PCI_MEM_BASE_ADJUSTMENT 0 -#define PCI_DRAM_OFFSET 0 - -extern void BSP_motload_pci_fixup(void); - -/* PCI <-> local address mapping - no sophisticated windows - * (i.e., no support for cached regions etc. you read a BAR - * from config space and that's 1:1 where the CPU sees it). - * Our memory is mapped 1:1 to PCI also. - */ -#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a)) -#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a)) - -#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS 32 - -#define BSP_CONSOLE_PORT BSP_UART_COM1 -#define BSP_UART_BAUD_BASE 115200 - -/* I2C Devices */ -/* Note that the i2c addresses stated in the manual are - * left-shifted by one bit. - */ -#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ -#define BSP_USR_I2C_ADDR (0xAA>>1) /* the user EEPROM */ -#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ - -#define BSP_I2C_BUS_DESCRIPTOR gt64260_i2c_bus_descriptor - -#define BSP_I2C_BUS0_NAME "/dev/i2c0" - -#define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" -#define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" -#define BSP_I2C_DS1621_NAME "ds1621" -#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME -#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" - -#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) -#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) -#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) -#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME -#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) - - -/* Initialize the I2C driver and register all devices - * RETURNS 0 on success, -1 on error. - * - * Access to the VPD and user EEPROMS as well - * as the ds1621 temperature sensor is possible - * by means of file nodes - * - * /dev/i2c0.vpd-eeprom (read-only) - * /dev/i2c0.usr-eeprom (read-write) - * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) - * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) - */ -int BSP_i2c_initialize(void); - -/* Networking; */ -#if defined(RTEMS_NETWORKING) -#include <bsp/bsp_bsdnet_attach.h> -#endif - -/* NOT FOR PUBLIC USE BELOW HERE */ -#define BSP_PCI_HOSE0_MEM_BASE 0x80000000 /* must be aligned to size */ -#define BSP_PCI_HOSE0_MEM_SIZE 0x20000000 - -#define BSP_PCI_HOSE1_MEM_BASE 0xe0000000 - -#define BSP_DEV_AND_PCI_IO_BASE 0xf0000000 -#define BSP_DEV_AND_PCI_IO_SIZE 0x10000000 - -/* maintain coherency between CPU and GT64340 Ethernet - * (andpossibly other Discovery components). - */ -#define BSP_RW_PAGE_ATTRIBUTES TRIV121_ATTR_M - -extern unsigned BSP_pci_hose1_bus_base; - -void BSP_pci_initialize(void); - -/* Exception Handling */ - -/* Use a task notepad to attach user exception handler info; - * may be changed by application startup code (EPICS uses 11) - */ -#define BSP_EXCEPTION_NOTEPAD 14 - -#ifndef ASM - -#define outport_byte(port,value) outb(value,port) -#define outport_word(port,value) outw(value,port) -#define outport_long(port,value) outl(value,port) - -#define inport_byte(port,value) (value = inb(port)) -#define inport_word(port,value) (value = inw(port)) -#define inport_long(port,value) (value = inl(port)) -/* - * Vital Board data Start using DATA RESIDUAL - */ -/* - * Total memory using RESIDUAL DATA - */ -extern unsigned int BSP_mem_size; -/* - * Start of the heap - */ -extern unsigned int BSP_heap_start; -/* - * PCI Bus Frequency - */ -extern unsigned int BSP_bus_frequency; -/* - * processor clock frequency - */ -extern unsigned int BSP_processor_frequency; -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; - -extern char BSP_productIdent[20]; -extern char BSP_serialNumber[20]; - -extern char BSP_enetAddr0[7]; -extern char BSP_enetAddr1[7]; - -/* - * The commandline as passed from the bootloader. - */ -extern char *BSP_commandline_string; - - -#define BSP_Convert_decrementer( _value ) \ - ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) - -extern rtems_configuration_table BSP_Configuration; -extern void BSP_panic(char *s); -extern void bsp_reset(void); -extern int BSP_disconnect_clock_handler (void); -extern int BSP_connect_clock_handler (void); - -/* clear hostbridge errors - * - * enableMCP: whether to enable MCP checkstop / machine check interrupts - * on the hostbridge and in HID0. - * - * NOTE: The 5500 and 6100 boards have NO PHYSICAL CONNECTION - * to MCP so 'enableMCP' will always fail! - * - * quiet : be silent - * - * RETURNS : PCI status (hose 0 in byte 0, host 1 in byte 1) and - * VME bridge status (upper 16 bits). - * Zero if no errors were found. - */ -extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); - -/* clear vme bridge errors and return (bridge-dependent) 16-bit status - * - * quiet : be silent - * - * RETURNS : 0 if there were no errors, non-zero, bridge-dependent - * 16-bit error status on error. - * - */ -extern unsigned short (*_BSP_clear_vmebridge_errors)(int); - -/* - * Prototypes for debug helpers - */ -void discovery_pic_set_debug_irq(int on); -void discovery_pic_install_debug_irq(void); - -/* - * Prototypes for methods called only from .S for dependency tracking - */ -char *save_boot_params( - void *r3, - void *r4, - void *r5, - char *cmdline_start, - char *cmdline_end -); -void zero_bss(void); - -/* - * Prototypes for methods in the BSP that cross file boundaries - */ -uint32_t probeMemoryEnd(void); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/beatnik/irq/irq.h b/c/src/lib/libbsp/powerpc/beatnik/irq/irq.h deleted file mode 100644 index e5f9558ecf..0000000000 --- a/c/src/lib/libbsp/powerpc/beatnik/irq/irq.h +++ /dev/null @@ -1,133 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Modified by T. Straumann for the beatnik BSP, 2005-2007 - * Some information may be based on mvme5500/irq/irq.h by K. Feng. - */ - -#ifndef LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H -#define LIBBSP_POWERPC_MOT_PPC_NEW_IRQ_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 -#include <rtems/irq.h> -#include <bsp/vectors.h> - -/* This BSP also passes a pointer to the interrupt frame to the handler. - * The PPC ABI guarantees that this will not mess up handlers written - * without knowledge of this feature. - */ - -typedef void (*BSP_rtems_irq_hdl)(rtems_irq_hdl_param,BSP_Exception_frame*); - - -/* legal priorities are 0 <= priority <= MAX_PRIO; 0 effectively disables the interrupt */ -#define BSP_IRQ_MAX_PRIO 4 -#define BSP_IRQ_MIN_PRIO 1 - -/* Note that priorites are only honoured for 'PCI' interrupt numbers. - * The discovery pic has no support for hardware priorites; hence they - * are handled in software - */ -#define BSP_IRQ_DEFAULT_PRIORITY 2 - - -#define BSP_PCI_IRQ_LOWEST_OFFSET 0 /* IMPLEMENTATION RELIES ON discovery pic INTERRUPTS HAVING NUMBERS 0..95 */ -#define BSP_IRQ_DEV 1 /* device interface interrupt */ -#define BSP_IRQ_DMA 2 /* DMA addres error interrupt (260) */ -#define BSP_IRQ_CPU 3 /* CPU interface interrupt */ -#define BSP_IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt (260) */ -#define BSP_IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt (260) */ -#define BSP_IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt (260) */ -#define BSP_IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt (260) */ -#define BSP_IRQ_TIME0_1 8 /* Timer 0..1 interrupt; Timer 0 on 64360 */ -#define BSP_IRQ_TIME2_3 9 /* Timer 2..3 interrupt; Timer 1 on 64360 */ -#define BSP_IRQ_TIME4_5 10 /* Timer 4..5 interrupt; Timer 2 on 64360 */ -#define BSP_IRQ_TIME6_7 11 /* Timer 6..7 interrupt; Timer 3 on 64360 */ -#define BSP_IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary (PCI 0 interrupt summary on 64360) */ -#define BSP_IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary (SRAM PAR ERROR on 64360) */ -#define BSP_IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ -#define BSP_IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ -#define BSP_IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary (PCI 1 interrupt summary on 64360) */ -#define BSP_IRQ_ECC 17 /* ECC error interrupt */ -#define BSP_IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ -#define BSP_IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ -#define BSP_IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ -#define BSP_IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ -#define BSP_IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ -#define BSP_IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ -#define BSP_IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ -#define BSP_IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ -#define BSP_IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ -#define BSP_IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ -#define BSP_IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ -#define BSP_IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ -#define BSP_IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ -#define BSP_IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ -#define BSP_IRQ_SDMA (32+4) /* SDMA interrupt */ -#define BSP_IRQ_I2C (32+5) /* I2C interrupt */ -#define BSP_IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ -#define BSP_IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ -#define BSP_IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ -#define BSP_IRQ_COMM (32+11) /* Comm unit interrupt */ -#define BSP_IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt summary */ -#define BSP_IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt summary */ -#define BSP_IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt summary */ -#define BSP_IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt summary */ -#define BSP_IRQ_GPP_0 64 - -#define BSP_PCI_IRQ_NUMBER (64+32) -#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) - -#define BSP_PROCESSOR_IRQ_NUMBER 1 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET+1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - -/* summary */ - -#define BSP_IRQ_NUMBER (BSP_PCI_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER) -#define BSP_LOWEST_OFFSET 0 -#define BSP_MAX_OFFSET (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1) -#define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET - -#define BSP_UART_COM1_IRQ BSP_IRQ_GPP_0 -#define BSP_UART_COM2_IRQ BSP_IRQ_GPP_0 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - - -#include <bsp/irq_supp.h> - -int BSP_irq_is_enabled_at_pic(rtems_irq_number irq); - -/* set priority of an interrupt; must not be called from ISR level */ -int BSP_irq_set_priority(rtems_irq_number irq, rtems_irq_prio pri); - -/* Not for public use */ -void BSP_rtems_irq_mng_init(unsigned cpuId); - -#ifdef __cplusplus -} -#endif - - -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/beatnik/marvell/gtpcireg.h b/c/src/lib/libbsp/powerpc/beatnik/marvell/gtpcireg.h deleted file mode 100644 index d01fc702ac..0000000000 --- a/c/src/lib/libbsp/powerpc/beatnik/marvell/gtpcireg.h +++ /dev/null @@ -1,964 +0,0 @@ -/* $NetBSD: gtpcireg.h,v 1.4 2005/12/11 12:22:16 christos Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _DEV_GTPCIREG_H -#define _DEV_GTPCIREG_H - -#define PCI__BIT(bit) (1U << (bit)) -#define PCI__MASK(bit) (PCI__BIT(bit) - 1) -#define PCI__GEN(bus, off, num) (((off)^((bus) << 7))+((num) << 4)) -#define PCI__EXT(data, bit, len) (((data) >> (bit)) & PCI__MASK(len)) -#define PCI__CLR(data, bit, len) ((data) &= ~(PCI__MASK(len) << (bit))) -#define PCI__INS(bit, new) ((new) << (bit)) - -#define PCI_SYNC_REG(bus) (0xc0 | ((bus) << 3)) - -/* - * Table 185: PCI Slave ADDRess Decoding Register Map - */ -#define PCI_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c08, 0) -#define PCI_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0c0c, 0) -#define PCI_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0c10, 0) -#define PCI_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0c14, 0) -#define PCI_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d08, 0) -#define PCI_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0d0c, 0) -#define PCI_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d10, 0) -#define PCI_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0d14, 0) -#define PCI_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0d18, 0) -#define PCI_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0d1c, 0) -#define PCI_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0d20, 0) -#define PCI_P2P_IO_BAR_SIZE(bus) PCI__GEN(bus, 0x0d24, 0) -#define PCI_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0d28, 0) -#define PCI_EXPANSION_ROM_BAR_SIZE(bus) PCI__GEN(bus, 0x0d2c, 0) -#define PCI_DAC_SCS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e00, 0) -#define PCI_DAC_SCS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e04, 0) -#define PCI_DAC_SCS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e08, 0) -#define PCI_DAC_SCS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e0c, 0) -#define PCI_DAC_CS0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e10, 0) -#define PCI_DAC_CS1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e14, 0) -#define PCI_DAC_CS2_BAR_SIZE(bus) PCI__GEN(bus, 0x0e18, 0) -#define PCI_DAC_CS3_BAR_SIZE(bus) PCI__GEN(bus, 0x0e1c, 0) -#define PCI_DAC_BOOTCS_BAR_SIZE(bus) PCI__GEN(bus, 0x0e20, 0) -#define PCI_DAC_P2P_MEM0_BAR_SIZE(bus) PCI__GEN(bus, 0x0e24, 0) -#define PCI_DAC_P2P_MEM1_BAR_SIZE(bus) PCI__GEN(bus, 0x0e28, 0) -#define PCI_DAC_CPU_BAR_SIZE(bus) PCI__GEN(bus, 0x0e2c, 0) -#define PCI_BASE_ADDR_REGISTERS_ENABLE(bus) PCI__GEN(bus, 0x0c3c, 0) -#define PCI_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c48, 0) -#define PCI_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d48, 0) -#define PCI_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c4c, 0) -#define PCI_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d4c, 0) -#define PCI_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c50, 0) -#define PCI_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d50, 0) -#define PCI_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d58, 0) -#define PCI_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0c54, 0) -#define PCI_ADDR_DECODE_CONTROL(bus) PCI__GEN(bus, 0x0d3c, 0) -#define PCI_BOOTCS_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d54, 0) -#define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d5c, 0) -#define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d60, 0) -#define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0d64, 0) -#define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0d68, 0) -#define PCI_P2P_IO_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d6c, 0) -#define PCI_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0d70, 0) -#define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f00, 0) -#define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f04, 0) -#define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f08, 0) -#define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f0c, 0) -#define PCI_DAC_CS0_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f10, 0) -#define PCI_DAC_CS1_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f14, 0) -#define PCI_DAC_CS2_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f18, 0) -#define PCI_DAC_CS3_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f1c, 0) -#define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f20, 0) -#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f24, 0) -#define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f28, 0) -#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus) PCI__GEN(bus, 0x0f2c, 0) -#define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus) PCI__GEN(bus, 0x0f30, 0) -#define PCI_DAC_CPU_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f34, 0) -#define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus) PCI__GEN(bus, 0x0f38, 0) - -/* - * Table 186: PCI Control Register Map - */ -#define PCI_COMMAND(bus) PCI__GEN(bus, 0x0c00, 0) -#define PCI_MODE(bus) PCI__GEN(bus, 0x0d00, 0) -#define PCI_TIMEOUT_RETRY(bus) PCI__GEN(bus, 0x0c04, 0) -#define PCI_READ_BUFFER_DISCARD_TIMER(bus) PCI__GEN(bus, 0x0d04, 0) -#define PCI_MSI_TRIGGER_TIMER(bus) PCI__GEN(bus, 0x0c38, 0) -#define PCI_ARBITER_CONTROL(bus) PCI__GEN(bus, 0x1d00, 0) -#define PCI_INTERFACE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d08, 0) -#define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d0c, 0) -#define PCI_INTERFACE_XBAR_TIMEOUT(bus) PCI__GEN(bus, 0x1d04, 0) -#define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus) PCI__GEN(bus, 0x1d18, 0) -#define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus) PCI__GEN(bus, 0x1d1c, 0) -#define PCI_SYNC_BARRIER(bus) PCI__GEN(bus, 0x1d10, 0) -#define PCI_P2P_CONFIGURATION(bus) PCI__GEN(bus, 0x1d14, 0) -#define PCI_P2P_SWAP_CONTROL(bus) PCI__GEN(bus, 0x1d54, 0) -#define PCI_ACCESS_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1e00, n) -#define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1e04, n) -#define PCI_ACCESS_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1e08, n) - - -/* - * Table 187: PCI Snoop Control Register Map - */ -#define PCI_SNOOP_CONTROL_BASE_LOW(bus, n) PCI__GEN(bus, 0x1f00, n) -#define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n) PCI__GEN(bus, 0x1f04, n) -#define PCI_SNOOP_CONTROL_TOP(bus, n) PCI__GEN(bus, 0x1f08, n) - -/* - * Table 188: PCI Configuration ACCESS_Register Map - */ -#define PCI_CONFIG_ADDR(bus) PCI__GEN(bus, 0x0cf8, 0) -#define PCI_CONFIG_DATA(bus) PCI__GEN(bus, 0x0cfc, 0) -#define PCI_INTR_ACK(bus) PCI__GEN(bus, 0x0c34, 0) - -/* - * Table 189: PCI ERROR Report Register Map - */ -#define PCI_SERR_MASK(bus) PCI__GEN(bus, 0x0c28, 0) -#define PCI_ERROR_ADDRESS_LOW(bus) PCI__GEN(bus, 0x1d40, 0) -#define PCI_ERROR_ADDRESS_HIGH(bus) PCI__GEN(bus, 0x1d44, 0) -#define PCI_ERROR_DATA_LOW(bus) PCI__GEN(bus, 0x1d48, 0) -#define PCI_ERROR_DATA_HIGH(bus) PCI__GEN(bus, 0x1d4c, 0) -#define PCI_ERROR_COMMAND(bus) PCI__GEN(bus, 0x1d50, 0) -#define PCI_ERROR_CAUSE(bus) PCI__GEN(bus, 0x1d58, 0) -#define PCI_ERROR_MASK(bus) PCI__GEN(bus, 0x1d5c, 0) - - - -/* - * Table 223: PCI Base Address Registers Enable - * If a bit is clear, the BAR is enabled. If set, disabled. The GT64260] - * prevents disabling both memory mapped and I/O mapped BARs (bits 9 and 10 - * cannot simultaneously be set to 1). - */ -#define PCI_BARE_SCS0En PCI__BIT(0) /* SCS[0]* BAR Enable */ -#define PCI_BARE_SCS1En PCI__BIT(1) /* SCS[1]* BAR Enable */ -#define PCI_BARE_SCS2En PCI__BIT(2) /* SCS[2]* BAR Enable */ -#define PCI_BARE_SCS3En PCI__BIT(3) /* SCS[3]* BAR Enable */ -#define PCI_BARE_CS0En PCI__BIT(4) /* CS[0]* BAR Enable */ -#define PCI_BARE_CS1En PCI__BIT(5) /* CS[1]* BAR Enable */ -#define PCI_BARE_CS2En PCI__BIT(6) /* CS[2]* BAR Enable */ -#define PCI_BARE_CS3En PCI__BIT(7) /* CS[3]* BAR Enable */ -#define PCI_BARE_BootCSEn PCI__BIT(8) /* BootCS* BAR Enable */ -#define PCI_BARE_IntMemEn PCI__BIT(9) /* Memory Mapped Internal - * Registers BAR Enable */ -#define PCI_BARE_IntIOEn PCI__BIT(10) /* I/O Mapped Internal - * Registers BAR Enable */ -#define PCI_BARE_P2PMem0En PCI__BIT(11) /* P2P Mem0 BAR Enable */ -#define PCI_BARE_P2PMem1En PCI__BIT(12) /* P2P Mem1 BAR Enable */ -#define PCI_BARE_P2PIOEn PCI__BIT(13) /* P2P IO BAR Enable */ -#define PCI_BARE_CPUEn PCI__BIT(14) /* CPU BAR Enable */ -#define PCI_BARE_DSCS0En PCI__BIT(15) /* DAC SCS[0]* BAR Enable */ -#define PCI_BARE_DSCS1En PCI__BIT(16) /* DAC SCS[1]* BAR Enable */ -#define PCI_BARE_DSCS2En PCI__BIT(17) /* DAC SCS[2]* BAR Enable */ -#define PCI_BARE_DSCS3En PCI__BIT(18) /* DAC SCS[3]* BAR Enable */ -#define PCI_BARE_DCS0En PCI__BIT(19) /* DAC CS[0]* BAR Enable */ -#define PCI_BARE_DCS1En PCI__BIT(20) /* DAC CS[1]* BAR Enable */ -#define PCI_BARE_DCS2En PCI__BIT(21) /* DAC CS[2]* BAR Enable */ -#define PCI_BARE_DCS3En PCI__BIT(22) /* DAC CS[3]* BAR Enable */ -#define PCI_BARE_DBootCSEn PCI__BIT(23) /* DAC BootCS* BAR Enable */ -#define PCI_BARE_DP2PMem0En PCI__BIT(24) /* DAC P2P Mem0 BAR Enable */ -#define PCI_BARE_DP2PMem1En PCI__BIT(25) /* DAC P2P Mem1 BAR Enable */ -#define PCI_BARE_DCPUEn PCI__BIT(26) /* DAC CPU BAR Enable */ - -/* - * Table 254: PCI Address Decode Control - * Bits 7:4 and 31:25 are reserved - * 00:00 RemapWrDis Address Remap Registers Write Disable - * 0: Writes to a BAR result in updating the - * corresponding remap register with the BAR's - * new value. - * 1: Writes to a BAR have no affect on the - * corresponding Remap register value. - * 01:01 ExpRomDev Expansion ROM Device (0: CS[3]; 1: BootCS) - * 02:02 VPDDev VPD Device (0: CS[3]; 1: BootCS) - * 03:03 MsgAcc Messaging registers access - * 0: Messaging unit registers are accessible on - * lowest 4Kbyte of SCS[0] BAR space. - * 1: Messaging unit registers are only accessible - * as part of the GT64260 internal space. - * 07:04 Reserved - * 24:08 VPDHighAddr VPD High Address bits - * [31:15] of VPD the address. - * 31:25 Reserved - */ -#define PCI_ADC_RemapWrDis PCI__BIT(0) -#define PCI_ADC_ExpRomDev PCI__BIT(1) -#define PCI_ADC_VPDDev PCI__BIT(2) -#define PCI_ADC_MsgAcc PCI__BIT(3) -#define PCI_ADC_VPDHighAddr_GET(v) PCI__EXT(v, 8, 16) - - -/* - * Table 255: PCI Command - * 00:00 MByteSwap PCI Master Byte Swap - * NOTE: GT-64120 and GT-64130 compatible. - * When set to 0, the GTO64260 PCI master swaps the bytes - * of the incoming and outgoing PCI data (swap the 8 bytes - * of a longword). - * 01:01 Reserved - * 02:02 Reserved Must be 0. - * 03:03 Reserved - * 04:04 MWrCom PCI Master Write Combine Enable - * When set to 1, write combining is enabled. - * 05:05 MRdCom PCI Master Read Combine Enable - * When set to 1, read combining is enabled. - * 06:06 MWrTrig PCI Master Write Trigger - * 0: Accesses the PCI bus only when the whole burst is - * written into the master write buffer. - * 1: Accesses the PCI bus when the first data is written - * into the master write buffer. - * 07:07 MRdTrig PCI Master Read Trigger - * 0: Returns read data to the initiating unit only when - * the whole burst is written into master read buffer. - * 1: Returns read data to the initiating unit when the - * first read data is written into master read buffer. - * 08:08 MRdLine PCI Master Memory Read Line Enable - * (0: Disable; 1: Enable) - * 09:09 MRdMul PCI Master Memory Read Multiple Enable - * (0: Disable; 1: Enable) - * 10:10 MWordSwap PCI Master Word Swap - * NOTE: GT-64120 and GT-64130 compatible. - * When set to 1, the GT64260 PCI master swaps the 32-bit - * words of the incoming and outgoing PCI data. - * 11:11 SWordSwap PCI Slave Word Swap - * NOTE: GT-64120 and GT-64130 compatible. - * When set to 1, the GT64260 PCI slave swaps the 32-bit - * words of the incoming and outgoing PCI data. - * 12:12 IntBusCtl PCI Interface Unit Internal Bus Control - * NOTE: Reserved for Galileo Technology usage - * 0: Enable internal bus sharing between master and - * slave interfaces. - * 1: Disable internal bus sharing between master and - * slave interfaces. - * 13:13 SBDis PCI Slave Sync Barrier Disable - * When set to 1, the PCI configuration read transaction - * will stop act as sync barrier transaction. - * 14:14 Reserved Must be 0 - * 15:15 MReq64 PCI Master REQ64* Enable (0: Disable; 1: Enable) - * 16:16 SByteSwap PCI Slave Byte Swap - * NOTE: GT-64120 and GT-64130 compatible. - * When set to 0, the GT64260 PCI slave swaps the bytes of - * the incoming and outgoing PCI data (swap the 8 bytes of - * a long-word). - * 17:17 MDACEn PCI Master DAC Enable - * 0: Disable (The PCI master never drives the DAC cycle) - * 1: Enable (In case the upper 32-bit address is not 0, - * the PCI master drives the DAC cycle) - * 18:18 M64Allign PCI Master REQ64* assertion on non-aligned - * 0: Disable (The master asserts REQ64* only if - * the address is 64-bit aligned) - * 1: Enable (The master asserts REQ64* even if - * the address is not 64-bit aligned) - * 19:19 PErrProp Parity/ECC Errors Propagation Enable - * 0: Disable (The PCI interface always drives - * correct parity on the PAR signal) - * 1: Enable (In case of slave read bad ECC from - * SDRAM, or master write with bad parity/ECC - * indication from the initiator, the PCI interface - * drives bad parity on the PAR signal) - * 20:20 SSwapEn PCI Slave Swap Enable - * NOTE: Even if the SSwapEn bit is set to 1 and - * the PCI address does not match any of the - * Access Control registers, slave data swapping - * works according to SByteSwap and SWordSwap bits. - * 0: PCI slave data swapping is determined via - * SByteSwap and SWordSwap bits (bits 16 and 11), - * as in the GT-64120/130. - * 1: PCI slave data swapping is determined via PCISwap - * bits [25:24] in the PCI Access Control registers. - * 21:21 MSwapEn PCI Master Swap Enable - * 0: PCI master data swapping is determined via - * MByteSwap and MWordSwap bits (bits 0 and 10), - * as in the GT-64120/130. - * 1: PCI master data swapping is determined via - * PCISwap bits in CPU to PCI Address Decoding - * registers. - * 22:22 MIntSwapEn PCI Master Configuration Transactions Data Swap Enable - * NOTE: Reserved for Galileo Technology usage. - * 0: Disable (The PCI master configuration transaction - * to the PCI bus is always in Little Endian convention) - * 1: Enable (The PCI master configuration transaction to - * the PCI bus is determined according to the setting - * of MSwapEn bit) - * 23:23 LBEn PCI Loop Back Enable - * NOTE: Reserved for Galileo Technology usage. - * 0: Disable (The PCI slave does not respond to - * transactions initiated by the PCI master) - * 1: Enable (The PCI slave does respond to - * transactions initiated by the PCI master, - * if targeted to the slave (address match) - * 26:24 SIntSwap PCI Slave data swap control on PCI accesses to the - * GT64260 internal and configuration registers. - * Bits encoding are the same as bits[26:24] in PCI Access - * Control registers. - * 27:27 Reserved Must be 0. - * 31:28 Reserved Read only. - */ -#define PCI_CMD_MByteSwap PCI__BIT(0) -#define PCI_CMD_MBZ0_2 PCI__BIT(2) -#define PCI_CMD_MWrCom PCI__BIT(4) -#define PCI_CMD_MRdCom PCI__BIT(5) -#define PCI_CMD_MWrTrig PCI__BIT(6) -#define PCI_CMD_MRdTrig PCI__BIT(7) -#define PCI_CMD_MRdLine PCI__BIT(8) -#define PCI_CMD_MRdMul PCI__BIT(9) -#define PCI_CMD_MWordSwap PCI__BIT(10) -#define PCI_CMD_SWordSwap PCI__BIT(11) -#define PCI_CMD_IntBusCtl PCI__BIT(12) -#define PCI_CMD_SBDis PCI__BIT(13) -#define PCI_CMD_MBZ0_14 PCI__BIT(14) -#define PCI_CMD_MReq64 PCI__BIT(15) -#define PCI_CMD_SByteSwap PCI__BIT(16) -#define PCI_CMD_MDCAEn PCI__BIT(17) -#define PCI_CMD_M64Allign PCI__BIT(18) -#define PCI_CMD_PErrProp PCI__BIT(19) -#define PCI_CMD_SSwapEn PCI__BIT(20) -#define PCI_CMD_MSwapEn PCI__BIT(21) -#define PCI_CMD_MIntSwapEn PCI__BIT(22) -#define PCI_CMD_LBEn PCI__BIT(23) -#define PCI_CMD_SIntSwap_GET(v) PCI__EXT(v, 24, 3) -#define PCI_CMD_MBZ0_27 PCI__BIT(27) - - -/* - * Table 256: PCI Mode - * 00:00 PciID PCI Interface ID -- Read Only (PCI_0: 0x0; PCI_1: 0x1) - * 01:01 Reserved - * 02:02 Pci64 64-bit PCI Interface -- Read Only - * When set to 1, the PCI interface is configured to a - * 64 bit interface. - * 07:03 Reserved - * 08:08 ExpRom Expansion ROM Enable -- Read Only from PCI - * When set to 1, the expansion ROM BAR is enabled. - * 09:09 VPD VPD Enable -- Read Only from PCI - * When set to 1, VPD is supported. - * 10:10 MSI MSI Enable -- Read Only from PCI - * When set to 1, MSI is supported. - * 11:11 PMG Power Management Enable -- Read Only from PCI - * When set to 1, PMG is supported. - * 12:12 HotSwap CompactPCI Hot Swap Enable -- Read Only from PCI - * When set to 1, HotSwap is supported. - * 13:13 BIST BIST Enable -- Read only from PCI - * If set to 1, BIST is enabled. - * 30:14 Reserved - * 31:31 PRst PCI Interface Reset Indication -- Read Only - * Set to 0 as long as the RST* pin is asserted. - */ -#define PCI_MODE_PciID_GET(v) PCI__EXT(v, 0, 1) -#define PCI_MODE_Pci64 PCI__BIT(2) -#define PCI_MODE_ExpRom PCI__BIT(8) -#define PCI_MODE_VPD PCI__BIT(9) -#define PCI_MODE_MSI PCI__BIT(10) -#define PCI_MODE_PMG PCI__BIT(11) -#define PCI_MODE_HotSwap PCI__BIT(12) -#define PCI_MODE_BIST PCI__BIT(13) -#define PCI_MODE_PRst PCI__BIT(31) - -/* - * Table 257: PCI Timeout and Retry - * 07:00 Timeout0 Specifies the number of PClk cycles the GT64260 slave - * holds the PCI bus before terminating a transaction - * with RETRY. - * 15:08 Timeout1 Specifies the number of PClk cycles the GT64260 slave - * holds the PCI bus before terminating a transaction - * with DISCONNECT. - * 23:16 RetryCtr Retry Counter - * Specifies the number of retries of the GT64260 Master. - * The GT64260 generates an interrupt when this timer - * expires. A 0x00 value means a retry forever. - * 31:24 Reserved - */ -#define PCI_TMORTRY_Timeout0_GET(v) PCI__EXT(v, 0, 8) -#define PCI_TMORTRY_Timeout1_GET(v) PCI__EXT(v, 8, 8) -#define PCI_TMORTRY_RetryCtr_GET(v) PCI__EXT(v, 16, 8) - - -/* - * Table 258: PCI Read Buffer Discard Timer - * 15:00 Timer Specifies the number of PClk cycles the GT64260 - * slave keeps an non-accessed read buffers (non com- - * pleted delayed read) before invalidating the buffer. - * 23:16 RdBufEn Slave Read Buffers Enable - * Each bit corresponds to one of the eight read buffers. - * If set to 1, buffer is enabled. - * 31:24 Reserved - */ -#define PCI_RdBufDisTmr_Timer_GET(v) PCI__EXT(v, 0, 16) -#define PCI_RdBufDisTmr_RdBufEn_GET(v) PCI__EXT(v, 16, 8) -#define PCI_RdBufDisTmr_RdBufEn0(v) PCI__BIT(16) -#define PCI_RdBufDisTmr_RdBufEn1(v) PCI__BIT(17) -#define PCI_RdBufDisTmr_RdBufEn2(v) PCI__BIT(18) -#define PCI_RdBufDisTmr_RdBufEn3(v) PCI__BIT(19) -#define PCI_RdBufDisTmr_RdBufEn4(v) PCI__BIT(20) -#define PCI_RdBufDisTmr_RdBufEn5(v) PCI__BIT(21) -#define PCI_RdBufDisTmr_RdBufEn6(v) PCI__BIT(22) -#define PCI_RdBufDisTmr_RdBufEn7(v) PCI__BIT(23) - -/* - * Table 259: MSI Trigger Timer - * 15:00 Timer Specifies the number of TClk cycles between consecutive - * MSI requests. - * 31:16 Reserved - */ -#define PCI_MSITrigger_Timer_GET(v) PCI__EXT(v, 0, 16) - -/* - * Table 260: PCI Arbiter Control - * NOTE: If HPPV (bits [28:21]) is set to 0 and PAEn is set to 1, - * priority scheme is reversed. This means that high priority - * requests are granted if no low priority request is pending. - * 00:00 Reserved Must be 0. 0x0 - * 01:01 BDEn Broken Detection Enable - * If set to 1, broken master detection is enabled. A mas- - * ter is said to be broken if it fails to respond to grant - * assertion within a window specified in BV (bits [6:3]). - * 02:02 PAEn Priority Arbitration Enable - * 0: Low priority requests are granted only when no high - * priority request is pending - * 1: Weighted round robin arbitration is performed - * between high priority and low priority groups. - * 06:03 BV Broken Value - * This value sets the maximum number of cycles that the - * arbiter waits for a PCI master to respond to its grant - * assertion. If a PCI master fails to assert FRAME* within - * this time, the PCI arbiter aborts the transaction and - * performs a new arbitration cycle and a maskable - * interrupt is generated. Must be greater than 0. - * NOTE: The PCI arbiter waits for the current - * transaction to end before starting to - * count the wait-for-broken cycles. - * Must be greater than 1 for masters that performs address - * stepping (such as the GTO 64260 PCI master), since they - * require GNT* assertion for two cycles. - * 13:07 P[6:0] Priority - * These bits assign priority levels to the requests - * connected to the PCI arbiter. When a PM bit is set to - * 1, priority of the associated request is high. The - * mapping between P[6:0] bits and the request/grant pairs - * are as follows: - * P[0]: internal PCI master P[1]: external REQ0/GNT0 - * P[2]: external REQ1/GNT1 P[3]: external REQ2/GNT2 - * P[4]: external REQ3/GNT3 P[5]: external REQ4/GNT4 - * P[6]: external REQ5/GNT5 - * 20:14 PD[6:0] Parking Disable - * Use these bits to disable parking on any of the PCI - * masters. When a PD bit is set to 1, parking on the - * associated PCI master is disabled. - * NOTE: The arbiter parks on the last master granted - * unless disabled through the PD bit. Also, if - * PD bits are all 1, the PCI arbiter parks on - * the internal PCI master. - * 28:21 HPPV High Priority Preset Value - * This is the preset value of the high priority counter - * (High_cnt). This counter decrements each time a high - * priority request is granted. When the counter reaches - * zero, it reloads with this preset value. The counter - * reloads when a low priority request is granted. - * 30:29 Reserved - * 31:31 EN Enable - * Setting this bit to 1 enables operation of the arbiter. - */ -#define PCI_ARBCTL_MBZ0_0 PCI__BIT(0) -#define PCI_ARBCTL_BDEn PCI__BIT(1) -#define PCI_ARBCTL_PAEn PCI__BIT(2) -#define PCI_ARBCTL_BV_GET(v) PCI__EXT(v, 3, 4) -#define PCI_ARBCTL_P_GET(v) PCI__EXT(v, 7, 7) -#define PCI_ARBCTL_PD_GET(v) PCI__EXT(v, 14, 7) -#define PCI_ARBCTL_HPPV_GET(v) PCI__EXT(v, 21, 7) -#define PCI_ARBCTL_EN PCI__BIT(31) - -#define PCI_ARBPRI_IntPci PCI__BIT(0) -#define PCI_ARBPRI_ExtReqGnt0 PCI__BIT(1) -#define PCI_ARBPRI_ExtReqGnt1 PCI__BIT(2) -#define PCI_ARBPRI_EXtReqGnt2 PCI__BIT(3) -#define PCI_ARBPRI_EXtReqGnt3 PCI__BIT(4) -#define PCI_ARBPRI_EXtReqGnt4 PCI__BIT(5) -#define PCI_ARBPRI_EXtReqGnt5 PCI__BIT(6) - -/* - * Table 261: PCI Interface Crossbar Control (Low) - * 03:00 Arb0 Slice 0 of PCI master pizza arbiter. - * 07:04 Arb1 Slice 1 of PCI master pizza arbiter. - * 11:08 Arb2 Slice 2 of PCI master pizza arbiter. - * 15:12 Arb3 Slice 3 of PCI master pizza arbiter. - * 19:16 Arb4 Slice 4 of PCI master pizza arbiter. - * 23:20 Arb5 Slice 5 of PCI master pizza arbiter. - * 27:24 Arb6 Slice 6 of PCI master pizza arbiter. - * 31:28 Arb7 Slice 7 of PCI master pizza arbiter. - */ -#define PCI_IFXBRCTL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4) -#define PCI_IFXBRCTL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\ - (v) |= PCI__INS((n)*4, s))) - -/* - * Table 262: PCI Interface Crossbar Control (High) - * 03:00 Arb8 Slice 8 of PCI master pizza arbiter. - * 07:04 Arb9 Slice 9 of PCI master pizza arbiter. - * 11:08 Arb10 Slice 10 of PCI master pizza arbiter. - * 15:12 Arb11 Slice 11 of PCI master pizza arbiter. - * 19:16 Arb12 Slice 12 of PCI master pizza arbiter. - * 23:20 Arb13 Slice 13 of PCI master pizza arbiter. - * 27:24 Arb14 Slice 14 of PCI master pizza arbiter. - * 31:28 Arb15 Slice 15 of PCI master pizza arbiter. - */ -#define PCI_IFXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4) -#define PCI_IFXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\ - (v) |= PCI__INS(((n)-8)*4, s))) - -/* - * Table 263: PCI Interface Crossbar Timeout - (NOTE: Reserved for Galileo Technology usage.) - * 07:00 Timeout Crossbar Arbiter Timeout Preset Value - * 15:08 Reserved - * 16:16 TimeoutEn Crossbar Arbiter Timer Enable (1: Disable) - * 31:17 Reserved - */ -#define PCI_IFXBRTMO_Timeout_GET(v) PCI__EXT(v, 0, 8) -#define PCI_IFXBRTMO_TimeoutEn PCI__BIT(16) - -/* - * Table 264: PCI Read Response Crossbar Control (Low) - * 03:00 Arb0 Slice 0 of PCI slave pizza arbiter. - * 07:04 Arb1 Slice 1 of PCI slave pizza arbiter. - * 11:08 Arb2 Slice 2 of PCI slave pizza arbiter. - * 15:12 Arb3 Slice 3 of PCI slave pizza arbiter. - * 19:16 Arb4 Slice 4 of PCI slave pizza arbiter. - * 23:20 Arb5 Slice 5 of PCI slave pizza arbiter. - * 27:24 Arb6 Slice 6 of PCI slave pizza arbiter. - * 31:28 Arb7 Slice 7 of PCI slave pizza arbiter. - */ -#define PCI_RRXBRCL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4) -#define PCI_RRXBRCL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\ - (v) |= PCI__INS((n)*4, s))) - - -/* - * Table 265: PCI Read Response Crossbar Control (High) - * 03:00 Arb8 Slice 8 of PCI slave pizza arbiter. - * 07:04 Arb9 Slice 9 of PCI slave pizza arbiter. - * 11:08 Arb10 Slice 10 of PCI slave pizza arbiter. - * 15:12 Arb11 Slice 11 of PCI slave pizza arbiter. - * 19:16 Arb12 Slice 12 of PCI slave pizza arbiter. - * 23:20 Arb13 Slice 13 of PCI slave pizza arbiter. - * 27:24 Arb14 Slice 14 of PCI slave pizza arbiter. - * 31:28 Arb15 Slice 15 of PCI slave pizza arbiter. - */ -#define PCI_RRXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4) -#define PCI_RRXBRCH_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, ((n)*-8)4, 4),\ - (v) |= PCI__INS(((n)-8)*4, s))) - -/* - * Table 266: PCI Sync Barrier Virtual Register - * 31:0 SyncReg Sync Barrier Virtual Register - * PCI read from this register results in PCI slave sync barrier - * action. The returned data is un-deterministic. Read Only. - */ - -/* - * Table 267: PCI P2P Configuration - * 07:00 2ndBusL Secondary PCI Interface Bus Range Lower Boundary - * 15:08 2ndBusH Secondary PCI Interface Bus Range Upper Boundary - * 23:16 BusNum The PCI bus number to which the PCI interface - * is connected. - * 28:24 DevNum The PCI interface's device number. - * 31:29 Reserved Reserved. - */ -#define PCI_P2PCFG_2ndBusL_GET(v) PCI__EXT(v, 0, 8) -#define PCI_P2PCFG_2ndBusH_GET(v) PCI__EXT(v, 8, 8) -#define PCI_P2PCFG_BusNum_GET(v) PCI__EXT(v, 16, 8) -#define PCI_P2PCFG_DevNum_GET(v) PCI__EXT(v, 24, 5) - -/* - * Table 268: PCI P2P Swap Control - * 02:00 M0Sw P2P Mem0 BAR Swap Control - * 03:03 M0Req64 P2P Mem0 BAR Force REQ64 - * 06:04 M1Sw P2P Mem1 BAR Swap Control - * 07:07 M1Req64 P2P Mem1 BAR Force REQ64 - * 10:08 DM0Sw P2P DAC Mem0 BAR Swap Control - * 11:11 DM0Req64 P2P DAC Mem0 BAR Force REQ64 - * 14:12 DM1Sw P2P DAC Mem1 BAR Swap Control - * 15:15 DM1Req64 P2P DAC Mem1 BAR Force REQ64 - * 18:16 IOSw P2P I/O BAR Swap Control - * 19:19 Reserved - * 22:20 CfgSw P2P Configuration Swap Control - * 31:19 Reserved - */ -#define PCI_P2PSWAP_M0Sw_GET(v) PCI__EXT(v, 0, 3) -#define PCI_P2PSWAP_M0Req64 PCI__BIT(3) -#define PCI_P2PSWAP_M1Sw_GET(v) PCI__EXT(v, 4, 3) -#define PCI_P2PSWAP_M1Req64 PCI__BIT(7) -#define PCI_P2PSWAP_DM0Sw_GET(v) PCI__EXT(v, 8, 3) -#define PCI_P2PSWAP_DM0Req64 PCI__BIT(11) -#define PCI_P2PSWAP_DM1Sw_GET(v) PCI__EXT(v, 12, 3) -#define PCI_P2PSWAP_DM1Req64 PCI__BIT(15) -#define PCI_P2PSWAP_CfgSw_GET(v) PCI__EXT(v, 20, 3) - - - -/* - * Table 269: PCI Access Control Base (Low) - * 11:00 Addr Base Address Corresponds to address bits[31:20]. - * 12:12 PrefetchEn Read Prefetch Enable - * 0: Prefetch disabled (The PCI slave reads single words) - * 1: Prefetch enabled. - * 14:14 Reserved Must be 0 - * 15:15 Reserved - * 16:16 RdPrefetch PCI Read Aggressive Prefetch Enable; 0: Disable; - * 1: Enable (The PCI slave prefetches two - * bursts in advance) - * 17:17 RdLinePrefetch PCI Read Line Aggressive Prefetch Enable; 0: Disable; - * 1: Enable (PCI slave prefetch two bursts in advance) - * 18:18 RdMulPrefetch PCI Read Multiple Aggressive Prefetch Enable - * 0: Disable; 1: Enable (PCI slave prefetch two bursts in - * advance) - * 19:19 Reserved - * 21:20 MBurst PCI Max Burst - * Specifies the maximum burst size for a single transac- - * tion between a PCI slave and the other interfaces - * 00 - 4 64-bit words - * 01 - 8 64-bit words - * 10 - 16 64-bit words - * 11 - Reserved - * 23:22 Reserved - * 25:24 PCISwap Data Swap Control - * 00 - Byte Swap - * 01 - No swapping - * 10 - Both byte and word swap - * 11 - Word swap - * 26:26 Reserved Must be 0 - * 27:27 Reserved - * 28:28 AccProt Access Protect (0: PCI access is allowed; 1; Region is - not accessible from PCI) - * 29:29 WrProt Write Protect (0: PCI write is allowed; 1: Region is - * not writeable from PCI) - * 31:30 Reserved - */ -#define PCI_ACCCTLBASEL_Addr_GET(v) PCI__EXT(v, 0, 12) -#define PCI_ACCCTLBASEL_PrefetchEn PCI__BIT(12) -#define PCI_ACCCTLBASEL_MBZ0_14 PCI__BIT(14) -#define PCI_ACCCTLBASEL_RdPrefetch PCI__BIT(16) -#define PCI_ACCCTLBASEL_RdLinePrefetch PCI__BIT(17) -#define PCI_ACCCTLBASEL_RdMulPrefetch PCI__BIT(18) -#define PCI_ACCCTLBASEL_WBurst PCI__EXT(v, 20, 2) -#define PCI_ACCCTLBASEL_WBurst_8_QW PCI__INS(20, PCI_WBURST_8_QW) -#define PCI_ACCCTLBASEL_PCISwap PCI__EXT(v, 24, 2) -#define PCI_ACCCTLBASEL_PCISwap_NoSwap PCI__INS(24, PCI_PCISWAP_NoSwap) -#define PCI_ACCCTLBASEL_MBZ0_26 PCI__BIT(26) -#define PCI_ACCCTLBASEL_AccProt PCI__BIT(28) -#define PCI_ACCCTLBASEL_WrProt PCI__BIT(29) - -#define PCI_WBURST_4_QW 0x00 -#define PCI_WBURST_8_QW 0x01 -#define PCI_WBURST_16_QW 0x02 -#define PCI_WBURST_Reserved 0x04 - -#define PCI_PCISWAP_ByteSwap 0x00 -#define PCI_PCISWAP_NoSwap 0x01 -#define PCI_PCISWAP_ByteWordSwap 0x02 -#define PCI_PCISWAP_WordSwap 0x04 - -/* - * Table 293: PCI Snoop Control Base (Low) - * 11:00 Addr Base Address Corresponds to address bits[31:20]. - * 13:12 Snoop Snoop Type - * 31:14 Reserved - */ -#define PCI_SNOOPCTL_ADDR(v) PCI__EXT(v, 0, 12) -#define PCI_SNOOPCTL_TYPE(v) PCI__EXT(v, 12, 2) - -#define PCI_SNOOP_None 0 /* no snoop */ -#define PCI_SNOOP_WT 1 /* Snoop to WT region */ -#define PCI_SNOOP_WB 2 /* Snoop to WB region */ - - -/* - * Table 305: PCI Configuration Address - * - * 07:02 RegNum Register number. - * 10:08 FunctNum Function number. - * 15:11 DevNum Device number. - * 23:16 BusNum Bus number. - * 31:31 ConfigEn When set, an access to the Configuration Data - * register is translated into a Configuration - * or Special cycle on the PCI bus. - */ -#define PCI_CFG_MAKE_TAG(bus, dev, fun, reg) (PCI__BIT(31)|\ - PCI__INS(16, (bus))|\ - PCI__INS(11, (dev))|\ - PCI__INS( 8, (fun))|\ - PCI__INS( 0, (reg))) -#define PCI_CFG_GET_BUSNO(tag) PCI__EXT(tag, 16, 8) -#define PCI_CFG_GET_DEVNO(tag) PCI__EXT(tag, 11, 5) -#define PCI_CFG_GET_FUNCNO(tag) PCI__EXT(tag, 8, 3) -#define PCI_CFG_GET_REGNO(tag) PCI__EXT(tag, 0, 8) - -/* - * Table 306: PCI Configuration Data - * - * 31:00 ConfigData The data is transferred to/from the PCI bus when - * the CPU accesses this register and the ConfigEn - * bit in the Configuration Address register is set - * - * A CPU access to this register causes the GT64260 to perform a Configuration - * or Special cycle on the PCI bus. - */ - - -/* - * Table 307: PCI Interrupt Acknowledge (This register is READ ONLY) - * 31:00 IntAck A CPU read access to this register forces an - * interrupt acknowledge cycle on the PCI bus. - */ - - -/* - * Table 308: PCI SERR* Mask - * - * NOTE: The GT64260 asserts SERR* only if SERR* is enabled via the PCI Status - * and Command register. - * If the corresponding bit is set, then asserts SERR* upon ... - */ -#define PCI_SERRMSK_SAPerr PCI__BIT(0) /* PCI slave detection of bad - * address parity. */ -#define PCI_SERRMSK_SWrPerr PCI__BIT(1) /* PCI slave detection of bad - * write data parity. */ -#define PCI_SERRMSK_SRdPerr PCI__BIT(2) /* a PERR* response to read - * data driven by the PCI - * slave. */ -#define PCI_SERRMSK_MAPerr PCI__BIT(4) /* a PERR* response to an - * address driven by the PCI - * master. */ -#define PCI_SERRMSK_MWrPerr PCI__BIT(5) /* a PERR* response to write - * data driven by the PCI - * master. */ -#define PCI_SERRMSK_MRdPerr PCI__BIT(6) /* bad data parity detection - * during a PCI master read - * transaction. */ -#define PCI_SERRMSK_MMabort PCI__BIT(8) /* a PCI master generation of - * master abort. */ -#define PCI_SERRMSK_MTabort PCI__BIT(9) /* a PCI master detection of - * target abort. */ -#define PCI_SERRMSK_MRetry PCI__BIT(11) /* a PCI master reaching retry - * counter limit. */ -#define PCI_SERRMSK_SMabort PCI__BIT(16) /* a PCI slave detection of - * master abort. */ -#define PCI_SERRMSK_STabort PCI__BIT(17) /* a PCI slave termination of - * a transaction with Target - * Abort. */ -#define PCI_SERRMSK_SAccProt PCI__BIT(18) /* a PCI slave access protect - * violation. */ -#define PCI_SERRMSK_SWrProt PCI__BIT(19) /* a PCI slave write protect - * violation. */ -#define PCI_SERRMSK_SRdBuf PCI__BIT(20) /* the PCI slave's read buffer, - * discard timer expires */ -#define PCI_SERRMSK_Arb PCI__BIT(21) /* the internal PCI arbiter - * detection of a broken PCI - * master. */ - -#define PCI_SERRMSK_ALL_ERRS \ - (PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \ - |PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \ - |PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \ - |PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \ - |PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb) - - - -/* - * Table 309: PCI Error Address (Low) -- Read Only. - * 31:00 ErrAddr PCI address bits [31:0] are latched upon an error - * condition. Upon address latch, no new addresses can - * be registered (due to additional error condition) until - * the register is being read. - */ - - - -/* - * Table 310: PCI Error Address (High) Applicable only when running DAC cycles. - * 31:00 ErrAddr PCI address bits [63:32] are latched upon - * error condition. - * - * NOTE: Upon data sample, no new data is latched until the PCI Error Low - * Address register is read. This means that PCI Error Low Address - * register must bethe last register read by the interrupt handler. - */ - -/* - * Table 311: PCI Error Data (Low) - * 31:00 ErrData PCI data bits [31:00] are latched upon error condition. - */ - -/* - * Table 312: PCI Error Data (High) Applicable only when running - * 64-bit cycles. - * 31:00 ErrData PCI data bits [63:32] are latched upon error condition. - */ - -/* - * Table 313: PCI Error Command - * 03:00 ErrCmd PCI command is latched upon error condition. - * 07:04 Reserved - * 15:08 ErrBE PCI byte enable is latched upon error condition. - * 16:16 ErrPAR PCI PAR is latched upon error condition. - * 17:17 ErrPAR64 PCI PAR64 is latched upon error condition. - * Applicable only when running 64-bit cycles. - * 31:18 Reserved - * NOTE: Upon data sample, no new data is latched until the PCI Error Low - * Address register is read. This means that PCI Error Low Address register - * must be the last register read by the interrupt handler. - */ -#define PCI_ERRCMD_Cmd_GET(v) PCI__EXT(v, 0, 4) -#define PCI_ERRCMD_ByteEn_GET(v) PCI__EXT(v, 8, 8) -#define PCI_ERRCMD_PAR PCI__BIT(16) -#define PCI_ERRCMD_PAR64 PCI__BIT(17) - -/* - * Table 314: PCI Interrupt Cause - * 1. All bits are Clear Only. A cause bit set upon error event occurrence. - * A write of 0 clears the bit. A write of 1 has no affect. - * 2. PCI Interrupt bits are organized in four groups: - * bits[ 7: 0] for address and data parity errors, - * bits[15: 8] for PCI master transaction failure (possible external - * target problem), - * bits[23:16] for slave response failure (possible external master problem), - * bits[26:24] for external PCI events that require CPU handle. - */ -#define PCI_IC_SAPerr PCI__BIT(0) /* The PCI slave detected - * bad address parity. */ -#define PCI_IC_SWrPerr PCI__BIT(1) /* The PCI slave detected - * bad write data parity. */ -#define PCI_IC_SRdPerr PCI__BIT(2) /* PERR* response to read - * data driven by PCI slave. */ -#define PCI_IC_MAPerr PCI__BIT(4) /* PERR* response to address - * driven by the PCI master. */ -#define PCI_IC_MWrPerr PCI__BIT(5) /* PERR* response to write data - * driven by the PCI master. */ -#define PCI_IC_MRdPerr PCI__BIT(6) /* Bad data parity detected - * during the PCI master read - * transaction. */ -#define PCI_IC_MMabort PCI__BIT(8) /* The PCI master generated - * master abort. */ -#define PCI_IC_MTabort PCI__BIT(9) /* The PCI master detected - * target abort. */ -#define PCI_IC_MMasterEn PCI__BIT(10) /* An attempt to generate a PCI - * transaction while master is - * not enabled. */ -#define PCI_IC_MRetry PCI__BIT(11) /* The PCI master reached - * retry counter limit. */ -#define PCI_IC_SMabort PCI__BIT(16) /* The PCI slave detects an il- - * legal master termination. */ -#define PCI_IC_STabort PCI__BIT(17) /* The PCI slave terminates a - * transaction with Target - * Abort. */ -#define PCI_IC_SAccProt PCI__BIT(18) /* A PCI slave access protect - * violation. */ -#define PCI_IC_SWrProt PCI__BIT(19) /* A PCI slave write protect - * violation. */ -#define PCI_IC_SRdBuf PCI__BIT(20) /* A PCI slave read buffer - * discard timer expired. */ -#define PCI_IC_Arb PCI__BIT(21) /* Internal PCI arbiter detec- - * tion of a broken master. */ -#define PCI_IC_BIST PCI__BIT(24) /* PCI BIST Interrupt */ -#define PCI_IC_PMG PCI__BIT(25) /* PCI Power Management - * Interrupt */ -#define PCI_IC_PRST PCI__BIT(26) /* PCI Reset Assert */ - -/* -31:27 Sel Specifies the error event currently being reported in the -Error Address, Error Data, and Error Command registers. -*/ -#define PCI_IC_SEL_GET(v) PCI__EXT((v), 27, 5) -#define PCI_IC_SEL_SAPerr 0x00 -#define PCI_IC_SEL_SWrPerr 0x01 -#define PCI_IC_SEL_SRdPerr 0x02 -#define PCI_IC_SEL_MAPerr 0x04 -#define PCI_IC_SEL_MWrPerr 0x05 -#define PCI_IC_SEL_MRdPerr 0x06 -#define PCI_IC_SEL_MMabort 0x08 -#define PCI_IC_SEL_MTabort 0x09 -#define PCI_IC_SEL_MMasterEn 0x0a -#define PCI_IC_SEL_MRetry 0x0b -#define PCI_IC_SEL_SMabort 0x10 -#define PCI_IC_SEL_STabort 0x11 -#define PCI_IC_SEL_SAccProt 0x12 -#define PCI_IC_SEL_SWrProt 0x13 -#define PCI_IC_SEL_SRdBuf 0x14 -#define PCI_IC_SEL_Arb 0x15 -#define PCI_IC_SEL_BIST 0x18 -#define PCI_IC_SEL_PMG 0x19 -#define PCI_IC_SEL_PRST 0x1a - -#define PCI_IC_SEL_Strings { \ - "SAPerr", "SWrPerr", "SRdPerr", "Rsvd#03", \ - "MAPerr", "MWrPerr", "MRdPerr", "Rsvd#07", \ - "MMabort", "MTabort", "MMasterEn", "MRetry", \ - "Rsvd#0c", "Rsvd#0d", "Rsvd#0e", "Rsvd#0f", \ - "SMabort", "STabort", "SAccProt", "SWrProt", \ - "SRdBuf", "Arb", "Rsvd#16", "Rsvd#17", \ - "BIST", "PMG", "PRST", "Rsvd#1b", \ - "Rsvd#1c", "Rsvd#1d", "Rsvd#1e", "Rsvd#1f" } - -/* - * Table 315: PCI Error Mask - * If the corresponding bit is 1, that interrupt is enabled - * Bits 3, 7, 12:15, 22:23, 27:31 are reserved. - */ -#define PCI_ERRMASK_SAPErr PCI__BIT(0) -#define PCI_ERRMASK_SWrPErr PCI__BIT(1) -#define PCI_ERRMASK_SRdPErr PCI__BIT(2) -#define PCI_ERRMASK_MAPErr PCI__BIT(4) -#define PCI_ERRMASK_MWRPErr PCI__BIT(5) -#define PCI_ERRMASK_MRDPErr PCI__BIT(6) -#define PCI_ERRMASK_MMAbort PCI__BIT(8) -#define PCI_ERRMASK_MTAbort PCI__BIT(9) -#define PCI_ERRMASK_MMasterEn PCI__BIT(10) -#define PCI_ERRMASK_MRetry PCI__BIT(11) -#define PCI_ERRMASK_SMAbort PCI__BIT(16) -#define PCI_ERRMASK_STAbort PCI__BIT(17) -#define PCI_ERRMASK_SAccProt PCI__BIT(18) -#define PCI_ERRMASK_SWrProt PCI__BIT(19) -#define PCI_ERRMASK_SRdBuf PCI__BIT(20) -#define PCI_ERRMASK_Arb PCI__BIT(21) -#define PCI_ERRMASK_BIST PCI__BIT(24) -#define PCI_ERRMASK_PMG PCI__BIT(25) -#define PCI_ERRMASK_PRST PCI__BIT(26) - -#endif /* _DEV_GTPCIREG_H_ */ diff --git a/c/src/lib/libbsp/powerpc/beatnik/marvell/gtreg.h b/c/src/lib/libbsp/powerpc/beatnik/marvell/gtreg.h deleted file mode 100644 index a6c87e2047..0000000000 --- a/c/src/lib/libbsp/powerpc/beatnik/marvell/gtreg.h +++ /dev/null @@ -1,854 +0,0 @@ -/* $NetBSD: gtreg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _DISCOVERY_DEV_GTREG_H_ -#define _DISCOVERY_DEV_GTREG_H_ - - -#define GT__BIT(bit) (1U << (bit)) -#define GT__MASK(bit) (GT__BIT(bit) - 1) -#define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) -#define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) -#define GT__INS(new, bit) ((new) << (bit)) - - -/* - * Table 30: CPU Address Decode Register Map - */ -#define GT_SCS0_Low_Decode 0x0008 -#define GT_SCS0_High_Decode 0x0010 -#define GT_SCS1_Low_Decode 0x0208 -#define GT_SCS1_High_Decode 0x0210 -#define GT_SCS2_Low_Decode 0x0018 -#define GT_SCS2_High_Decode 0x0020 -#define GT_SCS3_Low_Decode 0x0218 -#define GT_SCS3_High_Decode 0x0220 -#define GT_CS0_Low_Decode 0x0028 -#define GT_CS0_High_Decode 0x0030 -#define GT_CS1_Low_Decode 0x0228 -#define GT_CS1_High_Decode 0x0230 -#define GT_CS2_Low_Decode 0x0248 -#define GT_CS2_High_Decode 0x0250 -#define GT_CS3_Low_Decode 0x0038 -#define GT_CS3_High_Decode 0x0040 -#define GT_BootCS_Low_Decode 0x0238 -#define GT_BootCS_High_Decode 0x0240 -#define GT_PCI0_IO_Low_Decode 0x0048 -#define GT_PCI0_IO_High_Decode 0x0050 -#define GT_PCI0_Mem0_Low_Decode 0x0058 -#define GT_PCI0_Mem0_High_Decode 0x0060 -#define GT_PCI0_Mem1_Low_Decode 0x0080 -#define GT_PCI0_Mem1_High_Decode 0x0088 -#define GT_PCI0_Mem2_Low_Decode 0x0258 -#define GT_PCI0_Mem2_High_Decode 0x0260 -#define GT_PCI0_Mem3_Low_Decode 0x0280 -#define GT_PCI0_Mem3_High_Decode 0x0288 -#define GT_PCI1_IO_Low_Decode 0x0090 -#define GT_PCI1_IO_High_Decode 0x0098 -#define GT_PCI1_Mem0_Low_Decode 0x00a0 -#define GT_PCI1_Mem0_High_Decode 0x00a8 -#define GT_PCI1_Mem1_Low_Decode 0x00b0 -#define GT_PCI1_Mem1_High_Decode 0x00b8 -#define GT_PCI1_Mem2_Low_Decode 0x02a0 -#define GT_PCI1_Mem2_High_Decode 0x02a8 -#define GT_PCI1_Mem3_Low_Decode 0x02b0 -#define GT_PCI1_Mem3_High_Decode 0x02b8 -#define GT_Internal_Decode 0x0068 -#define GT_CPU0_Low_Decode 0x0290 -#define GT_CPU0_High_Decode 0x0298 -#define GT_CPU1_Low_Decode 0x02c0 -#define GT_CPU1_High_Decode 0x02c8 -/* ts, 2005/8: it seems that these are implicitely written - * when setting the 'Low_Decode' regs... - */ -#define GT_PCI0_IO_Remap 0x00f0 -#define GT_PCI0_Mem0_Remap_Low 0x00f8 -#define GT_PCI0_Mem0_Remap_High 0x0320 -#define GT_PCI0_Mem1_Remap_Low 0x0100 -#define GT_PCI0_Mem1_Remap_High 0x0328 -#define GT_PCI0_Mem2_Remap_Low 0x02f8 -#define GT_PCI0_Mem2_Remap_High 0x0330 -#define GT_PCI0_Mem3_Remap_Low 0x0300 -#define GT_PCI0_Mem3_Remap_High 0x0338 -#define GT_PCI1_IO_Remap 0x0108 -#define GT_PCI1_Mem0_Remap_Low 0x0110 -#define GT_PCI1_Mem0_Remap_High 0x0340 -#define GT_PCI1_Mem1_Remap_Low 0x0118 -#define GT_PCI1_Mem1_Remap_High 0x0348 -#define GT_PCI1_Mem2_Remap_Low 0x0310 -#define GT_PCI1_Mem2_Remap_High 0x0350 -#define GT_PCI1_Mem3_Remap_Low 0x0318 -#define GT_PCI1_Mem3_Remap_High 0x0358 - - -/* - * Table 31: CPU Control Register Map - */ -#define GT_CPU_Cfg 0x0000 -#define GT_CPU_Mode 0x0120 -#define GT_CPU_Master_Ctl 0x0160 -#define GT_CPU_If_Xbar_Ctl_Low 0x0150 -#define GT_CPU_If_Xbar_Ctl_High 0x0158 -#define GT_CPU_If_Xbar_Timeout 0x0168 -#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 -#define GT_260_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 - -/* - * Table 32: CPU Sync Barrier Register Map - */ -#define GT_260_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) -#define GT_260_PCI0_Sync_Barrier 0x00c0 -#define GT_260_PCI1_Sync_Barrier 0x00c8 - -/* - * Table 33: CPU Access Protection Register Map - */ -#define GT_Protect_Low_0 0x0180 -#define GT_Protect_High_0 0x0188 -#define GT_Protect_Low_1 0x0190 -#define GT_Protect_High_1 0x0198 -#define GT_Protect_Low_2 0x01a0 -#define GT_Protect_High_2 0x01a8 -#define GT_Protect_Low_3 0x01b0 -#define GT_Protect_High_3 0x01b8 -#define GT_260_Protect_Low_4 0x01c0 -#define GT_260_Protect_High_4 0x01c8 -#define GT_260_Protect_Low_5 0x01d0 -#define GT_260_Protect_High_5 0x01d8 -#define GT_260_Protect_Low_6 0x01e0 -#define GT_260_Protect_High_6 0x01e8 -#define GT_260_Protect_Low_7 0x01f0 -#define GT_260_Protect_High_7 0x01f8 - -/* - * Table 34: Snoop Control Register Map - */ -#define GT_260_Snoop_Base_0 0x0380 -#define GT_260_Snoop_Top_0 0x0388 -#define GT_260_Snoop_Base_1 0x0390 -#define GT_260_Snoop_Top_1 0x0398 -#define GT_260_Snoop_Base_2 0x03a0 -#define GT_260_Snoop_Top_2 0x03a8 -#define GT_260_Snoop_Base_3 0x03b0 -#define GT_260_Snoop_Top_3 0x03b8 - -/* - * Table 35: CPU Error Report Register Map - */ -#define GT_CPU_Error_Address_Low 0x0070 -#define GT_CPU_Error_Address_High 0x0078 -#define GT_CPU_Error_Data_Low 0x0128 -#define GT_CPU_Error_Data_High 0x0130 -#define GT_CPU_Error_Parity 0x0138 -#define GT_CPU_Error_Cause 0x0140 -#define GT_CPU_Error_Mask 0x0148 - -#define GT_DecodeAddr_SET(g, r, v) \ - do { \ - gt_read((g), GT_Internal_Decode); \ - gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ - while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ - } while (0) - -#define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) -#define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) - -#define GT_MPP_Control0 0xf000 -#define GT_MPP_Control1 0xf004 -#define GT_MPP_Control2 0xf008 -#define GT_MPP_Control3 0xf00c - -#define GT_GPP_IO_Control 0xf100 -#define GT_GPP_Level_Control 0xf110 -#define GT_GPP_Value 0xf104 -#define GT_GPP_Interrupt_Cause 0xf108 -#define GT_GPP_Interrupt_Mask 0xf10c -/* - * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 - * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 - * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 - * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 - * Table 44: CS[0]* Low Decode Address, Offset: 0x028 - * Table 46: CS[1]* Low Decode Address, Offset: 0x228 - * Table 48: CS[2]* Low Decode Address, Offset: 0x248 - * Table 50: CS[3]* Low Decode Address, Offset: 0x038 - * Table 52: BootCS* Low Decode Address, Offset: 0x238 - * Table 75: CPU 0 Low Decode Address, Offset: 0x290 - * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 - * - * 11:00 LowAddr SCS[0] Base Address - * 31:12 Reserved Must be 0. - */ - -/* - * Table 37: SCS[0]* High Decode Address, Offset: 0x010 - * Table 39: SCS[1]* High Decode Address, Offset: 0x210 - * Table 41: SCS[2]* High Decode Address, Offset: 0x020 - * Table 43: SCS[3]* High Decode Address, Offset: 0x220 - * Table 45: CS[0]* High Decode Address, Offset: 0x030 - * Table 47: CS[1]* High Decode Address, Offset: 0x230 - * Table 49: CS[2]* High Decode Address, Offset: 0x250 - * Table 51: CS[3]* High Decode Address, Offset: 0x040 - * Table 53: BootCS* High Decode Address, Offset: 0x240 - * Table 76: CPU 0 High Decode Address, Offset: 0x298 - * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 - * - * 11:00 HighAddr SCS[0] Top Address - * 31:12 Reserved - */ - -/* - * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 - * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 - * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 - * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 - * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 - * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 - * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 - * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 - * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 - * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 - * - * 11:00 LowAddr PCI IO/Memory Space Base Address - * 23:12 Reserved - * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; - * 1: No swapping; 2: Both byte and word swap; - * 3: Word swap; 4..7: Reserved) - * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when - * configured to 64-bit PCI bus and not I/O) - * 0: Assert s REQ64* only when transaction - * is longer than 64-bits. - * 1: Always assert REQ64*. - * 31:28 Reserved - */ -#define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) -#define GT_PCISwap_ByteSwap 0 -#define GT_PCISwap_NoSwap 1 -#define GT_PCISwap_ByteWordSwap 2 -#define GT_PCISwap_WordSwap 3 -#define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) - -/* - * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 - * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 - * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 - * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 - * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 - * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 - * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 - * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 - * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 - * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 - * - * 11:00 HighAddr PCI_0 I/O Space Top Address - * 31:12 Reserved - */ - -/* - * Table 74: Internal Space Decode, Offset: 0x068 - * 15:00 IntDecode GT64260 Internal Space Base Address - * 23:16 Reserved - * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. - * NOTE: Reserved for Galileo Technology usage. - * Relevant only for PCI master configuration - * transactions on the PCI bus. - * 31:27 Reserved - */ - -/* - * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 - * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 - * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 - * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 - * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 - * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 - * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 - * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 - * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 - * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 - * - * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) - * 31:12 Reserved - */ - -/* - * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 - * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 - * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 - * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 - * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 - * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 - * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 - * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 - * - * 31:00 Remap PCI Memory Address Remap (high 32 bits) - */ - -/* - * Table 97: CPU Configuration, Offset: 0x000 - * 07:00 NoMatchCnt CPU Address Miss Counter - * 08:08 NoMatchCntEn CPU Address Miss Counter Enable - * NOTE: Relevant only if multi-GT is enabled. - * (0: Disabled; 1: Enabled) - * 09:09 NoMatchCntExt CPU address miss counter MSB - * 10:10 Reserved - * 11:11 AACKDelay Address Acknowledge Delay - * 0: AACK* is asserted one cycle after TS*. - * 1: AACK* is asserted two cycles after TS*. - * 12:12 Endianess Must be 0 - * NOTE: The GT64260 does not support the PowerPC - * Little Endian convention - * 13:13 Pipeline Pipeline Enable - * 0: Disabled. The GT64260 will not respond with - * AACK* to a new CPU transaction, before the - * previous transaction data phase completes. - * 1: Enabled. - * 14:14 Reserved - * 15:15 TADelay Transfer Acknowledge Delay - * 0: TA* is asserted one cycle after AACK* - * 1: TA* is asserted two cycles after AACK* - * 16:16 RdOOO Read Out of Order Completion - * 0: Not Supported, Data is always returned in - * order (DTI[0-2] is always driven - * 1: Supported - * 17:17 StopRetry Relevant only if PCI Retry is enabled - * 0: Keep Retry all PCI transactions targeted - * to the GT64260. - * 1: Stop Retry of PCI transactions. - * 18:18 MultiGTDec Multi-GT Address Decode - * 0: Normal address decoding - * 1: Multi-GT address decoding - * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... - * 0: is not checked. (Not connected) - * 1: is checked (Connected) - * 21:20 Reserved - * 22:22 PErrProp Parity Error Propagation - * 0: GT64260 always drives good parity on - * DP[0-7] during CPU reads. - * 1: GT64260 drives bad parity on DP[0-7] in case - * the read response from the target interface - * comes with erroneous data indication - * (e.g. ECC error from SDRAM interface). - * 25:23 Reserved - * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... - * 0: is not checked. (Not connected) - * 1: is checked (Connected) - * 27:27 RemapWrDis Address Remap Registers Write Control - * 0: Write to Low Address decode register. - * Results in writing of the corresponding - * Remap register. - * 1: Write to Low Address decode register. No - * affect on the corresponding Remap register. - * 28:28 ConfSBDis Configuration Read Sync Barrier Disable - * 0: enabled; 1: disabled - * 29:29 IOSBDis I/O Read Sync Barrier Disable - * 0: enabled; 1: disabled - * 30:30 ClkSync Clocks Synchronization - * 0: The CPU interface is running with SysClk, - * which is asynchronous to TClk. - * 1: The CPU interface is running with TClk. - * 31:31 Reserved - */ -#define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) -#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) -#define GT_CPUCfg_NoMatchCntExt GT__BIT(10) -#define GT_CPUCfg_AACKDelay GT__BIT(11) -#define GT_CPUCfg_Endianess GT__BIT(12) -#define GT_CPUCfg_Pipeline GT__BIT(13) -#define GT_CPUCfg_TADelay GT__BIT(15) -#define GT_CPUCfg_RdOOO GT__BIT(16) -#define GT_CPUCfg_StopRetry GT__BIT(17) -#define GT_CPUCfg_MultiGTDec GT__BIT(18) -#define GT_CPUCfg_DPValid GT__BIT(19) -#define GT_CPUCfg_PErrProp GT__BIT(22) -#define GT_CPUCfg_APValid GT__BIT(26) -#define GT_CPUCfg_RemapWrDis GT__BIT(27) -#define GT_CPUCfg_ConfSBDis GT__BIT(28) -#define GT_CPUCfg_IOSBDis GT__BIT(29) -#define GT_CPUCfg_ClkSync GT__BIT(30) - -/* - * Table 98: CPU Mode, Offset: 0x120, Read only - * 01:00 MultiGTID Multi-GT ID - * Represents the ID to which the GT64260 responds - * to during a multi-GT address decoding period. - * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration - * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions - * 07:04 CPUType - * 0x0-0x3: Reserved - * 0x4: 64-bit PowerPC CPU, 60x bus - * 0x5: 64-bit PowerPC CPU, MPX bus - * 0x6-0xf: Reserved - * 31:08 Reserved - */ -#define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) -#define GT_CPUMode_MultiGT GT__BIT(2) -#define GT_CPUMode_RetryEn GT__BIT(3) -#define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) - -/* - * Table 99: CPU Master Control, Offset: 0x160 - * 07:00 Reserved - * 08:08 IntArb CPU Bus Internal Arbiter Enable - * NOTE: Only relevant to 60x bus mode. When - * running MPX bus, the GT64260 internal - * arbiter must be used. - * 0: Disabled. External arbiter is required. - * 1: Enabled. Use the GT64260 CPU bus arbiter. - * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control - * NOTE: This bit must be set to 1. It is reserved - * for Galileo Technology usage. - * 0: Enable internal bus sharing between master - * and slave interfaces. - * 1: Disable internal bus sharing between master - * and slave interfaces. - * 10:10 MWrTrig Master Write Transaction Trigger - * 0: With first valid write data - * 1: With last valid write data - * 11:11 MRdTrig Master Read Response Trigger - * 0: With first valid read data - * 1: With last valid read data - * 12:12 CleanBlock Clean Block Snoop Transaction Support - * 0: CPU does not support clean block (603e,750) - * 1: CPU supports clean block (604e,G4) - * 13:13 FlushBlock Flush Block Snoop Transaction Support - * 0: CPU does not support flush block (603e,750) - * 1: CPU supports flush block (604e,G4) - * 31:14 Reserved - */ -#define GT_CPUMstrCtl_IntArb GT__BIT(8) -#define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) -#define GT_CPUMstrCtl_MWrTrig GT__BIT(10) -#define GT_CPUMstrCtl_MRdTrig GT__BIT(11) -#define GT_CPUMstrCtl_CleanBlock GT__BIT(12) -#define GT_CPUMstrCtl_FlushBlock GT__BIT(13) - -#define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ -#define GT_ArbSlice_DEVICE 0x1 /* Device request */ -#define GT_ArbSlice_NULL 0x2 /* NULL request */ -#define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ -#define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ -#define GT_ArbSlice_COMM 0x5 /* Comm unit access */ -#define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ -#define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ - /* 0x8-0xf: Reserved */ - -/* Pass in the slice number (from 0..16) as 'n' - */ -#define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) - -/* - * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 - * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter - * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter - * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter - * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter - * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter - * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter - * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter - * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter - */ - -/* - * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 - * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter - * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter - * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter - * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter - * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter - * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter - * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter - * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter - */ - -/* - * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 - * NOTE: Reserved for Galileo Technology usage. - * 07:00 Timeout Crossbar Arbiter Timeout Preset Value - * 15:08 Reserved - * 16:16 TimeoutEn Crossbar Arbiter Timer Enable - * (0: Enable; 1: Disable) - * 31:17 Reserved - */ - -/* - * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 - * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter - * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter - * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter - * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter - * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter - * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter - * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter - * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter - */ -/* - * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 - * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter - * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter - * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter - * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter - * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter - * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter - * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter - * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter - */ - -/* - * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 - * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 - * NOTE: The read data is random and should be ignored. - * 31:00 SyncBarrier A CPU read from this register creates a - * synchronization barrier cycle. - */ - -/* - * Table 107: CPU Protect Address 0 Low, Offset: 0x180 - * Table 109: CPU Protect Address 1 Low, Offset: 0x190 - * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 - * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 - * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 - * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 - * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 - * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 - * - * 11:00 LowAddr CPU Protect Region Base Address - * Corresponds to address bits[31:20]. - * 15:12 Reserved. Must be 0 - * 16:16 AccProtect CPU Access Protect - * Access is (0: allowed; 1: forbidden) - * 17:17 WrProtect CPU Write Protect - * Writes are (0: allowed; 1: forbidden) - * 18:18 CacheProtect CPU caching protect. Caching (block read) - * is (0: allowed; 1: forbidden) - * 31:19 Reserved - */ -#define GT_CPU_AccProtect GT__BIT(16) -#define GT_CPU_WrProtect GT__BIT(17) -#define GT_CPU_CacheProtect GT__BIT(18) - -/* - * Table 108: CPU Protect Address 0 High, Offset: 0x188 - * Table 110: CPU Protect Address 1 High, Offset: 0x198 - * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 - * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 - * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 - * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 - * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 - * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 - * - * 11:00 HighAddr CPU Protect Region Top Address - * Corresponds to address bits[31:20] - * 31:12 Reserved - */ - -/* - * Table 123: Snoop Base Address 0, Offset: 0x380 - * Table 125: Snoop Base Address 1, Offset: 0x390 - * Table 127: Snoop Base Address 2, Offset: 0x3a0 - * Table 129: Snoop Base Address 3, Offset: 0x3b0 - * - * 11:00 LowAddr Snoop Region Base Address [31:20] - * 15:12 Reserved Must be 0. - * 17:16 Snoop Snoop Type - * 0x0: No Snoop - * 0x1: Snoop to WT region - * 0x2: Snoop to WB region - * 0x3: Reserved - * 31:18 Reserved - */ -#define GT_Snoop_GET(v) GT__EXT((v), 16, 2) -#define GT_Snoop_INS(v) GT__INS((v), 16) -#define GT_Snoop_None 0 -#define GT_Snoop_WT 1 -#define GT_Snoop_WB 2 - - -/* - * Table 124: Snoop Top Address 0, Offset: 0x388 - * Table 126: Snoop Top Address 1, Offset: 0x398 - * Table 128: Snoop Top Address 2, Offset: 0x3a8 - * Table 130: Snoop Top Address 3, Offset: 0x3b8 - * 11:00 HighAddr Snoop Region Top Address [31:20] - * 31:12 Reserved - */ - - -/* - * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. - * In case of multiple errors, only the first one is latched. New error - * report latching is enabled only after the CPU Error Address Low register - * is being read. - * 31:00 ErrAddr Latched address bits [31:0] of a CPU - * transaction in case of: - * o illegal address (failed address decoding) - * o access protection violation - * o bad data parity - * o bad address parity - * Upon address latch, no new address are - * registered (due to additional error condition), - * until the register is being read. - */ - -/* - * Table 132: CPU Error Address High, Offset: 0x078, Read Only. - * Once data is latched, no new data can be registered (due to additional - * error condition), until CPU Error Low Address is being read (which - * implies, it should be the last being read by the interrupt handler). - * 03:00 Reserved - * 07:04 ErrPar Latched address parity bits in case - * of bad CPU address parity detection. - * 31:08 Reserved - */ -#define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) - -/* - * Table 133: CPU Error Data Low, Offset: 0x128, Read only. - * 31:00 PErrData Latched data bits [31:0] in case of bad data - * parity sampled on write transactions or on - * master read transactions. - */ - -/* - * Table 134: CPU Error Data High, Offset: 0x130, Read only. - * 31:00 PErrData Latched data bits [63:32] in case of bad data - * parity sampled on write transactions or on - * master read transactions. - */ - -/* - * Table 135: CPU Error Parity, Offset: 0x138, Read only. - * 07:00 PErrPar Latched data parity bus in case of bad data - * parity sampled on write transactions or on - * master read transactions. - * 31:10 Reserved - */ -#define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) - -/* - * Table 136: CPU Error Cause, Offset: 0x140 - * Bits[7:0] are clear only. A cause bit is set upon an error condition - * occurrence. Write a 0 value to clear the bit. Writing a 1 value has - * no affect. - * 00:00 AddrOut CPU Address Out of Range - * 01:01 AddrPErr Bad Address Parity Detected - * 02:02 TTErr Transfer Type Violation. - * The CPU attempts to burst (read or write) to an - * internal register. - * 03:03 AccErr Access to a Protected Region - * 04:04 WrErr Write to a Write Protected Region - * 05:05 CacheErr Read from a Caching protected region - * 06:06 WrDataPErr Bad Write Data Parity Detected - * 07:07 RdDataPErr Bad Read Data Parity Detected - * 26:08 Reserved - * 31:27 Sel Specifies the error event currently being - * reported in Error Address, Error Data, and - * Error Parity registers. - * 0x0: AddrOut - * 0x1: AddrPErr - * 0x2: TTErr - * 0x3: AccErr - * 0x4: WrErr - * 0x5: CacheErr - * 0x6: WrDataPErr - * 0x7: RdDataPErr - * 0x8-0x1f: Reserved - */ -#define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) -#define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) -#define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) -#define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) -#define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) -#define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) -#define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) -#define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) - -#define GT_CPUError_Sel_AddrOut 0 -#define GT_CPUError_Sel_AddrPErr 1 -#define GT_CPUError_Sel_TTErr 2 -#define GT_CPUError_Sel_AccErr 3 -#define GT_CPUError_Sel_WrErr 4 -#define GT_CPUError_Sel_CacheErr 5 -#define GT_CPUError_Sel_WrDataPErr 6 -#define GT_CPUError_Sel_RdDataPErr 7 - -#define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) - -/* - * Table 137: CPU Error Mask, Offset: 0x148 - * 00:00 AddrOut If set to 1, enables AddrOut interrupt. - * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. - * 02:02 TTErr If set to 1, enables TTErr interrupt. - * 03:03 AccErr If set to 1, enables AccErr interrupt. - * 04:04 WrErr If set to 1, enables WrErr interrupt. - * 05:05 CacheErr If set to 1, enables CacheErr interrupt. - * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. - * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. - * 31:08 Reserved - */ - -/* - * Comm Unit Interrupt registers - */ - -/* Comm Unit Arbiter Control */ -#define GT_CommUnitArb_Ctrl 0xf300 -/* GPP IRQs level vs. edge sensitivity */ -#define GT_CommUnitArb_Ctrl_GPP_Ints_Level_Sensitive (1<<10) - -#define GT_CommUnitIntr_Cause 0xf310 -#define GT_CommUnitIntr_Mask 0xf314 -#define GT_CommUnitIntr_ErrAddr 0xf318 - -#define GT_CommUnitIntr_E0 0x00000007 -#define GT_CommUnitIntr_E1 0x00000070 -#define GT_CommUnitIntr_E2 0x00000700 -#define GT_CommUnitIntr_S0 0x00070000 -#define GT_CommUnitIntr_S1 0x00700000 -#define GT_CommUnitIntr_Sel 0x70000000 - -/* - * SDRAM Error Report (ECC) Registers - */ -#define GT_260_ECC_Data_Lo 0x484 /* latched Error Data (low) */ -#define GT_260_ECC_Data_Hi 0x480 /* latched Error Data (high) */ -#define GT_260_ECC_Addr 0x490 /* latched Error Address */ -#define GT_260_ECC_Rec 0x488 /* latched ECC code from SDRAM */ -#define GT_260_ECC_Calc 0x48c /* latched ECC code from SDRAM */ -#define GT_260_ECC_Ctl 0x494 /* ECC Control */ -#define GT_260_ECC_Count 0x498 /* ECC 1-bit error count */ - -/* Timer/Counter Registers (t. straumann) - */ -#define GT_TIMER_0 0x0850 /* preset / running value */ -#define GT_TIMER_1 0x0854 -#define GT_TIMER_2 0x0858 -#define GT_TIMER_3 0x085c - -#define GT_TIMER_0_3_Ctl 0x0864 - -#define GT_TIMER_0_Ctl_Enb 0x00000001 /* enable timer */ -#define GT_TIMER_0_Ctl_Rld 0x00000002 /* reload after expiration */ -#define GT_TIMER_1_Ctl_Enb 0x00000100 /* enable timer */ -#define GT_TIMER_1_Ctl_Rld 0x00000200 /* reload after expiration */ -#define GT_TIMER_2_Ctl_Enb 0x00010000 /* enable timer */ -#define GT_TIMER_2_Ctl_Rld 0x00020000 /* reload after expiration */ -#define GT_TIMER_3_Ctl_Enb 0x01000000 /* enable timer */ -#define GT_TIMER_3_Ctl_Rld 0x02000000 /* reload after expiration */ - -#define GT_TIMER_0_3_Intr_Cse 0x0868 -#define GT_TIMER_0_Intr 0x00000001 -#define GT_TIMER_1_Intr 0x00000002 -#define GT_TIMER_2_Intr 0x00000004 -#define GT_TIMER_3_Intr 0x00000008 -#define GT_TIMER_Intr_Smry 0x80000000 /* Interrupt Summary */ - -#define GT_TIMER_0_3_Intr_Msk 0x086c - -/* - * Watchdog Registers - */ -#define GT_WDOG_Config 0xb410 -#define GT_WDOG_Value 0xb414 -#define GT_WDOG_Value_NMI GT__MASK(24) -#define GT_WDOG_Config_Preset GT__MASK(24) -#define GT_WDOG_Config_Ctl1a GT__BIT(24) -#define GT_WDOG_Config_Ctl1b GT__BIT(25) -#define GT_WDOG_Config_Ctl2a GT__BIT(26) -#define GT_WDOG_Config_Ctl2b GT__BIT(27) -#define GT_WDOG_Config_Enb GT__BIT(31) - -#define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) -#define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) - -/* - * Device Bus Interrupts - */ -#define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ -#define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ -#define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ - -/* - * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK - */ -#define GT_DEVBUS_DBurstErr GT__BIT(0) -#define GT_DEVBUS_DRdyErr GT__BIT(1) -#define GT_DEVBUS_Sel GT__BIT(27) -#define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) - -/* MV64360 */ -/* Enable individual CPU windows by *clearing* respective bits - * in MV_64360_BASE_ADDR_DISBL - * - * Bit ordering is: - * - * SDRAM_CS_0..3 (1<<0..3) - * DEV_CS_0..3 (1<<4..7) - * BOOT_CS_0..3 (1<<8) - * PCI_0_IO (1<<9) - * PCI_0_MEM_0..3 (1<<10..13) - * PCI_1_IO (1<<14) - * PCI_1_MEM_0..3 (1<<15..18) - * INTERNAL_SRAM (1<<19) - * MV64x60_REGS (1<<20) - */ -#define MV_64360_BASE_ADDR_DISBL (0x278) - -/* Internal SRAM */ -#define MV_64360_SRAM_BASE (0x268) -#define MV_64360_SRAM_CTRL (0x380) -/* Control register bits */ -#define MV_64360_SRAM_CacheWb GT__BIT(1) -/* default setup used by linux, motload (uses 90 instead of b0), ... - * Comments say: - * - parity enabled, - * - parity error propagation - * - arbitration not parked for CPU only - * - other bits are reserved - */ -#define MV_64360_SRAM_Ctl_Setup (0x001600b0) - -#define MV_64360_SRAM_TEST_MODE (0x3f4) -#define MV_64340_SRAM_ERR_CAUSE (0x388) -#define MV_64340_SRAM_ERR_ADDR (0x390) -#define MV_64340_SRAM_ERR_ADDR_HI (0X3f8) -#define MV_64340_SRAM_ERR_DATA_LO (0x398) -#define MV_64340_SRAM_ERR_DATA_HI (0x3a0) -#define MV_64340_SRAM_ERR_DATA_PARITY (0x3a8) - -#endif /* !_DISCOVERY_DEV_GTREG_H */ diff --git a/c/src/lib/libbsp/powerpc/beatnik/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/beatnik/vme/VMEConfig.h deleted file mode 100644 index 986a01674e..0000000000 --- a/c/src/lib/libbsp/powerpc/beatnik/vme/VMEConfig.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef RTEMS_BSP_VME_CONFIG_H -#define RTEMS_BSP_VME_CONFIG_H - -/* BSP specific address space configuration parameters */ - -/* - * Authorship - * ---------- - * This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was - * created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007, - * Stanford Linear Accelerator Center, Stanford University. - * - * Acknowledgement of sponsorship - * ------------------------------ - * The 'beatnik' BSP was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -#define _VME_DRIVER_TSI148 -#define _VME_DRIVER_UNIVERSE - -/* - * NOTE: the BSP (startup/bspstart.c) uses - * hardcoded window lengths that match this - * layout when setting BATs: - */ -#define _VME_A32_WIN0_ON_PCI 0x90000000 -/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate - * CSR for space. - */ -#define _VME_CSR_ON_PCI 0x9e000000 -#define _VME_A24_ON_PCI 0x9f000000 -#define _VME_A16_ON_PCI 0x9fff0000 - -/* start of the A32 window on the VME bus - * TODO: this should perhaps be a configuration option - */ -#define _VME_A32_WIN0_ON_VME 0x20000000 - -/* if _VME_DRAM_OFFSET is defined, the BSP - * will map our RAM onto the VME bus, starting - * at _VME_DRAM_OFFSET - */ -#define _VME_DRAM_OFFSET 0x90000000 - -extern int BSP_VMEInit(void); -extern int BSP_VMEIrqMgrInstall(void); - -#define BSP_VME_INSTALL_IRQ_MGR(err) \ - do { \ - err = -1; \ - switch (BSP_getBoardType()) { \ - case MVME6100: \ - err = theOps->install_irq_mgr( \ - VMETSI148_IRQ_MGR_FLAG_SHARED, \ - 0, BSP_IRQ_GPP_0 + 20, \ - 1, BSP_IRQ_GPP_0 + 21, \ - 2, BSP_IRQ_GPP_0 + 22, \ - 3, BSP_IRQ_GPP_0 + 23, \ - -1); \ - break; \ -\ - case MVME5500: \ - err = theOps->install_irq_mgr( \ - VMEUNIVERSE_IRQ_MGR_FLAG_SHARED | \ - VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND, \ - 0, BSP_IRQ_GPP_0 + 12, \ - 1, BSP_IRQ_GPP_0 + 13, \ - 2, BSP_IRQ_GPP_0 + 14, \ - 3, BSP_IRQ_GPP_0 + 15, \ - -1); \ - break; \ -\ - default: \ - printk("WARNING: unknown board; "); \ - break; \ - } \ - if ( err ) \ - printk("VME interrupt manager NOT INSTALLED (error: %i)\n", err); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h b/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h deleted file mode 100644 index d989785a7d..0000000000 --- a/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_EP1A_BSP_H -#define LIBBSP_POWERPC_EP1A_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <libcpu/io.h> -#include <rtems/clockdrv.h> -#include <bsp/vectors.h> - -/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ -#define _IO_BASE CHRP_ISA_IO_BASE -#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE -/* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET -#define PCI_MEM_BASE 0x80000000 -#define PCI_MEM_BASE_ADJUSTMENT 0 -/* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET - -/* offset of pci memory as seen from the CPU */ -#undef PCI_MEM_BASE -#define PCI_MEM_BASE 0x00000000 - -/* Override the default values for the following DEFAULT */ -#define PCI_CONFIG_ADDR 0xfec00000 /* 0xcf8 */ -#define PCI_CONFIG_DATA 0xfee00000 /* 0xcfc */ - -/* - * EP1A configuration Registers. - * Note: All addresses assume flash boot. - */ - -#define EQUIPMENT_PRESENT_REGISTER1 ((volatile unsigned char *)0xffa00000) -#define EQUIPMENT_PRESENT_REGISTER2 ((volatile unsigned char *)0xffa00008) -#define BOARD_REVISION_REGISTER1 ((volatile unsigned char *)0xffa00010) -#define BOARD_REVISION_REGISTER2 ((volatile unsigned char *)0xffa00018) -#define GENERAL_REGISTER1 ((volatile unsigned char *)0xffa00020) -#define GENERAL_REGISTER2 ((volatile unsigned char *)0xffa00028) -#define WATCHDOG_TRIGGER ((volatile unsigned char *)0xffa00030) - -/* EQUIPMENT_PRESENT_REGISTER1 */ -#define BANK_MEMORY_SIZE_128MB 0x20 -#define BANK_MEMORY_SIZE_64MB 0x10 -#define ECC_ENABLED 0x04 - -/* EQUIPMENT-PRESENT_REGISTER2 */ -#define PLL_CFG_MASK 0xf8 -#define MHZ_33_66_200 0x70 /* PCI MEM CPU Frequency */ -#define MHZ_33_100_200 0x80 /* PCI MEM CPU Frequency */ -#define MHZ_33_66_266 0xb0 /* PCI MEM CPU Frequency */ -#define MHZ_33_66_333 0x50 /* PCI MEM CPU Frequency */ -#define MHZ_33_100_333 0x08 /* PCI MEM CPU Frequency */ -#define MHZ_33_100_350 0x78 /* PCI MEM CPU Frequency */ - -#define PMC_SLOT1_PRESENT 0x02 -#define PMC_SLOT2_PRESENT 0x01 - -/* BOARD_REVISION_REGISTER1 */ -#define ARTWORK_REVISION_MASK 0xf0 -#define BUILD_REVISION_MASK 0x0f - -/* BOARD_REVISION_REGISTER2 */ -#define HARDWARE_ID_MASK 0xe0 -#define HARDWARE_ID_PPC5_EP1A 0xe0 -#define HARDWARE_ID_EP1B 0xc0 - -/* GENERAL_REGISTER1 */ -#define DISABLE_WATCHDOG 0x80 -#define DISABLE_RESET_SWITCH 0x40 -#define DISABLE_USER_FLASH 0x20 -#define DISABLE_BOOT_FLASH 0x10 -#define LED4_OFF 0x08 -#define LED3_OFF 0x04 -#define LED2_OFF 0x02 -#define LED1_OFF 0x01 - - -/* GENERAL_REGISTER2 */ -#define BSP_FLASH_VPP_ENABLE 0x01 -#define BSP_FLASH_PAGE_MASK 0x38 -#define BSP_FLASH_PAGE_SHIFT 0x03 -#define BSP_BIT_SLOWSTART 0x04 -#define BSP_OFFLINE 0x02 -#define BSP_SYSFAIL 0x01 - -/* WATCHDOG_TRIGGER */ -#define BSP_FLASH_BASE 0xff000000 -#define BSP_VME_A16_BASE 0x9fff0000 -#define BSP_VME_A24_BASE 0x9f000000 - -/* - * address definitions for several devices - * - */ -#define UART_OFFSET_1_8245 (0x04500) -#define UART_OFFSET_2_8245 (0x04600) -#define UART_BASE_COM1 0xff800000 -#define UART_BASE_COM2 0xff800040 - -#include <bsp/openpic.h> - -/* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start - * assume that open pic specifies this pad but not mentioned in - * 8245 docs. - * This is an offset from EUMBBAR - */ -#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 - -/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver - * to implement VME IRQ priorities in software. - * Note that this requires support by the interrupt controller - * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c) - * and the BSP-specific universe initialization/configuration - * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c) - * - * ********* IMPORTANT NOTE ******** - * When deriving from this file (new BSPs) - * DO NOT define "BSP_PIC_DO_EOI" if you don't know what - * you are doing i.e., w/o implementing the required pieces - * mentioned above. - * ********* IMPORTANT NOTE ******** - */ -#define BSP_PIC_DO_EOI openpic_eoi(0) - - -#ifndef ASM -#define outport_byte(port,value) outb(value,port) -#define outport_word(port,value) outw(value,port) -#define outport_long(port,value) outl(value,port) - -#define inport_byte(port,value) (value = inb(port)) -#define inport_word(port,value) (value = inw(port)) -#define inport_long(port,value) (value = inl(port)) - -/* - * EUMMBAR - */ -extern unsigned int EUMBBAR; - -/* - * Total memory - */ -extern unsigned int BSP_mem_size; - -/* - * PCI Bus Frequency - */ -extern unsigned int BSP_bus_frequency; - -/* - * processor clock frequency - */ -extern unsigned int BSP_processor_frequency; - -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; - -#define BSP_Convert_decrementer( _value ) \ - ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) - -#define Processor_Synchronize() \ - __asm__ (" eieio ") - -extern void BSP_panic(char *s); -extern int BSP_disconnect_clock_handler (void); -extern int BSP_connect_clock_handler (void); - -/* - * FLASH - */ -int BSP_FLASH_Enable_writes( uint32_t area ); -int BSP_FLASH_Disable_writes( uint32_t area ); -void BSP_FLASH_set_page( uint8_t page ); - -#define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area ) -#define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area ) -#define BSP_FLASH_SET_PAGE(_page) BSP_FLASH_set_page( _page ) - -/* clear hostbridge errors - * - * enableMCP: whether to enable MCP checkstop / machine check interrupts - * on the hostbridge and in HID0. - * - * NOTE: HID0 and MEREN are left alone if this flag is 0 - * - * quiet : be silent - * - * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if - * there were no errors - */ -extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); - -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/ep1a/include/tm27.h b/c/src/lib/libbsp/powerpc/ep1a/include/tm27.h deleted file mode 100644 index 8f819a5d5c..0000000000 --- a/c/src/lib/libbsp/powerpc/ep1a/include/tm27.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * @file - * @ingroup powerpc_ep1a - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/irq.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -void nullFunc() {} - -static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, - 0, - (rtems_irq_enable)nullFunc, - (rtems_irq_disable)nullFunc, - (rtems_irq_is_enabled) nullFunc}; -void Install_tm27_vector(void (*_handler)()) -{ - clockIrqData.hdl = _handler; - if (!BSP_install_rtems_irq_handler (&clockIrqData)) { - printk("Error installing clock interrupt handler!\n"); - rtems_fatal_error_occurred(1); - } -} - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 8; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - - -#define Clear_tm27_intr() \ - do { \ - uint32_t _clicks = 0xffffffff; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - uint32_t _msr = 0; \ - _ISR_Set_level( 0 ); \ - __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - _msr |= 0x8002; \ - __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - } while (0) -#endif diff --git a/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h deleted file mode 100644 index 1a57610133..0000000000 --- a/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h +++ /dev/null @@ -1,113 +0,0 @@ -#ifndef RTEMS_BSP_VME_CONFIG_H -#define RTEMS_BSP_VME_CONFIG_H - -/* BSP specific address space configuration parameters */ - -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 2002, - * Stanford Linear Accelerator Center, Stanford University. - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ -/* - * The BSP maps VME address ranges into - * one BAT. - * NOTE: the BSP (startup/bspstart.c) uses - * hardcoded window lengths that match this - * layout: - * - * BSP_VME_BAT_IDX defines - * which BAT to use for mapping the VME bus. - * If this is undefined, no extra BAT will be - * configured and VME has to share the available - * PCI address space with PCI devices. - */ -#undef BSP_VME_BAT_IDX - -#define _VME_A32_WIN0_ON_PCI 0x90000000 -#define _VME_A24_ON_PCI 0x9f000000 -#define _VME_A16_ON_PCI 0x9fff0000 - -/* start of the A32 window on the VME bus - * TODO: this should perhaps be a configuration option - */ -#define _VME_A32_WIN0_ON_VME 0x20000000 - -/* if _VME_DRAM_OFFSET is defined, the BSP - * will map our RAM onto the VME bus, starting - * at _VME_DRAM_OFFSET - */ -#undef _VME_DRAM_OFFSET -#define _VME_DRAM_OFFSET 0xc0000000 -#define _VME_DRAM_32_OFFSET1 0x20000000 -#define _VME_DRAM_32_OFFSET2 0x20b00000 -#define _VME_DRAM_24_OFFSET1 0x00000000 -#define _VME_DRAM_24_OFFSET2 0x00100000 -#define _VME_DRAM_16_OFFSET1 0x00000000 -#define _VME_DRAM_16_OFFSET2 0x00008000 - -#define _VME_A24_SIZE 0x00100000 -#define _VME_A16_SIZE 0x00008000 - -#undef _VME_CSR_ON_PCI - -/* Tell the interrupt manager that the universe driver - * already called openpic_eoi() and that this step hence - * must be omitted. - */ - -#define BSP_PCI_VME_DRIVER_DOES_EOI - -/* don't reference vmeUniverse0PciIrqLine directly here - leave it up to - * bspstart() to set BSP_vme_bridge_irq. That way, we can generate variants - * of the BSP with / without the universe driver... - */ -extern int _BSP_vme_bridge_irq; - -extern int BSP_VMEInit(void); -extern int BSP_VMEIrqMgrInstall(void); - -#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ - do { \ - err = vmeUniverseInstallIrqMgr(0,5,1,6); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h b/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h deleted file mode 100644 index 66d8364671..0000000000 --- a/c/src/lib/libbsp/powerpc/gen5200/include/bsp.h +++ /dev/null @@ -1,269 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MPC5200 BSP | -+-----------------------------------------------------------------+ -| Partially based on the code references which are named below. | -| Adaptions, modifications, enhancements and any recent parts of | -| the code are: | -| Copyright (c) 2005 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains board specific definitions | -\*===============================================================*/ - -#ifndef LIBBSP_POWERPC_GEN5200_BSP_H -#define LIBBSP_POWERPC_GEN5200_BSP_H - -#include <bspopts.h> - -#include <libcpu/powerpc-utility.h> - -/* - * Some symbols defined in the linker command file. - */ - -LINKER_SYMBOL(bsp_ram_start); -LINKER_SYMBOL(bsp_ram_end); -LINKER_SYMBOL(bsp_ram_size); - -LINKER_SYMBOL(bsp_rom_start); -LINKER_SYMBOL(bsp_rom_end); -LINKER_SYMBOL(bsp_rom_size); - -LINKER_SYMBOL(bsp_dpram_start); -LINKER_SYMBOL(bsp_dpram_end); -LINKER_SYMBOL(bsp_dpram_size); - -LINKER_SYMBOL(bsp_section_text_start); -LINKER_SYMBOL(bsp_section_text_end); -LINKER_SYMBOL(bsp_section_text_size); - -LINKER_SYMBOL(bsp_section_data_start); -LINKER_SYMBOL(bsp_section_data_end); -LINKER_SYMBOL(bsp_section_data_size); - -LINKER_SYMBOL(bsp_section_bss_start); -LINKER_SYMBOL(bsp_section_bss_end); -LINKER_SYMBOL(bsp_section_bss_size); - -LINKER_SYMBOL(bsp_interrupt_stack_start); -LINKER_SYMBOL(bsp_interrupt_stack_end); -LINKER_SYMBOL(bsp_interrupt_stack_size); - -LINKER_SYMBOL(bsp_work_area_start); - -LINKER_SYMBOL(MBAR); - -/* Provide legacy defines */ - -#ifdef MPC5200_BOARD_PM520_ZE30 -#define PM520_ZE30 -#endif - -#ifdef MPC5200_BOARD_PM520_CR825 -#define PM520_CR825 -#endif - -#ifdef MPC5200_BOARD_ICECUBE -#define icecube -#endif - -#ifdef MPC5200_BOARD_BRS5L -#define BRS5L -#endif - -/* - * distinguish board characteristics - */ -/* - * for PM520 mdule on a ZE30 carrier - */ -#if defined(MPC5200_BOARD_PM520_ZE30) -#define PM520 -#endif -/* - * for PM520 mdule on a CR825 carrier - */ -#if defined(MPC5200_BOARD_PM520_CR825) -#define PM520 -#endif - -#if !defined(HAS_UBOOT) - /* we need the low level initialization in start.S*/ - #define NEED_LOW_LEVEL_INIT -#endif - -#if defined(MPC5200_BOARD_BRS5L) -/* - * IMD Custom Board BRS5L - */ - -#define HAS_NVRAM_93CXX - -#elif defined(MPC5200_BOARD_BRS6L) - #define MPC5200_BRS6L_FPGA_BEGIN 0x800000 - #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024) - #define MPC5200_BRS6L_FPGA_END \ - (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE) - - #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000 - #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024) - #define MPC5200_BRS6L_MRAM_END \ - (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE) -#elif defined (PM520) - -/* Nothing special */ - -#elif defined (MPC5200_BOARD_ICECUBE) -/* - * Codename: IceCube - * Compatible Boards: - * Freescape MPC5200LITE - * Embedded Planet EP5200 - */ - -#elif defined (MPC5200_BOARD_DP2) - -/* Nothing special */ - -#else -#error "board type not defined" -#endif - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/rtc.h> -#include <i2cdrv.h> -#include <bsp/irq.h> -#include <bsp/vectors.h> -#include <bsp/u-boot.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc5200_fec_driver_attach_detach - -/* miscellaneous stuff assumed to exist */ - -/* - * We need to decide how much memory will be non-cacheable. This - * will mainly be memory that will be used in DMA (network and serial - * buffers). - */ -/* -#define NOCACHE_MEM_SIZE 512*1024 -*/ - -/* - * Device Driver Table Entries - */ - -#ifdef HAS_NVRAM_93CXX -#define NVRAM_DRIVER_TABLE_ENTRY \ - { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \ - nvram_driver_read, nvram_driver_write, NULL } -#endif - -/* - * indicate, that BSP has IDE driver - */ -#define RTEMS_BSP_HAS_IDE_DRIVER - -/* functions */ - -/* #define SHOW_MORE_INIT_SETTINGS 1 */ - -/* ata modes */ -/* #undef ATA_USE_INT */ -#define ATA_USE_INT - -/* clock settings */ -#if defined(HAS_UBOOT) -#define IPB_CLOCK (bsp_uboot_board_info.bi_ipbfreq) -#define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq) -#define G2_CLOCK (bsp_uboot_board_info.bi_intfreq) -#elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L) -#define IPB_CLOCK 66000000 /* 66 MHz */ -#define XLB_CLOCK 132000000 /* 132 MHz */ -#define G2_CLOCK 396000000 /* 396 MHz */ -#else -#define IPB_CLOCK 33000000 /* 33 MHz */ -#define XLB_CLOCK 66000000 /* 66 MHz */ -#define G2_CLOCK 231000000 /* 231 MHz */ -#endif - -#if defined(HAS_UBOOT) -#define GEN5200_CONSOLE_BAUD (bsp_uboot_board_info.bi_baudrate) -#else -#define GEN5200_CONSOLE_BAUD 115200 -#endif - -/* - * Convert decrement value to tenths of microsecnds (used by - * shared timer driver). - * - * + CPU has a XLB_CLOCK bus, - * + There are 4 bus cycles per click - * + We return value in 1/10 microsecond units. - * Modified following equation to integer equation to remove - * floating point math. - * (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0)) - */ - -#define BSP_Convert_decrementer( _value ) \ - (int) (((_value) * 4000) / (XLB_CLOCK/10000)) - -/* slicetimer settings */ -#define USE_SLICETIMER_0 TRUE -#define USE_SLICETIMER_1 FALSE - -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* BSP specific IRQ Benchmarking support */ -void BSP_IRQ_Benchmarking_Reset(void); -void BSP_IRQ_Benchmarking_Report(void); - -#if defined(HAS_UBOOT) - /* Routine to obtain U-Boot environment variables */ - const char *bsp_uboot_getenv( - const char *name - ); -#endif - -void cpu_init(void); - -int mpc5200_eth_mii_read( - int phyAddr, - void *arg, - unsigned regAddr, - uint32_t *retVal -); - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* GEN5200 */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/i2c.h b/c/src/lib/libbsp/powerpc/gen5200/include/i2c.h deleted file mode 100644 index e5d7d472dd..0000000000 --- a/c/src/lib/libbsp/powerpc/gen5200/include/i2c.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Generic I2C bus interface for RTEMS - * - * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __RTEMS__I2C_H__ -#define __RTEMS__I2C_H__ - -#include <rtems.h> -#include <bsp.h> -/* This header file define the generic interface to i2c buses available in - * system. This interface may be used by user applications or i2c-device - * drivers (like RTC, NVRAM, etc). - * - * Functions i2c_initialize and i2c_transfer declared in this header usually - * implemented in particular board support package. Usually this - * implementation is a simple wrapper or multiplexor to I2C controller - * driver which is available in system. It may be generic "software - * controller" I2C driver which control SDA and SCL signals directly (if SDA - * and SCL is general-purpose I/O pins), or driver for hardware I2C - * controller (standalone or integrated with processors: MBus controller in - * ColdFire processors, I2C controller in PowerQUICC and so on). - * - * i2c_transfer is a very generic low-level function. Higher-level function - * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too. - */ - -/* I2C Bus Number type */ -typedef uint32_t i2c_bus_number; - -/* I2C device address */ -typedef uint16_t i2c_address; - -/* I2C error codes generated during message transfer */ -typedef enum i2c_message_status { - I2C_SUCCESSFUL = 0, - I2C_TIMEOUT, - I2C_NO_DEVICE, - I2C_ARBITRATION_LOST, - I2C_NO_ACKNOWLEDGE, - I2C_NO_DATA, - I2C_RESOURCE_NOT_AVAILABLE -} i2c_message_status; - -/* I2C Message */ -typedef struct i2c_message { - i2c_address addr; /* I2C slave device address */ - uint16_t flags; /* message flags (see below) */ - i2c_message_status status; /* message transfer status code */ - uint16_t len; /* Number of bytes to read or write */ - uint8_t *buf; /* pointer to data array */ -} i2c_message; - -/* I2C message flag */ -#define I2C_MSG_ADDR_10 (0x01) /* 10-bit address */ -#define I2C_MSG_WR (0x02) /* transfer direction for this message - from master to slave */ -#define I2C_MSG_ERRSKIP (0x04) /* Skip message if last transfered message - is failed */ -/* Type for function which is called when transfer over I2C bus is finished */ -typedef void (*i2c_transfer_done) (void * arg); - -/* i2c_initialize -- - * I2C driver initialization. This function usually called on device - * driver initialization state, before initialization task. All I2C - * buses are initialized; reasonable slow data transfer rate is - * selected for each bus. - * - * PARAMETERS: - * major - I2C device major number - * minor - I2C device minor number - * arg - RTEMS driver initialization argument - * - * RETURNS: - * RTEMS status code - */ -rtems_device_driver -i2c_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg); - -/* i2c_select_clock_rate -- - * select I2C bus clock rate for specified bus. Some bus controller do not - * allow to select arbitrary clock rate; in this case nearest possible - * slower clock rate is selected. - * - * PARAMETERS: - * bus - I2C bus number - * bps - data transfer rate for this bytes in bits per second - * - * RETURNS: - * RTEMS_SUCCESSFUL, if operation performed successfully, - * RTEMS_INVALID_NUMBER, if wrong bus number is specified, - * RTEMS_UNSATISFIED, if bus do not support data transfer rate selection - * or specified data transfer rate could not be used. - */ -rtems_status_code -i2c_select_clock_rate(i2c_bus_number bus, int bps); - -/* i2c_transfer -- - * Initiate multiple-messages transfer over specified I2C bus or - * put request into queue if bus or some other resource is busy. (This - * is non-blocking function). - * - * PARAMETERS: - * bus - I2C bus number - * nmsg - number of messages - * msg - pointer to messages array - * done - function which is called when transfer is finished - * done_arg_ptr - arbitrary argument ptr passed to done funciton - * - * RETURNS: - * RTEMS_SUCCESSFUL if transfer initiated successfully, or error - * code if something failed. - */ -rtems_status_code -i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg, - i2c_transfer_done done, void *done_arg); - -/* i2c_transfer_wait -- - * Initiate I2C bus transfer and block until this transfer will be - * finished. This function wait the semaphore if system in - * SYSTEM_STATE_UP state, or poll done flag in other states. - * - * PARAMETERS: - * bus - I2C bus number - * msg - pointer to transfer messages array - * nmsg - number of messages in transfer - * - * RETURNS: - * I2C_SUCCESSFUL, if tranfer finished successfully, - * I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed, - * value of status field of first error-finished message in transfer, - * if something wrong. - */ -i2c_message_status -i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg); - -/* i2c_poll -- - * Poll I2C bus controller for events and hanle it. This function is - * used when I2C driver operates in poll-driven mode. - * - * PARAMETERS: - * bus - bus number to be polled - * - * RETURNS: - * none - */ -void -i2c_poll(i2c_bus_number bus); - -/* i2c_write -- - * Send single message over specified I2C bus to addressed device and - * wait while transfer is finished. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * buf - data to be sent to device - * size - data buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size); - -/* i2c_wrbyte -- - * Send single one-byte long message over specified I2C bus to - * addressed device and wait while transfer is finished. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * cmd - byte message to be sent to device - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t cmd); - -/* i2c_read -- - * receive single message over specified I2C bus from addressed device. - * This call will wait while transfer is finished. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * buf - buffer for received message - * size - receive buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size); - -/* i2c_wrrd -- - * Send message over I2C bus to specified device and receive message - * from the same device during single transfer. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * bufw - data to be sent to device - * sizew - send data buffer size - * bufr - buffer for received message - * sizer - receive buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew, - void *bufr, int sizer); - -/* i2c_wbrd -- - * Send one-byte message over I2C bus to specified device and receive - * message from the same device during single transfer. - * - * PARAMETERS: - * bus - I2C bus number - * addr - address of I2C device - * cmd - one-byte message to be sent over I2C bus - * bufr - buffer for received message - * sizer - receive buffer size - * - * RETURNS: - * transfer status - */ -i2c_message_status -i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t cmd, - void *bufr, int sizer); - -#endif diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/irq.h b/c/src/lib/libbsp/powerpc/gen5200/include/irq.h deleted file mode 100644 index 5a0b3bd29e..0000000000 --- a/c/src/lib/libbsp/powerpc/gen5200/include/irq.h +++ /dev/null @@ -1,212 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MPC5200 BSP | -+-----------------------------------------------------------------+ -| Partially based on the code references which are named below. | -| Adaptions, modifications, enhancements and any recent parts of | -| the code are: | -| Copyright (c) 2005, 2010 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains declarations for the irq controller handler | -\*===============================================================*/ -/***********************************************************************/ -/* */ -/* Module: irq.h */ -/* Date: 07/17/2003 */ -/* Purpose: RTEMS MPC5x00 CPU interrupt header file */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Description: This include file describe the data structure and */ -/* the functions implemented by rtems to write */ -/* interrupt handlers. */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Code */ -/* References: MPC8260ads CPU interrupt header file */ -/* Module: irq.h */ -/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */ -/* Version 1.1 */ -/* Date: 10/10/2002 */ -/* */ -/* Author(s) / Copyright(s): */ -/* */ -/* Copyright (C) 1999 valette@crf.canon.fr */ -/* */ -/* This code is heavilly inspired by the public specification of */ -/* STREAM V2 that can be found at: */ -/* */ -/* <http://www.chorus.com/Documentation/index.html> by following */ -/* the STREAM API Specification Document link. */ -/* */ -/* Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> */ -/* Surrey Satellite Technology Limited */ -/* The interrupt handling on the mpc8260 seems quite different from */ -/* the 860 (I don't know the 860 well). Although some interrupts */ -/* are routed via the CPM irq and some are direct to the SIU they */ -/* all appear logically the same.Therefore I removed the distinction */ -/* between SIU and CPM interrupts. */ -/* */ -/* The license and distribution terms for this file may be */ -/* found in the file LICENSE in this distribution or at */ -/* http://www.rtems.org/license/LICENSE. */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Partially based on the code references which are named above. */ -/* Adaptions, modifications, enhancements and any recent parts of */ -/* the code are under the right of */ -/* */ -/* IPR Engineering, Dachauer Straße 38, D-80335 München */ -/* Copyright(C) 2003 */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* IPR Engineering makes no representation or warranties with */ -/* respect to the performance of this computer program, and */ -/* specifically disclaims any responsibility for any damages, */ -/* special or consequential, connected with the use of this program. */ -/* */ -/*---------------------------------------------------------------------*/ -/* */ -/* Version history: 1.0 */ -/* */ -/***********************************************************************/ - -#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H -#define LIBBSP_POWERPC_GEN5200_IRQ_H - -#define PMCE_CE_SHADOW (1U << (31 - 31)) -#define PMCE_CSE_STICKY (1U << (31 - 21)) -#define PMCE_MSE_STICKY (1U << (31 - 10)) -#define PMCE_PSE_STICKY (1U << (31 - 2)) -#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U) -#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU) -#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU) - -/* - * Peripheral IRQ handlers related definitions - */ -#define BSP_PER_IRQ_NUMBER 22 -#define BSP_PER_IRQ_LOWEST_OFFSET 0 -#define BSP_PER_IRQ_MAX_OFFSET \ - (BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */ -/* - * Main IRQ handlers related definitions - */ -#define BSP_MAIN_IRQ_NUMBER 17 -#define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */ -#define BSP_MAIN_IRQ_MAX_OFFSET \ - (BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */ -/* - * Critical IRQ handlers related definitions - */ -#define BSP_CRIT_IRQ_NUMBER 4 -#define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */ -#define BSP_CRIT_IRQ_MAX_OFFSET \ - (BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */ -/* - * Summary of SIU interrupts - */ -#define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */ -#define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ -#define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */ -/* - * Processor IRQ handlers related definitions - */ -#define BSP_PROCESSOR_IRQ_NUMBER 3 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */ -#define BSP_PROCESSOR_IRQ_MAX_OFFSET \ - (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */ -/* - * Summary - */ -#define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */ -#define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */ -#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */ - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -/* - * index table for the module specific handlers, a few entries are only placeholders - */ -typedef enum { - BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0, - BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1, - BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2, - BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3, - BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4, - BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5, - BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6, - BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7, - BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8, - BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9, - BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10, - BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11, - BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12, - BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13, - BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14, - BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15, - BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16, - BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17, - BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18, - BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19, - BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20, - BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21, - - /* SL_TIMER1 -- handler entry only used in case of SMI */ - BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0, - BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, - BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2, - BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3, - /* LO_INT -- handler entry never used (only placeholder) */ - BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4, - BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5, - BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6, - BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7, - BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8, - BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9, - BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10, - BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1, - BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12, - BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13, - BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14, - BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15, - BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16, - - BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0, - BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1, - /* HI_INT -- handler entry never used (only placeholder) */ - BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2, - BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3, - - BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, - BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, - BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 -} rtems_irq_symbolic_name; - -#define BSP_CRIT_IRQ_PRIO_LEVELS 4 -#define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6 - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -#endif - -#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/tm27.h b/c/src/lib/libbsp/powerpc/gen5200/include/tm27.h deleted file mode 100644 index ff43cc9ab6..0000000000 --- a/c/src/lib/libbsp/powerpc/gen5200/include/tm27.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * @file - * @ingroup powerpc_gen5200 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/fatal.h> -#include <bsp/irq.h> - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -void nullFunc() {} - -static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, - 0, - (rtems_irq_enable)nullFunc, - (rtems_irq_disable)nullFunc, - (rtems_irq_is_enabled) nullFunc}; -void Install_tm27_vector(void (*_handler)()) -{ - clockIrqData.hdl = _handler; - if (!BSP_install_rtems_irq_handler (&clockIrqData)) { - printk("Error installing clock interrupt handler!\n"); - bsp_fatal(MPC5200_FATAL_TM27_IRQ_INSTALL); - } -} - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 8; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Clear_tm27_intr() \ - do { \ - uint32_t _clicks = 0xffffffff; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - uint32_t _msr = 0; \ - _ISR_Set_level( 0 ); \ - __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - _msr |= 0x8002; \ - __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/gen5200/include/u-boot-config.h b/c/src/lib/libbsp/powerpc/gen5200/include/u-boot-config.h deleted file mode 100644 index 2fee83bce9..0000000000 --- a/c/src/lib/libbsp/powerpc/gen5200/include/u-boot-config.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H -#define LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H - -#define CONFIG_MPC5xxx - -#endif /* LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h b/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h deleted file mode 100644 index 1e1243bf4c..0000000000 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h +++ /dev/null @@ -1,165 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MPC83xx BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains board specific definitions | -\*===============================================================*/ - - -#ifndef LIBBSP_POWERPC_GEN83XX_BSP_H -#define LIBBSP_POWERPC_GEN83XX_BSP_H - -#define BSP_FEATURE_IRQ_EXTENSION - -#include <bspopts.h> - -#include <libcpu/powerpc-utility.h> - -#include <bsp/hwreg_vals.h> - -/* - * Some symbols defined in the linker command file. - */ - -LINKER_SYMBOL(bsp_ram_start); -LINKER_SYMBOL(bsp_ram_end); -LINKER_SYMBOL(bsp_ram_size); - -LINKER_SYMBOL(bsp_rom_start); -LINKER_SYMBOL(bsp_rom_end); -LINKER_SYMBOL(bsp_rom_size); - -LINKER_SYMBOL(bsp_section_text_start); -LINKER_SYMBOL(bsp_section_text_end); -LINKER_SYMBOL(bsp_section_text_size); - -LINKER_SYMBOL(bsp_section_data_start); -LINKER_SYMBOL(bsp_section_data_end); -LINKER_SYMBOL(bsp_section_data_size); - -LINKER_SYMBOL(bsp_section_bss_start); -LINKER_SYMBOL(bsp_section_bss_end); -LINKER_SYMBOL(bsp_section_bss_size); - -LINKER_SYMBOL(bsp_interrupt_stack_start); -LINKER_SYMBOL(bsp_interrupt_stack_end); -LINKER_SYMBOL(bsp_interrupt_stack_size); - -LINKER_SYMBOL(bsp_work_area_start); - -LINKER_SYMBOL(IMMRBAR); - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <bsp/vectors.h> -#include <bsp/irq.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * indicate, that BSP has no IDE driver - */ -#undef RTEMS_BSP_HAS_IDE_DRIVER - -/* misc macros */ -#define BSP_ARRAY_CNT(arr) (sizeof(arr)/sizeof(arr[0])) - -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* functions */ -rtems_status_code bsp_register_i2c(void); -rtems_status_code bsp_register_spi(void); - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int BSP_tsec_attach(struct rtems_bsdnet_ifconfig *config,int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach - -#ifdef MPC83XX_BOARD_MPC8313ERDB - #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec2" - #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec1" -#else - #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" - #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" -#endif - -#if defined(MPC83XX_BOARD_MPC8349EAMDS) -/* - * i2c EEPROM device name - */ -#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" -#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" - -/* - * SPI Flash device name - */ -#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash" -#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash" -#endif /* defined(MPC83XX_BOARD_MPC8349EAMDS) */ - -#if defined(MPC83XX_BOARD_HSC_CM01) -/* - * i2c EEPROM device name - */ -#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" -#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" - -/* - * SPI FRAM device name - */ -#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram" -#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram" -#endif /* defined(MPC83XX_BOARD_HSC_CM01) */ - -extern unsigned int BSP_bus_frequency; - -extern uint32_t bsp_clicks_per_usec; - -/* - * Convert decrementer value to tenths of microseconds (used by shared timer - * driver). - */ -#define BSP_Convert_decrementer( _value ) \ - ((int) (((_value) * 10) / bsp_clicks_per_usec)) - -void mpc83xx_zero_4( void *dest, size_t n); - -void cpu_init( void); - -void bsp_restart(void *addr); - -#if defined(HAS_UBOOT) - /* Routine to obtain U-Boot environment variables */ - const char *bsp_uboot_getenv( - const char *name - ); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* GEN83xx */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/irq.h b/c/src/lib/libbsp/powerpc/gen83xx/include/irq.h deleted file mode 100644 index dc084ed2a2..0000000000 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/irq.h +++ /dev/null @@ -1,184 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS generic MPC83xx BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2007, 2010 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file declares constants of the interrupt controller | -\*===============================================================*/ - - -#ifndef GEN83xx_IRQ_IRQ_H -#define GEN83xx_IRQ_IRQ_H - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#include <bspopts.h> - -/* - * the following definitions specify the indices used - * to interface the interrupt handler API - */ - -/* - * Peripheral IRQ handlers related definitions - */ -#define BSP_IPIC_PER_IRQ_NUMBER 128 -#define BSP_IPIC_IRQ_LOWEST_OFFSET 0 -#define BSP_IPIC_IRQ_MAX_OFFSET (BSP_IPIC_IRQ_LOWEST_OFFSET\ - +BSP_IPIC_PER_IRQ_NUMBER-1) - -#define BSP_IS_IPIC_IRQ(irqnum) \ - (((irqnum) >= BSP_IPIC_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_IPIC_IRQ_MAX_OFFSET)) -/* - * Processor IRQ handlers related definitions - */ -#define BSP_PROCESSOR_IRQ_NUMBER 1 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_IPIC_IRQ_MAX_OFFSET+1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ - +BSP_PROCESSOR_IRQ_NUMBER-1) - -#define BSP_IS_PROCESSOR_IRQ(irqnum) \ - (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) -#define BSP_LOWEST_OFFSET BSP_IPIC_IRQ_LOWEST_OFFSET -#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET - -#define BSP_IS_VALID_IRQ(irqnum) \ - (BSP_IS_PROCESSOR_IRQ(irqnum) \ - || BSP_IS_IPIC_IRQ(irqnum)) - -#ifndef ASM -#ifdef __cplusplus -extern "C" { -#endif - -/* - * index table for the module specific handlers, a few entries are only placeholders - */ - typedef enum { - BSP_IPIC_IRQ_FIRST = BSP_IPIC_IRQ_LOWEST_OFFSET, - BSP_IPIC_IRQ_ERROR = BSP_IPIC_IRQ_LOWEST_OFFSET + 0, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_DMA1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 3, - BSP_IPIC_IRQ_UART = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, - BSP_IPIC_IRQ_FLEXCAN = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, -#else - BSP_IPIC_IRQ_UART1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 9, - BSP_IPIC_IRQ_UART2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 10, - BSP_IPIC_IRQ_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 11, -#endif - BSP_IPIC_IRQ_I2C1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 14, - BSP_IPIC_IRQ_I2C2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 15, - BSP_IPIC_IRQ_SPI = BSP_IPIC_IRQ_LOWEST_OFFSET + 16, - BSP_IPIC_IRQ_IRQ1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 17, - BSP_IPIC_IRQ_IRQ2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 18, - BSP_IPIC_IRQ_IRQ3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 19, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_QUICC_HI = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, - BSP_IPIC_IRQ_QUICC_LO = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, -#else - BSP_IPIC_IRQ_IRQ4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 20, - BSP_IPIC_IRQ_IRQ5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 21, - BSP_IPIC_IRQ_IRQ6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 22, - BSP_IPIC_IRQ_IRQ7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 23, - BSP_IPIC_IRQ_TSEC1_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 32, - BSP_IPIC_IRQ_TSEC1_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 33, - BSP_IPIC_IRQ_TSEC1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 34, - BSP_IPIC_IRQ_TSEC2_TX = BSP_IPIC_IRQ_LOWEST_OFFSET + 35, - BSP_IPIC_IRQ_TSEC2_RX = BSP_IPIC_IRQ_LOWEST_OFFSET + 36, - BSP_IPIC_IRQ_TSEC2_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 37, -#endif - BSP_IPIC_IRQ_USB_DR = BSP_IPIC_IRQ_LOWEST_OFFSET + 38, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_ESDHC = BSP_IPIC_IRQ_LOWEST_OFFSET + 42, -#else - BSP_IPIC_IRQ_USB_MPH = BSP_IPIC_IRQ_LOWEST_OFFSET + 39, -#endif - BSP_IPIC_IRQ_IRQ0 = BSP_IPIC_IRQ_LOWEST_OFFSET + 48, - BSP_IPIC_IRQ_RTC_SEC = BSP_IPIC_IRQ_LOWEST_OFFSET + 64, - BSP_IPIC_IRQ_PIT = BSP_IPIC_IRQ_LOWEST_OFFSET + 65, - BSP_IPIC_IRQ_PCI1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 66, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_MSIR1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, -#else - BSP_IPIC_IRQ_PCI2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 67, -#endif - BSP_IPIC_IRQ_RTC_ALR = BSP_IPIC_IRQ_LOWEST_OFFSET + 68, - BSP_IPIC_IRQ_MU = BSP_IPIC_IRQ_LOWEST_OFFSET + 69, - BSP_IPIC_IRQ_SBA = BSP_IPIC_IRQ_LOWEST_OFFSET + 70, - BSP_IPIC_IRQ_DMA = BSP_IPIC_IRQ_LOWEST_OFFSET + 71, - BSP_IPIC_IRQ_GTM4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 72, - BSP_IPIC_IRQ_GTM8 = BSP_IPIC_IRQ_LOWEST_OFFSET + 73, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_QUICC_PORTS = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, - BSP_IPIC_IRQ_GPIO = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, -#else - BSP_IPIC_IRQ_GPIO1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 74, - BSP_IPIC_IRQ_GPIO2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 75, -#endif - BSP_IPIC_IRQ_DDR = BSP_IPIC_IRQ_LOWEST_OFFSET + 76, - BSP_IPIC_IRQ_LBC = BSP_IPIC_IRQ_LOWEST_OFFSET + 77, - BSP_IPIC_IRQ_GTM2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 78, - BSP_IPIC_IRQ_GTM6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 79, - BSP_IPIC_IRQ_PMC = BSP_IPIC_IRQ_LOWEST_OFFSET + 80, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_MSIR2 = BSP_IPIC_IRQ_LOWEST_OFFSET + 81, - BSP_IPIC_IRQ_MSIR3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 82, -#else - BSP_IPIC_IRQ_GTM3 = BSP_IPIC_IRQ_LOWEST_OFFSET + 84, - BSP_IPIC_IRQ_GTM7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 85, -#endif -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_MSIR4 = BSP_IPIC_IRQ_LOWEST_OFFSET + 86, - BSP_IPIC_IRQ_MSIR5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 87, - BSP_IPIC_IRQ_MSIR6 = BSP_IPIC_IRQ_LOWEST_OFFSET + 88, - BSP_IPIC_IRQ_MSIR7 = BSP_IPIC_IRQ_LOWEST_OFFSET + 89, -#endif - BSP_IPIC_IRQ_GTM1 = BSP_IPIC_IRQ_LOWEST_OFFSET + 90, - BSP_IPIC_IRQ_GTM5 = BSP_IPIC_IRQ_LOWEST_OFFSET + 91, -#if MPC83XX_CHIP_TYPE / 10 == 830 - BSP_IPIC_IRQ_DMA1_ERR = BSP_IPIC_IRQ_LOWEST_OFFSET + 94, - BSP_IPIC_IRQ_DPTC = BSP_IPIC_IRQ_LOWEST_OFFSET + 95, -#endif - - BSP_IPIC_IRQ_LAST = BSP_IPIC_IRQ_MAX_OFFSET, - } rtems_irq_symbolic_name; - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask); - -#define MPC83XX_IPIC_INTERRUPT_NORMAL 0 - -#define MPC83XX_IPIC_INTERRUPT_SYSTEM 1 - -#define MPC83XX_IPIC_INTERRUPT_CRITICAL 2 - -rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type); - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ - -#endif /* GEN83XX_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/tm27.h b/c/src/lib/libbsp/powerpc/gen83xx/include/tm27.h deleted file mode 100644 index 22787473a5..0000000000 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/tm27.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file - * - * @brief Support file for Timer Test 27. - */ - -/* - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 - #error "This is an RTEMS internal file you must not include directly." -#endif /* _RTEMS_TMTEST27 */ - -#ifndef TMTESTS_TM27_H -#define TMTESTS_TM27_H - -#include <libcpu/powerpc-utility.h> -#include <bsp/vectors.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -static void (*tm27_interrupt_handler)(rtems_vector_number); - -static int tm27_exception_handler( BSP_Exception_frame *frame, unsigned number) -{ - (*tm27_interrupt_handler)( 0); - - return 0; -} - -void Install_tm27_vector( void (*handler)(rtems_vector_number)) -{ - int rv = 0; - - tm27_interrupt_handler = handler; - - rv = ppc_exc_set_handler( ASM_DEC_VECTOR, tm27_exception_handler); - if (rv < 0) { - printk( "Error installing clock interrupt handler!\n"); - } -} - -#define Cause_tm27_intr() \ - ppc_set_decrementer_register( 8) - -#define Clear_tm27_intr() \ - ppc_set_decrementer_register( UINT32_MAX) - -#define Lower_tm27_intr() \ - (void) ppc_external_exceptions_enable() - -#endif /* TMTESTS_TM27_H */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/tsec-config.h b/c/src/lib/libbsp/powerpc/gen83xx/include/tsec-config.h deleted file mode 100644 index 5ec0ccbad1..0000000000 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/tsec-config.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H -#define LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define TSEC_COUNT 2 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_GEN83XX_TSEC_CONFIG_H */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/u-boot-config.h b/c/src/lib/libbsp/powerpc/gen83xx/include/u-boot-config.h deleted file mode 100644 index c2271c965b..0000000000 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/u-boot-config.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H -#define LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H - -#define CONFIG_MPC83xx -#define CONFIG_HAS_ETH1 - -#endif /* LIBBSP_POWERPC_GEN83XX_U_BOOT_CONFIG_H */ diff --git a/c/src/lib/libbsp/powerpc/haleakala/include/bsp.h b/c/src/lib/libbsp/powerpc/haleakala/include/bsp.h deleted file mode 100644 index 8bd92da5aa..0000000000 --- a/c/src/lib/libbsp/powerpc/haleakala/include/bsp.h +++ /dev/null @@ -1,91 +0,0 @@ -/* bsp.h - * - * Generic 405EX bsp.h - * derived from virtex/include/bsp.h - * by Michael Hamel ADInstruments Ltd 2008 - * - * derived from helas403/include/bsp.h: - * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp - * Author: Thomas Doerfler <td@imd.m.isar.de> - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * - */ - -#ifndef LIBBSP_POWERPC_HALEAKALA_BSP_H -#define LIBBSP_POWERPC_HALEAKALA_BSP_H - -#include <bspopts.h> - -#ifdef ASM - - - /* Definition of where to store registers in alignment handler */ - #define ALIGN_REGS 0x0140 - -#else - - #include <rtems.h> - #include <rtems/console.h> - #include <rtems/clockdrv.h> - #include <libcpu/io.h> - #include <rtems/console.h> - #include <rtems/iosupp.h> - #include <bsp/irq.h> - #include <bsp/vectors.h> - #include <bsp/default-initial-extension.h> - - #ifdef __cplusplus - extern "C" { - #endif - - /* Network Defines */ - #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" - - struct rtems_bsdnet_ifconfig; - int rtems_emac_driver_attach(struct rtems_bsdnet_ifconfig* config, int attaching); - #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_emac_driver_attach - - #define BSP_UART_IOBASE_COM1 0xEF600200 /* PPC405EX */ - #define BSP_UART_IOBASE_COM2 0xEF600300 - - #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ - - #define BSP_UART_BAUD_BASE (11059200 / 16) /* Kilauea ext clock, max speed */ - - #ifdef __cplusplus - } - #endif -#endif /* ASM */ - -#endif /* BSP_H */ diff --git a/c/src/lib/libbsp/powerpc/haleakala/include/coverhd.h b/c/src/lib/libbsp/powerpc/haleakala/include/coverhd.h deleted file mode 100644 index b3323f8085..0000000000 --- a/c/src/lib/libbsp/powerpc/haleakala/include/coverhd.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * @ingroup powerpc_haleakala - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk> - * - * Units are 100ns. - * - * These numbers are of questionable use, as they are developed by calling - * the routine many times, thus getting its entry veneer into the (small) - * cache on the 403GA. This in general is not true of the RTEMS timing - * tests, which usually call a routine only once, thus having no cache loaded - * advantage. - * - * Whether the directive times are useful after deducting the function call - * overhead is also questionable. The user is more interested generally - * in the total cost of a directive, not the cost if the procedure call - * is inlined! (In general this is not true). - * - * Andrew Bray 18/08/1995 - * - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 1 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 1 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 1 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 -#define CALLING_OVERHEAD_TASK_MODE 1 -#define CALLING_OVERHEAD_TASK_GET_NOTE 1 -#define CALLING_OVERHEAD_TASK_SET_NOTE 1 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 -#define CALLING_OVERHEAD_CLOCK_GET 4 -#define CALLING_OVERHEAD_CLOCK_SET 3 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 1 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 1 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 - -#define CALLING_OVERHEAD_EVENT_SEND 1 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 1 -#define CALLING_OVERHEAD_SIGNAL_SEND 1 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 1 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 1 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 1 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 2 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h b/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h deleted file mode 100644 index c413ec3172..0000000000 --- a/c/src/lib/libbsp/powerpc/haleakala/irq/irq.h +++ /dev/null @@ -1,166 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS Haleakala BSP | -| by Michael Hamel ADInstruments Ltd 2008 | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -\*===============================================================*/ - - -#ifndef Haleakala_IRQ_IRQ_H -#define Haleakala_IRQ_IRQ_H - -/* Implemented for us in bsp_irq_dispatch_list */ -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#include <rtems/irq.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - - /* Define UIC interrupt numbers; IRQs that cause an external interrupt that needs further decode. - These are arbitrary but it makes things easier if they match the CPU interrupt numbers */ - - /* - - #define BSP_UIC_UART0_GP (BSP_UIC_IRQ_LOWEST_OFFSET + 0) - #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) - #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) - #define BSP_UIC_ExtMaster (BSP_UIC_IRQ_LOWEST_OFFSET + 3) - #define BSP_UIC_PCI (BSP_UIC_IRQ_LOWEST_OFFSET + 4) - #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 5) - #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 6) - #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) - #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 8) - #define BSP_UIC_ENetWU (BSP_UIC_IRQ_LOWEST_OFFSET + 9) - #define BSP_UIC_MALSERR (BSP_UIC_IRQ_LOWEST_OFFSET + 10) - #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) - #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 12) - #define BSP_UIC_MALTXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 13) - #define BSP_UIC_MALRXDE (BSP_UIC_IRQ_LOWEST_OFFSET + 14) - #define BSP_UIC_ENet (BSP_UIC_IRQ_LOWEST_OFFSET + 15) - #define BSP_UIC_PCISERR (BSP_UIC_IRQ_LOWEST_OFFSET + 16) - #define BSP_UIC_ECCERR (BSP_UIC_IRQ_LOWEST_OFFSET + 17) - #define BSP_UIC_PCIPower (BSP_UIC_IRQ_LOWEST_OFFSET + 18) - #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) - #define BSP_UIC_IRQ1 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) - #define BSP_UIC_IRQ2 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) - #define BSP_UIC_IRQ3 (BSP_UIC_IRQ_LOWEST_OFFSET + 28) - #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 29) - #define BSP_UIC_IRQ5 (BSP_UIC_IRQ_LOWEST_OFFSET + 30) - #define BSP_UIC_IRQ6 (BSP_UIC_IRQ_LOWEST_OFFSET + 31) - - #define BSP_UIC_IRQ_NUMBER (32) - - */ - /* PPC405EX interrupt vectors */ - #define BSP_UIC_UART1 (BSP_UIC_IRQ_LOWEST_OFFSET + 1) - #define BSP_UIC_IIC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 2) - #define BSP_UIC_EIPPKP_READY (BSP_UIC_IRQ_LOWEST_OFFSET + 3) - #define BSP_UIC_EIPPKP_TRNG (BSP_UIC_IRQ_LOWEST_OFFSET + 4) - #define BSP_UIC_EBM (BSP_UIC_IRQ_LOWEST_OFFSET + 5) - #define BSP_UIC_OPBtoPLB (BSP_UIC_IRQ_LOWEST_OFFSET + 6) - #define BSP_UIC_IIC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 7) - #define BSP_UIC_SPI (BSP_UIC_IRQ_LOWEST_OFFSET + 8) - #define BSP_UIC_IRQ0 (BSP_UIC_IRQ_LOWEST_OFFSET + 9) - #define BSP_UIC_MALTXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 10) - #define BSP_UIC_MALRXEOB (BSP_UIC_IRQ_LOWEST_OFFSET + 11) - #define BSP_UIC_DMA0 (BSP_UIC_IRQ_LOWEST_OFFSET + 12) - #define BSP_UIC_DMA1 (BSP_UIC_IRQ_LOWEST_OFFSET + 13) - #define BSP_UIC_DMA2 (BSP_UIC_IRQ_LOWEST_OFFSET + 14) - #define BSP_UIC_DMA3 (BSP_UIC_IRQ_LOWEST_OFFSET + 15) - #define BSP_UIC_PCIe0AL (BSP_UIC_IRQ_LOWEST_OFFSET + 16) - #define BSP_UIC_PCIe0VPD (BSP_UIC_IRQ_LOWEST_OFFSET + 17) - #define BSP_UIC_PCIe0HRst (BSP_UIC_IRQ_LOWEST_OFFSET + 18) - #define BSP_UIC_EIPPKP_PKA (BSP_UIC_IRQ_LOWEST_OFFSET + 19) - #define BSP_UIC_PCIe0TCR (BSP_UIC_IRQ_LOWEST_OFFSET + 20) - #define BSP_UIC_PCIe0VCO (BSP_UIC_IRQ_LOWEST_OFFSET + 21) - #define BSP_UIC_EIPPKP_TRNG_AL (BSP_UIC_IRQ_LOWEST_OFFSET + 22) - #define BSP_UIC_EIP94 (BSP_UIC_IRQ_LOWEST_OFFSET + 23) - #define BSP_UIC_EMAC0 (BSP_UIC_IRQ_LOWEST_OFFSET + 24) - #define BSP_UIC_EMAC1 (BSP_UIC_IRQ_LOWEST_OFFSET + 25) - #define BSP_UIC_UART0 (BSP_UIC_IRQ_LOWEST_OFFSET + 26) - #define BSP_UIC_IRQ4 (BSP_UIC_IRQ_LOWEST_OFFSET + 27) - #define BSP_UIC_UIC2_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 28) - #define BSP_UIC_UIC2_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 29) - #define BSP_UIC_UIC1_STD (BSP_UIC_IRQ_LOWEST_OFFSET + 30) - #define BSP_UIC_UIC1_CRIT (BSP_UIC_IRQ_LOWEST_OFFSET + 31) - - #define BSP_UIC1_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 32) - #define BSP_UIC_MALSERR (BSP_UIC1_IRQ_LOWEST_OFFSET + 0) - #define BSP_UIC_MALTXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 1) - #define BSP_UIC_MALRXDE (BSP_UIC1_IRQ_LOWEST_OFFSET + 2) - #define BSP_UIC_PCIe0DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 3) - #define BSP_UIC_PCIe1DCRErr (BSP_UIC1_IRQ_LOWEST_OFFSET + 4) - #define BSP_UIC_ExtBus (BSP_UIC1_IRQ_LOWEST_OFFSET + 5) - #define BSP_UIC_NDFC (BSP_UIC1_IRQ_LOWEST_OFFSET + 6) - #define BSP_UIC_EIPKP_SLAVE (BSP_UIC1_IRQ_LOWEST_OFFSET + 7) - #define BSP_UIC_GPT_TIMER5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 8) - #define BSP_UIC_GPT_TIMER6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 9) - - #define BSP_UIC_GPT_TIMER0 (BSP_UIC1_IRQ_LOWEST_OFFSET + 16) - #define BSP_UIC_GPT_TIMER1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 17) - #define BSP_UIC_IRQ7 (BSP_UIC1_IRQ_LOWEST_OFFSET + 18) - #define BSP_UIC_IRQ8 (BSP_UIC1_IRQ_LOWEST_OFFSET + 19) - #define BSP_UIC_IRQ9 (BSP_UIC1_IRQ_LOWEST_OFFSET + 20) - #define BSP_UIC_GPT_TIMER2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 21) - #define BSP_UIC_GPT_TIMER3 (BSP_UIC1_IRQ_LOWEST_OFFSET + 22) - #define BSP_UIC_GPT_TIMER4 (BSP_UIC1_IRQ_LOWEST_OFFSET + 23) - #define BSP_UIC_SERIAL_ROM (BSP_UIC1_IRQ_LOWEST_OFFSET + 24) - #define BSP_UIC_GPT_DEC (BSP_UIC1_IRQ_LOWEST_OFFSET + 25) - #define BSP_UIC_IRQ2 (BSP_UIC1_IRQ_LOWEST_OFFSET + 26) - #define BSP_UIC_IRQ5 (BSP_UIC1_IRQ_LOWEST_OFFSET + 27) - #define BSP_UIC_IRQ6 (BSP_UIC1_IRQ_LOWEST_OFFSET + 28) - #define BSP_UIC_EMAC0WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 29) - #define BSP_UIC_IRQ1 (BSP_UIC1_IRQ_LOWEST_OFFSET + 30) - #define BSP_UIC_EMAC1WU (BSP_UIC1_IRQ_LOWEST_OFFSET + 31) - - #define BSP_UIC2_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + 64) - #define BSP_UIC_PCIe0INTA (BSP_UIC2_IRQ_LOWEST_OFFSET + 0) - #define BSP_UIC_PCIe0INTB (BSP_UIC2_IRQ_LOWEST_OFFSET + 1) - #define BSP_UIC_PCIe0INTC (BSP_UIC2_IRQ_LOWEST_OFFSET + 2) - #define BSP_UIC_PCIe0INTD (BSP_UIC2_IRQ_LOWEST_OFFSET + 3) - #define BSP_UIC_IRQ3 (BSP_UIC2_IRQ_LOWEST_OFFSET + 4) - - #define BSP_UIC_USBOTG (BSP_UIC2_IRQ_LOWEST_OFFSET + 30) - - #define BSP_UIC_IRQ_NUMBER (95) - - - #define BSP_UIC_IRQ_LOWEST_OFFSET 0 - #define BSP_UIC_IRQ_MAX_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET + BSP_UIC_IRQ_NUMBER - 1) - - #define BSP_UART_COM1_IRQ BSP_UIC_UART0 /* Required by shared/console/uart.c */ - #define BSP_UART_COM2_IRQ BSP_UIC_UART1 - - /* Define processor IRQ numbers; IRQs that are handled by the exception vectors */ - - #define BSP_PIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET /* Required by ppc403/clock.c */ - #define BSP_FIT BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1 - #define BSP_WDOG BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 - - #define BSP_PROCESSOR_IRQ_NUMBER (3) - #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_UIC_IRQ_MAX_OFFSET + 1) - #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - - /* Summary and totals */ - - #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) - #define BSP_LOWEST_OFFSET (BSP_UIC_IRQ_LOWEST_OFFSET) - #define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) - - extern void BSP_rtems_irq_mng_init(unsigned cpuId); // Implemented in irq_init.c - #include <bsp/irq_supp.h> - - #ifdef __cplusplus - } - #endif -#endif /* ASM */ - -#endif /* Haleakala_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h deleted file mode 100644 index 98258d49be..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/8xx_immap.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - unsigned int sc_siumcr; - unsigned int sc_sypcr; - unsigned int sc_swt; - char res1[2]; - unsigned short sc_swsr; - unsigned int sc_sipend; - unsigned int sc_simask; - unsigned int sc_siel; - unsigned int sc_sivec; - unsigned int sc_tesr; - char res2[0xc]; - unsigned int sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - unsigned int pcmc_pbr0; - unsigned int pcmc_por0; - unsigned int pcmc_pbr1; - unsigned int pcmc_por1; - unsigned int pcmc_pbr2; - unsigned int pcmc_por2; - unsigned int pcmc_pbr3; - unsigned int pcmc_por3; - unsigned int pcmc_pbr4; - unsigned int pcmc_por4; - unsigned int pcmc_pbr5; - unsigned int pcmc_por5; - unsigned int pcmc_pbr6; - unsigned int pcmc_por6; - unsigned int pcmc_pbr7; - unsigned int pcmc_por7; - char res1[0x20]; - unsigned int pcmc_pgcra; - unsigned int pcmc_pgcrb; - unsigned int pcmc_pscr; - char res2[4]; - unsigned int pcmc_pipr; - char res3[4]; - unsigned int pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - unsigned int memc_br0; - unsigned int memc_or0; - unsigned int memc_br1; - unsigned int memc_or1; - unsigned int memc_br2; - unsigned int memc_or2; - unsigned int memc_br3; - unsigned int memc_or3; - unsigned int memc_br4; - unsigned int memc_or4; - unsigned int memc_br5; - unsigned int memc_or5; - unsigned int memc_br6; - unsigned int memc_or6; - unsigned int memc_br7; - unsigned int memc_or7; - char res1[0x24]; - unsigned int memc_mar; - unsigned int memc_mcr; - char res2[4]; - unsigned int memc_mamr; - unsigned int memc_mbmr; - unsigned short memc_mstat; - unsigned short memc_mptpr; - unsigned int memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - unsigned short sit_tbscr; - unsigned int sit_tbreff0; - unsigned int sit_tbreff1; - char res1[0x14]; - unsigned short sit_rtcsc; - unsigned int sit_rtc; - unsigned int sit_rtsec; - unsigned int sit_rtcal; - char res2[0x10]; - unsigned short sit_piscr; - char res3[2]; - unsigned int sit_pitc; - unsigned int sit_pitr; - char res4[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) -#define TBSCR_REFA ((unsigned short)0x0080) -#define TBSCR_REFB ((unsigned short)0x0040) -#define TBSCR_REFAE ((unsigned short)0x0008) -#define TBSCR_REFBE ((unsigned short)0x0004) -#define TBSCR_TBF ((unsigned short)0x0002) -#define TBSCR_TBE ((unsigned short)0x0001) - -#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) -#define RTCSC_SEC ((unsigned short)0x0080) -#define RTCSC_ALR ((unsigned short)0x0040) -#define RTCSC_38K ((unsigned short)0x0010) -#define RTCSC_SIE ((unsigned short)0x0008) -#define RTCSC_ALE ((unsigned short)0x0004) -#define RTCSC_RTF ((unsigned short)0x0002) -#define RTCSC_RTE ((unsigned short)0x0001) - -#define PISCR_PIRQ_MASK ((unsigned short)0xff00) -#define PISCR_PS ((unsigned short)0x0080) -#define PISCR_PIE ((unsigned short)0x0004) -#define PISCR_PTF ((unsigned short)0x0002) -#define PISCR_PTE ((unsigned short)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - unsigned int car_sccr; - unsigned int car_plprcr; - unsigned int car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - unsigned int sitk_tbscrk; - unsigned int sitk_tbreff0k; - unsigned int sitk_tbreff1k; - unsigned int sitk_tbk; - char res1[0x10]; - unsigned int sitk_rtcsck; - unsigned int sitk_rtck; - unsigned int sitk_rtseck; - unsigned int sitk_rtcalk; - char res2[0x10]; - unsigned int sitk_piscrk; - unsigned int sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - unsigned int cark_sccrk; - unsigned int cark_plprcrk; - unsigned int cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* LCD interface. MPC821 Only. -*/ -typedef struct lcd { - unsigned short lcd_lcolr[16]; - char res[0x20]; - unsigned int lcd_lccr; - unsigned int lcd_lchcr; - unsigned int lcd_lcvcr; - char res2[4]; - unsigned int lcd_lcfaa; - unsigned int lcd_lcfba; - char lcd_lcsr; - char res3[0x7]; -} lcd8xx_t; - -/* I2C -*/ -typedef struct i2c { - unsigned char i2c_i2mod; - char res1[3]; - unsigned char i2c_i2add; - char res2[3]; - unsigned char i2c_i2brg; - char res3[3]; - unsigned char i2c_i2com; - char res4[3]; - unsigned char i2c_i2cer; - char res5[3]; - unsigned char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - unsigned int sdma_sdar; - unsigned char sdma_sdsr; - char res3[3]; - unsigned char sdma_sdmr; - char res4[3]; - unsigned char sdma_idsr1; - char res5[3]; - unsigned char sdma_idmr1; - char res6[3]; - unsigned char sdma_idsr2; - char res7[3]; - unsigned char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - unsigned short cpic_civr; - char res[0xe]; - unsigned int cpic_cicr; - unsigned int cpic_cipr; - unsigned int cpic_cimr; - unsigned int cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - unsigned short iop_padir; - unsigned short iop_papar; - unsigned short iop_paodr; - unsigned short iop_padat; - char res1[8]; - unsigned short iop_pcdir; - unsigned short iop_pcpar; - unsigned short iop_pcso; - unsigned short iop_pcdat; - unsigned short iop_pcint; - char res2[6]; - unsigned short iop_pddir; - unsigned short iop_pdpar; - char res3[2]; - unsigned short iop_pddat; - char res4[8]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - unsigned short cpmt_tgcr; - char res1[0xe]; - unsigned short cpmt_tmr1; - unsigned short cpmt_tmr2; - unsigned short cpmt_trr1; - unsigned short cpmt_trr2; - unsigned short cpmt_tcr1; - unsigned short cpmt_tcr2; - unsigned short cpmt_tcn1; - unsigned short cpmt_tcn2; - unsigned short cpmt_tmr3; - unsigned short cpmt_tmr4; - unsigned short cpmt_trr3; - unsigned short cpmt_trr4; - unsigned short cpmt_tcr3; - unsigned short cpmt_tcr4; - unsigned short cpmt_tcn3; - unsigned short cpmt_tcn4; - unsigned short cpmt_ter1; - unsigned short cpmt_ter2; - unsigned short cpmt_ter3; - unsigned short cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - unsigned int scc_gsmrl; - unsigned int scc_gsmrh; - unsigned short scc_pmsr; - char res1[2]; - unsigned short scc_todr; - unsigned short scc_dsr; - unsigned short scc_scce; - char res2[2]; - unsigned short scc_sccm; - char res3; - unsigned char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - unsigned short smc_smcmr; - char res2[2]; - unsigned char smc_smce; - char res3[3]; - unsigned char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ -typedef struct fec { - unsigned int fec_addr_low; /* LS 32 bits of station address */ - unsigned short fec_addr_high; /* MS 16 bits of address */ - unsigned short res1; - unsigned int fec_hash_table_high; - unsigned int fec_hash_table_low; - unsigned int fec_r_des_start; - unsigned int fec_x_des_start; - unsigned int fec_r_buff_size; - unsigned int res2[9]; - unsigned int fec_ecntrl; - unsigned int fec_ievent; - unsigned int fec_imask; - unsigned int fec_ivec; - unsigned int fec_r_des_active; - unsigned int fec_x_des_active; - unsigned int res3[10]; - unsigned int fec_mii_data; - unsigned int fec_mii_speed; - unsigned int res4[17]; - unsigned int fec_r_bound; - unsigned int fec_r_fstart; - unsigned int res5[6]; - unsigned int fec_x_fstart; - unsigned int res6[17]; - unsigned int fec_fun_code; - unsigned int res7[3]; - unsigned int fec_r_cntrl; - unsigned int fec_r_hash; - unsigned int res8[14]; - unsigned int fec_x_cntrl; - unsigned int res9[0x1e]; -} fec_t; - -typedef struct comm_proc { - /* General control and status registers. - */ - unsigned short cp_cpcr; - char res1[2]; - unsigned short cp_rccr; - char res2[6]; - unsigned short cp_cpmcr1; - unsigned short cp_cpmcr2; - unsigned short cp_cpmcr3; - unsigned short cp_cpmcr4; - char res3[2]; - unsigned short cp_rter; - char res4[2]; - unsigned short cp_rtmr; - char res5[0x14]; - - /* Baud rate generators. - */ - unsigned int cp_brgc1; - unsigned int cp_brgc2; - unsigned int cp_brgc3; - unsigned int cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - unsigned short cp_spmode; - char res6[4]; - unsigned char cp_spie; - char res7[3]; - unsigned char cp_spim; - char res8[2]; - unsigned char cp_spcom; - char res9[2]; - - /* Parallel Interface Port. - */ - char res10[2]; - unsigned short cp_pipc; - char res11[2]; - unsigned short cp_ptpr; - unsigned int cp_pbdir; - unsigned int cp_pbpar; - char res12[2]; - unsigned short cp_pbodr; - unsigned int cp_pbdat; - char res13[0x18]; - - /* Serial Interface and Time Slot Assignment. - */ - unsigned int cp_simode; - unsigned char cp_sigmr; - char res14; - unsigned char cp_sistr; - unsigned char cp_sicmr; - char res15[4]; - unsigned int cp_sicr; - unsigned int cp_sirp; - char res16[0x10c]; - unsigned char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - */ - fec_t cp_fec; - char res18[0x1000]; - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - */ - unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ - unsigned char res19[0xc00]; - unsigned char cp_dparam[0x400]; /* Parameter RAM */ -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - lcd8xx_t im_lcd; /* LCD (821 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h deleted file mode 100644 index eeafa10e11..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h +++ /dev/null @@ -1,97 +0,0 @@ -/* bsp.h - * - * This include file contains all board IO definitions. - * - * This file includes definitions for the MBX860 and MBX821. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MBX8XX_BSP_H -#define LIBBSP_POWERPC_MBX8XX_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/irq.h> -#include <mpc8xx.h> -#include <mpc8xx/cpm.h> -#include <mpc8xx/mmu.h> -#include <mpc8xx/console.h> -#include <bsp/vectors.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Representation of initialization data in NVRAM - */ -typedef volatile struct nvram_config_ { - unsigned char cache_mode; /* 0xFA001000 */ - unsigned char console_mode; /* 0xFA001001 */ - unsigned char console_printk_port; /* 0xFA001002 */ - unsigned char eppcbug_smc1; /* 0xFA001003 */ - unsigned long ipaddr; /* 0xFA001004 */ - unsigned long netmask; /* 0xFA001008 */ - unsigned char enaddr[6]; /* 0xFA00100C */ - unsigned short processor_id; /* 0xFA001012 */ - unsigned long rma_start; /* 0xFA001014 */ - unsigned long vma_start; /* 0xFA001018 */ - unsigned long ramsize; /* 0xFA00101C */ -} nvram_config; - -/* - * Pointer to the base of User Area NVRAM - */ -#define nvram ((nvram_config * const) 0xFA001000) - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "scc1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach - -/* - * We need to decide how much memory will be non-cacheable. This - * will mainly be memory that will be used in DMA (network and serial - * buffers). - */ -#define NOCACHE_MEM_SIZE 512*1024 - -/* - * indicate, that BSP has IDE driver - */ -#define RTEMS_BSP_HAS_IDE_DRIVER - -extern uint32_t bsp_clock_speed; - -char serial_getc(void); - -int serial_tstc(void); - -void serial_init(void); - -int mbx8xx_console_get_configuration(void); - -void _InitMBX8xx(void); - -int BSP_disconnect_clock_handler(void); - -int BSP_connect_clock_handler (rtems_irq_hdl); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h b/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h deleted file mode 100644 index 4d8166847d..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/include/coverhd.h +++ /dev/null @@ -1,366 +0,0 @@ -/** - * @file - * @ingroup powerpc_mbx8xx - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) -#if BSP_INSTRUCTION_CACHE_ENABLED -/* - * 50 MHz processor, cache enabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 1 -#define CALLING_OVERHEAD_CLOCK_SET 1 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 0 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#else -/* - * 50 MHz processor, cache disabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 -#define CALLING_OVERHEAD_TASK_CREATE 7 -#define CALLING_OVERHEAD_TASK_IDENT 6 -#define CALLING_OVERHEAD_TASK_START 5 -#define CALLING_OVERHEAD_TASK_RESTART 5 -#define CALLING_OVERHEAD_TASK_DELETE 4 -#define CALLING_OVERHEAD_TASK_SUSPEND 4 -#define CALLING_OVERHEAD_TASK_RESUME 4 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 -#define CALLING_OVERHEAD_TASK_MODE 5 -#define CALLING_OVERHEAD_TASK_GET_NOTE 5 -#define CALLING_OVERHEAD_TASK_SET_NOTE 5 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 19 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 -#define CALLING_OVERHEAD_CLOCK_GET 20 -#define CALLING_OVERHEAD_CLOCK_SET 19 -#define CALLING_OVERHEAD_CLOCK_TICK 3 - -#define CALLING_OVERHEAD_TIMER_CREATE 5 -#define CALLING_OVERHEAD_TIMER_IDENT 4 -#define CALLING_OVERHEAD_TIMER_DELETE 5 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 21 -#define CALLING_OVERHEAD_TIMER_RESET 4 -#define CALLING_OVERHEAD_TIMER_CANCEL 4 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 6 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 6 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5 - -#define CALLING_OVERHEAD_EVENT_SEND 5 -#define CALLING_OVERHEAD_EVENT_RECEIVE 5 -#define CALLING_OVERHEAD_SIGNAL_CATCH 4 -#define CALLING_OVERHEAD_SIGNAL_SEND 5 -#define CALLING_OVERHEAD_PARTITION_CREATE 7 -#define CALLING_OVERHEAD_PARTITION_IDENT 6 -#define CALLING_OVERHEAD_PARTITION_DELETE 4 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 5 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 5 -#define CALLING_OVERHEAD_REGION_CREATE 7 -#define CALLING_OVERHEAD_REGION_IDENT 5 -#define CALLING_OVERHEAD_REGION_DELETE 4 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 6 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5 -#define CALLING_OVERHEAD_PORT_CREATE 6 -#define CALLING_OVERHEAD_PORT_IDENT 5 -#define CALLING_OVERHEAD_PORT_DELETE 4 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 6 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 6 - -#define CALLING_OVERHEAD_IO_INITIALIZE 6 -#define CALLING_OVERHEAD_IO_OPEN 6 -#define CALLING_OVERHEAD_IO_CLOSE 6 -#define CALLING_OVERHEAD_IO_READ 6 -#define CALLING_OVERHEAD_IO_WRITE 6 -#define CALLING_OVERHEAD_IO_CONTROL 6 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 5 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 - -#endif /* BSP_INSTRUCTION_CACHE_ENABLED */ - -#else -#if BSP_INSTRUCTION_CACHE_ENABLED -/* - * 40 MHz processor, cache enabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 1 -#define CALLING_OVERHEAD_CLOCK_SET 1 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#else -/* - * 40 MHz processor, cache disabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 3 -#define CALLING_OVERHEAD_TASK_CREATE 6 -#define CALLING_OVERHEAD_TASK_IDENT 5 -#define CALLING_OVERHEAD_TASK_START 5 -#define CALLING_OVERHEAD_TASK_RESTART 4 -#define CALLING_OVERHEAD_TASK_DELETE 4 -#define CALLING_OVERHEAD_TASK_SUSPEND 4 -#define CALLING_OVERHEAD_TASK_RESUME 4 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 -#define CALLING_OVERHEAD_TASK_MODE 4 -#define CALLING_OVERHEAD_TASK_GET_NOTE 5 -#define CALLING_OVERHEAD_TASK_SET_NOTE 5 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 17 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 3 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 -#define CALLING_OVERHEAD_CLOCK_GET 17 -#define CALLING_OVERHEAD_CLOCK_SET 17 -#define CALLING_OVERHEAD_CLOCK_TICK 3 - -#define CALLING_OVERHEAD_TIMER_CREATE 4 -#define CALLING_OVERHEAD_TIMER_IDENT 4 -#define CALLING_OVERHEAD_TIMER_DELETE 5 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 5 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 19 -#define CALLING_OVERHEAD_TIMER_RESET 4 -#define CALLING_OVERHEAD_TIMER_CANCEL 4 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 6 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 5 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 4 - -#define CALLING_OVERHEAD_EVENT_SEND 5 -#define CALLING_OVERHEAD_EVENT_RECEIVE 5 -#define CALLING_OVERHEAD_SIGNAL_CATCH 4 -#define CALLING_OVERHEAD_SIGNAL_SEND 4 -#define CALLING_OVERHEAD_PARTITION_CREATE 6 -#define CALLING_OVERHEAD_PARTITION_IDENT 5 -#define CALLING_OVERHEAD_PARTITION_DELETE 4 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 5 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 5 -#define CALLING_OVERHEAD_REGION_CREATE 6 -#define CALLING_OVERHEAD_REGION_IDENT 5 -#define CALLING_OVERHEAD_REGION_DELETE 4 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 6 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5 -#define CALLING_OVERHEAD_PORT_CREATE 6 -#define CALLING_OVERHEAD_PORT_IDENT 5 -#define CALLING_OVERHEAD_PORT_DELETE 4 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 5 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 5 - -#define CALLING_OVERHEAD_IO_INITIALIZE 5 -#define CALLING_OVERHEAD_IO_OPEN 5 -#define CALLING_OVERHEAD_IO_CLOSE 5 -#define CALLING_OVERHEAD_IO_READ 5 -#define CALLING_OVERHEAD_IO_WRITE 5 -#define CALLING_OVERHEAD_IO_CONTROL 5 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 3 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 5 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 - -#endif /* BSP_INSTRUCTION_CACHE_ENABLED */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h b/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h deleted file mode 100644 index b79ea96690..0000000000 --- a/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.h +++ /dev/null @@ -1,184 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MBX8XX_IRQ_IRQ_H -#define LIBBSP_POWERPC_MBX8XX_IRQ_IRQ_H - -#include <rtems/irq.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -extern volatile unsigned int ppc_cached_irq_mask; - -/* - * Symblolic IRQ names and related definitions. - */ - - /* - * SIU IRQ handler related definitions - */ -#define BSP_SIU_IRQ_NUMBER 16 /* 16 reserved but in the future... */ -#define BSP_SIU_IRQ_LOWEST_OFFSET 0 -#define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER - 1) - /* - * CPM IRQ handlers related definitions - * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE - */ -#define BSP_CPM_IRQ_NUMBER 32 -#define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_NUMBER + BSP_SIU_IRQ_LOWEST_OFFSET) -#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1) - /* - * PowerPc exceptions handled as interrupt where a rtems managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER 1 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - /* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET) - /* - * Some SIU IRQ symbolic name definition. Please note that - * INT IRQ are defined but a single one will be used to - * redirect all CPM interrupt. - */ -#define BSP_SIU_EXT_IRQ_0 0 -#define BSP_SIU_INT_IRQ_0 1 - -#define BSP_SIU_EXT_IRQ_1 2 -#define BSP_SIU_INT_IRQ_1 3 - -#define BSP_SIU_EXT_IRQ_2 4 -#define BSP_SIU_INT_IRQ_2 5 - -#define BSP_SIU_EXT_IRQ_3 6 -#define BSP_SIU_INT_IRQ_3 7 - -#define BSP_SIU_EXT_IRQ_4 8 -#define BSP_SIU_INT_IRQ_4 9 - -#define BSP_SIU_EXT_IRQ_5 10 -#define BSP_SIU_INT_IRQ_5 11 - -#define BSP_SIU_EXT_IRQ_6 12 -#define BSP_SIU_INT_IRQ_6 13 - -#define BSP_SIU_EXT_IRQ_7 14 -#define BSP_SIU_INT_IRQ_7 15 - /* - * Symbolic name for CPM interrupt on SIU Internal level 2 - */ -#define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2 -#define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6 -#define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3 - /* - * Some CPM IRQ symbolic name definition - */ -#define BSP_CPM_IRQ_ERROR BSP_CPM_IRQ_LOWEST_OFFSET -#define BSP_CPM_IRQ_PARALLEL_IO_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 1) -#define BSP_CPM_IRQ_PARALLEL_IO_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 2) -#define BSP_CPM_IRQ_SMC2_OR_PIP (BSP_CPM_IRQ_LOWEST_OFFSET + 3) -#define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4) -#define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 5) -#define BSP_CPM_IRQ_PARALLEL_IO_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 6) -#define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 7) - -#define BSP_CPM_IRQ_PARALLEL_IO_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 9) -#define BSP_CPM_IRQ_PARALLEL_IO_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 10) -#define BSP_CPM_IRQ_PARALLEL_IO_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 11) -#define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 12) - -#define BSP_CPM_IRQ_PARALLEL_IO_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 14) -#define BSP_CPM_IRQ_PARALLEL_IO_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 15) -#define BSP_CPM_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 16) -#define BSP_CPM_RISC_TIMER_TABLE (BSP_CPM_IRQ_LOWEST_OFFSET + 17) -#define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 18) - -#define BSP_CPM_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20) -#define BSP_CPM_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 21) -#define BSP_CPM_SDMA_CHANNEL_BUS_ERR (BSP_CPM_IRQ_LOWEST_OFFSET + 22) -#define BSP_CPM_IRQ_PARALLEL_IO_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 23) -#define BSP_CPM_IRQ_PARALLEL_IO_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 24) -#define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 25) -#define BSP_CPM_IRQ_PARALLEL_IO_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 26) -#define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 27) -#define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 28) -#define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 29) -#define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 30) -#define BSP_CPM_IRQ_PARALLEL_IO_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 31) - /* - * Some Processor exception handled as rtems IRQ symbolic name definition - */ -#define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -#define CPM_INTERRUPT - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ -/* - * ------------------------ PPC SIU Mngt Routines ------- - */ - -/* - * function to disable a particular irq at 8259 level. After calling - * this function, even if the device asserts the interrupt line it will - * not be propagated further to the processor - */ -int BSP_irq_disable_at_siu (const rtems_irq_number irqLine); -/* - * function to enable a particular irq at 8259 level. After calling - * this function, if the device asserts the interrupt line it will - * be propagated further to the processor - */ -int BSP_irq_enable_at_siu (const rtems_irq_number irqLine); -/* - * function to acknoledge a particular irq at 8259 level. After calling - * this function, if a device asserts an enabled interrupt line it will - * be propagated further to the processor. Mainly usefull for people - * writting raw handlers as this is automagically done for rtems managed - * handlers. - */ -int BSP_irq_ack_at_siu (const rtems_irq_number irqLine); -/* - * function to check if a particular irq is enabled at 8259 level. After calling - */ -int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine); - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); - -extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h deleted file mode 100644 index 0439e875ad..0000000000 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H -#define LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <libcpu/io.h> -#include <rtems/clockdrv.h> -#include <bsp/vectors.h> - -#ifdef qemu -#include <rtems/bspcmdline.h> -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * diagram illustrating the role of the configuration - * constants - * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible - * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this - * address being 'visible' or not!). - * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME - * _VME_A32_WIN0_ON_VME: VME address of that same window - * - * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between - * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI - * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to - * the base address read from PCI config.space in order to translate that - * into a CPU address. - * - * NOTE: VME addresses should NEVER be translated using these constants! - * they are strictly for BSP internal use. Drivers etc. should use - * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). - * - * CPU ADDR PCI_ADDR VME ADDR - * - * 00000000 XXXXXXXX XXXXXXXX - * ^ ^ ........ - * | | - * | | e.g., RAM XXXXXXXX - * | | 00000000 - * | | ......... ^ - * | | (possible offset | - * | | between pci and XXXXXXXX | ...... - * | | cpu addresses) | - * | v | - * | PCI_MEM_BASE -------------> 00000000 --------------- | - * | ........ ........ ^ | - * | invisible | | - * | ........ from CPU | | - * v | | - * PCI_MEM_WIN0 ============= first visible PCI addr | | - * | | - * pci devices pci window | | - * visible here v v - * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME - * vme window - * VME devices hostbridge mapped by - * visible here universe - * ===================================================== - * - */ - -/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ -#if defined(mvme2100) -#define _IO_BASE CHRP_ISA_IO_BASE -#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE -/* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET -/* offset of pci memory as seen from the CPU */ -#define PCI_MEM_BASE 0 -/* where (in CPU addr. space) does the PCI window start */ -#define PCI_MEM_WIN0 0x80000000 - -#else -#define _IO_BASE PREP_ISA_IO_BASE -#define _ISA_MEM_BASE PREP_ISA_MEM_BASE -#ifndef qemu -/* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET -/* offset of pci memory as seen from the CPU */ -#define PCI_MEM_BASE PREP_ISA_MEM_BASE -#define PCI_MEM_WIN0 0 -#else -#define PCI_DRAM_OFFSET 0 -#define PCI_MEM_BASE 0 -#define PCI_MEM_WIN0 PREP_ISA_MEM_BASE -#endif -#endif - - -/* - * Base address definitions for several devices - * - * MVME2100 is very similar but has fewer devices and uses on-CPU EPIC - * implementation of OpenPIC controller. It also cannot be probed to - * find out what it is which is VERY different from other Motorola boards. - */ - -#if defined(mvme2100) -#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000) -/* #define BSP_UART_IOBASE_COM1 (0xffe10000) */ -#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 - -#define MVME_HAS_DEC21140 -#else -#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8) -#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8) - -#if ! defined(qemu) -#define BSP_KBD_IOBASE ((_IO_BASE)+0x60) -#define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0) -#endif - -#if defined(mvme2300) -#define MVME_HAS_DEC21140 -#endif -#endif - -#define BSP_CONSOLE_PORT BSP_UART_COM1 -#define BSP_UART_BAUD_BASE 115200 - -#if defined(MVME_HAS_DEC21140) -struct rtems_bsdnet_ifconfig; -#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach -extern int rtems_dec21140_driver_attach(); -#endif - -#ifdef qemu -#define RTEMS_BSP_NETWORK_DRIVER_NAME "ne1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ne_driver_attach -extern int rtems_ne_driver_attach(); -#endif - -#ifdef qemu -#define BSP_IDLE_TASK_BODY bsp_ppc_idle_task_body -extern void *bsp_ppc_idle_task_body(uintptr_t arg); -#endif - -#include <bsp/openpic.h> -/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver - * to implement VME IRQ priorities in software. - * Note that this requires support by the interrupt controller - * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c) - * and the BSP-specific universe initialization/configuration - * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c) - * - * ********* IMPORTANT NOTE ******** - * When deriving from this file (new BSPs) - * DO NOT define "BSP_PIC_DO_EOI" if you don't know what - * you are doing i.e., w/o implementing the required pieces - * mentioned above. - * ********* IMPORTANT NOTE ******** - */ -#define BSP_PIC_DO_EOI openpic_eoi(0) - -#ifndef ASM -#define outport_byte(port,value) outb(value,port) -#define outport_word(port,value) outw(value,port) -#define outport_long(port,value) outl(value,port) - -#define inport_byte(port,value) (value = inb(port)) -#define inport_word(port,value) (value = inw(port)) -#define inport_long(port,value) (value = inl(port)) - -/* - * Vital Board data Start using DATA RESIDUAL - */ - -/* - * Total memory using RESIDUAL DATA - */ -extern unsigned int BSP_mem_size; -/* - * Start of the heap - */ -extern unsigned int BSP_heap_start; -/* - * PCI Bus Frequency - */ -extern unsigned int BSP_bus_frequency; -/* - * processor clock frequency - */ -extern unsigned int BSP_processor_frequency; -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; - -/* - * String passed by the bootloader. - */ -extern char *BSP_commandline_string; - -#define BSP_Convert_decrementer( _value ) \ - ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) - -extern void BSP_panic(char *s); -/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ -extern int BSP_disconnect_clock_handler (void); -extern int BSP_connect_clock_handler (void); - -/* clear hostbridge errors - * - * NOTE: The routine returns always (-1) if 'enableMCP==1' - * [semantics needed by libbspExt] if the MCP input is not wired. - * It returns and clears the error bits of the PCI status register. - * MCP support is disabled because: - * a) the 2100 has no raven chip - * b) the raven (2300) would raise machine check interrupts - * on PCI config space access to empty slots. - */ -extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); - -/* - * Prototypes for methods called only from .S for dependency tracking - */ -char *save_boot_params( - void *r3, - void *r4, - void *r5, - char *cmdline_start, - char *cmdline_end -); -void zero_bss(void); - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void VIA_isa_bridge_interrupts_setup(void); - -#endif - -#ifdef __cplusplus -}; -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/tm27.h b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/tm27.h deleted file mode 100644 index 81eb55a54a..0000000000 --- a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/tm27.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * @file - * @ingroup powerpc_motorola_powerpc - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - */ - -#include <bsp/irq.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -void nullFunc() {} -static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, - 0, - (rtems_irq_enable)nullFunc, - (rtems_irq_disable)nullFunc, - (rtems_irq_is_enabled) nullFunc}; -void Install_tm27_vector(void (*_handler)()) -{ - clockIrqData.hdl = _handler; - if (!BSP_install_rtems_irq_handler (&clockIrqData)) { - printk("Error installing clock interrupt handler!\n"); - rtems_fatal_error_occurred(1); - } -} - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 8; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Clear_tm27_intr() \ - do { \ - uint32_t _clicks = 0xffffffff; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - uint32_t _msr = 0; \ - _ISR_Set_level( 0 ); \ - __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - _msr |= 0x8002; \ - __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h b/c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h deleted file mode 100644 index f860960904..0000000000 --- a/c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief Global BSP variables and functions - */ - -/* - * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MPC55XXEVB_BSP_H -#define LIBBSP_POWERPC_MPC55XXEVB_BSP_H - -#include <bspopts.h> - -#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN - -#define BSP_FEATURE_IRQ_EXTENSION - -#define MPC55XX_PERIPHERAL_CLOCK \ - (MPC55XX_SYSTEM_CLOCK / MPC55XX_SYSTEM_CLOCK_DIVIDER) - -#ifndef ASM - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#include <libcpu/powerpc-utility.h> - -#include <bsp/tictac.h> -#include <bsp/linker-symbols.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** @brief System clock frequency */ -extern unsigned int bsp_clock_speed; - -/** @brief Time base clicks per micro second */ -extern uint32_t bsp_clicks_per_usec; - -/** @brief Convert Decrementer ticks to microseconds */ -#define BSP_Convert_decrementer( _value ) \ - (((unsigned long long) (_value)) / ((unsigned long long)bsp_clicks_per_usec)) - -rtems_status_code mpc55xx_sd_card_init( bool mount); - -/* Network driver configuration */ - -struct rtems_bsdnet_ifconfig; - -int smsc9218i_attach_detach( - struct rtems_bsdnet_ifconfig *config, - int attaching -); - -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH smsc9218i_attach_detach - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" - -rtems_status_code bsp_register_i2c(void); - -void bsp_restart(void *addr); - -void *bsp_idle_thread(uintptr_t arg); - -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -LINKER_SYMBOL(bsp_section_dsram_begin) -LINKER_SYMBOL(bsp_section_dsram_end) -LINKER_SYMBOL(bsp_section_dsram_size) -LINKER_SYMBOL(bsp_section_dsram_load_begin) -LINKER_SYMBOL(bsp_section_dsram_load_end) - -#define BSP_DSRAM_SECTION __attribute__((section(".bsp_dsram"))) - -LINKER_SYMBOL(bsp_section_sysram_begin) -LINKER_SYMBOL(bsp_section_sysram_end) -LINKER_SYMBOL(bsp_section_sysram_size) -LINKER_SYMBOL(bsp_section_sysram_load_begin) -LINKER_SYMBOL(bsp_section_sysram_load_end) - -#define BSP_SYSRAM_SECTION __attribute__((section(".bsp_sysram"))) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_POWERPC_MPC55XXEVB_BSP_H */ diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h b/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h deleted file mode 100644 index 67713455ed..0000000000 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/include/bsp.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This include file contains all board IO definitions. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_MPC8260ADS_BSP_H -#define LIBBSP_POWERPC_MPC8260ADS_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <mpc8260.h> -#include <mpc8260/cpm.h> -#include <mpc8260/mmu.h> -#include <mpc8260/console.h> -#include <bsp/irq.h> -#include <bsp/vectors.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Board configuration registers - */ - -typedef struct bcsr - -{ - uint32_t bcsr0; /* Board Control and Status Register */ - uint32_t bcsr1; - uint32_t bcsr2; - uint32_t bcsr3; - -} BCSR; - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach - -/* miscellaneous stuff assumed to exist */ - -/* - * We need to decide how much memory will be non-cacheable. This - * will mainly be memory that will be used in DMA (network and serial - * buffers). - */ -/* -#define NOCACHE_MEM_SIZE 512*1024 -*/ - -/* functions */ - -#if 0 -void M8260ExecuteRISC( uint32_t command ); -void *M8260AllocateBufferDescriptors( int count ); -void *M8260AllocateRiscTimers( int count ); -extern char M8260DefaultWatchdogFeeder; -#endif - -/* - * Prototypes for items shared across file boundaries in the BSP - */ -extern uint32_t bsp_serial_per_sec; -void *bsp_idle_thread( uintptr_t ignored ); -void cpu_init(void); -int mbx8xx_console_get_configuration(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/include/tm27.h b/c/src/lib/libbsp/powerpc/mpc8260ads/include/tm27.h deleted file mode 100644 index b1eafc47aa..0000000000 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/include/tm27.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * @file - * @ingroup powerpc_mpc8260ads - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <rtems/powerpc/powerpc.h> - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) \ - do { \ - static rtems_irq_connect_data scIrqData = { \ - PPC_IRQ_SCALL, \ - (rtems_irq_hdl) handler, \ - NULL, \ - NULL, \ - NULL \ - }; \ - BSP_install_rtems_irq_handler (&scIrqData); \ - } while(0) - -#define Cause_tm27_intr() __asm__ volatile ("sc") - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h b/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h deleted file mode 100644 index 1dd18611fc..0000000000 --- a/c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.h +++ /dev/null @@ -1,193 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> - * Surrey Satellite Technology Limited - * The interrupt handling on the mpc8260 seems quite different from - * the 860 (I don't know the 860 well). Although some interrupts - * are routed via the CPM irq and some are direct to the SIU they all - * appear logically the same. Therefore I removed the distinction - * between SIU and CPM interrupts. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_IRQ_H -#define LIBBSP_POWERPC_IRQ_H -#include <rtems/irq.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* -extern volatile unsigned int ppc_cached_irq_mask; -*/ - -/* - * Symblolic IRQ names and related definitions. - */ - - /* - * CPM IRQ handlers related definitions - * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE - */ -#define BSP_CPM_IRQ_NUMBER (64) -#define BSP_CPM_IRQ_LOWEST_OFFSET (0) -#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1) - /* - * PowerPc exceptions handled as interrupt where a rtems managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - /* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET) - - /* - * Some SIU IRQ symbolic name definition. Please note that - * INT IRQ are defined but a single one will be used to - * redirect all CPM interrupt. - * - * On the mpc8260 all this seems to be transparent. Although the - * CPM, PIT and TMCNT interrupt may well be the only interrupts routed - * to the SIU at the hardware level all of them appear as CPM interupts - * to software apart from the registers for setting priority. - * - * The MPC8260 User Manual seems shot through with inconsistencies - * about this whole area. - */ - - /* - * Some CPM IRQ symbolic name definition - */ -#define BSP_CPM_IRQ_ERROR (BSP_CPM_IRQ_LOWEST_OFFSET + 0) -#define BSP_CPM_IRQ_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 1) -#define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 2) -#define BSP_CPM_IRQ_RISC_TIMERS (BSP_CPM_IRQ_LOWEST_OFFSET + 3) -#define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4) -#define BSP_CPM_IRQ_SMC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 5) -#define BSP_CPM_IRQ_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 6) -#define BSP_CPM_IRQ_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 7) -#define BSP_CPM_IRQ_IDMA3 (BSP_CPM_IRQ_LOWEST_OFFSET + 8) -#define BSP_CPM_IRQ_IDMA4 (BSP_CPM_IRQ_LOWEST_OFFSET + 9) -#define BSP_CPM_IRQ_SDMA (BSP_CPM_IRQ_LOWEST_OFFSET + 10) - -#define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 12) -#define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 13) -#define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 14) -#define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 15) -#define BSP_CPM_IRQ_TMCNT (BSP_CPM_IRQ_LOWEST_OFFSET + 16) -#define BSP_CPM_IRQ_PIT (BSP_CPM_IRQ_LOWEST_OFFSET + 17) - -#define BSP_CPM_IRQ_IRQ1 (BSP_CPM_IRQ_LOWEST_OFFSET + 19) -#define BSP_CPM_IRQ_IRQ2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20) -#define BSP_CPM_IRQ_IRQ3 (BSP_CPM_IRQ_LOWEST_OFFSET + 21) -#define BSP_CPM_IRQ_IRQ4 (BSP_CPM_IRQ_LOWEST_OFFSET + 22) -#define BSP_CPM_IRQ_IRQ5 (BSP_CPM_IRQ_LOWEST_OFFSET + 23) -#define BSP_CPM_IRQ_IRQ6 (BSP_CPM_IRQ_LOWEST_OFFSET + 24) -#define BSP_CPM_IRQ_IRQ7 (BSP_CPM_IRQ_LOWEST_OFFSET + 25) - -#define BSP_CPM_IRQ_FCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 32) -#define BSP_CPM_IRQ_FCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 33) -#define BSP_CPM_IRQ_FCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 34) -#define BSP_CPM_IRQ_MCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 36) -#define BSP_CPM_IRQ_MCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 37) - -#define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 40) -#define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 41) -#define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 42) -#define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 43) - -#define BSP_CPM_IRQ_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 48) -#define BSP_CPM_IRQ_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 49) -#define BSP_CPM_IRQ_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 50) -#define BSP_CPM_IRQ_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 51) -#define BSP_CPM_IRQ_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 52) -#define BSP_CPM_IRQ_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 53) -#define BSP_CPM_IRQ_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 54) -#define BSP_CPM_IRQ_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 55) -#define BSP_CPM_IRQ_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 56) -#define BSP_CPM_IRQ_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 57) -#define BSP_CPM_IRQ_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 58) -#define BSP_CPM_IRQ_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 59) -#define BSP_CPM_IRQ_PC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 60) -#define BSP_CPM_IRQ_PC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 61) -#define BSP_CPM_IRQ_PC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 62) -#define BSP_CPM_IRQ_PC0 (BSP_CPM_IRQ_LOWEST_OFFSET + 63) - - /* - * Some Processor exception handled as rtems IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) -#define BSP_PERIODIC_TIMER (BSP_DECREMENTER) - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -#define CPM_INTERRUPT - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ -/* - * ------------------------ PPC CPM Mngt Routines ------- - */ - -/* - * function to disable a particular irq. After calling - * this function, even if the device asserts the interrupt line it will - * not be propagated further to the processor - */ -int BSP_irq_disable_at_cpm (const rtems_irq_number irqLine); -/* - * function to enable a particular irq. After calling - * this function, if the device asserts the interrupt line it will - * be propagated further to the processor - */ -int BSP_irq_enable_at_cpm (const rtems_irq_number irqLine); -/* - * function to acknoledge a particular irq. After calling - * this function, if a device asserts an enabled interrupt line it will - * be propagated further to the processor. Mainly usefull for people - * writting raw handlers as this is automagically done for rtems managed - * handlers. - */ -int BSP_irq_ack_at_cpm (const rtems_irq_number irqLine); -/* - * function to check if a particular irq is enabled. After calling - */ -int BSP_irq_enabled_at_cpm (const rtems_irq_number irqLine); - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); - -#ifdef __cplusplus -} -#endif - -/* Now that we have defined some basics, include the generic support */ -#include <bsp/irq-generic.h> - -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/mvme3100/include/bsp.h b/c/src/lib/libbsp/powerpc/mvme3100/include/bsp.h deleted file mode 100644 index a6a697662b..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme3100/include/bsp.h +++ /dev/null @@ -1,345 +0,0 @@ -/** - * @file - * - * @ingroup mvme3100_bsp - * - * @brief This file contains BSP API definition. - */ - -/* - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Adapted for the mvme3100 BSP by T. Straumann, 2007. - */ -#ifndef LIBBSP_POWERPC_MVME3100_BSP_H -#define LIBBSP_POWERPC_MVME3100_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <libcpu/io.h> -#include <rtems/clockdrv.h> -#include <bsp/vectors.h> - -/** - * @defgroup mvme3100_bsp confdefs.h overrides - * - * @ingroup powerpc_mvme3100 - * - * @brief confdefs.h overrides for this BSP: - */ - -#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) - -/* - * diagram illustrating the role of the configuration - * constants - * PCI_MEM_WIN0: CPU starting addr where PCI memory space is visible - * PCI_MEM_BASE: CPU address of PCI mem addr. zero. (regardless of this - * address being 'visible' or not!). - * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME - * _VME_A32_WIN0_ON_VME: VME address of that same window - * - * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between - * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI - * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to - * the base address read from PCI config.space in order to translate that - * into a CPU address. - * - * NOTE: VME addresses should NEVER be translated using these constants! - * they are strictly for BSP internal use. Drivers etc. should use - * the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs). - * - * CPU ADDR PCI_ADDR VME ADDR - * - * 00000000 XXXXXXXX XXXXXXXX - * ^ ^ ........ - * | | - * | | e.g., RAM XXXXXXXX - * | | 00000000 - * | | ......... ^ - * | | (possible offset | - * | | between pci and XXXXXXXX | ...... - * | | cpu addresses) | - * | v | - * | PCI_MEM_BASE -------------> 00000000 --------------- | - * | ........ ........ ^ | - * | invisible | | - * | ........ from CPU | | - * v | | - * PCI_MEM_WIN0 ============= first visible PCI addr | | - * | | - * pci devices pci window | | - * visible here v v - * mapped by ========== _VME_A32_WIN0_ON_PCI ======= _VME_A32_WIN0_ON_VME - * vme window - * VME devices hostbridge mapped by - * visible here universe - * ===================================================== - * - */ - -/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */ -#define _IO_BASE 0xe0000000 /* Motload's PCI IO base */ -#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE -/* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET -/* offset of pci memory as seen from the CPU */ -#define PCI_MEM_BASE 0 -/* where (in CPU addr. space) does the PCI window start */ -#define PCI_MEM_WIN0 0x80000000 - -/* - * Base address definitions for several devices - */ - -#define BSP_OPEN_PIC_BASE_OFFSET 0x40000 -#define BSP_OPEN_PIC_BIG_ENDIAN - -#define BSP_8540_CCSR_BASE (0xe1000000) - -#define BSP_UART_IOBASE_COM1 (BSP_8540_CCSR_BASE+0x4500) -#define BSP_UART_IOBASE_COM2 (BSP_8540_CCSR_BASE+0x4600) -#define PCI_CONFIG_ADDR (BSP_8540_CCSR_BASE+0x8000) -#define PCI_CONFIG_DATA (BSP_8540_CCSR_BASE+0x8004) -#define PCI_CONFIG_WR_ADDR( addr, val ) out_be32((uint32_t*)(addr), (val)) - -#define BSP_CONSOLE_PORT BSP_UART_COM1 -#define BSP_UART_BAUD_BASE (-9600) /* use existing divisor to determine clock rate */ -#define BSP_UART_USE_SHARED_IRQS - -#define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) - -/* I2C Devices */ -/* Note that the i2c addresses stated in the manual are - * left-shifted by one bit. - */ -#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */ -#define BSP_USR0_I2C_ADDR (0xA4>>1) /* the 1st user EEPROM */ -#define BSP_USR1_I2C_ADDR (0xA6>>1) /* the 2nd user EEPROM */ -#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */ -#define BSP_RTC_I2C_ADDR (0xD0>>1) /* the DS1375 wall-clock */ - -#define BSP_I2C_BUS_DESCRIPTOR mpc8540_i2c_bus_descriptor - -#define BSP_I2C_BUS0_NAME "/dev/i2c0" - -#define BSP_I2C_VPD_EEPROM_NAME "vpd-eeprom" -#define BSP_I2C_USR_EEPROM_NAME "usr-eeprom" -#define BSP_I2C_USR1_EEPROM_NAME "usr1-eeprom" -#define BSP_I2C_DS1621_NAME "ds1621" -#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME -#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw" -#define BSP_I2C_DS1375_RAW_NAME "ds1375-raw" -#define BSP_I2C_RTC_RAW_NAME BSP_I2C_DS1375_RAW_NAME - -#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME) -#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME) -#define BSP_I2C_USR1_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR1_EEPROM_NAME) -#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME) -#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME -#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME) -#define BSP_I2C_DS1375_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1375_RAW_NAME) - -/* Definitions useful for bootloader (netboot); where to find - * boot/'environment' parameters. - */ -#define BSP_EEPROM_BOOTPARMS_NAME BSP_I2C_USR1_EEPROM_DEV_NAME -#define BSP_EEPROM_BOOTPARMS_SIZE 1024 -#define BSP_EEPROM_BOOTPARMS_OFFSET 0 -#define BSP_BOOTPARMS_WRITE_ENABLE() do { BSP_eeprom_write_enable(); } while (0) -#define BSP_BOOTPARMS_WRITE_DISABLE() do { BSP_eeprom_write_protect();} while (0) - - -#ifdef __cplusplus -extern "C" { -#endif -/* Initialize the I2C driver and register all devices - * RETURNS 0 on success, -1 on error. - * - * Access to the VPD and user EEPROMS as well - * as the ds1621 temperature sensor is possible - * by means of file nodes - * - * /dev/i2c0.vpd-eeprom (read-only) - * /dev/i2c0.usr-eeprom (read-write) - * /dev/i2c0.usr1-eeprom (read-write) - * /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC) - * /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621) - * /dev/i2c0.ds1375-raw (read-write; transfer bytes to/from the ds1375) - * - */ -int BSP_i2c_initialize(void); - -/* System Control Register */ -#define BSP_MVME3100_SYS_CR ((volatile uint8_t *)0xe2000001) -#define BSP_MVME3100_SYS_CR_RESET_MSK (7<<5) -#define BSP_MVME3100_SYS_CR_RESET (5<<5) -#define BSP_MVME3100_SYS_CR_EEPROM_WP (1<<1) -#define BSP_MVME3100_SYS_CR_TSTAT_MSK (1<<0) - -/* LED support */ -#define BSP_MVME3100_SYS_IND_REG ((volatile uint8_t *)0xe2000002) -#define BSP_LED_BRD_FAIL (1<<0) -#define BSP_LED_USR1 (1<<1) -#define BSP_LED_USR2 (1<<2) -#define BSP_LED_USR3 (1<<3) - -/* Flash CSR */ -#define BSP_MVME3100_FLASH_CSR ((volatile uint8_t *)0xe2000003) -#define BSP_MVME3100_FLASH_CSR_FLASH_RDY (1<<0) -#define BSP_MVME3100_FLASH_CSR_FBT_BLK_SEL (1<<1) -#define BSP_MVME3100_FLASH_CSR_F_WP_HW (1<<2) -#define BSP_MVME3100_FLASH_CSR_F_WP_SW (1<<3) -#define BSP_MVME3100_FLASH_CSR_MAP_SEL (1<<4) - -/* Phy interrupt detect */ -#define BSP_MVME3100_IRQ_DETECT_REG ((volatile uint8_t *)0xe2000007) - -/* Atomically set bits in a sys-register; The bits set in 'mask' - * are set in the register others; are left unmodified. - * - * RETURNS: old state. - * - * NOTE : since BSP_setSysReg( reg, 0 ) does not make - * any changes this call may be used - * to read the current status w/o modifying it. - */ -uint8_t BSP_setSysReg(volatile uint8_t *r, uint8_t mask); - -/* Atomically clear bits in a sys-register; The bits set in 'mask' - * are cleared in the register; others are left unmodified. - * - * RETURNS: old state. - * - * NOTE : since BSP_clrSysReg( reg, 0 ) does not make - * any changes this call may be used - * to read the current status w/o modifying it. - */ - -uint8_t BSP_clrSysReg(volatile uint8_t *r, uint8_t mask); - -/* Convenience wrappers around BSP_setSysReg()/BSP_clrSysReg() */ - -/* Set write-protection for all EEPROM devices - * RETURNS: old status - */ -uint8_t BSP_eeprom_write_protect(void); - -/* Disengage write-protection for all EEPROM devices - * RETURNS: old status - */ -uint8_t BSP_eeprom_write_enable(void); - -/* Set LEDs that have their bit set in the mask - * - * RETURNS: old status. - * - * NOTE : since BSP_setLEDs( 0 ) does not make - * any changes this call may be used - * to read the current status w/o modifying it. - */ -uint8_t BSP_setLEDs(uint8_t mask); - -/* Clear LEDs that have their bit set in the mask - * - * RETURNS: old status - * - * NOTE: : see above (BSP_setLEDs) - */ -uint8_t BSP_clrLEDs(uint8_t mask); - -#if 0 -#define outport_byte(port,value) outb(value,port) -#define outport_word(port,value) outw(value,port) -#define outport_long(port,value) outl(value,port) - -#define inport_byte(port,value) (value = inb(port)) -#define inport_word(port,value) (value = inw(port)) -#define inport_long(port,value) (value = inl(port)) -#endif - -/* - * Total memory using RESIDUAL DATA - */ -extern unsigned int BSP_mem_size; -/* - * PCI Bus Frequency - */ -extern unsigned int BSP_bus_frequency; -/* - * processor clock frequency - */ -extern unsigned int BSP_processor_frequency; -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; -/* - * The commandline as passed from the bootloader. - */ -extern char *BSP_commandline_string; - -#define BSP_Convert_decrementer( _value ) \ - ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) - -extern rtems_configuration_table BSP_Configuration; -extern void BSP_panic(char *s); -/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ -extern int BSP_disconnect_clock_handler (void); -extern int BSP_connect_clock_handler (void); - -/* clear hostbridge errors - * - * NOTE: The routine returns always (-1) if 'enableMCP==1' - * [semantics needed by libbspExt] if the MCP input is not wired. - * It returns and clears the error bits of the PCI status register. - * MCP support is disabled because: - * a) the 2100 has no raven chip - * b) the raven (2300) would raise machine check interrupts - * on PCI config space access to empty slots. - */ -extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); -extern void BSP_motload_pci_fixup(void); - -struct rtems_bsdnet_ifconfig; - -int -rtems_tsec_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "tse1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_tsec_attach - -/* - * Prototypes for methods called only from .S for dependency tracking - */ -char *save_boot_params( - void *r3, - void *r4, - void *r5, - char *cmdline_start, - char *cmdline_end -); -void zero_bss(void); - -/* - * Prototypes for methods in the BSP that cross file boundaries - */ -extern void BSP_vme_config(void); -extern void BSP_pciConfigDump_early( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/mvme3100/irq/irq.h b/c/src/lib/libbsp/powerpc/mvme3100/irq/irq.h deleted file mode 100644 index 0158e05149..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme3100/irq/irq.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * - * @ingroup powerpc_irq - * - * @brief This include file describe the data structure and the functions - * implemented by RTEMS to write interrupt handlers. - */ - -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by RTEMS to write interrupt handlers. - * - * Copyright (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Adapted for the mvme3100 BSP by T. Straumann, 2007. - */ - -#ifndef BSP_POWERPC_IRQ_H -#define BSP_POWERPC_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 -#include <rtems/irq.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup powerpc_irq Definitions - * - * @ingroup powerpc_mvme3100 - * - * @brief rtems_irq_number Definitions - */ - -/* Must pad number of external sources to 16 because - * of the layout of vector/priority registers in the - * 8540's openpic where there is a gap between - * registers corresponding to external and core sources. - */ -#define BSP_EXT_IRQ_NUMBER (16) -#define BSP_CORE_IRQ_NUMBER (32) - -/* openpic glue code from shared/irq assigns priorities and configures - * initial ISRs for BSP_PCI_IRQ_NUMBER entries (plus ISA stuff on legacy - * boards). Hence PCI_IRQ_NUMBER must also cover the internal sources - * even though they have nothing to do with PCI. - */ -#define BSP_PCI_IRQ_NUMBER (BSP_EXT_IRQ_NUMBER + BSP_CORE_IRQ_NUMBER) -#define BSP_PCI_IRQ_LOWEST_OFFSET (0) -#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) - -#define BSP_CORE_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_EXT_IRQ_NUMBER) -#define BSP_CORE_IRQ_MAX_OFFSET (BSP_CORE_IRQ_LOWEST_OFFSET + BSP_CORE_IRQ_NUMBER - 1) - -/* - * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CORE_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) -/* Misc vectors for OPENPIC irqs (IPI, timers) - */ -#define BSP_MISC_IRQ_NUMBER (8) -#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) - -/* - * Some PCI IRQ symbolic name definition - */ -#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) - -#define BSP_VME0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 0) -#define BSP_VME1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) -#define BSP_VME2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) -#define BSP_VME3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) - -#define BSP_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) -#define BSP_TEMP_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) -#define BSP_PHY_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) -#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 11) - -/* Weird - they provide 3 different IRQ lines per ethernet controller - * but only one shared line for 2 UARTs ??? - */ -#define BSP_UART_COM1_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26) -#define BSP_UART_COM2_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 26) -#define BSP_I2C_IRQ (BSP_CORE_IRQ_LOWEST_OFFSET + 27) - -/* - * Some internal (CORE) name definitions - */ -/* Ethernet (FEC) */ -#define BSP_CORE_IRQ_FEC (BSP_CORE_IRQ_LOWEST_OFFSET + 25) -/* i2c controller */ -#define BSP_CORE_IRQ_I2C (BSP_CORE_IRQ_LOWEST_OFFSET + 27) - -/* - * Some Processor execption handled as RTEMS IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); - -#include <bsp/irq_supp.h> - -#ifdef __cplusplus -}; -#endif - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/mvme3100/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/mvme3100/vme/VMEConfig.h deleted file mode 100644 index 10b424c2a8..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme3100/vme/VMEConfig.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - * @file - * - * @ingroup powerpc_vmeconfig - * - * @brief mvme3100 BSP specific address space configuration parameters - */ - -#ifndef RTEMS_BSP_VME_CONFIG_H -#define RTEMS_BSP_VME_CONFIG_H - -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 2002..2007, - * Stanford Linear Accelerator Center, Stanford University. - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -/* - * NOTE: the BSP (startup/bspstart.c) uses - * hardcoded window lengths that match this - * layout: - */ - -#define _VME_A32_WIN0_ON_PCI 0xc0000000 -#define _VME_CSR_ON_PCI 0xce000000 -#define _VME_A24_ON_PCI 0xcf000000 -#define _VME_A16_ON_PCI 0xcfff0000 - -/* start of the A32 window on the VME bus - * TODO: this should perhaps be a run-time configuration option - */ -#define _VME_A32_WIN0_ON_VME 0x20000000 - -/* if _VME_DRAM_OFFSET is defined, the BSP - * will map the board RAM onto the VME bus, starting - * at _VME_DRAM_OFFSET - */ -#define _VME_DRAM_OFFSET 0xc0000000 - -/* If your BSP requires a non-standard way to configure - * the VME interrupt manager then define the symbol - * - * BSP_VME_INSTALL_IRQ_MGR - * - * to a proper instruction sequence that installs the - * universe interrupt manager. This requires knowledge - * of the wiring between the universe and the PIC (main - * interrupt controller), i.e., which IRQ 'pins' of the - * universe are wired to which 'lines'/inputs at the PIC. - * (consult vmeUniverse.h for more information). - * - * When installing the universe IRQ manager it is also - * possible to specify whether it should try to share - * PIC interrupts with other sources. This might not - * be supported by all BSPs (but the unverse driver - * recognizes that). - * - * If BSP_VME_INSTALL_IRQ_MGR is undefined then - * the default algorithm is used (vme_universe.c): - * - * This default setup uses only a single wire. It reads - * the PIC 'line' from PCI configuration space and assumes - * this to be wired to the first (LIRQ0) IRQ input at the - * universe. The default setup tries to use interrupt - * sharing. - */ - -extern int BSP_VMEInit(void); -extern int BSP_VMEIrqMgrInstall(void); - -/** - * @defgroup powerpc_vme BSP_VME_INSTALL_IRQ_MGR Support - * - * @ingroup powerpc_mvme3100 - * - * @brief BSP_VME_INSTALL_IRQ_MGR Support Package - */ -#define BSP_VME_INSTALL_IRQ_MGR(err) \ - do { \ - err = vmeTsi148InstallIrqMgrAlt(\ - VMETSI148_IRQ_MGR_FLAG_SHARED, /* use shared IRQs */ \ - 0, BSP_VME0_IRQ, \ - 1, BSP_VME1_IRQ, \ - 2, BSP_VME2_IRQ, \ - 3, BSP_VME3_IRQ, \ - -1 /* terminate list */ \ - ); \ - } while (0) - -/* This BSP uses the Tsi148 Driver */ -#define _VME_DRIVER_TSI148 - -#endif diff --git a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h deleted file mode 100644 index e9aaeff844..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h +++ /dev/null @@ -1,810 +0,0 @@ -/* $NetBSD: gtreg.h,v 1.1 2003/03/05 22:08:22 matt Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _DISCOVERY_DEV_GTREG_H_ -#define _DISCOVERY_DEV_GTREG_H_ - -#define GT__BIT(bit) (1U << (bit)) -#define GT__MASK(bit) (GT__BIT(bit) - 1) -#define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) -#define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) -#define GT__INS(new, bit) ((new) << (bit)) - - -/* - * Table 30: CPU Address Decode Register Map - */ -#define GT_SCS0_Low_Decode 0x0008 -#define GT_SCS0_High_Decode 0x0010 -#define GT_SCS1_Low_Decode 0x0208 -#define GT_SCS1_High_Decode 0x0210 -#define GT_SCS2_Low_Decode 0x0018 -#define GT_SCS2_High_Decode 0x0020 -#define GT_SCS3_Low_Decode 0x0218 -#define GT_SCS3_High_Decode 0x0220 -#define GT_CS0_Low_Decode 0x0028 -#define GT_CS0_High_Decode 0x0030 -#define GT_CS1_Low_Decode 0x0228 -#define GT_CS1_High_Decode 0x0230 -#define GT_CS2_Low_Decode 0x0248 -#define GT_CS2_High_Decode 0x0250 -#define GT_CS3_Low_Decode 0x0038 -#define GT_CS3_High_Decode 0x0040 -#define GT_BootCS_Low_Decode 0x0238 -#define GT_BootCS_High_Decode 0x0240 -#define GT_PCI0_IO_Low_Decode 0x0048 -#define GT_PCI0_IO_High_Decode 0x0050 -#define GT_PCI0_Mem0_Low_Decode 0x0058 -#define GT_PCI0_Mem0_High_Decode 0x0060 -#define GT_PCI0_Mem1_Low_Decode 0x0080 -#define GT_PCI0_Mem1_High_Decode 0x0088 -#define GT_PCI0_Mem2_Low_Decode 0x0258 -#define GT_PCI0_Mem2_High_Decode 0x0260 -#define GT_PCI0_Mem3_Low_Decode 0x0280 -#define GT_PCI0_Mem3_High_Decode 0x0288 -#define GT_PCI1_IO_Low_Decode 0x0090 -#define GT_PCI1_IO_High_Decode 0x0098 -#define GT_PCI1_Mem0_Low_Decode 0x00a0 -#define GT_PCI1_Mem0_High_Decode 0x00a8 -#define GT_PCI1_Mem1_Low_Decode 0x00b0 -#define GT_PCI1_Mem1_High_Decode 0x00b8 -#define GT_PCI1_Mem2_Low_Decode 0x02a0 -#define GT_PCI1_Mem2_High_Decode 0x02a8 -#define GT_PCI1_Mem3_Low_Decode 0x02b0 -#define GT_PCI1_Mem3_High_Decode 0x02b8 -#define GT_Internal_Decode 0x0068 -#define GT_CPU0_Low_Decode 0x0290 -#define GT_CPU0_High_Decode 0x0298 -#define GT_CPU1_Low_Decode 0x02c0 -#define GT_CPU1_High_Decode 0x02c8 -#define GT_PCI0_IO_Remap 0x00f0 -#define GT_PCI0_Mem0_Remap_Low 0x00f8 -#define GT_PCI0_Mem0_Remap_High 0x0320 -#define GT_PCI0_Mem1_Remap_Low 0x0100 -#define GT_PCI0_Mem1_Remap_High 0x0328 -#define GT_PCI0_Mem2_Remap_Low 0x02f8 -#define GT_PCI0_Mem2_Remap_High 0x0330 -#define GT_PCI0_Mem3_Remap_Low 0x0300 -#define GT_PCI0_Mem3_Remap_High 0x0338 -#define GT_PCI1_IO_Remap 0x0108 -#define GT_PCI1_Mem0_Remap_Low 0x0110 -#define GT_PCI1_Mem0_Remap_High 0x0340 -#define GT_PCI1_Mem1_Remap_Low 0x0118 -#define GT_PCI1_Mem1_Remap_High 0x0348 -#define GT_PCI1_Mem2_Remap_Low 0x0310 -#define GT_PCI1_Mem2_Remap_High 0x0350 -#define GT_PCI1_Mem3_Remap_Low 0x0318 -#define GT_PCI1_Mem3_Remap_High 0x0358 - - -/* - * Table 31: CPU Control Register Map - */ -#define GT_CPU_Cfg 0x0000 -#define GT_CPU_Mode 0x0120 -#define GT_CPU_Master_Ctl 0x0160 -#define GT_CPU_If_Xbar_Ctl_Low 0x0150 -#define GT_CPU_If_Xbar_Ctl_High 0x0158 -#define GT_CPU_If_Xbar_Timeout 0x0168 -#define GT_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 -#define GT_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 - -/* - * Table 32: CPU Sync Barrier Register Map - */ -#define GT_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) -#define GT_PCI0_Sync_Barrier 0x00c0 -#define GT_PCI1_Sync_Barrier 0x00c8 - -/* - * Table 33: CPU Access Protection Register Map - */ -#define GT_Protect_Low_0 0x0180 -#define GT_Protect_High_0 0x0188 -#define GT_Protect_Low_1 0x0190 -#define GT_Protect_High_1 0x0198 -#define GT_Protect_Low_2 0x01a0 -#define GT_Protect_High_2 0x01a8 -#define GT_Protect_Low_3 0x01b0 -#define GT_Protect_High_3 0x01b8 -#define GT_Protect_Low_4 0x01c0 -#define GT_Protect_High_4 0x01c8 -#define GT_Protect_Low_5 0x01d0 -#define GT_Protect_High_5 0x01d8 -#define GT_Protect_Low_6 0x01e0 -#define GT_Protect_High_6 0x01e8 -#define GT_Protect_Low_7 0x01f0 -#define GT_Protect_High_7 0x01f8 - -/* - * Table 34: Snoop Control Register Map - */ -#define GT_Snoop_Base_0 0x0380 -#define GT_Snoop_Top_0 0x0388 -#define GT_Snoop_Base_1 0x0390 -#define GT_Snoop_Top_1 0x0398 -#define GT_Snoop_Base_2 0x03a0 -#define GT_Snoop_Top_2 0x03a8 -#define GT_Snoop_Base_3 0x03b0 -#define GT_Snoop_Top_3 0x03b8 - -/* - * Table 35: CPU Error Report Register Map - */ -#define GT_CPU_Error_Address_Low 0x0070 -#define GT_CPU_Error_Address_High 0x0078 -#define GT_CPU_Error_Data_Low 0x0128 -#define GT_CPU_Error_Data_High 0x0130 -#define GT_CPU_Error_Parity 0x0138 -#define GT_CPU_Error_Cause 0x0140 -#define GT_CPU_Error_Mask 0x0148 - -#define GT_DecodeAddr_SET(g, r, v) \ - do { \ - gt_read((g), GT_Internal_Decode); \ - gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ - while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ - } while (0) - -#define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) -#define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) - -#define GT_MPP_Control0 0xf000 -#define GT_MPP_Control1 0xf004 -#define GT_MPP_Control2 0xf008 -#define GT_MPP_Control3 0xf00c - -/* <skf> added for GT64260 */ -#define GT_MPP_SerialPortMultiplex 0xf010 - -#define GT_GPP_IO_Control 0xf100 -#define GT_GPP_Level_Control 0xf110 -#define GT_GPP_Value 0xf104 -#define GT_GPP_Interrupt_Cause 0xf108 -#define GT_GPP_Interrupt_Mask 0xf10c -/* - * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 - * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 - * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 - * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 - * Table 44: CS[0]* Low Decode Address, Offset: 0x028 - * Table 46: CS[1]* Low Decode Address, Offset: 0x228 - * Table 48: CS[2]* Low Decode Address, Offset: 0x248 - * Table 50: CS[3]* Low Decode Address, Offset: 0x038 - * Table 52: BootCS* Low Decode Address, Offset: 0x238 - * Table 75: CPU 0 Low Decode Address, Offset: 0x290 - * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 - * - * 11:00 LowAddr SCS[0] Base Address - * 31:12 Reserved Must be 0. - */ - -/* - * Table 37: SCS[0]* High Decode Address, Offset: 0x010 - * Table 39: SCS[1]* High Decode Address, Offset: 0x210 - * Table 41: SCS[2]* High Decode Address, Offset: 0x020 - * Table 43: SCS[3]* High Decode Address, Offset: 0x220 - * Table 45: CS[0]* High Decode Address, Offset: 0x030 - * Table 47: CS[1]* High Decode Address, Offset: 0x230 - * Table 49: CS[2]* High Decode Address, Offset: 0x250 - * Table 51: CS[3]* High Decode Address, Offset: 0x040 - * Table 53: BootCS* High Decode Address, Offset: 0x240 - * Table 76: CPU 0 High Decode Address, Offset: 0x298 - * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 - * - * 11:00 HighAddr SCS[0] Top Address - * 31:12 Reserved - */ - -/* - * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 - * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 - * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 - * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 - * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 - * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 - * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 - * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 - * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 - * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 - * - * 11:00 LowAddr PCI IO/Memory Space Base Address - * 23:12 Reserved - * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; - * 1: No swapping; 2: Both byte and word swap; - * 3: Word swap; 4..7: Reserved) - * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when - * configured to 64-bit PCI bus and not I/O) - * 0: Assert s REQ64* only when transaction - * is longer than 64-bits. - * 1: Always assert REQ64*. - * 31:28 Reserved - */ -#define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) -#define GT_PCISwap_ByteSwap 0 -#define GT_PCISwap_NoSwap 1 -#define GT_PCISwap_ByteWordSwap 2 -#define GT_PCISwap_WordSwap 3 -#define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) - -/* - * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 - * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 - * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 - * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 - * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 - * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 - * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 - * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 - * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 - * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 - * - * 11:00 HighAddr PCI_0 I/O Space Top Address - * 31:12 Reserved - */ - -/* - * Table 74: Internal Space Decode, Offset: 0x068 - * 15:00 IntDecode GT64260 Internal Space Base Address - * 23:16 Reserved - * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. - * NOTE: Reserved for Galileo Technology usage. - * Relevant only for PCI master configuration - * transactions on the PCI bus. - * 31:27 Reserved - */ - -/* - * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 - * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 - * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 - * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 - * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 - * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 - * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 - * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 - * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 - * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 - * - * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) - * 31:12 Reserved - */ - -/* - * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 - * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 - * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 - * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 - * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 - * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 - * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 - * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 - * - * 31:00 Remap PCI Memory Address Remap (high 32 bits) - */ - -/* - * Table 97: CPU Configuration, Offset: 0x000 - * 07:00 NoMatchCnt CPU Address Miss Counter - * 08:08 NoMatchCntEn CPU Address Miss Counter Enable - * NOTE: Relevant only if multi-GT is enabled. - * (0: Disabled; 1: Enabled) - * 09:09 NoMatchCntExt CPU address miss counter MSB - * 10:10 Reserved - * 11:11 AACKDelay Address Acknowledge Delay - * 0: AACK* is asserted one cycle after TS*. - * 1: AACK* is asserted two cycles after TS*. - * 12:12 Endianess Must be 0 - * NOTE: The GT64260 does not support the PowerPC - * Little Endian convention - * 13:13 Pipeline Pipeline Enable - * 0: Disabled. The GT64260 will not respond with - * AACK* to a new CPU transaction, before the - * previous transaction data phase completes. - * 1: Enabled. - * 14:14 Reserved - * 15:15 TADelay Transfer Acknowledge Delay - * 0: TA* is asserted one cycle after AACK* - * 1: TA* is asserted two cycles after AACK* - * 16:16 RdOOO Read Out of Order Completion - * 0: Not Supported, Data is always returned in - * order (DTI[0-2] is always driven - * 1: Supported - * 17:17 StopRetry Relevant only if PCI Retry is enabled - * 0: Keep Retry all PCI transactions targeted - * to the GT64260. - * 1: Stop Retry of PCI transactions. - * 18:18 MultiGTDec Multi-GT Address Decode - * 0: Normal address decoding - * 1: Multi-GT address decoding - * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... - * 0: is not checked. (Not connected) - * 1: is checked (Connected) - * 21:20 Reserved - * 22:22 PErrProp Parity Error Propagation - * 0: GT64260 always drives good parity on - * DP[0-7] during CPU reads. - * 1: GT64260 drives bad parity on DP[0-7] in case - * the read response from the target interface - * comes with erroneous data indication - * (e.g. ECC error from SDRAM interface). - * 25:23 Reserved - * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... - * 0: is not checked. (Not connected) - * 1: is checked (Connected) - * 27:27 RemapWrDis Address Remap Registers Write Control - * 0: Write to Low Address decode register. - * Results in writing of the corresponding - * Remap register. - * 1: Write to Low Address decode register. No - * affect on the corresponding Remap register. - * 28:28 ConfSBDis Configuration Read Sync Barrier Disable - * 0: enabled; 1: disabled - * 29:29 IOSBDis I/O Read Sync Barrier Disable - * 0: enabled; 1: disabled - * 30:30 ClkSync Clocks Synchronization - * 0: The CPU interface is running with SysClk, - * which is asynchronous to TClk. - * 1: The CPU interface is running with TClk. - * 31:31 Reserved - */ -#define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) -#define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) -#define GT_CPUCfg_NoMatchCntExt GT__BIT(10) -#define GT_CPUCfg_AACKDelay GT__BIT(11) -#define GT_CPUCfg_Endianess GT__BIT(12) -#define GT_CPUCfg_Pipeline GT__BIT(13) -#define GT_CPUCfg_TADelay GT__BIT(15) -#define GT_CPUCfg_RdOOO GT__BIT(16) -#define GT_CPUCfg_StopRetry GT__BIT(17) -#define GT_CPUCfg_MultiGTDec GT__BIT(18) -#define GT_CPUCfg_DPValid GT__BIT(19) -#define GT_CPUCfg_PErrProp GT__BIT(22) -#define GT_CPUCfg_APValid GT__BIT(26) -#define GT_CPUCfg_RemapWrDis GT__BIT(27) -#define GT_CPUCfg_ConfSBDis GT__BIT(28) -#define GT_CPUCfg_IOSBDis GT__BIT(29) -#define GT_CPUCfg_ClkSync GT__BIT(30) - -/* - * Table 98: CPU Mode, Offset: 0x120, Read only - * 01:00 MultiGTID Multi-GT ID - * Represents the ID to which the GT64260 responds - * to during a multi-GT address decoding period. - * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration - * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions - * 07:04 CPUType - * 0x0-0x3: Reserved - * 0x4: 64-bit PowerPC CPU, 60x bus - * 0x5: 64-bit PowerPC CPU, MPX bus - * 0x6-0xf: Reserved - * 31:08 Reserved - */ -#define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) -#define GT_CPUMode_MultiGT GT__BIT(2) -#define GT_CPUMode_RetryEn GT__BIT(3) -#define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) - -/* - * Table 99: CPU Master Control, Offset: 0x160 - * 07:00 Reserved - * 08:08 IntArb CPU Bus Internal Arbiter Enable - * NOTE: Only relevant to 60x bus mode. When - * running MPX bus, the GT64260 internal - * arbiter must be used. - * 0: Disabled. External arbiter is required. - * 1: Enabled. Use the GT64260 CPU bus arbiter. - * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control - * NOTE: This bit must be set to 1. It is reserved - * for Galileo Technology usage. - * 0: Enable internal bus sharing between master - * and slave interfaces. - * 1: Disable internal bus sharing between master - * and slave interfaces. - * 10:10 MWrTrig Master Write Transaction Trigger - * 0: With first valid write data - * 1: With last valid write data - * 11:11 MRdTrig Master Read Response Trigger - * 0: With first valid read data - * 1: With last valid read data - * 12:12 CleanBlock Clean Block Snoop Transaction Support - * 0: CPU does not support clean block (603e,750) - * 1: CPU supports clean block (604e,G4) - * 13:13 FlushBlock Flush Block Snoop Transaction Support - * 0: CPU does not support flush block (603e,750) - * 1: CPU supports flush block (604e,G4) - * 31:14 Reserved - */ -#define GT_CPUMstrCtl_IntArb GT__BIT(8) -#define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) -#define GT_CPUMstrCtl_MWrTrig GT__BIT(10) -#define GT_CPUMstrCtl_MRdTrig GT__BIT(11) -#define GT_CPUMstrCtl_CleanBlock GT__BIT(12) -#define GT_CPUMstrCtl_FlushBlock GT__BIT(13) - -#define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ -#define GT_ArbSlice_DEVICE 0x1 /* Device request */ -#define GT_ArbSlice_NULL 0x2 /* NULL request */ -#define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ -#define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ -#define GT_ArbSlice_COMM 0x5 /* Comm unit access */ -#define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ -#define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ - /* 0x8-0xf: Reserved */ - -/* Pass in the slice number (from 0..16) as 'n' - */ -#define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) - -/* - * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 - * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter - * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter - * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter - * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter - * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter - * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter - * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter - * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter - */ - -/* - * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 - * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter - * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter - * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter - * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter - * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter - * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter - * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter - * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter - */ - -/* - * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 - * NOTE: Reserved for Galileo Technology usage. - * 07:00 Timeout Crossbar Arbiter Timeout Preset Value - * 15:08 Reserved - * 16:16 TimeoutEn Crossbar Arbiter Timer Enable - * (0: Enable; 1: Disable) - * 31:17 Reserved - */ - -/* - * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 - * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter - * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter - * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter - * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter - * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter - * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter - * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter - * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter - */ -/* - * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 - * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter - * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter - * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter - * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter - * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter - * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter - * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter - * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter - */ - -/* - * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 - * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 - * NOTE: The read data is random and should be ignored. - * 31:00 SyncBarrier A CPU read from this register creates a - * synchronization barrier cycle. - */ - -/* - * Table 107: CPU Protect Address 0 Low, Offset: 0x180 - * Table 109: CPU Protect Address 1 Low, Offset: 0x190 - * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 - * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 - * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 - * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 - * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 - * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 - * - * 11:00 LowAddr CPU Protect Region Base Address - * Corresponds to address bits[31:20]. - * 15:12 Reserved. Must be 0 - * 16:16 AccProtect CPU Access Protect - * Access is (0: allowed; 1: forbidden) - * 17:17 WrProtect CPU Write Protect - * Writes are (0: allowed; 1: forbidden) - * 18:18 CacheProtect CPU caching protect. Caching (block read) - * is (0: allowed; 1: forbidden) - * 31:19 Reserved - */ -#define GT_CPU_AccProtect GT__BIT(16) -#define GT_CPU_WrProtect GT__BIT(17) -#define GT_CPU_CacheProtect GT__BIT(18) - -/* - * Table 108: CPU Protect Address 0 High, Offset: 0x188 - * Table 110: CPU Protect Address 1 High, Offset: 0x198 - * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 - * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 - * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 - * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 - * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 - * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 - * - * 11:00 HighAddr CPU Protect Region Top Address - * Corresponds to address bits[31:20] - * 31:12 Reserved - */ - -/* - * Table 123: Snoop Base Address 0, Offset: 0x380 - * Table 125: Snoop Base Address 1, Offset: 0x390 - * Table 127: Snoop Base Address 2, Offset: 0x3a0 - * Table 129: Snoop Base Address 3, Offset: 0x3b0 - * - * 11:00 LowAddr Snoop Region Base Address [31:20] - * 15:12 Reserved Must be 0. - * 17:16 Snoop Snoop Type - * 0x0: No Snoop - * 0x1: Snoop to WT region - * 0x2: Snoop to WB region - * 0x3: Reserved - * 31:18 Reserved - */ -#define GT_Snoop_GET(v) GT__EXT((v), 16, 2) -#define GT_Snoop_INS(v) GT__INS((v), 16) -#define GT_Snoop_None 0 -#define GT_Snoop_WT 1 -#define GT_Snoop_WB 2 - - -/* - * Table 124: Snoop Top Address 0, Offset: 0x388 - * Table 126: Snoop Top Address 1, Offset: 0x398 - * Table 128: Snoop Top Address 2, Offset: 0x3a8 - * Table 130: Snoop Top Address 3, Offset: 0x3b8 - * 11:00 HighAddr Snoop Region Top Address [31:20] - * 31:12 Reserved - */ - - -/* - * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. - * In case of multiple errors, only the first one is latched. New error - * report latching is enabled only after the CPU Error Address Low register - * is being read. - * 31:00 ErrAddr Latched address bits [31:0] of a CPU - * transaction in case of: - * o illegal address (failed address decoding) - * o access protection violation - * o bad data parity - * o bad address parity - * Upon address latch, no new address are - * registered (due to additional error condition), - * until the register is being read. - */ - -/* - * Table 132: CPU Error Address High, Offset: 0x078, Read Only. - * Once data is latched, no new data can be registered (due to additional - * error condition), until CPU Error Low Address is being read (which - * implies, it should be the last being read by the interrupt handler). - * 03:00 Reserved - * 07:04 ErrPar Latched address parity bits in case - * of bad CPU address parity detection. - * 31:08 Reserved - */ -#define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) - -/* - * Table 133: CPU Error Data Low, Offset: 0x128, Read only. - * 31:00 PErrData Latched data bits [31:0] in case of bad data - * parity sampled on write transactions or on - * master read transactions. - */ - -/* - * Table 134: CPU Error Data High, Offset: 0x130, Read only. - * 31:00 PErrData Latched data bits [63:32] in case of bad data - * parity sampled on write transactions or on - * master read transactions. - */ - -/* - * Table 135: CPU Error Parity, Offset: 0x138, Read only. - * 07:00 PErrPar Latched data parity bus in case of bad data - * parity sampled on write transactions or on - * master read transactions. - * 31:10 Reserved - */ -#define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) - -/* - * Table 136: CPU Error Cause, Offset: 0x140 - * Bits[7:0] are clear only. A cause bit is set upon an error condition - * occurrence. Write a 0 value to clear the bit. Writing a 1 value has - * no affect. - * 00:00 AddrOut CPU Address Out of Range - * 01:01 AddrPErr Bad Address Parity Detected - * 02:02 TTErr Transfer Type Violation. - * The CPU attempts to burst (read or write) to an - * internal register. - * 03:03 AccErr Access to a Protected Region - * 04:04 WrErr Write to a Write Protected Region - * 05:05 CacheErr Read from a Caching protected region - * 06:06 WrDataPErr Bad Write Data Parity Detected - * 07:07 RdDataPErr Bad Read Data Parity Detected - * 26:08 Reserved - * 31:27 Sel Specifies the error event currently being - * reported in Error Address, Error Data, and - * Error Parity registers. - * 0x0: AddrOut - * 0x1: AddrPErr - * 0x2: TTErr - * 0x3: AccErr - * 0x4: WrErr - * 0x5: CacheErr - * 0x6: WrDataPErr - * 0x7: RdDataPErr - * 0x8-0x1f: Reserved - */ -#define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) -#define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) -#define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) -#define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) -#define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) -#define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) -#define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) -#define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) - -#define GT_CPUError_Sel_AddrOut 0 -#define GT_CPUError_Sel_AddrPErr 1 -#define GT_CPUError_Sel_TTErr 2 -#define GT_CPUError_Sel_AccErr 3 -#define GT_CPUError_Sel_WrErr 4 -#define GT_CPUError_Sel_CacheErr 5 -#define GT_CPUError_Sel_WrDataPErr 6 -#define GT_CPUError_Sel_RdDataPErr 7 - -#define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) - -/* - * Table 137: CPU Error Mask, Offset: 0x148 - * 00:00 AddrOut If set to 1, enables AddrOut interrupt. - * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. - * 02:02 TTErr If set to 1, enables TTErr interrupt. - * 03:03 AccErr If set to 1, enables AccErr interrupt. - * 04:04 WrErr If set to 1, enables WrErr interrupt. - * 05:05 CacheErr If set to 1, enables CacheErr interrupt. - * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. - * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. - * 31:08 Reserved - */ - -/* Comm Unit Arbiter Control */ -#define GT_CommUnitArb_Ctrl 0xf300 /*<skf>*/ -/* - * Comm Unit Interrupt registers - */ -#define GT_CommUnitIntr_Cause 0xf310 -#define GT_CommUnitIntr_Mask 0xf314 -#define GT_CommUnitIntr_ErrAddr 0xf318 - -#define GT_CommUnitIntr_E0 0x00000007 -#define GT_CommUnitIntr_E1 0x00000070 -#define GT_CommUnitIntr_E2 0x00000700 -#define GT_CommUnitIntr_S0 0x00070000 -#define GT_CommUnitIntr_S1 0x00700000 -#define GT_CommUnitIntr_Sel 0x70000000 - -/* - * SDRAM Error Report (ECC) Registers - */ -#define GT_ECC_Data_Lo 0x484 /* latched Error Data (low) */ -#define GT_ECC_Data_Hi 0x480 /* latched Error Data (high) */ -#define GT_ECC_Addr 0x490 /* latched Error Address */ -#define GT_ECC_Rec 0x488 /* latched ECC code from SDRAM */ -#define GT_ECC_Calc 0x48c /* latched ECC code from SDRAM */ -#define GT_ECC_Ctl 0x494 /* ECC Control */ -#define GT_ECC_Count 0x498 /* ECC 1-bit error count */ - -/* - * Watchdog Registers - */ -#define GT_WDOG_Config 0xb410 -#define GT_WDOG_Value 0xb414 -#define GT_WDOG_Value_NMI GT__MASK(24) -#define GT_WDOG_Config_Preset GT__MASK(24) -#define GT_WDOG_Config_Ctl1a GT__BIT(24) -#define GT_WDOG_Config_Ctl1b GT__BIT(25) -#define GT_WDOG_Config_Ctl2a GT__BIT(26) -#define GT_WDOG_Config_Ctl2b GT__BIT(27) -#define GT_WDOG_Config_Enb GT__BIT(31) - -#define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) -#define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) - -/* - * Device Bus Interrupts - */ -#define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ -#define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ -#define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ - -/* - * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK - */ -#define GT_DEVBUS_DBurstErr GT__BIT(0) -#define GT_DEVBUS_DRdyErr GT__BIT(1) -#define GT_DEVBUS_Sel GT__BIT(27) -#define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) - -/* TWSI Interface - TWSI Interface Registers <skf> */ -#define TWSI_SLV_ADDR 0xc000 -#define TWSI_EXT_SLV_ADDR 0xc010 -#define TWSI_DATA 0xc004 -#define TWSI_CTRL 0xc008 -#define TWSI_STATUS 0xc00c -#define TWSI_BAUDE_RATE 0xc00c -#define TWSI_SFT_RST 0xc01c - -/* Section 25.2 : Table 734 <skf> */ - -#define GT64260_MAIN_INT_CAUSE_LO 0xc18 /* read Only */ -#define GT64260_MAIN_INT_CAUSE_HI 0xc68 /* read Only */ -#define GT64260_CPU_INT_MASK_LO 0xc1c -#define GT64260_CPU_INT_MASK_HI 0xc6c -#define GT64260_CPU_SEL_CAUSE 0xc70 /* read Only */ -#define GT_PCI0_INT_MASK_LO 0xc24 -#define GT_PCI0_INT_MASK_HI 0xc64 -#define GT_PCI0_SEL_CAUSE 0xc74 /* read Only */ -#define GT_PCI1_INT_MASK_LO 0xca4 -#define GT_PCI1_INT_MASK_HI 0xce4 -#define GT_PCI1_SEL_CAUSE 0xcf4 /* read Only */ -#define GT_CPU_INT0_MASK 0xe60 -#define GT_CPU_INT1_MASK 0xe64 -#define GT_CPU_INT2_MASK 0xe68 -#define GT_CPU_INT3_MASK 0xe6c - -#endif /* !_DISCOVERY_DEV_GTREG_H */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h deleted file mode 100644 index 3a65ce21da..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. - */ - -#ifndef LIBBSP_POWERPC_MVME5500_BSP_H -#define LIBBSP_POWERPC_MVME5500_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <libcpu/io.h> -#include <bsp/vectors.h> - -/* Board type */ -typedef enum { - undefined = 0, - MVME5500, - MVME6100 -} BSP_BoardTypes; - -BSP_BoardTypes BSP_getBoardType(void); - -/* Board type */ -typedef enum { - Undefined, - UNIVERSE2, - TSI148, -} BSP_VMEchipTypes; - -BSP_VMEchipTypes BSP_getVMEchipType(void); - -/* The version of Discovery system controller */ - -typedef enum { - notdefined, - GT64260A, - GT64260B, - MV64360, -} DiscoveryChipVersion; - -DiscoveryChipVersion BSP_getDiscoveryChipVersion(void); - -#define _256M 0x10000000 -#define _512M 0x20000000 - -#define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ -#define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ - -#define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base - */ -#define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ - -/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ -#define _IO_BASE GT64x60_REG_BASE - -#define BSP_NVRAM_BASE_ADDR 0xf1110000 - -#define BSP_RTC_INTA_REG 0x7ff0 -#define BSP_RTC_SECOND 0x7ff2 -#define BSP_RTC_MINUTE 0x7ff3 -#define BSP_RTC_HOUR 0x7ff4 -#define BSP_RTC_DATE 0x7ff5 -#define BSP_RTC_INTERRUPTS 0x7ff6 -#define BSP_RTC_WATCHDOG 0x7ff7 - -/* PCI0 Domain I/O space */ -#define PCI0_IO_BASE 0xf0000000 -#define PCI1_IO_BASE 0xf0800000 - -/* PCI 0 memory space as seen from the CPU */ -#define PCI0_MEM_BASE 0x80000000 -#define PCI_MEM_BASE 0 /* glue for vmeUniverse */ -#define PCI_MEM_BASE_ADJUSTMENT 0 - -/* address of our ram on the PCI bus */ -#define PCI_DRAM_OFFSET 0 - -/* PCI 1 memory space as seen from the CPU */ -#define PCI1_MEM_BASE 0xe0000000 -#define PCI1_MEM_SIZE 0x10000000 - -/* Needed for hot adding via PMCspan on the PCI0 local bus. - * This is board dependent, only because mvme5500 - * supports hot adding and has more than one local PCI - * bus. - */ -#define BSP_MAX_PCI_BUS_ON_PCI0 8 -#define BSP_MAX_PCI_BUS_ON_PCI1 2 -#define BSP_MAX_PCI_BUS (BSP_MAX_PCI_BUS_ON_PCI0+BSP_MAX_PCI_BUS_ON_PCI1) - - -/* The glues to Till's vmeUniverse, although the name does not - * actually reflect the relevant architect of the MVME5500. - */ -#define BSP_PCI_IRQ0 BSP_GPP_IRQ_LOWEST_OFFSET - -/* - * confdefs.h overrides for this BSP: - * - Interrupt stack space is not minimum if defined. - */ -#define BSP_INTERRUPT_STACK_SIZE (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */ - -/* uart.c uses out_8 instead of outb */ -#define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 -#define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 - -#define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ -#define BSP_UART_BAUD_BASE 115200 - -/* - * Total memory using RESIDUAL DATA - */ -extern unsigned int BSP_mem_size; -/* - * PCI Bus Frequency - */ -extern unsigned int BSP_bus_frequency; -/* - * processor clock frequency - */ -extern unsigned int BSP_processor_frequency; -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; - -#define BSP_Convert_decrementer( _value ) \ - ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) - -extern void BSP_panic(char *s); -extern void bsp_reset(void); -/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ -extern int BSP_disconnect_clock_handler(void); -extern int BSP_connect_clock_handler(void); - -unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); - -/* - * Prototypes for methods called only from .S for dependency tracking - */ -char *save_boot_params( - void *r3, - void *r4, - void *r5, - char *cmdline_start, - char *cmdline_end -); -void zero_bss(void); - -/* - * Prototypes for methods in the BSP that cross file boundaries - */ -uint32_t probeMemoryEnd(void); -void pci_interface(void); -void BSP_printPicIsrTbl(void); -int I2Cread_eeprom( - unsigned char I2cBusAddr, - uint32_t devA2A1A0, - uint32_t AddrBytes, - unsigned char *pBuff, - uint32_t numBytes -); - -#if 0 -#define RTEMS_BSP_NETWORK_DRIVER_NAME "gt1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_GT64260eth_driver_attach -#else -#define RTEMS_BSP_NETWORK_DRIVER_NAME "wmG1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach -#endif - -extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); - -#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() - -static inline void lwmemBar(void) -{ - __asm__ volatile("lwsync":::"memory"); -} - -static inline void io_flush(void) -{ - __asm__ volatile("isync":::"memory"); -} - -static inline void memBar(void) -{ - __asm__ volatile("sync":::"memory"); -} - -static inline void ioBar(void) -{ - __asm__ volatile("eieio":::"memory"); -} - -#endif - -#endif /* !ASM */ diff --git a/c/src/lib/libbsp/powerpc/mvme5500/include/tm27.h b/c/src/lib/libbsp/powerpc/mvme5500/include/tm27.h deleted file mode 100644 index 2a80618cfb..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/include/tm27.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * @file - * @ingroup powerpc_mvme5500 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/irq.h> - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -void nullFunc() {} -static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, - 0, - (rtems_irq_enable)nullFunc, - (rtems_irq_disable)nullFunc, - (rtems_irq_is_enabled) nullFunc}; - -void Install_tm27_vector(void (*_handler)()) -{ - clockIrqData.hdl = _handler; - if (!BSP_install_rtems_irq_handler (&clockIrqData)) { - printk("Error installing clock interrupt handler!\n"); - rtems_fatal_error_occurred(1); - } -} - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 1; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - - -#define Clear_tm27_intr() \ - do { \ - uint32_t _clicks = 0xffffffff; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - uint32_t _msr = 0; \ - _ISR_Set_level( 0 ); \ - __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - _msr |= 0x8002; \ - __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h deleted file mode 100644 index 6704c2f626..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h +++ /dev/null @@ -1,137 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Copyright 2004, 2005 Brookhaven National Laboratory and - * Shuchen Kate Feng <feng1@bnl.gov> - * - * - modified shared/irq/irq.h for Mvme5500 (no ISA devices/PIC) - * - Discovery GT64260 interrupt controller instead of 8259. - * - Added support for software IRQ priority levels. - * - modified to optimize the IRQ latency and handling - */ - -#ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H -#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 -#include <rtems/irq.h> - -#ifndef ASM - -#define OneTierIrqPrioTbl 1 - -/* - * Symbolic IRQ names and related definitions. - */ - -/* leave the ISA symbols in there, so we can reuse shared/irq.c - * Also, we start numbering PCI irqs at 16 because the OPENPIC - * driver relies on this when mapping irq number <-> vectors - * (OPENPIC_VEC_SOURCE in openpic.h) - */ - - /* See section 25.2 , Table 734 of GT64260 controller - * Main Interrupt Cause Low register - */ -#define BSP_MICL_IRQ_NUMBER (32) -#define BSP_MICL_IRQ_LOWEST_OFFSET (0) -#define BSP_MICL_IRQ_MAX_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET + BSP_MICL_IRQ_NUMBER -1) - /* - * Main Interrupt Cause High register - */ -#define BSP_MICH_IRQ_NUMBER (32) -#define BSP_MICH_IRQ_LOWEST_OFFSET (BSP_MICL_IRQ_MAX_OFFSET+1) -#define BSP_MICH_IRQ_MAX_OFFSET (BSP_MICH_IRQ_LOWEST_OFFSET + BSP_MICH_IRQ_NUMBER -1) - /* External GPP Interrupt assignements - */ -#define BSP_GPP_IRQ_NUMBER (32) -#define BSP_GPP_IRQ_LOWEST_OFFSET (BSP_MICH_IRQ_MAX_OFFSET+1) -#define BSP_GPP_IRQ_MAX_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET + BSP_GPP_IRQ_NUMBER - 1) - - /* - * PowerPc exceptions handled as interrupt where a rtems managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - - /* allow a couple of vectors for VME and counter/timer irq sources etc. - * This is probably not needed any more. - */ -#define BSP_MISC_IRQ_NUMBER (30) -#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) - - /* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) -#define BSP_MAIN_IRQ_NUMBER (64) -#define BSP_PIC_IRQ_NUMBER (96) -#define BSP_LOWEST_OFFSET (BSP_MICL_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) - - /* Main CPU interrupt cause (Low) */ -#define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8) -#define BSP_MAIN_PCI0_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+12) -#define BSP_MAIN_PCI0_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+13) -#define BSP_MAIN_PCI0_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+14) -#define BSP_MAIN_PCI0_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+15) -#define BSP_MAIN_PCI1_7_0 (BSP_MICL_IRQ_LOWEST_OFFSET+16) -#define BSP_MAIN_PCI1_15_8 (BSP_MICL_IRQ_LOWEST_OFFSET+18) -#define BSP_MAIN_PCI1_23_16 (BSP_MICL_IRQ_LOWEST_OFFSET+19) -#define BSP_MAIN_PCI1_31_24 (BSP_MICL_IRQ_LOWEST_OFFSET+20) - - - /* Main CPU interrupt cause (High) */ -#define BSP_MAIN_ETH0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET) -#define BSP_MAIN_ETH1_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+1) -#define BSP_MAIN_ETH2_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+2) -#define BSP_MAIN_GPP7_0_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+24) -#define BSP_MAIN_GPP15_8_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+25) -#define BSP_MAIN_GPP23_16_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+26) -#define BSP_MAIN_GPP31_24_IRQ (BSP_MICH_IRQ_LOWEST_OFFSET+27) - - /* on the MVME5500, these are the GT64260B external GPP0 interrupt */ -#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET) -#define BSP_UART_COM2_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) -#define BSP_UART_COM1_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET) -#define BSP_GPP8_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+8) -#define BSP_GPP_PMC1_INTA (BSP_GPP8_IRQ_OFFSET) -#define BSP_GPP16_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+16) -#define BSP_GPP24_IRQ_OFFSET (BSP_GPP_IRQ_LOWEST_OFFSET+24) -#define BSP_GPP_VME_VLINT0 (BSP_GPP_IRQ_LOWEST_OFFSET+12) -#define BSP_GPP_VME_VLINT1 (BSP_GPP_IRQ_LOWEST_OFFSET+13) -#define BSP_GPP_VME_VLINT2 (BSP_GPP_IRQ_LOWEST_OFFSET+14) -#define BSP_GPP_VME_VLINT3 (BSP_GPP_IRQ_LOWEST_OFFSET+15) -#define BSP_GPP_PMC2_INTA (BSP_GPP_IRQ_LOWEST_OFFSET+16) -#define BSP_GPP_82544_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+20) -#define BSP_GPP_WDT_NMI_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+24) -#define BSP_GPP_WDT_EXP_IRQ (BSP_GPP_IRQ_LOWEST_OFFSET+25) - - /* - * Some Processor execption handled as rtems IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); - -#include <bsp/irq_supp.h> - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h b/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h deleted file mode 100644 index 74751f6088..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NetBSD: gtpcireg.h,v 1.2 2003/03/24 17:03:18 matt Exp $ */ - -/* - * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Allegro Networks, Inc., and Wasabi Systems, Inc. - * 4. The name of Allegro Networks, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * 5. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND - * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#define PCI_ARBCTL_EN (1<<31) - -#define PCI_COMMAND_SB_DIS 0x2000 /* PCI configuration read will stop - * acting as sync barrier transactin - */ - -#define PCI_MEM_BASE_ADDR PCI_BASE_ADDRESS_4 - -#define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 - -#define PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */ - -#define PCI_BARE_IntMemEn 0x200 - -#define PCI_ACCCTLBASEL_PrefetchEn 0x0001000 -#define PCI_ACCCTLBASEL_RdPrefetch 0x0010000 -#define PCI_ACCCTLBASEL_RdLinePrefetch 0x0020000 -#define PCI_ACCCTLBASEL_RdMulPrefetch 0x0040000 -#define PCI_ACCCTLBASEL_WBurst_8_QW 0x0100000 -#define PCI_ACCCTLBASEL_PCISwap_NoSwap 0x1000000 - -#define PCI0_P2P_CONFIG 0x1d14 -#define PCI_SNOOP_BASE0_LOW 0x1f00 -#define PCI_SNOOP_BASE0_HIGH 0x1f04 -#define PCI_SNOOP_TOP0 0x1f08 - -#define PCI0_SCS0_BAR_SIZE 0x0c08 -#define PCI0_SCS1_BAR_SIZE 0x0d08 -#define PCI0_SCS2_BAR_SIZE 0x0c0c -#define PCI0_SCS3_BAR_SIZE 0x0d0c - -#define PCI0_BASE_ADDR_REG_ENABLE 0x0c3c -#define PCI0_ARBITER_CNTL 0x1d00 -#define PCI0_ACCESS_CNTL_BASE0_LOW 0x1e00 -#define PCI0_ACCESS_CNTL_BASE0_HIGH 0x1e04 -#define PCI0_ACCESS_CNTL_BASE0_TOP 0x1e08 - -#define PCI0_ACCESS_CNTL_BASE1_LOW 0x1e10 -#define PCI0_ACCESS_CNTL_BASE1_HIGH 0x1e14 -#define PCI0_ACCESS_CNTL_BASE1_TOP 0x1e18 - -#define PCI1_BASE_ADDR_REG_ENABLE 0x0cbc -#define PCI1_ARBITER_CNTL 0x1d80 -#define PCI1_ACCESS_CNTL_BASE0_LOW 0x1e80 -#define PCI1_ACCESS_CNTL_BASE0_HIGH 0x1e84 -#define PCI1_ACCESS_CNTL_BASE0_TOP 0x1e88 - -#define PCI1_ACCESS_CNTL_BASE1_LOW 0x1e90 -#define PCI1_ACCESS_CNTL_BASE1_HIGH 0x1e94 -#define PCI1_ACCESS_CNTL_BASE1_TOP 0x1e98 - -#define PCI_SNOOP_BASE1_LOW 0x1f10 -#define PCI_SNOOP_BASE1_HIGH 0x1f14 -#define PCI_SNOOP_TOP1 0x1f18 - -#define PCI0_CMD_CNTL 0xc00 - -#define PCI1_P2P_CONFIG 0x1d94 -#define PCI1_CMD_CNTL 0xc80 -#define PCI1_CONFIG_ADDR 0xc78 -#define PCI1_CONFIG_DATA 0xc7c diff --git a/c/src/lib/libbsp/powerpc/mvme5500/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/mvme5500/vme/VMEConfig.h deleted file mode 100644 index ecc5789899..0000000000 --- a/c/src/lib/libbsp/powerpc/mvme5500/vme/VMEConfig.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef RTEMS_BSP_VME_CONFIG_H -#define RTEMS_BSP_VME_CONFIG_H -/* VMEConfig.h, S. Kate Feng modified it for MVME5500 3/04 - * - * May 2011 : Use the VME shared IRQ handlers. - * - * It seems that the implementation of VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND - * is not fully developed. The UNIV_REGOFF_VCSR_BS is defined for VME64 - * specification, which does not apply to a VME32 crate. In order to avoid - * spurious VME interrupts, a better and more universal solution is - * to flush the vmeUniverse FIFO by reading a register back within the - * users' Interrupt Service Routine (ISR) before returning. - * - * Some devices might require the ISR to issue an interrupt status READ - * after its IRQ is cleared, but before its corresponding interrupt - * is enabled again. - * - */ - -/* - * Prototypes - */ -int BSP_VMEInit(void); -int BSP_VMEIrqMgrInstall(void); - -/* BSP specific address space configuration parameters */ - -/* - * The BSP maps VME address ranges into - * one BAT. - * NOTE: the BSP (startup/bspstart.c) uses - * hardcoded window lengths that match this - * layout: - */ -#define _VME_A32_WIN0_ON_PCI 0x90000000 -/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate - * CSR for space. - */ -#define _VME_CSR_ON_PCI 0x9e000000 -#define _VME_A24_ON_PCI 0x9f000000 -#define _VME_A16_ON_PCI 0x9fff0000 - -/* Reuse BAT 0 for VME */ -#define BSP_VME_BAT_IDX 0 - -/* start of the A32 window on the VME bus - * TODO: this should perhaps be a configuration option - */ -#define _VME_A32_WIN0_ON_VME 0x20000000 - -/* if _VME_DRAM_OFFSET is defined, the BSP - * will map our RAM onto the VME bus, starting - * at _VME_DRAM_OFFSET - */ -#define _VME_DRAM_OFFSET 0x90000000 - -#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ - do { \ - err = vmeUniverseInstallIrqMgrAlt(VMEUNIVERSE_IRQ_MGR_FLAG_SHARED,\ - 0, BSP_GPP_VME_VLINT0, \ - 1, BSP_GPP_VME_VLINT1, \ - 2, BSP_GPP_VME_VLINT2, \ - 3, BSP_GPP_VME_VLINT3, \ - -1 /* terminate list */); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/psim/include/bsp.h b/c/src/lib/libbsp/powerpc/psim/include/bsp.h deleted file mode 100644 index 0fac3b0869..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/include/bsp.h +++ /dev/null @@ -1,93 +0,0 @@ -/* bsp.h - * - * This include file contains all Papyrus board IO definitions. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_PSIM_BSP_H -#define LIBBSP_POWERPC_PSIM_BSP_H - -#include <bspopts.h> - -#ifdef ASM -/* Definition of where to store registers in alignment handler */ -#define ALIGN_REGS 0x0140 - -#else -#include <rtems.h> -#include <rtems/console.h> -#include <libcpu/io.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <bsp/vectors.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int end; /* last address in the program */ -extern int RAM_END; - -extern uint32_t BSP_mem_size; - -#define BSP_Convert_decrementer( _value ) ( (unsigned long long) _value ) - -/* macros */ -#define Processor_Synchronize() \ - __asm__ (" eieio ") - -/* - * Network configuration - */ -struct rtems_bsdnet_ifconfig; - -int rtems_ifsim_attach(struct rtems_bsdnet_ifconfig *ifcfg, int attaching); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "ifsim1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_ifsim_attach - -/* - * Interfaces to required Clock Driver support methods - */ -int BSP_disconnect_clock_handler(void); -int BSP_connect_clock_handler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#define BSP_HAS_NO_VME - -#endif diff --git a/c/src/lib/libbsp/powerpc/psim/include/coverhd.h b/c/src/lib/libbsp/powerpc/psim/include/coverhd.h deleted file mode 100644 index 16cfc1f06d..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/include/coverhd.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * @ingroup powerpc_psim - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk> - * - * Units are 100ns. - * - * These numbers are of questionable use, as they are developed by calling - * the routine many times, thus getting its entry veneer into the (small) - * cache on the 403GA. This in general is not true of the RTEMS timing - * tests, which usually call a routine only once, thus having no cache loaded - * advantage. - * - * Whether the directive times are useful after deducting the function call - * overhead is also questionable. The user is more interested generally - * in the total cost of a directive, not the cost if the procedure call - * is inlined! (In general this is not true). - * - * Andrew Bray 18/08/1995 - * - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 1 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 1 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 1 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 -#define CALLING_OVERHEAD_TASK_MODE 1 -#define CALLING_OVERHEAD_TASK_GET_NOTE 1 -#define CALLING_OVERHEAD_TASK_SET_NOTE 1 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 -#define CALLING_OVERHEAD_CLOCK_GET 4 -#define CALLING_OVERHEAD_CLOCK_SET 3 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 1 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 1 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 - -#define CALLING_OVERHEAD_EVENT_SEND 1 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 1 -#define CALLING_OVERHEAD_SIGNAL_SEND 1 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 1 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 1 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 1 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 2 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/psim/include/tm27.h b/c/src/lib/libbsp/powerpc/psim/include/tm27.h deleted file mode 100644 index 3a41283a13..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/include/tm27.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * @file - * @ingroup powerpc_psim - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/irq.h> - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -void nullFunc() {} -static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, - 0, - (rtems_irq_enable)nullFunc, - (rtems_irq_disable)nullFunc, - (rtems_irq_is_enabled) nullFunc}; - -void Install_tm27_vector(void (*_handler)()) -{ - clockIrqData.hdl = _handler; - if (!BSP_install_rtems_irq_handler (&clockIrqData)) { - printk("Error installing clock interrupt handler!\n"); - rtems_fatal_error_occurred(1); - } -} - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 1; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - - -#define Clear_tm27_intr() \ - do { \ - uint32_t _clicks = 0xffffffff; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - uint32_t _msr = 0; \ - _ISR_Set_level( 0 ); \ - __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - _msr |= 0x8002; \ - __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/psim/irq/irq.h b/c/src/lib/libbsp/powerpc/psim/irq/irq.h deleted file mode 100644 index 376c95a627..0000000000 --- a/c/src/lib/libbsp/powerpc/psim/irq/irq.h +++ /dev/null @@ -1,74 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_IRQ_H -#define LIBBSP_POWERPC_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#ifndef ASM - -#include <rtems/irq.h> - - -/* - * Symblolic IRQ names and related definitions. - */ - -/* - * PCI IRQ handlers related definitions - * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE - */ -#define BSP_PCI_IRQ_NUMBER (16) -#define BSP_PCI_IRQ_LOWEST_OFFSET (0) -#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) - -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) - - - /* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) - - /* - * Some Processor execption handled as rtems IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - -#include <bsp/irq_supp.h> - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -#ifdef __cplusplus -extern "C" { -#endif - -void BSP_rtems_irq_mng_init(unsigned cpuId); - -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/qemuppc/include/bsp.h b/c/src/lib/libbsp/powerpc/qemuppc/include/bsp.h deleted file mode 100644 index 14b600bba9..0000000000 --- a/c/src/lib/libbsp/powerpc/qemuppc/include/bsp.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This include file contains some definitions specific to the - * qemu powerpc Prep simulator - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_QEMUPPC_BSP_H -#define LIBBSP_POWERPC_QEMUPPC_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Convert decrementer value to tenths of microseconds (used by shared timer - * driver). - */ -#define BSP_Convert_decrementer( _value ) \ - ((int) (((_value) * 10) / bsp_clicks_per_usec)) - -/* - * Prototypes for methods that are referenced from .S - */ -void cmain(void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/qemuppc/irq/irq.h b/c/src/lib/libbsp/powerpc/qemuppc/irq/irq.h deleted file mode 100644 index 7124dbcaf8..0000000000 --- a/c/src/lib/libbsp/powerpc/qemuppc/irq/irq.h +++ /dev/null @@ -1,76 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_IRQ_H -#define LIBBSP_POWERPC_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 - -#ifndef ASM - -#include <rtems/irq.h> - - -/* - * Symblolic IRQ names and related definitions. - */ - -/* - * PCI IRQ handlers related definitions - * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE - */ -/* FIXME: do we need PCI interrrupts here ? */ -#define BSP_PCI_IRQ_NUMBER (16) -#define BSP_PCI_IRQ_LOWEST_OFFSET (0) -#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) - -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) - - - /* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_IRQ_NUMBER - 1) - - /* - * Some Processor execption handled as rtems IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -/* #include <bsp/irq_supp.h> */ - -#ifdef __cplusplus -extern "C" { -#endif - -void BSP_rtems_irq_mng_init(unsigned cpuId); - -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h b/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h deleted file mode 100644 index a0d0092a1d..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/include/bsp.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file - * - * @ingroup QorIQ - * - * @brief BSP API. - */ - -/* - * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_QORIQ_BSP_H -#define LIBBSP_POWERPC_QORIQ_BSP_H - -#include <bspopts.h> - -#ifndef ASM - -#include <rtems.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#define QORIQ_CHIP(alpha, num) ((alpha) * 10000 + (num)) - -#define QORIQ_CHIP_P1020 QORIQ_CHIP('P', 1020) - -#define QORIQ_CHIP_T2080 QORIQ_CHIP('T', 2080) - -#define QORIQ_CHIP_T4240 QORIQ_CHIP('T', 4240) - -#define QORIQ_CHIP_IS_T_VARIANT(variant) ((variant) / 10000 == 'T') - -extern unsigned BSP_bus_frequency; - -struct rtems_bsdnet_ifconfig; - -int BSP_tsec_attach( - struct rtems_bsdnet_ifconfig *config, - int attaching -); - -int qoriq_if_intercom_attach_detach( - struct rtems_bsdnet_ifconfig *config, - int attaching -); - -#if defined(HAS_UBOOT) - /* Routine to obtain U-Boot environment variables */ - const char *bsp_uboot_getenv( - const char *name - ); -#endif - -/* Internal SMP startup function */ -void qoriq_start_thread(void); - -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH BSP_tsec_attach -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH4 qoriq_if_intercom_attach_detach - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1" -#define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" -#define RTEMS_BSP_NETWORK_DRIVER_NAME3 "tsec3" -#define RTEMS_BSP_NETWORK_DRIVER_NAME4 "intercom1" - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_POWERPC_QORIQ_BSP_H */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/irq.h b/c/src/lib/libbsp/powerpc/qoriq/include/irq.h deleted file mode 100644 index 1363ec3580..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/include/irq.h +++ /dev/null @@ -1,386 +0,0 @@ -/** - * @file - * - * @ingroup QorIQInterrupt - * - * @brief Interrupt API. - */ - -/* - * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_QORIQ_IRQ_H -#define LIBBSP_POWERPC_QORIQ_IRQ_H - -#include <bsp.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define QORIQ_IRQ_ERROR 0 - -#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) - -#define QORIQ_IRQ_PCI_EXPRESS_1 4 -#define QORIQ_IRQ_PCI_EXPRESS_2 5 -#define QORIQ_IRQ_PCI_EXPRESS_3 6 -#define QORIQ_IRQ_PCI_EXPRESS_4 7 -#define QORIQ_IRQ_PAMU 8 -#define QORIQ_IRQ_IFC 9 -#define QORIQ_IRQ_DMA_CHANNEL_1_1 12 -#define QORIQ_IRQ_DMA_CHANNEL_1_2 13 -#define QORIQ_IRQ_DMA_CHANNEL_1_3 14 -#define QORIQ_IRQ_DMA_CHANNEL_1_4 15 -#define QORIQ_IRQ_DMA_CHANNEL_2_1 16 -#define QORIQ_IRQ_DMA_CHANNEL_2_2 17 -#define QORIQ_IRQ_DMA_CHANNEL_2_3 18 -#define QORIQ_IRQ_DMA_CHANNEL_2_4 19 -#define QORIQ_IRQ_DUART_1 20 -#define QORIQ_IRQ_DUART_2 21 -#define QORIQ_IRQ_DUARL_I2C_1 22 -#define QORIQ_IRQ_DUARL_I2C_2 23 -#define QORIQ_IRQ_PCI_EXPRESS_1_INTA 24 -#define QORIQ_IRQ_PCI_EXPRESS_2_INTA 25 -#define QORIQ_IRQ_PCI_EXPRESS_3_INTA 26 -#define QORIQ_IRQ_PCI_EXPRESS_4_INTA 27 -#define QORIQ_IRQ_USB_1 28 -#define QORIQ_IRQ_USB_2 29 -#define QORIQ_IRQ_ESDHC 32 -#define QORIQ_IRQ_PERF_MON 36 -#define QORIQ_IRQ_ESPI 37 -#define QORIQ_IRQ_GPIO_2 38 -#define QORIQ_IRQ_GPIO_1 39 -#define QORIQ_IRQ_SATA_1 52 -#define QORIQ_IRQ_SATA_2 53 -#define QORIQ_IRQ_DMA_CHANNEL_1_5 60 -#define QORIQ_IRQ_DMA_CHANNEL_1_6 61 -#define QORIQ_IRQ_DMA_CHANNEL_1_7 62 -#define QORIQ_IRQ_DMA_CHANNEL_1_8 63 -#define QORIQ_IRQ_DMA_CHANNEL_2_5 64 -#define QORIQ_IRQ_DMA_CHANNEL_2_6 65 -#define QORIQ_IRQ_DMA_CHANNEL_2_7 66 -#define QORIQ_IRQ_DMA_CHANNEL_2_8 67 -#define QORIQ_IRQ_EVENT_PROC_UNIT_1 68 -#define QORIQ_IRQ_EVENT_PROC_UNIT_2 69 -#define QORIQ_IRQ_GPIO_3 70 -#define QORIQ_IRQ_GPIO_4 71 -#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_1 72 -#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_2 73 -#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_3 74 -#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_4 75 -#define QORIQ_IRQ_SEC_5_2_GLOBAL_ERROR 76 -#define QORIQ_IRQ_SEC_MON 77 -#define QORIQ_IRQ_EVENT_PROC_UNIT_3 78 -#define QORIQ_IRQ_EVENT_PROC_UNIT_4 79 -#define QORIQ_IRQ_FRAME_MGR 80 -#define QORIQ_IRQ_MDIO_1 84 -#define QORIQ_IRQ_MDIO_2 85 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_0 88 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_0 89 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_1 90 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_1 91 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_2 92 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_2 93 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_3 94 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_3 95 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_4 96 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_4 97 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_5 98 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_5 99 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_6 100 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_6 101 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_7 102 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_7 103 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_8 104 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_8 105 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_9 106 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_9 107 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_10 109 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_10 109 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_11 110 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_11 111 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_12 112 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_12 113 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_13 114 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_13 115 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_14 116 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_14 117 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_15 118 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_15 119 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_16 120 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_16 121 -#define QORIQ_IRQ_QUEUE_MGR_PORTAL_17 122 -#define QORIQ_IRQ_BUFFER_MGR_PORTAL_17 123 -#define QORIQ_IRQ_DMA_CHANNEL_3_1 240 -#define QORIQ_IRQ_DMA_CHANNEL_3_2 241 -#define QORIQ_IRQ_DMA_CHANNEL_3_3 242 -#define QORIQ_IRQ_DMA_CHANNEL_3_4 243 -#define QORIQ_IRQ_DMA_CHANNEL_3_4 244 -#define QORIQ_IRQ_DMA_CHANNEL_3_5 245 -#define QORIQ_IRQ_DMA_CHANNEL_3_6 246 -#define QORIQ_IRQ_DMA_CHANNEL_3_8 247 - -#define QORIQ_IRQ_EXT_BASE 256 - -#else /* QORIQ_CHIP_VARIANT */ - -/** - * @defgroup QoriqInterruptP1020 QorIQ - P1020 Internal Interrupt Sources - * - * @ingroup QorIQInterrupt - * - * @brief P1020 internal interrupt sources. - * - * @{ - */ - -#define QORIQ_IRQ_ETSEC_TX_1_GROUP_1 1 -#define QORIQ_IRQ_ETSEC_RX_1_GROUP_1 2 -#define QORIQ_IRQ_ETSEC_ER_1_GROUP_1 8 -#define QORIQ_IRQ_ETSEC_TX_3_GROUP_1 9 -#define QORIQ_IRQ_ETSEC_RX_3_GROUP_1 10 -#define QORIQ_IRQ_ETSEC_ER_3_GROUP_1 11 -#define QORIQ_IRQ_ETSEC_TX_2_GROUP_1 35 -#define QORIQ_IRQ_ETSEC_RX_2_GROUP_1 36 -#define QORIQ_IRQ_TDM 46 -#define QORIQ_IRQ_TDM_ERROR 47 -#define QORIQ_IRQ_ETSEC_ER_2_GROUP_1 51 - -/** @} */ - -/** - * @defgroup QoriqInterruptP2020 QorIQ - P2020 Internal Interrupt Sources - * - * @ingroup QorIQInterrupt - * - * @brief P2020 internal interrupt sources. - * - * @{ - */ - -#define QORIQ_IRQ_L2_CACHE 0 -#define QORIQ_IRQ_ECM 1 -#define QORIQ_IRQ_DDR_CONTROLLER 2 -#define QORIQ_IRQ_PCI_EXPRESS_3 8 -#define QORIQ_IRQ_PCI_EXPRESS_2 9 -#define QORIQ_IRQ_PCI_EXPRESS_1 10 -#define QORIQ_IRQ_SRIO_ERR_WRT_1_2 32 -#define QORIQ_IRQ_SRIO_OUT_DOORBELL_1 33 -#define QORIQ_IRQ_SRIO_IN_DOORBELL_1 34 -#define QORIQ_IRQ_SRIO_OUT_MSG_1 37 -#define QORIQ_IRQ_SRIO_IN_MSG_1 38 -#define QORIQ_IRQ_SRIO_OUT_MSG_2 39 -#define QORIQ_IRQ_SRIO_IN_MSG_2 40 - -/** @} */ - -/** - * @defgroup QoriqInterruptAll QorIQ - Internal Interrupt Sources - * - * @ingroup QorIQInterrupt - * - * @brief Internal interrupt sources. - * - * @{ - */ - -#define QORIQ_IRQ_ELBC 3 -#define QORIQ_IRQ_DMA_CHANNEL_1_1 4 -#define QORIQ_IRQ_DMA_CHANNEL_2_1 5 -#define QORIQ_IRQ_DMA_CHANNEL_3_1 6 -#define QORIQ_IRQ_DMA_CHANNEL_4_1 7 -#define QORIQ_IRQ_USB_1 12 -#define QORIQ_IRQ_ETSEC_TX_1 13 -#define QORIQ_IRQ_ETSEC_RX_1 14 -#define QORIQ_IRQ_ETSEC_TX_3 15 -#define QORIQ_IRQ_ETSEC_RX_3 16 -#define QORIQ_IRQ_ETSEC_ER_3 17 -#define QORIQ_IRQ_ETSEC_ER_1 18 -#define QORIQ_IRQ_ETSEC_TX_2 19 -#define QORIQ_IRQ_ETSEC_RX_2 20 -#define QORIQ_IRQ_ETSEC_ER_2 24 -#define QORIQ_IRQ_DUART_1 26 -#define QORIQ_IRQ_I2C 27 -#define QORIQ_IRQ_PERFORMANCE_MONITOR 28 -#define QORIQ_IRQ_SECURITY_1 29 -#define QORIQ_IRQ_USB_2 30 -#define QORIQ_IRQ_GPIO 31 -#define QORIQ_IRQ_SECURITY_2 42 -#define QORIQ_IRQ_ESPI 43 -#define QORIQ_IRQ_ETSEC_IEEE_1588_1 52 -#define QORIQ_IRQ_ETSEC_IEEE_1588_2 53 -#define QORIQ_IRQ_ETSEC_IEEE_1588_3 54 -#define QORIQ_IRQ_ESDHC 56 -#define QORIQ_IRQ_DMA_CHANNEL_1_2 60 -#define QORIQ_IRQ_DMA_CHANNEL_2_2 61 -#define QORIQ_IRQ_DMA_CHANNEL_3_2 62 -#define QORIQ_IRQ_DMA_CHANNEL_4_2 63 - -/** @} */ - -#define QORIQ_IRQ_EXT_BASE 64 - -#endif /* QORIQ_CHIP_VARIANT */ - -/** - * @defgroup QoriqInterruptExternal QorIQ - External Interrupt Sources - * - * @ingroup QorIQInterrupt - * - * @brief External interrupt sources. - * - * @{ - */ - -#define QORIQ_IRQ_EXT_0 (QORIQ_IRQ_EXT_BASE + 0) -#define QORIQ_IRQ_EXT_1 (QORIQ_IRQ_EXT_BASE + 1) -#define QORIQ_IRQ_EXT_2 (QORIQ_IRQ_EXT_BASE + 2) -#define QORIQ_IRQ_EXT_3 (QORIQ_IRQ_EXT_BASE + 3) -#define QORIQ_IRQ_EXT_4 (QORIQ_IRQ_EXT_BASE + 4) -#define QORIQ_IRQ_EXT_5 (QORIQ_IRQ_EXT_BASE + 5) -#define QORIQ_IRQ_EXT_6 (QORIQ_IRQ_EXT_BASE + 6) -#define QORIQ_IRQ_EXT_7 (QORIQ_IRQ_EXT_BASE + 7) -#define QORIQ_IRQ_EXT_8 (QORIQ_IRQ_EXT_BASE + 8) -#define QORIQ_IRQ_EXT_9 (QORIQ_IRQ_EXT_BASE + 9) -#define QORIQ_IRQ_EXT_10 (QORIQ_IRQ_EXT_BASE + 10) -#define QORIQ_IRQ_EXT_11 (QORIQ_IRQ_EXT_BASE + 11) - -/** @} */ - -/** - * @defgroup QoriqInterruptIPI QorIQ - Interprocessor Interrupts - * - * @ingroup QorIQInterrupt - * - * @brief Interprocessor interrupts. - * - * @{ - */ - -#define QORIQ_IRQ_IPI_BASE (QORIQ_IRQ_EXT_11 + 1) -#define QORIQ_IRQ_IPI_0 (QORIQ_IRQ_IPI_BASE + 0) -#define QORIQ_IRQ_IPI_1 (QORIQ_IRQ_IPI_BASE + 1) -#define QORIQ_IRQ_IPI_2 (QORIQ_IRQ_IPI_BASE + 2) -#define QORIQ_IRQ_IPI_3 (QORIQ_IRQ_IPI_BASE + 3) - -/** @} */ - -/** - * @defgroup QoriqInterruptIPI QorIQ - Message Interrupts - * - * @ingroup QorIQInterrupt - * - * @brief Message interrupts. - * - * @{ - */ - -#define QORIQ_IRQ_MI_BASE (QORIQ_IRQ_IPI_3 + 1) -#define QORIQ_IRQ_MI_0 (QORIQ_IRQ_MI_BASE + 0) -#define QORIQ_IRQ_MI_1 (QORIQ_IRQ_MI_BASE + 1) -#define QORIQ_IRQ_MI_2 (QORIQ_IRQ_MI_BASE + 2) -#define QORIQ_IRQ_MI_3 (QORIQ_IRQ_MI_BASE + 3) -#define QORIQ_IRQ_MI_4 (QORIQ_IRQ_MI_BASE + 4) -#define QORIQ_IRQ_MI_5 (QORIQ_IRQ_MI_BASE + 5) -#define QORIQ_IRQ_MI_6 (QORIQ_IRQ_MI_BASE + 6) -#define QORIQ_IRQ_MI_7 (QORIQ_IRQ_MI_BASE + 7) - -/** @} */ - -/** - * @defgroup QoriqInterruptIPI QorIQ - Shared Message Signaled Interrupts - * - * @ingroup QorIQInterrupt - * - * @brief Shared message signaled interrupts. - * - * @{ - */ - -#define QORIQ_IRQ_MSI_BASE (QORIQ_IRQ_MI_7 + 1) -#define QORIQ_IRQ_MSI_0 (QORIQ_IRQ_MSI_BASE + 0) -#define QORIQ_IRQ_MSI_1 (QORIQ_IRQ_MSI_BASE + 1) -#define QORIQ_IRQ_MSI_2 (QORIQ_IRQ_MSI_BASE + 2) -#define QORIQ_IRQ_MSI_3 (QORIQ_IRQ_MSI_BASE + 3) -#define QORIQ_IRQ_MSI_4 (QORIQ_IRQ_MSI_BASE + 4) -#define QORIQ_IRQ_MSI_5 (QORIQ_IRQ_MSI_BASE + 5) -#define QORIQ_IRQ_MSI_6 (QORIQ_IRQ_MSI_BASE + 6) -#define QORIQ_IRQ_MSI_7 (QORIQ_IRQ_MSI_BASE + 7) - -/** @} */ - -/** - * @defgroup QoriqInterruptIPI QorIQ - Global Timer Interrupts - * - * @ingroup QorIQInterrupt - * - * @brief Global Timer interrupts. - * - * @{ - */ - -#define QORIQ_IRQ_GT_BASE (QORIQ_IRQ_MSI_7 + 1) -#define QORIQ_IRQ_GT_A_0 (QORIQ_IRQ_GT_BASE + 0) -#define QORIQ_IRQ_GT_A_1 (QORIQ_IRQ_GT_BASE + 1) -#define QORIQ_IRQ_GT_A_2 (QORIQ_IRQ_GT_BASE + 2) -#define QORIQ_IRQ_GT_A_3 (QORIQ_IRQ_GT_BASE + 3) -#define QORIQ_IRQ_GT_B_0 (QORIQ_IRQ_GT_BASE + 4) -#define QORIQ_IRQ_GT_B_1 (QORIQ_IRQ_GT_BASE + 5) -#define QORIQ_IRQ_GT_B_2 (QORIQ_IRQ_GT_BASE + 6) -#define QORIQ_IRQ_GT_B_3 (QORIQ_IRQ_GT_BASE + 7) - -/** @} */ - -/** - * @defgroup QorIQInterrupt QorIQ - Interrupt Support - * - * @ingroup QorIQ - * - * @brief Interrupt support. - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX QORIQ_IRQ_GT_B_3 - -#define QORIQ_PIC_PRIORITY_LOWEST 1 -#define QORIQ_PIC_PRIORITY_HIGHEST 15 -#define QORIQ_PIC_PRIORITY_DISABLED 0 -#define QORIQ_PIC_PRIORITY_INVALID (QORIQ_PIC_PRIORITY_HIGHEST + 1) -#define QORIQ_PIC_PRIORITY_DEFAULT (QORIQ_PIC_PRIORITY_LOWEST + 1) -#define QORIQ_PIC_PRIORITY_IS_VALID(p) \ - ((p) >= QORIQ_PIC_PRIORITY_DISABLED && (p) <= QORIQ_PIC_PRIORITY_HIGHEST) - -rtems_status_code qoriq_pic_set_priority( - rtems_vector_number vector, - int new_priority, - int *old_priority -); - -rtems_status_code qoriq_pic_set_affinity( - rtems_vector_number vector, - uint32_t processor_index -); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_QORIQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h b/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h deleted file mode 100644 index f08cc43384..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/include/mmu.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * @file - * - * @ingroup QorIQMMU - * - * @brief MMU API. - */ - -/* - * Copyright (c) 2011-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_QORIQ_MMU_H -#define LIBBSP_POWERPC_QORIQ_MMU_H - -#include <stdint.h> -#include <stdbool.h> - -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup QorIQMMU QorIQ - MMU Support - * - * @ingroup QorIQ - * - * @brief MMU support. - * - * @{ - */ - -#define QORIQ_MMU_MIN_POWER 12 -#define QORIQ_MMU_MAX_POWER 30 -#define QORIQ_MMU_POWER_STEP 2 - -typedef struct { - uint32_t begin; - uint32_t last; - uint32_t mas1; - uint32_t mas2; - uint32_t mas3; - uint32_t mas7; -} qoriq_mmu_entry; - -typedef struct { - int count; - qoriq_mmu_entry entries [QORIQ_TLB1_ENTRY_COUNT]; -} qoriq_mmu_context; - -void qoriq_mmu_context_init(qoriq_mmu_context *self); - -bool qoriq_mmu_add( - qoriq_mmu_context *self, - uint32_t begin, - uint32_t last, - uint32_t mas1, - uint32_t mas2, - uint32_t mas3, - uint32_t mas7 -); - -void qoriq_mmu_partition(qoriq_mmu_context *self, int max_count); - -void qoriq_mmu_write_to_tlb1(qoriq_mmu_context *self, int first_tlb); - -void qoriq_mmu_change_perm(uint32_t test, uint32_t set, uint32_t clear); - -void qoriq_mmu_config(int first_tlb, int scratch_tlb); - -void qoriq_tlb1_write( - int esel, - uint32_t mas1, - uint32_t mas2, - uint32_t mas3, - uint32_t mas7, - uint32_t ea, - uint32_t tsize -); - -void qoriq_tlb1_invalidate(int esel); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_QORIQ_MMU_H */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h b/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h deleted file mode 100644 index 46264b7e67..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/include/tm27.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * - * @ingroup QorIQ - * - * @brief Support file for Timer Test 27. - */ - -/* - * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 - #error "This is an RTEMS internal file you must not include directly." -#endif /* _RTEMS_TMTEST27 */ - -#ifndef TMTESTS_TM27_H -#define TMTESTS_TM27_H - -#include <assert.h> - -#include <libcpu/powerpc-utility.h> - -#include <bsp/irq.h> -#include <bsp/qoriq.h> - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define IPI_INDEX_LOW 1 - -#define IPI_INDEX_HIGH 2 - -static void Install_tm27_vector(void (*handler)(rtems_vector_number)) -{ - rtems_status_code sc; - rtems_vector_number low = QORIQ_IRQ_IPI_0 + IPI_INDEX_LOW; - rtems_vector_number high = QORIQ_IRQ_IPI_0 + IPI_INDEX_HIGH; - - sc = rtems_interrupt_handler_install( - low, - "tm17 low", - RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL - ); - assert(sc == RTEMS_SUCCESSFUL); - - sc = qoriq_pic_set_priority(low, 1, NULL); - assert(sc == RTEMS_SUCCESSFUL); - - sc = rtems_interrupt_handler_install( - high, - "tm17 high", - RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) handler, - NULL - ); - assert(sc == RTEMS_SUCCESSFUL); - - sc = qoriq_pic_set_priority(high, 2, NULL); - assert(sc == RTEMS_SUCCESSFUL); -} - -static void qoriq_tm27_cause(uint32_t ipi_index) -{ - uint32_t self = ppc_processor_id(); - - qoriq.pic.per_cpu[self].ipidr[ipi_index].reg = UINT32_C(1) << self; -} - -static void Cause_tm27_intr() -{ - qoriq_tm27_cause(IPI_INDEX_LOW); -} - -static void Clear_tm27_intr() -{ - /* Nothing to do */ -} - -static void Lower_tm27_intr(void) -{ - qoriq_tm27_cause(IPI_INDEX_HIGH); -} - -#endif /* TMTESTS_TM27_H */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/tsec-config.h b/c/src/lib/libbsp/powerpc/qoriq/include/tsec-config.h deleted file mode 100644 index b1a70e7486..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/include/tsec-config.h +++ /dev/null @@ -1,36 +0,0 @@ -/** - * @file - * - * @ingroup QorIQ - * - * @brief TSEC configuration. - */ - -/* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H -#define LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define TSEC_COUNT 3 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H */ diff --git a/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h b/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h deleted file mode 100644 index 3e6fa90b55..0000000000 --- a/c/src/lib/libbsp/powerpc/qoriq/include/u-boot-config.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_QORIQ_U_BOOT_CONFIG_H -#define LIBBSP_POWERPC_QORIQ_U_BOOT_CONFIG_H - -#include <bspopts.h> - -#define U_BOOT_BOARD_INFO_TEXT_SECTION __attribute__((section(".bsp_start_text"))) - -#define U_BOOT_BOARD_INFO_DATA_SECTION __attribute__((section(".bsp_start_data"))) - -#define CONFIG_E500 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 - -#endif /* LIBBSP_POWERPC_QORIQ_U_BOOT_CONFIG_H */ diff --git a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h deleted file mode 100644 index 0b6eb28446..0000000000 --- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * This include file contains all board IO definitions. - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_SCORE603E_BSP_H -#define LIBBSP_POWERPC_SCORE603E_BSP_H - -#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> -#include <rtems.h> -#include <rtems/console.h> -#include <libcpu/io.h> -#include <rtems/clockdrv.h> -#include <bsp/vectors.h> - -#ifdef ASM -/* Definition of where to store registers in alignment handler */ -#define ALIGN_REGS 0x0140 - -#else -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> - -/* - * We no longer support the first generation board. - */ - -#include <gen2.h> -#include <bsp/irq.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The following macro calculates the Baud constant. For the Z8530 chip. - * - * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 - * for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2 - */ -#define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate ) \ - ( (_frequency /( _clock_by * 2 * _baud_rate)) - 2) - -#define Score603e_Z8530_Chip1_Baud( _value ) \ - _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \ - SCORE603E_85C30_1_CLOCK_X, _value ) - -#define Score603e_Z8530_Chip0_Baud( _value ) \ - _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \ - SCORE603E_85C30_0_CLOCK_X, _value ) - -#define Initialize_Board_ctrl_register() \ - *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ - SCORE603E_BRD_FLASH_DISABLE_MASK) - -#define Processor_Synchronize() \ - __asm__ volatile(" eieio ") - - -/* Constants */ - -/* - * Device Driver Table Entries - */ - -/* - * NOTE: Use the standard Console driver entry - */ - -/* - * NOTE: Use the standard Clock driver entry - */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; -extern int CPU_PPC_CLICKS_PER_MS; - -extern int end; /* last address in the program */ - -/* - * Total RAM available - */ -extern int end; /* last address in the program */ -extern int RAM_END; -extern uint32_t BSP_mem_size; - - -/* - * How many libio files we want - */ - -#define BSP_LIBIO_MAX_FDS 20 - -/* functions */ - -/* - * - */ -rtems_isr_entry set_EE_vector( - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector /* vector number */ -); -void initialize_external_exception_vector(void); - -/* - * Hwr_init.c - */ -void init_PCI(void); -void init_RTC(void); -void instruction_cache_enable(void); -void data_cache_enable(void); - -void initialize_PCI_bridge(void); -uint16_t read_and_clear_irq(void); -void set_irq_mask(uint16_t value); -uint16_t get_irq_mask(void); - -/* - * universe.c - */ -void initialize_universe(void); -void set_irq_mask(uint16_t value); -uint16_t get_irq_mask(void); -void unmask_irq(uint16_t irq_idx); -void mask_irq(uint16_t irq_idx); -void init_irq_data_register(void); -uint16_t read_and_clear_PMC_irq(uint16_t irq); -bool Is_PMC_IRQ( uint32_t pmc_irq, uint16_t status_word); -uint16_t read_and_clear_irq(void); -void set_vme_base_address(uint32_t base_address); -uint32_t get_vme_slave_size(void); -void set_vme_slave_size (uint32_t size); - -/* - * FPGA.c - */ -void initialize_PCI_bridge(void); -void init_irq_data_register(void); -uint32_t Read_pci_device_register(uint32_t address); -void Write_pci_device_register(uint32_t address, uint32_t data); - -/* flash.c */ -unsigned int SCORE603e_FLASH_Disable(uint32_t unused); -unsigned int SCORE603e_FLASH_verify_enable(void); -unsigned int SCORE603e_FLASH_Enable_writes(uint32_t area); - -/* - * PCI.c - */ -uint32_t PCI_bus_read(volatile uint32_t *_addr); -void PCI_bus_write(volatile uint32_t *_addr, uint32_t _data); - -#define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area ) -#define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area ) - -#define Convert_Endian_32( _data ) \ - ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \ - ((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) ) - -#define Convert_Endian_16( _data ) \ - ( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) ) - -/* - * Interfaces to required Clock Driver support methods - */ -int BSP_disconnect_clock_handler(void); -int BSP_connect_clock_handler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/score603e/include/tm27.h b/c/src/lib/libbsp/powerpc/score603e/include/tm27.h deleted file mode 100644 index 0ee290c705..0000000000 --- a/c/src/lib/libbsp/powerpc/score603e/include/tm27.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * @file - * @ingroup powerpc_score603e - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 1989-2014. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -#include <bsp/irq.h> - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -void nullFunc() {} - -static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, - 0, - (rtems_irq_enable)nullFunc, - (rtems_irq_disable)nullFunc, - (rtems_irq_is_enabled) nullFunc}; -void Install_tm27_vector(void (*_handler)()) -{ - clockIrqData.hdl = _handler; - if (!BSP_install_rtems_irq_handler (&clockIrqData)) { - printk("Error installing clock interrupt handler!\n"); - rtems_fatal_error_occurred(1); - } -} - -#define Cause_tm27_intr() \ - do { \ - uint32_t _clicks = 8; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Clear_tm27_intr() \ - do { \ - uint32_t _clicks = 0xffffffff; \ - __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - uint32_t _msr = 0; \ - _ISR_Set_level( 0 ); \ - __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - _msr |= 0x8002; \ - __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h b/c/src/lib/libbsp/powerpc/score603e/irq/irq.h deleted file mode 100644 index 97977a75e7..0000000000 --- a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h +++ /dev/null @@ -1,153 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by RTEMS to write interrupt handlers. - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * COPYRIGHT (c) 1989-2009. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef BSP_POWERPC_IRQ_H -#define BSP_POWERPC_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 -#include <rtems/irq.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - - -/* - * rtems_irq_number Definitions - */ - -/* - * ISA IRQ handler related definitions - */ -#define BSP_ISA_IRQ_NUMBER (16) -#define BSP_ISA_IRQ_LOWEST_OFFSET (0) -#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) - -/* - * PCI IRQ handlers related definitions - */ -#define BSP_PCI_IRQ_NUMBER (16) -#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) -#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) - -/* - * PMC IRQ - */ -#define BSP_PMC_IRQ_NUMBER (4) -#define BSP_PMC_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) -#define BSP_PMC_IRQ_MAX_OFFSET (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1) - - -/* - * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) - -/* Misc vectors for OPENPIC irqs (IPI, timers) - */ -#define BSP_MISC_IRQ_NUMBER (8) -#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) - -/* - * Some Processor execption handled as RTEMS IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - -/* - * First Score Unique IRQ - */ -#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET ) - -/* - * The Following Are part of a Score603e FPGA. - */ -#define SCORE603E_IRQ00 ( Score_IRQ_First + 0 ) -#define SCORE603E_IRQ01 ( Score_IRQ_First + 1 ) -#define SCORE603E_IRQ02 ( Score_IRQ_First + 2 ) -#define SCORE603E_IRQ03 ( Score_IRQ_First + 3 ) -#define SCORE603E_IRQ04 ( Score_IRQ_First + 4 ) -#define SCORE603E_IRQ05 ( Score_IRQ_First + 5 ) -#define SCORE603E_IRQ06 ( Score_IRQ_First + 6 ) -#define SCORE603E_IRQ07 ( Score_IRQ_First + 7 ) -#define SCORE603E_IRQ08 ( Score_IRQ_First + 8 ) -#define SCORE603E_IRQ09 ( Score_IRQ_First + 9 ) -#define SCORE603E_IRQ10 ( Score_IRQ_First + 10 ) -#define SCORE603E_IRQ11 ( Score_IRQ_First + 11 ) -#define SCORE603E_IRQ12 ( Score_IRQ_First + 12 ) -#define SCORE603E_IRQ13 ( Score_IRQ_First + 13 ) -#define SCORE603E_IRQ14 ( Score_IRQ_First + 14 ) -#define SCORE603E_IRQ15 ( Score_IRQ_First + 15 ) - -#define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 -#define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 -#define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 -#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 -#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 -#define SCORE603E_RTC_IRQ SCORE603E_IRQ05 -#define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 -#define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 -#define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 -#define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 -#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 -#define SCORE603E_1553_IRQ SCORE603E_IRQ11 -#define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 -#define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 -#define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 -#define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 - -/* - * The Score FPGA maps all interrupts comming from the PMC card to - * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be - * read to indicate which interrupt was chained to the FPGA. - */ -#define SCORE603E_IRQ16 ( Score_IRQ_First + 16 ) -#define SCORE603E_IRQ17 ( Score_IRQ_First + 17 ) -#define SCORE603E_IRQ18 ( Score_IRQ_First + 18 ) -#define SCORE603E_IRQ19 ( Score_IRQ_First + 19 ) - -/* - * IRQ'a read from the PMC card - */ -#define SCORE603E_85C30_4_IRQ SCORE603E_IRQ16 /* SCC 422-1 */ -#define SCORE603E_85C30_2_IRQ SCORE603E_IRQ17 /* SCC 232-1 */ -#define SCORE603E_85C30_5_IRQ SCORE603E_IRQ18 /* SCC 422-2 */ -#define SCORE603E_85C30_3_IRQ SCORE603E_IRQ19 /* SCC 232-2 */ - -#define MAX_BOARD_IRQS SCORE603E_IRQ19 - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); - -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/shared/console/uart.h b/c/src/lib/libbsp/powerpc/shared/console/uart.h deleted file mode 100644 index b7539b5b7b..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/console/uart.h +++ /dev/null @@ -1,190 +0,0 @@ - -/* - * This software is Copyright (C) 1998 by T.sqware - all rights limited - * It is provided in to the public domain "as is", can be freely modified - * as far as this copyight notice is kept unchanged, but does not imply - * an endorsement by T.sqware of the product in which it is included. - */ - -#ifndef _BSPUART_H -#define _BSPUART_H - -#include <bsp/irq.h> - -#include <sys/ioctl.h> -#include <rtems/libio.h> - -void BSP_uart_init(int uart, int baud, int hwFlow); -void BSP_uart_set_baud(int uart, int baud); -void BSP_uart_intr_ctrl(int uart, int cmd); -void BSP_uart_throttle(int uart); -void BSP_uart_unthrottle(int uart); -int BSP_uart_polled_status(int uart); -void BSP_uart_polled_write(int uart, int val); -int BSP_uart_polled_read(int uart); -void BSP_uart_termios_set(int uart, void *ttyp); -ssize_t BSP_uart_termios_write_com(int minor, const char *buf, size_t len); -int BSP_uart_termios_read_com (int minor); -void BSP_uart_termios_isr_com1(void *unused); -void BSP_uart_termios_isr_com2(void *unused); -void BSP_uart_dbgisr_com1(void); -void BSP_uart_dbgisr_com2(void); -int BSP_uart_install_isr(int uart, rtems_irq_hdl handler); -int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler); -ssize_t BSP_uart_termios_write_polled(int minor, const char *buf, size_t len); -int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg); -int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg); - -extern unsigned BSP_poll_char_via_serial(void); -extern void BSP_output_char_via_serial(const char val); -extern int BSPConsolePort; -extern int BSPBaseBaud; - -/* Special IOCTLS to install a lowlevel 'BREAK' handler */ - -/* pass a BSP_UartBreakCb pointer to ioctl when retrieving - * or installing break callback - */ -typedef void (*BSP_UartBreakCbProc)( - int uartMinor, - unsigned uartRBRLSRStatus, - void *termiosPrivatePtr, - void *private -); - -typedef struct BSP_UartBreakCbRec_ { - BSP_UartBreakCbProc handler; /* NOTE: handler runs in INTERRUPT CONTEXT */ - void *private; /* closure pointer which is passed to the callback */ -} BSP_UartBreakCbRec, *BSP_UartBreakCb; - -#define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec)) -#define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec)) - -/* - * Command values for BSP_uart_intr_ctrl(), - * values are strange in order to catch errors - * with assert - */ -#define BSP_UART_INTR_CTRL_DISABLE (0) -#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ -#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ -#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ - -/* Return values for uart_polled_status() */ -#define BSP_UART_STATUS_ERROR (-1) /* No character */ -#define BSP_UART_STATUS_NOCHAR (0) /* No character */ -#define BSP_UART_STATUS_CHAR (1) /* Character present */ -#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ - -/* PC UART definitions */ -#define BSP_UART_COM1 (0) -#define BSP_UART_COM2 (1) - -/* - * Offsets from base - */ - -/* DLAB 0 */ -#define RBR (0) /* Rx Buffer Register (read) */ -#define THR (0) /* Tx Buffer Register (write) */ -#define IER (1) /* Interrupt Enable Register */ - -/* DLAB X */ -#define IIR (2) /* Interrupt Ident Register (read) */ -#define FCR (2) /* FIFO Control Register (write) */ -#define LCR (3) /* Line Control Register */ -#define MCR (4) /* Modem Control Register */ -#define LSR (5) /* Line Status Register */ -#define MSR (6) /* Modem Status Register */ -#define SCR (7) /* Scratch register */ - -/* DLAB 1 */ -#define DLL (0) /* Divisor Latch, LSB */ -#define DLM (1) /* Divisor Latch, MSB */ -#define AFR (2) /* Alternate Function register */ - -/* - * Interrupt source definition via IIR - */ -#define MODEM_STATUS 0 -#define NO_MORE_INTR 1 -#define TRANSMITTER_HODING_REGISTER_EMPTY 2 -#define RECEIVER_DATA_AVAIL 4 -#define RECEIVER_ERROR 6 -#define CHARACTER_TIMEOUT_INDICATION 12 - -/* - * Bits definition of IER - */ -#define RECEIVE_ENABLE 0x1 -#define TRANSMIT_ENABLE 0x2 -#define RECEIVER_LINE_ST_ENABLE 0x4 -#define MODEM_ENABLE 0x8 -#define INTERRUPT_DISABLE 0x0 - -/* - * Bits definition of the Line Status Register (LSR) - */ -#define DR 0x01 /* Data Ready */ -#define OE 0x02 /* Overrun Error */ -#define PE 0x04 /* Parity Error */ -#define FE 0x08 /* Framing Error */ -#define BI 0x10 /* Break Interrupt */ -#define THRE 0x20 /* Transmitter Holding Register Empty */ -#define TEMT 0x40 /* Transmitter Empty */ -#define ERFIFO 0x80 /* Error receive Fifo */ - -/* - * Bits definition of the MODEM Control Register (MCR) - */ -#define DTR 0x01 /* Data Terminal Ready */ -#define RTS 0x02 /* Request To Send */ -#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */ -#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */ -#define LB 0x10 /* Enable Internal Loop Back */ - -/* - * Bits definition of the Line Control Register (LCR) - */ -#define CHR_5_BITS 0 -#define CHR_6_BITS 1 -#define CHR_7_BITS 2 -#define CHR_8_BITS 3 - -#define WL 0x03 /* Word length mask */ -#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ -#define PEN 0x08 /* Parity Enabled */ -#define EPS 0x10 /* Even Parity Select, otherwise Odd */ -#define SP 0x20 /* Stick Parity */ -#define BCB 0x40 /* Break Control Bit */ -#define DLAB 0x80 /* Enable Divisor Latch Access */ - -/* - * Bits definition of the MODEM Status Register (MSR) - */ -#define DCTS 0x01 /* Delta Clear To Send */ -#define DDSR 0x02 /* Delta Data Set Ready */ -#define TERI 0x04 /* Trailing Edge Ring Indicator */ -#define DDCD 0x08 /* Delta Carrier Detect Indicator */ -#define CTS 0x10 /* Clear To Send (when loop back is active) */ -#define DSR 0x20 /* Data Set Ready (when loop back is active) */ -#define RI 0x40 /* Ring Indicator (when loop back is active) */ -#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */ - -/* - * Bits definition of the FIFO Control Register : WD16C552 or NS16550 - */ - -#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ -#define FIFO_EN 0x01 /* Enable the FIFO */ -#define XMIT_RESET 0x02 /* Transmit FIFO Reset */ -#define RCV_RESET 0x04 /* Receive FIFO Reset */ -#define FCR3 0x08 /* do not understand manual! */ - -#define RECEIVE_FIFO_TRIGGER1 0x00 /* trigger RX interrupt after 1 byte */ -#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger RX interrupt after 4 bytes */ -#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger RX interrupt after 8 bytes */ -#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger RX interrupt after 12 bytes */ -#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ - -#endif /* _BSPUART_H */ diff --git a/c/src/lib/libbsp/powerpc/shared/include/linker-symbols.h b/c/src/lib/libbsp/powerpc/shared/include/linker-symbols.h deleted file mode 100644 index 06f11655f6..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/include/linker-symbols.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file - * - * @ingroup powerpc_linker - * - * @brief Symbols defined in linker command base file. - */ - -/* - * Copyright (c) 2010-2015 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H -#define LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H - -#include <libcpu/powerpc-utility.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup powerpc_linker Linker Support - * - * @ingroup powerpc_shared - * - * @brief Linker support. - * - * @{ - */ - -LINKER_SYMBOL(bsp_section_start_begin) -LINKER_SYMBOL(bsp_section_start_end) -LINKER_SYMBOL(bsp_section_start_size) - -LINKER_SYMBOL(bsp_section_fast_text_begin) -LINKER_SYMBOL(bsp_section_fast_text_end) -LINKER_SYMBOL(bsp_section_fast_text_size) -LINKER_SYMBOL(bsp_section_fast_text_load_begin) -LINKER_SYMBOL(bsp_section_fast_text_load_end) - -LINKER_SYMBOL(bsp_section_text_begin) -LINKER_SYMBOL(bsp_section_text_end) -LINKER_SYMBOL(bsp_section_text_size) -LINKER_SYMBOL(bsp_section_text_load_begin) -LINKER_SYMBOL(bsp_section_text_load_end) - -LINKER_SYMBOL(bsp_section_rodata_begin) -LINKER_SYMBOL(bsp_section_rodata_end) -LINKER_SYMBOL(bsp_section_rodata_size) -LINKER_SYMBOL(bsp_section_rodata_load_begin) -LINKER_SYMBOL(bsp_section_rodata_load_end) - -LINKER_SYMBOL(bsp_section_fast_data_begin) -LINKER_SYMBOL(bsp_section_fast_data_end) -LINKER_SYMBOL(bsp_section_fast_data_size) -LINKER_SYMBOL(bsp_section_fast_data_load_begin) -LINKER_SYMBOL(bsp_section_fast_data_load_end) - -LINKER_SYMBOL(bsp_section_data_begin) -LINKER_SYMBOL(bsp_section_data_end) -LINKER_SYMBOL(bsp_section_data_size) -LINKER_SYMBOL(bsp_section_data_load_begin) -LINKER_SYMBOL(bsp_section_data_load_end) - -LINKER_SYMBOL(bsp_section_bss_begin) -LINKER_SYMBOL(bsp_section_bss_end) -LINKER_SYMBOL(bsp_section_bss_size) - -LINKER_SYMBOL(bsp_section_sbss_begin) -LINKER_SYMBOL(bsp_section_sbss_end) -LINKER_SYMBOL(bsp_section_sbss_size) - -LINKER_SYMBOL(bsp_section_rwextra_begin) -LINKER_SYMBOL(bsp_section_rwextra_end) -LINKER_SYMBOL(bsp_section_rwextra_size) - -LINKER_SYMBOL(bsp_section_work_begin) -LINKER_SYMBOL(bsp_section_work_end) -LINKER_SYMBOL(bsp_section_work_size) - -LINKER_SYMBOL(bsp_section_stack_begin) -LINKER_SYMBOL(bsp_section_stack_end) -LINKER_SYMBOL(bsp_section_stack_size) - -LINKER_SYMBOL(bsp_section_nocache_begin) -LINKER_SYMBOL(bsp_section_nocache_end) -LINKER_SYMBOL(bsp_section_nocache_size) -LINKER_SYMBOL(bsp_section_nocache_load_begin) -LINKER_SYMBOL(bsp_section_nocache_load_end) - -LINKER_SYMBOL(bsp_section_nocachenoload_begin) -LINKER_SYMBOL(bsp_section_nocachenoload_end) -LINKER_SYMBOL(bsp_section_nocachenoload_size) - -LINKER_SYMBOL(bsp_section_nocacheheap_begin) -LINKER_SYMBOL(bsp_section_nocacheheap_end) -LINKER_SYMBOL(bsp_section_nocacheheap_size) - -LINKER_SYMBOL(bsp_section_nvram_begin) -LINKER_SYMBOL(bsp_section_nvram_end) -LINKER_SYMBOL(bsp_section_nvram_size) - -#define BSP_FAST_TEXT_SECTION __attribute__((section(".bsp_fast_text"))) - -#define BSP_FAST_DATA_SECTION __attribute__((section(".bsp_fast_data"))) - -#define BSP_NOCACHE_SECTION __attribute__((section(".bsp_nocache"))) - -#define BSP_NOCACHENOLOAD_SECTION __attribute__((section(".bsp_noload_nocache"))) - -#define BSP_NVRAM_SECTION __attribute__((section(".bsp_nvram"))) - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_SHARED_LINKER_SYMBOLS_H */ diff --git a/c/src/lib/libbsp/powerpc/shared/include/nvram.h b/c/src/lib/libbsp/powerpc/shared/include/nvram.h deleted file mode 100644 index f579544336..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/include/nvram.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * PreP compliant NVRAM access - * - * This file can be found in motorla or IBP PPC site. - */ - -#ifndef _PPC_NVRAM_H -#define _PPC_NVRAM_H - -#define NVRAM_AS0 0x74 -#define NVRAM_AS1 0x75 -#define NVRAM_DATA 0x77 - -/* RTC Offsets */ - -#define MOTO_RTC_SECONDS 0x1FF9 -#define MOTO_RTC_MINUTES 0x1FFA -#define MOTO_RTC_HOURS 0x1FFB -#define MOTO_RTC_DAY_OF_WEEK 0x1FFC -#define MOTO_RTC_DAY_OF_MONTH 0x1FFD -#define MOTO_RTC_MONTH 0x1FFE -#define MOTO_RTC_YEAR 0x1FFF -#define MOTO_RTC_CONTROLA 0x1FF8 -#define MOTO_RTC_CONTROLB 0x1FF9 - -#ifndef BCD_TO_BIN -#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) -#endif - -#ifndef BIN_TO_BCD -#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) -#endif - -/* Structure map for NVRAM on PowerPC Reference Platform */ -/* All fields are either character/byte strings which are valid either - endian or they are big-endian numbers. - - There are a number of Date and Time fields which are in RTC format, - big-endian. These are stored in UT (GMT). - - For enum's: if given in hex then they are bit significant, i.e. only - one bit is on for each enum. -*/ - -#define NVSIZE 4096 /* size of NVRAM */ -#define OSAREASIZE 512 /* size of OSArea space */ -#define CONFSIZE 1024 /* guess at size of Configuration space */ - -#ifndef ASM - -typedef struct _SECURITY { - unsigned long BootErrCnt; /* Count of boot password errors */ - unsigned long ConfigErrCnt; /* Count of config password errors */ - unsigned long BootErrorDT[2]; /* Date&Time from RTC of last error in pw */ - unsigned long ConfigErrorDT[2]; /* Date&Time from RTC of last error in pw */ - unsigned long BootCorrectDT[2]; /* Date&Time from RTC of last correct pw */ - unsigned long ConfigCorrectDT[2]; /* Date&Time from RTC of last correct pw */ - unsigned long BootSetDT[2]; /* Date&Time from RTC of last set of pw */ - unsigned long ConfigSetDT[2]; /* Date&Time from RTC of last set of pw */ - unsigned char Serial[16]; /* Box serial number */ -} SECURITY; - -typedef enum _OS_ID { - Unknown = 0, - Firmware = 1, - AIX = 2, - NT = 3, - MKOS2 = 4, - MKAIX = 5, - Taligent = 6, - Solaris = 7, - MK = 12 -} OS_ID; - -typedef struct _ERROR_LOG { - unsigned char ErrorLogEntry[40]; /* To be architected */ -} ERROR_LOG; - -typedef enum _BOOT_STATUS { - BootStarted = 0x01, - BootFinished = 0x02, - RestartStarted = 0x04, - RestartFinished = 0x08, - PowerFailStarted = 0x10, - PowerFailFinished = 0x20, - ProcessorReady = 0x40, - ProcessorRunning = 0x80, - ProcessorStart = 0x0100 -} BOOT_STATUS; - -typedef struct _RESTART_BLOCK { - unsigned short Version; - unsigned short Revision; - unsigned long ResumeReserve1[2]; - volatile unsigned long BootStatus; - unsigned long CheckSum; /* Checksum of RESTART_BLOCK */ - void* RestartAddress; - void* SaveAreaAddr; - unsigned long SaveAreaLength; -} RESTART_BLOCK; - -typedef enum _OSAREA_USAGE { - Empty = 0, - Used = 1 -} OSAREA_USAGE; - -typedef enum _PM_MODE { - Suspend = 0x80, /* Part of state is in memory */ - Normal = 0x00 /* No power management in effect */ -} PMMode; - -typedef struct _HEADER { - unsigned short Size; /* NVRAM size in K(1024) */ - unsigned char Version; /* Structure map different */ - unsigned char Revision; /* Structure map the same -may - be new values in old fields - in other words old code still works */ - unsigned short Crc1; /* check sum from beginning of nvram to OSArea */ - unsigned short Crc2; /* check sum of config */ - unsigned char LastOS; /* OS_ID */ - unsigned char Endian; /* B if big endian, L if little endian */ - unsigned char OSAreaUsage;/* OSAREA_USAGE */ - unsigned char PMMode; /* Shutdown mode */ - RESTART_BLOCK RestartBlock; - SECURITY Security; - ERROR_LOG ErrorLog[2]; - - /* Global Environment information */ - void* GEAddress; - unsigned long GELength; - - /* Date&Time from RTC of last change to Global Environment */ - unsigned long GELastWriteDT[2]; - - /* Configuration information */ - void* ConfigAddress; - unsigned long ConfigLength; - - /* Date&Time from RTC of last change to Configuration */ - unsigned long ConfigLastWriteDT[2]; - unsigned long ConfigCount; /* Count of entries in Configuration */ - - /* OS dependent temp area */ - void* OSAreaAddress; - unsigned long OSAreaLength; - - /* Date&Time from RTC of last change to OSArea */ - unsigned long OSAreaLastWriteDT[2]; -} HEADER; - -/* Here is the whole map of the NVRAM */ -typedef struct _NVRAM_MAP { - HEADER Header; - unsigned char GEArea[NVSIZE-CONFSIZE-OSAREASIZE-sizeof(HEADER)]; - unsigned char OSArea[OSAREASIZE]; - unsigned char ConfigArea[CONFSIZE]; -} NVRAM_MAP; - -/* Routines to manipulate the NVRAM */ -void init_prep_nvram(void); -char *prep_nvram_get_var(const char *name); -char *prep_nvram_first_var(void); -char *prep_nvram_next_var(char *name); - -#endif /* ASM */ - -#endif /* _PPC_NVRAM_H */ diff --git a/c/src/lib/libbsp/powerpc/shared/include/start.h b/c/src/lib/libbsp/powerpc/shared/include/start.h deleted file mode 100644 index ab718a87ee..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/include/start.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * - * @ingroup powerpc_start - * - * @brief System low level start. - */ - -/* - * Copyright (c) 2010 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_SHARED_START_H -#define LIBBSP_POWERPC_SHARED_START_H - -#include <stddef.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup powerpc_start PowerPC System Start - * - * @ingroup powerpc_shared - * - * @brief PowerPC low level start. - * - * @{ - */ - -#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text"))) - -#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data"))) - -/** -* @brief System start entry. -*/ -void _start(void); - -/** - * Zeros @a byte_count bytes starting at @a begin. - * - * It wraps around in case of an address overflow. The stack will not be used. - * The code is position independent. It uses the data cache block zero - * instruction in case the data cache is enabled. There are no alignment - * constains for @a begin and @a byte_count. - * - * @see bsp_start_zero_begin, bsp_start_zero_end, and bsp_start_zero_size. - */ -void BSP_START_TEXT_SECTION bsp_start_zero(void *begin, size_t byte_count); - -/** - * @brief Symbol which equals the bsp_start_zero() code begin. - */ -extern char bsp_start_zero_begin []; - -/** - * @brief Symbol which equals the bsp_start_zero() code end. - */ -extern char bsp_start_zero_end []; - -/** - * @brief Symbol which equals the bsp_start_zero() code size. - */ -extern char bsp_start_zero_size []; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_SHARED_START_H */ diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq.h b/c/src/lib/libbsp/powerpc/shared/irq/irq.h deleted file mode 100644 index 2d575d8122..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/irq/irq.h +++ /dev/null @@ -1,204 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by RTEMS to write interrupt handlers. - * - * Copyright (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef BSP_POWERPC_IRQ_H -#define BSP_POWERPC_IRQ_H - -#define BSP_SHARED_HANDLER_SUPPORT 1 -#include <rtems/irq.h> - -/* - * 8259 edge/level control definitions at VIA - */ -#define ISA8259_M_ELCR 0x4d0 -#define ISA8259_S_ELCR 0x4d1 - -#define ELCRS_INT15_LVL 0x80 -#define ELCRS_INT14_LVL 0x40 -#define ELCRS_INT13_LVL 0x20 -#define ELCRS_INT12_LVL 0x10 -#define ELCRS_INT11_LVL 0x08 -#define ELCRS_INT10_LVL 0x04 -#define ELCRS_INT9_LVL 0x02 -#define ELCRS_INT8_LVL 0x01 -#define ELCRM_INT7_LVL 0x80 -#define ELCRM_INT6_LVL 0x40 -#define ELCRM_INT5_LVL 0x20 -#define ELCRM_INT4_LVL 0x10 -#define ELCRM_INT3_LVL 0x8 -#define ELCRM_INT2_LVL 0x4 -#define ELCRM_INT1_LVL 0x2 -#define ELCRM_INT0_LVL 0x1 - - /* PIC's command and mask registers */ -#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ -#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ -#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ -#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ - - /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ -#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ -#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ -#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * rtems_irq_number Definitions - */ - -/* - * ISA IRQ handler related definitions - */ -#define BSP_ISA_IRQ_NUMBER (16) -#define BSP_ISA_IRQ_LOWEST_OFFSET (0) -#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) -/* - * PCI IRQ handlers related definitions - * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE - */ -#ifndef qemu -#define BSP_PCI_IRQ_NUMBER (16) -#else -#define BSP_PCI_IRQ_NUMBER (0) -#endif -#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) -#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) -/* - * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt - * handler might be connected - */ -#define BSP_PROCESSOR_IRQ_NUMBER (1) -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) -/* Misc vectors for OPENPIC irqs (IPI, timers) - */ -#ifndef qemu -#define BSP_MISC_IRQ_NUMBER (8) -#else -#define BSP_MISC_IRQ_NUMBER (0) -#endif - -#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) -#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) -#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) -#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) -/* - * Some ISA IRQ symbolic name definition - */ -#define BSP_ISA_PERIODIC_TIMER (0) -#define BSP_ISA_KEYBOARD (1) -#define BSP_ISA_UART_COM2_IRQ (3) -#define BSP_ISA_UART_COM1_IRQ (4) -#define BSP_ISA_RT_TIMER1 (8) -#define BSP_ISA_RT_TIMER3 (10) -/* - * Some PCI IRQ symbolic name definition - */ -#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) -#if BSP_PCI_IRQ_NUMBER > 0 -#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) -#endif - -#if defined(mvme2100) -#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) -#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) -#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) -#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4) -#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5) -#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7) -#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) -#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) -#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) -#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13) -#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14) -#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15) -#else -#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ -#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ -#endif - -/* - * Some Processor execption handled as RTEMS IRQ symbolic name definition - */ -#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) - - -/* - * Type definition for RTEMS managed interrupts - */ -typedef unsigned short rtems_i8259_masks; - -extern volatile rtems_i8259_masks i8259s_cache; - -/*-------------------------------------------------------------------------+ -| Function Prototypes. -+--------------------------------------------------------------------------*/ -/* - * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- - */ -void BSP_i8259s_init(void); - -/* - * function to disable a particular irq at 8259 level. After calling - * this function, even if the device asserts the interrupt line it will - * not be propagated further to the processor - * - * RETURNS: 1/0 if the interrupt was enabled/disabled originally or - * a value < 0 on error. - */ -int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); -/* - * function to enable a particular irq at 8259 level. After calling - * this function, if the device asserts the interrupt line it will - * be propagated further to the processor - */ -int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); -/* - * function to acknowledge a particular irq at 8259 level. After calling - * this function, if a device asserts an enabled interrupt line it will - * be propagated further to the processor. Mainly usefull for people - * writing raw handlers as this is automagically done for RTEMS managed - * handlers. - */ -int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); -/* - * function to check if a particular irq is enabled at 8259 level. After calling - */ -int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); - -extern void BSP_rtems_irq_mng_init(unsigned cpuId); -extern void BSP_i8259s_init(void); - -/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */ -#include <bsp/irq_supp.h> - -#ifdef __cplusplus -}; -#endif - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/shared/pci/pci.h b/c/src/lib/libbsp/powerpc/shared/pci/pci.h deleted file mode 100644 index 42dc43875b..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/pci/pci.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * PCI defines and function prototypes - * - * For more information, please consult the following manuals (look at - * http://www.pcisig.com/ for how to get them): - * - * PCI BIOS Specification - * PCI Local Bus Specification - * PCI to PCI Bridge Specification - * PCI System Design Guide - */ - -/* - * Copyright 1994, Drew Eckhardt - * Copyright 1997, 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz> - */ - -#ifndef BSP_POWERPC_PCI_H -#define BSP_POWERPC_PCI_H - -#include <rtems/pci.h> -#include <stdio.h> - -struct _pin_routes -{ - int pin; - int int_name[4]; -}; -struct _int_map -{ - int bus; - int slot; - int opts; - struct _pin_routes pin_route[5]; -}; - -/* If there's a conflict between a name in the routing table and - * what's already set on the device, reprogram the device setting - * to reflect int_name[0] for the routing table entry - */ -#define PCI_FIXUP_OPT_OVERRIDE_NAME (1<<0) - -/* - * This is assumed to be provided by the BSP. - */ -void detect_host_bridge(void); - -void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) ); - -/* FIXME: This probably belongs into rtems/pci.h */ -extern unsigned char pci_bus_count(); - -/* FIXME: This also is generic and could go into rtems/pci.h */ - -/* Scan pci config space and run a user callback on each - * device present; the user callback may return 0 to - * continue the scan or a value > 0 to abort the scan. - * Return values < 0 are reserved and must not be used. - * - * RETURNS: a (opaque) handle pointing to the bus/slot/fn-triple - * just after where the scan was aborted by a callback - * returning 1 (see above) or NULL if all devices were - * scanned. - * The handle may be passed to this routine to resume the - * scan continuing with the device after the one causing the - * abort. - * Pass a NULL 'handle' argument to start scanning from - * the beginning (bus/slot/fn = 0/0/0). - */ -typedef void *BSP_PciScanHandle; -typedef int (*BSP_PciScannerCb)(int bus, int slot, int fun, void *uarg); - -BSP_PciScanHandle -BSP_pciScan(BSP_PciScanHandle handle, BSP_PciScannerCb cb, void *uarg); - -/* Dump basic config. space info to a file. The argument may - * be NULL in which case 'stdout' is used. - * NOTE: the C-library must be functional before you can use - * this routine. - */ -void -BSP_pciConfigDump(FILE *fp); - -#endif /* BSP_POWERPC_PCI_H */ diff --git a/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h deleted file mode 100644 index 9b355819f1..0000000000 --- a/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h +++ /dev/null @@ -1,233 +0,0 @@ -#ifndef RTEMS_BSP_VME_CONFIG_H -#define RTEMS_BSP_VME_CONFIG_H - -/* BSP specific address space configuration parameters */ - -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 2002, - * Stanford Linear Accelerator Center, Stanford University. - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -/* - * The BSP maps VME address ranges into - * one BAT. - * NOTE: the BSP (startup/bspstart.c) uses - * hardcoded window lengths that match this - * layout: - * - * BSP_VME_BAT_IDX defines - * which BAT to use for mapping the VME bus. - * If this is undefined, no extra BAT will be - * configured and VME has to share the available - * PCI address space with PCI devices. - * - * If you do define BSP_VME_BAT_IDX you must - * make sure the corresponding BAT is really - * available and unused! - */ - -#if defined(mvme2100) -#define _VME_A32_WIN0_ON_PCI 0x90000000 -#define _VME_A24_ON_PCI 0x9f000000 -#define _VME_A16_ON_PCI 0x9fff0000 -#define BSP_VME_BAT_IDX 1 -#else -#define _VME_A32_WIN0_ON_PCI 0x10000000 -#define _VME_A24_ON_PCI 0x1f000000 -#define _VME_A16_ON_PCI 0x1fff0000 -#define BSP_VME_BAT_IDX 0 -#endif - -/* start of the A32 window on the VME bus - * TODO: this should perhaps be a run-time configuration option - */ -#define _VME_A32_WIN0_ON_VME 0x20000000 - -/* if _VME_DRAM_OFFSET is defined, the BSP - * will map the board RAM onto the VME bus, starting - * at _VME_DRAM_OFFSET - */ -#define _VME_DRAM_OFFSET 0xc0000000 - -/* Define BSP_PCI_VME_DRIVER_DOES_EOI to let the vmeUniverse - * driver (Tsi148 driver doesn't implement this) implement - * VME IRQ priorities in software. - * - * Here's how this works: - * - * 1) VME IRQ happens - * 2) universe propagates IRQ to PCI/PPC/main interrupt - * controller ('PIC' - programmable interrupt controller). - * 3) PIC driver dispatches universe driver's ISR - * 4) universe driver ISR acknowledges IRQ on VME, - * determines VME vector. - * ++++++++++++ stuff between ++ signs is related to SW priorities +++++++++ - * 5) universe driver *masks* all VME IRQ levels <= interrupting - * level. - * 6) universe driver calls PIC driver's 'EOI' routine. - * This effectively re-enables PCI and hence higher - * level VME interrupts. - * 7) universe driver dispatches user VME ISR. - * - * ++>> HIGHER PRIORITY VME IRQ COULD HAPPEN HERE and would be handled <<++ - * - * 8) user ISR returns, universe driver re-enables lower - * level VME interrupts, returns. - * 9) universe driver ISR returns control to PIC driver - * 10) PIC driver *omits* regular EOI sequence since this - * was already done by universe driver (step 6). - * ++++++++++++ end of special handling (SW priorities) ++++++++++++++++++++ - * 11) PIC driver ISR dispatcher returns. - * - * Note that the BSP *MUST* provide the following hooks - * in order for this to work: - * a) bsp.h must define the symbol BSP_PIC_DO_EOI to - * a sequence of instructions that terminates an - * interrupt at the interrupt controller. - * b) The interrupt controller driver must check the - * interrupt source and *must omit* running the EOI - * sequence if the interrupt source is the vmeUniverse - * (because the universe driver already ran BSP_PIC_DO_EOI) - * The interrupt controller must define the variable - * - * int _BSP_vme_bridge_irq = -1; - * - * which is assigned the universe's interrupt line information - * by vme_universe.c:BSP_VMEIrqMgrInstall(). The interrupt - * controller driver may use this variable to determine - * if an IRQ was caused by the universe. - * - * c) define BSP_PCI_VME_DRIVER_DOES_EOI - * - * NOTE: If a) and b) are not implemented by the BSP - * BSP_PCI_VME_DRIVER_DOES_EOI must be *undefined*. - */ -#define BSP_PCI_VME_DRIVER_DOES_EOI - -#ifdef BSP_PCI_VME_DRIVER_DOES_EOI -/* don't reference vmeUniverse0PciIrqLine directly from the irq - * controller driver - leave it up to BSP_VMEIrqMgrInstall() to - * set _BSP_vme_bridge_irq. That way, we can avoid linking - * the universe driver if VME is unused... - */ -extern int _BSP_vme_bridge_irq; -#endif - -/* If your BSP requires a non-standard way to configure - * the VME interrupt manager then define the symbol - * - * BSP_VME_UNIVERSE_INSTALL_IRQ_MGR - * - * to a proper instruction sequence that installs the - * universe interrupt manager. This requires knowledge - * of the wiring between the universe and the PIC (main - * interrupt controller), i.e., which IRQ 'pins' of the - * universe are wired to which 'lines'/inputs at the PIC. - * (consult vmeUniverse.h for more information). - * - * When installing the universe IRQ manager it is also - * possible to specify whether it should try to share - * PIC interrupts with other sources. This might not - * be supported by all BSPs (but the unverse driver - * recognizes that). - * - * If BSP_VME_UNIVERSE_INSTALL_IRQ_MGR is undefined then - * the default algorithm is used (vme_universe.c): - * - * This default setup uses only a single wire. It reads - * the PIC 'line' from PCI configuration space and assumes - * this to be wired to the first (LIRQ0) IRQ input at the - * universe. The default setup tries to use interrupt - * sharing. - */ - -#include <bsp/motorola.h> -#include <bsp/pci.h> - -#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \ -do { \ -int bus, dev, i = 0, j; \ -const struct _int_map *bspmap; \ - /* install the VME interrupt manager; \ - * if there's a bsp route map, use it to \ - * configure additional lines... \ - */ \ - err = -1; \ - if (0 == pci_find_device(0x10e3, 0x0000, 0, &bus, &dev, &i)){ \ - if ( (bspmap = motorolaIntMap(currentBoard)) ) { \ - for ( i=0; bspmap[i].bus >= 0; i++ ) { \ - if ( bspmap[i].bus == bus && bspmap[i].slot == dev ) { \ - int pins[5], names[4]; \ - /* found it; use info here... */ \ - /* copy up to 4 entries; terminated with -1 pin */ \ - for ( j=0; \ - j<5 && (pins[j]=bspmap[i].pin_route[j].pin-1)>=0; \ - j++) { \ - names[j] = bspmap[i].pin_route[j].int_name[0]; \ - } \ - pins[4] = -1; \ - if ( 0 == vmeUniverseInstallIrqMgrAlt( \ - VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, /* shared IRQs */\ - pins[0], names[0], \ - pins[1], names[1], \ - pins[2], names[2], \ - pins[3], names[3], \ - -1) ) { \ - i = -1; \ - break; \ - } \ - } \ - } \ - } \ - if ( i >= 0 ) \ - err = vmeUniverseInstallIrqMgrAlt( \ - VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, \ - 0,-1, \ - -1); \ - } \ -} while (0) - -extern int BSP_VMEInit(void); -extern int BSP_VMEIrqMgrInstall(void); - -#endif diff --git a/c/src/lib/libbsp/powerpc/ss555/include/bsp.h b/c/src/lib/libbsp/powerpc/ss555/include/bsp.h deleted file mode 100644 index 7a814a8f8c..0000000000 --- a/c/src/lib/libbsp/powerpc/ss555/include/bsp.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file includes definitions for the Intec SS555. - */ - -/* - * SS555 port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h: - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_SS555_BSP_H -#define LIBBSP_POWERPC_SS555_BSP_H - -#ifndef ASM - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <mpc5xx.h> -#include <mpc5xx/console.h> -#include <libcpu/vectors.h> -#include <bsp/irq.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Clock definitions - */ - -#define BSP_CRYSTAL_HZ 4000000 /* crystal frequency, Hz */ -#define BSP_CLOCK_HZ 40000000 /* CPU clock frequency, Hz - -/* - * I/O definitions - * - * The SS555 board includes a CPLD to control on-board features and - * off-board devices. - */ -typedef struct cpld_ { - uint8_t cs3a[32]; /* Chip select 3A */ - uint8_t pad0[0x200000 - 0x000020]; - - uint8_t cs3b[32]; /* Chip select 3B */ - uint8_t pad2[0x400000 - 0x200020]; - - uint8_t cs3c[32]; /* Chip select 3C */ - uint8_t pad4[0x600000 - 0x400020]; - - uint8_t cs3d[32]; /* Chip select 3D */ - uint8_t pad6[0x800000 - 0x600020]; - - uint8_t serial_ints; /* Enable/disable serial interrupts */ - uint8_t serial_resets; /* Enable/disable serial resets */ - uint8_t serial_ack; /* Acknowledge serial transfers */ - uint8_t pad8[0xA00000 - 0x800003]; - - uint8_t iflash_writess; /* Enable/disable internal-flash writes */ - uint8_t nflash_writess; /* Enable/disable NAND-flash writes */ - uint8_t padA[0xC00000 - 0xA00002]; -} cpld_t; - -extern volatile cpld_t cpld; /* defined in linkcmds */ - -/* clock/p_clock.c */ -extern int BSP_disconnect_clock_handler (void); - -extern int BSP_connect_clock_handler (rtems_irq_hdl hdl); - -/* - * Prototypes for methods called from .S to support dependency tracking. - */ -void _InitSS555(void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/ss555/include/tm27.h b/c/src/lib/libbsp/powerpc/ss555/include/tm27.h deleted file mode 100644 index 5106801744..0000000000 --- a/c/src/lib/libbsp/powerpc/ss555/include/tm27.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * @file - * @ingroup powerpc_ss555 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * - * The following require that IRQ7 be jumpered to ground. On the SS555, - * this can be done by shorting together CN5 pin 48 and CN5 pin 50. - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ -{ \ - extern rtems_irq_connect_data tm27IrqData; \ - usiu.siel |= (1 << 17); \ - usiu.sipend |= (1 << 17); \ - \ - tm27IrqData.hdl = (rtems_irq_hdl)handler; \ - BSP_install_rtems_irq_handler (&tm27IrqData); \ -} - -#define Cause_tm27_intr() \ -{ \ - usiu.siel &= ~(1 << 17); \ -} - -#define Clear_tm27_intr() \ -{ \ - usiu.siel |= (1 << 17); \ - usiu.sipend |= (1 << 17); \ -} - -#define Lower_tm27_intr() \ -{ \ - ppc_cached_irq_mask |= (1 << 17); \ - usiu.simask = ppc_cached_irq_mask; \ -} - -#endif diff --git a/c/src/lib/libbsp/powerpc/ss555/irq/irq.h b/c/src/lib/libbsp/powerpc/ss555/irq/irq.h deleted file mode 100644 index 31c4be9a9e..0000000000 --- a/c/src/lib/libbsp/powerpc/ss555/irq/irq.h +++ /dev/null @@ -1,67 +0,0 @@ -/* irq.h - * - * This include file describe the data structure and the functions implemented - * by rtems to write interrupt handlers. - * - * - * SS555 port sponsored by Defence Research and Development Canada - Suffield - * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) - * - * Derived from libbsp/powerpc/mbx8xx/irq/irq.h: - * - * CopyRight (C) 1999 valette@crf.canon.fr - * - * This code is heavilly inspired by the public specification of STREAM V2 - * that can be found at : - * - * <http://www.chorus.com/Documentation/index.html> by following - * the STREAM API Specification Document link. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_SS555_IRQ_IRQ_H -#define LIBBSP_POWERPC_SS555_IRQ_IRQ_H - -#include <libcpu/irq.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * These are no longer prototyped anywhere else. This appears to be - * remnants of the IRQ code upgrade. - * - * --joel 28 April 2010 - */ -int CPU_install_rtems_irq_handler(const rtems_irq_connect_data* irq); -int CPU_get_current_rtems_irq_handler(rtems_irq_connect_data* irq); -int CPU_remove_rtems_irq_handler(const rtems_irq_connect_data* irq); -int CPU_rtems_irq_mngt_set(rtems_irq_global_settings* config); -int CPU_rtems_irq_mngt_get(rtems_irq_global_settings** config); -void C_dispatch_irq_handler(CPU_Interrupt_frame *frame, unsigned int excNum); -void C_default_exception_handler(CPU_Exception_frame* excPtr); - -/* - * The SS555 has no external interrupt controller chip, so use the standard - * routines from the CPU-dependent code. - */ -#define BSP_install_rtems_irq_handler(ptr) CPU_install_rtems_irq_handler(ptr) -#define BSP_get_current_rtems_irq_handler(ptr) CPU_get_current_rtems_irq_handler(ptr) -#define BSP_remove_rtems_irq_handler(ptr) CPU_remove_rtems_irq_handler(ptr) -#define BSP_rtems_irq_mngt_set(config) CPU_rtems_irq_mngt_set(config) -#define BSP_rtems_irq_mngt_get(config) CPU_rtems_irq_mngt_get(config) -#define BSP_rtems_irq_mng_init(cpuId) CPU_rtems_irq_mng_init(cpuId) - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* LIBBSP_POWERPC_SS555_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h b/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h deleted file mode 100644 index 4ce387710b..0000000000 --- a/c/src/lib/libbsp/powerpc/t32mppc/include/bsp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2012-2014 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Dornierstr. 4 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_T32MPPC_BSP_H -#define LIBBSP_POWERPC_T32MPPC_BSP_H - -#include <bspopts.h> - -#ifndef ASM - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_T32MPPC_BSP_H */ diff --git a/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h b/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h deleted file mode 100644 index 4a01bf4f9f..0000000000 --- a/c/src/lib/libbsp/powerpc/t32mppc/include/irq.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_T32MPPC_IRQ_H -#define LIBBSP_POWERPC_T32MPPC_IRQ_H - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 0 - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_T32MPPC_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/include/8xx_immap.h b/c/src/lib/libbsp/powerpc/tqm8xx/include/8xx_immap.h deleted file mode 100644 index c1c414e25f..0000000000 --- a/c/src/lib/libbsp/powerpc/tqm8xx/include/8xx_immap.h +++ /dev/null @@ -1,477 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS BSP support for TQ modules | -+-----------------------------------------------------------------+ -| Partially based on the code references which are named below. | -| Adaptions, modifications, enhancements and any recent parts of | -| the code are: | -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains definitions to interact with TQC's | -| processor modules | -\*===============================================================*/ -/* derived from mbx8xx BSP */ -/* - * MPC8xx Internal Memory Map - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * The I/O on the MPC860 is comprised of blocks of special registers - * and the dual port ram for the Communication Processor Module. - * Within this space are functional units such as the SIU, memory - * controller, system timers, and other control functions. It is - * a combination that I found difficult to separate into logical - * functional files.....but anyone else is welcome to try. -- Dan - */ -#ifndef __IMMAP_8XX__ -#define __IMMAP_8XX__ - -/* System configuration registers. -*/ -typedef struct sys_conf { - unsigned int sc_siumcr; - unsigned int sc_sypcr; - unsigned int sc_swt; - char res1[2]; - unsigned short sc_swsr; - unsigned int sc_sipend; - unsigned int sc_simask; - unsigned int sc_siel; - unsigned int sc_sivec; - unsigned int sc_tesr; - char res2[0xc]; - unsigned int sc_sdcr; - char res3[0x4c]; -} sysconf8xx_t; - -/* PCMCIA configuration registers. -*/ -typedef struct pcmcia_conf { - unsigned int pcmc_pbr0; - unsigned int pcmc_por0; - unsigned int pcmc_pbr1; - unsigned int pcmc_por1; - unsigned int pcmc_pbr2; - unsigned int pcmc_por2; - unsigned int pcmc_pbr3; - unsigned int pcmc_por3; - unsigned int pcmc_pbr4; - unsigned int pcmc_por4; - unsigned int pcmc_pbr5; - unsigned int pcmc_por5; - unsigned int pcmc_pbr6; - unsigned int pcmc_por6; - unsigned int pcmc_pbr7; - unsigned int pcmc_por7; - char res1[0x20]; - unsigned int pcmc_pgcra; - unsigned int pcmc_pgcrb; - unsigned int pcmc_pscr; - char res2[4]; - unsigned int pcmc_pipr; - char res3[4]; - unsigned int pcmc_per; - char res4[4]; -} pcmconf8xx_t; - -/* Memory controller registers. -*/ -typedef struct mem_ctlr { - unsigned int memc_br0; - unsigned int memc_or0; - unsigned int memc_br1; - unsigned int memc_or1; - unsigned int memc_br2; - unsigned int memc_or2; - unsigned int memc_br3; - unsigned int memc_or3; - unsigned int memc_br4; - unsigned int memc_or4; - unsigned int memc_br5; - unsigned int memc_or5; - unsigned int memc_br6; - unsigned int memc_or6; - unsigned int memc_br7; - unsigned int memc_or7; - char res1[0x24]; - unsigned int memc_mar; - unsigned int memc_mcr; - char res2[4]; - unsigned int memc_mamr; - unsigned int memc_mbmr; - unsigned short memc_mstat; - unsigned short memc_mptpr; - unsigned int memc_mdr; - char res3[0x80]; -} memctl8xx_t; - -/* System Integration Timers. -*/ -typedef struct sys_int_timers { - unsigned short sit_tbscr; - unsigned int sit_tbreff0; - unsigned int sit_tbreff1; - char res1[0x14]; - unsigned short sit_rtcsc; - unsigned int sit_rtc; - unsigned int sit_rtsec; - unsigned int sit_rtcal; - char res2[0x10]; - unsigned short sit_piscr; - char res3[2]; - unsigned int sit_pitc; - unsigned int sit_pitr; - char res4[0x34]; -} sit8xx_t; - -#define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) -#define TBSCR_REFA ((unsigned short)0x0080) -#define TBSCR_REFB ((unsigned short)0x0040) -#define TBSCR_REFAE ((unsigned short)0x0008) -#define TBSCR_REFBE ((unsigned short)0x0004) -#define TBSCR_TBF ((unsigned short)0x0002) -#define TBSCR_TBE ((unsigned short)0x0001) - -#define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) -#define RTCSC_SEC ((unsigned short)0x0080) -#define RTCSC_ALR ((unsigned short)0x0040) -#define RTCSC_38K ((unsigned short)0x0010) -#define RTCSC_SIE ((unsigned short)0x0008) -#define RTCSC_ALE ((unsigned short)0x0004) -#define RTCSC_RTF ((unsigned short)0x0002) -#define RTCSC_RTE ((unsigned short)0x0001) - -#define PISCR_PIRQ_MASK ((unsigned short)0xff00) -#define PISCR_PS ((unsigned short)0x0080) -#define PISCR_PIE ((unsigned short)0x0004) -#define PISCR_PTF ((unsigned short)0x0002) -#define PISCR_PTE ((unsigned short)0x0001) - -/* Clocks and Reset. -*/ -typedef struct clk_and_reset { - unsigned int car_sccr; - unsigned int car_plprcr; - unsigned int car_rsr; - char res[0x74]; /* Reserved area */ -} car8xx_t; - -/* System Integration Timers keys. -*/ -typedef struct sitk { - unsigned int sitk_tbscrk; - unsigned int sitk_tbreff0k; - unsigned int sitk_tbreff1k; - unsigned int sitk_tbk; - char res1[0x10]; - unsigned int sitk_rtcsck; - unsigned int sitk_rtck; - unsigned int sitk_rtseck; - unsigned int sitk_rtcalk; - char res2[0x10]; - unsigned int sitk_piscrk; - unsigned int sitk_pitck; - char res3[0x38]; -} sitk8xx_t; - -/* Clocks and reset keys. -*/ -typedef struct cark { - unsigned int cark_sccrk; - unsigned int cark_plprcrk; - unsigned int cark_rsrk; - char res[0x474]; -} cark8xx_t; - -/* The key to unlock registers maintained by keep-alive power. -*/ -#define KAPWR_KEY ((unsigned int)0x55ccaa33) - -/* LCD interface. MPC821 Only. -*/ -typedef struct lcd { - unsigned short lcd_lcolr[16]; - char res[0x20]; - unsigned int lcd_lccr; - unsigned int lcd_lchcr; - unsigned int lcd_lcvcr; - char res2[4]; - unsigned int lcd_lcfaa; - unsigned int lcd_lcfba; - char lcd_lcsr; - char res3[0x7]; -} lcd8xx_t; - -/* I2C -*/ -typedef struct i2c { - unsigned char i2c_i2mod; - char res1[3]; - unsigned char i2c_i2add; - char res2[3]; - unsigned char i2c_i2brg; - char res3[3]; - unsigned char i2c_i2com; - char res4[3]; - unsigned char i2c_i2cer; - char res5[3]; - unsigned char i2c_i2cmr; - char res6[0x8b]; -} i2c8xx_t; - -/* DMA control/status registers. -*/ -typedef struct sdma_csr { - char res1[4]; - unsigned int sdma_sdar; - unsigned char sdma_sdsr; - char res3[3]; - unsigned char sdma_sdmr; - char res4[3]; - unsigned char sdma_idsr1; - char res5[3]; - unsigned char sdma_idmr1; - char res6[3]; - unsigned char sdma_idsr2; - char res7[3]; - unsigned char sdma_idmr2; - char res8[0x13]; -} sdma8xx_t; - -/* Communication Processor Module Interrupt Controller. -*/ -typedef struct cpm_ic { - unsigned short cpic_civr; - char res[0xe]; - unsigned int cpic_cicr; - unsigned int cpic_cipr; - unsigned int cpic_cimr; - unsigned int cpic_cisr; -} cpic8xx_t; - -/* Input/Output Port control/status registers. -*/ -typedef struct io_port { - unsigned short iop_padir; - unsigned short iop_papar; - unsigned short iop_paodr; - unsigned short iop_padat; - char res1[8]; - unsigned short iop_pcdir; - unsigned short iop_pcpar; - unsigned short iop_pcso; - unsigned short iop_pcdat; - unsigned short iop_pcint; - char res2[6]; - unsigned short iop_pddir; - unsigned short iop_pdpar; - char res3[2]; - unsigned short iop_pddat; - char res4[8]; -} iop8xx_t; - -/* Communication Processor Module Timers -*/ -typedef struct cpm_timers { - unsigned short cpmt_tgcr; - char res1[0xe]; - unsigned short cpmt_tmr1; - unsigned short cpmt_tmr2; - unsigned short cpmt_trr1; - unsigned short cpmt_trr2; - unsigned short cpmt_tcr1; - unsigned short cpmt_tcr2; - unsigned short cpmt_tcn1; - unsigned short cpmt_tcn2; - unsigned short cpmt_tmr3; - unsigned short cpmt_tmr4; - unsigned short cpmt_trr3; - unsigned short cpmt_trr4; - unsigned short cpmt_tcr3; - unsigned short cpmt_tcr4; - unsigned short cpmt_tcn3; - unsigned short cpmt_tcn4; - unsigned short cpmt_ter1; - unsigned short cpmt_ter2; - unsigned short cpmt_ter3; - unsigned short cpmt_ter4; - char res2[8]; -} cpmtimer8xx_t; - -/* Finally, the Communication Processor stuff..... -*/ -typedef struct scc { /* Serial communication channels */ - unsigned int scc_gsmrl; - unsigned int scc_gsmrh; - unsigned short scc_pmsr; - char res1[2]; - unsigned short scc_todr; - unsigned short scc_dsr; - unsigned short scc_scce; - char res2[2]; - unsigned short scc_sccm; - char res3; - unsigned char scc_sccs; - char res4[8]; -} scc_t; - -typedef struct smc { /* Serial management channels */ - char res1[2]; - unsigned short smc_smcmr; - char res2[2]; - unsigned char smc_smce; - char res3[3]; - unsigned char smc_smcm; - char res4[5]; -} smc_t; - -/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but - * it fits within the address space. - */ -typedef struct fec { - unsigned int fec_addr_low; /* LS 32 bits of station address */ - unsigned short fec_addr_high; /* MS 16 bits of address */ - unsigned short res1; - unsigned int fec_hash_table_high; - unsigned int fec_hash_table_low; - unsigned int fec_r_des_start; - unsigned int fec_x_des_start; - unsigned int fec_r_buff_size; - unsigned int res2[9]; - unsigned int fec_ecntrl; - unsigned int fec_ievent; - unsigned int fec_imask; - unsigned int fec_ivec; - unsigned int fec_r_des_active; - unsigned int fec_x_des_active; - unsigned int res3[10]; - unsigned int fec_mii_data; - unsigned int fec_mii_speed; - unsigned int res4[17]; - unsigned int fec_r_bound; - unsigned int fec_r_fstart; - unsigned int res5[6]; - unsigned int fec_x_fstart; - unsigned int res6[17]; - unsigned int fec_fun_code; - unsigned int res7[3]; - unsigned int fec_r_cntrl; - unsigned int fec_r_hash; - unsigned int res8[14]; - unsigned int fec_x_cntrl; - unsigned int res9[0x1e]; -} fec_t; - -typedef struct comm_proc { - /* General control and status registers. - */ - unsigned short cp_cpcr; - char res1[2]; - unsigned short cp_rccr; - char res2[6]; - unsigned short cp_cpmcr1; - unsigned short cp_cpmcr2; - unsigned short cp_cpmcr3; - unsigned short cp_cpmcr4; - char res3[2]; - unsigned short cp_rter; - char res4[2]; - unsigned short cp_rtmr; - char res5[0x14]; - - /* Baud rate generators. - */ - unsigned int cp_brgc1; - unsigned int cp_brgc2; - unsigned int cp_brgc3; - unsigned int cp_brgc4; - - /* Serial Communication Channels. - */ - scc_t cp_scc[4]; - - /* Serial Management Channels. - */ - smc_t cp_smc[2]; - - /* Serial Peripheral Interface. - */ - unsigned short cp_spmode; - char res6[4]; - unsigned char cp_spie; - char res7[3]; - unsigned char cp_spim; - char res8[2]; - unsigned char cp_spcom; - char res9[2]; - - /* Parallel Interface Port. - */ - char res10[2]; - unsigned short cp_pipc; - char res11[2]; - unsigned short cp_ptpr; - unsigned int cp_pbdir; - unsigned int cp_pbpar; - char res12[2]; - unsigned short cp_pbodr; - unsigned int cp_pbdat; - char res13[0x18]; - - /* Serial Interface and Time Slot Assignment. - */ - unsigned int cp_simode; - unsigned char cp_sigmr; - char res14; - unsigned char cp_sistr; - unsigned char cp_sicmr; - char res15[4]; - unsigned int cp_sicr; - unsigned int cp_sirp; - char res16[0x10c]; - unsigned char cp_siram[0x200]; - - /* The fast ethernet controller is not really part of the CPM, - * but it resides in the address space. - */ - fec_t cp_fec; - char res18[0x1000]; - - /* Dual Ported RAM follows. - * There are many different formats for this memory area - * depending upon the devices used and options chosen. - */ - unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ - unsigned char res19[0xc00]; - unsigned char cp_dparam[0x400]; /* Parameter RAM */ -} cpm8xx_t; - -/* Internal memory map. -*/ -typedef struct immap { - sysconf8xx_t im_siu_conf; /* SIU Configuration */ - pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ - memctl8xx_t im_memctl; /* Memory Controller */ - sit8xx_t im_sit; /* System integration timers */ - car8xx_t im_clkrst; /* Clocks and reset */ - sitk8xx_t im_sitk; /* Sys int timer keys */ - cark8xx_t im_clkrstk; /* Clocks and reset keys */ - lcd8xx_t im_lcd; /* LCD (821 only) */ - i2c8xx_t im_i2c; /* I2C control/status */ - sdma8xx_t im_sdma; /* SDMA control/status */ - cpic8xx_t im_cpic; /* CPM Interrupt Controller */ - iop8xx_t im_ioport; /* IO Port control/status */ - cpmtimer8xx_t im_cpmtimer; /* CPM timers */ - cpm8xx_t im_cpm; /* Communication processor */ -} immap_t; - -#endif /* __IMMAP_8XX__ */ diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/include/bsp.h b/c/src/lib/libbsp/powerpc/tqm8xx/include/bsp.h deleted file mode 100644 index 51dc78936f..0000000000 --- a/c/src/lib/libbsp/powerpc/tqm8xx/include/bsp.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * RTEMS TQM8xx BSP - * This include file contains all board IO definitions. - */ - -/* - * This file has been adapted to MPC8xx by: - * Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> - * Copyright (c) 2008 - * Embedded Brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * rtems@embedded-brains.de - * - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_TQM8XX_BSP_H -#define LIBBSP_POWERPC_TQM8XX_BSP_H - -/* - * indicate, that BSP is booted via TQMMon - */ -#define BSP_HAS_TQMMON - -#include <libcpu/powerpc-utility.h> - -LINKER_SYMBOL(TopRamReserved); - -LINKER_SYMBOL( bsp_ram_start); -LINKER_SYMBOL( bsp_ram_end); -LINKER_SYMBOL( bsp_ram_size); - -LINKER_SYMBOL( bsp_rom_start); -LINKER_SYMBOL( bsp_rom_end); -LINKER_SYMBOL( bsp_rom_size); - -LINKER_SYMBOL( bsp_section_text_start); -LINKER_SYMBOL( bsp_section_text_end); -LINKER_SYMBOL( bsp_section_text_size); - -LINKER_SYMBOL( bsp_section_data_start); -LINKER_SYMBOL( bsp_section_data_end); -LINKER_SYMBOL( bsp_section_data_size); - -LINKER_SYMBOL( bsp_section_bss_start); -LINKER_SYMBOL( bsp_section_bss_end); -LINKER_SYMBOL( bsp_section_bss_size); - -LINKER_SYMBOL( bsp_interrupt_stack_start); -LINKER_SYMBOL( bsp_interrupt_stack_end); -LINKER_SYMBOL( bsp_interrupt_stack_size); - -LINKER_SYMBOL( bsp_work_area_start); - -#ifndef ASM - -#include <bspopts.h> - -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/irq.h> -#include <mpc8xx.h> -#include <mpc8xx/cpm.h> -#include <mpc8xx/mmu.h> -#include <mpc8xx/console.h> -#include <bsp/vectors.h> -#include <bsp/tqm.h> -#include <libcpu/powerpc-utility.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; - -#if BSP_USE_NETWORK_FEC -extern int rtems_fec_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attaching); -#define RTEMS_BSP_FEC_NETWORK_DRIVER_NAME "fec1" -#define RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH rtems_fec_enet_driver_attach -#endif - -#if BSP_USE_NETWORK_SCC -extern int rtems_scc_enet_driver_attach (struct rtems_bsdnet_ifconfig *config, - int attaching); -#define RTEMS_BSP_SCC_NETWORK_DRIVER_NAME "scc1" -#define RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH rtems_scc_enet_driver_attach -#endif - -#if BSP_USE_NETWORK_FEC -#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_FEC_NETWORK_DRIVER_NAME -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_FEC_NETWORK_DRIVER_ATTACH -#elif BSP_USE_NETWORK_SCC -#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_SCC_NETWORK_DRIVER_NAME -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_SCC_NETWORK_DRIVER_ATTACH -#endif -/* - * We need to decide how much memory will be non-cacheable. This - * will mainly be memory that will be used in DMA (network and serial - * buffers). - */ -#define NOCACHE_MEM_SIZE 512*1024 - -/* - * indicate, that BSP has IDE driver - */ -#undef RTEMS_BSP_HAS_IDE_DRIVER - -/* - * SPI driver configuration - */ - - /* select values for SPI addressing */ -#define PGHPLUS_SPI_ADDR_EEPROM 0 -#define PGHPLUS_SPI_ADDR_DISP4 1 - /* NOTE: DISP4 occupies two consecutive addresses for data and control port */ -#define PGHPLUS_SPI_ADDR_DISP4_DATA (PGHPLUS_SPI_ADDR_DISP4) -#define PGHPLUS_SPI_ADDR_DISP4_CTRL (PGHPLUS_SPI_ADDR_DISP4_DATA+1) - - /* bit masks for Port B lines */ -#define PGHPLUS_PB_SPI_EEP_CE_MSK (1<< 0) -#define PGHPLUS_PB_SPI_DISP4_RS_MSK (1<<15) -#define PGHPLUS_PB_SPI_DISP4_CE_MSK (1<<14) - -/* - * our (internal) bus frequency - */ -extern uint32_t BSP_bus_frequency; - -/* - * Interfaces to required Clock Driver support methods - */ -int BSP_disconnect_clock_handler(void); -int BSP_connect_clock_handler (rtems_irq_hdl); - -extern uint32_t bsp_clock_speed; - -char serial_getc(void); - -int serial_tstc(void); - -void serial_init(void); - -int mbx8xx_console_get_configuration(void); - -void _InitTQM8xx (void); - -rtems_status_code bsp_register_spi(void); - -void *bsp_idle_thread( uintptr_t ignored ); - -void cpu_init(void); - -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/include/coverhd.h b/c/src/lib/libbsp/powerpc/tqm8xx/include/coverhd.h deleted file mode 100644 index 9bd1c357c8..0000000000 --- a/c/src/lib/libbsp/powerpc/tqm8xx/include/coverhd.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file - * @ingroup powerpc_tqm8xx - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * 133 MHz processor, cache enabled. - */ -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 1 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 1 -#define CALLING_OVERHEAD_CLOCK_SET 1 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 1 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 1 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 0 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/include/irq.h b/c/src/lib/libbsp/powerpc/tqm8xx/include/irq.h deleted file mode 100644 index 2d66829037..0000000000 --- a/c/src/lib/libbsp/powerpc/tqm8xx/include/irq.h +++ /dev/null @@ -1,160 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS TQM8xx BSP | -+-----------------------------------------------------------------+ -| This file has been adapted to MPC8xx by | -| Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | -| Copyright (c) 2008 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -| | -| See the other copyright notice below for the original parts. | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the console driver | -\*===============================================================*/ -/* derived from: generic MPC83xx BSP */ -#ifndef TQM8xx_IRQ_IRQ_H -#define TQM8xx_IRQ_IRQ_H - -#include <stdbool.h> - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -/* - * the following definitions specify the indices used - * to interface the interrupt handler API - */ - -/* - * Peripheral IRQ handlers related definitions - */ -#define BSP_SIU_PER_IRQ_NUMBER 16 -#define BSP_SIU_IRQ_LOWEST_OFFSET 0 -#define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET\ - +BSP_SIU_PER_IRQ_NUMBER-1) - -#define BSP_IS_SIU_IRQ(irqnum) \ - (((irqnum) >= BSP_SIU_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_SIU_IRQ_MAX_OFFSET)) - -#define BSP_CPM_PER_IRQ_NUMBER 32 -#define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_MAX_OFFSET+1) -#define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET\ - +BSP_CPM_PER_IRQ_NUMBER-1) - -#define BSP_IS_CPM_IRQ(irqnum) \ - (((irqnum) >= BSP_CPM_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_CPM_IRQ_MAX_OFFSET)) -/* - * Processor IRQ handlers related definitions - */ -#define BSP_PROCESSOR_IRQ_NUMBER 1 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET+1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ - +BSP_PROCESSOR_IRQ_NUMBER-1) - -#define BSP_IS_PROCESSOR_IRQ(irqnum) \ - (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) -#define BSP_LOWEST_OFFSET BSP_SIU_IRQ_LOWEST_OFFSET -#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET - -#define BSP_IS_VALID_IRQ(irqnum) \ - (BSP_IS_PROCESSOR_IRQ(irqnum) \ - || BSP_IS_SIU_IRQ(irqnum) \ - || BSP_IS_CPM_IRQ(irqnum)) - -#ifndef ASM -#ifdef __cplusplus -extern "C" { -#endif - -/* - * index table for the module specific handlers, a few entries are only placeholders - */ - typedef enum { - BSP_SIU_EXT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 0, - BSP_SIU_INT_IRQ_0 = BSP_SIU_IRQ_LOWEST_OFFSET + 1, - BSP_SIU_EXT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 2, - BSP_SIU_INT_IRQ_1 = BSP_SIU_IRQ_LOWEST_OFFSET + 3, - BSP_SIU_EXT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 4, - BSP_SIU_INT_IRQ_2 = BSP_SIU_IRQ_LOWEST_OFFSET + 5, - BSP_SIU_EXT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 6, - BSP_SIU_INT_IRQ_3 = BSP_SIU_IRQ_LOWEST_OFFSET + 7, - BSP_SIU_EXT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 8, - BSP_SIU_INT_IRQ_4 = BSP_SIU_IRQ_LOWEST_OFFSET + 9, - BSP_SIU_EXT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 10, - BSP_SIU_INT_IRQ_5 = BSP_SIU_IRQ_LOWEST_OFFSET + 11, - BSP_SIU_EXT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 12, - BSP_SIU_INT_IRQ_6 = BSP_SIU_IRQ_LOWEST_OFFSET + 13, - BSP_SIU_EXT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 14, - BSP_SIU_INT_IRQ_7 = BSP_SIU_IRQ_LOWEST_OFFSET + 15, - BSP_SIU_IRQ_LAST = BSP_SIU_IRQ_MAX_OFFSET, - /* - * Some CPM IRQ symbolic name definition - */ - BSP_CPM_IRQ_ERROR = (BSP_CPM_IRQ_LOWEST_OFFSET), - BSP_CPM_IRQ_PARALLEL_IO_PC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 1), - BSP_CPM_IRQ_PARALLEL_IO_PC5 = (BSP_CPM_IRQ_LOWEST_OFFSET + 2), - BSP_CPM_IRQ_SMC2_OR_PIP = (BSP_CPM_IRQ_LOWEST_OFFSET + 3), - BSP_CPM_IRQ_SMC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 4), - BSP_CPM_IRQ_SPI = (BSP_CPM_IRQ_LOWEST_OFFSET + 5), - BSP_CPM_IRQ_PARALLEL_IO_PC6 = (BSP_CPM_IRQ_LOWEST_OFFSET + 6), - BSP_CPM_IRQ_TIMER_4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 7), - BSP_CPM_IRQ_PARALLEL_IO_PC7 = (BSP_CPM_IRQ_LOWEST_OFFSET + 9), - BSP_CPM_IRQ_PARALLEL_IO_PC8 = (BSP_CPM_IRQ_LOWEST_OFFSET + 10), - BSP_CPM_IRQ_PARALLEL_IO_PC9 = (BSP_CPM_IRQ_LOWEST_OFFSET + 11), - BSP_CPM_IRQ_TIMER_3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 12), - BSP_CPM_IRQ_PARALLEL_IO_PC10= (BSP_CPM_IRQ_LOWEST_OFFSET + 14), - BSP_CPM_IRQ_PARALLEL_IO_PC11= (BSP_CPM_IRQ_LOWEST_OFFSET + 15), - BSP_CPM_I2C = (BSP_CPM_IRQ_LOWEST_OFFSET + 16), - BSP_CPM_RISC_TIMER_TABLE = (BSP_CPM_IRQ_LOWEST_OFFSET + 17), - BSP_CPM_IRQ_TIMER_2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 18), - BSP_CPM_IDMA2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 20), - BSP_CPM_IDMA1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 21), - BSP_CPM_SDMA_CHANNEL_BUS_ERR= (BSP_CPM_IRQ_LOWEST_OFFSET + 22), - BSP_CPM_IRQ_PARALLEL_IO_PC12= (BSP_CPM_IRQ_LOWEST_OFFSET + 23), - BSP_CPM_IRQ_PARALLEL_IO_PC13= (BSP_CPM_IRQ_LOWEST_OFFSET + 24), - BSP_CPM_IRQ_TIMER_1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 25), - BSP_CPM_IRQ_PARALLEL_IO_PC14= (BSP_CPM_IRQ_LOWEST_OFFSET + 26), - BSP_CPM_IRQ_SCC4 = (BSP_CPM_IRQ_LOWEST_OFFSET + 27), - BSP_CPM_IRQ_SCC3 = (BSP_CPM_IRQ_LOWEST_OFFSET + 28), - BSP_CPM_IRQ_SCC2 = (BSP_CPM_IRQ_LOWEST_OFFSET + 29), - BSP_CPM_IRQ_SCC1 = (BSP_CPM_IRQ_LOWEST_OFFSET + 30), - BSP_CPM_IRQ_PARALLEL_IO_PC15= (BSP_CPM_IRQ_LOWEST_OFFSET + 31), - BSP_CPM_IRQ_LAST = BSP_CPM_IRQ_MAX_OFFSET, - } rtems_irq_symbolic_name; - - /* - * Symbolic name for CPM interrupt on SIU Internal level 2 - */ -#define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2 -#define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6 -#define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3 - -#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET - -#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET - -extern int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine); - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ - -#endif /* TQM8XX_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/spi/spi.h b/c/src/lib/libbsp/powerpc/tqm8xx/spi/spi.h deleted file mode 100644 index e2af971c8d..0000000000 --- a/c/src/lib/libbsp/powerpc/tqm8xx/spi/spi.h +++ /dev/null @@ -1,146 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS support for MPC8xx | -+-----------------------------------------------------------------+ -| Copyright (c) 2009 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file contains the MPC8xx SPI driver declarations | -\*===============================================================*/ -#ifndef _M8XX_SPIDRV_H -#define _M8XX_SPIDRV_H - -#include <mpc8xx.h> -#include <rtems/libi2c.h> -#include <rtems/irq.h> - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct m8xx_spi_softc { - int initialized; - rtems_id irq_sema_id; - rtems_isr_entry old_handler; - m8xxBufferDescriptor_t *rx_bd; - m8xxBufferDescriptor_t *tx_bd; -} m8xx_spi_softc_t ; - -typedef struct { - rtems_libi2c_bus_t bus_desc; - m8xx_spi_softc_t softc; -} m8xx_spi_desc_t; - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code m8xx_spi_init -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| initialize the driver | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh /* bus specifier structure */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| o = ok or error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int m8xx_spi_read_bytes -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| receive some bytes from SPI device | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - unsigned char *buf, /* buffer to store bytes */ - int len /* number of bytes to receive */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| number of bytes received or (negative) error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int m8xx_spi_write_bytes -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| send some bytes to SPI device | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - unsigned char *buf, /* buffer to send */ - int len /* number of bytes to send */ - - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| number of bytes sent or (negative) error code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -rtems_status_code m8xx_spi_set_tfr_mode -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| set SPI to desired baudrate/clock mode/character mode | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - const rtems_libi2c_tfr_mode_t *tfr_mode /* transfer mode info */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| rtems_status_code | -\*=========================================================================*/ - -/*=========================================================================*\ -| Function: | -\*-------------------------------------------------------------------------*/ -int m8xx_spi_ioctl -( -/*-------------------------------------------------------------------------*\ -| Purpose: | -| perform selected ioctl function for SPI | -+---------------------------------------------------------------------------+ -| Input Parameters: | -\*-------------------------------------------------------------------------*/ - rtems_libi2c_bus_t *bh, /* bus specifier structure */ - int cmd, /* ioctl command code */ - void *arg /* additional argument array */ - ); -/*-------------------------------------------------------------------------*\ -| Return Value: | -| rtems_status_code | -\*=========================================================================*/ - -#ifdef __cplusplus -} -#endif - - -#endif /* _M8XX_SPIDRV_H */ diff --git a/c/src/lib/libbsp/powerpc/virtex/include/bsp.h b/c/src/lib/libbsp/powerpc/virtex/include/bsp.h deleted file mode 100644 index ac919500cd..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex/include/bsp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* bsp.h - * - * This include file contains all GEN405 board IO definitions. - * - * derived from helas403/include/bsp.h: - * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp - * Author: Thomas Doerfler <td@imd.m.isar.de> - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef LIBBSP_POWERPC_VIRTEX_BSP_H -#define LIBBSP_POWERPC_VIRTEX_BSP_H - -#include <bspopts.h> - -#ifdef ASM -/* Definition of where to store registers in alignment handler */ -#define ALIGN_REGS 0x0140 - -#else -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/iosupp.h> -#include <bsp/irq.h> -#include <bsp/vectors.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN - -/* miscellaneous stuff assumed to exist */ -extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ - -/* Network Defines */ -#if 1 /* EB/doe changes */ -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" -#else -#include "xiltemac.h" -#define RTEMS_BSP_NETWORK_DRIVER_NAME XILTEMAC_DRIVER_PREFIX -#endif -extern xilTemac_driver_attach(struct rtems_bsdnet_ifconfig*, int ); -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH xilTemac_driver_attach - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex/include/coverhd.h b/c/src/lib/libbsp/powerpc/virtex/include/coverhd.h deleted file mode 100644 index 498e603092..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex/include/coverhd.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * @ingroup powerpc_virtex - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk> - * - * Units are 100ns. - * - * These numbers are of questionable use, as they are developed by calling - * the routine many times, thus getting its entry veneer into the (small) - * cache on the 403GA. This in general is not true of the RTEMS timing - * tests, which usually call a routine only once, thus having no cache loaded - * advantage. - * - * Whether the directive times are useful after deducting the function call - * overhead is also questionable. The user is more interested generally - * in the total cost of a directive, not the cost if the procedure call - * is inlined! (In general this is not true). - * - * Andrew Bray 18/08/1995 - * - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 1 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 1 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 1 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 -#define CALLING_OVERHEAD_TASK_MODE 1 -#define CALLING_OVERHEAD_TASK_GET_NOTE 1 -#define CALLING_OVERHEAD_TASK_SET_NOTE 1 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 -#define CALLING_OVERHEAD_CLOCK_GET 4 -#define CALLING_OVERHEAD_CLOCK_SET 3 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 1 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 1 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 - -#define CALLING_OVERHEAD_EVENT_SEND 1 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 1 -#define CALLING_OVERHEAD_SIGNAL_SEND 1 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 1 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 1 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 1 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 2 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex/irq/irq.h b/c/src/lib/libbsp/powerpc/virtex/irq/irq.h deleted file mode 100644 index 1ce5b68b98..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex/irq/irq.h +++ /dev/null @@ -1,94 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS virtex BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file declares constants of the interrupt controller | -\*===============================================================*/ -#ifndef VIRTEX_IRQ_IRQ_H -#define VIRTEX_IRQ_IRQ_H - -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <bsp/opbintctrl.h> - -/* - * the following definitions specify the indices used - * to interface the interrupt handler API - */ - -/* - * Peripheral IRQ handlers related definitions - */ -#define BSP_OPBINTC_PER_IRQ_NUMBER XPAR_INTC_MAX_NUM_INTR_INPUTS -#define BSP_OPBINTC_IRQ_LOWEST_OFFSET 0 -#define BSP_OPBINTC_IRQ_MAX_OFFSET (BSP_OPBINTC_IRQ_LOWEST_OFFSET\ - +BSP_OPBINTC_PER_IRQ_NUMBER-1) - -#define BSP_IS_OPBINTC_IRQ(irqnum) \ - (((irqnum) >= BSP_OPBINTC_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_OPBINTC_IRQ_MAX_OFFSET)) -/* - * Processor IRQ handlers related definitions - */ -#define BSP_PROCESSOR_IRQ_NUMBER 3 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_OPBINTC_IRQ_MAX_OFFSET+1) -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ - +BSP_PROCESSOR_IRQ_NUMBER-1) - -#define BSP_IS_PROCESSOR_IRQ(irqnum) \ - (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) -#define BSP_LOWEST_OFFSET BSP_OPBINTC_IRQ_LOWEST_OFFSET -#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET - -#define BSP_IS_VALID_IRQ(irqnum) \ - (BSP_IS_PROCESSOR_IRQ(irqnum) \ - || BSP_IS_OPBINTC_IRQ(irqnum)) - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_PROCESSOR_IRQ_MAX_OFFSET - -#ifndef ASM -#ifdef __cplusplus -extern "C" { -#endif - -/* - * index table for the module specific handlers, a few entries are only placeholders - */ - typedef enum { - BSP_OPBINTC_IRQ_FIRST = BSP_OPBINTC_IRQ_LOWEST_OFFSET, - /* - * Note: for this BSP, the peripheral names are derived - * from the Xilinx parameter file - */ - BSP_OPBINTC_IRQ_LAST = BSP_OPBINTC_IRQ_MAX_OFFSET, - BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, - BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, - BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 - } rtems_irq_symbolic_name; - -#define BSP_OPBINTC_XPAR(xname) (BSP_OPBINTC_IRQ_LOWEST_OFFSET+xname) - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ - -#endif /* VIRTEX_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/virtex4/include/bsp.h b/c/src/lib/libbsp/powerpc/virtex4/include/bsp.h deleted file mode 100644 index 67215a029c..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex4/include/bsp.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This include file contains all Virtex4 board IO definitions. - */ - -/* - * derived from helas403/include/bsp.h: - * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp - * Author: Thomas Doerfler <td@imd.m.isar.de> - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef LIBBSP_POWERPC_VIRTEX4_BSP_H -#define LIBBSP_POWERPC_VIRTEX4_BSP_H - -#include <bspopts.h> - -/* - * confdefs.h overrides for this BSP: - * - Interrupt stack space is not minimum if defined. - */ -#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) - -#ifdef ASM -/* Definition of where to store registers in alignment handler */ -#define ALIGN_REGS 0x0140 - -#else -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> - -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* miscellaneous stuff assumed to exist */ -extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ - -extern rtems_configuration_table BSP_Configuration; /* owned by BSP */ -#endif /* ASM */ - -void BSP_ask_for_reset(void); -void BSP_panic(char *s); -void _BSP_Fatal_error(unsigned int v); - -/* - * Prototypes for BSP methods shared across file boundaries - */ -void zero_bss(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex4/include/coverhd.h b/c/src/lib/libbsp/powerpc/virtex4/include/coverhd.h deleted file mode 100644 index ce5a92c120..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex4/include/coverhd.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * @ingroup powerpc_virtex4 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk> - * - * Units are 100ns. - * - * These numbers are of questionable use, as they are developed by calling - * the routine many times, thus getting its entry veneer into the (small) - * cache on the 403GA. This in general is not true of the RTEMS timing - * tests, which usually call a routine only once, thus having no cache loaded - * advantage. - * - * Whether the directive times are useful after deducting the function call - * overhead is also questionable. The user is more interested generally - * in the total cost of a directive, not the cost if the procedure call - * is inlined! (In general this is not true). - * - * Andrew Bray 18/08/1995 - * - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 1 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 1 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 1 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 -#define CALLING_OVERHEAD_TASK_MODE 1 -#define CALLING_OVERHEAD_TASK_GET_NOTE 1 -#define CALLING_OVERHEAD_TASK_SET_NOTE 1 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 -#define CALLING_OVERHEAD_CLOCK_GET 4 -#define CALLING_OVERHEAD_CLOCK_SET 3 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 1 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 1 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 - -#define CALLING_OVERHEAD_EVENT_SEND 1 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 1 -#define CALLING_OVERHEAD_SIGNAL_SEND 1 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 1 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 1 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 1 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 2 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex4/include/irq.h b/c/src/lib/libbsp/powerpc/virtex4/include/irq.h deleted file mode 100644 index 45ef69adbf..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex4/include/irq.h +++ /dev/null @@ -1,79 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS virtex BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file declares constants of the interrupt controller | -\*===============================================================*/ -#ifndef VIRTEX4_IRQ_IRQ_H -#define VIRTEX4_IRQ_IRQ_H - -#include <rtems/irq.h> - -/* - * the following definitions specify the indices used - * to interface the interrupt handler API - */ - -/* - * Peripheral IRQ handlers related definitions - */ - /* Not supported at this level */ - -/* - * Processor IRQ handlers related definitions - */ -#define BSP_PROCESSOR_IRQ_NUMBER 3 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET 0 -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ - +BSP_PROCESSOR_IRQ_NUMBER-1) - -#define BSP_IS_PROCESSOR_IRQ(irqnum) \ - (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) - -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) -#define BSP_LOWEST_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET -#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET - -#define BSP_IS_VALID_IRQ(irqnum) (BSP_IS_PROCESSOR_IRQ(irqnum)) - -#ifndef ASM -#ifdef __cplusplus -extern "C" { -#endif - -/* - * index table for the module specific handlers, a few entries are only placeholders - */ - typedef enum { - BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, - BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, - BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 - } rtems_irq_symbolic_name; - - extern rtems_irq_connect_data *BSP_rtems_irq_tbl; - void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data); - void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused); - void BSP_rtems_irq_mngt_init(unsigned cpuId); - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ - -#endif /* VIRTEX4_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/virtex4/include/mmu.h b/c/src/lib/libbsp/powerpc/virtex4/include/mmu.h deleted file mode 100644 index 3e2710b95c..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex4/include/mmu.h +++ /dev/null @@ -1,269 +0,0 @@ -#ifndef RTEMS_VIRTEX4_MMU_H -#define RTEMS_VIRTEX4_MMU_H -/** - * @file - * - * @ingroup Virtex4MMU - * - * @brief Routines to manipulate the PPC 405 MMU. - */ -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, - * Stanford Linear Accelerator Center, Stanford University. - * and was transcribed for the PPC 405 by - * R. Claus <claus@slac.stanford.edu>, 2012, - * Stanford Linear Accelerator Center, Stanford University, - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -#include <rtems.h> -#include <inttypes.h> -#include <stdio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup Virtex4MMU Virtex 4 - MMU Support - * - * @ingroup Virtex4 - * - * @brief MMU support. - * - * @{ - */ - -/* Some routines require or return a index 'key'. - */ -typedef int bsp_tlb_idx_t; - -/* Cache the relevant TLB entries so that we can make sure the user cannot - * create conflicting (overlapping) entries. Keep them public for informational - * purposes. - */ -typedef struct { - struct { - uint32_t pad:24; - uint32_t tid:8; /** Translation ID */ - } id; - struct { - uint32_t epn:22; /** Effective page number */ - uint32_t size:3; /** Page size */ - uint32_t v:1; /** Valid */ - uint32_t att:2; /** Little-endian, User-defined */ - uint32_t pad:4; - } hi; /** High word*/ - struct { - uint32_t rpn:22; /** Real page number */ - uint32_t perm:6; /** Execute enable, Write-enable, Zone select */ - uint32_t wimg:4; /** Write-through, Caching inhibited, Mem coherent, Guarded */ - } lo; /** Low word */ -} bsp_tlb_entry_t; - -#define NTLBS 64 - -extern bsp_tlb_entry_t* bsp_mmu_cache; - - -// These constants will have to be shifted right by 20 bits before -// being inserted the high word of the TLB. - -#define MMU_M_SIZE_1K (0x00000000U) -#define MMU_M_SIZE_4K (0x08000000U) -#define MMU_M_SIZE_16K (0x10000000U) -#define MMU_M_SIZE_64K (0x18000000U) -#define MMU_M_SIZE_256K (0x20000000U) -#define MMU_M_SIZE_1M (0x28000000U) -#define MMU_M_SIZE_4M (0x30000000U) -#define MMU_M_SIZE_16M (0x38000000U) -#define MMU_M_SIZE_MIN (MMU_M_SIZE_1K) -#define MMU_M_SIZE_MAX (MMU_M_SIZE_16M) -#define MMU_M_SIZE (0x38000000U) -#define MMU_V_SIZE (27) - -#define MMU_M_ATTR_LITTLE_ENDIAN (0x02000000U) -#define MMU_M_ATTR_USER0 (0x01000000U) -#define MMU_M_ATTR (0x03000000U) -#define MMU_V_ATTR (24) - -// These constants have the same bit positions they'll occupy -// in low word of the TLB. - -#define MMU_M_PERM_EXEC (0x00000200U) -#define MMU_M_PERM_DATA_WRITE (0x00000100U) -#define MMU_M_PERM_ZONE_SELECT (0x000000f0U) -#define MMU_M_PERM (0x000003f0U) -#define MMU_V_PERM (4) - -#define MMU_M_PROP_WRITE_THROUGH (0x00000008U) -#define MMU_M_PROP_UNCACHED (0x00000004U) -#define MMU_M_PROP_MEM_COHERENT (0x00000002U) -#define MMU_M_PROP_GUARDED (0x00000001U) -#define MMU_M_PROP (0x0000000fU) -#define MMU_V_PROP (0) - - -/* - * Dump (cleartext) content info from cached TLB entries - * to a file (stdout if f==NULL). - */ -void -bsp_mmu_dump_cache(FILE *f); - -/* Read a TLB entry from the hardware and store the settings in the - * bsp_mmu_cache[] structure. - * - * The routine can perform this operation quietly or - * print information to a file. - * - * 'key': TLB entry index. - * 'quiet': perform operation silently (no info printed) if nonzero. - * 'f': open FILE where to print information. May be NULL, in - * which case 'stdout' is used. - * - * RETURNS: - * 0: success; TLB entry is VALID - * +1: success but TLB entry is INVALID - * < 0: error (-1: invalid argument) - * (-2: driver not initialized) - */ -int -bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f); - -/* Initialize cache. Should be done only once although this is not enforced. - * - * RETURNS: zero on success, nonzero on error; in this case the driver will - * refuse to change TLB entries (other than disabling them). - */ -int -bsp_mmu_initialize(void); - -/* Find first free TLB entry by examining all entries' valid bit. The first - * entry without the valid bit set is returned. - * - * RETURNS: A free TLB entry number. -1 if no entry can be found. - */ -bsp_tlb_idx_t -bsp_mmu_find_first_free(void); - -/* Write a TLB entry (can also be used to disable an entry). - * - * The routine checks against the cached data in bsp_mmu_cache[] - * to prevent the user from generating overlapping entries. - * - * 'idx': TLB entry # to manipulate - * 'ea': Effective address (must be page aligned) - * 'pa': Physical address (must be page aligned) - * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes. - * 'sz' may also be one of the following: - * - page size in bytes ( >= 1024 ); the selector - * value is then computed by this routine. - * However, 'sz' must be a valid page size - * or -1 will be returned. - * - a value < 0 to invalidate/disable the - * TLB entry. - * 'flgs': Page's little-endian & user-defined flags, permissions and attributes - * 'tid': Translation ID - * - * RETURNS: 0 on success, nonzero on error: - * - * >0: requested mapping would overlap with - * existing mapping in another entry. Return - * value gives conflicting entry + 1; i.e., - * if a value of 4 is returned then the request - * conflicts with existing mapping in entry 3. - * -1: invalid argument - * -3: driver not initialized (or initialization failed). - * <0: other error - */ -bsp_tlb_idx_t -bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, uint sz, - uint32_t flgs, uint32_t tid); - -/* Check if a ea/tid/sz mapping overlaps with an existing entry. - * - * 'ea': The Effective Address to match against - * 'sz': The 'logarithmic' size selector; the page size - * is 1024*2^(2*sz). - * 'tid': The TID to match against - * - * RETURNS: - * >= 0: index of TLB entry that already provides a mapping - * which overlaps within the ea range. - * -1: SUCCESS (no conflicting entry found) - * <=-2: ERROR (invalid input) - */ -bsp_tlb_idx_t -bsp_mmu_match(uint32_t ea, int sz, uint32_t tid); - -/* Find TLB index that maps 'ea/tid' combination - * - * 'ea': Effective address to match against - * 'tid': The TID to match against - * - * RETURNS: index 'key'; i.e., the index number. - * - * On error (no mapping) -1 is returned. - */ -bsp_tlb_idx_t -bsp_mmu_find(uint32_t ea, uint32_t tid); - -/* Mark TLB entry as invalid ('disabled'). - * - * 'key': TLB entry index. - * - * RETURNS: zero on success, nonzero on error (TLB unchanged). - * - * NOTE: If a TLB entry is disabled the associated - * entry in bsp_mmu_cache[] is also marked as disabled. - */ -int -bsp_mmu_invalidate(bsp_tlb_idx_t key); - -/** @} */ - -#ifdef __cplusplus -}; -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h b/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h deleted file mode 100644 index fc03cf1546..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex5/include/bsp.h +++ /dev/null @@ -1,112 +0,0 @@ -/* @file - * - * This include file contains all GEN405 board IO definitions. - */ - -/* - * derived from helas403/include/bsp.h: - * Id: bsp.h,v 1.4 2001/06/18 17:01:48 joel Exp - * Author: Thomas Doerfler <td@imd.m.isar.de> - * IMD Ingenieurbuero fuer Microcomputertechnik - * - * COPYRIGHT (c) 1998 by IMD - * - * Changes from IMD are covered by the original distributions terms. - * This file has been derived from the papyrus BSP. - * - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/lib/libbsp/no_cpu/no_bsp/include/bsp.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef LIBBSP_POWERPC_VIRTEX5_BSP_H -#define LIBBSP_POWERPC_VIRTEX5_BSP_H - -#include <bspopts.h> - -/* - * confdefs.h overrides for this BSP: - * - Interrupt stack space is not minimum if defined. - */ -#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) - -#ifdef ASM -/* Definition of where to store registers in alignment handler */ -#define ALIGN_REGS 0x0140 - -#else -#include <rtems.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> -#include <rtems/iosupp.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* miscellaneous stuff assumed to exist */ -extern bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ - -/* - * Bus Frequency - */ -extern unsigned int BSP_bus_frequency; -/* - * Processor Clock Frequency - */ -extern unsigned int BSP_processor_frequency; -/* - * Time base divisior (how many tick for 1 second). - */ -extern unsigned int BSP_time_base_divisor; - -/* - * Macro used by shared MPC6xx timer driver - */ -#define BSP_Convert_decrementer( _value ) \ - ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) - -/* - * Interfaces to required Clock Driver support methods - */ -int BSP_disconnect_clock_handler(void); -int BSP_connect_clock_handler(void); - -/* - * Prototypes for BSP methods shared across file boundaries - */ -void zero_bss(void); - -#endif /* ASM */ - -void BSP_ask_for_reset(void); -void BSP_panic(char *s); -void _BSP_Fatal_error(unsigned int v); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex5/include/coverhd.h b/c/src/lib/libbsp/powerpc/virtex5/include/coverhd.h deleted file mode 100644 index f6a00b1e81..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex5/include/coverhd.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * @ingroup powerpc_virtex5 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include - * all calling overhead including passing of arguments. - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* - * Updated for a 25MHz Papyrus by Andrew Bray <andy@i-cubed.co.uk> - * - * Units are 100ns. - * - * These numbers are of questionable use, as they are developed by calling - * the routine many times, thus getting its entry veneer into the (small) - * cache on the 403GA. This in general is not true of the RTEMS timing - * tests, which usually call a routine only once, thus having no cache loaded - * advantage. - * - * Whether the directive times are useful after deducting the function call - * overhead is also questionable. The user is more interested generally - * in the total cost of a directive, not the cost if the procedure call - * is inlined! (In general this is not true). - * - * Andrew Bray 18/08/1995 - * - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 3 -#define CALLING_OVERHEAD_TASK_IDENT 1 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 1 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 1 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 -#define CALLING_OVERHEAD_TASK_MODE 1 -#define CALLING_OVERHEAD_TASK_GET_NOTE 1 -#define CALLING_OVERHEAD_TASK_SET_NOTE 1 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 4 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 -#define CALLING_OVERHEAD_CLOCK_GET 4 -#define CALLING_OVERHEAD_CLOCK_SET 3 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 1 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 1 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 2 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 5 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 2 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 2 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 - -#define CALLING_OVERHEAD_EVENT_SEND 1 -#define CALLING_OVERHEAD_EVENT_RECEIVE 2 -#define CALLING_OVERHEAD_SIGNAL_CATCH 1 -#define CALLING_OVERHEAD_SIGNAL_SEND 1 -#define CALLING_OVERHEAD_PARTITION_CREATE 3 -#define CALLING_OVERHEAD_PARTITION_IDENT 1 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 -#define CALLING_OVERHEAD_REGION_CREATE 3 -#define CALLING_OVERHEAD_REGION_IDENT 1 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 1 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 2 - -#define CALLING_OVERHEAD_IO_INITIALIZE 2 -#define CALLING_OVERHEAD_IO_OPEN 2 -#define CALLING_OVERHEAD_IO_CLOSE 2 -#define CALLING_OVERHEAD_IO_READ 2 -#define CALLING_OVERHEAD_IO_WRITE 2 -#define CALLING_OVERHEAD_IO_CONTROL 2 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/powerpc/virtex5/include/irq.h b/c/src/lib/libbsp/powerpc/virtex5/include/irq.h deleted file mode 100644 index 066090de7f..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex5/include/irq.h +++ /dev/null @@ -1,82 +0,0 @@ -/*===============================================================*\ -| Project: RTEMS virtex BSP | -+-----------------------------------------------------------------+ -| Copyright (c) 2007 | -| Embedded Brains GmbH | -| Obere Lagerstr. 30 | -| D-82178 Puchheim | -| Germany | -| rtems@embedded-brains.de | -+-----------------------------------------------------------------+ -| The license and distribution terms for this file may be | -| found in the file LICENSE in this distribution or at | -| | -| http://www.rtems.org/license/LICENSE. | -| | -+-----------------------------------------------------------------+ -| this file declares constants of the interrupt controller | -\*===============================================================*/ -#ifndef VIRTEX5_IRQ_IRQ_H -#define VIRTEX5_IRQ_IRQ_H - -#include <rtems/irq.h> - -/* - * the following definitions specify the indices used - * to interface the interrupt handler API - */ - -/* - * Peripheral IRQ handlers related definitions - */ - /* Not supported at this level */ - -/* - * Processor IRQ handlers related definitions - */ -#define BSP_PROCESSOR_IRQ_NUMBER 3 -#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET 0 -#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET\ - +BSP_PROCESSOR_IRQ_NUMBER-1) - -#define BSP_IS_PROCESSOR_IRQ(irqnum) \ - (((irqnum) >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) && \ - ((irqnum) <= BSP_PROCESSOR_IRQ_MAX_OFFSET)) - -/* - * Summary - */ -#define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET+1) -#define BSP_LOWEST_OFFSET BSP_PROCESSOR_IRQ_LOWEST_OFFSET -#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET - -#define BSP_IS_VALID_IRQ(irqnum) (BSP_IS_PROCESSOR_IRQ(irqnum)) - -#ifndef ASM -#ifdef __cplusplus -extern "C" { -#endif - -/* - * index table for the module specific handlers, a few entries are only placeholders - */ - typedef enum { - BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0, - BSP_PIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1, - BSP_CRIT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2 - } rtems_irq_symbolic_name; - - extern rtems_irq_connect_data *BSP_rtems_irq_tbl; - void BSP_irqexc_on_fnc(const rtems_irq_connect_data *conn_data); - void BSP_irqexc_off_fnc(const rtems_irq_connect_data *unused); - void BSP_rtems_irq_mngt_init(unsigned cpuId); - -#define BSP_DEC BSP_PIT -#define BSP_DECREMENTER BSP_PIT - -#ifdef __cplusplus -} -#endif -#endif /* ASM */ - -#endif /* VIRTEX5_IRQ_IRQ_H */ diff --git a/c/src/lib/libbsp/powerpc/virtex5/include/mmu.h b/c/src/lib/libbsp/powerpc/virtex5/include/mmu.h deleted file mode 100644 index a3fb32b662..0000000000 --- a/c/src/lib/libbsp/powerpc/virtex5/include/mmu.h +++ /dev/null @@ -1,287 +0,0 @@ -#ifndef RTEMS_VIRTEX5_MMU_H -#define RTEMS_VIRTEX5_MMU_H -/** - * @file - * - * @ingroup Virtex5MMU - * - * @brief Routines to manipulate the PPC 440 MMU. - */ -/* - * Authorship - * ---------- - * This software was created by - * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, - * Stanford Linear Accelerator Center, Stanford University. - * and was transcribed for the PPC 440 by - * R. Claus <claus@slac.stanford.edu>, 2012, - * Stanford Linear Accelerator Center, Stanford University, - * - * Acknowledgement of sponsorship - * ------------------------------ - * This software was produced by - * the Stanford Linear Accelerator Center, Stanford University, - * under Contract DE-AC03-76SFO0515 with the Department of Energy. - * - * Government disclaimer of liability - * ---------------------------------- - * Neither the United States nor the United States Department of Energy, - * nor any of their employees, makes any warranty, express or implied, or - * assumes any legal liability or responsibility for the accuracy, - * completeness, or usefulness of any data, apparatus, product, or process - * disclosed, or represents that its use would not infringe privately owned - * rights. - * - * Stanford disclaimer of liability - * -------------------------------- - * Stanford University makes no representations or warranties, express or - * implied, nor assumes any liability for the use of this software. - * - * Stanford disclaimer of copyright - * -------------------------------- - * Stanford University, owner of the copyright, hereby disclaims its - * copyright and all other rights in this software. Hence, anyone may - * freely use it for any purpose without restriction. - * - * Maintenance of notices - * ---------------------- - * In the interest of clarity regarding the origin and status of this - * SLAC software, this and all the preceding Stanford University notices - * are to remain affixed to any copy or derivative of this software made - * or distributed by the recipient and are to be affixed to any copy of - * software made or distributed by the recipient that contains a copy or - * derivative of this software. - * - * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 - */ - -#include <rtems.h> -#include <inttypes.h> -#include <stdio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup Virtex5MMU Virtex 5 - MMU Support - * - * @ingroup Virtex5 - * - * @brief MMU support. - * - * @{ - */ - -/* Some routines require or return an index 'key'. - */ -typedef int bsp_tlb_idx_t; - -/* Cache the relevant TLB entries so that we can make sure the user cannot - * create conflicting (overlapping) entries. Keep them public for informational - * purposes. - */ -typedef struct { - struct { - uint32_t pad:24; - uint32_t tid:8; /** Translation ID */ - } id; - struct { - uint32_t epn:22; /** Effective page number */ - uint32_t v:1; /** Valid */ - uint32_t ts:1; /** Translation Address Space */ - uint32_t size:4; /** Page size */ - uint32_t tpar:4; /** Tag parity */ - } w0; - struct { - uint32_t rpn:22; /** The real (translated) page number. */ - uint32_t par1:2; /** For matching the TLB array parity */ - uint32_t pad:4; - uint32_t erpn:4; /** Extended Real Page Number */ - } w1; - struct { - uint32_t par2:2; /** Parity for TLB word 2 */ - uint32_t pad1:14; - uint32_t att:4; /** User-defined attributes */ - uint32_t wimge:5; /** Write-Through/Caching Inhibited/Memory Coherent/Guarded/Endian */ - uint32_t pad2:1; - uint32_t perm:6; /** User-State Executable/Writeable/Readable Supervisor-State Executable/Writeable/Readable */ - } w2; -} bsp_tlb_entry_t; - -#define NTLBS 64 - -extern bsp_tlb_entry_t* bsp_mmu_cache; - -// These constants will have to be shifted right by 20 bits before -// being inserted the high word of the TLB. - -#define MMU_M_SIZE_1K (0x00000000U) -#define MMU_M_SIZE_4K (0x08000000U) -#define MMU_M_SIZE_16K (0x10000000U) -#define MMU_M_SIZE_64K (0x18000000U) -#define MMU_M_SIZE_256K (0x20000000U) -#define MMU_M_SIZE_1M (0x28000000U) -#define MMU_M_SIZE_16M (0x38000000U) -#define MMU_M_SIZE_256M (0x48000000U) -#define MMU_M_SIZE_MIN (MMU_M_SIZE_1K) -#define MMU_M_SIZE_MAX (MMU_M_SIZE_256M) -#define MMU_M_SIZE (0x78000000U) -#define MMU_V_SIZE (27) - -// These constants have the same bit positions they'll occupy -// in low word of the TLB. - -#define MMU_M_ATTR_USER0 (0x00010000U) -#define MMU_M_ATTR_USER1 (0x00008000U) -#define MMU_M_ATTR_USER2 (0x00004000U) -#define MMU_M_ATTR_USER3 (0x00002000U) -#define MMU_M_ATTR (0x0001e000U) -#define MMU_V_ATTR (13) - -#define MMU_M_PROP_WRITE_THROUGH (0x00001000U) -#define MMU_M_PROP_UNCACHED (0x00000800U) -#define MMU_M_PROP_MEM_COHERENT (0x00000400U) -#define MMU_M_PROP_GUARDED (0x00000200U) -#define MMU_M_PROP_LITTLE_ENDIAN (0x00000100U) -#define MMU_M_PROP (0x00000f00U) -#define MMU_V_PROP (8) - -#define MMU_M_PERM_USER_EXEC (0x00000020U) -#define MMU_M_PERM_USER_WRITE (0x00000010U) -#define MMU_M_PERM_USER_READ (0x00000008U) -#define MMU_M_PERM_SUPER_EXEC (0x00000004U) -#define MMU_M_PERM_SUPER_WRITE (0x00000002U) -#define MMU_M_PERM_SUPER_READ (0x00000001U) -#define MMU_M_PERM (0x0000003fU) -#define MMU_V_PERM (0) - - -/* - * Dump (cleartext) content info from cached TLB entries - * to a file (stdout if f==NULL). - */ -void -bsp_mmu_dump_cache(FILE *f); - -/* Read a TLB entry from the hardware and store the settings in the - * bsp_mmu_cache[] structure. - * - * The routine can perform this operation quietly or - * print information to a file. - * - * 'key': TLB entry index. - * 'quiet': perform operation silently (no info printed) if nonzero. - * 'f': open FILE where to print information. May be NULL, in - * which case 'stdout' is used. - * - * RETURNS: - * 0: success; TLB entry is VALID - * +1: success but TLB entry is INVALID - * < 0: error (-1: invalid argument) - * (-2: driver not initialized) - */ -int -bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f); - -/* Initialize cache. Should be done only once although this is not enforced. - * - * RETURNS: zero on success, nonzero on error; in this case the driver will - * refuse to change TLB entries (other than disabling them). - */ -int -bsp_mmu_initialize(void); - -/* Find first free TLB entry by examining all entries' valid bit. The first - * entry without the valid bit set is returned. - * - * RETURNS: A free TLB entry number. -1 if no entry can be found. - */ -bsp_tlb_idx_t -bsp_mmu_find_first_free(void); - -/* Write a TLB entry (can also be used to disable an entry). - * - * The routine checks against the cached data in bsp_mmu_cache[] - * to prevent the user from generating overlapping entries. - * - * 'idx': TLB entry # to manipulate - * 'ea': Effective address (must be page aligned) - * 'pa': Physical address (must be page aligned) - * 'sz': Page size selector; page size is 1024 * 2^(2*sz) bytes. - * 'sz' may also be one of the following: - * - page size in bytes ( >= 1024 ); the selector - * value is then computed by this routine. - * However, 'sz' must be a valid page size - * or -1 will be returned. - * - a value < 0 to invalidate/disable the - * TLB entry. - * 'flgs': Page's User-defined flags, permissions and WIMGE page attributes - * 'tid': Translation ID - * 'ts': Translation Space - * 'erpn': Extended Real Page Number - * - * RETURNS: 0 on success, nonzero on error: - * - * >0: requested mapping would overlap with - * existing mapping in another entry. Return - * value gives conflicting entry + 1; i.e., - * if a value of 4 is returned then the request - * conflicts with existing mapping in entry 3. - * -1: invalid argument - * -3: driver not initialized (or initialization failed). - * <0: other error - */ -bsp_tlb_idx_t -bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, int sz, - uint32_t flgs, uint32_t tid, uint32_t ts, uint32_t erpn); - -/* Check if a ea/tid/ts/sz mapping overlaps with an existing entry. - * - * 'ea': The Effective Address to match against - * 'sz': The 'logarithmic' size selector; the page size - * is 1024*2^(2*sz). - * 'tid': Translation ID - * 'ts': Translation Space - * - * RETURNS: - * >= 0: index of TLB entry that already provides a mapping - * which overlaps within the ea range. - * -1: SUCCESS (no conflicting entry found) - * <=-2: ERROR (invalid input) - */ -bsp_tlb_idx_t -bsp_mmu_match(uint32_t ea, int sz, uint32_t tid, uint32_t ts); - -/* Find TLB index that maps 'ea/tid/ts' combination - * - * 'ea': Effective address to match against - * 'tid': Translation ID - * 'ts': Translation Space - * - * RETURNS: index 'key'; i.e., the index number. - * - * On error (no mapping) -1 is returned. - */ -bsp_tlb_idx_t -bsp_mmu_find(uint32_t ea, uint32_t tid, uint32_t ts); - -/* Mark TLB entry as invalid ('disabled'). - * - * 'key': TLB entry index. - * - * RETURNS: zero on success, nonzero on error (TLB unchanged). - * - * NOTE: If a TLB entry is disabled the associated - * entry in bsp_tlb_cache[] is also marked as disabled. - */ -int -bsp_mmu_invalidate(bsp_tlb_idx_t key); - -/** @} */ - -#ifdef __cplusplus -}; -#endif - -#endif diff --git a/c/src/lib/libbsp/sh/gensh1/include/bsp.h b/c/src/lib/libbsp/sh/gensh1/include/bsp.h deleted file mode 100644 index 297e2299a3..0000000000 --- a/c/src/lib/libbsp/sh/gensh1/include/bsp.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * generic sh1 - * - * This include file contains all board IO definitions. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_SH_GENSH1_BSP_H -#define LIBBSP_SH_GENSH1_BSP_H - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <termios.h> /* for tcflag_t */ - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* EDIT: To activate the sci driver, change the define below */ -#if 1 -#include <rtems/devnull.h> -#define BSP_CONSOLE_DEVNAME "/dev/null" -#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVNULL_DRIVER_TABLE_ENTRY -#else -#include <sh/sci.h> -#define BSP_CONSOLE_DEVNAME "/dev/sci0" -#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY -#endif - -/* Constants */ - -/* - * Defined in the linker script 'linkcmds' - */ - -extern void *CPU_Interrupt_stack_low; -extern void *CPU_Interrupt_stack_high; - -/* - * Device Driver Table Entries - */ - -/* - * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console - */ -#undef CONSOLE_DRIVER_TABLE_ENTRY -#define CONSOLE_DRIVER_TABLE_ENTRY \ - BSP_CONSOLE_DRIVER_TABLE_ENTRY, \ - { console_initialize, console_open, console_close, \ - console_read, console_write, console_control } - -/* - * BSP methods that cross file boundaries. - */ -void bsp_hw_init(void); - -extern int _sci_get_brparms( - tcflag_t cflag, - unsigned char *smr, - unsigned char *brr -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sh/gensh1/include/coverhd.h b/c/src/lib/libbsp/sh/gensh1/include/coverhd.h deleted file mode 100644 index 9bad9bf01a..0000000000 --- a/c/src/lib/libbsp/sh/gensh1/include/coverhd.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - * @file - * @ingroup sh_gensh1 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include all - * all calling overhead including passing of arguments. - * - * - * These are the figures tmoverhd.exe reported with egcs-980205 -O3 - * on a Diesner OktagonSH/Amos-2.1 board with SH7032/20MHz - * - * These results are assumed to be applicable to most SH7032/20MHz boards - * - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 -#define CALLING_OVERHEAD_TASK_CREATE 9 -#define CALLING_OVERHEAD_TASK_IDENT 6 -#define CALLING_OVERHEAD_TASK_START 5 -#define CALLING_OVERHEAD_TASK_RESTART 5 -#define CALLING_OVERHEAD_TASK_DELETE 4 -#define CALLING_OVERHEAD_TASK_SUSPEND 4 -#define CALLING_OVERHEAD_TASK_RESUME 4 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 -#define CALLING_OVERHEAD_TASK_MODE 5 -#define CALLING_OVERHEAD_TASK_GET_NOTE 5 -#define CALLING_OVERHEAD_TASK_SET_NOTE 5 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 14 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 -#define CALLING_OVERHEAD_CLOCK_GET 16 -#define CALLING_OVERHEAD_CLOCK_SET 14 -#define CALLING_OVERHEAD_CLOCK_TICK 3 - -#define CALLING_OVERHEAD_TIMER_CREATE 4 -#define CALLING_OVERHEAD_TIMER_IDENT 4 -#define CALLING_OVERHEAD_TIMER_DELETE 4 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 20 -#define CALLING_OVERHEAD_TIMER_RESET 4 -#define CALLING_OVERHEAD_TIMER_CANCEL 4 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 7 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 5 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5 - -#define CALLING_OVERHEAD_EVENT_SEND 6 -#define CALLING_OVERHEAD_EVENT_RECEIVE 5 -#define CALLING_OVERHEAD_SIGNAL_CATCH 4 -#define CALLING_OVERHEAD_SIGNAL_SEND 4 -#define CALLING_OVERHEAD_PARTITION_CREATE 9 -#define CALLING_OVERHEAD_PARTITION_IDENT 5 -#define CALLING_OVERHEAD_PARTITION_DELETE 4 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 6 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 6 -#define CALLING_OVERHEAD_REGION_CREATE 9 -#define CALLING_OVERHEAD_REGION_IDENT 5 -#define CALLING_OVERHEAD_REGION_DELETE 4 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 9 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5 -#define CALLING_OVERHEAD_PORT_CREATE 9 -#define CALLING_OVERHEAD_PORT_IDENT 4 -#define CALLING_OVERHEAD_PORT_DELETE 4 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 7 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 8 - -#define CALLING_OVERHEAD_IO_INITIALIZE 5 -#define CALLING_OVERHEAD_IO_OPEN 5 -#define CALLING_OVERHEAD_IO_CLOSE 5 -#define CALLING_OVERHEAD_IO_READ 5 -#define CALLING_OVERHEAD_IO_WRITE 5 -#define CALLING_OVERHEAD_IO_CONTROL 5 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sh/gensh2/include/bsp.h b/c/src/lib/libbsp/sh/gensh2/include/bsp.h deleted file mode 100644 index 16361240e5..0000000000 --- a/c/src/lib/libbsp/sh/gensh2/include/bsp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * generic sh2 - * - * This include file contains all board IO definitions. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Minor adaptations for sh2 by: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef LIBBSP_SH_GENSH2_BSP_H -#define LIBBSP_SH_GENSH2_BSP_H - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <termios.h> /* for tcflag_t */ - -#include <sh/sci.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#if 1 -/* FIXME: - * These definitions will be no longer necessary if the old - * implementation of SCI driver will be droped - */ -#define BSP_CONSOLE_DEVNAME "/dev/sci0" -#define BSP_CONSOLE_MINOR_NUMBER ((rtems_device_minor_number) 0) -#define BSP_CONSOLE_DRIVER_TABLE_ENTRY DEVSCI_DRIVER_TABLE_ENTRY -#define BSP_CONSOLE_DEVICE_TERMIOS_HANDLERS (sh_sci_get_termios_handlers(TRUE)) -#endif - -/* Constants */ - -/* - * Defined in the linker script 'linkcmds' - */ -extern void *CPU_Interrupt_stack_low; -extern void *CPU_Interrupt_stack_high; - -/* - * BSP methods that cross file boundaries. - */ -void bsp_hw_init(void); -extern int _sci_get_brparms( - tcflag_t cflag, - unsigned char *smr, - unsigned char *brr -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sh/gensh2/include/coverhd.h b/c/src/lib/libbsp/sh/gensh2/include/coverhd.h deleted file mode 100644 index d6eec4fe6d..0000000000 --- a/c/src/lib/libbsp/sh/gensh2/include/coverhd.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * @file - * @ingroup sh_gensh2 - * @brief C Overhead definitions - */ - -/* - * - * This include file has defines to represent the overhead associated - * with calling a particular directive from C. These are used in the - * Timing Test Suite to ignore the overhead required to pass arguments - * to directives. On some CPUs and/or target boards, this overhead - * is significant and makes it difficult to distinguish internal - * RTEMS execution time from that used to call the directive. - * This file should be updated after running the C overhead timing - * test. Once this update has been performed, the RTEMS Time Test - * Suite should be rebuilt to account for these overhead times in the - * timing results. - * - * NOTE: If these are all zero, then the times reported include all - * all calling overhead including passing of arguments. - * - * - * These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4 - * on a Hitachi SH7045F Evaluation Board with SH7045F at 29 MHz - * - * These results are assumed to be applicable to most SH7045/29MHz boards - * - * Author: John M.Mills (jmills@tga.com) - * - * COPYRIGHT (c) 1999. TGA Technologies, Inc., Norcross, GA, USA - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 1 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 1 -#define CALLING_OVERHEAD_TASK_CREATE 2 -#define CALLING_OVERHEAD_TASK_IDENT 1 -#define CALLING_OVERHEAD_TASK_START 1 -#define CALLING_OVERHEAD_TASK_RESTART 1 -#define CALLING_OVERHEAD_TASK_DELETE 1 -#define CALLING_OVERHEAD_TASK_SUSPEND 1 -#define CALLING_OVERHEAD_TASK_RESUME 1 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 1 -#define CALLING_OVERHEAD_TASK_MODE 1 -#define CALLING_OVERHEAD_TASK_GET_NOTE 1 -#define CALLING_OVERHEAD_TASK_SET_NOTE 1 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 2 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 1 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 1 -#define CALLING_OVERHEAD_CLOCK_GET 3 -#define CALLING_OVERHEAD_CLOCK_SET 2 -#define CALLING_OVERHEAD_CLOCK_TICK 1 - -#define CALLING_OVERHEAD_TIMER_CREATE 1 -#define CALLING_OVERHEAD_TIMER_IDENT 1 -#define CALLING_OVERHEAD_TIMER_DELETE 1 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 3 -#define CALLING_OVERHEAD_TIMER_RESET 1 -#define CALLING_OVERHEAD_TIMER_CANCEL 1 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 1 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 1 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 1 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 1 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 1 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 1 - -#define CALLING_OVERHEAD_EVENT_SEND 1 -#define CALLING_OVERHEAD_EVENT_RECEIVE 1 -#define CALLING_OVERHEAD_SIGNAL_CATCH 1 -#define CALLING_OVERHEAD_SIGNAL_SEND 1 -#define CALLING_OVERHEAD_PARTITION_CREATE 2 -#define CALLING_OVERHEAD_PARTITION_IDENT 1 -#define CALLING_OVERHEAD_PARTITION_DELETE 1 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 1 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 1 -#define CALLING_OVERHEAD_REGION_CREATE 2 -#define CALLING_OVERHEAD_REGION_IDENT 1 -#define CALLING_OVERHEAD_REGION_DELETE 1 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 2 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 1 -#define CALLING_OVERHEAD_PORT_CREATE 2 -#define CALLING_OVERHEAD_PORT_IDENT 1 -#define CALLING_OVERHEAD_PORT_DELETE 1 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 1 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 1 - -#define CALLING_OVERHEAD_IO_INITIALIZE 1 -#define CALLING_OVERHEAD_IO_OPEN 1 -#define CALLING_OVERHEAD_IO_CLOSE 1 -#define CALLING_OVERHEAD_IO_READ 1 -#define CALLING_OVERHEAD_IO_WRITE 1 -#define CALLING_OVERHEAD_IO_CONTROL 1 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 1 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 1 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 1 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sh/gensh4/include/bsp.h b/c/src/lib/libbsp/sh/gensh4/include/bsp.h deleted file mode 100644 index 5ef6d005a4..0000000000 --- a/c/src/lib/libbsp/sh/gensh4/include/bsp.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * generic sh4 BSP - * - * This include file contains all board IO definitions. - */ - -/* - * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia - * Author: Victor V. Vengerov <vvv@oktet.ru> - * - * Based on work: - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Minor adaptations for sh2 by: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - */ - -#ifndef LIBBSP_SH_GENSH4_BSP_H -#define LIBBSP_SH_GENSH4_BSP_H - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include "rtems/score/sh7750_regs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -/* - * Defined in the linker script 'linkcmds' - */ - -extern void *CPU_Interrupt_stack_low; -extern void *CPU_Interrupt_stack_high; - -/* - * Defined in start.S - */ -extern uint32_t boot_mode; -#define SH4_BOOT_MODE_FLASH 0 -#define SH4_BOOT_MODE_IPL 1 - -/* - * Device Driver Table Entries - */ - -/* - * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console - */ -#undef CONSOLE_DRIVER_TABLE_ENTRY -#define CONSOLE_DRIVER_TABLE_ENTRY \ - { console_initialize, console_open, console_close, \ - console_read, console_write, console_control } - -/* - * BSP methods that cross file boundaries. - */ -void bsp_hw_init(void); -void early_hw_init(void); -void bsp_cache_on(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sh/gensh4/include/tm27.h b/c/src/lib/libbsp/sh/gensh4/include/tm27.h deleted file mode 100644 index c26ec49272..0000000000 --- a/c/src/lib/libbsp/sh/gensh4/include/tm27.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * @file - * @ingroup sh_gensh4 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#ifndef SH7750_EVT_WDT_ITI -# error "..." -#endif - -#define Install_tm27_vector( handler ) \ -{ \ - rtems_isr_entry old_handler; \ - rtems_status_code status; \ - status = rtems_interrupt_catch( (handler), \ - SH7750_EVT_TO_NUM(SH7750_EVT_WDT_ITI), &old_handler); \ - if (status != RTEMS_SUCCESSFUL) \ - printf("Status of rtems_interrupt_catch = %d", status); \ -} - -#define Cause_tm27_intr() \ -{ \ - *(volatile uint16_t*)SH7750_IPRB |= 0xf000; \ - *(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \ - *(volatile uint16_t*)SH7750_WTCNT = SH7750_WTCNT_KEY | 0xfe; \ - *(volatile uint16_t*)SH7750_WTCSR = \ - SH7750_WTCSR_KEY | SH7750_WTCSR_TME; \ -} - -#define Clear_tm27_intr() \ -{ \ - *(volatile uint16_t*)SH7750_WTCSR = SH7750_WTCSR_KEY; \ -} - -#define Lower_tm27_intr() \ -{ \ - sh_set_interrupt_level((SH7750_IPRB & 0xf000) << SH4_SR_IMASK_S); \ -} - -#endif diff --git a/c/src/lib/libbsp/sh/shsim/include/bsp.h b/c/src/lib/libbsp/sh/shsim/include/bsp.h deleted file mode 100644 index 65b55fa13e..0000000000 --- a/c/src/lib/libbsp/sh/shsim/include/bsp.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * SH-gdb simulator BSP - * - * This include file contains all board IO definitions. - */ - -/* - * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) - * - * COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * COPYRIGHT (c) 2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_SH_SHSIM_BSP_H -#define LIBBSP_SH_SHSIM_BSP_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -/* - * FIXME: One of these would be enough. - */ -#include <rtems/devnull.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* Constants */ - -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -/* - * Defined in the linker script 'linkcmds' - */ -extern void *CPU_Interrupt_stack_low; -extern void *CPU_Interrupt_stack_high; - -/* - * BSP methods that cross file boundaries. - */ -int _sys_exit (int n); -void bsp_hw_init(void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ -#endif diff --git a/c/src/lib/libbsp/sh/shsim/include/syscall.h b/c/src/lib/libbsp/sh/shsim/include/syscall.h deleted file mode 100644 index e5cde7217b..0000000000 --- a/c/src/lib/libbsp/sh/shsim/include/syscall.h +++ /dev/null @@ -1,32 +0,0 @@ -#define SYS_exit 1 -#define SYS_fork 2 - -#define SYS_read 3 -#define SYS_write 4 -#define SYS_open 5 -#define SYS_close 6 -#define SYS_wait4 7 -#define SYS_creat 8 -#define SYS_link 9 -#define SYS_unlink 10 -#define SYS_execv 11 -#define SYS_chdir 12 -#define SYS_mknod 14 -#define SYS_chmod 15 -#define SYS_chown 16 -#define SYS_lseek 19 -#define SYS_getpid 20 -#define SYS_isatty 21 -#define SYS_fstat 22 -#define SYS_time 23 - -#define SYS_ARG 24 -#define SYS_stat 38 - -#define SYS_pipe 42 -#define SYS_execve 59 - -#define SYS_utime 201 /* not really a system call */ -#define SYS_wait 202 /* nor is this */ - -int __trap34(int, int, void*, int ); diff --git a/c/src/lib/libbsp/shared/include/coverhd.h b/c/src/lib/libbsp/shared/include/coverhd.h deleted file mode 100644 index 3a551e412a..0000000000 --- a/c/src/lib/libbsp/shared/include/coverhd.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file - * - * @ingroup shared_coverhd - * - * @brief This include file has defines to represent the overhead associated - * with calling a particular directive from C on this target. - */ - -/* coverhd.h - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __COVERHD_h -#define __COVERHD_h - -#ifdef __cplusplus -extern "C" { -#endif - -#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 -#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 -#define CALLING_OVERHEAD_TASK_CREATE 0 -#define CALLING_OVERHEAD_TASK_IDENT 0 -#define CALLING_OVERHEAD_TASK_START 0 -#define CALLING_OVERHEAD_TASK_RESTART 0 -#define CALLING_OVERHEAD_TASK_DELETE 0 -#define CALLING_OVERHEAD_TASK_SUSPEND 0 -#define CALLING_OVERHEAD_TASK_RESUME 0 -#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 -#define CALLING_OVERHEAD_TASK_MODE 0 -#define CALLING_OVERHEAD_TASK_GET_NOTE 0 -#define CALLING_OVERHEAD_TASK_SET_NOTE 0 -#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0 -#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 -#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 -#define CALLING_OVERHEAD_CLOCK_GET 0 -#define CALLING_OVERHEAD_CLOCK_SET 0 -#define CALLING_OVERHEAD_CLOCK_TICK 0 - -#define CALLING_OVERHEAD_TIMER_CREATE 0 -#define CALLING_OVERHEAD_TIMER_IDENT 0 -#define CALLING_OVERHEAD_TIMER_DELETE 0 -#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0 -#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 0 -#define CALLING_OVERHEAD_TIMER_RESET 0 -#define CALLING_OVERHEAD_TIMER_CANCEL 0 -#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 -#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 -#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 -#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 -#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 -#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 - -#define CALLING_OVERHEAD_EVENT_SEND 0 -#define CALLING_OVERHEAD_EVENT_RECEIVE 0 -#define CALLING_OVERHEAD_SIGNAL_CATCH 0 -#define CALLING_OVERHEAD_SIGNAL_SEND 0 -#define CALLING_OVERHEAD_PARTITION_CREATE 0 -#define CALLING_OVERHEAD_PARTITION_IDENT 0 -#define CALLING_OVERHEAD_PARTITION_DELETE 0 -#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 -#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 -#define CALLING_OVERHEAD_REGION_CREATE 0 -#define CALLING_OVERHEAD_REGION_IDENT 0 -#define CALLING_OVERHEAD_REGION_DELETE 0 -#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 -#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 -#define CALLING_OVERHEAD_PORT_CREATE 0 -#define CALLING_OVERHEAD_PORT_IDENT 0 -#define CALLING_OVERHEAD_PORT_DELETE 0 -#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 -#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 - -#define CALLING_OVERHEAD_IO_INITIALIZE 0 -#define CALLING_OVERHEAD_IO_OPEN 0 -#define CALLING_OVERHEAD_IO_CLOSE 0 -#define CALLING_OVERHEAD_IO_READ 0 -#define CALLING_OVERHEAD_IO_WRITE 0 -#define CALLING_OVERHEAD_IO_CONTROL 0 -#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 -#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 -#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/lib/libbsp/shared/include/tm27.h b/c/src/lib/libbsp/shared/include/tm27.h deleted file mode 100644 index 7fdb09a5ba..0000000000 --- a/c/src/lib/libbsp/shared/include/tm27.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @ingroup shared_tm27 - * - * @brief Empty stub for tm27.h - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup shared_tm27 Time Test 27 - * - * @ingroup shared_include - * - * @brief Stuff for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -void Install_tm27_vector(void (*_handler)()) -{ -} - -#define Cause_tm27_intr() \ - do { \ - ; \ - } while (0) - - -#define Clear_tm27_intr() \ - do { \ - ; \ - } while (0) - -#define Lower_tm27_intr() \ - do { \ - ; \ - } while (0) - -#endif diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h b/c/src/lib/libbsp/sparc/erc32/include/bsp.h deleted file mode 100644 index 942a873772..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/bsp.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * @file - * - * @ingroup sparc_erc32 - * - * @brief Global BSP Definitions. - */ - -/* - * COPYRIGHT (c) 1989-2007. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef LIBBSP_SPARC_ERC32_BSP_H -#define LIBBSP_SPARC_ERC32_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <erc32.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sparc_erc32 ERC32 Support - * - * @ingroup bsp_sparc - * - * @brief ERC32 Support Package - */ - -/* - * BSP provides its own Idle thread body - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_erc32_sonic_driver_attach( - struct rtems_bsdnet_ifconfig *config -); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "sonic1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; - -extern int end; /* last address in the program */ - -/* functions */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -void BSP_fatal_exit(uint32_t error); - -void bsp_spurious_initialize( void ); - -/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function - * can be called at any time. The work-area will shrink when called before - * bsp_work_area_initialize(). malloc() is called to get memory when this - * function is called after bsp_work_area_initialize(). - */ -void *bsp_early_malloc(int size); - -/* Interrupt Service Routine (ISR) pointer */ -typedef void (*bsp_shared_isr)(void *arg); - -/* Initializes the Shared System Interrupt service */ -extern void BSP_shared_interrupt_init(void); - -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ -void bsp_isr_handler(rtems_vector_number vector); - -/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple - * interrupt handlers may use the same IRQ number, all ISRs will be called - * when an interrupt on that line is fired. - * - * Arguments - * irq System IRQ number - * info Optional Name of IRQ source - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_register - ( - int irq, - const char *info, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_install(irq, info, - RTEMS_INTERRUPT_SHARED, isr, arg); -} - -/* Unregister previously registered shared IRQ handler. - * - * Arguments - * irq System IRQ number - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_unregister - ( - int irq, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_remove(irq, isr, arg); -} - -/* Clear interrupt pending on IRQ controller, this is typically done on a - * level triggered interrupt source such as PCI to avoid taking double IRQs. - * In such a case the interrupt source must be cleared first on LEON, before - * acknowledging the IRQ with this function. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_clear(int irq); - -/* Enable Interrupt. This function will unmask the IRQ at the interrupt - * controller. This is normally done by _register(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_unmask(int irq); - -/* Disable Interrupt. This function will mask one IRQ at the interrupt - * controller. This is normally done by _unregister(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_mask(int irq); - -/* - * Delay for the specified number of microseconds. - */ -void rtems_bsp_delay(int usecs); - -/* - * Prototypes for methods used across file boundaries - */ -void console_outbyte_polled(int port, unsigned char ch); -int console_inbyte_nonblocking(int port); - -/* BSP PCI Interrupt support - to avoid warnings by libpci */ -#define BSP_PCI_shared_interrupt_register BSP_shared_interrupt_register -#define BSP_PCI_shared_interrupt_unregister BSP_shared_interrupt_unregister -#define BSP_PCI_shared_interrupt_unmask BSP_shared_interrupt_unmask -#define BSP_PCI_shared_interrupt_mask BSP_shared_interrupt_mask -#define BSP_PCI_shared_interrupt_clear BSP_shared_interrupt_clear - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp/irq.h b/c/src/lib/libbsp/sparc/erc32/include/bsp/irq.h deleted file mode 100644 index e0bc3393d8..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/bsp/irq.h +++ /dev/null @@ -1,28 +0,0 @@ -/** - * @file - * @ingroup sparc_erc32 - * @brief ERC32 generic shared IRQ setup - * - * Based on libbsp/shared/include/irq.h. - */ - -/* - * Copyright (c) 2012. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ERC32_IRQ_CONFIG_H -#define LIBBSP_ERC32_IRQ_CONFIG_H - -#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD - -/* No extra check is needed */ -#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR - -#endif /* LIBBSP_ERC32_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/sparc/erc32/include/tm27.h b/c/src/lib/libbsp/sparc/erc32/include/tm27.h deleted file mode 100644 index 958036fbf0..0000000000 --- a/c/src/lib/libbsp/sparc/erc32/include/tm27.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file - * @ingroup sparc_erc32 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 2006. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Since the interrupt code for the SPARC supports both synchronous - * and asynchronous trap handlers, support for testing with both - * is included. - */ - -#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0 - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1) - -#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); - -#define Cause_tm27_intr() \ - __asm__ volatile( "ta 0x10; nop " ); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/* - * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. - */ - -#else /* use a regular asynchronous trap */ - -#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1 -#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1) -#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) -#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); \ - set_vector( (handler), TEST_VECTOR2, 1 ); - -#define Cause_tm27_intr() \ - do { \ - ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \ - nop(); \ - nop(); \ - nop(); \ - } while (0) - -#define Clear_tm27_intr() \ - ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE ) - -#define Lower_tm27_intr() /* empty */ - -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon2/include/bsp.h b/c/src/lib/libbsp/sparc/leon2/include/bsp.h deleted file mode 100644 index 09cf7f702a..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/bsp.h +++ /dev/null @@ -1,236 +0,0 @@ -/** - * @file - * - * @ingroup sparc_leon2 - * - * @brief Global BSP Definitions. - */ - -/* bsp.h - * - * This include file contains all SPARC simulator definitions. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef LIBBSP_SPARC_LEON2_BSP_H -#define LIBBSP_SPARC_LEON2_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <leon.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sparc_leon2 LEON2 Support - * - * @ingroup bsp_sparc - * - * @brief LEON2 Support Package - * - */ - -/* SPARC CPU variant: LEON2 */ -#define LEON2 1 - -/* - * BSP provides its own Idle thread body - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_leon_open_eth_driver_attach( - struct rtems_bsdnet_ifconfig *config -); -extern int rtems_smc91111_driver_attach_leon2( - struct rtems_bsdnet_ifconfig *config -); -#define RTEMS_BSP_NETWORK_DRIVER_NAME "open_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ - rtems_leon_open_eth_driver_attach -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ - rtems_smc91111_driver_attach_leon2 - -#define HAS_SMC91111 - -/* Configure GRETH driver */ -#define GRETH_SUPPORTED -#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t) addr) - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -extern int CPU_SPARC_HAS_SNOOPING; - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; - -extern int end; /* last address in the program */ - -/* miscellaneous stuff assumed to exist */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -void BSP_fatal_exit(uint32_t error); - -void bsp_spurious_initialize( void ); - -/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function - * can be called at any time. The work-area will shrink when called before - * bsp_work_area_initialize(). malloc() is called to get memory when this - * function is called after bsp_work_area_initialize(). - */ -void *bsp_early_malloc(int size); - -/* Interrupt Service Routine (ISR) pointer */ -typedef void (*bsp_shared_isr)(void *arg); - -/* Initializes the Shared System Interrupt service */ -extern void BSP_shared_interrupt_init(void); - -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ -void bsp_isr_handler(rtems_vector_number vector); - -/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple - * interrupt handlers may use the same IRQ number, all ISRs will be called - * when an interrupt on that line is fired. - * - * Arguments - * irq System IRQ number - * info Optional Name of IRQ source - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_register - ( - int irq, - const char *info, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_install(irq, info, - RTEMS_INTERRUPT_SHARED, isr, arg); -} - -/* Unregister previously registered shared IRQ handler. - * - * Arguments - * irq System IRQ number - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_unregister - ( - int irq, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_remove(irq, isr, arg); -} - -/* Clear interrupt pending on IRQ controller, this is typically done on a - * level triggered interrupt source such as PCI to avoid taking double IRQs. - * In such a case the interrupt source must be cleared first on LEON, before - * acknowledging the IRQ with this function. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_clear(int irq); - -/* Enable Interrupt. This function will unmask the IRQ at the interrupt - * controller. This is normally done by _register(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_unmask(int irq); - -/* Disable Interrupt. This function will mask one IRQ at the interrupt - * controller. This is normally done by _unregister(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_mask(int irq); - -/* - * Delay method - */ -void rtems_bsp_delay(int usecs); - -/* - * Prototypes for BSP methods that are used across file boundaries - */ -int cchip1_register(void); - -/* BSP PCI Interrupt support */ -#define BSP_PCI_shared_interrupt_register BSP_shared_interrupt_register -#define BSP_PCI_shared_interrupt_unregister BSP_shared_interrupt_unregister -#define BSP_PCI_shared_interrupt_unmask BSP_shared_interrupt_unmask -#define BSP_PCI_shared_interrupt_mask BSP_shared_interrupt_mask -#define BSP_PCI_shared_interrupt_clear BSP_shared_interrupt_clear - -/* AT697 has PCI defined as big endian */ -#define BSP_PCI_BIG_ENDIAN - -/* Common driver build-time configurations. On small systems undefine - * [DRIVER]_INFO_AVAIL to avoid info routines get dragged in. It is good - * for debugging and printing information about the system, but makes the - * image bigger. - */ -#define AMBAPPBUS_INFO_AVAIL /* AMBAPP Bus driver */ -#define GPTIMER_INFO_AVAIL /* GPTIMER Timer driver */ -#define GRETH_INFO_AVAIL /* GRETH Ethernet driver */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon2/include/bsp/irq.h b/c/src/lib/libbsp/sparc/leon2/include/bsp/irq.h deleted file mode 100644 index 086bf253c4..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/bsp/irq.h +++ /dev/null @@ -1,28 +0,0 @@ -/** - * @file - * @ingroup sparc_leon2 - * @brief Interrupts definitions - * - * Based on libbsp/shared/include/irq.h. - */ - -/* - * Copyright (c) 2012. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_LEON2_IRQ_CONFIG_H -#define LIBBSP_LEON2_IRQ_CONFIG_H - -#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_STD - -/* No extra check is needed */ -#undef BSP_INTERRUPT_CUSTOM_VALID_VECTOR - -#endif /* LIBBSP_LEON2_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/sparc/leon2/include/leon.h b/c/src/lib/libbsp/sparc/leon2/include/leon.h deleted file mode 100644 index 7ec6b1dcf9..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/leon.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - * @defgroup leon1 Leon-1 Handler - * @ingroup sparc_leon2 - * - * @file - * @ingroup leon1 - * @brief Handlers Leon-1 - * - * This include file contains information pertaining to the LEON-1. - * The LEON-1 is a custom SPARC V7 implementation. - * This CPU has a number of on-board peripherals and - * was developed by the European Space Agency to target space applications. - * - * NOTE: Other than where absolutely required, this version currently - * supports only the peripherals and bits used by the basic board - * support package. This includes at least significant pieces of - * the following items: - * - * + UART Channels A and B - * + Real Time Clock - * + Memory Control Register - * + Interrupt Control - * - */ - -/* - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to LEON implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef _INCLUDE_LEON_h -#define _INCLUDE_LEON_h - -#include <rtems/score/sparc.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Interrupt Sources - * - * The interrupt source numbers directly map to the trap type and to - * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - */ - -#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 -#define LEON_INTERRUPT_UART_2_RX_TX 2 -#define LEON_INTERRUPT_UART_1_RX_TX 3 -#define LEON_INTERRUPT_EXTERNAL_0 4 -#define LEON_INTERRUPT_EXTERNAL_1 5 -#define LEON_INTERRUPT_EXTERNAL_2 6 -#define LEON_INTERRUPT_EXTERNAL_3 7 -#define LEON_INTERRUPT_TIMER1 8 -#define LEON_INTERRUPT_TIMER2 9 -#define LEON_INTERRUPT_EMPTY1 10 -#define LEON_INTERRUPT_EMPTY2 11 -#define LEON_INTERRUPT_EMPTY3 12 -#define LEON_INTERRUPT_EMPTY4 13 -#define LEON_INTERRUPT_EMPTY5 14 -#define LEON_INTERRUPT_EMPTY6 15 - -#ifndef ASM - -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define LEON_INT_TRAP( _trap ) \ - ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \ - (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) ) - -/* - * Structure for LEON memory mapped registers. - * - * Source: Section 6.1 - On-chip registers - * - * NOTE: There is only one of these structures per CPU, its base address - * is 0x80000000, and the variable LEON_REG is placed there by the - * linkcmds file. - */ - -typedef struct { - volatile unsigned int Memory_Config_1; - volatile unsigned int Memory_Config_2; - volatile unsigned int Edac_Control; - volatile unsigned int Failed_Address; - volatile unsigned int Memory_Status; - volatile unsigned int Cache_Control; - volatile unsigned int Power_Down; - volatile unsigned int Write_Protection_1; - volatile unsigned int Write_Protection_2; - volatile unsigned int Leon_Configuration; - volatile unsigned int dummy2; - volatile unsigned int dummy3; - volatile unsigned int dummy4; - volatile unsigned int dummy5; - volatile unsigned int dummy6; - volatile unsigned int dummy7; - volatile unsigned int Timer_Counter_1; - volatile unsigned int Timer_Reload_1; - volatile unsigned int Timer_Control_1; - volatile unsigned int Watchdog; - volatile unsigned int Timer_Counter_2; - volatile unsigned int Timer_Reload_2; - volatile unsigned int Timer_Control_2; - volatile unsigned int dummy8; - volatile unsigned int Scaler_Counter; - volatile unsigned int Scaler_Reload; - volatile unsigned int dummy9; - volatile unsigned int dummy10; - volatile unsigned int UART_Channel_1; - volatile unsigned int UART_Status_1; - volatile unsigned int UART_Control_1; - volatile unsigned int UART_Scaler_1; - volatile unsigned int UART_Channel_2; - volatile unsigned int UART_Status_2; - volatile unsigned int UART_Control_2; - volatile unsigned int UART_Scaler_2; - volatile unsigned int Interrupt_Mask; - volatile unsigned int Interrupt_Pending; - volatile unsigned int Interrupt_Force; - volatile unsigned int Interrupt_Clear; - volatile unsigned int PIO_Data; - volatile unsigned int PIO_Direction; - volatile unsigned int PIO_Interrupt; -} LEON_Register_Map; - -#endif - -/* - * The following constants are intended to be used ONLY in assembly - * language files. - * - * NOTE: The intended style of usage is to load the address of LEON REGS - * into a register and then use these as displacements from - * that register. - */ - -#ifdef ASM - -#define LEON_REG_MEMCFG1_OFFSET 0x00 -#define LEON_REG_MEMCFG2_OFFSET 0x04 -#define LEON_REG_EDACCTRL_OFFSET 0x08 -#define LEON_REG_FAILADDR_OFFSET 0x0C -#define LEON_REG_MEMSTATUS_OFFSET 0x10 -#define LEON_REG_CACHECTRL_OFFSET 0x14 -#define LEON_REG_POWERDOWN_OFFSET 0x18 -#define LEON_REG_WRITEPROT1_OFFSET 0x1C -#define LEON_REG_WRITEPROT2_OFFSET 0x20 -#define LEON_REG_LEONCONF_OFFSET 0x24 -#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 -#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C -#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 -#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 -#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 -#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C -#define LEON_REG_TIMERCNT1_OFFSET 0x40 -#define LEON_REG_TIMERLOAD1_OFFSET 0x44 -#define LEON_REG_TIMERCTRL1_OFFSET 0x48 -#define LEON_REG_WDOG_OFFSET 0x4C -#define LEON_REG_TIMERCNT2_OFFSET 0x50 -#define LEON_REG_TIMERLOAD2_OFFSET 0x54 -#define LEON_REG_TIMERCTRL2_OFFSET 0x58 -#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C -#define LEON_REG_SCALERCNT_OFFSET 0x60 -#define LEON_REG_SCALER_LOAD_OFFSET 0x64 -#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 -#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C -#define LEON_REG_UARTDATA1_OFFSET 0x70 -#define LEON_REG_UARTSTATUS1_OFFSET 0x74 -#define LEON_REG_UARTCTRL1_OFFSET 0x78 -#define LEON_REG_UARTSCALER1_OFFSET 0x7C -#define LEON_REG_UARTDATA2_OFFSET 0x80 -#define LEON_REG_UARTSTATUS2_OFFSET 0x84 -#define LEON_REG_UARTCTRL2_OFFSET 0x88 -#define LEON_REG_UARTSCALER2_OFFSET 0x8C -#define LEON_REG_IRQMASK_OFFSET 0x90 -#define LEON_REG_IRQPEND_OFFSET 0x94 -#define LEON_REG_IRQFORCE_OFFSET 0x98 -#define LEON_REG_IRQCLEAR_OFFSET 0x9C -#define LEON_REG_PIODATA_OFFSET 0xA0 -#define LEON_REG_PIODIR_OFFSET 0xA4 -#define LEON_REG_PIOIRQ_OFFSET 0xA8 -#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 -#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 - -#endif - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 - - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - * - */ - -#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the LEON UART Status Registers. - */ - -#define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */ -#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ -#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ -#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ -#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ - - -/* - * The following defines the bits in the LEON UART Status Registers. - */ - -#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ -#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ -#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ -#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ -#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ -#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ -#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ -#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ - -#ifndef ASM - -/* - * This is used to manipulate the on-chip registers. - * - * The following symbol must be defined in the linkcmds file and point - * to the correct location. - */ - -extern LEON_Register_Map LEON_REG; - -static __inline__ int bsp_irq_fixup(int irq) -{ - return irq; -} - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -#define LEON_Clear_interrupt( _source ) \ - do { \ - LEON_REG.Interrupt_Clear = (1 << (_source)); \ - } while (0) - -#define LEON_Force_interrupt( _source ) \ - do { \ - LEON_REG.Interrupt_Force = (1 << (_source)); \ - } while (0) - -#define LEON_Is_interrupt_pending( _source ) \ - (LEON_REG.Interrupt_Pending & (1 << (_source))) - -#define LEON_Is_interrupt_masked( _source ) \ - (!(LEON_REG.Interrupt_Mask & (1 << (_source)))) - -#define LEON_Mask_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define LEON_Unmask_interrupt( _source ) \ - do { \ - uint32_t _level; \ - \ - _level = sparc_disable_interrupts(); \ - LEON_REG.Interrupt_Mask |= (1 << (_source)); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -#define LEON_Disable_interrupt( _source, _previous ) \ - do { \ - uint32_t _level; \ - uint32_t _mask = 1 << (_source); \ - \ - _level = sparc_disable_interrupts(); \ - (_previous) = LEON_REG.Interrupt_Mask; \ - LEON_REG.Interrupt_Mask = _previous & ~_mask; \ - sparc_enable_interrupts( _level ); \ - (_previous) &= _mask; \ - } while (0) - -#define LEON_Restore_interrupt( _source, _previous ) \ - do { \ - uint32_t _level; \ - uint32_t _mask = 1 << (_source); \ - \ - _level = sparc_disable_interrupts(); \ - LEON_REG.Interrupt_Mask = \ - (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \ - sparc_enable_interrupts( _level ); \ - } while (0) - -/* Make all SPARC BSPs have common macros for interrupt handling */ -#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) -#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) -#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) -#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) -#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) -#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) -#define BSP_Disable_interrupt(_source, _previous) \ - LEON_Disable_interrupt(_source, _prev) -#define BSP_Restore_interrupt(_source, _previous) \ - LEON_Restore_interrupt(_source, _previous) - -/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ -#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ - BSP_Is_interrupt_masked(_source) -#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ - BSP_Unmask_interrupt(_source) -#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ - BSP_Mask_interrupt(_source) -#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ - BSP_Disable_interrupt(_source, _prev) -#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ - BSP_Cpu_Restore_interrupt(_source, _previous) - -/* - * Each timer control register is organized as follows: - * - * D0 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D1 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D2 - Counter Load - * 1 = load counter with preset value - * 0 = no function - * - */ - -#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 -#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 - -#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 -#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 -#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 - -#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 -#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 - -/* Load 32-bit word by forcing a cache-miss */ -static inline unsigned int leon_r32_no_cache(uintptr_t addr) -{ - unsigned int tmp; - __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); - return tmp; -} - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_LEON_h */ - diff --git a/c/src/lib/libbsp/sparc/leon2/include/tm27.h b/c/src/lib/libbsp/sparc/leon2/include/tm27.h deleted file mode 100644 index 0d28641b9b..0000000000 --- a/c/src/lib/libbsp/sparc/leon2/include/tm27.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * @ingroup sparc_leon2 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 2006. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Since the interrupt code for the SPARC supports both synchronous - * and asynchronous trap handlers, support for testing with both - * is included. - */ - -#define SIS_USE_SYNCHRONOUS_TRAP 0 - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -#if (SIS_USE_SYNCHRONOUS_TRAP == 1) - -#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); - -#define Cause_tm27_intr() \ - __asm__ volatile( "ta 0x10; nop " ); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/* - * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. - */ - -#else /* use a regular asynchronous trap */ - -#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 -#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) -#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 -#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); \ - set_vector( (handler), TEST_VECTOR2, 1 ); - -#define Cause_tm27_intr() \ - do { \ - LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ - nop(); \ - nop(); \ - nop(); \ - } while (0) - -#define Clear_tm27_intr() \ - LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) - -#define Lower_tm27_intr() /* empty */ - -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon3/include/bsp.h b/c/src/lib/libbsp/sparc/leon3/include/bsp.h deleted file mode 100644 index 5642e14c57..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/bsp.h +++ /dev/null @@ -1,266 +0,0 @@ -/** - * @file - * - * @ingroup sparc_leon3 - * - * @brief Global BSP Definitions. - */ - -/* bsp.h - * - * This include file contains all SPARC simulator definitions. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Ported to ERC32 implementation of the SPARC by On-Line Applications - * Research Corporation (OAR) under contract to the European Space - * Agency (ESA). - * - * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. - * European Space Agency. - */ - -#ifndef LIBBSP_SPARC_LEON3_BSP_H -#define LIBBSP_SPARC_LEON3_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <leon.h> -#include <rtems/clockdrv.h> -#include <rtems/console.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup sparc_leon3 LEON3 Support - * - * @ingroup bsp_sparc - * - * @brief LEON3 support package - * - */ - -/* SPARC CPU variant: LEON3 */ -#define LEON3 1 - -/* - * BSP provides its own Idle thread body - */ -void *bsp_idle_thread( uintptr_t ignored ); -#define BSP_IDLE_TASK_BODY bsp_idle_thread - -/* Maximum supported APBUARTs by BSP */ -#define BSP_NUMBER_OF_TERMIOS_PORTS 8 - -/* Make sure maximum number of consoles fit in filesystem */ -#define BSP_MAXIMUM_DEVICES 8 - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int rtems_leon_open_eth_driver_attach( - struct rtems_bsdnet_ifconfig *config, - int attach -); -extern int rtems_smc91111_driver_attach_leon3( - struct rtems_bsdnet_ifconfig *config, - int attach -); -extern int rtems_leon_greth_driver_attach( - struct rtems_bsdnet_ifconfig *config, - int attach -); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME_OPENETH "open_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH \ - rtems_leon_open_eth_driver_attach -#define RTEMS_BSP_NETWORK_DRIVER_NAME_SMC91111 "smc_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \ - rtems_smc91111_driver_attach_leon3 -#define RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH "gr_eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH \ - rtems_leon_greth_driver_attach - -#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME -#define RTEMS_BSP_NETWORK_DRIVER_NAME RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH -#endif - -#define HAS_SMC91111 - -/* Configure GRETH driver */ -#define GRETH_SUPPORTED -#define GRETH_MEM_LOAD(addr) leon_r32_no_cache((uintptr_t)addr) - -extern int CPU_SPARC_HAS_SNOOPING; - -/* Constants */ - -/* - * Information placed in the linkcmds file. - */ - -extern int RAM_START; -extern int RAM_END; -extern int RAM_SIZE; - -extern int PROM_START; -extern int PROM_END; -extern int PROM_SIZE; - -extern int CLOCK_SPEED; - -extern int end; /* last address in the program */ - -/* miscellaneous stuff assumed to exist */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -void BSP_fatal_exit(uint32_t error); - -void bsp_spurious_initialize( void ); - -/* - * Delay for the specified number of microseconds. - */ -void rtems_bsp_delay(int usecs); - -/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function - * can be called at any time. The work-area will shrink when called before - * bsp_work_area_initialize(). malloc() is called to get memory when this - * function is called after bsp_work_area_initialize(). - */ -void *bsp_early_malloc(int size); - -/* Interrupt Service Routine (ISR) pointer */ -typedef void (*bsp_shared_isr)(void *arg); - -/* Initializes the Shared System Interrupt service */ -extern void BSP_shared_interrupt_init(void); - -/* Called directly from IRQ trap handler TRAP[0x10..0x1F] = IRQ[0..15] */ -void bsp_isr_handler(rtems_vector_number vector); - -/* Registers a shared IRQ handler, and enable it at IRQ controller. Multiple - * interrupt handlers may use the same IRQ number, all ISRs will be called - * when an interrupt on that line is fired. - * - * Arguments - * irq System IRQ number - * info Optional Name of IRQ source - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_register - ( - int irq, - const char *info, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_install(irq, info, - RTEMS_INTERRUPT_SHARED, isr, arg); -} - -/* Unregister previously registered shared IRQ handler. - * - * Arguments - * irq System IRQ number - * isr Function pointer to the ISR - * arg Second argument to function isr - */ -static __inline__ int BSP_shared_interrupt_unregister - ( - int irq, - bsp_shared_isr isr, - void *arg - ) -{ - return rtems_interrupt_handler_remove(irq, isr, arg); -} - -/* Clear interrupt pending on IRQ controller, this is typically done on a - * level triggered interrupt source such as PCI to avoid taking double IRQs. - * In such a case the interrupt source must be cleared first on LEON, before - * acknowledging the IRQ with this function. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_clear(int irq); - -/* Enable Interrupt. This function will unmask the IRQ at the interrupt - * controller. This is normally done by _register(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_unmask(int irq); - -/* Disable Interrupt. This function will mask one IRQ at the interrupt - * controller. This is normally done by _unregister(). Note that this will - * affect all ISRs on this IRQ. - * - * Arguments - * irq System IRQ number - */ -extern void BSP_shared_interrupt_mask(int irq); - -#if defined(RTEMS_SMP) || defined(RTEMS_MULTIPROCESSING) -/* Irq used by the shared memory driver and for inter-processor interrupts. - * The variable is weakly linked. Redefine the variable in your application - * to override the BSP default. - */ -extern const unsigned char LEON3_mp_irq; -#endif - -#ifdef RTEMS_SMP -/* Weak table used to implement static interrupt CPU affinity in a SMP - * configuration. The array index is the interrupt to be looked up, and - * the array[INTERRUPT] content is the CPU number relative to boot CPU - * index that will be servicing the interrupts from the IRQ source. The - * default is to let the first CPU (the boot cpu) to handle all - * interrupts (all zeros). - */ -extern const unsigned char LEON3_irq_to_cpu[32]; -#endif - -/* BSP PCI Interrupt support */ -#define BSP_PCI_shared_interrupt_register BSP_shared_interrupt_register -#define BSP_PCI_shared_interrupt_unregister BSP_shared_interrupt_unregister -#define BSP_PCI_shared_interrupt_unmask BSP_shared_interrupt_unmask -#define BSP_PCI_shared_interrupt_mask BSP_shared_interrupt_mask -#define BSP_PCI_shared_interrupt_clear BSP_shared_interrupt_clear - -/* Common driver build-time configurations. On small systems undefine - * [DRIVER]_INFO_AVAIL to avoid info routines get dragged in. It is good - * for debugging and printing information about the system, but makes the - * image bigger. - */ -#define AMBAPPBUS_INFO_AVAIL /* AMBAPP Bus driver */ -#define APBUART_INFO_AVAIL /* APBUART Console driver */ -#define GPTIMER_INFO_AVAIL /* GPTIMER Timer driver */ -#define GRETH_INFO_AVAIL /* GRETH Ethernet driver */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon3/include/bsp/irq.h b/c/src/lib/libbsp/sparc/leon3/include/bsp/irq.h deleted file mode 100644 index b429c864b5..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/bsp/irq.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief LEON3 generic shared IRQ setup - * - * Based on libbsp/shared/include/irq.h. - */ - -/* - * Copyright (c) 2012. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_LEON3_IRQ_CONFIG_H -#define LIBBSP_LEON3_IRQ_CONFIG_H - -#include <leon.h> - -#define BSP_INTERRUPT_VECTOR_MAX_STD 15 /* Standard IRQ controller */ -#define BSP_INTERRUPT_VECTOR_MAX_EXT 31 /* Extended IRQ controller */ - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX BSP_INTERRUPT_VECTOR_MAX_EXT - -/* The check is different depending on IRQ controller, runtime detected */ -#define BSP_INTERRUPT_CUSTOM_VALID_VECTOR - -/** - * @brief Returns true if the interrupt vector with number @a vector is valid. - */ -static inline bool bsp_interrupt_is_valid_vector(rtems_vector_number vector) -{ - return (rtems_vector_number) BSP_INTERRUPT_VECTOR_MIN <= vector - && ((vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_STD && - LEON3_IrqCtrl_EIrq == 0) || - (vector <= (rtems_vector_number) BSP_INTERRUPT_VECTOR_MAX_EXT && - LEON3_IrqCtrl_EIrq != 0)); -} - -#endif /* LIBBSP_LEON3_IRQ_CONFIG_H */ diff --git a/c/src/lib/libbsp/sparc/leon3/include/leon.h b/c/src/lib/libbsp/sparc/leon3/include/leon.h deleted file mode 100644 index 5ac1d71872..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/leon.h +++ /dev/null @@ -1,452 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief LEON3 BSP data types and macros - */ - -/* leon.h - * - * LEON3 BSP data types and macros. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * Modified for LEON3 BSP. - * COPYRIGHT (c) 2004. - * Gaisler Research. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _INCLUDE_LEON_h -#define _INCLUDE_LEON_h - -#include <rtems.h> -#include <amba.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define LEON_INTERRUPT_EXTERNAL_1 5 - -#ifndef ASM -/* - * Trap Types for on-chip peripherals - * - * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments - * - * NOTE: The priority level for each source corresponds to the least - * significant nibble of the trap type. - */ - -#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) - -#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) - -#define LEON_INT_TRAP( _trap ) \ - ( (_trap) >= 0x11 && \ - (_trap) <= 0x1F ) - -/* /\* */ -/* * This is used to manipulate the on-chip registers. */ -/* * */ -/* * The following symbol must be defined in the linkcmds file and point */ -/* * to the correct location. */ -/* *\/ */ -/* Leon uses dynamic register mapping using amba configuration records */ -/* LEON_Register_Map is obsolete */ -/* extern LEON_Register_Map LEON_REG; */ - -#endif - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 - -/* - * The following defines the bits in Memory Configuration Register 1. - */ - -#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 - - -/* - * The following defines the bits in the Timer Control Register. - */ - -#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ - /* 0 = hold scalar and counter */ -#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ - /* 0 = stop at 0 */ -#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ - /* 0 = no function */ - -/* - * The following defines the bits in the UART Control Registers. - */ - -#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ - -/* - * The following defines the bits in the LEON UART Status Register. - */ - -#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ -#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ -#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ -#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ -#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ -#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ -#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ -#define LEON_REG_UART_STATUS_TF 0x00000200 /* FIFO Full */ -#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ - -/* - * The following defines the bits in the LEON UART Control Register. - */ - -#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ -#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ -#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ -#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ -#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ -#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ -#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ -#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ -#define LEON_REG_UART_CTRL_DB 0x00000800 /* Debug FIFO enable */ -#define LEON_REG_UART_CTRL_SI 0x00004000 /* TX shift register empty IRQ enable */ -#define LEON_REG_UART_CTRL_FA 0x80000000 /* FIFO Available */ -#define LEON_REG_UART_CTRL_FA_BIT 31 - -/* - * The following defines the bits in the LEON Cache Control Register. - */ -#define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ -#define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ - -/* LEON3 Interrupt Controller */ -extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; -extern struct ambapp_dev *LEON3_IrqCtrl_Adev; - -/* LEON3 GP Timer */ -extern volatile struct gptimer_regs *LEON3_Timer_Regs; -extern struct ambapp_dev *LEON3_Timer_Adev; - -/* LEON3 CPU Index of boot CPU */ -extern uint32_t LEON3_Cpu_Index; - -/* The external IRQ number, -1 if not external interrupts */ -extern int LEON3_IrqCtrl_EIrq; - -static __inline__ int bsp_irq_fixup(int irq) -{ - int eirq, cpu; - - if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { - /* Get interrupt number from IRQ controller */ - cpu = _LEON3_Get_current_processor(); - eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; - if (eirq & 0x10) - irq = eirq; - } - - return irq; -} - -/* Macros used for manipulating bits in LEON3 GP Timer Control Register */ - -#define LEON3_IRQMPSTATUS_CPUNR 28 -#define LEON3_IRQMPSTATUS_BROADCAST 27 - - -#ifndef ASM - -/* - * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, - * and the Interrupt Pending Registers. - * - * NOTE: For operations which are not atomic, this code disables interrupts - * to guarantee there are no intervening accesses to the same register. - * The operations which read the register, modify the value and then - * store the result back are vulnerable. - */ - -extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; - -#define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ - rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) - -#define LEON3_IRQCTRL_RELEASE( _lock_context ) \ - rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) - -#define LEON_Clear_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iclear = (1 << (_source)); \ - } while (0) - -#define LEON_Force_interrupt( _source ) \ - do { \ - LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \ - } while (0) - -#define LEON_Is_interrupt_pending( _source ) \ - (LEON3_IrqCtrl_Regs->ipend & (1 << (_source))) - -#define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ - (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1 << (_source)))) - -#define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1 << (_source)); \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -#define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] |= (1 << (_source)); \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -#define LEON_Cpu_Disable_interrupt( _source, _previous, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1 << (_source); \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ - LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - (_previous) &= _mask; \ - } while (0) - -#define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ - do { \ - rtems_interrupt_lock_context _lock_context; \ - uint32_t _mask = 1 << (_source); \ - LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ - LEON3_IrqCtrl_Regs->mask[_cpu] = \ - (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ - LEON3_IRQCTRL_RELEASE( &_lock_context ); \ - } while (0) - -/* Map single-cpu operations to local CPU */ -#define LEON_Is_interrupt_masked( _source ) \ - LEON_Cpu_Is_interrupt_masked(_source, _LEON3_Get_current_processor()) - -#define LEON_Mask_interrupt(_source) \ - LEON_Cpu_Mask_interrupt(_source, _LEON3_Get_current_processor()) - -#define LEON_Unmask_interrupt(_source) \ - LEON_Cpu_Unmask_interrupt(_source, _LEON3_Get_current_processor()) - -#define LEON_Disable_interrupt(_source, _previous) \ - LEON_Cpu_Disable_interrupt(_source, _previous, _LEON3_Get_current_processor()) - -#define LEON_Restore_interrupt(_source, _previous) \ - LEON_Cpu_Restore_interrupt(_source, _previous, _LEON3_Get_current_processor()) - -/* Make all SPARC BSPs have common macros for interrupt handling */ -#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) -#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) -#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) -#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) -#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) -#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) -#define BSP_Disable_interrupt(_source, _previous) \ - LEON_Disable_interrupt(_source, _prev) -#define BSP_Restore_interrupt(_source, _previous) \ - LEON_Restore_interrupt(_source, _previous) - -/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ -#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ - LEON_Cpu_Is_interrupt_masked(_source, _cpu) -#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ - LEON_Cpu_Unmask_interrupt(_source, _cpu) -#define BSP_Cpu_Mask_interrupt(_source, _cpu) \ - LEON_Cpu_Mask_interrupt(_source, _cpu) -#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ - LEON_Cpu_Disable_interrupt(_source, _prev, _cpu) -#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ - LEON_Cpu_Restore_interrupt(_source, _previous, _cpu) - -/* - * Each timer control register is organized as follows: - * - * D0 - Enable - * 1 = enable counting - * 0 = hold scaler and counter - * - * D1 - Counter Reload - * 1 = reload counter at zero and restart - * 0 = stop counter at zero - * - * D2 - Counter Load - * 1 = load counter with preset value - * 0 = no function - * - */ - -#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 -#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 - -#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 - -#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 -#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 - -#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 -#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 - -#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 -#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 - -#if defined(RTEMS_MULTIPROCESSING) - #define LEON3_CLOCK_INDEX \ - (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) -#else - #define LEON3_CLOCK_INDEX 0 -#endif - -/* - * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to - * run with 1MHz. This is used to determine all clock frequencies of the PnP - * devices. See also ambapp_freq_init() and ambapp_freq_get(). - */ -#define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 - -/* Load 32-bit word by forcing a cache-miss */ -static inline unsigned int leon_r32_no_cache(uintptr_t addr) -{ - unsigned int tmp; - __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); - return tmp; -} - -/* Let user override which on-chip APBUART will be debug UART - * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... - * 1 = APBUART[0] - * 2 = APBUART[1] - * 3 = APBUART[2] - * ... - */ -extern int syscon_uart_index; - -/* Let user override which on-chip APBUART will be debug UART - * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... - * 1 = APBUART[0] - * 2 = APBUART[1] - * 3 = APBUART[2] - * ... - */ -extern int debug_uart_index; - -/* Let user override which on-chip TIMER core will be used for system clock - * timer. This controls which timer core will be accociated with - * LEON3_Timer_Regs registers base address. This value will by destroyed during - * initialization. - * 0 = Default configuration. GPTIMER[0] - * 1 = GPTIMER[1] - * 2 = GPTIMER[2] - * ... - */ -extern int leon3_timer_core_index; - -/* Let user override system clock timer prescaler. This affects all timer - * instances on the system clock timer core determined by - * leon3_timer_core_index. - * 0 = Default configuration. Use bootloader configured value. - * N = Prescaler is set to N. N must not be less that number of timers. - * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) - * ... - */ -extern unsigned int leon3_timer_prescaler; - -void leon3_cpu_counter_initialize(void); - -/* GRLIB extended IRQ controller register */ -void leon3_ext_irq_init(void); - -void bsp_debug_uart_init(void); - -void leon3_power_down_loop(void) RTEMS_NO_RETURN; - -static inline uint32_t leon3_get_cpu_count( - volatile struct irqmp_regs *irqmp -) -{ - uint32_t mpstat = irqmp->mpstat; - - return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; -} - -static inline void leon3_set_system_register(uint32_t addr, uint32_t val) -{ - __asm__ volatile( - "sta %1, [%0] 2" - : - : "r" (addr), "r" (val) - ); -} - -static inline uint32_t leon3_get_system_register(uint32_t addr) -{ - uint32_t val; - - __asm__ volatile( - "lda [%1] 2, %0" - : "=r" (val) - : "r" (addr) - ); - - return val; -} - -static inline void leon3_set_cache_control_register(uint32_t val) -{ - leon3_set_system_register(0x0, val); -} - -static inline uint32_t leon3_get_cache_control_register(void) -{ - return leon3_get_system_register(0x0); -} - -static inline bool leon3_data_cache_snooping_enabled(void) -{ - return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; -} - -static inline uint32_t leon3_get_inst_cache_config_register(void) -{ - return leon3_get_system_register(0x8); -} - -static inline uint32_t leon3_get_data_cache_config_register(void) -{ - return leon3_get_system_register(0xc); -} - -static inline bool leon3_irqmp_has_timestamp( - volatile struct irqmp_timestamp_regs *irqmp_ts -) -{ - return (irqmp_ts->control >> 27) > 0; -} - -#endif /* !ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_INCLUDE_LEON_h */ -/* end of include file */ - diff --git a/c/src/lib/libbsp/sparc/leon3/include/tm27.h b/c/src/lib/libbsp/sparc/leon3/include/tm27.h deleted file mode 100644 index 00921d4880..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/tm27.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * @file - * @ingroup sparc_leon3 - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * COPYRIGHT (c) 2006. - * Aeroflex Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - * - * NOTE: Since the interrupt code for the SPARC supports both synchronous - * and asynchronous trap handlers, support for testing with both - * is included. - */ - -#define SIS_USE_SYNCHRONOUS_TRAP 0 - -/* - * The synchronous trap is an arbitrarily chosen software trap. - */ - -#if (SIS_USE_SYNCHRONOUS_TRAP == 1) - -#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 ) - -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); - -#define Cause_tm27_intr() \ - __asm__ volatile( "ta 0x10; nop " ); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/* - * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source. - */ - -#else /* use a regular asynchronous trap */ - -#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1 -#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE ) -#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1 -#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 ) -#define MUST_WAIT_FOR_INTERRUPT 1 - -#define Install_tm27_vector( handler ) \ - set_vector( (handler), TEST_VECTOR, 1 ); \ - set_vector( (handler), TEST_VECTOR2, 1 ); - -#define Cause_tm27_intr() \ - do { \ - LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \ - nop(); \ - nop(); \ - nop(); \ - } while (0) - -#define Clear_tm27_intr() \ - LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE ) - -#define Lower_tm27_intr() /* empty */ - -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc/leon3/include/watchdog.h b/c/src/lib/libbsp/sparc/leon3/include/watchdog.h deleted file mode 100644 index 3c63be2a8f..0000000000 --- a/c/src/lib/libbsp/sparc/leon3/include/watchdog.h +++ /dev/null @@ -1,49 +0,0 @@ -/* watchdog.h - * - * The LEON3 BSP timer watch-dog interface - * - * COPYRIGHT (c) 2012. - * Cobham Gaisler AB. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Initialize BSP watchdog routines. Returns number of watchdog timers found. - * Currently only one is supported. - */ -int bsp_watchdog_init(void); - -/* Reload watchdog (last timer on the first GPTIMER core), all systems does not - * feature a watchdog, it is expected that if this function is called the - * user knows that there is a watchdog available. - * - * The prescaler is normally set to number of MHz of system, this is to - * make the system clock tick be stable. - * - * Arguments - * watchdog - Always 0 for now - * reload_value - Number of timer clocks (after prescaler) to count before - * watchdog is woken. - */ -void bsp_watchdog_reload(int watchdog, unsigned int reload_value); - -/* Stop watchdog timer */ -void bsp_watchdog_stop(int watchdog); - -/* Use watchdog0 timer to reset the system */ -void bsp_watchdog_system_reset(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc64/niagara/include/bsp.h b/c/src/lib/libbsp/sparc64/niagara/include/bsp.h deleted file mode 100644 index 0eb31300ea..0000000000 --- a/c/src/lib/libbsp/sparc64/niagara/include/bsp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* bsp.h - * - * This include file contains all SPARC64 simulator definitions. - * - * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_SPARC64_NIAGARA_BSP_H -#define LIBBSP_SPARC64_NIAGARA_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -/* -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body -*/ - -/* this should be defined somewhere */ -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc64/niagara/include/tm27.h b/c/src/lib/libbsp/sparc64/niagara/include/tm27.h deleted file mode 100644 index 9001b807ab..0000000000 --- a/c/src/lib/libbsp/sparc64/niagara/include/tm27.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * @file - * @ingroup sparc64_niagara - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ - -#define Cause_tm27_intr() /* XXX */ - -#define Clear_tm27_intr() /* XXX */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/sparc64/usiii/include/bsp.h b/c/src/lib/libbsp/sparc64/usiii/include/bsp.h deleted file mode 100644 index 3db442a18a..0000000000 --- a/c/src/lib/libbsp/sparc64/usiii/include/bsp.h +++ /dev/null @@ -1,45 +0,0 @@ -/* bsp.h - * - * This include file contains all SPARC64 simulator definitions. - * - * COPYRIGHT (c) 1989-1998. On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef LIBBSP_SPARC64_USIII_BSP_H -#define LIBBSP_SPARC64_USIII_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -/* -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body -*/ - -/* this should be defined somewhere */ -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/sparc64/usiii/include/tm27.h b/c/src/lib/libbsp/sparc64/usiii/include/tm27.h deleted file mode 100644 index 14e07ca3a8..0000000000 --- a/c/src/lib/libbsp/sparc64/usiii/include/tm27.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * @file - * @ingroup sparc64_usiii - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ - -#define Cause_tm27_intr() /* XXX */ - -#define Clear_tm27_intr() /* XXX */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h b/c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h deleted file mode 100644 index 6942eefd09..0000000000 --- a/c/src/lib/libbsp/v850/gdbv850sim/include/bsp.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This include file contains some definitions specific to the - * GDB simulator in gdb. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_V850_GDBV850SIM_BSP_H -#define LIBBSP_V850_GDBV850SIM_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* support for simulated clock tick */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h b/c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h deleted file mode 100644 index d8eebdd3f9..0000000000 --- a/c/src/lib/libbsp/v850/gdbv850sim/include/syscall.h +++ /dev/null @@ -1,47 +0,0 @@ -/* from libgloss/v850 */ -#ifndef _SYS_SYSCALL_H_ -#define _SYS_SYSCALL_H_ - -#ifndef ASM -extern int __trap0 (int function, int p1, int p2, int p3); - -#define TRAP0(f, p1, p2, p3) __trap0(f, (int)(p1), (int)(p2), (int)(p3)) -#endif - -#define SYS_exit 1 -#define SYS_fork 2 - -#define SYS_read 3 -#define SYS_write 4 -#define SYS_open 5 -#define SYS_close 6 -#define SYS_wait4 7 -#define SYS_creat 8 -#define SYS_link 9 -#define SYS_unlink 10 -#define SYS_execv 11 -#define SYS_chdir 12 -#define SYS_mknod 14 -#define SYS_chmod 15 -#define SYS_chown 16 -#define SYS_lseek 19 -#define SYS_getpid 20 -#define SYS_isatty 21 -#define SYS_fstat 22 -#define SYS_time 23 - - -#define SYS_ARG 24 -#define SYS_stat 38 - - -#define SYS_pipe 42 -#define SYS_execve 59 -#define SYS_times 43 -#define SYS_gettimeofday 116 -#define SYS_rename 134 - -#define SYS_utime 201 /* not really a system call */ -#define SYS_wait 202 /* nor is this */ - -#endif diff --git a/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h b/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h deleted file mode 100644 index 771059a3e4..0000000000 --- a/c/src/lib/libcpu/arm/at91rm9200/irq/irq.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Interrupt handler Header file - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#endif /* __asm__ */ - -/* possible interrupt sources on the AT91RM9200 */ -#define AT91RM9200_INT_FIQ 0 -#define AT91RM9200_INT_SYSIRQ 1 -#define AT91RM9200_INT_PIOA 2 -#define AT91RM9200_INT_PIOB 3 -#define AT91RM9200_INT_PIOC 4 -#define AT91RM9200_INT_PIOD 5 -#define AT91RM9200_INT_US0 6 -#define AT91RM9200_INT_US1 7 -#define AT91RM9200_INT_US2 8 -#define AT91RM9200_INT_US3 9 -#define AT91RM9200_INT_MCI 10 -#define AT91RM9200_INT_UDP 11 -#define AT91RM9200_INT_TWI 12 -#define AT91RM9200_INT_SPI 13 -#define AT91RM9200_INT_SSC0 14 -#define AT91RM9200_INT_SSC1 15 -#define AT91RM9200_INT_SSC2 16 -#define AT91RM9200_INT_TC0 17 -#define AT91RM9200_INT_TC1 18 -#define AT91RM9200_INT_TC2 19 -#define AT91RM9200_INT_TC3 20 -#define AT91RM9200_INT_TC4 21 -#define AT91RM9200_INT_TC5 22 -#define AT91RM9200_INT_UHP 23 -#define AT91RM9200_INT_EMAC 24 -#define AT91RM9200_INT_IRQ0 25 -#define AT91RM9200_INT_IRQ1 26 -#define AT91RM9200_INT_IRQ2 27 -#define AT91RM9200_INT_IRQ3 28 -#define AT91RM9200_INT_IRQ4 28 -#define AT91RM9200_INT_IRQ5 30 -#define AT91RM9200_INT_IRQ6 31 -#define AT91RM9200_MAX_INT 32 - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (AT91RM9200_MAX_INT - 1) - -#endif /* __IRQ_H__ */ diff --git a/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h b/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h deleted file mode 100644 index 31825ca56e..0000000000 --- a/c/src/lib/libcpu/arm/lpc22xx/irq/irq.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Interrupt handler Header file - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#endif /* __asm__ */ - -/* possible interrupt sources on the LPC22xx */ -#define LPC22xx_INTERRUPT_WDINT 0 /* Watchdog int. 0 */ -#define LPC22xx_INTERRUPT_RSV0 1 /* Reserved int. 1 */ -#define LPC22xx_INTERRUPT_DBGRX 2 /* Embedded ICE DbgCommRx receive */ -#define LPC22xx_INTERRUPT_DBGTX 3 /* Embedded ICE DbgCommRx Transmit*/ -#define LPC22xx_INTERRUPT_TIMER0 4 /* Timer 0 */ -#define LPC22xx_INTERRUPT_TIMER1 5 /* Timer 1 */ -#define LPC22xx_INTERRUPT_UART0 6 /* UART 0 */ -#define LPC22xx_INTERRUPT_UART1 7 /* UART 1 */ -#define LPC22xx_INTERRUPT_PWM0 8 /* PWM */ -#define LPC22xx_INTERRUPT_I2C 9 /* I2C */ -#define LPC22xx_INTERRUPT_SPI0 10 /* SPI0 */ -#define LPC22xx_INTERRUPT_SPI1 11 /* SPI1 */ -#define LPC22xx_INTERRUPT_PLL 12 /* PLL */ -#define LPC22xx_INTERRUPT_RTC 13 /* RTC */ -#define LPC22xx_INTERRUPT_EINT0 14 /* Externel Interrupt 0 */ -#define LPC22xx_INTERRUPT_EINT1 15 /* Externel Interrupt 1 */ -#define LPC22xx_INTERRUPT_EINT2 16 /* Externel Interrupt 2 */ -#define LPC22xx_INTERRUPT_EINT3 17 /* Externel Interrupt 3 */ -#define LPC22xx_INTERRUPT_ADC 18 /* AD Converter */ -/* Following interrupt used by lpc229x */ -#define LPC22xx_INTERRUPT_CANERR 19 /* CAN LUTerr interrupt */ -#define LPC22xx_INTERRUPT_CAN1TX 20 /* CAN1 Tx interrupt */ -#define LPC22xx_INTERRUPT_CAN1RX 21 /* CAN1 Rx interrupt */ -#define LPC22xx_INTERRUPT_CAN2TX 22 /* CAN2 Tx interrupt */ -#define LPC22xx_INTERRUPT_CAN2RX 23 /* CAN2 Rx interrupt */ -#define LPC22xx_INTERRUPT_CAN3TX 24 /* CAN1 Tx interrupt */ -#define LPC22xx_INTERRUPT_CAN3RX 25 /* CAN1 Rx interrupt */ -#define LPC22xx_INTERRUPT_CAN4TX 26 /* CAN2 Tx interrupt */ -#define LPC22xx_INTERRUPT_CAN4RX 27 /* CAN2 Rx interrupt */ -#define BSP_MAX_INT 28 - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) - -#define UNDEFINED_INSTRUCTION_VECTOR_ADDR (*(u_long *)0x00000004L) -#define SOFTWARE_INTERRUPT_VECTOR_ADDR (*(u_long *)0x00000008L) -#define PREFETCH_ABORT_VECTOR_ADDR (*(u_long *)0x0000000CL) -#define DATA_ABORT_VECTOR_ADDR (*(u_long *)0x00000010L) -#define IRQ_VECTOR_ADDR (*(u_long *)0x00000018L) -#define FIQ_VECTOR_ADDR (*(u_long *)0x0000001CL) - -#define DATA_ABORT_ISR_ADDR (*(u_long *)0x00000030L) -#define IRQ_ISR_ADDR (*(u_long *)0x00000038L) -#define FIQ_ISR_ADDR (*(u_long *)0x0000003CL) - -#endif /* __IRQ_H__ */ diff --git a/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h b/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h deleted file mode 100644 index eb56fdd887..0000000000 --- a/c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Interrupt handler Header file - * - * Copyright (c) 2010 embedded brains GmbH. - * - * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#endif /* __asm__ */ - -/* possible interrupt sources on the MC9328MXL */ -#define BSP_INT_UART3_PFERR 0 -#define BSP_INT_UART3_RTS 1 -#define BSP_INT_UART3_DTR 2 -#define BSP_INT_UART3_UARTC 3 -#define BSP_INT_UART3_TX 4 -#define BSP_INT_PEN_UP 5 -#define BSP_INT_CSI 6 -#define BSP_INT_MMA_MAC 7 -#define BSP_INT_MMA 8 -#define BSP_INT_COMP 9 -#define BSP_INT_MSIRQ 10 -#define BSP_INT_GPIO_PORTA 11 -#define BSP_INT_GPIO_PORTB 12 -#define BSP_INT_GPIO_PORTC 13 -#define BSP_INT_LCDC 14 -#define BSP_INT_SIM_IRQ 15 -#define BSP_INT_SIM_DATA 16 -#define BSP_INT_RTC 17 -#define BSP_INT_RTC_SAM 18 -#define BSP_INT_UART2_PFERR 19 -#define BSP_INT_UART2_RTS 20 -#define BSP_INT_UART2_DTR 21 -#define BSP_INT_UART2_UARTC 22 -#define BSP_INT_UART2_TX 23 -#define BSP_INT_UART2_RX 24 -#define BSP_INT_UART1_PFERR 25 -#define BSP_INT_UART1_RTS 26 -#define BSP_INT_UART1_DTR 27 -#define BSP_INT_UART1_UARTC 28 -#define BSP_INT_UART1_TX 29 -#define BSP_INT_UART1_RX 30 -#define BSP_INT_RES31 31 -#define BSP_INT_RES32 32 -#define BSP_INT_PEN_DATA 33 -#define BSP_INT_PWM 34 -#define BSP_INT_MMC_IRQ 35 -#define BSP_INT_SSI2_TX 36 -#define BSP_INT_SSI2_RX 37 -#define BSP_INT_SSI2_ERR 38 -#define BSP_INT_I2C 39 -#define BSP_INT_SPI2 40 -#define BSP_INT_SPI1 41 -#define BSP_INT_SSI_TX 42 -#define BSP_INT_SSI_TX_ERR 43 -#define BSP_INT_SSI_RX 44 -#define BSP_INT_SSI_RX_ERR 45 -#define BSP_INT_TOUCH 46 -#define BSP_INT_USBD0 47 -#define BSP_INT_USBD1 48 -#define BSP_INT_USBD2 49 -#define BSP_INT_USBD3 50 -#define BSP_INT_USBD4 51 -#define BSP_INT_USBD5 52 -#define BSP_INT_USBD6 53 -#define BSP_INT_UART3_RX 54 -#define BSP_INT_BTSYS 55 -#define BSP_INT_BTTIM 56 -#define BSP_INT_BTWUI 57 -#define BSP_INT_TIMER2 58 -#define BSP_INT_TIMER1 59 -#define BSP_INT_DMA_ERR 60 -#define BSP_INT_DMA 61 -#define BSP_INT_GPIO_PORTD 62 -#define BSP_INT_WDT 63 -#define BSP_MAX_INT 64 - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) - -#endif /* __IRQ_H__ */ diff --git a/c/src/lib/libcpu/arm/pxa255/irq/irq.h b/c/src/lib/libcpu/arm/pxa255/irq/irq.h deleted file mode 100644 index a8b5d24da1..0000000000 --- a/c/src/lib/libcpu/arm/pxa255/irq/irq.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2010 embedded brains GmbH. - * - * Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com> - * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifndef __asm__ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#include <pxa255.h> - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (PRIMARY_IRQS - 1) - -#endif /* __asm__ */ - -#endif /* __IRQ_H__ */ diff --git a/c/src/lib/libcpu/arm/s3c24xx/irq/irq.h b/c/src/lib/libcpu/arm/s3c24xx/irq/irq.h deleted file mode 100644 index 8882b4362b..0000000000 --- a/c/src/lib/libcpu/arm/s3c24xx/irq/irq.h +++ /dev/null @@ -1,96 +0,0 @@ -/* irq.h - * - * Copyright (c) 2010 embedded brains GmbH. - * - * CopyRight (C) 2000 Canon Research France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Common file, merged from s3c2400/irq/irq.h and s3c2410/irq/irq.h - */ - -#ifndef _IRQ_H_ -#define _IRQ_H_ - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#include <s3c24xx.h> - -#ifdef CPU_S3C2400 - /* possible interrupt sources */ -#define BSP_EINT0 0 -#define BSP_EINT1 1 -#define BSP_EINT2 2 -#define BSP_EINT3 3 -#define BSP_EINT4 4 -#define BSP_EINT5 5 -#define BSP_EINT6 6 -#define BSP_EINT7 7 -#define BSP_INT_TICK 8 -#define BSP_INT_WDT 9 -#define BSP_INT_TIMER0 10 -#define BSP_INT_TIMER1 11 -#define BSP_INT_TIMER2 12 -#define BSP_INT_TIMER3 13 -#define BSP_INT_TIMER4 14 -#define BSP_INT_UERR01 15 -#define _res0 16 -#define BSP_INT_DMA0 17 -#define BSP_INT_DMA1 18 -#define BSP_INT_DMA2 19 -#define BSP_INT_DMA3 20 -#define BSP_INT_MMC 21 -#define BSP_INT_SPI 22 -#define BSP_INT_URXD0 23 -#define BSP_INT_URXD1 24 -#define BSP_INT_USBD 25 -#define BSP_INT_USBH 26 -#define BSP_INT_IIC 27 -#define BSP_INT_UTXD0 28 -#define BSP_INT_UTXD1 29 -#define BSP_INT_RTC 30 -#define BSP_INT_ADC 31 -#define BSP_MAX_INT 32 - -#elif defined CPU_S3C2410 - /* possible interrupt sources */ -#define BSP_EINT0 0 -#define BSP_EINT1 1 -#define BSP_EINT2 2 -#define BSP_EINT3 3 -#define BSP_EINT4_7 4 -#define BSP_EINT8_23 5 -#define BSP_nBATT_FLT 7 -#define BSP_INT_TICK 8 -#define BSP_INT_WDT 9 -#define BSP_INT_TIMER0 10 -#define BSP_INT_TIMER1 11 -#define BSP_INT_TIMER2 12 -#define BSP_INT_TIMER3 13 -#define BSP_INT_TIMER4 14 -#define BSP_INT_UART2 15 -#define BSP_INT_LCD 16 -#define BSP_INT_DMA0 17 -#define BSP_INT_DMA1 18 -#define BSP_INT_DMA2 19 -#define BSP_INT_DMA3 20 -#define BSP_INT_SDI 21 -#define BSP_INT_SPI0 22 -#define BSP_INT_UART1 23 -#define BSP_INT_USBD 25 -#define BSP_INT_USBH 26 -#define BSP_INT_IIC 27 -#define BSP_INT_UART0 28 -#define BSP_INT_SPI1 29 -#define BSP_INT_RTC 30 -#define BSP_INT_ADC 31 -#define BSP_MAX_INT 32 -#endif - -#define BSP_INTERRUPT_VECTOR_MIN 0 - -#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) - -#endif /* _IRQ_H_ */ -/* end of include file */ diff --git a/c/src/lib/libcpu/arm/shared/include/cache_.h b/c/src/lib/libcpu/arm/shared/include/cache_.h deleted file mode 100644 index a31fc11fc4..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/cache_.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - * @file - * - * @ingroup arm - * - * @brief ARM cache defines and implementation. - */ - -/* - * Copyright (c) 2009-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBCPU_ARM_CACHE__H -#define LIBCPU_ARM_CACHE__H - -#ifdef __ARM_ARCH_5TEJ__ - #include <libcpu/arm-cp15.h> - - #define CPU_DATA_CACHE_ALIGNMENT 32 - #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 - - static inline void _CPU_cache_flush_1_data_line(const void *d_addr) - { - arm_cp15_data_cache_clean_line(d_addr); - } - - static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr) - { - arm_cp15_data_cache_invalidate_line(d_addr); - } - - static inline void _CPU_cache_freeze_data(void) - { - /* TODO */ - } - - static inline void _CPU_cache_unfreeze_data(void) - { - /* TODO */ - } - - static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) - { - arm_cp15_instruction_cache_invalidate_line(d_addr); - } - - static inline void _CPU_cache_freeze_instruction(void) - { - /* TODO */ - } - - static inline void _CPU_cache_unfreeze_instruction(void) - { - /* TODO */ - } - - static inline void _CPU_cache_flush_entire_data(void) - { - arm_cp15_data_cache_test_and_clean(); - } - - static inline void _CPU_cache_invalidate_entire_data(void) - { - arm_cp15_data_cache_invalidate(); - } - - static inline void _CPU_cache_enable_data(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - ctrl = arm_cp15_get_control(); - ctrl |= ARM_CP15_CTRL_C; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } - - static inline void _CPU_cache_disable_data(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - arm_cp15_data_cache_test_and_clean_and_invalidate(); - ctrl = arm_cp15_get_control(); - ctrl &= ~ARM_CP15_CTRL_C; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } - - static inline void _CPU_cache_invalidate_entire_instruction(void) - { - arm_cp15_instruction_cache_invalidate(); - } - - static inline void _CPU_cache_enable_instruction(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - ctrl = arm_cp15_get_control(); - ctrl |= ARM_CP15_CTRL_I; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } - - static inline void _CPU_cache_disable_instruction(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - ctrl = arm_cp15_get_control(); - ctrl &= ~ARM_CP15_CTRL_I; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } -#endif - -#endif /* LIBCPU_ARM_CACHE__H */ diff --git a/c/src/lib/libcpu/arm/shared/include/mmu.h b/c/src/lib/libcpu/arm/shared/include/mmu.h deleted file mode 100644 index b82e838695..0000000000 --- a/c/src/lib/libcpu/arm/shared/include/mmu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * ARM MMU header file - */ - -/* - * Copyright (c) 2004 by Cogent Computer Systems - * Written by Jay Monkman <jtm@lopingdog.com> - */ - -#ifndef __LIBCPU_MMU_H__ -#define __LIBCPU_MMU_H__ - -#include <stdint.h> - -#define MMU_SECT_SIZE 0x100000 - -#define MMU_CACHE_NONE 0x0 -#define MMU_CACHE_BUFFERED 0x1 -#define MMU_CACHE_WTHROUGH 0x2 -#define MMU_CACHE_WBACK 0x3 - -typedef struct { - uint32_t paddr; - uint32_t vaddr; - uint32_t size; /* in MB */ - uint8_t cache_flags; -} mmu_sect_map_t; - -void mmu_init(mmu_sect_map_t *map); -void mmu_set_cpu_async_mode(void); - -#endif /* __MMU_H__ */ diff --git a/c/src/lib/libcpu/bfin/mmu/mmu.h b/c/src/lib/libcpu/bfin/mmu/mmu.h deleted file mode 100644 index d6e2ea58a9..0000000000 --- a/c/src/lib/libcpu/bfin/mmu/mmu.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Blackfin MMU Support - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow <allanh@kallisti.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -/* NOTE: this currently only implements a static table. It should be made - to handle more regions than fit in the CPLBs, with an exception handler - to do replacements as needed. This would of course require great care - to insure any storage required by the exception handler, including any - stack space, the exception handler itself, and the region descriptors - it needs to update the CPLBs, are in regions that will never be - replaced. */ - -#ifndef _mmu_h_ -#define _mmu_h_ - -#include <libcpu/mmuRegs.h> - - -#define INSTR_NOCACHE (ICPLB_DATA_CPLB_USER_RD | \ - ICPLB_DATA_CPLB_VALID) - -#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \ - ICPLB_DATA_CPLB_USER_RD | \ - ICPLB_DATA_CPLB_VALID) - -#define DATA_NOCACHE (DCPLB_DATA_CPLB_DIRTY | \ - DCPLB_DATA_CPLB_SUPV_WR | \ - DCPLB_DATA_CPLB_USER_WR | \ - DCPLB_DATA_CPLB_USER_RD | \ - DCPLB_DATA_CPLB_VALID) - -#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \ - DCPLB_DATA_CPLB_L1_CHBL | \ - DCPLB_DATA_CPLB_DIRTY | \ - DCPLB_DATA_CPLB_SUPV_WR | \ - DCPLB_DATA_CPLB_USER_WR | \ - DCPLB_DATA_CPLB_USER_RD | \ - DCPLB_DATA_CPLB_VALID) - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - struct { - void *address; - uint32_t flags; - } instruction[ICPLB_COUNT]; - struct { - void *address; - uint32_t flags; - } data[DCPLB_COUNT]; -} bfin_mmu_config_t; - - -void bfin_mmu_init(bfin_mmu_config_t *config); - - -#ifdef __cplusplus -} -#endif - -#endif /* _mmu_h_ */ - diff --git a/c/src/lib/libcpu/i386/byteorder.h b/c/src/lib/libcpu/i386/byteorder.h deleted file mode 100644 index 939e51fe84..0000000000 --- a/c/src/lib/libcpu/i386/byteorder.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_BYTEORDER_H -#define _LIBCPU_BYTEORDER_H - -static inline void st_le32(volatile uint32_t *addr, uint32_t value) -{ - *(addr)=value ; -} - -static inline uint32_t ld_le32(volatile uint32_t *addr) -{ - return(*addr); -} - -static inline void st_le16(volatile uint16_t *addr, uint16_t value) -{ - *(addr)=value ; -} - -static inline uint16_t ld_le16(volatile uint16_t *addr) -{ - return(*addr); -} - - -#endif diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h deleted file mode 100644 index 0ea939f847..0000000000 --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * or1k Cache Manager Support - */ - -#ifndef __OR1K_CACHE_H -#define __OR1K_CACHE_H - -#include <bsp/cache_.h> -#include <libcpu/cache.h> - -#endif -/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h b/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h deleted file mode 100644 index 4efa92219e..0000000000 --- a/c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h +++ /dev/null @@ -1,499 +0,0 @@ -/** - * @file - * - * @ingroup mpc55xx - * - * @brief IRQ - */ - -/* - * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_POWERPC_IRQ_H -#define LIBBSP_POWERPC_IRQ_H - -#include <rtems/irq-extension.h> -#include <rtems/irq.h> - -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* - * Interrupt numbers - */ - -#define MPC55XX_IRQ_INVALID 0x10000U -#define MPC55XX_IRQ_MIN 0U - -/* Software interrupts */ -#define MPC55XX_IRQ_SOFTWARE_MIN 0U -#define MPC55XX_IRQ_SOFTWARE_MAX 7U -#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v) -#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i) -#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U) - -#if MPC55XX_CHIP_FAMILY == 551 - #define MPC55XX_IRQ_MAX 293U - - /* eDMA */ - #define MPC55XX_IRQ_EDMA_ERROR(group) \ - ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) - #define MPC55XX_IRQ_EDMA(ch) \ - ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID) - - /* I2C */ - #define MPC55XX_IRQ_I2C(mod) \ - ((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID) - - /* SIU external interrupts */ - #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U - #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U - #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U - #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U - #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U - - /* PIT */ - #define MPC55XX_IRQ_RTI 148U - #define MPC55XX_IRQ_PIT(timer) (148U + (timer)) - - /* eTPU */ - #define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID - - /* DSPI */ - #define MPC55XX_IRQ_DSPI_BASE(mod) \ - ((mod) == 0 ? 117U : \ - ((mod) == 1 ? 122U : \ - ((mod) == 2 ? 274U : \ - ((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID)))) - - /* eMIOS */ - #define MPC55XX_IRQ_EMIOS(ch) \ - ((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID) - - /* eQADC */ - #define MPC55XX_IRQ_EQADC_BASE(mod) \ - ((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID) - - /* eSCI */ - #define MPC55XX_IRQ_ESCI(mod) \ - ((mod) == 0 ? 113U : \ - ((mod) == 1 ? 114U : \ - ((mod) == 2 ? 115U : \ - ((mod) == 3 ? 116U : \ - ((mod) == 4 ? 270U : \ - ((mod) == 5 ? 271U : \ - ((mod) == 6 ? 272U : \ - ((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID)))))))) - - /* FlexCAN */ - #define MPC55XX_IRQ_CAN_BASE(mod) \ - ((mod) == 0 ? 127U : \ - ((mod) == 1 ? 157U : \ - ((mod) == 2 ? 178U : \ - ((mod) == 3 ? 199U : \ - ((mod) == 4 ? 220U : \ - ((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID)))))) - - /* FlexRay */ - #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ - ((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID) -#elif MPC55XX_CHIP_FAMILY == 564 - #define MPC55XX_IRQ_MAX 255U - - /* eDMA */ - #define MPC55XX_IRQ_EDMA_ERROR(group) \ - ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) - #define MPC55XX_IRQ_EDMA(ch) \ - ((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID) - - /* SWT */ - #define MPC55XX_IRQ_SWT_0 28U - #define MPC55XX_IRQ_SWT_1 29U - - /* STM */ - #define MPC55XX_IRQ_STM_CHANNEL(ch) ((ch) + 30U) - - /* ECSM */ - #define MPC55XX_IRQ_ECSM_FAS 9U - #define MPC55XX_IRQ_ECSM_NCE 35U - #define MPC55XX_IRQ_ECSM_COR 36U - - /* MC */ - #define MPC55XX_IRQ_MC_ME_SAFE_MODE 51U - #define MPC55XX_IRQ_MC_ME_MODE_TRANSITION 52U - #define MPC55XX_IRQ_MC_ME_INVALID_MODE 53U - #define MPC55XX_IRQ_MC_ME_INVALID_CONFIG 54U - #define MPC55XX_IRQ_MC_RGM_FRAE 56U - - /* XOSC */ - #define MPC55XX_IRQ_XOSC 57U - - /* PIT */ - #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ - ((ch) == 3 ? 127U : ((ch) + 59U)) - - /* SIU external interrupts */ - #define MPC55XX_IRQ_SIU_EXTERNAL_0 41U - #define MPC55XX_IRQ_SIU_EXTERNAL_1 42U - #define MPC55XX_IRQ_SIU_EXTERNAL_2 43U - #define MPC55XX_IRQ_SIU_EXTERNAL_3 44U - - /* ADC */ - #define MPC55XX_IRQ_ADC_BASE(mod) \ - ((mod) == 0 ? 62U : \ - ((mod) == 1 ? 82U : MPC55XX_IRQ_INVALID)) - - /* DSPI */ - #define MPC55XX_IRQ_DSPI_BASE(mod) \ - ((mod) == 0 ? 74U : \ - ((mod) == 1 ? 94U : \ - ((mod) == 2 ? 114U : MPC55XX_IRQ_INVALID))) - - /* FlexCAN */ - #define MPC55XX_IRQ_CAN_BASE(mod) \ - ((mod) == 0 ? 65U : \ - ((mod) == 1 ? 85U : MPC55XX_IRQ_INVALID)) - - /* FlexPWM */ - #define MPC55XX_IRQ_FLEXPWM_BASE(mod) \ - ((mod) == 0 ? 179U : \ - ((mod) == 1 ? 233U : MPC55XX_IRQ_INVALID)) - - /* FlexRay */ - #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ - ((mod) == 0 ? 131U : MPC55XX_IRQ_INVALID) - - /* LINFlexD */ - #define MPC55XX_IRQ_LINFLEX_BASE(mod) \ - ((mod) == 0 ? 79U : \ - ((mod) == 1 ? 99U : MPC55XX_IRQ_INVALID)) - - /* eTimer */ - #define MPC55XX_IRQ_ETIMER_BASE(mod) \ - ((mod) == 0 ? 157U : \ - ((mod) == 1 ? 168U : \ - ((mod) == 2 ? 222U : MPC55XX_IRQ_INVALID))) - - /* CTU */ - #define MPC55XX_IRQ_CTU_MRS 193U - #define MPC55XX_IRQ_CTU_T(idx) ((idx) + 194U) - #define MPC55XX_IRQ_CTU_FIFO(idx) ((idx) + 202U) - #define MPC55XX_IRQ_CTU_ADC 206U - #define MPC55XX_IRQ_CTU_ERR 207U - - /* SEMA */ - #define MPC55XX_IRQ_SEMA_0 247U - #define MPC55XX_IRQ_SEMA_1 248U - - /* FCCU */ - #define MPC55XX_IRQ_FCCU_ALRM 250U - #define MPC55XX_IRQ_FCCU_CFG_TO 251U - #define MPC55XX_IRQ_FCCU_SC_RCC0_F 252U - #define MPC55XX_IRQ_FCCU_SC_RCC1_F 253U - - /* PMU */ - #define MPC55XX_IRQ_PMU 254U - - /* SWG */ - #define MPC55XX_IRQ_SWG 255U -#elif MPC55XX_CHIP_FAMILY == 566 - #define MPC55XX_IRQ_MAX 315U - - /* eDMA */ - #define MPC55XX_IRQ_EDMA_ERROR(group) \ - ((group) == 0 ? 10U : MPC55XX_IRQ_INVALID) - #define MPC55XX_IRQ_EDMA(ch) \ - ((unsigned) (ch) < 32U ? 11U + (ch) : MPC55XX_IRQ_INVALID) - - /* PIT */ - #define MPC55XX_IRQ_PIT_CHANNEL(ch) \ - ((unsigned) (ch) < 9U ? 148U + (ch) : MPC55XX_IRQ_INVALID) - - /* SIU external interrupts */ - #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U - #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U - #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U - #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U - - /* eMIOS */ - #define MPC55XX_IRQ_EMIOS(ch) \ - ((unsigned) (ch) < 24U ? 58U + (ch) : \ - ((unsigned) (ch) < 32U ? 262U + (ch) : MPC55XX_IRQ_INVALID)) - - /* eSCI */ - #define MPC55XX_IRQ_ESCI(mod) \ - ((unsigned) (mod) < 4U ? 113U + (mod) : \ - ((unsigned) (mod) < 8U ? 270U + (mod) : \ - ((unsigned) (mod) < 12U ? 306U + (mod) : MPC55XX_IRQ_INVALID))) -#else - #if MPC55XX_CHIP_FAMILY == 555 - #define MPC55XX_IRQ_MAX 307U - #elif MPC55XX_CHIP_FAMILY == 556 - #define MPC55XX_IRQ_MAX 360U - #elif MPC55XX_CHIP_FAMILY == 567 - #define MPC55XX_IRQ_MAX 479U - #else - #error "unsupported chip type" - #endif - - /* eDMA */ - #define MPC55XX_IRQ_EDMA_ERROR(group) \ - ((group) == 0 ? 10U : \ - ((group) == 1 ? 210U : \ - ((group) == 2 ? 425U : MPC55XX_IRQ_INVALID))) - #define MPC55XX_IRQ_EDMA(ch) \ - ((unsigned) (ch) < 32U ? 11U + (ch) : \ - ((unsigned) (ch) < 64U ? 179U + (ch) : \ - ((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID))) - - /* I2C */ - #define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID - - /* SIU external interrupts */ - #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U - #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U - #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U - #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U - #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U - - /* PIT */ - #define MPC55XX_IRQ_RTI 305U - #define MPC55XX_IRQ_PIT(ch) (301U + (ch)) - - /* eTPU */ - #define MPC55XX_IRQ_ETPU_BASE(mod) \ - ((mod) == 0 ? 67U : \ - ((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID)) - - /* DSPI */ - #define MPC55XX_IRQ_DSPI_BASE(mod) \ - ((mod) == 0 ? 275U : \ - ((mod) == 1 ? 131U : \ - ((mod) == 2 ? 136U : \ - ((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID)))) - - /* eMIOS */ - #define MPC55XX_IRQ_EMIOS(ch) \ - ((unsigned) (ch) < 16U ? 51U + (ch) : \ - ((unsigned) (ch) < 24U ? 186U + (ch) : \ - ((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID))) - - /* eQADC */ - #define MPC55XX_IRQ_EQADC_BASE(mod) \ - ((mod) == 0 ? 100U : \ - ((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID)) - - /* eSCI */ - #define MPC55XX_IRQ_ESCI(mod) \ - ((mod) == 0 ? 146U : \ - ((mod) == 1 ? 149U : \ - ((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID))) - - /* FlexCAN */ - #define MPC55XX_IRQ_CAN_BASE(mod) \ - ((mod) == 0 ? 152U : \ - ((mod) == 1 ? 280U : \ - ((mod) == 2 ? 173U : \ - ((mod) == 3 ? 308U : \ - ((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID))))) - - /* FlexRay */ - #define MPC55XX_IRQ_FLEXRAY_BASE(mod) \ - ((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID) -#endif - -#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U) - -/* ADC */ -#define MPC55XX_IRQ_ADC_EOC(mod) \ - (MPC55XX_IRQ_ADC_BASE(mod) + 0U) -#define MPC55XX_IRQ_ADC_ER(mod) \ - (MPC55XX_IRQ_ADC_BASE(mod) + 1U) -#define MPC55XX_IRQ_ADC_WD(mod) \ - (MPC55XX_IRQ_ADC_BASE(mod) + 2U) - -/* eTimer */ -#define MPC55XX_IRQ_ETIMER_TC(mod, ch) \ - (MPC55XX_IRQ_ETIMER_BASE(mod) + (ch)) -#define MPC55XX_IRQ_ETIMER_WTIF(mod) \ - (MPC55XX_IRQ_ETIMER_BASE(mod) + 8U) -#define MPC55XX_IRQ_ETIMER_RCF(mod) \ - (MPC55XX_IRQ_ETIMER_BASE(mod) + 10U) - -/* eTPU */ -#define MPC55XX_IRQ_ETPU(mod) \ - (MPC55XX_IRQ_ETPU_BASE(mod) + 0U) -#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \ - (MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch)) - -/* DSPI */ -#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U) -#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U) -#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U) -#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U) -#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U) - -/* eQADC */ -#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \ - (MPC55XX_IRQ_EQADC_BASE(mod) + 0U) -#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \ - (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U) -#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \ - (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U) -#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \ - (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U) -#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \ - (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U) -#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \ - (MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U) - -/* FlexCAN */ -#if MPC55XX_CHIP_FAMILY == 564 - #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U) - #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U) - #define MPC55XX_IRQ_CAN_BUF_0_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U) - #define MPC55XX_IRQ_CAN_BUF_4_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U) - #define MPC55XX_IRQ_CAN_BUF_8_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U) - #define MPC55XX_IRQ_CAN_BUF_12_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U) - #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U) -#else - #define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 0U) - #define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 1U) - #define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 3U) - #define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 4U) - #define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 5U) - #define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 6U) - #define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 7U) - #define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 8U) - #define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 9U) - #define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 10U) - #define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U) - #define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 12U) - #define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 13U) - #define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 14U) - #define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 15U) - #define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 16U) - #define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 17U) - #define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 18U) - #define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 19U) - #define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN_BASE(mod) + 20U) -#endif - -/* FlexPWM */ -#define MPC55XX_IRQ_FLEXPWM_RF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 0U) -#define MPC55XX_IRQ_FLEXPWM_COF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 1U) -#define MPC55XX_IRQ_FLEXPWM_CAF(mod, ch) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 3U * (ch) + 2U) -#define MPC55XX_IRQ_FLEXPWM_FFLAG(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 12U) -#define MPC55XX_IRQ_FLEXPWM_REF(mod) (MPC55XX_IRQ_FLEXPWM_BASE(mod) + 13U) - -/* FlexRay */ -#if MPC55XX_CHIP_FAMILY == 564 - #define MPC55XX_IRQ_FLEXRAY_LRNEIF_DRNEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U) - #define MPC55XX_IRQ_FLEXRAY_LRCEIF_DRCEIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U) - #define MPC55XX_IRQ_FLEXRAY_FAFAIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U) - #define MPC55XX_IRQ_FLEXRAY_FAFVIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U) - #define MPC55XX_IRQ_FLEXRAY_WUPIEF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U) - #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U) - #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U) - #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U) - #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 8U) - #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 9U) -#else - #define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U) - #define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U) - #define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U) - #define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U) - #define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U) - #define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U) - #define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U) - #define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U) -#endif - -/* LINFlexD */ -#define MPC55XX_IRQ_LINFLEX_RXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 0U) -#define MPC55XX_IRQ_LINFLEX_TXI(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 1U) -#define MPC55XX_IRQ_LINFLEX_ERR(mod) (MPC55XX_IRQ_LINFLEX_BASE(mod) + 2U) - -/* Checks */ -#define MPC55XX_IRQ_IS_VALID(v) \ - ((v) >= MPC55XX_IRQ_MIN && \ - (v) <= MPC55XX_IRQ_MAX) -#define MPC55XX_IRQ_IS_SOFTWARE(v) \ - ((v) >= MPC55XX_IRQ_SOFTWARE_MIN && \ - (v) <= MPC55XX_IRQ_SOFTWARE_MAX) - -/* - * Interrupt controller - */ - -#define MPC55XX_INTC_MIN_PRIORITY 1U -#define MPC55XX_INTC_MAX_PRIORITY 15U -#define MPC55XX_INTC_DISABLED_PRIORITY 0U -#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1) -#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1) -#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \ - ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY) - -rtems_status_code mpc55xx_interrupt_handler_install( - rtems_vector_number vector, - const char *info, - rtems_option options, - unsigned priority, - rtems_interrupt_handler handler, - void *arg -); - -rtems_status_code mpc55xx_intc_get_priority( - rtems_vector_number vector, - unsigned *priority -); - -rtems_status_code mpc55xx_intc_set_priority( - rtems_vector_number vector, - unsigned priority -); - -rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector); - -rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector); - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN - -#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX - -#ifdef BSP_INTERRUPT_HANDLER_TABLE_SIZE - #define BSP_INTERRUPT_USE_INDEX_TABLE - #define BSP_INTERRUPT_NO_HEAP_USAGE -#endif - -/** @} */ - -/* Legacy API */ -#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch) -#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch) - -#ifdef __cplusplus -}; -#endif /* __cplusplus */ - -#endif /* LIBBSP_POWERPC_IRQ_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/byteorder.h b/c/src/lib/libcpu/powerpc/shared/include/byteorder.h deleted file mode 100644 index 0654fefb58..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/byteorder.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * byteorder.h - * - * This file contains inline implementation of function to - * deal with endian conversion. - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_BYTEORDER_H -#define _LIBCPU_BYTEORDER_H - -#ifdef __cplusplus -extern "C" { -#endif - -static inline unsigned ld_le16(volatile uint16_t *addr) -{ - unsigned val; - - __asm__ volatile ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -static inline void st_le16(volatile uint16_t *addr, unsigned val) -{ - __asm__ volatile ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -static inline unsigned ld_le32(volatile uint32_t *addr) -{ - unsigned val; - - __asm__ volatile ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr)); - return val; -} - -static inline void st_le32(volatile uint32_t *addr, unsigned val) -{ - __asm__ volatile ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _LIBCPU_BYTEORDER_H */ diff --git a/c/src/lib/libcpu/powerpc/shared/include/mmu.h b/c/src/lib/libcpu/powerpc/shared/include/mmu.h deleted file mode 100644 index d3081316eb..0000000000 --- a/c/src/lib/libcpu/powerpc/shared/include/mmu.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * mmu.h - * - * PowerPC memory management structures - * - * It is a stripped down version of linux ppc file... - * - * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) - * Canon Centre Recherche France. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_MMU_H -#define _LIBCPU_MMU_H - -#ifndef ASM -/* Hardware Page Table Entry */ -typedef struct _PTE { - unsigned long v:1; /* Entry is valid */ - unsigned long vsid:24; /* Virtual segment identifier */ - unsigned long h:1; /* Hash algorithm indicator */ - unsigned long api:6; /* Abbreviated page index */ - unsigned long rpn:20; /* Real (physical) page number */ - unsigned long :3; /* Unused */ - unsigned long r:1; /* Referenced */ - unsigned long c:1; /* Changed */ - unsigned long w:1; /* Write-thru cache mode */ - unsigned long i:1; /* Cache inhibited */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page protection */ -} PTE; - -/* Values for PP (assumes Ks=0, Kp=1) */ -#define PP_RWXX 0 /* Supervisor read/write, User none */ -#define PP_RWRX 1 /* Supervisor read/write, User read */ -#define PP_RWRW 2 /* Supervisor read/write, User read/write */ -#define PP_RXRX 3 /* Supervisor read, User read */ - -/* Segment Register */ -typedef struct _SEGREG { - unsigned long t:1; /* Normal or I/O type */ - unsigned long ks:1; /* Supervisor 'key' (normally 0) */ - unsigned long kp:1; /* User 'key' (normally 1) */ - unsigned long n:1; /* No-execute */ - unsigned long :4; /* Unused */ - unsigned long vsid:24; /* Virtual Segment Identifier */ -} SEGREG; - -/* Block Address Translation (BAT) Registers */ -typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :8; /* unused */ - unsigned long w:1; - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long ks:1; /* Supervisor key (normally 0) */ - unsigned long kp:1; /* User key (normally 1) */ - unsigned long pp:2; /* Page access protections */ -} P601_BATU; - -typedef struct _BATU { /* Upper part of BAT (all except 601) */ - unsigned long bepi:15; /* Effective page index (virtual address) */ - unsigned long :4; /* Unused */ - unsigned long bl:11; /* Block size mask */ - unsigned long vs:1; /* Supervisor valid */ - unsigned long vp:1; /* User valid */ -} BATU; - -typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long v:1; /* Valid bit */ - unsigned long bl:6; /* Block size mask */ -} P601_BATL; - -typedef struct _BATL { /* Lower part of BAT (all except 601) */ - unsigned long brpn:15; /* Real page index (physical address) */ - unsigned long :10; /* Unused */ - unsigned long w:1; /* Write-thru cache */ - unsigned long i:1; /* Cache inhibit */ - unsigned long m:1; /* Memory coherence */ - unsigned long g:1; /* Guarded (MBZ in IBAT) */ - unsigned long :1; /* Unused */ - unsigned long pp:2; /* Page access protections */ -} BATL; - -typedef struct _BAT { - BATU batu; /* Upper register */ - BATL batl; /* Lower register */ -} BAT; - -typedef struct _P601_BAT { - P601_BATU batu; /* Upper register */ - P601_BATL batl; /* Lower register */ -} P601_BAT; - -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF - -/* BAT Access Protection */ -#define BPP_XX 0x00 /* No access */ -#define BPP_RX 0x01 /* Read only */ -#define BPP_RW 0x02 /* Read/write */ - -/* - * Simulated two-level MMU. This structure is used by the kernel - * to keep track of MMU mappings and is used to update/maintain - * the hardware HASH table which is really a cache of mappings. - * - * The simulated structures mimic the hardware available on other - * platforms, notably the 80x86 and 680x0. - */ - -typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ -} pte; - -#define PD_SHIFT (10+12) /* Page directory */ -#define PD_MASK 0x03FF -#define PT_SHIFT (12) /* Page Table */ -#define PT_MASK 0x03FF -#define PG_SHIFT (12) /* Page Entry */ - - -/* MMU context */ - -typedef struct _MMU_context { - SEGREG segs[16]; /* Segment registers */ - pte **pmap; /* Two-level page-map structure */ -} MMU_context; - -/* Used to set up SDR1 register */ -#define HASH_TABLE_SIZE_64K 0x00010000 -#define HASH_TABLE_SIZE_128K 0x00020000 -#define HASH_TABLE_SIZE_256K 0x00040000 -#define HASH_TABLE_SIZE_512K 0x00080000 -#define HASH_TABLE_SIZE_1M 0x00100000 -#define HASH_TABLE_SIZE_2M 0x00200000 -#define HASH_TABLE_SIZE_4M 0x00400000 -#define HASH_TABLE_MASK_64K 0x000 -#define HASH_TABLE_MASK_128K 0x001 -#define HASH_TABLE_MASK_256K 0x003 -#define HASH_TABLE_MASK_512K 0x007 -#define HASH_TABLE_MASK_1M 0x00F -#define HASH_TABLE_MASK_2M 0x01F -#define HASH_TABLE_MASK_4M 0x03F - -/* invalidate a TLB entry */ -static inline void _tlbie(unsigned long va) -{ - asm volatile ("tlbie %0" : : "r"(va)); -} - -extern void _tlbia(void); /* invalidate all TLB entries */ -#endif /* ASM */ - -/* Control/status registers for the MPC8xx. - * A write operation to these registers causes serialized access. - * During software tablewalk, the registers used perform mask/shift-add - * operations when written/read. A TLB entry is created when the Mx_RPN - * is written, and the contents of several registers are used to - * create the entry. - */ -#define MI_CTR 784 /* Instruction TLB control register */ -#define MI_GPM 0x80000000 /* Set domain manager mode */ -#define MI_PPM 0x40000000 /* Set subpage protection */ -#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MI_RESETVAL 0x00000000 /* Value of register at reset */ - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MI_AP 786 -#define MI_Ks 0x80000000 /* Should not be set */ -#define MI_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MI_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MI_EPN 787 -#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MI_EVALID 0x00000200 /* Entry is valid */ -#define MI_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the instruction TLB, it contains bits that get loaded into the - * TLB entry when the MI_RPN is written. - */ -#define MI_TWC 789 -#define MI_APG 0x000001e0 /* Access protection group (0) */ -#define MI_GUARDED 0x00000010 /* Guarded storage */ -#define MI_PSMASK 0x0000000c /* Mask of page size bits */ -#define MI_PS8MEG 0x0000000c /* 8M page size */ -#define MI_PS512K 0x00000004 /* 512K page size */ -#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MI_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the instruction TLB, using - * additional information from the MI_EPN, and MI_TWC registers. - */ -#define MI_RPN 790 - -/* Define an RPN value for mapping kernel memory to large virtual - * pages for boot initialization. This has real page number of 0, - * large page size, shared page, cache enabled, and valid. - * Also mark all subpages valid and write access. - */ -#define MI_BOOTINIT 0x000001fd - -#define MD_CTR 792 /* Data TLB control register */ -#define MD_GPM 0x80000000 /* Set domain manager mode */ -#define MD_PPM 0x40000000 /* Set subpage protection */ -#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ -#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ -#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ -#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ -#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ -#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ -#define MD_RESETVAL 0x04000000 /* Value of register at reset */ - -#define M_CASID 793 /* Address space ID (context) to match */ -#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - - -/* These are the Ks and Kp from the PowerPC books. For proper operation, - * Ks = 0, Kp = 1. - */ -#define MD_AP 794 -#define MD_Ks 0x80000000 /* Should not be set */ -#define MD_Kp 0x40000000 /* Should always be set */ - -/* The effective page number register. When read, contains the information - * about the last instruction TLB miss. When MD_RPN is written, bits in - * this register are used to create the TLB entry. - */ -#define MD_EPN 795 -#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ -#define MD_EVALID 0x00000200 /* Entry is valid */ -#define MD_ASIDMASK 0x0000000f /* ASID match value */ - /* Reset value is undefined */ - -/* The pointer to the base address of the first level page table. - * During a software tablewalk, reading this register provides the address - * of the entry associated with MD_EPN. - */ -#define M_TWB 796 -#define M_L1TB 0xfffff000 /* Level 1 table base address */ -#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ - /* Reset value is undefined */ - -/* A "level 1" or "segment" or whatever you want to call it register. - * For the data TLB, it contains bits that get loaded into the TLB entry - * when the MD_RPN is written. It is also provides the hardware assist - * for finding the PTE address during software tablewalk. - */ -#define MD_TWC 797 -#define MD_L2TB 0xfffff000 /* Level 2 table base address */ -#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ -#define MD_APG 0x000001e0 /* Access protection group (0) */ -#define MD_GUARDED 0x00000010 /* Guarded storage */ -#define MD_PSMASK 0x0000000c /* Mask of page size bits */ -#define MD_PS8MEG 0x0000000c /* 8M page size */ -#define MD_PS512K 0x00000004 /* 512K page size */ -#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ -#define MD_WT 0x00000002 /* Use writethrough page attribute */ -#define MD_SVALID 0x00000001 /* Segment entry is valid */ - /* Reset value is undefined */ - - -/* Real page number. Defined by the pte. Writing this register - * causes a TLB entry to be created for the data TLB, using - * additional information from the MD_EPN, and MD_TWC registers. - */ -#define MD_RPN 798 - -/* This is a temporary storage register that could be used to save - * a processor working register during a tablewalk. - */ -#define M_TW 799 -#endif /* _LIBCPU_MMU_H */ diff --git a/c/src/lib/libcpu/sh/sh7032/include/sci.h b/c/src/lib/libcpu/sh/sh7032/include/sci.h deleted file mode 100644 index 5653afca3c..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/include/sci.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Driver for the sh1 703x on-chip serial devices (sci) - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh_sci_h -#define _sh_sci_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Devices are set to 9600 bps, 8 databits, 1 stopbit, no - * parity and asynchronous mode by default. - * - * NOTE: - * The onboard serial devices of the SH do not support hardware - * handshake. - */ - -#define DEVSCI_DRIVER_TABLE_ENTRY \ - { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ - sh_sci_write, sh_sci_control } - -extern rtems_device_driver sh_sci_initialize( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_open( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_close( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_read( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_write( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_control( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h deleted file mode 100644 index 1045af6af8..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Bit values for the pin function controller of the Hitachi SH703X - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_pfc_h -#define _sh7_pfc_h - -#include <rtems/score/iosh7032.h> - -/* - * Port B IO Register (PBIOR) - */ -#define PBIOR PFC_PBIOR -#define PB15IOR 0x8000 -#define PB14IOR 0x4000 -#define PB13IOR 0x2000 -#define PB12IOR 0x1000 -#define PB11IOR 0x0800 -#define PB10IOR 0x0400 -#define PB9IOR 0x0200 -#define PB8IOR 0x0100 -#define PB7IOR 0x0080 -#define PB6IOR 0x0040 -#define PB5IOR 0x0020 -#define PB4IOR 0x0010 -#define PB3IOR 0x0008 -#define PB2IOR 0x0004 -#define PB1IOR 0x0002 -#define PB0IOR 0x0001 - -/* - * Port B Control Register (PBCR1) - */ -#define PBCR1 PFC_PBCR1 -#define PB15MD1 0x8000 -#define PB15MD0 0x4000 -#define PB14MD1 0x2000 -#define PB14MD0 0x1000 -#define PB13MD1 0x0800 -#define PB13MD0 0x0400 -#define PB12MD1 0x0200 -#define PB12MD0 0x0100 -#define PB11MD1 0x0080 -#define PB11MD0 0x0040 -#define PB10MD1 0x0020 -#define PB10MD0 0x0010 -#define PB9MD1 0x0008 -#define PB9MD0 0x0004 -#define PB8MD1 0x0002 -#define PB8MD0 0x0001 - -#define PB15MD PB15MD1|PB14MD0 -#define PB14MD PB14MD1|PB14MD0 -#define PB13MD PB13MD1|PB13MD0 -#define PB12MD PB12MD1|PB12MD0 -#define PB11MD PB11MD1|PB11MD0 -#define PB10MD PB10MD1|PB10MD0 -#define PB9MD PB9MD1|PB9MD0 -#define PB8MD PB8MD1|PB8MD0 - -#define PB_TXD1 PB11MD1 -#define PB_RXD1 PB10MD1 -#define PB_TXD0 PB9MD1 -#define PB_RXD0 PB8MD1 - -/* - * Port B Control Register (PBCR2) - */ -#define PBCR2 PFC_PBCR2 -#define PB7MD1 0x8000 -#define PB7MD0 0x4000 -#define PB6MD1 0x2000 -#define PB6MD0 0x1000 -#define PB5MD1 0x0800 -#define PB5MD0 0x0400 -#define PB4MD1 0x0200 -#define PB4MD0 0x0100 -#define PB3MD1 0x0080 -#define PB3MD0 0x0040 -#define PB2MD1 0x0020 -#define PB2MD0 0x0010 -#define PB1MD1 0x0008 -#define PB1MD0 0x0004 -#define PB0MD1 0x0002 -#define PB0MD0 0x0001 - -#define PB7MD PB7MD1|PB7MD0 -#define PB6MD PB6MD1|PB6MD0 -#define PB5MD PB5MD1|PB5MD0 -#define PB4MD PB4MD1|PB4MD0 -#define PB3MD PB3MD1|PB3MD0 -#define PB2MD PB2MD1|PB2MD0 -#define PB1MD PB1MD1|PB1MD0 -#define PB0MD PB0MD1|PB0MD0 - -#endif /* _sh7_pfc_h */ diff --git a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h deleted file mode 100644 index 0b80a485d3..0000000000 --- a/c/src/lib/libcpu/sh/sh7032/include/sh7_sci.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Bit values for the serial control registers of the Hitachi SH703X - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_sci_h -#define _sh7_sci_h - -#include <rtems/score/iosh7032.h> - -/* - * Serial mode register bits - */ - -#define SCI_SYNC_MODE 0x80 -#define SCI_SEVEN_BIT_DATA 0x40 -#define SCI_PARITY_ON 0x20 -#define SCI_ODD_PARITY 0x10 -#define SCI_STOP_BITS_2 0x08 -#define SCI_ENABLE_MULTIP 0x04 -#define SCI_PHI_64 0x03 -#define SCI_PHI_16 0x02 -#define SCI_PHI_4 0x01 -#define SCI_PHI_0 0x00 - -/* - * Serial register offsets, relative to SCI0_SMR or SCI1_SMR - */ - -#define SCI_SMR 0x00 -#define SCI_BRR 0x01 -#define SCI_SCR 0x02 -#define SCI_TDR 0x03 -#define SCI_SSR 0x04 -#define SCI_RDR 0x05 - -/* - * Serial control register bits - */ -#define SCI_TIE 0x80 /* Transmit interrupt enable */ -#define SCI_RIE 0x40 /* Receive interrupt enable */ -#define SCI_TE 0x20 /* Transmit enable */ -#define SCI_RE 0x10 /* Receive enable */ -#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ -#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ -#define SCI_CKE1 0x02 /* Clock enable 1 */ -#define SCI_CKE0 0x01 /* Clock enable 0 */ - -/* - * Serial status register bits - */ -#define SCI_TDRE 0x80 /* Transmit data register empty */ -#define SCI_RDRF 0x40 /* Receive data register full */ -#define SCI_ORER 0x20 /* Overrun error */ -#define SCI_FER 0x10 /* Framing error */ -#define SCI_PER 0x08 /* Parity error */ -#define SCI_TEND 0x04 /* Transmit end */ -#define SCI_MPB 0x02 /* Multiprocessor bit */ -#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ - -#endif /* _sh7_sci_h */ diff --git a/c/src/lib/libcpu/sh/sh7045/include/sci.h b/c/src/lib/libcpu/sh/sh7045/include/sci.h deleted file mode 100644 index dc34371d48..0000000000 --- a/c/src/lib/libcpu/sh/sh7045/include/sci.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Driver for the sh2 704x on-chip serial devices (sci) - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh_sci_h -#define _sh_sci_h - -#include <rtems/libio.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Devices are set to 9600 bps, 8 databits, 1 stopbit, no - * parity and asynchronous mode by default. - * - * NOTE: - * The onboard serial devices of the SH do not support hardware - * handshake. - */ - -#define DEVSCI_DRIVER_TABLE_ENTRY \ - { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \ - sh_sci_write, sh_sci_control } - -extern rtems_device_driver sh_sci_initialize( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_open( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_close( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_read( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_write( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern rtems_device_driver sh_sci_control( - rtems_device_major_number, - rtems_device_minor_number, - void * -); - -extern const rtems_termios_callbacks * sh_sci_get_termios_handlers( - bool poll -); - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h deleted file mode 100644 index b56433a9e2..0000000000 --- a/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Bit values for the pin function controller of the Hitachi SH704x - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_pfc_h -#define _sh7_pfc_h - -#include <rtems/score/iosh7045.h> - -/* - * Port A IO Registers (PAIORH, PAIORL) - * 1 => OUTPUT - * 0 => INPUT - */ -#define PAIORH PFC_PAIORH -#define PAIORL PFC_PAIORL - -/* PAIORH */ -#define PA23IOR 0x0080 -#define PA22IOR 0x0040 -#define PA21IOR 0x0020 -#define PA20IOR 0x0010 -#define PA19IOR 0x0008 -#define PA18IOR 0x0004 -#define PA17IOR 0x0002 -#define PA16IOR 0x0001 - -/* PAIORL */ -#define PA15IOR 0x8000 -#define PA14IOR 0x4000 -#define PA13IOR 0x2000 -#define PA12IOR 0x1000 -#define PA11IOR 0x0800 -#define PA10IOR 0x0400 -#define PA9IOR 0x0200 -#define PA8IOR 0x0100 -#define PA7IOR 0x0080 -#define PA6IOR 0x0040 -#define PA5IOR 0x0020 -#define PA4IOR 0x0010 -#define PA3IOR 0x0008 -#define PA2IOR 0x0004 -#define PA1IOR 0x0002 -#define PA0IOR 0x0001 - -/* - * Port A Control Registers (PACRH, PACRL1, PACRL2) - * and mode bits - */ -#define PACRH PFC_PACRH -#define PACRL1 PFC_PACRL1 -#define PACRL2 PFC_PACRL2 - -/* PACRH */ -#define PA23MD0 0x4000 -#define PA22MD0 0x1000 -#define PA21MD0 0x0400 -#define PA20MD0 0x0100 -#define PA19MD1 0x0080 -#define PA19MD0 0x0040 -#define PA18MD1 0x0020 -#define PA18MD0 0x0010 -#define PA17MD0 0x0004 -#define PA16MD0 0x0001 - -/* PACRL1 */ -#define PA15MD0 0x4000 -#define PA14MD0 0x1000 -#define PA13MD0 0x0400 -#define PA12MD0 0x0100 -#define PA11MD0 0x0040 -#define PA10MD0 0x0010 -#define PA9MD1 0x0008 -#define PA9MD0 0x0004 -#define PA8MD1 0x0002 -#define PA8MD0 0x0001 - -/* PACRL2 */ -#define PA7MD1 0x8000 -#define PA7MD0 0x4000 -#define PA6MD1 0x2000 -#define PA6MD0 0x1000 -#define PA5MD1 0x0800 -#define PA5MD0 0x0400 -#define PA4MD0 0x0100 -#define PA3MD0 0x0040 -#define PA2MD1 0x0020 -#define PA2MD0 0x0010 -#define PA1MD0 0x0004 -#define PA0MD0 0x0001 - -#define PA_TXD1 PA4MD0 -#define PA_RXD1 PA3MD0 -#define PA_TXD0 PA1MD0 -#define PA_RXD0 PA0MD0 - -/* - * Port B IO Register (PBIOR) - */ -#define PBIOR PFC_PBIOR -#define PB15IOR 0x8000 -#define PB14IOR 0x4000 -#define PB13IOR 0x2000 -#define PB12IOR 0x1000 -#define PB11IOR 0x0800 -#define PB10IOR 0x0400 -#define PB9IOR 0x0200 -#define PB8IOR 0x0100 -#define PB7IOR 0x0080 -#define PB6IOR 0x0040 -#define PB5IOR 0x0020 -#define PB4IOR 0x0010 -#define PB3IOR 0x0008 -#define PB2IOR 0x0004 -#define PB1IOR 0x0002 -#define PB0IOR 0x0001 - -/* - * Port B Control Register (PBCR1) - */ -#define PBCR1 PFC_PBCR1 -#define PB15MD1 0x8000 -#define PB15MD0 0x4000 -#define PB14MD1 0x2000 -#define PB14MD0 0x1000 -#define PB13MD1 0x0800 -#define PB13MD0 0x0400 -#define PB12MD1 0x0200 -#define PB12MD0 0x0100 -#define PB11MD1 0x0080 -#define PB11MD0 0x0040 -#define PB10MD1 0x0020 -#define PB10MD0 0x0010 -#define PB9MD1 0x0008 -#define PB9MD0 0x0004 -#define PB8MD1 0x0002 -#define PB8MD0 0x0001 - -#define PB15MD PB15MD1|PB14MD0 -#define PB14MD PB14MD1|PB14MD0 -#define PB13MD PB13MD1|PB13MD0 -#define PB12MD PB12MD1|PB12MD0 -#define PB11MD PB11MD1|PB11MD0 -#define PB10MD PB10MD1|PB10MD0 -#define PB9MD PB9MD1|PB9MD0 -#define PB8MD PB8MD1|PB8MD0 - -#define PB_TXD1 PB11MD1 -#define PB_RXD1 PB10MD1 -#define PB_TXD0 PB9MD1 -#define PB_RXD0 PB8MD1 - -/* - * Port B Control Register (PBCR2) - */ -#define PBCR2 PFC_PBCR2 -#define PB7MD1 0x8000 -#define PB7MD0 0x4000 -#define PB6MD1 0x2000 -#define PB6MD0 0x1000 -#define PB5MD1 0x0800 -#define PB5MD0 0x0400 -#define PB4MD1 0x0200 -#define PB4MD0 0x0100 -#define PB3MD1 0x0080 -#define PB3MD0 0x0040 -#define PB2MD1 0x0020 -#define PB2MD0 0x0010 -#define PB1MD1 0x0008 -#define PB1MD0 0x0004 -#define PB0MD1 0x0002 -#define PB0MD0 0x0001 - -#define PB7MD PB7MD1|PB7MD0 -#define PB6MD PB6MD1|PB6MD0 -#define PB5MD PB5MD1|PB5MD0 -#define PB4MD PB4MD1|PB4MD0 -#define PB3MD PB3MD1|PB3MD0 -#define PB2MD PB2MD1|PB2MD0 -#define PB1MD PB1MD1|PB1MD0 -#define PB0MD PB0MD1|PB0MD0 - -#endif /* _sh7_pfc_h */ diff --git a/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h b/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h deleted file mode 100644 index 7218313704..0000000000 --- a/c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Bit values for the serial control registers of the Hitachi SH704X - * - * From Hitachi tutorials - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sh7_sci_h -#define _sh7_sci_h - -#include <rtems/score/iosh7045.h> - -/* - * Serial mode register bits - */ - -#define SCI_SYNC_MODE 0x80 -#define SCI_SEVEN_BIT_DATA 0x40 -#define SCI_PARITY_ON 0x20 -#define SCI_ODD_PARITY 0x10 -#define SCI_STOP_BITS_2 0x08 -#define SCI_ENABLE_MULTIP 0x04 -#define SCI_PHI_64 0x03 -#define SCI_PHI_16 0x02 -#define SCI_PHI_4 0x01 -#define SCI_PHI_0 0x00 - -/* - * Serial register offsets, relative to SCI0_SMR or SCI1_SMR - */ - -#define SCI_SMR 0x00 -#define SCI_BRR 0x01 -#define SCI_SCR 0x02 -#define SCI_TDR 0x03 -#define SCI_SSR 0x04 -#define SCI_RDR 0x05 - -/* - * Serial control register bits - */ -#define SCI_TIE 0x80 /* Transmit interrupt enable */ -#define SCI_RIE 0x40 /* Receive interrupt enable */ -#define SCI_TE 0x20 /* Transmit enable */ -#define SCI_RE 0x10 /* Receive enable */ -#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */ -#define SCI_TEIE 0x04 /* Transmit end interrupt enable */ -#define SCI_CKE1 0x02 /* Clock enable 1 */ -#define SCI_CKE0 0x01 /* Clock enable 0 */ - -/* - * Serial status register bits - */ -#define SCI_TDRE 0x80 /* Transmit data register empty */ -#define SCI_RDRF 0x40 /* Receive data register full */ -#define SCI_ORER 0x20 /* Overrun error */ -#define SCI_FER 0x10 /* Framing error */ -#define SCI_PER 0x08 /* Parity error */ -#define SCI_TEND 0x04 /* Transmit end */ -#define SCI_MPB 0x02 /* Multiprocessor bit */ -#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */ - -/* - * INTC Priority Settings - */ - -#define SCI0_IPMSK 0x00F0 -#define SCI0_LOWIP 0x0010 -#define SCI1_IPMSK 0x000F -#define SCI1_LOWIP 0x0001 - -#endif /* _sh7_sci_h */ diff --git a/c/src/lib/libcpu/sparc/include/libcpu/byteorder.h b/c/src/lib/libcpu/sparc/include/libcpu/byteorder.h deleted file mode 100644 index 10b4239480..0000000000 --- a/c/src/lib/libcpu/sparc/include/libcpu/byteorder.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * byteorder.h - Endian conversion for SPARC. SPARC is big endian only. - * - * COPYRIGHT (c) 2011 - * Aeroflex Gaisler. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _LIBCPU_BYTEORDER_H -#define _LIBCPU_BYTEORDER_H - -#include <rtems/system.h> -#include <rtems/score/cpu.h> - -#ifdef __cplusplus -extern "C" { -#endif - -RTEMS_INLINE_ROUTINE uint16_t ld_le16(volatile uint16_t *addr) -{ - return CPU_swap_u16(*addr); -} - -RTEMS_INLINE_ROUTINE void st_le16(volatile uint16_t *addr, uint16_t val) -{ - *addr = CPU_swap_u16(val); -} - -RTEMS_INLINE_ROUTINE uint32_t ld_le32(volatile uint32_t *addr) -{ - return CPU_swap_u32(*addr); -} - -RTEMS_INLINE_ROUTINE void st_le32(volatile uint32_t *addr, uint32_t val) -{ - *addr = CPU_swap_u32(val); -} - -RTEMS_INLINE_ROUTINE uint16_t ld_be16(volatile uint16_t *addr) -{ - return *addr; -} - -RTEMS_INLINE_ROUTINE void st_be16(volatile uint16_t *addr, uint16_t val) -{ - *addr = val; -} - -RTEMS_INLINE_ROUTINE uint32_t ld_be32(volatile uint32_t *addr) -{ - return *addr; -} - -RTEMS_INLINE_ROUTINE void st_be32(volatile uint32_t *addr, uint32_t val) -{ - *addr = val; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/libdl/include/arch/arm/machine/elf_machdep.h b/cpukit/libdl/include/arch/arm/machine/elf_machdep.h deleted file mode 100644 index 78c88b5af8..0000000000 --- a/cpukit/libdl/include/arch/arm/machine/elf_machdep.h +++ /dev/null @@ -1,131 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.8 2009/05/30 05:56:52 skrll Exp $ */ - -#if defined(__ARMEB__) -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#else -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB -#endif - -#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ -#define ELF64_MACHDEP_ID_CASES \ - /* no 64-bit ELF machine types supported */ - -/* Processor specific flags for the ELF header e_flags field. */ -#define EF_ARM_RELEXEC 0x00000001 -#define EF_ARM_HASENTRY 0x00000002 -#define EF_ARM_INTERWORK 0x00000004 /* GNU binutils 000413 */ -#define EF_ARM_SYMSARESORTED 0x00000004 /* ARM ELF A08 */ -#define EF_ARM_APCS_26 0x00000008 /* GNU binutils 000413 */ -#define EF_ARM_DYNSYMSUSESEGIDX 0x00000008 /* ARM ELF B01 */ -#define EF_ARM_APCS_FLOAT 0x00000010 /* GNU binutils 000413 */ -#define EF_ARM_MAPSYMSFIRST 0x00000010 /* ARM ELF B01 */ -#define EF_ARM_PIC 0x00000020 -#define EF_ARM_ALIGN8 0x00000040 /* 8-bit structure alignment. */ -#define EF_ARM_NEW_ABI 0x00000080 -#define EF_ARM_OLD_ABI 0x00000100 -#define EF_ARM_SOFT_FLOAT 0x00000200 -#define EF_ARM_EABIMASK 0xff000000 - -#define ELF32_MACHDEP_ID_CASES \ - case EM_ARM: \ - break; - -#define ELF32_MACHDEP_ID EM_ARM - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -/* Processor specific relocation types */ - -#define R_ARM_NONE 0 -#define R_ARM_PC24 1 -#define R_ARM_ABS32 2 -#define R_ARM_REL32 3 -#define R_ARM_PC13 4 -#define R_ARM_ABS16 5 -#define R_ARM_ABS12 6 -#define R_ARM_THM_ABS5 7 -#define R_ARM_ABS8 8 -#define R_ARM_SBREL32 9 -#define R_ARM_THM_CALL 10 -#define R_ARM_THM_PC8 11 -#define R_ARM_AMP_VCALL9 12 -#define R_ARM_SWI24 13 -#define R_ARM_THM_SWI8 14 -#define R_ARM_XPC25 15 -#define R_ARM_THM_XPC22 16 - -/* TLS relocations */ -#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ -#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ -#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ - -/* 20-31 are reserved for ARM Linux. */ -#define R_ARM_COPY 20 -#define R_ARM_GLOB_DAT 21 -#define R_ARM_JUMP_SLOT 22 -#define R_ARM_RELATIVE 23 -#define R_ARM_GOTOFF 24 -#define R_ARM_GOTPC 25 -#define R_ARM_GOT32 26 -#define R_ARM_PLT32 27 -#define R_ARM_CALL 28 -#define R_ARM_JUMP24 29 -#define R_ARM_THM_JUMP24 30 -#define R_ARM_BASE_ABS 31 - -#define R_ARM_ALU_PCREL_7_0 32 -#define R_ARM_ALU_PCREL_15_8 33 -#define R_ARM_ALU_PCREL_23_15 34 -#define R_ARM_ALU_SBREL_11_0 35 -#define R_ARM_ALU_SBREL_19_12 36 -#define R_ARM_ALU_SBREL_27_20 37 -#define R_ARM_V4BX 40 -#define R_ARM_PREL31 41 - -#define R_ARM_MOVW_ABS_NC 43 -#define R_ARM_MOVT_ABS 44 - -#define R_ARM_THM_MOVW_ABS_NC 47 -#define R_ARM_THM_MOVT_ABS 48 - -#define R_ARM_THM_JUMP19 51 - -/* 96-111 are reserved to G++. */ -#define R_ARM_GNU_VTENTRY 100 -#define R_ARM_GNU_VTINHERIT 101 -#define R_ARM_THM_JUMP11 102 -#define R_ARM_THM_JUMP8 103 - -/* More TLS relocations */ -#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic */ -#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic */ -#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS */ -#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of */ -#define R_ARM_TLS_LE32 108 -#define R_ARM_TLS_LDO12 109 -#define R_ARM_TLS_LE12 110 -#define R_ARM_TLS_IE12GP 111 - -/* 112-127 are reserved for private experiments. */ - -#define R_ARM_RXPC25 249 -#define R_ARM_RSBREL32 250 -#define R_ARM_THM_RPC22 251 -#define R_ARM_RREL32 252 -#define R_ARM_RABS32 253 -#define R_ARM_RPC24 254 -#define R_ARM_RBASE 255 - -#define R_TYPE(name) __CONCAT(R_ARM_,name) - -/* Processor specific program header flags */ -#define PF_ARM_SB 0x10000000 -#define PF_ARM_PI 0x20000000 -#define PF_ARM_ENTRY 0x80000000 - -/* Processor specific section header flags */ -#define SHF_ENTRYSECT 0x10000000 -#define SHF_COMDEF 0x80000000 - -/* Processor specific symbol types */ -#define STT_ARM_TFUNC STT_LOPROC diff --git a/cpukit/libdl/include/arch/i386/machine/elf_machdep.h b/cpukit/libdl/include/arch/i386/machine/elf_machdep.h deleted file mode 100644 index 442c561a9c..0000000000 --- a/cpukit/libdl/include/arch/i386/machine/elf_machdep.h +++ /dev/null @@ -1,63 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.10 2009/05/30 05:56:52 skrll Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_386: \ - case EM_486: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ -#define ELF64_MACHDEP_ID_CASES \ - /* no 64-bit ELF machine types supported */ - -#define ELF32_MACHDEP_ID EM_386 - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -/* i386 relocations */ -#define R_386_NONE 0 -#define R_386_32 1 -#define R_386_PC32 2 -#define R_386_GOT32 3 -#define R_386_PLT32 4 -#define R_386_COPY 5 -#define R_386_GLOB_DAT 6 -#define R_386_JMP_SLOT 7 -#define R_386_RELATIVE 8 -#define R_386_GOTOFF 9 -#define R_386_GOTPC 10 - -/* TLS relocations */ -#define R_386_TLS_TPOFF 14 -#define R_386_TLS_IE 15 -#define R_386_TLS_GOTIE 16 -#define R_386_TLS_LE 17 -#define R_386_TLS_GD 18 -#define R_386_TLS_LDM 19 - -/* The following relocations are GNU extensions. */ -#define R_386_16 20 -#define R_386_PC16 21 -#define R_386_8 22 -#define R_386_PC8 23 - -/* More TLS relocations */ -#define R_386_TLS_GD_32 24 -#define R_386_TLS_GD_PUSH 25 -#define R_386_TLS_GD_CALL 26 -#define R_386_TLS_GD_POP 27 -#define R_386_TLS_LDM_32 28 -#define R_386_TLS_LDM_PUSH 29 -#define R_386_TLS_LDM_CALL 30 -#define R_386_TLS_LDM_POP 31 -#define R_386_TLS_LDO_32 32 -#define R_386_TLS_IE_32 33 -#define R_386_TLS_LE_32 34 -#define R_386_TLS_DTPMOD32 35 -#define R_386_TLS_DTPOFF32 36 -#define R_386_TLS_TPOFF32 37 -#define R_386_TLS_GOTDESC 39 -#define R_386_TLS_DESC_CALL 40 -#define R_386_TLS_DESC 41 - -#define R_TYPE(name) __CONCAT(R_386_,name) diff --git a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h b/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h deleted file mode 100644 index 3f531cf901..0000000000 --- a/cpukit/libdl/include/arch/m32r/machine/elf_machdep.h +++ /dev/null @@ -1,39 +0,0 @@ -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB - -#define ELF32_MACHDEP_ID_CASES \ - case EM_M32R: \ - break; - -#define ELF32_MACHDEP_ID EM_M32R - -#define ARCH_ELFSIZE 32 - -#define R_M32R_NONE 0 -/*-----------OLD TYPE-------------*/ -#define R_M32R_16 1 -#define R_M32R_32 2 -#define R_M32R_24 3 -#define R_M32R_10_PCREL 4 -#define R_M32R_18_PCREL 5 -#define R_M32R_26_PCREL 6 -#define R_M32R_HI16_ULO 7 -#define R_M32R_HI16_SLO 8 -#define R_M32R_LO16 9 -#define R_M32R_SDA16 10 -#define R_M32R_GNU_VTINHERIT 11 -#define R_M32R_GNU_VTENTRY 12 -/*--------------------------------*/ - -#define R_M32R_16_RELA 33 -#define R_M32R_32_RELA 34 -#define R_M32R_24_RELA 35 -#define R_M32R_18_PCREL_RELA 37 -#define R_M32R_26_PCREL_RELA 38 -#define R_M32R_HI16_ULO_RELA 39 -#define R_M32R_HI16_SLO_RELA 40 -#define R_M32R_LO16_RELA 41 -#define R_M32R_SDA16_RELA 42 -#define R_M32R_RELA_GNU_VTINHERIT 43 -#define R_M32R_RELA_GNU_VTENTRY 44 - -#define R_TYPE(name) __CONCAT(R_M32R_,name) diff --git a/cpukit/libdl/include/arch/m68k/machine/elf_machdep.h b/cpukit/libdl/include/arch/m68k/machine/elf_machdep.h deleted file mode 100644 index 9a987c69b5..0000000000 --- a/cpukit/libdl/include/arch/m68k/machine/elf_machdep.h +++ /dev/null @@ -1,47 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.7 2002/01/28 21:34:48 thorpej Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_68K: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS XXX /* break compilation */ -#define ELF64_MACHDEP_ID_CASES \ - /* no 64-bit ELF machine types supported */ - -#define ELF32_MACHDEP_ID EM_68K - -/* - * Machine-dependent ELF flags. These are defined by the GNU tools. - */ -#define EF_CPU32 0x00810000 -#define EF_M68000 0x01000000 - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -/* m68k relocation types */ -#define R_68K_NONE 0 -#define R_68K_32 1 -#define R_68K_16 2 -#define R_68K_8 3 -#define R_68K_PC32 4 -#define R_68K_PC16 5 -#define R_68K_PC8 6 -#define R_68K_GOT32 7 -#define R_68K_GOT16 8 -#define R_68K_GOT8 9 -#define R_68K_GOT32O 10 -#define R_68K_GOT16O 11 -#define R_68K_GOT8O 12 -#define R_68K_PLT32 13 -#define R_68K_PLT16 14 -#define R_68K_PLT8 15 -#define R_68K_PLT32O 16 -#define R_68K_PLT16O 17 -#define R_68K_PLT8O 18 -#define R_68K_COPY 19 -#define R_68K_GLOB_DAT 20 -#define R_68K_JMP_SLOT 21 -#define R_68K_RELATIVE 22 - -#define R_TYPE(name) __CONCAT(R_68K_,name) diff --git a/cpukit/libdl/include/arch/mips/machine/elf_machdep.h b/cpukit/libdl/include/arch/mips/machine/elf_machdep.h deleted file mode 100644 index 26700ce4ce..0000000000 --- a/cpukit/libdl/include/arch/mips/machine/elf_machdep.h +++ /dev/null @@ -1,199 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */ - -#ifndef _MIPS_ELF_MACHDEP_H_ -#define _MIPS_ELF_MACHDEP_H_ - -#ifdef _LP64 -#define ARCH_ELFSIZE 64 /* MD native binary size */ -#else -#define ARCH_ELFSIZE 32 /* MD native binary size */ -#endif - -#if ARCH_ELFSIZE == 32 -#define ELF32_MACHDEP_ID_CASES \ - case EM_MIPS: \ - break; - -#define ELF32_MACHDEP_ID EM_MIPS - -#elif ARCH_ELFSIZE == 64 -#define ELF64_MACHDEP_ID_CASES \ - case EM_MIPS: \ - break; - -#define ELF64_MACHDEP_ID EM_MIPS - -#endif - - -/* mips relocs. */ - -#define R_MIPS_NONE 0 -#define R_MIPS_16 1 -#define R_MIPS_32 2 -#define R_MIPS_REL32 3 -#define R_MIPS_REL R_MIPS_REL32 -#define R_MIPS_26 4 -#define R_MIPS_HI16 5 /* high 16 bits of symbol value */ -#define R_MIPS_LO16 6 /* low 16 bits of symbol value */ -#define R_MIPS_GPREL16 7 /* GP-relative reference */ -#define R_MIPS_LITERAL 8 /* Reference to literal section */ -#define R_MIPS_GOT16 9 /* Reference to global offset table */ -#define R_MIPS_GOT R_MIPS_GOT16 -#define R_MIPS_PC16 10 /* 16 bit PC relative reference */ -#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */ -#define R_MIPS_CALL R_MIPS_CALL16 -#define R_MIPS_GPREL32 12 - -/* 13, 14, 15 are not defined at this point. */ -#define R_MIPS_UNUSED1 13 -#define R_MIPS_UNUSED2 14 -#define R_MIPS_UNUSED3 15 - -/* - * The remaining relocs are apparently part of the 64-bit Irix ELF ABI. - */ -#define R_MIPS_SHIFT5 16 -#define R_MIPS_SHIFT6 17 - -#define R_MIPS_64 18 -#define R_MIPS_GOT_DISP 19 -#define R_MIPS_GOT_PAGE 20 -#define R_MIPS_GOT_OFST 21 -#define R_MIPS_GOT_HI16 22 -#define R_MIPS_GOT_LO16 23 -#define R_MIPS_SUB 24 -#define R_MIPS_INSERT_A 25 -#define R_MIPS_INSERT_B 26 -#define R_MIPS_DELETE 27 -#define R_MIPS_HIGHER 28 -#define R_MIPS_HIGHEST 29 -#define R_MIPS_CALL_HI16 30 -#define R_MIPS_CALL_LO16 31 -#define R_MIPS_SCN_DISP 32 -#define R_MIPS_REL16 33 -#define R_MIPS_ADD_IMMEDIATE 34 -#define R_MIPS_PJUMP 35 -#define R_MIPS_RELGOT 36 -#define R_MIPS_JALR 37 -/* TLS relocations */ - -#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ -#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ -#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ -#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ -#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ -#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ -#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ -#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ -#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ -#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ -#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ -#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ -#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ - -#define R_MIPS_max 51 - -#define R_TYPE(name) __CONCAT(R_MIPS_,name) - -#define R_MIPS16_min 100 -#define R_MIPS16_26 100 -#define R_MIPS16_GPREL 101 -#define R_MIPS16_GOT16 102 -#define R_MIPS16_CALL16 103 -#define R_MIPS16_HI16 104 -#define R_MIPS16_LO16 105 -#define R_MIPS16_max 106 - - -/* mips dynamic tags */ - -#define DT_MIPS_RLD_VERSION 0x70000001 -#define DT_MIPS_TIME_STAMP 0x70000002 -#define DT_MIPS_ICHECKSUM 0x70000003 -#define DT_MIPS_IVERSION 0x70000004 -#define DT_MIPS_FLAGS 0x70000005 -#define DT_MIPS_BASE_ADDRESS 0x70000006 -#define DT_MIPS_CONFLICT 0x70000008 -#define DT_MIPS_LIBLIST 0x70000009 -#define DT_MIPS_CONFLICTNO 0x7000000b -#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */ -#define DT_MIPS_LIBLISTNO 0x70000010 -#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */ -#define DT_MIPS_UNREFEXTNO 0x70000012 -#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */ -#define DT_MIPS_HIPAGENO 0x70000014 -#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */ - -/* - * ELF Flags - */ -#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */ -#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */ -#define EF_MIPS_ABI2 0x00000020 /* N32 */ - -#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */ -#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */ -#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */ - -#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */ -#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */ -#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */ -#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */ -#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */ -#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */ -#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */ -#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */ -#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */ -#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */ - -#define EF_MIPS_ABI 0x0000f000 -#define EF_MIPS_ABI_O32 0x00001000 -#define EF_MIPS_ABI_O64 0x00002000 -#define EF_MIPS_ABI_EABI32 0x00003000 -#define EF_MIPS_ABI_EABI64 0x00004000 - -#if defined(__MIPSEB__) -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB -#elif defined(__MIPSEL__) -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB -#elif !defined(HAVE_NBTOOL_CONFIG_H) -#error neither __MIPSEL__ nor __MIPSEB__ are defined. -#endif - -#ifdef _KERNEL -#ifdef _KERNEL_OPT -#include "opt_compat_netbsd.h" -#endif -#ifdef COMPAT_16 -/* - * Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable. - * Tell the kernel ELF exec code not to try relocating the interpreter - * for dynamically-linked ELF binaries. - */ -#define ELF_INTERP_NON_RELOCATABLE -#endif /* COMPAT_16 */ - -/* - * We need to be able to include the ELF header so we can pick out the - * ABI being used. - */ -#ifdef ELFSIZE -#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe) -#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup) -#endif - -struct exec_package; - -int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *, - vaddr_t *); -void coredump_elf32_setup(struct lwp *, void *); - -int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *, - vaddr_t *); -void coredump_elf64_setup(struct lwp *, void *); -#endif /* _KERNEL */ - -#endif /* _MIPS_ELF_MACHDEP_H_ */ diff --git a/cpukit/libdl/include/arch/moxie/machine/elf_machdep.h b/cpukit/libdl/include/arch/moxie/machine/elf_machdep.h deleted file mode 100644 index 3f0df23cdc..0000000000 --- a/cpukit/libdl/include/arch/moxie/machine/elf_machdep.h +++ /dev/null @@ -1,15 +0,0 @@ -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB - -#define ELF32_MACHDEP_ID_CASES \ - case EM_MOXIE: \ - break; - -#define ELF32_MACHDEP_ID EM_MOXIE - -#define ARCH_ELFSIZE 32 - -#define R_MOXIE_NONE 0 -#define R_MOXIE_32 1 -#define R_MOXIE_PCREL10 2 - -#define R_TYPE(name) __CONCAT(R_MOXIE_,name) diff --git a/cpukit/libdl/include/arch/powerpc/machine/elf_machdep.h b/cpukit/libdl/include/arch/powerpc/machine/elf_machdep.h deleted file mode 100644 index f0fdb3f33b..0000000000 --- a/cpukit/libdl/include/arch/powerpc/machine/elf_machdep.h +++ /dev/null @@ -1,105 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.9 2011/01/15 10:00:07 matt Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_PPC: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF64_MACHDEP_ID_CASES \ - case EM_PPC64: \ - break; - -#define ELF32_MACHDEP_ID EM_PPC -#define ELF64_MACHDEP_ID EM_PPC64 - -#ifdef _LP64 -#define ARCH_ELFSIZE 64 /* MD native binary size */ -#else -#define ARCH_ELFSIZE 32 /* MD native binary size */ -#endif - -/* Specify the value of _GLOBAL_OFFSET_TABLE_ */ -#define DT_PPC_GOT DT_LOPROC - -#define R_PPC_NONE 0 -#define R_PPC_32 1 -#define R_PPC_24 2 -#define R_PPC_16 3 -#define R_PPC_16_LO 4 -#define R_PPC_16_HI 5 /* R_PPC_ADDIS */ -#define R_PPC_16_HA 6 -#define R_PPC_14 7 -#define R_PPC_14_TAKEN 8 -#define R_PPC_14_NTAKEN 9 -#define R_PPC_REL24 10 /* R_PPC_BRANCH */ -#define R_PPC_REL14 11 -#define R_PPC_REL14_TAKEN 12 -#define R_PPC_REL14_NTAKEN 13 -#define R_PPC_GOT16 14 -#define R_PPC_GOT16_LO 15 -#define R_PPC_GOT16_HI 16 -#define R_PPC_GOT16_HA 17 -#define R_PPC_PLT24 18 -#define R_PPC_COPY 19 -#define R_PPC_GLOB_DAT 20 -#define R_PPC_JMP_SLOT 21 -#define R_PPC_RELATIVE 22 -#define R_PPC_LOCAL24PC 23 -#define R_PPC_U32 24 -#define R_PPC_U16 25 -#define R_PPC_REL32 26 -#define R_PPC_PLT32 27 -#define R_PPC_PLTREL32 28 -#define R_PPC_PLT16_LO 29 -#define R_PPC_PLT16_HI 30 -#define R_PPC_PLT16_HA 31 -#define R_PPC_SDAREL16 32 -#define R_PPC_SECTOFF 33 -#define R_PPC_SECTOFF_LO 34 -#define R_PPC_SECTOFF_HI 35 -#define R_PPC_SECTOFF_HA 36 -#define R_PPC_ADDR30 37 - -/* TLS relocations */ -#define R_PPC_TLS 67 - -#define R_PPC_DTPMOD32 68 -#define R_PPC_TPREL16 69 -#define R_PPC_TPREL16_LO 70 -#define R_PPC_TPREL16_HI 71 -#define R_PPC_TPREL16_HA 72 -#define R_PPC_TPREL32 73 -#define R_PPC_DTPREL16 74 -#define R_PPC_DTPREL16_LO 75 -#define R_PPC_DTPREL16_HI 76 -#define R_PPC_DTPREL16_HA 77 -#define R_PPC_DTPREL32 78 - -#define R_PPC_GOT_TLSGD16 79 -#define R_PPC_GOT_TLSGD16_LO 80 -#define R_PPC_GOT_TLSGD16_HI 81 -#define R_PPC_GOT_TLSGD16_HA 82 -#define R_PPC_GOT_TLSLD16 83 -#define R_PPC_GOT_TLSLD16_LO 84 -#define R_PPC_GOT_TLSLD16_HI 85 -#define R_PPC_GOT_TLSLD16_HA 86 - -#define R_PPC_GOT_TPREL16 87 -#define R_PPC_GOT_TPREL16_LO 88 -#define R_PPC_GOT_TPREL16_HI 89 -#define R_PPC_GOT_TPREL16_HA 90 -#define R_PPC_GOT_DTPREL16 91 -#define R_PPC_GOT_DTPREL16_LO 92 -#define R_PPC_GOT_DTPREL16_HI 93 -#define R_PPC_GOT_DTPREL16_HA 94 -#define R_PPC_TLSGD 95 -#define R_PPC_TLSLD 96 - -/* Used for the secure-plt PIC code sequences */ -#define R_PPC_REL16 249 -#define R_PPC_REL16_LO 250 -#define R_PPC_REL16_HI 251 -#define R_PPC_REL16_HA 252 - -#define R_TYPE(name) __CONCAT(R_PPC_,name) diff --git a/cpukit/libdl/include/arch/sparc/machine/elf_machdep.h b/cpukit/libdl/include/arch/sparc/machine/elf_machdep.h deleted file mode 100644 index e8f2b630c2..0000000000 --- a/cpukit/libdl/include/arch/sparc/machine/elf_machdep.h +++ /dev/null @@ -1,92 +0,0 @@ -/* $NetBSD: elf_machdep.h,v 1.7 2009/05/30 05:56:53 skrll Exp $ */ - -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF32_MACHDEP_ID_CASES \ - case EM_SPARC: \ - case EM_SPARC32PLUS: \ - break; - -#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB -#define ELF64_MACHDEP_ID_CASES \ - case EM_SPARC32PLUS: \ - case EM_SPARCV9: \ - /* no 64-bit ELF machine types supported */ - -#define ELF32_MACHDEP_ID EM_SPARC /* XXX right? */ - -#define ARCH_ELFSIZE 32 /* MD native binary size */ - -#define R_SPARC_NONE 0 -#define R_SPARC_8 1 -#define R_SPARC_16 2 -#define R_SPARC_32 3 -#define R_SPARC_DISP8 4 -#define R_SPARC_DISP16 5 -#define R_SPARC_DISP32 6 -#define R_SPARC_WDISP30 7 -#define R_SPARC_WDISP22 8 -#define R_SPARC_HI22 9 -#define R_SPARC_22 10 -#define R_SPARC_13 11 -#define R_SPARC_LO10 12 -#define R_SPARC_GOT10 13 -#define R_SPARC_GOT13 14 -#define R_SPARC_GOT22 15 -#define R_SPARC_PC10 16 -#define R_SPARC_PC22 17 -#define R_SPARC_WPLT30 18 -#define R_SPARC_COPY 19 -#define R_SPARC_GLOB_DAT 20 -#define R_SPARC_JMP_SLOT 21 -#define R_SPARC_RELATIVE 22 -#define R_SPARC_UA32 23 -#define R_SPARC_PLT32 24 -#define R_SPARC_HIPLT22 25 -#define R_SPARC_LOPLT10 26 -#define R_SPARC_PCPLT32 27 -#define R_SPARC_PCPLT22 28 -#define R_SPARC_PCPLT10 29 -#define R_SPARC_10 30 -#define R_SPARC_11 31 -#define R_SPARC_64 32 -#define R_SPARC_OLO10 33 -#define R_SPARC_HH22 34 -#define R_SPARC_HM10 35 -#define R_SPARC_LM22 36 -#define R_SPARC_PC_HH22 37 -#define R_SPARC_PC_HM10 38 -#define R_SPARC_PC_LM22 39 -#define R_SPARC_WDISP16 40 -#define R_SPARC_WDISP19 41 -#define R_SPARC_GLOB_JMP 42 -#define R_SPARC_7 43 -#define R_SPARC_5 44 -#define R_SPARC_6 45 - -/* TLS relocations */ -#define R_SPARC_TLS_GD_HI22 56 -#define R_SPARC_TLS_GD_LO10 57 -#define R_SPARC_TLS_GD_ADD 58 -#define R_SPARC_TLS_GD_CALL 59 -#define R_SPARC_TLS_LDM_HI22 60 -#define R_SPARC_TLS_LDM_LO10 61 -#define R_SPARC_TLS_LDM_ADD 62 -#define R_SPARC_TLS_LDM_CALL 63 -#define R_SPARC_TLS_LDO_HIX22 64 -#define R_SPARC_TLS_LDO_LOX10 65 -#define R_SPARC_TLS_LDO_ADD 66 -#define R_SPARC_TLS_IE_HI22 67 -#define R_SPARC_TLS_IE_LO10 68 -#define R_SPARC_TLS_IE_LD 69 -#define R_SPARC_TLS_IE_LDX 70 -#define R_SPARC_TLS_IE_ADD 71 -#define R_SPARC_TLS_LE_HIX22 72 -#define R_SPARC_TLS_LE_LOX10 73 -#define R_SPARC_TLS_DTPMOD32 74 -#define R_SPARC_TLS_DTPMOD64 75 -#define R_SPARC_TLS_DTPOFF32 76 -#define R_SPARC_TLS_DTPOFF64 77 -#define R_SPARC_TLS_TPOFF32 78 -#define R_SPARC_TLS_TPOFF64 79 - -#define R_TYPE(name) __CONCAT(R_SPARC_,name) diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h deleted file mode 100644 index d22514d60a..0000000000 --- a/cpukit/score/cpu/arm/rtems/asm.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - * @file - * - * @brief ARM Assembler Support API - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/percpu.h> - -/** - * @defgroup ScoreCPUARMASM ARM Assembler Support - * - * @ingroup ScoreCPU - * - * @brief ARM Assembler Support - */ -/**@{**/ - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) -#define r14 REG(r14) -#define r15 REG(r15) - -#define CPSR REG(CPSR) - -#define SPSR REG(SPSR) - -#define NUM_IRQ_VECTOR 6 // IRQ number -#define NUM_FIQ_VECTOR 7 // IRQ number - // // -#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1 -#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 -#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 -#define CPSR_FIQ_MODE 0x11 -#define CPSR_IRQ_MODE 0x12 -#define CPSR_SUPERVISOR_MODE 0x13 -#define CPSR_UNDEF_MODE 0x1B - -#define CPSR_MODE_BITS 0x1F - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#define FUNCTION_THUMB_ENTRY(name) \ - .thumb; \ - .thumb_func; \ - .align 2; \ - .globl name; \ - .type name, %function; \ - name: - -#define FUNCTION_ENTRY(name) \ - .align 2; \ - .globl name; \ - .type name, %function; \ - name: - -#define FUNCTION_END(name) \ - .size name, . - name - -#if defined(ARM_MULTILIB_ARCH_V7M) - #define DEFINE_FUNCTION_ARM(name) \ - .thumb_func ; .globl name ; name: -#elif defined(__thumb__) - #define DEFINE_FUNCTION_ARM(name) \ - .thumb_func ; .globl name ; name: ; bx pc ; \ - .arm ; .globl name ## _arm ; name ## _arm: -#else - #define DEFINE_FUNCTION_ARM(name) \ - .globl name ; name: ; .globl name ## _arm ; name ## _arm: -#endif - -.macro SWITCH_FROM_THUMB_TO_ARM -#ifdef __thumb__ -.align 2 - bx pc -.arm -#endif /* __thumb__ */ -.endm - -.macro SWITCH_FROM_ARM_TO_THUMB REG -#ifdef __thumb__ - add \REG, pc, #1 - bx \REG -.thumb -#endif /* __thumb__ */ -.endm - -.macro GET_SELF_CPU_CONTROL REG, TMP - ldr \REG, =_Per_CPU_Information -#ifdef RTEMS_SMP - /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ - mrc p15, 0, \TMP, c0, c0, 5 - - and \TMP, \TMP, #0xff - add \REG, \REG, \TMP, asl #PER_CPU_CONTROL_SIZE_LOG2 -#endif -.endm - -/** @} */ - -#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h deleted file mode 100644 index ae33b572af..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ /dev/null @@ -1,719 +0,0 @@ -/** - * @file - * - * @brief ARM Architecture Support API - */ - -/* - * This include file contains information pertaining to the ARM - * processor. - * - * Copyright (c) 2009-2015 embedded brains GmbH. - * - * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com> - * - * Copyright (c) 2006 OAR Corporation - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include <rtems/score/types.h> -#include <rtems/score/arm.h> - -#if defined(ARM_MULTILIB_ARCH_V4) - -/** - * @defgroup ScoreCPUARM ARM Specific Support - * - * @ingroup ScoreCPU - * - * @brief ARM specific support. - */ -/**@{**/ - -#if defined(__thumb__) && !defined(__thumb2__) - #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg - #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" - #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" - #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) - #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT -#else - #define ARM_SWITCH_REGISTERS - #define ARM_SWITCH_TO_ARM - #define ARM_SWITCH_BACK - #define ARM_SWITCH_OUTPUT - #define ARM_SWITCH_ADDITIONAL_OUTPUT -#endif - -/** - * @name Program Status Register - */ -/**@{**/ - -#define ARM_PSR_N (1 << 31) -#define ARM_PSR_Z (1 << 30) -#define ARM_PSR_C (1 << 29) -#define ARM_PSR_V (1 << 28) -#define ARM_PSR_Q (1 << 27) -#define ARM_PSR_J (1 << 24) -#define ARM_PSR_GE_SHIFT 16 -#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) -#define ARM_PSR_E (1 << 9) -#define ARM_PSR_A (1 << 8) -#define ARM_PSR_I (1 << 7) -#define ARM_PSR_F (1 << 6) -#define ARM_PSR_T (1 << 5) -#define ARM_PSR_M_SHIFT 0 -#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) -#define ARM_PSR_M_USR 0x10 -#define ARM_PSR_M_FIQ 0x11 -#define ARM_PSR_M_IRQ 0x12 -#define ARM_PSR_M_SVC 0x13 -#define ARM_PSR_M_ABT 0x17 -#define ARM_PSR_M_UND 0x1b -#define ARM_PSR_M_SYS 0x1f - -/** @} */ - -/** @} */ - -#endif /* defined(ARM_MULTILIB_ARCH_V4) */ - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* If someone uses THUMB we assume she wants minimal code size */ -#ifdef __thumb__ - #define CPU_INLINE_ENABLE_DISPATCH FALSE -#else - #define CPU_INLINE_ENABLE_DISPATCH TRUE -#endif - -#if defined(__ARMEL__) - #define CPU_BIG_ENDIAN FALSE - #define CPU_LITTLE_ENDIAN TRUE -#elif defined(__ARMEB__) - #define CPU_BIG_ENDIAN TRUE - #define CPU_LITTLE_ENDIAN FALSE -#else - #error "unknown endianness" -#endif - -/* - * The ARM uses the PIC interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#if defined(ARM_MULTILIB_HAS_WFI) - #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#else - #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE -#endif - -#define CPU_STACK_GROWS_UP FALSE - -/* XXX Why 32? */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * The interrupt mask disables only normal interrupts (IRQ). - * - * In order to support fast interrupts (FIQ) such that they can do something - * useful, we have to disable the operating system support for FIQs. Having - * operating system support for them would require that FIQs are disabled - * during critical sections of the operating system and application. At this - * level IRQs and FIQs would be equal. It is true that FIQs could interrupt - * the non critical sections of IRQs, so here they would have a small - * advantage. Without operating system support, the FIQs can execute at any - * time (of course not during the service of another FIQ). If someone needs - * operating system support for a FIQ, she can trigger a software interrupt and - * service the request in a two-step process. - */ -#define CPU_MODES_INTERRUPT_MASK 0x1 - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -#define CPU_STACK_MINIMUM_SIZE (1024 * 4) - -/* AAPCS, section 4.1, Fundamental Data Types */ -#define CPU_SIZEOF_POINTER 4 - -/* AAPCS, section 4.1, Fundamental Data Types */ -#define CPU_ALIGNMENT 8 - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* AAPCS, section 4.3.1, Aggregates */ -#define CPU_PARTITION_ALIGNMENT 4 - -/* AAPCS, section 5.2.1.2, Stack constraints at a public interface */ -#define CPU_STACK_ALIGNMENT 8 - -/* - * Bitfield handler macros. - * - * If we had a particularly fast function for finding the first - * bit set in a word, it would go here. Since we don't (*), we'll - * just use the universal macros. - * - * (*) On ARM V5 and later, there's a CLZ function which could be - * used to implement much quicker than the default macro. - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/** @} */ - -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 -#endif - -#ifdef ARM_MULTILIB_VFP - #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 -#endif - -#ifdef RTEMS_SMP - #ifdef ARM_MULTILIB_VFP - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 - #else - #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 - #endif -#endif - -#define ARM_EXCEPTION_FRAME_SIZE 80 - -#define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 - -#define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 - -#define ARM_VFP_CONTEXT_SIZE 264 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -typedef struct { -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t register_cpsr; - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_fp; - uint32_t register_sp; - uint32_t register_lr; -#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_r11; - void *register_lr; - void *register_sp; - uint32_t isr_nest_level; -#else - void *register_sp; -#endif -#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER - uint32_t thread_id; -#endif -#ifdef ARM_MULTILIB_VFP - uint64_t register_d8; - uint64_t register_d9; - uint64_t register_d10; - uint64_t register_d11; - uint64_t register_d12; - uint64_t register_d13; - uint64_t register_d14; - uint64_t register_d15; -#endif -#ifdef RTEMS_SMP - volatile bool is_executing; -#endif -} Context_Control; - -typedef struct { - /* Not supported */ -} Context_Control_fp; - -extern uint32_t arm_cpu_mode; - -static inline void _ARM_Data_memory_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "dmb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline void _ARM_Data_synchronization_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "dsb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline void _ARM_Instruction_synchronization_barrier( void ) -{ -#ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS - __asm__ volatile ( "isb" : : : "memory" ); -#else - RTEMS_COMPILER_MEMORY_BARRIER(); -#endif -} - -static inline uint32_t arm_interrupt_disable( void ) -{ - uint32_t level; - -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[level], cpsr\n" - "orr %[arm_switch_reg], %[level], #0x80\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - uint32_t basepri = 0x80; - - __asm__ volatile ( - "mrs %[level], basepri\n" - "msr basepri_max, %[basepri]\n" - : [level] "=&r" (level) - : [basepri] "r" (basepri) - ); -#else - level = 0; -#endif - - return level; -} - -static inline void arm_interrupt_enable( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - ARM_SWITCH_REGISTERS; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "msr cpsr, %[level]\n" - ARM_SWITCH_BACK - : ARM_SWITCH_OUTPUT - : [level] "r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - __asm__ volatile ( - "msr basepri, %[level]\n" - : - : [level] "r" (level) - ); -#endif -} - -static inline void arm_interrupt_flash( uint32_t level ) -{ -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - - __asm__ volatile ( - ARM_SWITCH_TO_ARM - "mrs %[arm_switch_reg], cpsr\n" - "msr cpsr, %[level]\n" - "msr cpsr, %[arm_switch_reg]\n" - ARM_SWITCH_BACK - : [arm_switch_reg] "=&r" (arm_switch_reg) - : [level] "r" (level) - ); -#elif defined(ARM_MULTILIB_ARCH_V7M) - uint32_t basepri; - - __asm__ volatile ( - "mrs %[basepri], basepri\n" - "msr basepri, %[level]\n" - "msr basepri, %[basepri]\n" - : [basepri] "=&r" (basepri) - : [level] "r" (level) - ); -#endif -} - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - _isr_cookie = arm_interrupt_disable(); \ - } while (0) - -#define _CPU_ISR_Enable( _isr_cookie ) \ - arm_interrupt_enable( _isr_cookie ) - -#define _CPU_ISR_Flash( _isr_cookie ) \ - arm_interrupt_flash( _isr_cookie ) - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -#define _CPU_Fatal_halt( _source, _err ) \ - do { \ - uint32_t _level; \ - uint32_t _error = _err; \ - _CPU_ISR_Disable( _level ); \ - (void) _level; \ - __asm__ volatile ("mov r0, %0\n" \ - : "=r" (_error) \ - : "0" (_error) \ - : "r0" ); \ - while (1); \ - } while (0); - -/** - * @brief CPU initialization. - */ -void _CPU_Initialize( void ); - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief CPU switch context. - */ -void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); - -void _CPU_Context_restore( Context_Control *new_context ) - RTEMS_NO_RETURN; - -#if defined(ARM_MULTILIB_ARCH_V7M) - void _ARMV7M_Start_multitasking( Context_Control *heir ) - RTEMS_NO_RETURN; - #define _CPU_Start_multitasking _ARMV7M_Start_multitasking -#endif - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t mpidr; - - /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */ - __asm__ volatile ( - "mrc p15, 0, %[mpidr], c0, c0, 5\n" - : [mpidr] "=&r" (mpidr) - ); - - return mpidr & 0xffU; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _ARM_Send_event( void ) - { - __asm__ volatile ( "sev" : : : "memory" ); - } - - static inline void _ARM_Wait_for_event( void ) - { - __asm__ volatile ( "wfe" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - _ARM_Data_synchronization_barrier(); - _ARM_Send_event(); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - _ARM_Wait_for_event(); - _ARM_Data_memory_barrier(); - } -#endif - - -static inline uint32_t CPU_swap_u32( uint32_t value ) -{ -#if defined(__thumb2__) - __asm__ volatile ( - "rev %0, %0" - : "=r" (value) - : "0" (value) - ); - return value; -#elif defined(__thumb__) - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -#else - uint32_t tmp = value; /* make compiler warnings go away */ - __asm__ volatile ("EOR %1, %0, %0, ROR #16\n" - "BIC %1, %1, #0xff0000\n" - "MOV %0, %0, ROR #8\n" - "EOR %0, %0, %1, LSR #8\n" - : "=r" (value), "=r" (tmp) - : "0" (value), "1" (tmp)); - return value; -#endif -} - -static inline uint16_t CPU_swap_u16( uint16_t value ) -{ -#if defined(__thumb2__) - __asm__ volatile ( - "rev16 %0, %0" - : "=r" (value) - : "0" (value) - ); - return value; -#else - return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU)); -#endif -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#if CPU_PROVIDES_IDLE_THREAD_BODY == TRUE - void *_CPU_Thread_Idle_body( uintptr_t ignored ); -#endif - -/** @} */ - -/** - * @addtogroup ScoreCPUARM - */ -/**@{**/ - -#if defined(ARM_MULTILIB_ARCH_V4) - -typedef enum { - ARM_EXCEPTION_RESET = 0, - ARM_EXCEPTION_UNDEF = 1, - ARM_EXCEPTION_SWI = 2, - ARM_EXCEPTION_PREF_ABORT = 3, - ARM_EXCEPTION_DATA_ABORT = 4, - ARM_EXCEPTION_RESERVED = 5, - ARM_EXCEPTION_IRQ = 6, - ARM_EXCEPTION_FIQ = 7, - MAX_EXCEPTIONS = 8, - ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff -} Arm_symbolic_exception_name; - -#endif /* defined(ARM_MULTILIB_ARCH_V4) */ - -typedef struct { - uint32_t register_fpexc; - uint32_t register_fpscr; - uint64_t register_d0; - uint64_t register_d1; - uint64_t register_d2; - uint64_t register_d3; - uint64_t register_d4; - uint64_t register_d5; - uint64_t register_d6; - uint64_t register_d7; - uint64_t register_d8; - uint64_t register_d9; - uint64_t register_d10; - uint64_t register_d11; - uint64_t register_d12; - uint64_t register_d13; - uint64_t register_d14; - uint64_t register_d15; - uint64_t register_d16; - uint64_t register_d17; - uint64_t register_d18; - uint64_t register_d19; - uint64_t register_d20; - uint64_t register_d21; - uint64_t register_d22; - uint64_t register_d23; - uint64_t register_d24; - uint64_t register_d25; - uint64_t register_d26; - uint64_t register_d27; - uint64_t register_d28; - uint64_t register_d29; - uint64_t register_d30; - uint64_t register_d31; -} ARM_VFP_context; - -typedef struct { - uint32_t register_r0; - uint32_t register_r1; - uint32_t register_r2; - uint32_t register_r3; - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - uint32_t register_r8; - uint32_t register_r9; - uint32_t register_r10; - uint32_t register_r11; - uint32_t register_r12; - uint32_t register_sp; - void *register_lr; - void *register_pc; -#if defined(ARM_MULTILIB_ARCH_V4) - uint32_t register_cpsr; - Arm_symbolic_exception_name vector; -#elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) - uint32_t register_xpsr; - uint32_t vector; -#endif - const ARM_VFP_context *vfp_context; - uint32_t reserved_for_stack_alignment; -} CPU_Exception_frame; - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -void _ARM_Exception_default( CPU_Exception_frame *frame ); - -/* - * FIXME: In case your BSP uses this function, then convert it to use - * the shared start.S file for ARM. - */ -void rtems_exception_init_mngt( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h deleted file mode 100644 index c430911373..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * - * @ingroup ScoreCPU - * - * @brief ARM Assembler Support API - */ - -/* - * COPYRIGHT (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file is the include file for cpu_asm.S - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - -/* Registers saved in context switch: */ -.set REG_CPSR, 0 -.set REG_R4, 4 -.set REG_R5, 8 -.set REG_R6, 12 -.set REG_R7, 16 -.set REG_R8, 20 -.set REG_R9, 24 -.set REG_R10, 28 -.set REG_R11, 32 -.set REG_SP, 36 -.set REG_LR, 40 -.set REG_PC, 44 -.set SIZE_REGS, REG_PC + 4 - -#endif diff --git a/cpukit/score/cpu/arm/rtems/score/types.h b/cpukit/score/cpu/arm/rtems/score/types.h deleted file mode 100644 index deefd54996..0000000000 --- a/cpukit/score/cpu/arm/rtems/score/types.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * - * @brief ARM Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/avr/rtems/asm.h b/cpukit/score/cpu/avr/rtems/asm.h deleted file mode 100644 index e93841d06e..0000000000 --- a/cpukit/score/cpu/avr/rtems/asm.h +++ /dev/null @@ -1,464 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/avr.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* Copyright (c) 2002, 2005, 2006, 2007 Marek Michalkiewicz - Copyright (c) 2006 Dmitry Xmelkov - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* - macros.inc - macros for use in assembler sources - - Contributors: - Created by Marek Michalkiewicz <marekm@linux.org.pl> - */ - -#include <avr/common.h> - -/* if not defined, assume old version with underscores */ -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* the assembler line separator (just in case it ever changes) */ -#define _L $ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -#define _U(x) CONCAT1(__USER_LABEL_PREFIX__, x) - -#define _R(x) CONCAT1(__REGISTER_PREFIX__, x) - -/* these should help to fix the "can't have function named r1()" bug - which may require adding '%' in front of register names. */ - -#define r0 _R(r0) -#define r1 _R(r1) -#define r2 _R(r2) -#define r3 _R(r3) -#define r4 _R(r4) -#define r5 _R(r5) -#define r6 _R(r6) -#define r7 _R(r7) -#define r8 _R(r8) -#define r9 _R(r9) -#define r10 _R(r10) -#define r11 _R(r11) -#define r12 _R(r12) -#define r13 _R(r13) -#define r14 _R(r14) -#define r15 _R(r15) -#define r16 _R(r16) -#define r17 _R(r17) -#define r18 _R(r18) -#define r19 _R(r19) -#define r20 _R(r20) -#define r21 _R(r21) -#define r22 _R(r22) -#define r23 _R(r23) -#define r24 _R(r24) -#define r25 _R(r25) -#define r26 _R(r26) -#define r27 _R(r27) -#define r28 _R(r28) -#define r29 _R(r29) -#define r30 _R(r30) -#define r31 _R(r31) - -#ifndef __tmp_reg__ -#define __tmp_reg__ r0 -#endif - -#ifndef __zero_reg__ -#define __zero_reg__ r1 -#endif - -#if __AVR_MEGA__ - #define XJMP jmp - #define XCALL call -#else - #define XJMP rjmp - #define XCALL rcall -#endif - -/* used only by fplib/strtod.S - libgcc internal function calls */ -#define PROLOGUE_SAVES(offset) XJMP (__prologue_saves__ + 2 * (offset)) -#define EPILOGUE_RESTORES(offset) XJMP (__epilogue_restores__ + 2 * (offset)) - -#if FLASHEND > 0x10000 /* ATmega103 */ - #define BIG_CODE 1 -#else - #define BIG_CODE 0 -#endif - -#ifndef __AVR_HAVE_MOVW__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_MOVW__ 1 -# endif -#endif - -#ifndef __AVR_HAVE_LPMX__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_LPMX__ 1 -# endif -#endif - -#ifndef __AVR_HAVE_MUL__ -# if defined(__AVR_ENHANCED__) && __AVR_ENHANCED__ -# define __AVR_HAVE_MUL__ 1 -# endif -#endif - -/* - Smart version of movw: - - uses "movw" if possible (supported by MCU, and both registers even) - - handles overlapping register pairs correctly - - no instruction generated if source and destination are the same - (may expand to 0, 1 or 2 instructions). - */ - -.macro X_movw dst src - .L_movw_dst = -1 - .L_movw_src = -1 - .L_movw_n = 0 - .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ - r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ - r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ - r30,r31 - .ifc \reg,\dst - .L_movw_dst = .L_movw_n - .endif - .ifc \reg,\src - .L_movw_src = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .L_movw_n = 0 - .irp reg, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ - R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ - R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ - R30,R31 - .ifc \reg,\dst - .L_movw_dst = .L_movw_n - .endif - .ifc \reg,\src - .L_movw_src = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .if .L_movw_dst < 0 - .L_movw_n = 0 - .rept 32 - .if \dst == .L_movw_n - .L_movw_dst = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .endif - .if .L_movw_src < 0 - .L_movw_n = 0 - .rept 32 - .if \src == .L_movw_n - .L_movw_src = .L_movw_n - .endif - .L_movw_n = .L_movw_n + 1 - .endr - .endif - .if (.L_movw_dst < 0) || (.L_movw_src < 0) - .err ; Invalid 'X_movw' arg. - .endif - - .if ((.L_movw_src) - (.L_movw_dst)) /* different registers */ - .if (((.L_movw_src) | (.L_movw_dst)) & 0x01) - .if (((.L_movw_src)-(.L_movw_dst)) & 0x80) /* src < dest */ - mov (.L_movw_dst)+1, (.L_movw_src)+1 - mov (.L_movw_dst), (.L_movw_src) - .else /* src > dest */ - mov (.L_movw_dst), (.L_movw_src) - mov (.L_movw_dst)+1, (.L_movw_src)+1 - .endif - .else /* both even -> overlap not possible */ -#if defined(__AVR_HAVE_MOVW__) && __AVR_HAVE_MOVW__ - movw \dst, \src -#else - mov (.L_movw_dst), (.L_movw_src) - mov (.L_movw_dst)+1, (.L_movw_src)+1 -#endif - .endif - .endif -.endm - -/* Macro 'X_lpm' extends enhanced lpm instruction for classic chips. - Usage: - X_lpm reg, dst - where - reg is 0..31, r0..r31 or R0..R31 - dst is z, Z, z+ or Z+ - It is possible to omit both arguments. - - Possible results for classic chips: - lpm - lpm / mov Rd,r0 - lpm / adiw ZL,1 - lpm / mov Rd,r0 / adiw ZL,1 - - For enhanced chips it is one instruction always. - - ATTENTION: unlike enhanced chips SREG (S,V,N,Z,C) flags are - changed in case of 'Z+' dst. R0 is scratch. - */ -.macro X_lpm dst=r0, src=Z - - /* dst evaluation */ - .L_lpm_dst = -1 - - .L_lpm_n = 0 - .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, \ - r10,r11,r12,r13,r14,r15,r16,r17,r18,r19, \ - r20,r21,r22,r23,r24,r25,r26,r27,r28,r29, \ - r30,r31 - .ifc \reg,\dst - .L_lpm_dst = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - - .L_lpm_n = 0 - .irp reg, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, \ - R10,R11,R12,R13,R14,R15,R16,R17,R18,R19, \ - R20,R21,R22,R23,R24,R25,R26,R27,R28,R29, \ - R30,R31 - .ifc \reg,\dst - .L_lpm_dst = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - - .if .L_lpm_dst < 0 - .L_lpm_n = 0 - .rept 32 - .if \dst == .L_lpm_n - .L_lpm_dst = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - .endif - - .if (.L_lpm_dst < 0) - .err ; Invalid dst arg of 'X_lpm' macro. - .endif - - /* src evaluation */ - .L_lpm_src = -1 - .L_lpm_n = 0 - .irp reg, z,Z,z+,Z+ - .ifc \reg,\src - .L_lpm_src = .L_lpm_n - .endif - .L_lpm_n = .L_lpm_n + 1 - .endr - - .if (.L_lpm_src < 0) - .err ; Invalid src arg of 'X_lpm' macro. - .endif - - /* instruction(s) */ - .if .L_lpm_src < 2 - .if .L_lpm_dst == 0 - lpm - .else -#if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ - lpm .L_lpm_dst, Z -#else - lpm - mov .L_lpm_dst, r0 -#endif - .endif - .else - .if (.L_lpm_dst >= 30) - .err ; Registers 30 and 31 are inhibited as 'X_lpm *,Z+' dst. - .endif -#if defined(__AVR_HAVE_LPMX__) && __AVR_HAVE_LPMX__ - lpm .L_lpm_dst, Z+ -#else - lpm - .if .L_lpm_dst - mov .L_lpm_dst, r0 - .endif - adiw r30, 1 -#endif - .endif -.endm - -/* - LPM_R0_ZPLUS_INIT is used before the loop to initialize RAMPZ - for future devices with RAMPZ:Z auto-increment - [e]lpm r0, Z+. - - LPM_R0_ZPLUS_NEXT is used inside the loop to load a byte from - the program memory at [RAMPZ:]Z to R0, and increment [RAMPZ:]Z. - - The argument in both macros is a register that contains the - high byte (bits 23-16) of the address, bits 15-0 should be in - the Z (r31:r30) register. It can be any register except for: - r0, r1 (__zero_reg__ - assumed to always contain 0), r30, r31. - */ - - .macro LPM_R0_ZPLUS_INIT hhi -#if __AVR_ENHANCED__ - #if BIG_CODE - out AVR_RAMPZ_ADDR, \hhi - #endif -#endif - .endm - - .macro LPM_R0_ZPLUS_NEXT hhi -#if __AVR_ENHANCED__ - #if BIG_CODE - /* ELPM with RAMPZ:Z post-increment, load RAMPZ only once */ - elpm r0, Z+ - #else - /* LPM with Z post-increment, max 64K, no RAMPZ (ATmega83/161/163/32) */ - lpm r0, Z+ - #endif -#else - #if BIG_CODE - /* ELPM without post-increment, load RAMPZ each time (ATmega103) */ - out AVR_RAMPZ_ADDR, \hhi - elpm - adiw r30,1 - adc \hhi, __zero_reg__ - #else - /* LPM without post-increment, max 64K, no RAMPZ (AT90S*) */ - lpm - adiw r30,1 - #endif -#endif - .endm - -#endif /* _RTEMS_ASM_H */ diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h deleted file mode 100644 index f3baec4451..0000000000 --- a/cpukit/score/cpu/avr/rtems/score/cpu.h +++ /dev/null @@ -1,1176 +0,0 @@ -/** - * @file - * - * @brief Intel AVR CPU Department Source - * - * This include file contains information pertaining to the AVR - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/avr.h> -#include <avr/common.h> - -/* conditional compilation parameters */ - -#ifndef RTEMS_USE_16_BIT_OBJECT -#define RTEMS_USE_16_BIT_OBJECT -#endif - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "AVR_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if ( AVR_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALL_TASKS_ARE_FP TRUE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -typedef struct { - uint16_t stack_pointer; - uint8_t status; /* SREG */ -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->stack_pointer - - - - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -#endif /* ASM */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_MINIMUM_SIZE 512 - -/* - * Maximum priority of a thread. Note based from 0 which is the idle task. - */ -#define CPU_PRIORITY_MAXIMUM 15 - -#define CPU_SIZEOF_POINTER 2 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = SREG; \ - __asm__ volatile ("cli"::); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - SREG = _isr_cookie; \ - __asm__ volatile ("sei"::); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - SREG=(_isr_cookie); \ - __asm__ volatile("sei"::); \ - (_isr_cookie) = SREG; \ - __asm__ volatile("cli"::); \ - } while (0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - * AVR Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#ifndef ASM -static inline void _CPU_ISR_Set_level( unsigned int new_level ) -{ -} - - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ -/* -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp ) \ - \ - do { \ - uint16_t *_stack;\ - _stack = (uint16_t) (_stack_base) + (uint16_t)(_size);\ - (_the_context)->stack_pointer = _stack-1; \ - *(_stack) = *(_entry_point); \ - printk("the ret address is %x\n", *(uint16_t *)(_stack));\ - printk("sp = 0x%x\nep = 0x%x\n",_stack, *(_entry_point)); \ - printk("stack base = 0x%x\n size = 0x%x\n",_stack_base, _size);\ - printk("struct starting address = 0x%x\n", _the_context);\ - printk("struct stack pointer address = 0x%x\n",(_the_context)->stack_pointer);\ - } while ( 0 ) - -*/ -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( _the_context ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/*context_initialize asm-function*/ - -void context_initialize(unsigned short* context, - unsigned short stack_add, - unsigned short entry_point); - -/* - * _CPU_Context_Initialize - * - * This kernel routine initializes the basic non-FP context area associated - * with each thread. - * - * Input parameters: - * the_context - pointer to the context area - * stack_base - address of memory for the SPARC - * size - size in bytes of the stack area - * new_level - interrupt level for this context area - * entry_point - the starting execution point for this this context - * is_fp - TRUE if this context is associated with an FP thread - * - * Output parameters: NONE - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* -* -* _CPU_Push -* -* this routine pushes 2 bytes onto the stack -* -* -* -* -* -* -* -*/ - -void _CPU_Push(uint16_t _SP_, uint16_t entry_point); - - - - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * AVR Specific Information: - * - * XXX document implementation including references if appropriate - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h b/cpukit/score/cpu/avr/rtems/score/cpu_asm.h deleted file mode 100644 index af920d143e..0000000000 --- a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief Intel AVR Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/avr/rtems/score/types.h b/cpukit/score/cpu/avr/rtems/score/types.h deleted file mode 100644 index f63f5d5a3b..0000000000 --- a/cpukit/score/cpu/avr/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Intel AVR CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * avr processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void avr_isr; -typedef void ( *avr_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/asm.h b/cpukit/score/cpu/bfin/rtems/asm.h deleted file mode 100644 index 5d133ddbdd..0000000000 --- a/cpukit/score/cpu/bfin/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/bfin.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h deleted file mode 100644 index ebcfe1e15e..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpu.h +++ /dev/null @@ -1,1278 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Department Source - * - * This include file contains information pertaining to the Blackfin - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch> - * and Antonio Giovanini <antonio@atos.com.br> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/bfin.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * BFIN Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( BLACKFIN_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN FALSE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN TRUE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ - -/* make sure this stays in sync with the assembly function - __CPU_Context_switch in cpu_asm.S */ -typedef struct { - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - - uint32_t register_p3; - uint32_t register_p4; - uint32_t register_p5; - uint32_t register_fp; - uint32_t register_sp; - - uint32_t register_rets; - - uint32_t imask; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /* FPU registers are listed here */ - /* Blackfin has no Floating Point */ -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - /*uint32_t special_interrupt_register;*/ -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif /* ASM */ - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 - -/** - * @ingroup CPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 8 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _level ) \ - { \ - __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ - } - - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _level ) { \ - __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ - } - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _level ) { \ - __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ - : : "d"(_level) : "R0" ); \ - } - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ - } - -#ifndef ASM - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * See implementation in cpu.c - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - __asm__ volatile ( "cli R1; \ - R1 = %0; \ - _halt: \ - idle; \ - jump _halt;"\ - : : "r" (_error) ); \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - __asm__ ("bit(1);"): - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** @} */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h deleted file mode 100644 index 4f78c9d358..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h +++ /dev/null @@ -1,27 +0,0 @@ -/** - * @file - * - * @brief Blackfin Assembly File - * - * Defines a couple of Macros used in cpu_asm.S - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer <alain.schaefer@easc.ch> - * and Antonio Giovanini <antonio@atos.com.br> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/bfin/rtems/score/types.h b/cpukit/score/cpu/bfin/rtems/score/types.h deleted file mode 100644 index eaa8de6bd9..0000000000 --- a/cpukit/score/cpu/bfin/rtems/score/types.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Blackfin processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -/** This defines the return type for an ISR entry point. */ -typedef void blackfin_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef blackfin_isr ( *blackfin_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/asm.h b/cpukit/score/cpu/epiphany/rtems/asm.h deleted file mode 100644 index 87e0cca1cb..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef __EPIPHANY_ASM_H -#define __EPIPHANY_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/epiphany.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .extern SYM (sym) -#define TYPE_FUNC(sym) .type SYM (sym), %function - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h b/cpukit/score/cpu/epiphany/rtems/score/cpu.h deleted file mode 100644 index d0cbb64b44..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h +++ /dev/null @@ -1,1163 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _EPIPHANY_CPU_H -#define _EPIPHANY_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/epiphany.h> /* pick up machine definitions */ -#include <rtems/score/types.h> -#ifndef ASM -#include <rtems/bspIo.h> -#include <stdint.h> -#include <stdio.h> /* for printk */ -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Currently, for epiphany port, _ISR_Handler is responsible for switching to - * RTEMS dedicated interrupt task. - * - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "epiphany_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * epiphany Specific Information: - * - * At this time there are no implementations of Epiphany that are - * expected to implement floating point. - */ - -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - */ - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * epiphany Specific Information: - * - * This version of RTEMS is designed specifically to run with - * big endian architectures. If you want little endian, you'll - * have to make the appropriate adjustments here and write - * efficient routines for byte swapping. The epiphany architecture - * doesn't do this very well. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * - */ -#ifndef ASM - -typedef struct { - uint32_t r[64]; - - uint32_t status; - uint32_t config; - uint32_t iret; - -#ifdef RTEMS_SMP - /** - * @brief On SMP configurations the thread context must contain a boolean - * indicator to signal if this context is executing on a processor. - * - * This field must be updated during a context switch. The context switch - * to the heir must wait until the heir context indicates that it is no - * longer executing on a processor. The context switch must also check if - * a thread dispatch is necessary to honor updates of the heir thread for - * this processor. This indicator must be updated using an atomic test and - * set operation to ensure that at most one processor uses the heir - * context at the same time. - * - * @code - * void _CPU_Context_switch( - * Context_Control *executing, - * Context_Control *heir - * ) - * { - * save( executing ); - * - * executing->is_executing = false; - * memory_barrier(); - * - * if ( test_and_set( &heir->is_executing ) ) { - * do { - * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); - * - * if ( cpu_self->dispatch_necessary ) { - * heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); - * } - * } while ( test_and_set( &heir->is_executing ) ); - * } - * - * restore( heir ); - * } - * @endcode - */ - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r[13] - -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * epiphany Specific Information: - * - */ - -#define CPU_CONTEXT_FP_SIZE 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - */ - -#define CPU_ALIGNMENT 8 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - */ - -#define CPU_STACK_ALIGNMENT 8 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline uint32_t epiphany_interrupt_disable( void ) -{ - uint32_t sr; - __asm__ __volatile__ ("movfs %[sr], status \n" : [sr] "=r" (sr):); - __asm__ __volatile__("gid \n"); - return sr; -} - -static inline void epiphany_interrupt_enable(uint32_t level) -{ - __asm__ __volatile__("gie \n"); - __asm__ __volatile__ ("movts status, %[level] \n" :: [level] "r" (level):); -} - -#define _CPU_ISR_Disable( _level ) \ - _level = epiphany_interrupt_disable() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - */ - -#define _CPU_ISR_Enable( _level ) \ - epiphany_interrupt_enable( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - */ - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - if ( (_level & 0x2) != 0 ) \ - _CPU_ISR_Enable( _level ); \ - epiphany_interrupt_disable(); \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - */ - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - */ - -/** - * @brief Account for GCC red-zone - * - * The following macro is used when initializing task's stack - * to account for GCC red-zone. - */ - -#define EPIPHANY_GCC_RED_ZONE_SIZE 128 - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ) - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - */ - -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - asm("trap 3" :: "r" (_error)); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - */ - - /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - (1 << _bit_number) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { -/* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; -#endif /* ASM */ - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 -#define CPU_EXCEPTION_FRAME_SIZE 260 -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM -typedef uint16_t Priority_bit_map_Word; - -typedef struct { - uint32_t r[62]; - uint32_t status; - uint32_t config; - uint32_t iret; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * epiphany Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef RTEMS_SMP - /** - * @brief Performs CPU specific SMP initialization in the context of the boot - * processor. - * - * This function is invoked on the boot processor during system - * initialization. All interrupt stacks are allocated at this point in case - * the CPU port allocates the interrupt stacks. This function is called - * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is - * used. - * - * @return The count of physically or virtually available processors. - * Depending on the configuration the application may use not all processors. - */ - uint32_t _CPU_SMP_Initialize( void ); - - /** - * @brief Starts a processor specified by its index. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after _CPU_SMP_Initialize(). - * - * @param[in] cpu_index The processor index. - * - * @retval true Successful operation. - * @retval false Unable to start this processor. - */ - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - /** - * @brief Performs final steps of CPU specific SMP initialization in the - * context of the boot processor. - * - * This function is invoked on the boot processor during system - * initialization. - * - * This function will be called after all processors requested by the - * application have been started. - * - * @param[in] cpu_count The minimum value of the count of processors - * requested by the application configuration and the count of physically or - * virtually available processors. - */ - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - /** - * @brief Returns the index of the current processor. - * - * An architecture specific method must be used to obtain the index of the - * current processor in the system. The set of processor indices is the - * range of integers starting with zero up to the processor count minus one. - */ - uint32_t _CPU_SMP_Get_current_processor( void ); - - /** - * @brief Sends an inter-processor interrupt to the specified target - * processor. - * - * This operation is undefined for target processor indices out of range. - * - * @param[in] target_processor_index The target processor index. - */ - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - /** - * @brief Broadcasts a processor event. - * - * Some architectures provide a low-level synchronization primitive for - * processors in a multi-processor environment. Processors waiting for this - * event may go into a low-power state and stop generating system bus - * transactions. This function must ensure that preceding store operations - * can be observed by other processors. - * - * @see _CPU_SMP_Processor_event_receive(). - */ - void _CPU_SMP_Processor_event_broadcast( void ); - - /** - * @brief Receives a processor event. - * - * This function will wait for the processor event and may wait forever if no - * such event arrives. - * - * @see _CPU_SMP_Processor_event_broadcast(). - */ - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - /** - * @brief Gets the is executing indicator of the thread context. - * - * @param[in] context The context. - */ - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - /** - * @brief Sets the is executing indicator of the thread context. - * - * @param[in] context The context. - * @param[in] is_executing The new value for the is executing indicator. - */ - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif /* RTEMS_SMP */ - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h b/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h deleted file mode 100644 index cc091fa909..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief Epiphany Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/epiphany/rtems/score/types.h b/cpukit/score/cpu/epiphany/rtems/score/types.h deleted file mode 100644 index 5b6c503739..0000000000 --- a/cpukit/score/cpu/epiphany/rtems/score/types.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file - * - * @brief Epiphany Architecture Types API - */ - -/* - * Copyright (c) 2015 University of York. - * Hesham ALMatary <hmka501@york.ac.uk> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - - #ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void epiphany_isr; -typedef void ( *epiphany_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/h8300/rtems/asm.h b/cpukit/score/cpu/h8300/rtems/asm.h deleted file mode 100644 index 6c1a643db4..0000000000 --- a/cpukit/score/cpu/h8300/rtems/asm.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#include <rtems/score/h8300.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) - -#define er0 REG(er0) -#define er1 REG(er1) -#define er2 REG(er2) -#define er3 REG(er3) -#define er4 REG(er4) -#define er5 REG(er5) -#define er6 REG(er6) -#define er7 REG(er7) - -#define sp REG(sp) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE __asm__ ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h deleted file mode 100644 index 8b34bb4c7f..0000000000 --- a/cpukit/score/cpu/h8300/rtems/score/cpu.h +++ /dev/null @@ -1,1176 +0,0 @@ -/** - * @file - * - * @brief Hitachi H8300 CPU Department Source - * - * This include file contains information pertaining to the H8300 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/h8300.h> -#ifndef ASM - #include <rtems/bspIo.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should this target use 16 or 32 bit object Ids? - * - */ -#define RTEMS_USE_16_BIT_OBJECT - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * H8300 Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "H8300_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * H8300 Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * H8300 Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * H8300 Specific Information: - * - * XXX - */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -#define nogap __attribute__ ((packed)) - -typedef struct { - uint16_t ccr nogap; - void *er7 nogap; - void *er6 nogap; - uint32_t er5 nogap; - uint32_t er4 nogap; - uint32_t er3 nogap; - uint32_t er2 nogap; - uint32_t er1 nogap; - uint32_t er0 nogap; - uint32_t xxx nogap; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->er7 - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * H8300 Specific Information: - * - * XXX - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * H8300 Specific Information: - * - * XXX - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif /* ASM */ - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * H8300 Specific Information: - * - * It is highly unlikely the H8300 will get used in a multiprocessor system. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_MINIMUM_SIZE (1536) - -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) - #define CPU_SIZEOF_POINTER 4 -#else - #define CPU_SIZEOF_POINTER 2 -#endif - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_STACK_ALIGNMENT 2 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. - Note requires ISR_Level be uint16_t or assembler croaks. -*/ - -#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 ) - - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - - -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \ - } while (0) - - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - - -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \ - } while (0) - -/* end of ISR handler macros */ - -#else /* modern gcc version */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * H8300 Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented for the SX. - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned char __ccr; \ - __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \ - : "=m" (__ccr) /* : "0" (__ccr) */ ); \ - (_isr_cookie) = __ccr; \ - } while (0) -#else -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) -#endif - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * H8300 Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented for the SX. - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - __asm__ volatile( "ldc %0, ccr" : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) -#endif - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * H8300 Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented for the SX. - */ - -#if defined(__H8300H__) || defined(__H8300S__) -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned char __ccr = (unsigned char) (_isr_cookie); \ - __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \ - } while (0) -#else -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) -#endif - -#endif /* end of old gcc */ - - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \ - else __asm__ volatile ( "andc #0x7f,ccr\n" ); \ - } - -#ifndef ASM - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * H8300 Specific Information: - * - * XXX - */ - - -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - /* Locate Me */ \ - do { \ - uintptr_t _stack; \ - \ - if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ - else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ - \ - (void) _is_fp; /* to eliminate set but not used warning */ \ - _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->er7 = (void *) _stack; \ - (_the_context)->er6 = (void *) _stack; \ - (_the_context)->er5 = 0; \ - (_the_context)->er4 = 1; \ - (_the_context)->er3 = 2; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * H8300 Specific Information: - * - * XXX - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - for(;;) - - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * H8300 Specific Information: - * - * XXX - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * H8300 Specific Information: - * - * XXX - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * H8300 Specific Information: - * - * XXX - */ - -void *_CPU_Thread_Idle_body( uint32_t ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * H8300 Specific Information: - * - * XXX - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * H8300 Specific Information: - * - * This is the generic implementation. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -/* to be provided by the BSP */ -extern void H8BD_Install_IRQ( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler ); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/h8300/rtems/score/types.h b/cpukit/score/cpu/h8300/rtems/score/types.h deleted file mode 100644 index 7fcac8b552..0000000000 --- a/cpukit/score/cpu/h8300/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Hitachi H8300 CPU Type Definitions - * - * This include file contains type definitions pertaining to the Hitachi - * h8300 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void h8300_isr; -typedef void ( *h8300_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/i386/rtems/asm.h b/cpukit/score/cpu/i386/rtems/asm.h deleted file mode 100644 index 50b0fd71a0..0000000000 --- a/cpukit/score/cpu/i386/rtems/asm.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/i386.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -/* - * Looks like there is a bug in gcc 2.6.2 where this is not - * defined correctly when configured as i386-coff and - * i386-aout. - */ - -#undef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ % - -/* -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif -*/ - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) - -#define eax REG (eax) -#define ebx REG (ebx) -#define ecx REG (ecx) -#define edx REG (edx) -#define esi REG (esi) -#define edi REG (edi) -#define esp REG (esp) -#define ebp REG (ebp) -#define cr0 REG (cr0) -#define cr4 REG (cr4) - -#define ax REG (ax) -#define bx REG (bx) -#define cx REG (cx) -#define dx REG (dx) -#define si REG (si) -#define di REG (di) -#define sp REG (sp) -#define bp REG (bp) - -#define ah REG (ah) -#define bh REG (bh) -#define ch REG (ch) -#define dh REG (dh) - -#define al REG (al) -#define bl REG (bl) -#define cl REG (cl) -#define dl REG (dl) - -#define cs REG (cs) -#define ds REG (ds) -#define es REG (es) -#define fs REG (fs) -#define gs REG (gs) -#define ss REG (ss) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h deleted file mode 100644 index 4f0cd6e6b0..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/cpu.h +++ /dev/null @@ -1,748 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Dependent Source - * - * This include file contains information pertaining to the Intel - * i386 processor. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifndef ASM -#include <string.h> /* for memcpy */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/i386.h> - -#ifndef ASM -#include <rtems/score/interrupts.h> /* formerly in libcpu/cpu.h> */ -#include <rtems/score/registers.h> /* formerly part of libcpu */ -#endif - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * i386 has an RTEMS allocated and managed interrupt stack. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the i387 - * for the i386, others have it built in (i486DX, Pentium). - */ - -#ifdef __SSE__ -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP TRUE -#define CPU_IDLE_TASK_IS_FP TRUE -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else /* __SSE__ */ - -#if ( I386_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE /* i387 for i386 */ -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#if defined(RTEMS_SMP) - #define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else - #define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif -#endif /* __SSE__ */ - -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0 -#define I386_CONTEXT_CONTROL_ESP_OFFSET 4 -#define I386_CONTEXT_CONTROL_EBP_OFFSET 8 -#define I386_CONTEXT_CONTROL_EBX_OFFSET 12 -#define I386_CONTEXT_CONTROL_ESI_OFFSET 16 -#define I386_CONTEXT_CONTROL_EDI_OFFSET 20 - -#ifdef RTEMS_SMP - #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 24 -#endif - -/* structures */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Basic integer context for the i386 family. - */ - -typedef struct { - uint32_t eflags; /* extended flags register */ - void *esp; /* extended stack pointer register */ - void *ebp; /* extended base pointer register */ - uint32_t ebx; /* extended bx register */ - uint32_t esi; /* extended source index register */ - uint32_t edi; /* extended destination index flags register */ -#ifdef RTEMS_SMP - volatile bool is_executing; -#endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->esp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -/* - * FP context save area for the i387 numeric coprocessors. - */ -#ifdef __SSE__ -/* All FPU and SSE registers are volatile; hence, as long - * as we are within normally executing C code (including - * a task switch) there is no need for saving/restoring - * any of those registers. - * We must save/restore the full FPU/SSE context across - * interrupts and exceptions, however: - * - after ISR execution a _Thread_Dispatch() may happen - * and it is therefore necessary to save the FPU/SSE - * registers to be restored when control is returned - * to the interrupted task. - * - gcc may implicitly use FPU/SSE instructions in - * an ISR. - * - * Even though there is no explicit mentioning of the FPU - * control word in the SYSV ABI (i386) being non-volatile - * we maintain MXCSR and the FPU control-word for each task. - */ -typedef struct { - uint32_t mxcsr; - uint16_t fpucw; -} Context_Control_fp; - -#else - -typedef struct { - uint8_t fp_save_area[108]; /* context size area for I80387 */ - /* 28 bytes for environment */ -} Context_Control_fp; - -#endif - - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of execptions. - * - * idtIndex is either the interrupt number or the trap/exception number. - * faultCode is the code pushed by the processor on some exceptions. - * - * Since the first registers are directly pushed by the CPU they - * may not respect 16-byte stack alignment, which is, however, - * mandatory for the SSE register area. - * Therefore, these registers are stored at an aligned address - * and a pointer is stored in the CPU_Exception_frame. - * If the executive was compiled without SSE support then - * this pointer is NULL. - */ - -struct Context_Control_sse; - -typedef struct { - struct Context_Control_sse *fp_ctxt; - uint32_t edi; - uint32_t esi; - uint32_t ebp; - uint32_t esp0; - uint32_t ebx; - uint32_t edx; - uint32_t ecx; - uint32_t eax; - uint32_t idtIndex; - uint32_t faultCode; - uint32_t eip; - uint32_t cs; - uint32_t eflags; -} CPU_Exception_frame; - -#ifdef __SSE__ -typedef struct Context_Control_sse { - uint16_t fcw; - uint16_t fsw; - uint8_t ftw; - uint8_t res_1; - uint16_t fop; - uint32_t fpu_ip; - uint16_t cs; - uint16_t res_2; - uint32_t fpu_dp; - uint16_t ds; - uint16_t res_3; - uint32_t mxcsr; - uint32_t mxcsr_mask; - struct { - uint8_t fpreg[10]; - uint8_t res_4[ 6]; - } fp_mmregs[8]; - uint8_t xmmregs[8][16]; - uint8_t res_5[224]; -} Context_Control_sse -__attribute__((aligned(16))) -; -#endif - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(void); - -/* - * This port does not pass any frame info to the - * interrupt handler. - */ - -typedef void CPU_Interrupt_frame; - -typedef enum { - I386_EXCEPTION_DIVIDE_BY_ZERO = 0, - I386_EXCEPTION_DEBUG = 1, - I386_EXCEPTION_NMI = 2, - I386_EXCEPTION_BREAKPOINT = 3, - I386_EXCEPTION_OVERFLOW = 4, - I386_EXCEPTION_BOUND = 5, - I386_EXCEPTION_ILLEGAL_INSTR = 6, - I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7, - I386_EXCEPTION_DOUBLE_FAULT = 8, - I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, - I386_EXCEPTION_INVALID_TSS = 10, - I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11, - I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, - I386_EXCEPTION_GENERAL_PROT_ERR = 13, - I386_EXCEPTION_PAGE_FAULT = 14, - I386_EXCEPTION_INTEL_RES15 = 15, - I386_EXCEPTION_FLOAT_ERROR = 16, - I386_EXCEPTION_ALIGN_CHECK = 17, - I386_EXCEPTION_MACHINE_CHECK = 18, - I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */ - -} Intel_symbolic_exception_name; - - -/* - * context size area for floating point - * - * NOTE: This is out of place on the i386 to avoid a forward reference. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* variables */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On i386 thread stacks require no further alignment after allocation - * from the Workspace. However, since gcc maintains 16-byte alignment - * we try to respect that. If you find an option to let gcc squeeze - * the stack more tightly then setting CPU_STACK_ALIGNMENT to 16 still - * doesn't waste much space since this only determines the *initial* - * alignment. - */ - -#define CPU_STACK_ALIGNMENT 16 - -/* macros */ - -#ifndef ASM -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if ( _new_level ) __asm__ volatile ( "cli" ); \ - else __asm__ volatile ( "sti" ); \ - } - -uint32_t _CPU_ISR_Get_level( void ); - -/* Make sure interrupt stack has space for ISR - * 'vector' arg at the top and that it is aligned - * properly. - */ - -#define _CPU_Interrupt_stack_setup( _lo, _hi ) \ - do { \ - _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \ - } while (0) - -#endif /* ASM */ - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 -#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 - -#ifndef ASM - -/* - * Stack alignment note: - * - * We want the stack to look to the '_entry_point' routine - * like an ordinary stack frame as if '_entry_point' was - * called from C-code. - * Note that '_entry_point' is jumped-to by the 'ret' - * instruction returning from _CPU_Context_switch() or - * _CPU_Context_restore() thus popping the _entry_point - * from the stack. - * However, _entry_point expects a frame to look like this: - * - * args [_Thread_Handler expects no args, however] - * ------ (alignment boundary) - * SP-> return_addr return here when _entry_point returns which (never happens) - * - * - * Hence we must initialize the stack as follows - * - * [arg1 ]: n/a - * [arg0 (aligned)]: n/a - * [ret. addr ]: NULL - * SP-> [jump-target ]: _entry_point - * - * When Context_switch returns it pops the _entry_point from - * the stack which then finds a standard layout. - */ - - - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - do { \ - uint32_t _stack; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \ - else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \ - \ - _stack = ((uint32_t)(_stack_base)) + (_size); \ - _stack &= ~ (CPU_STACK_ALIGNMENT - 1); \ - _stack -= 2*sizeof(proc_ptr*); /* see above for why we need to do this */ \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - (_the_context)->ebp = (void *) 0; \ - (_the_context)->esp = (void *) _stack; \ - } while (0) - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -#if defined(RTEMS_SMP) - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - uint32_t _CPU_SMP_Get_current_processor( void ); - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -#define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \ - } - -/* end of Context handler macros */ - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - uint32_t _error_lvalue = ( _error ); \ - __asm__ volatile ( "cli ; \ - movl %0,%%eax ; \ - hlt" \ - : "=r" ((_error_lvalue)) : "0" ((_error_lvalue)) \ - ); \ - } - -#endif /* ASM */ - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register uint16_t __value_in_register = (_value); \ - \ - _output = 0; \ - \ - __asm__ volatile ( "bsfw %0,%1 " \ - : "=r" (__value_in_register), "=r" (_output) \ - : "0" (__value_in_register), "1" (_output) \ - ); \ - } - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* functions */ - -#ifndef ASM -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Thread_Idle_body - * - * Use the halt instruction of low power mode of a particular i386 model. - */ - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner and avoid stack conflicts. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -#ifdef __SSE__ -#define _CPU_Context_save_fp(fp_context_pp) \ - do { \ - __asm__ __volatile__( \ - "fstcw %0" \ - :"=m"((*(fp_context_pp))->fpucw) \ - ); \ - __asm__ __volatile__( \ - "stmxcsr %0" \ - :"=m"((*(fp_context_pp))->mxcsr) \ - ); \ - } while (0) -#else -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ -#ifdef __SSE__ -#define _CPU_Context_restore_fp(fp_context_pp) \ - do { \ - __asm__ __volatile__( \ - "fldcw %0" \ - ::"m"((*(fp_context_pp))->fpucw) \ - :"fpcr" \ - ); \ - __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ - } while (0) -#else -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -#ifdef __SSE__ -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ __volatile__( \ - "finit" \ - : \ - : \ - :"st","st(1)","st(2)","st(3)", \ - "st(4)","st(5)","st(6)","st(7)", \ - "fpsr","fpcr" \ - ); \ - if ( _Thread_Executing->fp_context ) { \ - _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ - } \ - } while (0) -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/i386/rtems/score/types.h b/cpukit/score/cpu/i386/rtems/score/types.h deleted file mode 100644 index 40ccecb1f8..0000000000 --- a/cpukit/score/cpu/i386/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Intel I386 CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * i386 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void i386_isr; -typedef i386_isr ( *i386_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/asm.h b/cpukit/score/cpu/lm32/rtems/asm.h deleted file mode 100644 index 15046df81c..0000000000 --- a/cpukit/score/cpu/lm32/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/lm32.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h deleted file mode 100644 index e783331cc7..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpu.h +++ /dev/null @@ -1,1281 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Department Source - * - * This include file contains information pertaining to the LM32 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/lm32.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * L2 cache lines are 32 bytes in Milkymist SoC - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t ie; - uint32_t epc; -} Context_Control; - -/** - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t ra; - uint32_t ba; - uint32_t ea; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * The LM32 architecture manual simply states: "All memory accesses must be - * aligned to the size of the access", and there is no hardware support - * whatsoever for 64-bit numbers. - * (lm32_archman.pdf, July 2009, p. 15) - */ -#define CPU_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. - * - * - * Port Specific Information: - * - * Stack is software-managed - */ -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - lm32_disable_interrupts( _isr_cookie ); - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - lm32_enable_interrupts( _isr_cookie ); - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - lm32_flash_interrupts( _isr_cookie ); - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \ - } - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -extern char _gp[]; - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - do { \ - uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - (void) _isr; /* avoid warning for being unused */ \ - (_the_context)->gp = (uint32_t)_gp; \ - (_the_context)->fp = (uint32_t)_stack; \ - (_the_context)->sp = (uint32_t)_stack; \ - (_the_context)->ra = (uint32_t)(_entry_point); \ - } while ( 0 ) - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) -#if 0 - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) -#if 0 - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** @} */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** @} */ - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -static inline uint16_t CPU_swap_u16(uint16_t v) -{ - return v << 8 | v >> 8; -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h b/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h deleted file mode 100644 index 3909c1d608..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/lm32/rtems/score/types.h b/cpukit/score/cpu/lm32/rtems/score/types.h deleted file mode 100644 index c0fc8a8a89..0000000000 --- a/cpukit/score/cpu/lm32/rtems/score/types.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file - * - * @brief LM32 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Lattice lm32 processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, - * Micro-Research Finland Oy - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/asm.h b/cpukit/score/cpu/m32c/rtems/asm.h deleted file mode 100644 index f3f244d066..0000000000 --- a/cpukit/score/cpu/m32c/rtems/asm.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/m32c.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * @see __USER_LABEL_PREFIX__ - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** - * This macro is used to denote the beginning of a data declaration section. - */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @see PUBLIC(sym) .globl SYM (sym) - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h b/cpukit/score/cpu/m32c/rtems/score/cpu.h deleted file mode 100644 index fdee5729ed..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpu.h +++ /dev/null @@ -1,1229 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Dependent Source - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/m32c.h> - -/* conditional compilation parameters */ - -#define RTEMS_USE_16_BIT_OBJECT - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "M32C_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( M32C_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -#define CPU_CONTEXT_FP_SIZE 0 - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (2))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * @ingroup Management - * - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - /** This will contain the stack pointer. */ - uint32_t sp; - /** This will contain the frame base pointer. */ - uint32_t fb; -} Context_Control; - -/** - * @ingroup Management - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -/** - * @ingroup Management - * - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** - * This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - * - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** This defines the highest interrupt vector number for this port. */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (2048L) - -#ifdef __m32cm_cpu__ - #define CPU_SIZEOF_POINTER 4 -#else - #define CPU_SIZEOF_POINTER 2 -#endif - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 2 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT 4 - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - int _flg; \ - m32c_get_flg( _flg ); \ - _isr_cookie = _flg; \ - __asm__ volatile( "fclr I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable(_isr_cookie) \ - do { \ - int _flg = (int) (_isr_cookie); \ - m32c_set_flg( _flg ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - int _flg = (int) (_isr_cookie); \ - m32c_set_flg( _flg ); \ - __asm__ volatile( "fclr I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - *This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - do { \ - if (_new_level) __asm__ volatile( "fclr I" ); \ - else __asm__ volatile( "fset I" ); \ - } while(0) - -/** - * @ingroup CPUInterrupt - * - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/** - * @ingroup CPUContext - * - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/** @} */ - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h deleted file mode 100644 index 451c022d75..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/m32c/rtems/score/types.h b/cpukit/score/cpu/m32c/rtems/score/types.h deleted file mode 100644 index 11e0a0ceb4..0000000000 --- a/cpukit/score/cpu/m32c/rtems/score/types.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @brief M32C CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * m32c processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef unsigned long CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -/** This defines the return type for an ISR entry point. */ -typedef void m32c_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef m32c_isr ( *m32c_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m32r/rtems/asm.h b/cpukit/score/cpu/m32r/rtems/asm.h deleted file mode 100644 index 11f5b876b9..0000000000 --- a/cpukit/score/cpu/m32r/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/m32r.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * NOTE: This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu.h b/cpukit/score/cpu/m32r/rtems/score/cpu.h deleted file mode 100644 index 9ad41cd2c6..0000000000 --- a/cpukit/score/cpu/m32r/rtems/score/cpu.h +++ /dev/null @@ -1,1272 +0,0 @@ -/** - * @file - * - * @brief Intel M32R CPU Dependent Source - * - * This include file contains information pertaining to the XXX - * processor. - * - * NOTE: This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -/* - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/m32r.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * NOTE: In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "M32R_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( M32R_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - /** r8 -- temporary register */ - uint32_t r8; - /** r9 -- temporary register */ - uint32_t r9; - /** r10 -- temporary register */ - uint32_t r10; - /** r11 -- temporary register */ - uint32_t r11; - /** r12 -- may be global pointer */ - uint32_t r12; - /** r13 -- frame pointer */ - uint32_t r13_fp; - /** r14 -- link register (aka return pointer */ - uint32_t r14_lr; - /** r15 -- stack pointer */ - uint32_t r15_sp; - /** dsp accumulator low order 32-bits */ - uint32_t acc_low; - /** dsp accumulator high order 32-bits */ - uint32_t acc_high; -} Context_Control; - -/** - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r15_sp - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -static inline void _CPU_ISR_Set_level( unsigned int new_level ) -{ -} - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * NOTE: This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * TODO: As of 8 October 2014, this method is not implemented. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @brief Initialize CPU context. - * - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - size_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt( _source, _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/** @} */ - -/* functions */ - -/** - * @brief CPU initialization. - * - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * NOTE: May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h deleted file mode 100644 index ac6aac41a8..0000000000 --- a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file - * - * @brief Intel M32R Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/m32r/rtems/score/types.h b/cpukit/score/cpu/m32r/rtems/score/types.h deleted file mode 100644 index 3ee57f2e57..0000000000 --- a/cpukit/score/cpu/m32r/rtems/score/types.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * - * @brief Intel M32R CPU Type Definitions - * - * This include file contains type definitions pertaining to the Intel - * m32r processor family. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -/** This defines the return type for an ISR entry point. */ -typedef void m32r_isr; - -/** This defines the prototype for an ISR entry point. */ -typedef m32r_isr ( *m32r_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/asm.h b/cpukit/score/cpu/m68k/rtems/asm.h deleted file mode 100644 index cbd2a7f8b2..0000000000 --- a/cpukit/score/cpu/m68k/rtems/asm.h +++ /dev/null @@ -1,152 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT0 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT0 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) -#define sp REG (sp) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) -#define vbr REG (vbr) -#define dfc REG (dfc) -#define sfc REG (sfc) - -/* mcf52xx special regs */ -#define cacr REG (cacr) -#define acr0 REG (acr0) -#define acr1 REG (acr1) -#define rambar0 REG (rambar0) -#define mbar REG (mbar) - -/* additional v4e special regs */ -#define rambar1 REG (rambar1) -#define macsr REG (macsr) -#define acc0 REG (acc0) -#define acc1 REG (acc1) -#define acc2 REG (acc2) -#define acc3 REG (acc3) -#define accext01 REG (accext01) -#define accext23 REG (accext23) -#define mask REG (mask) - - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) -#define fpsr REG (fpsr) - - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h deleted file mode 100644 index 7fcbac54a8..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ /dev/null @@ -1,780 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Dependent Source - * - * This include file contains information pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/m68k.h> - -/* conditional compilation parameters */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * M68K Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Use the m68k's hardware interrupt stack support and have the - * interrupt manager allocate the memory for it. - */ - -#if ( M68K_HAS_SEPARATE_STACKS == 1) -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 -#else -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 -#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 -#endif -#define CPU_ALLOCATE_INTERRUPT_STACK 1 - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Some family members have no FP, some have an FPU such as the - * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040). - * - * NOTE: If on a CPU without hardware FP, then one can use software - * emulation. The gcc software FP emulation code has data which - * must be contexted switched on a per task basis. - */ - -#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) - #define CPU_HARDWARE_FP TRUE - #define CPU_SOFTWARE_FP FALSE -#else - #define CPU_HARDWARE_FP FALSE - #if defined( __GNUC__ ) - #define CPU_SOFTWARE_FP TRUE - #else - #define CPU_SOFTWARE_FP FALSE - #endif -#endif - -/* - * All tasks are not by default floating point tasks on this CPU. - * The IDLE task does not have a floating point context on this CPU. - * It is safe to use the deferred floating point context switch - * algorithm on this CPU. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE -#define CPU_IDLE_TASK_IS_FP FALSE -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE -#define CPU_STACK_GROWS_UP FALSE -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (4))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) - #if defined( __mc68060__ ) - #define M68K_FP_STATE_SIZE 16 - #else - #define M68K_FP_STATE_SIZE 216 - #endif -#endif - -#ifndef ASM - -/* structures */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Basic integer context for the m68k family. - */ - -typedef struct { - uint32_t sr; /* (sr) status register */ - uint32_t d2; /* (d2) data register 2 */ - uint32_t d3; /* (d3) data register 3 */ - uint32_t d4; /* (d4) data register 4 */ - uint32_t d5; /* (d5) data register 5 */ - uint32_t d6; /* (d6) data register 6 */ - uint32_t d7; /* (d7) data register 7 */ - void *a2; /* (a2) address register 2 */ - void *a3; /* (a3) address register 3 */ - void *a4; /* (a4) address register 4 */ - void *a5; /* (a5) address register 5 */ - void *a6; /* (a6) address register 6 */ - void *a7_msp; /* (a7) master stack pointer */ - #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) - uint8_t fpu_dis; - #endif -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->a7_msp - -/* - * Floating point context areas and support routines - */ - -#if ( CPU_SOFTWARE_FP == TRUE ) - /* - * This is the same as gcc's view of the software FP condition code - * register _fpCCR. The implementation of the emulation code is - * in the gcc-VERSION/config/m68k directory. This structure is - * correct as of gcc 2.7.2.2. - */ - typedef struct { - uint16_t _exception_bits; - uint16_t _trap_enable_bits; - uint16_t _sticky_bits; - uint16_t _rounding_mode; - uint16_t _format; - uint16_t _last_operation; - union { - float sf; - double df; - } _operand1; - union { - float sf; - double df; - } _operand2; - } Context_Control_fp; - - /* - * This software FP implementation is only for GCC. - */ - #define _CPU_Context_Fp_start( _base, _offset ) \ - ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) - - #define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - Context_Control_fp *_fp; \ - _fp = *(Context_Control_fp **)_fp_area; \ - _fp->_exception_bits = 0; \ - _fp->_trap_enable_bits = 0; \ - _fp->_sticky_bits = 0; \ - _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \ - _fp->_format = 0; /* NIL */ \ - _fp->_last_operation = 0; /* NOOP */ \ - _fp->_operand1.df = 0; \ - _fp->_operand2.df = 0; \ - } -#endif - -#if ( CPU_HARDWARE_FP == TRUE ) - #if defined( __mcoldfire__ ) - /* We need memset() to initialize the FP context */ - #include <string.h> - - #if ( M68K_HAS_FPU == 1 ) - /* - * The Cache Control Register (CACR) has write-only access. It is also - * used to enable and disable the FPU. We need to maintain a copy of - * this register to allow per thread values. - */ - extern uint32_t _CPU_cacr_shadow; - #endif - - /* We assume that each ColdFire core with a FPU has also an EMAC unit */ - typedef struct { - uint32_t emac_macsr; - uint32_t emac_acc0; - uint32_t emac_acc1; - uint32_t emac_acc2; - uint32_t emac_acc3; - uint32_t emac_accext01; - uint32_t emac_accext23; - uint32_t emac_mask; - #if ( M68K_HAS_FPU == 1 ) - uint16_t fp_state_format; - uint16_t fp_state_fpcr; - double fp_state_op; - uint32_t fp_state_fpsr; - - /* - * We need to save the FP Instruction Address Register (FPIAR), because - * a context switch can occur within a FP exception before the handler - * was able to save this register. - */ - uint32_t fp_fpiar; - - double fp_data [8]; - #endif - } Context_Control_fp; - - #define _CPU_Context_Fp_start( _base, _offset ) \ - ((void *) _Addresses_Add_offset( (_base), (_offset) )) - - /* - * The reset value for all context relevant registers except the FP data - * registers is zero. The reset value of the FP data register is NAN. The - * restore of the reset FP state will reset the FP data registers, so the - * initial value of them can be arbitrary here. - */ - #define _CPU_Context_Initialize_fp( _fp_area ) \ - memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) - #else - /* - * FP context save area for the M68881/M68882 and 68060 numeric - * coprocessors. - */ - typedef struct { - /* - * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE - * 96 bytes for FMOVEM FP0-7 - * 12 bytes for FMOVEM CREGS - * 4 bytes for non-null flag - */ - uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112]; - } Context_Control_fp; - - #define _CPU_Context_Fp_start( _base, _offset ) \ - ( \ - (void *) _Addresses_Add_offset( \ - (_base), \ - (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ - ) \ - ) - - #define _CPU_Context_Initialize_fp( _fp_area ) \ - { \ - uint32_t *_fp_context = (uint32_t *)*(_fp_area); \ - *(--(_fp_context)) = 0; \ - *(_fp_area) = (void *)(_fp_context); \ - } - #endif -#endif - -/* - * The following structures define the set of information saved - * on the current stack by RTEMS upon receipt of each exc/interrupt. - * These are not used by m68k handlers. - * The exception frame is for rdbg. - */ - -typedef struct { - uint32_t vecnum; /* vector number */ -} CPU_Interrupt_frame; - -typedef struct { - uint32_t vecnum; /* vector number */ - uint32_t sr; /* status register */ - uint32_t pc; /* program counter */ - uint32_t d0, d1, d2, d3, d4, d5, d6, d7; - uint32_t a0, a1, a2, a3, a4, a5, a6, a7; -} CPU_Exception_frame; - -/* variables */ - -extern void* _VBR; - -#if ( M68K_HAS_VBR == 0 ) - -/* - * Table of ISR handler entries that resides in RAM. The FORMAT/ID is - * pushed onto the stack. This is not is the same order as VBR processors. - * The ISR handler takes the format and uses it for dispatching the user - * handler. - * - * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS - * - */ - -typedef struct { - uint16_t move_a7; /* move #FORMAT_ID,%a7@- */ - uint16_t format_id; - uint16_t jmp; /* jmp _ISR_Handlers */ - uint32_t isr_handler; -} _CPU_ISR_handler_entry; - -#define M68K_MOVE_A7 0x3F3C -#define M68K_JMP 0x4EF9 - - /* points to jsr-exception-table in targets wo/ VBR register */ -SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; - -#endif /* M68K_HAS_VBR */ - -#endif /* ASM */ - -/* constants */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */ - -/* - * context size area for floating point - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * extra stack required by the MPCI receive server thread - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * m68k family supports 256 distinct vectors. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Minimum size of a thread's stack. - */ - -#define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE - -/* - * Maximum priority of a thread. Note based from 0 which is the idle task. - */ -#define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM - -#define CPU_SIZEOF_POINTER 4 - -/* - * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries. - */ - -#define CPU_ALIGNMENT 4 -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * On m68k thread stacks require no further alignment after allocation - * from the Workspace. - */ - -#define CPU_STACK_ALIGNMENT 0 - -#ifndef ASM - -/* macros */ - -/* - * ISR handler macros - * - * These macros perform the following functions: - * + initialize the RTEMS vector table - * + disable all maskable CPU interrupts - * + restore previous interrupt level (enable) - * + temporarily restore interrupts (flash) - * + set a particular level - */ - -#define _CPU_Initialize_vectors() - -#define _CPU_ISR_Disable( _level ) \ - m68k_disable_interrupts( _level ) - -#define _CPU_ISR_Enable( _level ) \ - m68k_enable_interrupts( _level ) - -#define _CPU_ISR_Flash( _level ) \ - m68k_flash_interrupts( _level ) - -#define _CPU_ISR_Set_level( _newlevel ) \ - m68k_set_interrupt_level( _newlevel ) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* - * Context handler macros - * - * These macros perform the following functions: - * + initialize a context area - * + restart the current thread - * + calculate the initial pointer into a FP context area - * + initialize an FP context area - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* end of Context handler macros */ - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * Fatal Error manager macros - * - * These macros perform the following functions: - * + disable interrupts and halt the CPU - */ - -#if ( defined(__mcoldfire__) ) -#define _CPU_Fatal_halt( _source, _error ) \ - { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ - "or.l %2,%%d0\n\t" \ - "move.w %%d0,%%sr\n\t" \ - "move.l %1,%%d0\n\t" \ - "move.l #0xDEADBEEF,%%d1\n\t" \ - "halt" \ - : "=g" (_error) \ - : "0" (_error), "d"(0x0700) \ - : "d0", "d1" ); \ - } -#else -#define _CPU_Fatal_halt( _source, _error ) \ - { __asm__ volatile( "movl %0,%%d0; " \ - "orw #0x0700,%%sr; " \ - "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ - } -#endif - -/* end of Fatal Error manager macros */ - -/* - * Bitfield handler macros - * - * These macros perform the following functions: - * + scan for the highest numbered (MSB) set in a 16 bit bitfield - * - * NOTE: - * - * It appears that on the M68020 bitfield are always 32 bits wide - * when in a register. This code forces the bitfield to be in - * memory (it really always is anyway). This allows us to - * have a real 16 bit wide bitfield which operates "correctly." - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE FALSE -#define CPU_USE_GENERIC_BITFIELD_DATA FALSE - -#if ( M68K_HAS_BFFFO != 1 ) -/* - * Lookup table for BFFFO simulation - */ -extern const unsigned char _CPU_m68k_BFFFO_table[256]; -#endif - -#if ( M68K_HAS_BFFFO == 1 ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); - -#elif ( __mcfisaaplus__ ) - /* This is simplified by the fact that RTEMS never calls it with _value=0 */ -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - __asm__ volatile ( \ - " swap %0\n" \ - " ff1.l %0\n" \ - : "=d" ((_output)) \ - : "0" ((_value)) \ - : "cc" ) ; - -#else -/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in - _CPU_Priority_bits_index is not needed), handles the 0 case, and - does not molest _value -- jsg */ -#if ( defined(__mcoldfire__) ) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( \ - " clr.l %1\n" \ - " move.w %2,%1\n" \ - " lsr.l #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1),%0\n" \ - " bra.s 0f\n" \ - "1: move.w %2,%1\n" \ - " move.b (%3,%1),%0\n" \ - " addq.l #8,%0\n" \ - "0: and.l #0xff,%0\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#elif ( M68K_HAS_EXTB_L == 1 ) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " extb.l %0\n" \ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#else -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - register int dumby; \ - \ - __asm__ volatile ( " move.w %2,%1\n" \ - " lsr.w #8,%1\n" \ - " beq.s 1f\n" \ - " move.b (%3,%1.w),%0\n" \ - " and.l #0x000000ff,%0\n"\ - " bra.s 0f\n" \ - "1: moveq.l #8,%0\n" \ - " add.b (%3,%2.w),%0\n" \ - "0:\n" \ - : "=&d" ((_output)), "=&d" ((dumby)) \ - : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ - : "cc" ) ; \ - } -#endif - -#endif - -/* end of Bitfield handler macros */ - -/* - * Priority handler macros - * - * These macros perform the following functions: - * + return a mask with the bit for this major/minor portion of - * of thread priority set. - * + translate the bit number returned by "Bitfield_find_first_bit" - * into an index into the thread ready chain bit maps - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x8000 >> (_bit_number) ) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -void _CPU_Context_Restart_self( - Context_Control *the_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** - * This method prints the CPU exception frame. - * - * @param[in] frame points to the frame to be printed - */ -void _CPU_Exception_frame_print( - const CPU_Exception_frame *frame -); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#if (M68K_HAS_FPSP_PACKAGE == 1) -/* - * Hooks for the Floating Point Support Package (FPSP) provided by Motorola - * - * NOTES: - * - * Motorola 68k family CPU's before the 68040 used a coprocessor - * (68881 or 68882) to handle floating point. The 68040 has internal - * floating point support -- but *not* the complete support provided by - * the 68881 or 68882. The leftover functions are taken care of by the - * M68040 Floating Point Support Package. Quoting from the MC68040 - * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040): - * - * "When used with the M68040FPSP, the MC68040 FPU is fully - * compliant with IEEE floating-point standards." - * - * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and - * is invoked early in the application code to ensure that proper FP - * behavior is installed. This is not left to the BSP to call, since - * this would force all applications using that BSP to use FPSP which - * is not necessarily desirable. - * - * There is a similar package for the 68060 but RTEMS does not yet - * support the 68060. - */ - -void M68KFPSPInstallExceptionHandlers (void); - -SCORE_EXTERN int (*_FPSP_install_raw_handler)( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#endif - - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/m68k/rtems/score/types.h b/cpukit/score/cpu/m68k/rtems/score/types.h deleted file mode 100644 index 96f9a4c37e..0000000000 --- a/cpukit/score/cpu/m68k/rtems/score/types.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @brief Motorola M68K CPU Type Definitions - * - * This include file contains type definitions pertaining to the Motorola - * m68xxx processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h deleted file mode 100644 index 9c84f61990..0000000000 --- a/cpukit/score/cpu/mips/rtems/asm.h +++ /dev/null @@ -1,160 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ -/* @(#)asm.h 03/15/96 1.1 */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/system.h> -#include <rtems/score/cpuopts.h> -#include <rtems/score/mips.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Debugger macros for assembly language routines. Allows the - * programmer to set up the necessary stack frame info - * required by debuggers to do stack traces. - */ - -#ifndef XDS -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl name; \ - .ent name; \ -name:; \ - .frame frm_reg,offset,ret_reg -#define ENDFRAME(name) \ - .end name -#else -#define FRAME(name,frm_reg,offset,ret_reg) \ - .globl _##name;\ -_##name: -#define ENDFRAME(name) -#endif /* XDS */ - -/* - * Hardware Floating Point Registers - */ - -#define R_FP0 0 -#define R_FP1 1 -#define R_FP2 2 -#define R_FP3 3 -#define R_FP4 4 -#define R_FP5 5 -#define R_FP6 6 -#define R_FP7 7 -#define R_FP8 8 -#define R_FP9 9 -#define R_FP10 10 -#define R_FP11 11 -#define R_FP12 12 -#define R_FP13 13 -#define R_FP14 14 -#define R_FP15 15 -#define R_FP16 16 -#define R_FP17 17 -#define R_FP18 18 -#define R_FP19 19 -#define R_FP20 20 -#define R_FP21 21 -#define R_FP22 22 -#define R_FP23 23 -#define R_FP24 24 -#define R_FP25 25 -#define R_FP26 26 -#define R_FP27 27 -#define R_FP28 28 -#define R_FP29 29 -#define R_FP30 30 -#define R_FP31 31 - -#endif -/* end of include file */ - diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h deleted file mode 100644 index ac589d2a68..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ /dev/null @@ -1,1181 +0,0 @@ -/** - * @file - * - * @brief Mips CPU Dependent Header File - */ - -/* - * Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and - * Joel Sherrill <joel@OARcorp.com>. - * - * These changes made the code conditional on standard cpp predefines, - * merged the mips1 and mips3 code sequences as much as possible, - * and moved some of the assembly code to C. Alan did much of the - * initial analysis and rework. Joel took over from there and - * wrote the JMR3904 BSP so this could be tested. Joel also - * added the new interrupt vectoring support in libcpu and - * tried to better support the various interrupt controllers. - * - */ - -/* - * Original MIP64ORION port by Craig Lebakken <craigl@transition.com> - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of Transition Networks not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * Transition Networks makes no representations about the suitability - * of this software for any purpose. - * - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -/** - * @defgroup ScoreCPU CPU CPU - * - * @ingroup Score - * - */ -/**@{*/ - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/mips.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * MIPS Specific Information: - * - * Up to and including RTEMS 4.10, the MIPS port used simple vectored - * interrupts. But this was changed to the PIC model after 4.10. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - - - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MIPS_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( MIPS_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Mips Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -/* we can use the low power wait instruction for the IDLE thread */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -/* our stack grows down */ -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -/* our cache line size is 16 bytes */ -#if __GNUC__ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) -#else -#define CPU_STRUCTURE_ALIGNMENT -#endif - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -/* __MIPSEB__ or __MIPSEL__ is defined by GCC based on -EB or -EL command line options */ -#if defined(__MIPSEB__) -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#elif defined(__MIPSEL__) -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#else -#error "Unknown endianness" -#endif - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000ff - -#define CPU_SIZEOF_POINTER 4 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */ -#if (__mips == 1) || (__mips == 32) -#define __MIPS_REGISTER_TYPE uint32_t -#define __MIPS_FPU_REGISTER_TYPE uint32_t -#elif __mips == 3 -#define __MIPS_REGISTER_TYPE uint64_t -#define __MIPS_FPU_REGISTER_TYPE uint64_t -#else -#error "mips register size: unknown architecture level!!" -#endif -typedef struct { - __MIPS_REGISTER_TYPE s0; - __MIPS_REGISTER_TYPE s1; - __MIPS_REGISTER_TYPE s2; - __MIPS_REGISTER_TYPE s3; - __MIPS_REGISTER_TYPE s4; - __MIPS_REGISTER_TYPE s5; - __MIPS_REGISTER_TYPE s6; - __MIPS_REGISTER_TYPE s7; - __MIPS_REGISTER_TYPE sp; - __MIPS_REGISTER_TYPE fp; - __MIPS_REGISTER_TYPE ra; - __MIPS_REGISTER_TYPE c0_sr; - __MIPS_REGISTER_TYPE c0_epc; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (uintptr_t) (_context)->sp - -/* WARNING: If this structure is modified, the constants in cpu.h - * must also be updated. - */ - -typedef struct { -#if ( CPU_HARDWARE_FP == TRUE ) - __MIPS_FPU_REGISTER_TYPE fp0; - __MIPS_FPU_REGISTER_TYPE fp1; - __MIPS_FPU_REGISTER_TYPE fp2; - __MIPS_FPU_REGISTER_TYPE fp3; - __MIPS_FPU_REGISTER_TYPE fp4; - __MIPS_FPU_REGISTER_TYPE fp5; - __MIPS_FPU_REGISTER_TYPE fp6; - __MIPS_FPU_REGISTER_TYPE fp7; - __MIPS_FPU_REGISTER_TYPE fp8; - __MIPS_FPU_REGISTER_TYPE fp9; - __MIPS_FPU_REGISTER_TYPE fp10; - __MIPS_FPU_REGISTER_TYPE fp11; - __MIPS_FPU_REGISTER_TYPE fp12; - __MIPS_FPU_REGISTER_TYPE fp13; - __MIPS_FPU_REGISTER_TYPE fp14; - __MIPS_FPU_REGISTER_TYPE fp15; - __MIPS_FPU_REGISTER_TYPE fp16; - __MIPS_FPU_REGISTER_TYPE fp17; - __MIPS_FPU_REGISTER_TYPE fp18; - __MIPS_FPU_REGISTER_TYPE fp19; - __MIPS_FPU_REGISTER_TYPE fp20; - __MIPS_FPU_REGISTER_TYPE fp21; - __MIPS_FPU_REGISTER_TYPE fp22; - __MIPS_FPU_REGISTER_TYPE fp23; - __MIPS_FPU_REGISTER_TYPE fp24; - __MIPS_FPU_REGISTER_TYPE fp25; - __MIPS_FPU_REGISTER_TYPE fp26; - __MIPS_FPU_REGISTER_TYPE fp27; - __MIPS_FPU_REGISTER_TYPE fp28; - __MIPS_FPU_REGISTER_TYPE fp29; - __MIPS_FPU_REGISTER_TYPE fp30; - __MIPS_FPU_REGISTER_TYPE fp31; - uint32_t fpcs; -#endif -} Context_Control_fp; - -/* - * This struct reflects the stack frame employed in ISR_Handler. Note - * that the ISR routine save some of the registers to this frame for - * all interrupts and exceptions. Other registers are saved only on - * exceptions, while others are not touched at all. The untouched - * registers are not normally disturbed by high-level language - * programs so they can be accessed when required. - * - * The registers and their ordering in this struct must directly - * correspond to the layout and ordering of * shown in iregdef.h, - * as cpu_asm.S uses those definitions to fill the stack frame. - * This struct provides access to the stack frame for C code. - * - * Similarly, this structure is used by debugger stubs and exception - * processing routines so be careful when changing the format. - * - * NOTE: The comments with this structure and cpu_asm.S should be kept - * in sync. When in doubt, look in the code to see if the - * registers you're interested in are actually treated as expected. - * The order of the first portion of this structure follows the - * order of registers expected by gdb. - */ - -typedef struct -{ - __MIPS_REGISTER_TYPE r0; /* 0 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE at; /* 1 -- saved always */ - __MIPS_REGISTER_TYPE v0; /* 2 -- saved always */ - __MIPS_REGISTER_TYPE v1; /* 3 -- saved always */ - __MIPS_REGISTER_TYPE a0; /* 4 -- saved always */ - __MIPS_REGISTER_TYPE a1; /* 5 -- saved always */ - __MIPS_REGISTER_TYPE a2; /* 6 -- saved always */ - __MIPS_REGISTER_TYPE a3; /* 7 -- saved always */ - __MIPS_REGISTER_TYPE t0; /* 8 -- saved always */ - __MIPS_REGISTER_TYPE t1; /* 9 -- saved always */ - __MIPS_REGISTER_TYPE t2; /* 10 -- saved always */ - __MIPS_REGISTER_TYPE t3; /* 11 -- saved always */ - __MIPS_REGISTER_TYPE t4; /* 12 -- saved always */ - __MIPS_REGISTER_TYPE t5; /* 13 -- saved always */ - __MIPS_REGISTER_TYPE t6; /* 14 -- saved always */ - __MIPS_REGISTER_TYPE t7; /* 15 -- saved always */ - __MIPS_REGISTER_TYPE s0; /* 16 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s1; /* 17 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s2; /* 18 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s3; /* 19 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s4; /* 20 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s5; /* 21 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s6; /* 22 -- saved on exceptions */ - __MIPS_REGISTER_TYPE s7; /* 23 -- saved on exceptions */ - __MIPS_REGISTER_TYPE t8; /* 24 -- saved always */ - __MIPS_REGISTER_TYPE t9; /* 25 -- saved always */ - __MIPS_REGISTER_TYPE k0; /* 26 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE k1; /* 27 -- NOT FILLED IN, kernel tmp reg */ - __MIPS_REGISTER_TYPE gp; /* 28 -- saved always */ - __MIPS_REGISTER_TYPE sp; /* 29 -- saved on exceptions NOT RESTORED */ - __MIPS_REGISTER_TYPE fp; /* 30 -- saved always */ - __MIPS_REGISTER_TYPE ra; /* 31 -- saved always */ - __MIPS_REGISTER_TYPE c0_sr; /* 32 -- saved always, some bits are */ - /* manipulated per-thread */ - __MIPS_REGISTER_TYPE mdlo; /* 33 -- saved always */ - __MIPS_REGISTER_TYPE mdhi; /* 34 -- saved always */ - __MIPS_REGISTER_TYPE badvaddr; /* 35 -- saved on exceptions, read-only */ - __MIPS_REGISTER_TYPE cause; /* 36 -- saved on exceptions NOT restored */ - __MIPS_REGISTER_TYPE epc; /* 37 -- saved always, read-only register */ - /* but logically restored */ - __MIPS_FPU_REGISTER_TYPE f0; /* 38 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f1; /* 39 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f2; /* 40 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f3; /* 41 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f4; /* 42 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f5; /* 43 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f6; /* 44 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f7; /* 45 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f8; /* 46 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f9; /* 47 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f10; /* 48 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f11; /* 49 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f12; /* 50 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f13; /* 51 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f14; /* 52 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f15; /* 53 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f16; /* 54 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f17; /* 55 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f18; /* 56 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f19; /* 57 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f20; /* 58 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f21; /* 59 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f22; /* 60 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f23; /* 61 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f24; /* 62 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f25; /* 63 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f26; /* 64 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f27; /* 65 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f28; /* 66 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f29; /* 67 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f30; /* 68 -- saved if FP enabled */ - __MIPS_FPU_REGISTER_TYPE f31; /* 69 -- saved if FP enabled */ - __MIPS_REGISTER_TYPE fcsr; /* 70 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - __MIPS_REGISTER_TYPE feir; /* 71 -- saved on exceptions */ - /* (oddly not documented on MGV) */ - - /* GDB does not seem to care about anything past this point */ - - __MIPS_REGISTER_TYPE tlbhi; /* 72 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#if __mips == 1 - __MIPS_REGISTER_TYPE tlblo; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif -#if (__mips == 3) || (__mips == 32) - __MIPS_REGISTER_TYPE tlblo0; /* 73 - NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ -#endif - - __MIPS_REGISTER_TYPE inx; /* 74 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE rand; /* 75 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE ctxt; /* 76 -- NOT FILLED IN, doesn't exist on */ - /* all MIPS CPUs (at least MGV) */ - __MIPS_REGISTER_TYPE exctype; /* 77 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE mode; /* 78 -- NOT FILLED IN (not enough info) */ - __MIPS_REGISTER_TYPE prid; /* 79 -- NOT FILLED IN (not need to do so) */ - __MIPS_REGISTER_TYPE tar ; /* 80 -- target address register, filled on exceptions */ - /* end of __mips == 1 so NREGS == 81 */ -#if (__mips == 3) || (__mips == 32) - __MIPS_REGISTER_TYPE tlblo1; /* 81 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE pagemask; /* 82 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE wired; /* 83 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE count; /* 84 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE compare; /* 85 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE config; /* 86 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE lladdr; /* 87 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchlo; /* 88 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE watchhi; /* 89 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE ecc; /* 90 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE cacheerr; /* 91 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taglo; /* 92 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE taghi; /* 93 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE errpc; /* 94 -- NOT FILLED IN */ - __MIPS_REGISTER_TYPE xctxt; /* 95 -- NOT FILLED IN */ - /* end of __mips == 3 so NREGS == 96 */ -#endif - -} CPU_Interrupt_frame; - -typedef CPU_Interrupt_frame CPU_Exception_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (8 * 1024) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -void mips_vector_exceptions( CPU_Interrupt_frame *frame ); - -/* - * ISR handler macros - */ - -/* - * Declare the function that is present in the shared libcpu directory, - * that returns the processor dependent interrupt mask. - */ - -uint32_t mips_interrupt_mask( void ); - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \ - _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \ - } while(0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - unsigned int _scratch; \ - mips_get_sr( _scratch ); \ - mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \ - } while(0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _xlevel ) \ - do { \ - unsigned int _scratch2 = _xlevel; \ - _CPU_ISR_Enable( _scratch2 ); \ - _CPU_ISR_Disable( _scratch2 ); \ - _xlevel = _scratch2; \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * On the MIPS, 0 is all on. Non-zero is all off. This only - * manipulates the IEC. - */ - -uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */ - -void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */ - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * The per-thread status register holds the interrupt enable, FP enable - * and global interrupt enable for that thread. It means each thread can - * enable its own set of interrupts. If interrupts are disabled, RTEMS - * can still dispatch via blocking calls. This is the function of the - * "Interrupt Level", and on the MIPS, it controls the IEC bit and all - * the hardware interrupts as defined in the SR. Software ints - * are automatically enabled for all threads, as they will only occur under - * program control anyhow. Besides, the interrupt level parm is only 8 bits, - * and controlling the software ints plus the others would require 9. - * - * If the Interrupt Level is 0, all ints are on. Otherwise, the - * Interrupt Level should supply a bit pattern to impose on the SR - * interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6 - * apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of - * the Interrupt Level parameter is unused at this time. - * - * These are the only per-thread SR bits, the others are maintained - * globally & explicitly preserved by the Context Switch code in cpu_asm.s - */ - - -#if (__mips == 3) || (__mips == 32) -#define _INTON SR_IE -#if __mips_fpr==64 -#define _EXTRABITS SR_FR -#else -#define _EXTRABITS 0 -#endif /* __mips_fpr==64 */ -#endif /* __mips == 3 */ -#if __mips == 1 -#define _INTON SR_IEC -#define _EXTRABITS 0 /* make sure we're in user mode on MIPS1 processors */ -#endif /* __mips == 1 */ - - -void _CPU_Context_Initialize( - Context_Control *the_context, - uintptr_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * A floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#if ( CPU_HARDWARE_FP == TRUE ) -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - unsigned int _level; \ - _CPU_ISR_Disable(_level); \ - (void)_level; \ - loop: goto loop; \ - } while (0) - - -extern void mips_break( int error ); - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif - - - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/mips/rtems/score/types.h b/cpukit/score/cpu/mips/rtems/score/types.h deleted file mode 100644 index 01950cecef..0000000000 --- a/cpukit/score/cpu/mips/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file rtems/score/types.h - * - * @brief Type Definitions Pertaining to the MIPS Processor Family - * - * This include file contains type definitions pertaining to the MIPS - * processor family. - */ - -/* - * COPYRIGHT (c) 1989-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -/* @(#)mipstypes.h 08/20/96 1.4 */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -/** - * @defgroup ScoreTypes MIPS Processor Family Type Definitions - * - * @ingroup Score - * - */ -/**@{*/ - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void mips_isr; -typedef void ( *mips_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/**@}*/ -#endif diff --git a/cpukit/score/cpu/moxie/rtems/asm.h b/cpukit/score/cpu/moxie/rtems/asm.h deleted file mode 100644 index fdb182f32f..0000000000 --- a/cpukit/score/cpu/moxie/rtems/asm.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2011 - * Anthony Green - * - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * $Id: asm.h,v 1.9 2010/06/29 00:31:09 joel Exp $ - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#include <rtems/score/moxie.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ "$" -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define fp REG(fp) -#define sp REG(sp) -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE asm ( ".text -#define END_CODE "); -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/cpu.h b/cpukit/score/cpu/moxie/rtems/score/cpu.h deleted file mode 100644 index 297316bfeb..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/cpu.h +++ /dev/null @@ -1,1058 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the Moxie - * processor. - * - * Copyright (c) 2013 Anthony Green - * - * Based on code with the following copyright.. - * COPYRIGHT (c) 1989-2006, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/moxie.h> /* pick up machine definitions */ - -#include <rtems/bspIo.h> /* printk */ - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Should this target use 16 or 32 bit object Ids? - * - */ -#define RTEMS_USE_32_BIT_OBJECT - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * MOXIE Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "MOXIE_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HARDWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body - * must be provided and is the default IDLE thread body instead of - * _Internal_threads_Idle_thread_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - * MOXIE Specific Information: - * - * XXX - * The port initially called a BSP dependent routine called - * IDLE_Monitor. The idle task body can be overridden by - * the BSP in newer versions of RTEMS. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STRUCTURE_ALIGNMENT - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE -#define CPU_TIMESTAMP_USE_INT64 FALSE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - * - * MOXIE Specific Information: - * - * XXX - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * MOXIE Specific Information: - * - * XXX - */ - -#define nogap __attribute__ ((packed)) - -typedef struct { - void *fp nogap; - void *sp nogap; - uint32_t r0 nogap; - uint32_t r1 nogap; - uint32_t r2 nogap; - uint32_t r3 nogap; - uint32_t r4 nogap; - uint32_t r5 nogap; - uint32_t r6 nogap; - uint32_t r7 nogap; - uint32_t r8 nogap; - uint32_t r9 nogap; - uint32_t r10 nogap; - uint32_t r11 nogap; - uint32_t r12 nogap; - uint32_t r13 nogap; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef struct { - double some_float_register[2]; -} Context_Control_fp; - -typedef struct { - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - * - * MOXIE Specific Information: - * - * XXX - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * MOXIE Specific Information: - * - * XXX - */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * system initialization thread. Remember that in a multiprocessor - * system the system intialization thread becomes the MP server thread. - * - * MOXIE Specific Information: - * - * It is highly unlikely the MOXIE will get used in a multiprocessor system. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \ - (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_MINIMUM_SIZE (1536) - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - (_isr_cookie) = 0; \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - (_isr_cookie) = (_isr_cookie); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - _CPU_ISR_Enable( _isr_cookie ); \ - _CPU_ISR_Disable( _isr_cookie ); \ - } while (0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method is not implemented. - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - if (_new_level) asm volatile ( "nop\n" ); \ - else asm volatile ( "nop\n" ); \ - } - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - * MOXIE Specific Information: - * - * TODO: As of 7 October 2014, this method does not ensure that the context - * is set up with interrupts disabled/enabled as requested. - */ -#define CPU_CCR_INTERRUPTS_ON 0x80 -#define CPU_CCR_INTERRUPTS_OFF 0x00 - -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ - _isr, _entry_point, _is_fp, _tls_area ) \ - /* Locate Me */ \ - do { \ - uintptr_t _stack; \ - \ - (void) _is_fp; /* avoid warning for being unused */ \ - (void) _isr; /* avoid warning for being unused */ \ - _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ - *((proc_ptr *)(_stack)) = (_entry_point); \ - _stack -= 4; \ - (_the_context)->fp = (void *)_stack; \ - (_the_context)->sp = (void *)_stack; \ - } while (0) - - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) (_base) + (_offset) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * MOXIE Specific Information: - * - * XXX - */ -#define _CPU_Fatal_halt( _source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source,_error); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * MOXIE Specific Information: - * - * XXX - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - * MOXIE Specific Information: - * - * XXX - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * MOXIE Specific Information: - * - * XXX - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Internal_threads_Idle_thread_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * MOXIE Specific Information: - * - * XXX - */ -void *_CPU_Thread_Idle_body( uint32_t ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - * MOXIE Specific Information: - * - * XXX - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** - * @brief The set of registers that specifies the complete processor state. - * - * The CPU exception frame may be available in fatal error conditions like for - * example illegal opcodes, instruction fetch errors, or data access errors. - * - * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and - * rtems_exception_frame_print(). - */ -typedef struct { - uint32_t integer_registers [16]; -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * MOXIE Specific Information: - * - * This is the generic implementation. - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/moxie/rtems/score/types.h b/cpukit/score/cpu/moxie/rtems/score/types.h deleted file mode 100644 index 64427a831a..0000000000 --- a/cpukit/score/cpu/moxie/rtems/score/types.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file rtems/score/types.h - */ - -/* - * This file contains information pertaining to the Moxie processor. - * - * COPYRIGHT (c) 2011 - * Anthony Green - * - * Based on code with the following copyright... - * COPYRIGHT (c) 1989-1999, 2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#include <stdbool.h> -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void moxie_isr; -typedef void ( *moxie_isr_entry )( void ); - -#ifdef RTEMS_DEPRECATED_TYPES -typedef bool boolean; /* Boolean value */ -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/asm.h b/cpukit/score/cpu/nios2/rtems/asm.h deleted file mode 100644 index 45ccd8b050..0000000000 --- a/cpukit/score/cpu/nios2/rtems/asm.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/nios2.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h deleted file mode 100644 index fdb9d8aaef..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ /dev/null @@ -1,381 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II CPU Department Source - */ - -/* - * Copyright (c) 2011 embedded brains GmbH - * - * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) - * - * COPYRIGHT (c) 1989-2004. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/nios2.h> - -/* - * TODO: Run the timing tests and figure out what is better. - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -#define CPU_ISR_PASSES_FRAME_POINTER FALSE - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_CONTEXT_FP_SIZE 0 - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -#define CPU_STACK_GROWS_UP FALSE - -#define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -#define CPU_BIG_ENDIAN FALSE - -#define CPU_LITTLE_ENDIAN TRUE - -#define CPU_STACK_MINIMUM_SIZE (4 * 1024) - -#define CPU_SIZEOF_POINTER 4 - -/* - * Alignment value according to "Nios II Processor Reference" chapter 7 - * "Application Binary Interface" section "Memory Alignment". - */ -#define CPU_ALIGNMENT 4 - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * Alignment value according to "Nios II Processor Reference" chapter 7 - * "Application Binary Interface" section "Stacks". - */ -#define CPU_STACK_ALIGNMENT 4 - -/* - * A Nios II configuration with an external interrupt controller (EIC) supports - * up to 64 interrupt levels. A Nios II configuration with an internal - * interrupt controller (IIC) has only two interrupt levels (enabled and - * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will - * take care about configuration specific mappings. - */ -#define CPU_MODES_INTERRUPT_MASK 0x3f - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @brief Thread register context. - * - * The thread register context covers the non-volatile registers, the thread - * stack pointer, the return address, and the processor status. - * - * There is no need to save the global pointer (gp) since it is a system wide - * constant and set-up with the C runtime environment. - * - * The @a thread_dispatch_disabled field is used for the external interrupt - * controller (EIC) support. - * - * @see _Nios2_Thread_dispatch_disabled - */ -typedef struct { - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t fp; - uint32_t status; - uint32_t sp; - uint32_t ra; - uint32_t thread_dispatch_disabled; - uint32_t stack_mpubase; - uint32_t stack_mpuacc; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->sp - -typedef void CPU_Interrupt_frame; - -typedef struct { - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t gp; - uint32_t fp; - uint32_t sp; - uint32_t ra; - uint32_t et; - uint32_t ea; - uint32_t status; - uint32_t ienable; - uint32_t ipending; -} CPU_Exception_frame; - -#define _CPU_Initialize_vectors() - -/** - * @brief Macro to disable interrupts. - * - * The processor status before disabling the interrupts will be stored in - * @a _isr_cookie. This value will be used in _CPU_ISR_Flash() and - * _CPU_ISR_Enable(). - * - * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in - * the status register representing the interrupt level. The global symbol - * _Nios2_ISR_Status_bits will be used to set the bits representing an - * interrupt level that disables interrupts. Both global symbols must be - * provided by the board support package. - * - * In case the Nios II uses the internal interrupt controller (IIC), then only - * the PIE status bit is used. - * - * In case the Nios II uses the external interrupt controller (EIC), then the - * RSIE status bit or the IL status field is used depending on the interrupt - * handling variant and the shadow register usage. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - int _tmp; \ - __asm__ volatile ( \ - "rdctl %0, status\n" \ - "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ - "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ - "and %1, %0, %1\n" \ - "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ - "wrctl status, %1" \ - : "=&r" (_isr_cookie), "=&r" (_tmp) \ - ); \ - } while ( 0 ) - -/** - * @brief Macro to restore the processor status. - * - * The @a _isr_cookie must contain the processor status returned by - * _CPU_ISR_Disable(). The value is not modified. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - __builtin_wrctl( 0, (int) _isr_cookie ) - -/** - * @brief Macro to restore the processor status and disable the interrupts - * again. - * - * The @a _isr_cookie must contain the processor status returned by - * _CPU_ISR_Disable(). The value is not modified. - * - * This flash code is optimal for all Nios II configurations. The rdctl does - * not flush the pipeline and has only a late result penalty. The wrctl on - * the other hand leads to a pipeline flush. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - int _status = __builtin_rdctl( 0 ); \ - __builtin_wrctl( 0, (int) _isr_cookie ); \ - __builtin_wrctl( 0, _status ); \ - } while ( 0 ) - -/** - * @brief Sets the interrupt level for the executing thread. - * - * The valid values of @a new_level depend on the Nios II configuration. A - * value of zero represents enabled interrupts in all configurations. - * - * @see _CPU_ISR_Get_level() - */ -void _CPU_ISR_Set_level( uint32_t new_level ); - -/** - * @brief Returns the interrupt level of the executing thread. - * - * @retval 0 Interrupts are enabled. - * @retval otherwise The value depends on the Nios II configuration. In case - * of an internal interrupt controller (IIC) the only valid value is one which - * indicates disabled interrupts. In case of an external interrupt controller - * (EIC) there are two possibilities. Firstly if the RSIE status bit is used - * to disable interrupts, then one is the only valid value indicating disabled - * interrupts. Secondly if the IL status field is used to disable interrupts, - * then this value will be returned. Interrupts are disabled at the maximum - * level specified by the _Nios2_ISR_Status_bits. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -void _CPU_Fatal_halt( uint32_t _source, uint32_t _error ) - RTEMS_NO_RETURN; - -/** - * @brief CPU initialization. - */ -void _CPU_Initialize( void ); - -/** - * @brief CPU ISR install raw handler. - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief CPU ISR install vector. - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -static inline uint32_t CPU_swap_u32( uint32_t value ) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - - return swapped; -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h deleted file mode 100644 index 81a19c8d69..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h deleted file mode 100644 index 6eaee5c829..0000000000 --- a/cpukit/score/cpu/nios2/rtems/score/types.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * - * @brief Altera Nios II CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * Altera Nios II processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void nios2_isr; -typedef void ( *nios2_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/asm.h b/cpukit/score/cpu/or1k/rtems/asm.h deleted file mode 100644 index 4d2c22698b..0000000000 --- a/cpukit/score/cpu/or1k/rtems/asm.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * @file rtems/asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - */ - -/* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-1997. - * On-Line Applications Research Corporation (OAR). - * - */ - -#ifndef __OR1K_ASM_h -#define __OR1K_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/or1k.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h b/cpukit/score/cpu/or1k/rtems/score/cpu.h deleted file mode 100644 index 7d07de34b0..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpu.h +++ /dev/null @@ -1,1035 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains macros pertaining to the Opencores - * or1k processor family. - * - * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This file adapted from no_cpu example of the RTEMS distribution. - * The body has been modified for the Opencores OR1k implementation by - * Chris Ziomkowski. <chris@asics.ws> - * - */ - -#ifndef _OR1K_CPU_H -#define _OR1K_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#include <rtems/score/or1k.h> /* pick up machine definitions */ -#include <rtems/score/or1k-utility.h> -#include <rtems/score/types.h> -#ifndef ASM -#include <rtems/bspIo.h> -#include <stdint.h> -#include <stdio.h> /* for printk */ -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - * - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Currently, for or1k port, _ISR_Handler is responsible for switching to - * RTEMS dedicated interrupt task. - * - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - * - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 1 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "OR1K_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - * - * The CPU_SOFTWARE_FP is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Or1k Specific Information: - * - * At this time there are no implementations of Or1k that are - * expected to implement floating point. More importantly, the - * floating point architecture is expected to change significantly - * before such chips are fabricated. - */ - -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - * - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * Or1k Specific Information: - * - * This version of RTEMS is designed specifically to run with - * big endian architectures. If you want little endian, you'll - * have to make the appropriate adjustments here and write - * efficient routines for byte swapping. The Or1k architecture - * doesn't do this very well. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - */ - -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - */ - - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * - */ -#ifndef ASM -#ifdef OR1K_64BIT_ARCH -#define or1kreg uint64_t -#else -#define or1kreg uint32_t -#endif - -typedef struct { - uint32_t r1; /* Stack pointer */ - uint32_t r2; /* Frame pointer */ - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t r28; - uint32_t r29; - uint32_t r30; - uint32_t r31; - - uint32_t sr; /* Current supervision register non persistent values */ - uint32_t epcr; - uint32_t eear; - uint32_t esr; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r1 - -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Interrupt_frame; - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Or1k Specific Information: - * - */ - -#define CPU_CONTEXT_FP_SIZE 0 -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - * - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - */ - -#define CPU_ALIGNMENT 8 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * Size of a pointer. - * - * This must be an integer literal that can be used by the assembler. This - * value will be used to calculate offsets of structure members. These - * offsets will be used in assembler code. - */ -#define CPU_SIZEOF_POINTER 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - * - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - */ - -#define CPU_STACK_ALIGNMENT 0 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - * - */ - -static inline uint32_t or1k_interrupt_disable( void ) -{ - uint32_t sr; - sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); - - _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); - - return sr; -} - -static inline void or1k_interrupt_enable(uint32_t level) -{ - uint32_t sr; - - /* Enable interrupts and restore rs */ - sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; - _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); - -} - -#define _CPU_ISR_Disable( _level ) \ - _level = or1k_interrupt_disable() - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - * - */ - -#define _CPU_ISR_Enable( _level ) \ - or1k_interrupt_enable( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - * - */ - -#define _CPU_ISR_Flash( _level ) \ - do{ \ - _CPU_ISR_Enable( _level ); \ - _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ - } while(0) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - * - */ - -void _CPU_ISR_Set_level( uint32_t level ); - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * - */ - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - */ - -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - _OR1KSIM_CPU_Halt(); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - */ - - /* #define CPU_USE_GENERIC_BITFIELD_CODE FALSE */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - - /* Get a value between 0 and N where N is the bit size */ - /* This routine makes use of the fact that CPUCFGR defines - OB32S to have value 32, and OB64S to have value 64. If - this ever changes then this routine will fail. */ -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - asm volatile ("l.mfspr %0,r0,0x2 \n\t"\ - "l.andi %0,%0,0x60 \n\t"\ - "l.ff1 %1,%1,r0 \n\t"\ - "l.sub %0,%0,%1 \n\t" : "=&r" (_output), "+r" (_value)); - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - (1 << _bit_number) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { -/* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; -#endif /* ASM */ - -#define CPU_SIZEOF_POINTER 4 -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#ifndef ASM -typedef uint32_t CPU_Counter_ticks; -typedef uint16_t Priority_bit_map_Word; - -typedef struct { - uint32_t r[32]; - - /* The following registers must be saved if we have - fast context switch disabled and nested interrupt - levels are enabled. - */ -#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED - uint32_t epcr; /* exception PC register */ - uint32_t eear; /* exception effective address register */ - uint32_t esr; /* exception supervision register */ -#endif - -} CPU_Exception_frame; - -/** - * @brief Prints the exception frame via printk(). - * - * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. - */ -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - * - */ - -void _CPU_Initialize( - void -); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - * - * Or1k Specific Information: - * - * Please see the comments in the .c file for a description of how - * this function works. There are several things to be aware of. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - * - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - * - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - */ - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h b/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h deleted file mode 100644 index a5659f35ce..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/cpu_asm.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * @brief OR1K Assembly File - * - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -/* -#include <rtems/score/offsets.h> -*/ - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/or1k/rtems/score/types.h b/cpukit/score/cpu/or1k/rtems/score/types.h deleted file mode 100644 index b3beb8371f..0000000000 --- a/cpukit/score/cpu/or1k/rtems/score/types.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * @file - * - * @brief OR1K Architecture Types API - */ - -/* - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - - #ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup ScoreCPU - */ -/**@{**/ - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void or1k_isr; -typedef void ( *or1k_isr_entry )( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h deleted file mode 100644 index 192a00687d..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/asm.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1995. - * i-cubed ltd. - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/powerpc.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#ifndef __FLOAT_REGISTER_PREFIX__ -#define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ -#endif - -#ifndef __PROC_LABEL_PREFIX__ -#define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for procedure labels. */ - -#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* Use the right prefix for floating point registers. */ - -#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG(0) -#define r1 REG(1) -#define r2 REG(2) -#define r3 REG(3) -#define r4 REG(4) -#define r5 REG(5) -#define r6 REG(6) -#define r7 REG(7) -#define r8 REG(8) -#define r9 REG(9) -#define r10 REG(10) -#define r11 REG(11) -#define r12 REG(12) -#define r13 REG(13) -#define r14 REG(14) -#define r15 REG(15) -#define r16 REG(16) -#define r17 REG(17) -#define r18 REG(18) -#define r19 REG(19) -#define r20 REG(20) -#define r21 REG(21) -#define r22 REG(22) -#define r23 REG(23) -#define r24 REG(24) -#define r25 REG(25) -#define r26 REG(26) -#define r27 REG(27) -#define r28 REG(28) -#define r29 REG(29) -#define r30 REG(30) -#define r31 REG(31) -#define f0 FREG(0) -#define f1 FREG(1) -#define f2 FREG(2) -#define f3 FREG(3) -#define f4 FREG(4) -#define f5 FREG(5) -#define f6 FREG(6) -#define f7 FREG(7) -#define f8 FREG(8) -#define f9 FREG(9) -#define f10 FREG(10) -#define f11 FREG(11) -#define f12 FREG(12) -#define f13 FREG(13) -#define f14 FREG(14) -#define f15 FREG(15) -#define f16 FREG(16) -#define f17 FREG(17) -#define f18 FREG(18) -#define f19 FREG(19) -#define f20 FREG(20) -#define f21 FREG(21) -#define f22 FREG(22) -#define f23 FREG(23) -#define f24 FREG(24) -#define f25 FREG(25) -#define f26 FREG(26) -#define f27 FREG(27) -#define f28 FREG(28) -#define f29 FREG(29) -#define f30 FREG(30) -#define f31 FREG(31) -#define v0 0 -#define v1 1 -#define v2 2 -#define v3 3 -#define v4 4 -#define v5 5 -#define v6 6 -#define v7 7 -#define v8 8 -#define v9 9 -#define v10 10 -#define v11 11 -#define v12 12 -#define v13 13 -#define v14 14 -#define v15 15 -#define v16 16 -#define v17 17 -#define v18 18 -#define v19 19 -#define v20 20 -#define v21 21 -#define v22 22 -#define v23 23 -#define v24 24 -#define v25 25 -#define v26 26 -#define v27 27 -#define v28 28 -#define v29 29 -#define v30 30 -#define v31 31 - -/* - * Some special purpose registers (SPRs). - */ -#define srr0 0x01a -#define srr1 0x01b -#define srr2 0x3de /* IBM 400 series only */ -#define srr3 0x3df /* IBM 400 series only */ -#define csrr0 58 /* Book E */ -#define csrr1 59 /* Book E */ -#define mcsrr0 570 /* e500 */ -#define mcsrr1 571 /* e500 */ -#define dsrr0 574 /* e200 */ -#define dsrr1 575 /* e200 */ - -#define sprg0 0x110 -#define sprg1 0x111 -#define sprg2 0x112 -#define sprg3 0x113 -#define sprg4 276 -#define sprg5 277 -#define sprg6 278 -#define sprg7 279 - -#define usprg0 256 - -#define dar 0x013 /* Data Address Register */ -#define dec 0x016 /* Decrementer Register */ - -#if defined(ppc403) || defined(ppc405) -/* the following SPR/DCR registers exist only in IBM 400 series */ -#define dear 0x3d5 -#define evpr 0x3d6 /* SPR: exception vector prefix register */ -#define iccr 0x3fb /* SPR: instruction cache control reg. */ -#define dccr 0x3fa /* SPR: data cache control reg. */ - -#if defined (ppc403) -#define exisr 0x040 /* DCR: external interrupt status register */ -#define exier 0x042 /* DCR: external interrupt enable register */ -#endif /* ppc403 */ -#if defined(ppc405) -#define exisr 0x0C0 /* DCR: external interrupt status register */ -#define exier 0x0C2 /* DCR: external interrupt enable register */ -#endif /* ppc405 */ - -#define br0 0x080 /* DCR: memory bank register 0 */ -#define br1 0x081 /* DCR: memory bank register 1 */ -#define br2 0x082 /* DCR: memory bank register 2 */ -#define br3 0x083 /* DCR: memory bank register 3 */ -#define br4 0x084 /* DCR: memory bank register 4 */ -#define br5 0x085 /* DCR: memory bank register 5 */ -#define br6 0x086 /* DCR: memory bank register 6 */ -#define br7 0x087 /* DCR: memory bank register 7 */ - -/* end of IBM400 series register definitions */ - -#elif defined(mpc555) -/* The following registers are for the MPC5xx */ -#define eie 0x050 /* External Interrupt Enable Register */ -#define eid 0x051 /* External Interrupt Disable Register */ -#define nri 0x052 /* Non-Recoverable Interrupt Register */ - -#elif defined(mpc860) || defined(mpc821) -/* The following registers are for the MPC8x0 */ -#define der 0x095 /* Debug Enable Register */ -#define ictrl 0x09E /* Instruction Support Control Register */ -#define immr 0x27E /* Internal Memory Map Register */ -/* end of MPC8x0 registers */ -#endif - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC_VAR(sym) .globl SYM (sym) -#define EXTERN_VAR(sym) .extern SYM (sym) -#define PUBLIC_PROC(sym) .globl PROC (sym) -#define EXTERN_PROC(sym) .extern PROC (sym) - -/* Other potentially assembler specific operations */ -#if PPC_ASM == PPC_ASM_ELF -#define ALIGN(n,p) .align p -#define DESCRIPTOR(x) \ - .section .descriptors,"aw"; \ - PUBLIC_VAR (x); \ -SYM (x):; \ - .long PROC (x); \ - .long s.got; \ - .long 0 - -#define EXT_SYM_REF(x) .long x -#define EXT_PROC_REF(x) .long x - -/* - * Define macros to handle section beginning and ends. - */ - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA .data -#define END_DATA -#define BEGIN_BSS .bss -#define END_BSS -#define END - -#else -#error "PPC_ASM_TYPE is not properly defined" -#endif -#ifndef PPC_ASM -#error "PPC_ASM_TYPE is not properly defined" -#endif - - -#endif diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h deleted file mode 100644 index c30b9dc967..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ /dev/null @@ -1,1311 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Department Source - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * COPYRIGHT (c) 1995 i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. - * - * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). - * - * Copyright (c) 2010-2013 embedded brains GmbH. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#include <rtems/score/types.h> -#include <rtems/score/powerpc.h> -#include <rtems/powerpc/registers.h> - -#ifndef ASM - #include <string.h> /* for memset() */ -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT \ - __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#else -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#endif - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "PPC_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( PPC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * PowerPC Note: It appears the GCC can implicitly generate FPU - * and Altivec instructions when you least expect them. So make - * all tasks floating point. - */ - -#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -#ifndef __SPE__ - #define PPC_GPR_TYPE uint32_t - #define PPC_GPR_SIZE 4 - #define PPC_GPR_LOAD lwz - #define PPC_GPR_STORE stw -#else - #define PPC_GPR_TYPE uint64_t - #define PPC_GPR_SIZE 8 - #define PPC_GPR_LOAD evldd - #define PPC_GPR_STORE evstdd -#endif - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according - * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - - * Linux and Embedded") - */ -typedef struct { - uint32_t gpr1; - uint32_t msr; - uint32_t lr; - uint32_t cr; - PPC_GPR_TYPE gpr14; - PPC_GPR_TYPE gpr15; - PPC_GPR_TYPE gpr16; - PPC_GPR_TYPE gpr17; - PPC_GPR_TYPE gpr18; - PPC_GPR_TYPE gpr19; - PPC_GPR_TYPE gpr20; - PPC_GPR_TYPE gpr21; - PPC_GPR_TYPE gpr22; - PPC_GPR_TYPE gpr23; - PPC_GPR_TYPE gpr24; - PPC_GPR_TYPE gpr25; - PPC_GPR_TYPE gpr26; - PPC_GPR_TYPE gpr27; - PPC_GPR_TYPE gpr28; - PPC_GPR_TYPE gpr29; - PPC_GPR_TYPE gpr30; - PPC_GPR_TYPE gpr31; - uint32_t gpr2; - #if defined(PPC_MULTILIB_ALTIVEC) - uint32_t reserved_for_alignment; - uint8_t v20[16]; - uint8_t v21[16]; - uint8_t v22[16]; - uint8_t v23[16]; - uint8_t v24[16]; - uint8_t v25[16]; - uint8_t v26[16]; - uint8_t v27[16]; - uint8_t v28[16]; - uint8_t v29[16]; - uint8_t v30[16]; - uint8_t v31[16]; - uint32_t vrsave; - #elif defined(__ALTIVEC__) - /* - * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave - * and padding to ensure cache-alignment. Unfortunately, we can't verify - * the cache line size here in the cpukit but altivec support code will - * produce an error if this is ever different from 32 bytes. - * - * Note: it is the BSP/CPU-support's responsibility to save/restore - * volatile vregs across interrupts and exceptions. - */ - uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; - #endif - #if defined(PPC_MULTILIB_FPU) - double f14; - double f15; - double f16; - double f17; - double f18; - double f19; - double f20; - double f21; - double f22; - double f23; - double f24; - double f25; - double f26; - double f27; - double f28; - double f29; - double f30; - double f31; - #endif - #if defined(RTEMS_SMP) - /* - * This item is at the structure end, so that we can use dcbz for the - * previous items to optimize the context switch. We must not set this - * item to zero via the dcbz. - */ - volatile uint32_t is_executing; - #endif -} ppc_context; - -typedef struct { - uint8_t context [ - PPC_DEFAULT_CACHE_LINE_SIZE - + sizeof(ppc_context) - + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 - ? 0 - : PPC_DEFAULT_CACHE_LINE_SIZE - - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) - ]; -} Context_Control; - -static inline ppc_context *ppc_get_context( const Context_Control *context ) -{ - uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; - uintptr_t mask = clsz - 1; - uintptr_t addr = (uintptr_t) context; - - return (ppc_context *) ((addr & ~mask) + clsz); -} - -#define _CPU_Context_Get_SP( _context ) \ - ppc_get_context(_context)->gpr1 - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return ppc_get_context(context)->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - ppc_get_context(context)->is_executing = is_executing; - } -#endif -#endif /* ASM */ - -#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0) -#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) -#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8) -#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12) - -#define PPC_CONTEXT_GPR_OFFSET( gpr ) \ - (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16) - -#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) -#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) -#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) -#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) -#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) -#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) -#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) -#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) -#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) -#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) -#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) -#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) -#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) -#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) -#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) -#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) -#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) -#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) -#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 ) - -#ifdef PPC_MULTILIB_ALTIVEC - #define PPC_CONTEXT_OFFSET_V( v ) \ - ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) - #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) - #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) - #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) - #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) - #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) - #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) - #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) - #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) - #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) - #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) - #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) - #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) - #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 ) -#else - #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) -#endif - -#ifdef PPC_MULTILIB_FPU - #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) - #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) - #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) - #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) - #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) - #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) - #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) - #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) - #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) - #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) - #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) - #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) - #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) - #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) - #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) - #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) - #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) - #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) -#endif - -#if defined(PPC_MULTILIB_FPU) - #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) -#elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) -#else - #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4) -#endif - -#ifdef RTEMS_SMP - #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE -#endif - -#ifndef ASM -typedef struct { -#if (PPC_HAS_FPU == 1) - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - uint64_t fpscr; -#else - float f[32]; - uint32_t fpscr; -#endif -#endif /* (PPC_HAS_FPU == 1) */ -} Context_Control_fp; - -typedef struct CPU_Interrupt_frame { - uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ - uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ - - /* This is what is left out of the primary contexts */ - uint32_t gpr0; - uint32_t gpr2; /* play safe */ - uint32_t gpr3; - uint32_t gpr4; - uint32_t gpr5; - uint32_t gpr6; - uint32_t gpr7; - uint32_t gpr8; - uint32_t gpr9; - uint32_t gpr10; - uint32_t gpr11; - uint32_t gpr12; - uint32_t gpr13; /* Play safe */ - uint32_t gpr28; /* For internal use by the IRQ handler */ - uint32_t gpr29; /* For internal use by the IRQ handler */ - uint32_t gpr30; /* For internal use by the IRQ handler */ - uint32_t gpr31; /* For internal use by the IRQ handler */ - uint32_t cr; /* Bits of this are volatile, so no-one may save */ - uint32_t ctr; - uint32_t xer; - uint32_t lr; - uint32_t pc; - uint32_t msr; - uint32_t pad[3]; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * PowerPC Specific Information: - * - * The PowerPC and x86 were the first to use the PIC interrupt model. - * They do not use the simple vectored interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Note, however that compilers may use floating point registers/ - * instructions for optimization or they may save/restore FP registers - * on the stack. You must not use deferred switching in these cases - * and on the PowerPC attempting to do so will raise a "FP unavailable" - * exception. - */ -/* - * ACB Note: This could make debugging tricky.. - */ - -/* conservative setting (FALSE); probably doesn't affect performance too much */ -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Processor defined structures required for cpukit/score. - */ - -#ifndef ASM - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -/* EXTERN Context_Control_fp _CPU_Null_fp_context; */ - -#endif /* ndef ASM */ - -/* - * This defines the number of levels and the mask used to pick those - * bits out of a thread mode. - */ - -#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * (Optional) # of bytes for libmisc/stackchk to check - * If not specifed, then it defaults to something reasonable - * for most architectures. - */ - -#define CPU_STACK_CHECK_SIZE (128) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. Note that - * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level - * being maintained (e.g. watchdog queues). - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * ISR handler macros - */ - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _isr_cookie. - */ - -#ifndef ASM - -static inline uint32_t _CPU_ISR_Get_level( void ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (msr & MSR_EE) return 0; - else return 1; -} - -static inline void _CPU_ISR_Set_level( uint32_t level ) -{ - register unsigned int msr; - _CPU_MSR_GET(msr); - if (!(level & CPU_MODES_INTERRUPT_MASK)) { - msr |= ppc_interrupt_get_disable_mask(); - } - else { - msr &= ~ppc_interrupt_get_disable_mask(); - } - _CPU_MSR_SET(msr); -} - -void BSP_panic(char *); - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -void _BSP_Fatal_error(unsigned int); - -#endif /* ASM */ - -#define _CPU_Fatal_halt( _source, _error ) \ - _BSP_Fatal_error(_error) - -/* end of Fatal Error manager macros */ - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) - -#ifndef ASM -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t swapped; - - __asm__ volatile("rlwimi %0,%1,8,24,31;" - "rlwimi %0,%1,24,16,23;" - "rlwimi %0,%1,8,8,15;" - "rlwimi %0,%1,24,0,7;" : - "=&r" ((swapped)) : "r" ((value))); - - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - CPU_Counter_ticks value; - -#if defined(__PPC_CPU_E6500__) - /* Use Alternate Time Base */ - __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); -#else - __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); -#endif - - return value; -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - - -#ifndef ASM -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - memset( *(_destination), 0, sizeof( **(_destination) ) ) - -/* end of Context handler macros */ -#endif /* ASM */ - -#ifndef ASM -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_Bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ - "1" ((_value))); \ - } - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 0x80000000 >> (_bit_number) ) - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -/* end of Priority handler macros */ -#endif /* ASM */ - -/* functions */ - -#ifndef ASM - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generallu used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -#ifdef RTEMS_SMP - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t pir; - - /* Use Book E Processor ID Register (PIR) */ - __asm__ volatile ( - "mfspr %[pir], 286" - : [pir] "=&r" (pir) - ); - - return pir; - } - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -typedef struct { - uint32_t EXC_SRR0; - uint32_t EXC_SRR1; - uint32_t _EXC_number; - uint32_t EXC_CR; - uint32_t EXC_CTR; - uint32_t EXC_XER; - uint32_t EXC_LR; - #ifdef __SPE__ - uint32_t EXC_SPEFSCR; - uint64_t EXC_ACC; - #endif - PPC_GPR_TYPE GPR0; - PPC_GPR_TYPE GPR1; - PPC_GPR_TYPE GPR2; - PPC_GPR_TYPE GPR3; - PPC_GPR_TYPE GPR4; - PPC_GPR_TYPE GPR5; - PPC_GPR_TYPE GPR6; - PPC_GPR_TYPE GPR7; - PPC_GPR_TYPE GPR8; - PPC_GPR_TYPE GPR9; - PPC_GPR_TYPE GPR10; - PPC_GPR_TYPE GPR11; - PPC_GPR_TYPE GPR12; - PPC_GPR_TYPE GPR13; - PPC_GPR_TYPE GPR14; - PPC_GPR_TYPE GPR15; - PPC_GPR_TYPE GPR16; - PPC_GPR_TYPE GPR17; - PPC_GPR_TYPE GPR18; - PPC_GPR_TYPE GPR19; - PPC_GPR_TYPE GPR20; - PPC_GPR_TYPE GPR21; - PPC_GPR_TYPE GPR22; - PPC_GPR_TYPE GPR23; - PPC_GPR_TYPE GPR24; - PPC_GPR_TYPE GPR25; - PPC_GPR_TYPE GPR26; - PPC_GPR_TYPE GPR27; - PPC_GPR_TYPE GPR28; - PPC_GPR_TYPE GPR29; - PPC_GPR_TYPE GPR30; - PPC_GPR_TYPE GPR31; - #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU) - uint32_t reserved_for_alignment; - #endif - #ifdef PPC_MULTILIB_ALTIVEC - uint32_t VRSAVE; - - /* This field must take stvewx/lvewx requirements into account */ - uint32_t VSCR; - - uint8_t V0[16]; - uint8_t V1[16]; - uint8_t V2[16]; - uint8_t V3[16]; - uint8_t V4[16]; - uint8_t V5[16]; - uint8_t V6[16]; - uint8_t V7[16]; - uint8_t V8[16]; - uint8_t V9[16]; - uint8_t V10[16]; - uint8_t V11[16]; - uint8_t V12[16]; - uint8_t V13[16]; - uint8_t V14[16]; - uint8_t V15[16]; - uint8_t V16[16]; - uint8_t V17[16]; - uint8_t V18[16]; - uint8_t V19[16]; - uint8_t V20[16]; - uint8_t V21[16]; - uint8_t V22[16]; - uint8_t V23[16]; - uint8_t V24[16]; - uint8_t V25[16]; - uint8_t V26[16]; - uint8_t V27[16]; - uint8_t V28[16]; - uint8_t V29[16]; - uint8_t V30[16]; - uint8_t V31[16]; - #endif - #ifdef PPC_MULTILIB_FPU - double F0; - double F1; - double F2; - double F3; - double F4; - double F5; - double F6; - double F7; - double F8; - double F9; - double F10; - double F11; - double F12; - double F13; - double F14; - double F15; - double F16; - double F17; - double F18; - double F19; - double F20; - double F21; - double F22; - double F23; - double F24; - double F25; - double F26; - double F27; - double F28; - double F29; - double F30; - double F31; - uint64_t FPSCR; - #endif -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * _CPU_Initialize_altivec() - * - * Global altivec-related initialization. - */ -void -_CPU_Initialize_altivec(void); - -/* - * _CPU_Context_switch_altivec - * - * This routine switches the altivec contexts passed to it. - */ - -void -_CPU_Context_switch_altivec( - ppc_context *from, - ppc_context *to -); - -/* - * _CPU_Context_restore_altivec - * - * This routine restores the altivec context passed to it. - */ - -void -_CPU_Context_restore_altivec( - ppc_context *ctxt -); - -/* - * _CPU_Context_initialize_altivec - * - * This routine initializes the altivec context passed to it. - */ - -void -_CPU_Context_initialize_altivec( - ppc_context *ctxt -); - -void _CPU_Fatal_error( - uint32_t _error -); - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/powerpc/rtems/score/types.h b/cpukit/score/cpu/powerpc/rtems/score/types.h deleted file mode 100644 index f36038fe09..0000000000 --- a/cpukit/score/cpu/powerpc/rtems/score/types.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * @file - * - * @brief PowerPC CPU Type Definitions - * - * This include file contains type definitions pertaining to the PowerPC - * processor family. - */ - -/* - * Author: Andrew Bray <andy@i-cubed.co.uk> - * - * COPYRIGHT (c) 1995 by i-cubed ltd. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: - * permission to use, copy, modify, and distribute this file - * for any purpose is hereby granted without fee, provided that - * the above copyright notice and this notice appears in all - * copies, and that the name of i-cubed limited not be used in - * advertising or publicity pertaining to distribution of the - * software without specific, written prior permission. - * i-cubed limited makes no representations about the suitability - * of this software for any purpose. - * - * Derived from c/src/exec/cpu/no_cpu/no_cputypes.h: - * - * COPYRIGHT (c) 1989-1997. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may in - * the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint32_t Priority_bit_map_Word; -typedef void ppc_isr; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sh/rtems/asm.h b/cpukit/score/cpu/sh/rtems/asm.h deleted file mode 100644 index ac730310cd..0000000000 --- a/cpukit/score/cpu/sh/rtems/asm.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/sh.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ -#define r0 REG (r0) -#define r1 REG (r1) -#define r2 REG (r2) -#define r3 REG (r3) -#define r4 REG (r4) -#define r5 REG (r5) -#define r6 REG (r6) -#define r7 REG (r7) -#define r8 REG (r8) -#define r9 REG (r9) -#define r10 REG (r10) -#define r11 REG (r11) -#define r12 REG (r12) -#define r13 REG (r13) -#define r14 REG (r14) -#define r15 REG (r15) -#define vbr REG (vbr) -#define gbr REG (gbr) -#define pr REG (pr) -#define mach REG (mach) -#define macl REG (macl) -#define sr REG (sr) -#define pc REG (pc) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .global SYM (sym) -#define EXTERN(sym) .global SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h deleted file mode 100644 index 6ae0a83771..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/cpu.h +++ /dev/null @@ -1,909 +0,0 @@ -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2006. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/sh.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SH Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * We define the interrupt stack in the linker script - */ -#define CPU_ALLOCATE_INTERRUPT_STACK FALSE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * We currently support sh1 only, which has no FPU, other SHes have an FPU - * - * The macro name "SH_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if SH_HAS_FPU -#define CPU_HARDWARE_FP TRUE -#define CPU_SOFTWARE_FP FALSE -#else -#define CPU_SOFTWARE_FP FALSE -#define CPU_HARDWARE_FP FALSE -#endif - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#if SH_HAS_FPU -#define CPU_ALL_TASKS_ARE_FP TRUE -#else -#define CPU_ALL_TASKS_ARE_FP FALSE -#endif - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#if SH_HAS_FPU -#define CPU_IDLE_TASK_IS_FP TRUE -#else -#define CPU_IDLE_TASK_IS_FP FALSE -#endif - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#if SH_HAS_FPU -#define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else -#define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * NOTE: SHes can be big or little endian, the default is big endian - */ - -/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */ -#if defined(__LITTLE_ENDIAN__) -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE -#else -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE -#endif - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000f - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * Processor defined structures required for cpukit/score. - */ - -/* may need to put some structures here. */ - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - uint32_t *r15; /* stack pointer */ - - uint32_t macl; - uint32_t mach; - uint32_t *pr; - - uint32_t *r14; /* frame pointer/call saved */ - - uint32_t r13; /* call saved */ - uint32_t r12; /* call saved */ - uint32_t r11; /* call saved */ - uint32_t r10; /* call saved */ - uint32_t r9; /* call saved */ - uint32_t r8; /* call saved */ - - uint32_t *r7; /* arg in */ - uint32_t *r6; /* arg in */ - -#if 0 - uint32_t *r5; /* arg in */ - uint32_t *r4; /* arg in */ -#endif - - uint32_t *r3; /* scratch */ - uint32_t *r2; /* scratch */ - uint32_t *r1; /* scratch */ - - uint32_t *r0; /* arg return */ - - uint32_t gbr; - uint32_t sr; - -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r15 - -typedef struct { -#if SH_HAS_FPU -#ifdef SH4_USE_X_REGISTERS - union { - float f[16]; - double d[8]; - } x; -#endif - union { - float f[16]; - double d[8]; - } r; - float fpul; /* fp communication register */ - uint32_t fpscr; /* fp control register */ -#endif /* SH_HAS_FPU */ -} Context_Control_fp; - -typedef struct { -} CPU_Interrupt_frame; - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -#if SH_HAS_FPU -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; -#endif - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ -SCORE_EXTERN void CPU_delay( uint32_t microseconds ); - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * We have been able to run the sptests with this value, but have not - * been able to run the tmtest suite. - */ - -#define CPU_STACK_MINIMUM_SIZE 4096 - -#define CPU_SIZEOF_POINTER 4 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ -#if defined(__SH4__) -/* FIXME: sh3 and SH3E? */ -#define CPU_ALIGNMENT 8 -#else -#define CPU_ALIGNMENT 4 -#endif - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * SH Specific Information: NONE - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level) \ - sh_disable_interrupts( _level ) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level) \ - sh_enable_interrupts( _level) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level) \ - sh_flash_interrupts( _level) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -#define _CPU_ISR_Set_level( _newlevel) \ - sh_set_interrupt_level(_newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -/* - * FIXME: defined as a function for debugging - should be a macro - */ -SCORE_EXTERN void _CPU_Context_Initialize( - Context_Control *_the_context, - void *_stack_base, - uint32_t _size, - uint32_t _isr, - void (*_entry_point)(void), - int _is_fp, - void *_tls_area ); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have. - */ - -#if SH_HAS_FPU -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context;\ - } while(0) -#else -#define _CPU_Context_Initialize_fp( _destination ) \ - { } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * FIXME: Trap32 ??? - * - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * invokes a Trap32 Instruction which returns to the breakpoint - * routine of cmon. - */ - -#ifdef BSP_FATAL_HALT - /* we manage the fatal error in the board support package */ - void bsp_fatal_halt( uint32_t _error); -#define _CPU_Fatal_halt( _source, _error ) bsp_fatal_halt( _error) -#else -#define _CPU_Fatal_halt( _source, _error)\ -{ \ - __asm__ volatile("mov.l %0,r0"::"m" (_error)); \ - __asm__ volatile("mov #1, r4"); \ - __asm__ volatile("trapa #34"); \ -} -#endif - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_bit_map_Word. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -extern uint8_t _bit_set_table[]; - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - _output = 0;\ - if(_value > 0x00ff) \ - { _value >>= 8; _output = 8; } \ - if(_value > 0x000f) \ - { _output += 4; _value >>= 4; } \ - _output += _bit_set_table[ _value]; } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * @brief CPU Initialize - * - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * @brief This routine saves the floating point context passed to it. - * - * _CPU_Context_save_fp - * - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * @brief This routine restores the floating point context passed to it. - * - * _CPU_Context_restore_fp - * - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sh/rtems/score/types.h b/cpukit/score/cpu/sh/rtems/score/types.h deleted file mode 100644 index d740b2f901..0000000000 --- a/cpukit/score/cpu/sh/rtems/score/types.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * @file - * - * @brief Hitachi SH CPU Type Definitions - * - * This include file contains information pertaining to the Hitachi SH - * processor. - */ - -/* - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998-2001. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; - -typedef void sh_isr; -typedef void ( *sh_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/asm.h b/cpukit/score/cpu/sparc/rtems/asm.h deleted file mode 100644 index a2b11f63fc..0000000000 --- a/cpukit/score/cpu/sparc/rtems/asm.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -/* - * Entry for traps which jump to a programmer-specified trap handler. - */ - -#define TRAP(_vector, _handler) \ - mov %psr, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -/* - * Used for the reset trap to avoid a supervisor instruction - */ - -#define RTRAP(_vector, _handler) \ - mov %g0, %l0 ; \ - sethi %hi(_handler), %l4 ; \ - jmp %l4+%lo(_handler); \ - mov _vector, %l3 - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h deleted file mode 100644 index b73a56e0c0..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ /dev/null @@ -1,1383 +0,0 @@ -/** - * @file - * - * @brief SPARC CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC processor. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/sparc.h> - -/* conditional compilation parameters */ - -#if defined(RTEMS_SMP) - /* - * The SPARC ABI is a bit special with respect to the floating point context. - * The complete floating point context is volatile. Thus from an ABI point - * of view nothing needs to be saved and restored during a context switch. - * Instead the floating point context must be saved and restored during - * interrupt processing. Historically the deferred floating point switch is - * used for SPARC and the complete floating point context is saved and - * restored during a context switch to the new floating point unit owner. - * This is a bit dangerous since post-switch actions (e.g. signal handlers) - * and context switch extensions may silently corrupt the floating point - * context. The floating point unit is disabled for interrupt handlers. - * Thus in case an interrupt handler uses the floating point unit then this - * will result in a trap. - * - * On SMP configurations the deferred floating point switch is not - * supported in principle. So use here a safe floating point support. Safe - * means that the volatile floating point context is saved and restored - * around a thread dispatch issued during interrupt processing. Thus - * post-switch actions and context switch extensions may safely use the - * floating point unit. - */ - #define SPARC_USE_SAFE_FP_SUPPORT -#endif - -/** - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * - If TRUE, then they are inlined. - * - If FALSE, then a subroutine call is made. - * - * On this port, it is faster to inline _Thread_Enable_dispatch. - */ -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/** - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * - If TRUE, then RTEMS allocates the vector table it internally manages. - * - If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * THe SPARC is a simple vectored architecture. Usually there is no - * PIC and the CPU directly vectors the interrupts. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * - If TRUE, then it must be installed during initialization. - * - If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * - If TRUE, then the memory is allocated during initialization. - * - If FALSE, then the memory is allocated during initialization. - * - * The SPARC does not have hardware support for switching to a - * dedicated interrupt stack. The port includes support for doing this - * in software. - * - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * The SPARC port does not pass an Interrupt Stack Frame pointer to - * interrupt handlers. - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * Does the CPU have hardware floating point? - * - * - If TRUE, then the FLOATING_POINT task attribute is supported. - * - If FALSE, then the FLOATING_POINT task attribute is ignored. - * - * This is set based upon the multilib settings. - */ -#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SAFE_FP_SUPPORT) - #define CPU_HARDWARE_FP TRUE -#else - #define CPU_HARDWARE_FP FALSE -#endif - -/** - * The SPARC GCC port does not have a software floating point library - * that requires RTEMS assistance. - */ -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks FLOATING_POINT tasks implicitly? - * - * - If TRUE, then the FLOATING_POINT task attribute is assumed. - * - If FALSE, then the FLOATING_POINT task attribute is followed. - * - * The SPARC GCC port does not implicitly use floating point registers. - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * - If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * - If FALSE, then the IDLE task does not have a floating point context. - * - * The IDLE task does not have to be floating point on the SPARC. - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * - If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * - If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * On the SPARC, we can disable the FPU for integer only tasks so - * it is safe to defer floating point context switches. - */ -#if defined(SPARC_USE_SAFE_FP_SUPPORT) - #define CPU_USE_DEFERRED_FP_SWITCH FALSE -#else - #define CPU_USE_DEFERRED_FP_SWITCH TRUE -#endif - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * - If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * - If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * The SPARC architecture does not have a low power or halt instruction. - * It is left to the BSP and/or CPU specific code to provide an IDLE - * thread body which is aware of low power modes. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * - If TRUE, then the grows upward. - * - If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value was chosen to take advantages of caches. - */ -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * The SPARC is big endian. - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * The SPARC is NOT little endian. - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC has 16 interrupt levels in the PIL field of the PSR. - */ -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#ifndef ASM -/** - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ -typedef struct { - /** This is the offset of the l0 register. */ - uint32_t l0; - /** This is the offset of the l1 register. */ - uint32_t l1; - /** This is the offset of the l2 register. */ - uint32_t l2; - /** This is the offset of the l3 register. */ - uint32_t l3; - /** This is the offset of the l4 register. */ - uint32_t l4; - /** This is the offset of the l5 register. */ - uint32_t l5; - /** This is the offset of the l6 register. */ - uint32_t l6; - /** This is the offset of the l7 register. */ - uint32_t l7; - /** This is the offset of the l0 register. */ - uint32_t i0; - /** This is the offset of the i1 register. */ - uint32_t i1; - /** This is the offset of the i2 register. */ - uint32_t i2; - /** This is the offset of the i3 register. */ - uint32_t i3; - /** This is the offset of the i4 register. */ - uint32_t i4; - /** This is the offset of the i5 register. */ - uint32_t i5; - /** This is the offset of the i6 register. */ - uint32_t i6_fp; - /** This is the offset of the i7 register. */ - uint32_t i7; - /** This is the offset of the register used to return structures. */ - void *structure_return_address; - - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - /** This is the offset of the register for saved argument 0. */ - uint32_t saved_arg0; - /** This is the offset of the register for saved argument 1. */ - uint32_t saved_arg1; - /** This is the offset of the register for saved argument 2. */ - uint32_t saved_arg2; - /** This is the offset of the register for saved argument 3. */ - uint32_t saved_arg3; - /** This is the offset of the register for saved argument 4. */ - uint32_t saved_arg4; - /** This is the offset of the register for saved argument 5. */ - uint32_t saved_arg5; - /** This field pads the structure so ldd and std instructions can be used. */ - uint32_t pad0; -} CPU_Minimum_stack_frame; - -#endif /* ASM */ - -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L1_OFFSET 0x04 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L2_OFFSET 0x08 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L3_OFFSET 0x0c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L4_OFFSET 0x10 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L5_OFFSET 0x14 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L6_OFFSET 0x18 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_L7_OFFSET 0x1c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I0_OFFSET 0x20 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I1_OFFSET 0x24 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I2_OFFSET 0x28 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I3_OFFSET 0x2c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I4_OFFSET 0x30 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I5_OFFSET 0x34 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_I7_OFFSET 0x3c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 -/** This macro defines an offset into the stack frame for use in assembly. */ -#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c - -/** This defines the size of the minimum stack frame. */ -#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60 - -#if ( SPARC_HAS_FPU == 1 ) - #define CPU_PER_CPU_CONTROL_SIZE 8 -#else - #define CPU_PER_CPU_CONTROL_SIZE 4 -#endif - -/** - * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field - * relative to the Per_CPU_Control begin. - */ -#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0 - -#if ( SPARC_HAS_FPU == 1 ) - /** - * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the - * Per_CPU_Control begin. - */ - #define SPARC_PER_CPU_FSR_OFFSET 4 -#endif - -/** - * @defgroup Contexts SPARC Context Structures - * - * @ingroup Score - * - * Generally there are 2 types of context to save. - * + Interrupt registers to save - * + Task level registers to save - * - * This means we have the following 3 context items: - * + task level context stuff:: Context_Control - * + floating point task stuff:: Context_Control_fp - * + special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ -/**@{**/ - -#ifndef ASM - -typedef struct { - /** - * This flag is context switched with each thread. It indicates - * that THIS thread has an _ISR_Dispatch stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ - uint32_t isr_dispatch_disable; - -#if ( SPARC_HAS_FPU == 1 ) - /** - * @brief Memory location to store the FSR register during interrupt - * processing. - * - * This is a write-only field. The FSR is written to force a completion of - * floating point operations in progress. - */ - uint32_t fsr; -#endif -} CPU_Per_CPU_control; - -/** - * @brief SPARC basic context. - * - * This structure defines the non-volatile integer and processor state context - * for the SPARC architecture according to "SYSTEM V APPLICATION BINARY - * INTERFACE - SPARC Processor Supplement", Third Edition. - * - * The registers g2 through g4 are reserved for applications. GCC uses them as - * volatile registers by default. So they are treated like volatile registers - * in RTEMS as well. - * - * The register g6 contains the per-CPU control of the current processor. It - * is an invariant of the processor context. This register must not be saved - * and restored during context switches or interrupt services. - */ -typedef struct { - /** This will contain the contents of the g5 register. */ - uint32_t g5; - /** This will contain the contents of the g7 register. */ - uint32_t g7; - - /** - * This will contain the contents of the l0 and l1 registers. - * - * Using a double l0_and_l1 will put everything in this structure on a double - * word boundary which allows us to use double word loads and stores safely - * in the context switch. - */ - double l0_and_l1; - /** This will contain the contents of the l2 register. */ - uint32_t l2; - /** This will contain the contents of the l3 register. */ - uint32_t l3; - /** This will contain the contents of the l4 register. */ - uint32_t l4; - /** This will contain the contents of the l5 registeer.*/ - uint32_t l5; - /** This will contain the contents of the l6 register. */ - uint32_t l6; - /** This will contain the contents of the l7 register. */ - uint32_t l7; - - /** This will contain the contents of the i0 register. */ - uint32_t i0; - /** This will contain the contents of the i1 register. */ - uint32_t i1; - /** This will contain the contents of the i2 register. */ - uint32_t i2; - /** This will contain the contents of the i3 register. */ - uint32_t i3; - /** This will contain the contents of the i4 register. */ - uint32_t i4; - /** This will contain the contents of the i5 register. */ - uint32_t i5; - /** This will contain the contents of the i6 (e.g. frame pointer) register. */ - uint32_t i6_fp; - /** This will contain the contents of the i7 register. */ - uint32_t i7; - - /** This will contain the contents of the o6 (e.g. frame pointer) register. */ - uint32_t o6_sp; - /** - * This will contain the contents of the o7 (e.g. address of CALL - * instruction) register. - */ - uint32_t o7; - - /** This will contain the contents of the processor status register. */ - uint32_t psr; - /** - * This field is used to prevent heavy nesting of calls to _Thread_Dispatch - * on an interrupted task's stack. This is problematic on the slower - * SPARC CPU models at high interrupt rates. - */ - uint32_t isr_dispatch_disable; - -#if defined(RTEMS_SMP) - volatile uint32_t is_executing; -#endif -} Context_Control; - -/** - * This macro provides a CPU independent way for RTEMS to access the - * stack pointer in a context structure. The actual name and offset is - * CPU architecture dependent. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#ifdef RTEMS_SMP - static inline bool _CPU_Context_Get_is_executing( - const Context_Control *context - ) - { - return context->is_executing; - } - - static inline void _CPU_Context_Set_is_executing( - Context_Control *context, - bool is_executing - ) - { - context->is_executing = is_executing; - } -#endif - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -/** This macro defines an offset into the context for use in assembly. */ -#define G5_OFFSET 0x00 -/** This macro defines an offset into the context for use in assembly. */ -#define G7_OFFSET 0x04 - -/** This macro defines an offset into the context for use in assembly. */ -#define L0_OFFSET 0x08 -/** This macro defines an offset into the context for use in assembly. */ -#define L1_OFFSET 0x0C -/** This macro defines an offset into the context for use in assembly. */ -#define L2_OFFSET 0x10 -/** This macro defines an offset into the context for use in assembly. */ -#define L3_OFFSET 0x14 -/** This macro defines an offset into the context for use in assembly. */ -#define L4_OFFSET 0x18 -/** This macro defines an offset into the context for use in assembly. */ -#define L5_OFFSET 0x1C -/** This macro defines an offset into the context for use in assembly. */ -#define L6_OFFSET 0x20 -/** This macro defines an offset into the context for use in assembly. */ -#define L7_OFFSET 0x24 - -/** This macro defines an offset into the context for use in assembly. */ -#define I0_OFFSET 0x28 -/** This macro defines an offset into the context for use in assembly. */ -#define I1_OFFSET 0x2C -/** This macro defines an offset into the context for use in assembly. */ -#define I2_OFFSET 0x30 -/** This macro defines an offset into the context for use in assembly. */ -#define I3_OFFSET 0x34 -/** This macro defines an offset into the context for use in assembly. */ -#define I4_OFFSET 0x38 -/** This macro defines an offset into the context for use in assembly. */ -#define I5_OFFSET 0x3C -/** This macro defines an offset into the context for use in assembly. */ -#define I6_FP_OFFSET 0x40 -/** This macro defines an offset into the context for use in assembly. */ -#define I7_OFFSET 0x44 - -/** This macro defines an offset into the context for use in assembly. */ -#define O6_SP_OFFSET 0x48 -/** This macro defines an offset into the context for use in assembly. */ -#define O7_OFFSET 0x4C - -/** This macro defines an offset into the context for use in assembly. */ -#define PSR_OFFSET 0x50 -/** This macro defines an offset into the context for use in assembly. */ -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 - -#if defined(RTEMS_SMP) - #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 -#endif - -#ifndef ASM -/** - * @brief SPARC basic context. - * - * This structure defines floating point context area. - */ -typedef struct { - /** This will contain the contents of the f0 and f1 register. */ - double f0_f1; - /** This will contain the contents of the f2 and f3 register. */ - double f2_f3; - /** This will contain the contents of the f4 and f5 register. */ - double f4_f5; - /** This will contain the contents of the f6 and f7 register. */ - double f6_f7; - /** This will contain the contents of the f8 and f9 register. */ - double f8_f9; - /** This will contain the contents of the f10 and f11 register. */ - double f10_f11; - /** This will contain the contents of the f12 and f13 register. */ - double f12_f13; - /** This will contain the contents of the f14 and f15 register. */ - double f14_f15; - /** This will contain the contents of the f16 and f17 register. */ - double f16_f17; - /** This will contain the contents of the f18 and f19 register. */ - double f18_f19; - /** This will contain the contents of the f20 and f21 register. */ - double f20_f21; - /** This will contain the contents of the f22 and f23 register. */ - double f22_f23; - /** This will contain the contents of the f24 and f25 register. */ - double f24_f25; - /** This will contain the contents of the f26 and f27 register. */ - double f26_f27; - /** This will contain the contents of the f28 and f29 register. */ - double f28_f29; - /** This will contain the contents of the f30 and f31 register. */ - double f30_f31; - /** This will contain the contents of the floating point status register. */ - uint32_t fsr; -} Context_Control_fp; - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -/** This macro defines an offset into the FPU context for use in assembly. */ -#define FO_F1_OFFSET 0x00 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F2_F3_OFFSET 0x08 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F4_F5_OFFSET 0x10 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F6_F7_OFFSET 0x18 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F8_F9_OFFSET 0x20 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F1O_F11_OFFSET 0x28 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F12_F13_OFFSET 0x30 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F14_F15_OFFSET 0x38 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F16_F17_OFFSET 0x40 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F18_F19_OFFSET 0x48 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F2O_F21_OFFSET 0x50 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F22_F23_OFFSET 0x58 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F24_F25_OFFSET 0x60 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F26_F27_OFFSET 0x68 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F28_F29_OFFSET 0x70 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define F3O_F31_OFFSET 0x78 -/** This macro defines an offset into the FPU context for use in assembly. */ -#define FSR_OFFSET 0x80 - -/** This defines the size of the FPU context area for use in assembly. */ -#define CONTEXT_CONTROL_FP_SIZE 0x84 - -#ifndef ASM - -/** @} */ - -/** - * @brief Interrupt stack frame (ISF). - * - * Context saved on stack for an interrupt. - * - * NOTE: The PSR, PC, and NPC are only saved in this structure for the - * benefit of the user's handler. - */ -typedef struct { - /** On an interrupt, we must save the minimum stack frame. */ - CPU_Minimum_stack_frame Stack_frame; - /** This is the offset of the PSR on an ISF. */ - uint32_t psr; - /** This is the offset of the XXX on an ISF. */ - uint32_t pc; - /** This is the offset of the XXX on an ISF. */ - uint32_t npc; - /** This is the offset of the g1 register on an ISF. */ - uint32_t g1; - /** This is the offset of the g2 register on an ISF. */ - uint32_t g2; - /** This is the offset of the g3 register on an ISF. */ - uint32_t g3; - /** This is the offset of the g4 register on an ISF. */ - uint32_t g4; - /** This is the offset of the g5 register on an ISF. */ - uint32_t g5; - /** This is the offset is reserved for alignment on an ISF. */ - uint32_t reserved_for_alignment; - /** This is the offset of the g7 register on an ISF. */ - uint32_t g7; - /** This is the offset of the i0 register on an ISF. */ - uint32_t i0; - /** This is the offset of the i1 register on an ISF. */ - uint32_t i1; - /** This is the offset of the i2 register on an ISF. */ - uint32_t i2; - /** This is the offset of the i3 register on an ISF. */ - uint32_t i3; - /** This is the offset of the i4 register on an ISF. */ - uint32_t i4; - /** This is the offset of the i5 register on an ISF. */ - uint32_t i5; - /** This is the offset of the i6 register on an ISF. */ - uint32_t i6_fp; - /** This is the offset of the i7 register on an ISF. */ - uint32_t i7; - /** This is the offset of the y register on an ISF. */ - uint32_t y; - /** This is the offset of the tpc register on an ISF. */ - uint32_t tpc; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 -/** This macro defines an offset into the ISF for use in assembly. */ -#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c - -/** This defines the size of the ISF area for use in assembly. */ -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \ - CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 - -#ifndef ASM -/** - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; - -/** - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -typedef struct { - /** This will contain a "mov %psr, %l0" instruction. */ - uint32_t mov_psr_l0; - /** This will contain a "sethi %hi(_handler), %l4" instruction. */ - uint32_t sethi_of_handler_to_l4; - /** This will contain a "jmp %l4 + %lo(_handler)" instruction. */ - uint32_t jmp_to_low_of_handler_plus_l4; - /** This will contain a " mov _vector, %l3" instruction. */ - uint32_t mov_vector_l3; -} CPU_Trap_table_entry; - -/** - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/** - * The size of the floating point context area. - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/** - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 - -/** - * The SPARC has 256 vectors but the port treats 256-512 as synchronous - * traps. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 - -/** - * This is the bit step in a vector number to indicate it is being installed - * as a synchronous trap. - */ -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 - -/** - * This macro indicates that @a _trap as an asynchronous trap. - */ -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) - -/** - * This macro indicates that @a _trap as a synchronous trap. - */ -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) - -/** - * This macro returns the real hardware vector number associated with @a _trap. - */ -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/** - * What is the size of a pointer on this architecture? - */ -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -/* - * ISR handler macros - */ - -/** - * Support routine to initialize the RTEMS vector table after it is allocated. - */ -#define _CPU_Initialize_vectors() - -/** - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ -#define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/** - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -/** - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel << 8) - -/** - * @brief Obtain the current interrupt disable level. - * - * This method is invoked to return the current interrupt disable level. - * - * @return This method returns the current interrupt disable level. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/** - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * @param[in] the_context points to the context area - * @param[in] stack_base is the low address of the allocated stack area - * @param[in] size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to TRUE if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/** - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * The FP context area for the SPARC is a simple structure and nothing - * special is required to find the "starting load point" - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ -extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) - RTEMS_NO_RETURN; - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -#if ( SPARC_HAS_BITSCAN == 0 ) - /** - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - #define CPU_USE_GENERIC_BITFIELD_CODE TRUE - /** - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. Thus is needs the generic - * data table used by that algorithm. - */ - #define CPU_USE_GENERIC_BITFIELD_DATA TRUE -#else - #error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* functions */ - -/** - * @brief SPARC specific initialization. - * - * This routine performs CPU dependent initialization. - */ -void _CPU_Initialize(void); - -/** - * @brief SPARC specific raw ISR installer. - * - * This routine installs @a new_handler to be directly called from the trap - * table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the new ISR handler - * @param[in] old_handler will contain the old ISR handler - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief SPARC specific RTEMS ISR installer. - * - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the new ISR handler - * @param[in] old_handler will contain the old ISR handler - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @brief SPARC specific context switch. - * - * This routine switches from the run context to the heir context. - * - * @param[in] run is the currently executing thread - * @param[in] heir will become the currently executing thread - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @brief SPARC specific context restore. - * - * This routine is generally used only to restart self in an - * efficient manner. - * - * @param[in] new_context is the context to restore - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/** - * @brief The pointer to the current per-CPU control is available via register - * g6. - */ -register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" ); - -#define _CPU_Get_current_per_CPU_control() ( _SPARC_Per_CPU_current ) - -#if defined(RTEMS_SMP) - uint32_t _CPU_SMP_Initialize( void ); - - bool _CPU_SMP_Start_processor( uint32_t cpu_index ); - - void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); - - void _CPU_SMP_Prepare_start_multitasking( void ); - - #if defined(__leon__) && !defined(RTEMS_PARAVIRT) - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - return _LEON3_Get_current_processor(); - } - #else - uint32_t _CPU_SMP_Get_current_processor( void ); - #endif - - void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); - - static inline void _CPU_SMP_Processor_event_broadcast( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } - - static inline void _CPU_SMP_Processor_event_receive( void ) - { - __asm__ volatile ( "" : : : "memory" ); - } -#endif - -/** - * @brief SPARC specific save FPU method. - * - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is the area to save into - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @brief SPARC specific restore FPU method. - * - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is the area to restore from - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -void _CPU_Context_volatile_clobber( uintptr_t pattern ); - -void _CPU_Context_validate( uintptr_t pattern ); - -typedef struct { - uint32_t trap; - CPU_Interrupt_frame *isf; -} CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @brief SPARC specific method to endian swap an uint32_t. - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * @param[in] value is the value to endian swap - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * - swap least significant two bytes with 16-bit rotate - * - swap upper and lower 16-bits - * - swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * @brief SPARC specific method to endian swap an uint16_t. - * - * The following routine swaps the endian format of a uint16_t. - * - * @param[in] value is the value to endian swap - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -typedef CPU_Counter_ticks (*SPARC_Counter_difference)( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -/* - * The SPARC processors supported by RTEMS have no built-in CPU counter - * support. We have to use some hardware counter module for this purpose. The - * BSP must provide a 32-bit register which contains the current CPU counter - * value and a function for the difference calculation. It can use for example - * the GPTIMER instance used for the clock driver. - */ -typedef struct { - volatile const CPU_Counter_ticks *counter_register; - SPARC_Counter_difference counter_difference; -} SPARC_Counter; - -extern SPARC_Counter _SPARC_Counter; - -/* - * Returns always a value of one regardless of the parameters. This prevents - * an infinite loop in rtems_counter_delay_ticks(). Its only a reasonably safe - * default. - */ -CPU_Counter_ticks _SPARC_Counter_difference_default( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -static inline bool _SPARC_Counter_is_default( void ) -{ - return _SPARC_Counter.counter_difference - == _SPARC_Counter_difference_default; -} - -static inline void _SPARC_Counter_initialize( - volatile const CPU_Counter_ticks *counter_register, - SPARC_Counter_difference counter_difference -) -{ - _SPARC_Counter.counter_register = counter_register; - _SPARC_Counter.counter_difference = counter_difference; -} - -static inline CPU_Counter_ticks _CPU_Counter_read( void ) -{ - return *_SPARC_Counter.counter_register; -} - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return (*_SPARC_Counter.counter_difference)( second, first ); -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc/rtems/score/types.h b/cpukit/score/cpu/sparc/rtems/score/types.h deleted file mode 100644 index 4186012589..0000000000 --- a/cpukit/score/cpu/sparc/rtems/score/types.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file - * - * @brief SPARC CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * SPARC processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** - * @brief Priority bit map type. - * - * On the SPARC, there is no bitscan instruction and no penalty associated - * for using 16-bit variables. With no overriding architectural factors, - * just using a uint16_t. - */ -typedef uint16_t Priority_bit_map_Word; - -/** - * @brief SPARC ISR handler return type. - * - * This is the type which SPARC ISR Handlers return. - */ -typedef void sparc_isr; - -/** - * @brief SPARC ISR handler prototype. - * - * This is the prototype for SPARC ISR Handlers. - */ -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/asm.h b/cpukit/score/cpu/sparc64/rtems/asm.h deleted file mode 100644 index f4448b03a5..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/asm.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#ifndef __ASM__ -#define __ASM__ -#endif - -#include <rtems/score/cpuopts.h> -#include <rtems/score/cpu.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */ -/* XXX The following ifdef magic fixes the problem but results in a warning */ -/* XXX when compiling assembly code. */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/rtems/score/cpu.h deleted file mode 100644 index ff56c7121a..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h +++ /dev/null @@ -1,1073 +0,0 @@ -/** - * @file - * - * @brief SPARC64 CPU Department Source - * - * This include file contains information pertaining to the port of - * the executive to the SPARC64 processor. - */ - -/* - * - * - * COPYRIGHT (c) 1989-2006. On-Line Applications Research Corporation (OAR). - * - * This file is based on the SPARC cpu.h file. Modifications are made - * to support the SPARC64 processor. - * COPYRIGHT (c) 2010. Gedare Bloom. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/sparc64.h> - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Does the executive manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * The SPARC does not have a dedicated HW interrupt stack and one has - * been implemented in SW. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * SPARC Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * The SPARC does not have a dedicated HW interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/* - * Do we allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the FLOATING_POINT task attribute is supported. - * If FALSE, then the FLOATING_POINT task attribute is ignored. - */ - -#if ( SPARC_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks FLOATING_POINT tasks implicitly? - * - * If TRUE, then the FLOATING_POINT task attribute is assumed. - * If FALSE, then the FLOATING_POINT task attribute is followed. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * The stack grows to lower addresses on the SPARC. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical data structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The SPARC does not appear to have particularly strict alignment - * requirements. This value (16) was chosen to take advantages of caches. - * - * SPARC 64 requirements on floating point alignment is at least 8, - * and is 16 if quad-word fp instructions are available (e.g. LDQF). - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16))) - -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_BIG_ENDIAN TRUE -#define CPU_LITTLE_ENDIAN FALSE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The SPARC v9 has 16 interrupt levels in the PIL field of the PSR. - */ - -#define CPU_MODES_INTERRUPT_MASK 0x0000000F - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -/* - * This structure represents the organization of the minimum stack frame - * for the SPARC. More framing information is required in certain situaions - * such as when there are a large number of out parameters or when the callee - * must save floating point registers. - */ - -#ifndef ASM - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -typedef struct { - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - void *structure_return_address; - /* - * The following are for the callee to save the register arguments in - * should this be necessary. - */ - uint64_t saved_arg0; - uint64_t saved_arg1; - uint64_t saved_arg2; - uint64_t saved_arg3; - uint64_t saved_arg4; - uint64_t saved_arg5; - uint64_t pad0; -} CPU_Minimum_stack_frame; - -#endif /* !ASM */ - -#define CPU_STACK_FRAME_L0_OFFSET 0x00 -#define CPU_STACK_FRAME_L1_OFFSET 0x08 -#define CPU_STACK_FRAME_L2_OFFSET 0x10 -#define CPU_STACK_FRAME_L3_OFFSET 0x18 -#define CPU_STACK_FRAME_L4_OFFSET 0x20 -#define CPU_STACK_FRAME_L5_OFFSET 0x28 -#define CPU_STACK_FRAME_L6_OFFSET 0x30 -#define CPU_STACK_FRAME_L7_OFFSET 0x38 -#define CPU_STACK_FRAME_I0_OFFSET 0x40 -#define CPU_STACK_FRAME_I1_OFFSET 0x48 -#define CPU_STACK_FRAME_I2_OFFSET 0x50 -#define CPU_STACK_FRAME_I3_OFFSET 0x58 -#define CPU_STACK_FRAME_I4_OFFSET 0x60 -#define CPU_STACK_FRAME_I5_OFFSET 0x68 -#define CPU_STACK_FRAME_I6_FP_OFFSET 0x70 -#define CPU_STACK_FRAME_I7_OFFSET 0x78 -#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 -#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 -#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 -#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 -#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 -#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 -#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 -#define CPU_STACK_FRAME_PAD0_OFFSET 0xB8 - -#define CPU_MINIMUM_STACK_FRAME_SIZE 0xC0 - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On the SPARC, we are relatively conservative in that we save most - * of the CPU state in the context area. The ET (enable trap) bit and - * the CWP (current window pointer) fields of the PSR are considered - * system wide resources and are not maintained on a per-thread basis. - */ - -#ifndef ASM - -typedef struct { - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uint64_t i6_fp; - uint64_t i7; - - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - - uint32_t isr_dispatch_disable; - uint32_t pad; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->o6_sp - -#endif /* ASM */ - -/* - * Offsets of fields with Context_Control for assembly routines. - */ - -#define G1_OFFSET 0x00 -#define G2_OFFSET 0x08 -#define G3_OFFSET 0x10 -#define G4_OFFSET 0x18 -#define G5_OFFSET 0x20 -#define G6_OFFSET 0x28 -#define G7_OFFSET 0x30 - -#define L0_OFFSET 0x38 -#define L1_OFFSET 0x40 -#define L2_OFFSET 0x48 -#define L3_OFFSET 0x50 -#define L4_OFFSET 0x58 -#define L5_OFFSET 0x60 -#define L6_OFFSET 0x68 -#define L7_OFFSET 0x70 - -#define I0_OFFSET 0x78 -#define I1_OFFSET 0x80 -#define I2_OFFSET 0x88 -#define I3_OFFSET 0x90 -#define I4_OFFSET 0x98 -#define I5_OFFSET 0xA0 -#define I6_FP_OFFSET 0xA8 -#define I7_OFFSET 0xB0 - -#define O0_OFFSET 0xB8 -#define O1_OFFSET 0xC0 -#define O2_OFFSET 0xC8 -#define O3_OFFSET 0xD0 -#define O4_OFFSET 0xD8 -#define O5_OFFSET 0xE0 -#define O6_SP_OFFSET 0xE8 -#define O7_OFFSET 0xF0 - -#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 -#define ISR_PAD_OFFSET 0xFC - -/* - * The floating point context area. - */ - -#ifndef ASM - -typedef struct { - double f0; /* f0-f1 */ - double f2; /* f2-f3 */ - double f4; /* f4-f5 */ - double f6; /* f6-f7 */ - double f8; /* f8-f9 */ - double f10; /* f10-f11 */ - double f12; /* f12-f13 */ - double f14; /* f14-f15 */ - double f16; /* f16-f17 */ - double f18; /* f18-f19 */ - double f20; /* f20-f21 */ - double f22; /* f22-f23 */ - double f24; /* f24-f25 */ - double f26; /* f26-f27 */ - double f28; /* f28-f29 */ - double f30; /* f30-f31 */ - double f32; - double f34; - double f36; - double f38; - double f40; - double f42; - double f44; - double f46; - double f48; - double f50; - double f52; - double f54; - double f56; - double f58; - double f60; - double f62; - uint64_t fsr; -} Context_Control_fp; - -#endif /* !ASM */ - -/* - * Offsets of fields with Context_Control_fp for assembly routines. - */ - -#define FO_OFFSET 0x00 -#define F2_OFFSET 0x08 -#define F4_OFFSET 0x10 -#define F6_OFFSET 0x18 -#define F8_OFFSET 0x20 -#define F1O_OFFSET 0x28 -#define F12_OFFSET 0x30 -#define F14_OFFSET 0x38 -#define F16_OFFSET 0x40 -#define F18_OFFSET 0x48 -#define F2O_OFFSET 0x50 -#define F22_OFFSET 0x58 -#define F24_OFFSET 0x60 -#define F26_OFFSET 0x68 -#define F28_OFFSET 0x70 -#define F3O_OFFSET 0x78 -#define F32_OFFSET 0x80 -#define F34_OFFSET 0x88 -#define F36_OFFSET 0x90 -#define F38_OFFSET 0x98 -#define F4O_OFFSET 0xA0 -#define F42_OFFSET 0xA8 -#define F44_OFFSET 0xB0 -#define F46_OFFSET 0xB8 -#define F48_OFFSET 0xC0 -#define F5O_OFFSET 0xC8 -#define F52_OFFSET 0xD0 -#define F54_OFFSET 0xD8 -#define F56_OFFSET 0xE0 -#define F58_OFFSET 0xE8 -#define F6O_OFFSET 0xF0 -#define F62_OFFSET 0xF8 -#define FSR_OFFSET 0x100 - -#define CONTEXT_CONTROL_FP_SIZE 0x108 - -#ifndef ASM - -/* - * Context saved on stack for an interrupt. - * - * NOTE: The tstate, tpc, and tnpc are saved in this structure - * to allow resetting the TL while still being able to return - * from a trap later. The PIL is saved because - * if this is an external interrupt, we will mask lower - * priority interrupts until finishing. Even though the y register - * is deprecated, gcc still uses it. - */ - -typedef struct { - CPU_Minimum_stack_frame Stack_frame; - uint64_t tstate; - uint64_t tpc; - uint64_t tnpc; - uint64_t pil; - uint64_t y; - uint64_t g1; - uint64_t g2; - uint64_t g3; - uint64_t g4; - uint64_t g5; - uint64_t g6; - uint64_t g7; - uint64_t o0; - uint64_t o1; - uint64_t o2; - uint64_t o3; - uint64_t o4; - uint64_t o5; - uint64_t o6_sp; - uint64_t o7; - uint64_t tvec; -} CPU_Interrupt_frame; - -#endif /* ASM */ - -/* - * Offsets of fields with CPU_Interrupt_frame for assembly routines. - */ - -#define ISF_TSTATE_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00 -#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08 -#define ISF_TNPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10 -#define ISF_PIL_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18 -#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20 -#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28 -#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30 -#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38 -#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40 -#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48 -#define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 -#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x58 -#define ISF_O0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x60 -#define ISF_O1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x68 -#define ISF_O2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x70 -#define ISF_O3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x78 -#define ISF_O4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x80 -#define ISF_O5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x88 -#define ISF_O6_SP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x90 -#define ISF_O7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x98 -#define ISF_TVEC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0 - -#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8 -#ifndef ASM -/* - * This variable is contains the initialize context for the FP unit. - * It is filled in by _CPU_Initialize and copied into the task's FP - * context area during _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT; - -/* - * This flag is context switched with each thread. It indicates - * that THIS thread has an _ISR_Dispatch stack frame on its stack. - * By using this flag, we can avoid nesting more interrupt dispatching - * attempts on a previously interrupted thread's stack. - */ - -SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable; - -/* - * The following type defines an entry in the SPARC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ -/* For SPARC V9, we must use 6 of these instructions to perform a long - * jump, because the _handler value is now 64-bits. We also need to store - * temporary values in the global register set at this trap level. Because - * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3 - * to pass parameters to ISR_Handler. - * - * The instruction sequence is now more like: - * rdpr %tstate, %g4 - * setx _handler, %g2, %g3 - * jmp %g3+0 - * mov _vector, %g2 - */ -typedef struct { - uint32_t rdpr_tstate_g4; /* rdpr %tstate, %g4 */ - uint32_t sethi_of_hh_handler_to_g2; /* sethi %hh(_handler), %g2 */ - uint32_t or_g2_hm_handler_to_g2; /* or %l3, %hm(_handler), %g2 */ - uint32_t sllx_g2_by_32_to_g2; /* sllx %g2, 32, %g2 */ - uint32_t sethi_of_handler_to_g3; /* sethi %hi(_handler), %g3 */ - uint32_t or_g3_g2_to_g3; /* or %g3, %g2, %g3 */ - uint32_t jmp_to_low_of_handler_plus_g3; /* jmp %g3 + %lo(_handler) */ - uint32_t mov_vector_g2; /* mov _vector, %g2 */ -} CPU_Trap_table_entry; - -/* - * This is the set of opcodes for the instructions loaded into a trap - * table entry. The routine which installs a handler is responsible - * for filling in the fields for the _handler address and the _vector - * trap type. - * - * The constants following this structure are masks for the fields which - * must be filled in when the handler is installed. - */ - -extern const CPU_Trap_table_entry _CPU_Trap_slot_template; - -/* - * The size of the floating point context area. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -#endif - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by the executive. - * - * On the SPARC, there are really only 256 vectors. However, the executive - * has no easy, fast, reliable way to determine which traps are synchronous - * and which are asynchronous. By default, synchronous traps return to the - * instruction which caused the interrupt. So if you install a software - * trap handler as an executive interrupt handler (which is desirable since - * RTEMS takes care of window and register issues), then the executive needs - * to know that the return address is to the trap rather than the instruction - * following the trap. - * - * So vectors 0 through 255 are treated as regular asynchronous traps which - * provide the "correct" return address. Vectors 256 through 512 are assumed - * by the executive to be synchronous and to require that the return address - * be fudged. - * - * If you use this mechanism to install a trap handler which must reexecute - * the instruction which caused the trap, then it should be installed as - * an asynchronous trap. This will avoid the executive changing the return - * address. - */ -/* On SPARC v9, there are 512 vectors. The same philosophy applies to - * vector installation and use, we just provide a larger table. - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 512 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 - -#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 -#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) -#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 ) - -#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * This appears to be a fairly generous number for the SPARC since - * represents a call depth of about 20 routines based on the minimum - * stack frame. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 8 - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * On the SPARC, this is required for double word loads and stores. - * - * Note: quad-word loads/stores need alignment of 16, but currently supported - * architectures do not provide HW implemented quad-word operations. - */ - -#define CPU_ALIGNMENT 8 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - * - * The alignment restrictions for the SPARC are not that strict but this - * should unsure that the stack is always sufficiently alignment that the - * window overflow, underflow, and flush routines can use double word loads - * and stores. - */ - -#define CPU_STACK_ALIGNMENT 16 - -#ifndef ASM - -/* - * ISR handler macros - */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for a critical section. The previous - * level is returned in _level. - */ - - #define _CPU_ISR_Disable( _level ) \ - (_level) = sparc_disable_interrupts() - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of a critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - sparc_enable_interrupts( _level ) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - sparc_flash_interrupts( _level ) - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a straight fashion are undefined. - */ - -#define _CPU_ISR_Set_level( _newlevel ) \ - sparc_enable_interrupts( _newlevel) - -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * NOTE: Implemented as a subroutine for the SPARC port. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - void *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/* - * This macro is invoked from _Thread_Handler to do whatever CPU - * specific magic is required that must be done in the context of - * the thread when it starts. - * - * On the SPARC, this is setting the frame pointer so GDB is happy. - * Make GDB stop unwinding at _Thread_Handler, previous register window - * Frame pointer is 0 and calling address must be a function with starting - * with a SAVE instruction. If return address is leaf-function (no SAVE) - * GDB will not look at prev reg window fp. - * - * _Thread_Handler is known to start with SAVE. - */ - -#define _CPU_Context_Initialization_at_thread_begin() \ - do { \ - __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ - } while (0) - -/* - * This routine is responsible for somehow restarting the currently - * executing task. - * - * On the SPARC, this is is relatively painless but requires a small - * amount of wrapper code before using the regular restore code in - * of the context switch. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The FP context area for the SPARC is a simple structure and nothing - * special is required to find the "starting load point" - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * - * The SPARC allows us to use the simple initialization model - * in which an "initial" FP context was saved into _CPU_Null_fp_context - * at CPU initialization and it is simply copied into the destination - * context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - do { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } while (0) - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - uint32_t level; \ - \ - level = sparc_disable_interrupts(); \ - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 0 ) -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE -#else -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Bitfield handler macros */ - -/* Priority handler handler macros */ - -/* - * The SPARC port uses the generic C algorithm for bitfield scan if the - * CPU model does not have a scan instruction. - */ - -#if ( SPARC_HAS_BITSCAN == 1 ) -#error "scan instruction not currently supported by RTEMS!!" -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize(void); - -/* - * _CPU_ISR_install_raw_handler - * - * This routine installs new_handler to be directly called from the trap - * table. - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - uint64_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) - -/* - * _CPU_Thread_Idle_body - * - * Some SPARC implementations have low power, sleep, or idle modes. This - * tries to take advantage of those models. - */ - -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */ - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. - */ - -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/* - * CPU_swap_u32 - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if you come across a better - * way for the SPARC PLEASE use it. The most common way to swap a 32-bit - * entity as shown below is not any more efficient on the SPARC. - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * It is not obvious how the SPARC can do significantly better than the - * generic code. gcc 2.7.0 only generates about 12 instructions for the - * following code at optimization level four (i.e. -O4). - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/sparc64/rtems/score/types.h b/cpukit/score/cpu/sparc64/rtems/score/types.h deleted file mode 100644 index c4d1c7f85e..0000000000 --- a/cpukit/score/cpu/sparc64/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief SPARC64 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * SPARC-v9 processor family. - */ - -/* - * COPYRIGHT (c) 1989-1999. On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -typedef uint16_t Priority_bit_map_Word; -typedef void sparc_isr; -typedef void ( *sparc_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/cpukit/score/cpu/v850/rtems/asm.h b/cpukit/score/cpu/v850/rtems/asm.h deleted file mode 100644 index 265e4967ae..0000000000 --- a/cpukit/score/cpu/v850/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2012. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/no_cpu.h> - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include <rtems/concat.h> - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h deleted file mode 100644 index c531d0c131..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpu.h +++ /dev/null @@ -1,1209 +0,0 @@ -/** - * @file - * - * @brief V850 CPU Department Source - * - * This include file contains information pertaining to the v850 - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/v850.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * The v850 is a RISC CPU which typically has enough memory to justify - * the inlining of this method. - */ -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * The v850 does not have support for a hardware interrupt stack. - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * This port uses the Progammable Interrupt Controller interrupt model. - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * The v850 does not have support for a hardware interrupt stack. - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "V850_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * Some v850 models do have IEEE hardware floating point support but - * they do not have any special registers to save or bit(s) which - * determine if the FPU is enabled. In short, there appears to be nothing - * related to the floating point operations which impact the RTEMS - * thread context switch. Thus from an RTEMS perspective, there is really - * no FPU to manage. - */ -#define CPU_HARDWARE_FP FALSE -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * This should be false until it has been demonstrated that gcc for the - * v850 generates FPU code when it is unexpected. But even this would - * not matter since there are no FP specific registers or bits which - * would be corrupted if an FP operation occurred in an integer only - * thread. - */ -#define CPU_ALL_TASKS_ARE_FP FALSE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * The IDLE thread should not be using the FPU. Leave this off. - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * See earlier comments. There is no FPU state to manage. - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * There does not appear to be a reason for the v850 port itself to provide - * a special idle task. - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * The v850 stack grows from high addresses to low addresses. - */ -#define CPU_STACK_GROWS_UP FALSE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * Until proven otherwise, use the compiler default. - */ -#define CPU_STRUCTURE_ALIGNMENT - -/** - * The v850 should use 64-bit timestamps and inline them. - */ -#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - * - */ -/**@{**/ - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * The v850 is little endian. - */ -#define CPU_BIG_ENDIAN FALSE - -/** - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * The v850 is little endian. - */ -#define CPU_LITTLE_ENDIAN TRUE - -/** @} */ - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * The v850 only has a single bit in the CPU for interrupt disable/enable. - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -typedef struct { - /* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * On the v850, this port saves special registers and those that are - * callee saved. - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r1; - /** This field is the stack pointer (e.g. r3). */ - uint32_t r3_stack_pointer; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t r28; - uint32_t r29; - uint32_t r31; - uint32_t psw; -} Context_Control; - -/** - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r3_stack_pointer - -/** - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * The v850 does not need a floating point context but this needs to be - * defined so confdefs.h. - */ -/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */ -#define CPU_CONTEXT_FP_SIZE 0 - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * There is no reason to think the v850 needs extra MPCI receive - * server stack. - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** @} */ - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * This should be very conservative on the v850. - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than 8. - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than CPU_ALIGNMENT. - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * There is no apparent reason why this should be larger than CPU_ALIGNMENT. - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * The v850 has enough RAM where alignment to 16 may be desirable depending - * on the cache properties. But this remains to be demonstrated. - */ -#define CPU_STACK_ALIGNMENT 4 - -/* - * ISR handler macros - */ - -/** - * @addtogroup CPUInterrupt - */ -/**@{**/ - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * On the v850, we need to save the PSW and use "di" to disable interrupts. - */ -#define _CPU_ISR_Disable( _isr_cookie ) \ - do { \ - unsigned int _psw; \ - \ - v850_get_psw( _psw ); \ - __asm__ __volatile__( "di" ); \ - _isr_cookie = _psw; \ - } while (0) - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * On the v850, we simply need to restore the PSW. - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - do { \ - unsigned int _psw = (_isr_cookie); \ - \ - v850_set_psw( _psw ); \ - } while (0) - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * This saves at least one instruction over using enable/disable back to back. - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - do { \ - unsigned int _psw = (_isr_cookie); \ - v850_set_psw( _psw ); \ - __asm__ __volatile__( "di" ); \ - } while (0) - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * On the v850, level 0 is enabled. Non-zero is disabled. - */ -#define _CPU_ISR_Set_level( new_level ) \ - do { \ - if ( new_level ) \ - __asm__ __volatile__( "di" ); \ - else \ - __asm__ __volatile__( "ei" ); \ - } while (0) - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * This method is implemented in C on the v850. - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @ingroup CPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * This method is implemented in C on the v850. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * On the v850, we require a special entry point to restart a task. - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* XXX this should be possible to remove */ -#if 0 -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) -#endif - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - } -#endif - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * Move the error code into r10, disable interrupts and halt. - */ -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - __asm__ __volatile__ ( "di" ); \ - __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \ - __asm__ __volatile__ ( "halt" ); \ - } while (0) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ -/**@{**/ - -/** - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. The empty - * stub routines are left as a place holder in case someone figures - * out how to do a v850 implementation better than the generic algorithm. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Word. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * There is no single v850 instruction to do a bit scan so there is - * no CPU specific implementation of bit field scanning. - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/** @} */ - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * This is implemented in C. - * - * v850 CPU Dependent Source - */ -void _CPU_Initialize(void); - -/** - * @addtogroup CPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * This is implemented in assembly on the v850. - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * This is implemented in assembly on the v850. - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_NO_RETURN; - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -/* XXX this should be possible to remove */ -#if 0 -/** - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - while (1) { - /* TODO */ - } -} - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * The v850 has a single instruction to swap endianness on a 32 bit quantity. - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - unsigned int swapped; - - #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) - unsigned int v; - - v = value; - __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) ); - #else - uint32_t byte1, byte2, byte3, byte4; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - #endif - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * The v850 has a single instruction to swap endianness on a 16 bit quantity. - */ -static inline uint16_t CPU_swap_u16( uint16_t value ) -{ - unsigned int swapped; - - #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) - unsigned int v; - - v = value; - __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) ); - #else - swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff); - #endif - return swapped; -} - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -static inline CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -) -{ - return second - first; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h deleted file mode 100644 index 8a74cc6410..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file - * - * @brief V850 Assembly File - * Very loose template for an include file for the cpu_asm.? file - * if it is implemented as a ".S" file (preprocessed by cpp) instead - * of a ".s" file (preprocessed by gm4 or gasp). - */ - -/* - * COPYRIGHT (c) 1989-2012. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - -/* pull in the generated offsets */ - -#include <rtems/score/offsets.h> - -/* - * Hardware General Registers - */ - -/* put something here */ - -/* - * Hardware Floating Point Registers - */ - -/* put something here */ - -/* - * Hardware Control Registers - */ - -/* put something here */ - -/* - * Calling Convention - */ - -/* put something here */ - -/* - * Temporary registers - */ - -/* put something here */ - -/* - * Floating Point Registers - SW Conventions - */ - -/* put something here */ - -/* - * Temporary floating point registers - */ - -/* put something here */ - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/v850/rtems/score/types.h b/cpukit/score/cpu/v850/rtems/score/types.h deleted file mode 100644 index a209d091f3..0000000000 --- a/cpukit/score/cpu/v850/rtems/score/types.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * @file - * - * @brief V850 CPU Type Definitions - * - * This include file contains type definitions pertaining to the - * v850 processor family. - */ - -/* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_TYPES_H -#define _RTEMS_SCORE_TYPES_H - -#include <rtems/score/basedefs.h> - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -/** This defines the type for a priority bit map entry. */ -typedef uint16_t Priority_bit_map_Word; - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif diff --git a/c/src/lib/libbsp/i386/shared/irq/apic.h b/include/bsp/apic.h index 9ae103b963..9ae103b963 100644 --- a/c/src/lib/libbsp/i386/shared/irq/apic.h +++ b/include/bsp/apic.h diff --git a/c/src/lib/libbsp/i386/shared/smp/smp-imps.h b/include/bsp/smp-imps.h index 60e688547b..60e688547b 100644 --- a/c/src/lib/libbsp/i386/shared/smp/smp-imps.h +++ b/include/bsp/smp-imps.h |