diff options
author | Jiri Gaisler <jiri@gaisler.se> | 2020-12-05 17:49:25 +0100 |
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committer | Jiri Gaisler <jiri@gaisler.se> | 2020-12-15 15:28:09 +0100 |
commit | 36b4b0a9b95a351fc99ca3224503dab9e29af865 (patch) | |
tree | 2364018e2cc1e3118672e841b84bc545caf316a8 /elf.c | |
parent | Added emulation of GR740 SOC (diff) | |
download | sis-36b4b0a9b95a351fc99ca3224503dab9e29af865.tar.bz2 |
Added support for RISCV32 systems with CLINT/PLIC
Diffstat (limited to 'elf.c')
-rw-r--r-- | elf.c | 15 |
1 files changed, 12 insertions, 3 deletions
@@ -85,14 +85,22 @@ read_elf_header (FILE * fp) case EM_SPARC: if (sis_verbose) printf ("SPARC executable\n"); - efile.arch = CPU_ERC32; - efile.cpu = CPU_ERC32; + efile.arch = CPU_SPARC; + if (ehdr.e_entry == 0) + efile.cpu = CPU_LEON4; + else if (ehdr.e_entry == 0x40000000) + efile.cpu = CPU_LEON3; + else if (ehdr.e_entry == 0x2000000) + efile.cpu = CPU_ERC32; break; case EM_RISCV: if (sis_verbose) printf ("RISCV executable\n"); efile.arch = CPU_RISCV; - efile.cpu = CPU_RISCV; + if (ehdr.e_entry == 0x40000000) + efile.cpu = CPU_LEON3; + else if (ehdr.e_entry == 0x80000000) + efile.cpu = CPU_RISCV; break; default: printf ("Unknown architecture (%d)\n", ehdr.e_machine); @@ -106,6 +114,7 @@ read_elf_header (FILE * fp) } efile.ehdr = ehdr; ebase.cpu = efile.cpu; + ebase.arch = efile.arch; return (ehdr.e_entry); } |