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authorJiri Gaisler <jiri@gaisler.se>2020-12-05 17:49:25 +0100
committerJiri Gaisler <jiri@gaisler.se>2020-12-15 15:28:09 +0100
commit36b4b0a9b95a351fc99ca3224503dab9e29af865 (patch)
tree2364018e2cc1e3118672e841b84bc545caf316a8
parentAdded emulation of GR740 SOC (diff)
downloadsis-36b4b0a9b95a351fc99ca3224503dab9e29af865.tar.bz2
Added support for RISCV32 systems with CLINT/PLIC
Diffstat
-rw-r--r--Makefile.am8
-rw-r--r--Makefile.in13
-rwxr-xr-xconfigure20
-rw-r--r--configure.ac2
-rw-r--r--elf.c15
-rw-r--r--exec.c15
-rw-r--r--func.c3
-rw-r--r--gr740.c2
-rw-r--r--greth.c6
-rw-r--r--grlib.c284
-rw-r--r--grlib.h8
-rw-r--r--help.c3
-rw-r--r--interf.c2
-rw-r--r--leon3.c4
-rw-r--r--riscv.c64
-rw-r--r--riscv.h3
-rw-r--r--rv32.c273
-rw-r--r--rv32.dts251
-rw-r--r--rv32dtb.h394
-rw-r--r--sis.c100
-rw-r--r--sis.h13
-rw-r--r--sis.info78
-rw-r--r--sis.texi47
-rw-r--r--sparc.c10
-rw-r--r--version.texi6
25 files changed, 1485 insertions, 139 deletions
diff --git a/Makefile.am b/Makefile.am
index 384a58f..6a94413 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -7,12 +7,16 @@ endif
bin_PROGRAMS = sis
sis_SOURCES = erc32.c grlib.c leon3.c exec.c func.c help.c \
sparc.c riscv.c leon2.c sis.c interf.c remote.c elf.c \
- greth.c tap.c gr740.c \
+ greth.c tap.c gr740.c rv32.c \
$(LN_SRC)
AM_CFLAGS = -DFAST_UART
sis_LDADD = -lm @READLINE@ @LIBADD@
-EXTRA_DIST = elf.h grlib.h linenoise.h riscv.h sis.h sparc.h
+EXTRA_DIST = elf.h grlib.h linenoise.h riscv.h sis.h sparc.h rv32dtb.h
+
+rv32dtb.h: $(abs_srcdir)/rv32.dts
+ dtc -O dtb $(abs_srcdir)/rv32.dts -o rv32.dtb
+ xxd --include rv32.dtb > rv32dtb.h
info_TEXINFOS = sis.texi
diff --git a/Makefile.in b/Makefile.in
index d11bca3..a621756 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -79,13 +79,13 @@ am__installdirs = "$(DESTDIR)$(bindir)" "$(DESTDIR)$(infodir)"
PROGRAMS = $(bin_PROGRAMS)
am__sis_SOURCES_DIST = erc32.c grlib.c leon3.c exec.c func.c help.c \
sparc.c riscv.c leon2.c sis.c interf.c remote.c elf.c greth.c \
- tap.c gr740.c linenoise.c
+ tap.c gr740.c rv32.c linenoise.c
@LINENOISE_TRUE@am__objects_1 = linenoise.$(OBJEXT)
am_sis_OBJECTS = erc32.$(OBJEXT) grlib.$(OBJEXT) leon3.$(OBJEXT) \
exec.$(OBJEXT) func.$(OBJEXT) help.$(OBJEXT) sparc.$(OBJEXT) \
riscv.$(OBJEXT) leon2.$(OBJEXT) sis.$(OBJEXT) interf.$(OBJEXT) \
remote.$(OBJEXT) elf.$(OBJEXT) greth.$(OBJEXT) tap.$(OBJEXT) \
- gr740.$(OBJEXT) $(am__objects_1)
+ gr740.$(OBJEXT) rv32.$(OBJEXT) $(am__objects_1)
sis_OBJECTS = $(am_sis_OBJECTS)
sis_DEPENDENCIES =
DEFAULT_INCLUDES = -I.@am__isrc@
@@ -266,12 +266,12 @@ top_srcdir = @top_srcdir@
@LINENOISE_TRUE@LN_SRC = linenoise.c
sis_SOURCES = erc32.c grlib.c leon3.c exec.c func.c help.c \
sparc.c riscv.c leon2.c sis.c interf.c remote.c elf.c \
- greth.c tap.c gr740.c \
+ greth.c tap.c gr740.c rv32.c \
$(LN_SRC)
AM_CFLAGS = -DFAST_UART
sis_LDADD = -lm @READLINE@ @LIBADD@
-EXTRA_DIST = elf.h grlib.h linenoise.h riscv.h sis.h sparc.h
+EXTRA_DIST = elf.h grlib.h linenoise.h riscv.h sis.h sparc.h rv32dtb.h
info_TEXINFOS = sis.texi
all: config.h
$(MAKE) $(AM_MAKEFLAGS) all-am
@@ -391,6 +391,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/linenoise.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/remote.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/riscv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rv32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sis.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sparc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tap.Po@am__quote@
@@ -1033,6 +1034,10 @@ uninstall-am: uninstall-binPROGRAMS uninstall-dvi-am uninstall-html-am \
uninstall-info-am uninstall-pdf-am uninstall-ps-am
+rv32dtb.h: $(abs_srcdir)/rv32.dts
+ dtc -O dtb $(abs_srcdir)/rv32.dts -o rv32.dtb
+ xxd --include rv32.dtb > rv32dtb.h
+
.PHONY: v
v: version.texi
diff --git a/configure b/configure
index 963d11f..023ecd8 100755
--- a/configure
+++ b/configure
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.69 for sis 2.25.
+# Generated by GNU Autoconf 2.69 for sis 2.26.
#
#
# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
@@ -577,8 +577,8 @@ MAKEFLAGS=
# Identity of this package.
PACKAGE_NAME='sis'
PACKAGE_TARNAME='sis'
-PACKAGE_VERSION='2.25'
-PACKAGE_STRING='sis 2.25'
+PACKAGE_VERSION='2.26'
+PACKAGE_STRING='sis 2.26'
PACKAGE_BUGREPORT=''
PACKAGE_URL=''
@@ -1283,7 +1283,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures sis 2.25 to adapt to many kinds of systems.
+\`configure' configures sis 2.26 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1354,7 +1354,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of sis 2.25:";;
+ short | recursive ) echo "Configuration of sis 2.26:";;
esac
cat <<\_ACEOF
@@ -1444,7 +1444,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-sis configure 2.25
+sis configure 2.26
generated by GNU Autoconf 2.69
Copyright (C) 2012 Free Software Foundation, Inc.
@@ -1742,7 +1742,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by sis $as_me 2.25, which was
+It was created by sis $as_me 2.26, which was
generated by GNU Autoconf 2.69. Invocation command line was
$ $0 $@
@@ -2569,7 +2569,7 @@ fi
# Define the identity of the package.
PACKAGE='sis'
- VERSION='2.25'
+ VERSION='2.26'
cat >>confdefs.h <<_ACEOF
@@ -4911,7 +4911,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by sis $as_me 2.25, which was
+This file was extended by sis $as_me 2.26, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -4977,7 +4977,7 @@ _ACEOF
cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
ac_cs_version="\\
-sis config.status 2.25
+sis config.status 2.26
configured by $0, generated by GNU Autoconf 2.69,
with options \\"\$ac_cs_config\\"
diff --git a/configure.ac b/configure.ac
index 9a46dcb..b824fba 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,4 +1,4 @@
-AC_INIT([sis], [2.25])
+AC_INIT([sis], [2.26])
AC_CONFIG_SRCDIR([sis.c])
AC_CONFIG_AUX_DIR([build-aux])
AC_CONFIG_HEADERS(config.h)
diff --git a/elf.c b/elf.c
index 384502e..7ab6005 100644
--- a/elf.c
+++ b/elf.c
@@ -85,14 +85,22 @@ read_elf_header (FILE * fp)
case EM_SPARC:
if (sis_verbose)
printf ("SPARC executable\n");
- efile.arch = CPU_ERC32;
- efile.cpu = CPU_ERC32;
+ efile.arch = CPU_SPARC;
+ if (ehdr.e_entry == 0)
+ efile.cpu = CPU_LEON4;
+ else if (ehdr.e_entry == 0x40000000)
+ efile.cpu = CPU_LEON3;
+ else if (ehdr.e_entry == 0x2000000)
+ efile.cpu = CPU_ERC32;
break;
case EM_RISCV:
if (sis_verbose)
printf ("RISCV executable\n");
efile.arch = CPU_RISCV;
- efile.cpu = CPU_RISCV;
+ if (ehdr.e_entry == 0x40000000)
+ efile.cpu = CPU_LEON3;
+ else if (ehdr.e_entry == 0x80000000)
+ efile.cpu = CPU_RISCV;
break;
default:
printf ("Unknown architecture (%d)\n", ehdr.e_machine);
@@ -106,6 +114,7 @@ read_elf_header (FILE * fp)
}
efile.ehdr = ehdr;
ebase.cpu = efile.cpu;
+ ebase.arch = efile.arch;
return (ehdr.e_entry);
}
diff --git a/exec.c b/exec.c
index 0805b38..5a322e3 100644
--- a/exec.c
+++ b/exec.c
@@ -136,12 +136,12 @@ init_regs (sregs)
sregs[i].npc = 4;
sregs[i].trap = 0;
sregs[i].psr &= 0x00f03fdf;
- if (cputype == CPU_LEON3)
- sregs[i].psr |= 0xF3000080; /* Set supervisor bit */
+ if (cputype == CPU_ERC32)
+ sregs[i].psr |= 0x11000080; /* Set supervisor bit */
else if (cputype == CPU_LEON2)
sregs[i].psr |= 0x00000080; /* Set supervisor bit */
else
- sregs[i].psr |= 0x11000080; /* Set supervisor bit */
+ sregs[i].psr |= 0xF3000080; /* Set supervisor bit */
sregs[i].breakpoint = 0;
sregs[i].fpstate = 0;
sregs[i].fpqn = 0;
@@ -163,12 +163,9 @@ init_regs (sregs)
sregs[i].rett_err = 0;
sregs[i].jmpltime = 0;
- if (cputype == CPU_LEON3)
- {
- sregs[i].asr17 = 0x04000107 | (i << 28);
- if (!nfp)
- sregs[i].asr17 |= (3 << 10); /* Meiko FPU */
- }
+ sregs[i].asr17 = 0x04000107 | (i << 28);
+ if (!nfp)
+ sregs[i].asr17 |= (3 << 10); /* Meiko FPU */
sregs[i].cpu = i;
sregs[i].simtime = 0;
sregs[i].pwdtime = 0;
diff --git a/func.c b/func.c
index 36f9254..3df7b68 100644
--- a/func.c
+++ b/func.c
@@ -68,7 +68,8 @@ char bridge[32] = "";
char romb[MAX_ROM_SIZE];
char ramb[MAX_RAM_SIZE];
const struct memsys *ms;
-int cputype = 0; /* 0 = erc32, 2 = leon2,3 = leon3, 5 = riscv */
+int cputype = 0;
+int archtype = 0;
int sis_gdb_break;
int cpu = 0; /* active cpu */
int ncpu = 1; /* number of cpus to emulate */
diff --git a/gr740.c b/gr740.c
index 13a8831..6eb070a 100644
--- a/gr740.c
+++ b/gr740.c
@@ -60,7 +60,7 @@ init_sim (void)
grlib_ahbm_add (&leon3s, 0);
grlib_ahbs_add (&apbmst, 0, APBSTART, 0xFFF);
- grlib_ahbs_add (&srctrl, 0, RAM_START, RAM_MASKPP);
+ grlib_ahbs_add (&sdctrl, 0, RAM_START, RAM_MASKPP);
grlib_apb_add (&apbuart, 3, APBSTART + 0x02000, 0xFFF);
grlib_apb_add (&irqmp, 0, APBSTART + 0x04000, 0xFFF);
diff --git a/greth.c b/greth.c
index 0b6d0ca..f100b91 100644
--- a/greth.c
+++ b/greth.c
@@ -31,6 +31,7 @@
#include <arpa/inet.h>
#include "sis.h"
+#include "grlib.h"
#define MDIO_WRITE 1
#define MDIO_READ 2
@@ -64,6 +65,7 @@ static unsigned char *greth_rxbufptr;
static unsigned char greth_mac[6];
static long unsigned mac;
static const char broadcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+int greth_irq;
/* Simple emulation of Microchip KSZ8041NL/RNL PHY */
@@ -138,7 +140,7 @@ greth_tx (void)
sis_tap_write (greth_txbufptr, greth_txdesc & 0x7ff);
greth_status |= STATUS_TI;
if ((greth_ctrl & CTRL_TI) && (greth_txdesc & DESC_IE))
- ms->set_irq (6);
+ grlib_set_irq (greth_irq);
if (sis_verbose)
printf ("packet transmitted, len %d, desc %d\n",
greth_txdesc & 0x7ff, (greth_txbase & BASE_PNT) >> 3);
@@ -299,7 +301,7 @@ greth_rxready (unsigned char *buffer, int len)
greth_rxbase += 8;
if ((greth_ctrl & CTRL_RI) && (greth_rxdesc & DESC_IE))
- ms->set_irq (6);
+ grlib_set_irq (greth_irq);
}
else if (sis_verbose > 1)
printf ("net: received packet dropped!\n");
diff --git a/grlib.c b/grlib.c
index 478e9bb..fc99df9 100644
--- a/grlib.c
+++ b/grlib.c
@@ -18,7 +18,7 @@
*
*/
-#include "config.h"
+#include "riscv.h"
#include <stdio.h>
#include <inttypes.h>
#ifdef HAVE_TERMIOS_H
@@ -29,7 +29,6 @@
#include <errno.h>
#include <sys/types.h>
#include <string.h>
-#include "sis.h"
#include "grlib.h"
@@ -169,9 +168,9 @@ grlib_read (uint32 addr, uint32 * data)
{
if (ahbscores[i].core->read)
res = ahbscores[i].core->read (addr & ahbscores[i].mask, data);
- if (sis_verbose > 2)
- printf ("AHB read a: %08x, d: %08x\n", addr, *data);
- break;
+ else
+ res = 1;
+ return !res;
}
if (!res && ((addr >= AHBPP_START) && (addr <= AHBPP_END)))
@@ -196,6 +195,8 @@ grlib_write (uint32 addr, uint32 * data, uint32 sz)
{
if (ahbscores[i].core->write)
res = ahbscores[i].core->write (addr & ahbscores[i].mask, data, sz);
+ else
+ res = 1;
if (sis_verbose > 2)
printf ("AHB write a: %08x, d: %08x\n", addr, *data);
break;
@@ -221,6 +222,7 @@ grlib_apb_add (const struct grlib_ipcore *core, int irq,
/* ------------------- GRETH -----------------------*/
+extern int greth_irq;
static int
grlib_greth_read (uint32 addr, uint32 * data)
@@ -238,8 +240,11 @@ static void
greth_add (int irq, uint32 addr, uint32 mask)
{
grlib_ahbmpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_GRETH, 0, 0));
- grlib_apbpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_GRETH, 0, 6),
+ grlib_apbpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_GRETH, 0, irq),
GRLIB_PP_APBADDR (addr, mask));
+ greth_irq = irq;
+ if (sis_verbose)
+ printf(" GRETH 10/100 Mbit Ethernet core 0x%08x %d\n", addr, irq);
}
const struct grlib_ipcore greth = {
@@ -253,6 +258,8 @@ static void
leon3_add ()
{
grlib_ahbmpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_LEON3, 0, 0));
+ if (sis_verbose)
+ printf(" LEON3 SPARC V8 processor \n");
}
const struct grlib_ipcore leon3s = {
@@ -326,6 +333,8 @@ apbmst_add (int irq, uint32 addr, uint32 mask)
{
grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_APBMST, 0, 0),
GRLIB_PP_AHBADDR (addr, mask, 0, 0, 2), 0, 0, 0);
+ if (sis_verbose)
+ printf(" AHB/APB Bridge 0x%08x\n", addr);
}
const struct grlib_ipcore apbmst = {
@@ -588,6 +597,8 @@ irqmp_add (int irq, uint32 addr, uint32 mask)
{
grlib_apbpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_IRQMP, 2, 0),
GRLIB_PP_APBADDR (addr, mask));
+ if (sis_verbose)
+ printf(" IRQMP Interrupt controller 0x%08x\n", addr);
}
const struct grlib_ipcore irqmp = {
@@ -659,6 +670,8 @@ gpt_add (int irq, uint32 addr, uint32 mask)
grlib_apbpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_GPTIMER, 0, irq),
GRLIB_PP_APBADDR (addr, mask));
gpt_irq = irq;
+ if (sis_verbose)
+ printf(" GPTIMER timer unit 0x%08x %d\n", addr, irq);
}
static void
@@ -1209,13 +1222,15 @@ apbuart_add (int irq, uint32 addr, uint32 mask)
{
grlib_apbpp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_APBUART, 1, irq),
GRLIB_PP_APBADDR (addr, mask));
+ if (sis_verbose)
+ printf(" APBUART serial port 0x%08x %d\n", addr, irq);
}
const struct grlib_ipcore apbuart = {
apbuart_init, apbuart_reset, apbuart_read, apbuart_write, apbuart_add
};
-/* ------------------- SRCTRL -----------------------*/
+/* ------------------- SDCTRL -----------------------*/
/* Store data in host byte order. MEM points to the beginning of the
emulated memory; WADDR contains the index the emulated memory,
@@ -1246,39 +1261,69 @@ grlib_store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz)
}
static int
-srctrl_write (uint32 addr, uint32 * data, uint32 sz)
+sdctrl_write (uint32 addr, uint32 * data, uint32 sz)
{
grlib_store_bytes (ramb, addr, data, sz);
return 1;
}
static int
-srctrl_read (uint32 addr, uint32 * data)
+sdctrl_read (uint32 addr, uint32 * data)
{
memcpy (data, &ramb[addr & ~0x3], 4);
return 4;
}
static void
+sdctrl_add (int irq, uint32 addr, uint32 mask)
+{
+ grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_SDCTRL, 0, 0),
+ GRLIB_PP_AHBADDR (addr, mask, 1, 1, 2), 0, 0, 0);
+ if (sis_verbose)
+ printf(" SDRAM controller %d M 0x%08x\n",
+ (~(mask << 20) + 1) >> 20, addr);
+}
+
+const struct grlib_ipcore sdctrl = {
+ NULL, NULL, sdctrl_read, sdctrl_write, sdctrl_add
+};
+
+/* ------------------- srctrl -----------------------*/
+/* used only for ROM access */
+
+static int
+srctrl_write (uint32 addr, uint32 * data, uint32 sz)
+{
+ grlib_store_bytes (romb, addr, data, sz);
+ return 1;
+}
+
+static int
+srctrl_read (uint32 addr, uint32 * data)
+{
+ memcpy (data, &romb[addr & ~0x3], 4);
+ return 4;
+}
+
+static void
srctrl_add (int irq, uint32 addr, uint32 mask)
{
grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_GAISLER, GAISLER_SRCTRL, 0, 0),
GRLIB_PP_AHBADDR (addr, mask, 1, 1, 2), 0, 0, 0);
if (sis_verbose)
- printf ("RAM start: 0x%x, RAM size: %d K\n",
- addr, ((~mask << 20) + 1) / 1024);
+ printf(" PROM controller %d M 0x%08x\n",
+ (~(mask << 20) + 1) >> 20, addr);
}
const struct grlib_ipcore srctrl = {
NULL, NULL, srctrl_read, srctrl_write, srctrl_add
};
+/* ------------------- boot init --------------------*/
void
grlib_boot_init (void)
{
uint32 tmp;
- /* Generate 1 MHz RTC tick. */
-// apb_write (GPTIMER_SCALER, ebase.freq - 1);
tmp = ebase.freq - 1;
gpt_write (GPTIMER_SCLOAD, &tmp, 2);
tmp = -1;
@@ -1287,3 +1332,216 @@ grlib_boot_init (void)
tmp = 7;
gpt_write (GPTIMER_CTRL1, &tmp, 2);
}
+
+/* ------------------- ns16550 -----------------------*/
+
+static int32 uart_lcr;
+
+static void
+ns16550_add (int irq, uint32 addr, uint32 mask)
+{
+ grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_CONTRIB, CONTRIB_NS16550, 0, 0),
+ GRLIB_PP_AHBADDR (addr, mask, 0, 0, 2), 0, 0, 0);
+ if (sis_verbose)
+ printf(" NS16550 UART 0x%08x %d\n", addr, irq);
+}
+
+static int
+ns16550_write (uint32 addr, uint32 * data, uint32 sz)
+{
+ switch (addr & 0xff)
+ {
+ case 0:
+ if (!uart_lcr)
+ putchar (*data & 0xff);
+ break;
+ case 0x0c:
+ uart_lcr = *data & 0x80;
+ break;
+ }
+
+ return 1;
+}
+
+static int
+ns16550_read (uint32 addr, uint32 * data)
+{
+ *data = 0;
+ switch (addr & 0xff)
+ {
+ case 0x10:
+ *data = 0x03;
+ break;
+ case 0x14:
+ *data = 0x60;
+ break;
+ }
+ return 4;
+}
+
+static void
+ns16550_reset (void)
+{
+ uart_lcr = 0;
+}
+
+const struct grlib_ipcore ns16550 = {
+ NULL, ns16550_reset, ns16550_read, ns16550_write, ns16550_add
+};
+
+/* ------------------- clint -------------------------*/
+
+static void
+clint_add (int irq, uint32 addr, uint32 mask)
+{
+ grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_CONTRIB, CONTRIB_CLINT, 0, 0),
+ GRLIB_PP_AHBADDR (addr, mask, 0, 0, 2), 0, 0, 0);
+ if (sis_verbose)
+ printf(" CLINT Interrupt controller 0x%08x %d\n", addr, irq);
+}
+
+#define CLINTSTART 0x00000
+#define CLINTEND 0x10000
+#define CLINT_TIMECMP 0x04000
+#define CLINT_TIMEBASE 0x0BFF8
+static int
+clint_read (uint32 addr, uint32 * data)
+{
+ uint64 tmp;
+ int reg, cpuid;
+
+ reg = (addr >> 2) & 1;
+ cpuid = ((addr >> 3) % NCPU);
+ if ((addr >= CLINT_TIMEBASE) && (addr < CLINTEND))
+ {
+ tmp = ebase.simtime >> 32;
+ if (reg)
+ *data = tmp & 0xffffffff;
+ else
+ *data = ebase.simtime & 0xffffffff;
+ }
+ else if ((addr >= CLINT_TIMECMP) && (addr < CLINT_TIMEBASE))
+ {
+ tmp = sregs[cpuid].mtimecmp >> 32;
+ if (reg)
+ *data = tmp & 0xffffffff;
+ else
+ *data = sregs[cpuid].mtimecmp & 0xffffffff;
+ }
+ else if ((addr >= 0) && (addr < CLINT_TIMECMP))
+ {
+ cpuid = ((addr >> 2) % NCPU);
+ *data = ((sregs[cpuid].mip & MIP_MSIP) >> 4) & 1;
+ }
+
+ return 4;
+}
+
+static void
+set_mtip (int32 arg)
+{
+ sregs[arg].mip |= MIP_MTIP;
+ rv32_check_lirq (arg);
+}
+
+static int
+clint_write (uint32 addr, uint32 * data, uint32 sz)
+{
+ uint64 tmp;
+ int reg, cpuid;
+
+ if ((addr >= CLINTSTART) && (addr < CLINTEND))
+ {
+ reg = (addr >> 2) & 1;
+ if ((addr >= CLINT_TIMECMP) && (addr <= CLINT_TIMEBASE))
+ {
+ cpuid = ((addr >> 3) % NCPU);
+ if (reg)
+ {
+ tmp = sregs[cpuid].mtimecmp & 0xffffffff;
+ sregs[cpuid].mtimecmp = *data;
+ sregs[cpuid].mtimecmp <<= 32;
+ sregs[cpuid].mtimecmp |= tmp;
+ }
+ else
+ {
+ tmp = sregs[cpuid].mtimecmp >> 32;
+ sregs[cpuid].mtimecmp = (tmp << 32) | *data;
+ }
+ remove_event (set_mtip, cpuid);
+ sregs[cpuid].mip &= ~MIP_MTIP;
+ if (sregs[cpuid].mtimecmp <= sregs[cpuid].simtime)
+ sregs[cpuid].mip |= MIP_MTIP;
+ else
+ event (set_mtip, cpuid,
+ sregs[cpuid].mtimecmp - sregs[cpuid].simtime);
+ }
+ else if ((addr >= CLINTSTART) && (addr <= CLINT_TIMECMP))
+ {
+ cpuid = ((addr >> 2) % NCPU);
+ if ((*data & 1) == 1)
+ sregs[cpuid].mip |= MIP_MSIP;
+ else
+ sregs[cpuid].mip &= ~MIP_MSIP;
+ rv32_check_lirq (cpuid);
+ }
+ }
+
+ return 1;
+}
+
+const struct grlib_ipcore clint = {
+ NULL, NULL, clint_read, clint_write, clint_add
+};
+
+/* ------------------- plic --------------------------*/
+/* no functionality supported for now */
+
+static void
+plic_add (int irq, uint32 addr, uint32 mask)
+{
+ grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_CONTRIB, CONTRIB_PLIC, 0, 0),
+ GRLIB_PP_AHBADDR (addr, mask, 0, 0, 2), 0, 0, 0);
+ if (sis_verbose)
+ printf(" PLIC Interrupt controller 0x%08x %d\n", addr, irq);
+}
+
+const struct grlib_ipcore plic = {
+ NULL, NULL, NULL, NULL, plic_add
+};
+
+/* ------------------- sifive test module --------------*/
+/* used to halt processor */
+
+static int
+s5test_write (uint32 addr, uint32 * data, uint32 sz)
+{
+ int i;
+
+ switch (addr & 0xff)
+ {
+ case 0:
+ if (*data == 0x5555)
+ {
+ printf ("Power-off issued, exiting ...\n");
+ for (i=0; i< ncpu; i++)
+ sregs[i].trap = ERROR_TRAP;
+ }
+ break;
+ }
+
+ return 1;
+}
+
+static void
+s5test_add (int irq, uint32 addr, uint32 mask)
+{
+ grlib_ahbspp_add (GRLIB_PP_ID (VENDOR_CONTRIB, CONTRIB_S5TEST, 0, 0),
+ GRLIB_PP_AHBADDR (addr, mask, 0, 0, 2), 0, 0, 0);
+ if (sis_verbose)
+ printf(" S5 Test module 0x%08x %d\n", addr, irq);
+}
+
+const struct grlib_ipcore s5test = {
+ NULL, NULL, NULL, s5test_write, s5test_add
+};
diff --git a/grlib.h b/grlib.h
index 6d7606b..235d56a 100644
--- a/grlib.h
+++ b/grlib.h
@@ -26,6 +26,7 @@
#define VENDOR_GAISLER 1
#define VENDOR_PENDER 2
#define VENDOR_ESA 4
+#define VENDOR_CONTRIB 9
#define VENDOR_DLR 10
/* Devices */
@@ -33,11 +34,16 @@
#define GAISLER_LEON3 0x003
#define GAISLER_APBMST 0x006
#define GAISLER_SRCTRL 0x008
+#define GAISLER_SDCTRL 0x009
#define GAISLER_APBUART 0x00C
#define GAISLER_IRQMP 0x00D
#define GAISLER_GPTIMER 0x011
#define GAISLER_GRETH 0x01D
#define ESA_MCTRL 0x00F
+#define CONTRIB_NS16550 0x050
+#define CONTRIB_CLINT 0x051
+#define CONTRIB_PLIC 0x052
+#define CONTRIB_S5TEST 0x053
/* How to build entries in the plug&play area */
@@ -98,4 +104,4 @@ extern void apbuart_restore_stdio (void);
extern void apbuart_close_port (void);
extern void apbuart_flush (void);
extern const struct grlib_ipcore gptimer, irqmp, apbuart, apbmst,
- greth, leon3s, srctrl;
+ greth, leon3s, srctrl, ns16550, clint, plic, sdctrl, s5test;
diff --git a/help.c b/help.c
index b836878..4db2479 100644
--- a/help.c
+++ b/help.c
@@ -28,7 +28,7 @@ sis_usage ()
printf ("[-m <n>] [-dumbio] [-gdb] [-port port]\n");
printf ("[-cov] [-nfp] [-ift] [-wrp] [-rom8] [-uben]\n");
printf ("[-freq frequency] [-c batch_file]\n");
- printf ("[-erc32] [-leon2] [-leon3] [-ricsv]\n");
+ printf ("[-erc32] [-leon2] [-leon3] [-griscv] [-rv32]\n");
printf ("[-d] [-v] [-rt] [-bridge name] [files]\n");
}
@@ -42,6 +42,7 @@ gen_help ()
printf (" bp print all breakpoints\n");
printf
(" cont [icnt] continue execution for [icnt] instructions\n");
+ printf (" cpu <core> select cpu core for further commands\n");
printf (" deb <level> set debug level\n");
printf
(" dis [addr] [count] disassemble [count] instructions at address [addr]\n");
diff --git a/interf.c b/interf.c
index 421c0ac..edca4e0 100644
--- a/interf.c
+++ b/interf.c
@@ -98,7 +98,7 @@ sim_read (uint32 mem, char *buf, int length)
{
int i, len;
- if (sis_gdb_break && (cputype <= CPU_LEON3) && (length >= 4))
+ if (sis_gdb_break && (archtype == CPU_SPARC) && (length >= 4))
{
if (gdb_sp_read (mem, buf, length))
return length;
diff --git a/leon3.c b/leon3.c
index b4f8dad..d1bb52c 100644
--- a/leon3.c
+++ b/leon3.c
@@ -56,11 +56,11 @@ init_sim (void)
{
int i;
- for (i = 0; i < NCPU; i++)
+ for (i = 0; i < ncpu; i++)
grlib_ahbm_add (&leon3s, 0);
grlib_ahbs_add (&apbmst, 0, APBSTART, 0xFFF);
- grlib_ahbs_add (&srctrl, 0, RAM_START, RAM_MASKPP);
+ grlib_ahbs_add (&sdctrl, 0, RAM_START, RAM_MASKPP);
grlib_apb_add (&apbuart, 3, APBSTART + 0x100, 0xFFF);
grlib_apb_add (&irqmp, 0, APBSTART + 0x200, 0xFFF);
diff --git a/riscv.c b/riscv.c
index 715850d..6d8fa98 100644
--- a/riscv.c
+++ b/riscv.c
@@ -85,6 +85,7 @@ set_csr (address, sregs, value)
struct pstate *sregs;
uint32 value;
{
+ int res = 0;
switch (address)
{
case CSR_MSTATUS:
@@ -121,12 +122,13 @@ set_csr (address, sregs, value)
riscv_set_fsr (sregs->fsr);
break;
default:
- return 1;
+ res = 1;
}
if (sis_verbose > 1)
printf (" %8" PRIu64 " set csr 0x%03X : %08X\n",
sregs->simtime, address, value);
- return 0;
+ rv32_check_lirq (sregs->cpu);
+ return res;
}
int
@@ -134,6 +136,7 @@ get_csr (address, sregs)
uint32 address;
struct pstate *sregs;
{
+ uint64 tmp;
switch (address)
{
case CSR_MSTATUS:
@@ -167,7 +170,8 @@ get_csr (address, sregs)
return (sregs->simtime & 0xffffffff);
break;
case CSR_TIMEH:
- return ((sregs->simtime >> 32) & 0xffffffff);
+ tmp = sregs->simtime >> 32;
+ return tmp & 0xffffffff;
break;
case CSR_MHARTID:
return (sregs->cpu);
@@ -189,6 +193,26 @@ get_csr (address, sregs)
}
}
+int
+rv32_check_lirq (int cpu)
+{
+ uint32 tmpirq;
+
+ if (sregs[cpu].mstatus & MSTATUS_MIE)
+ {
+ tmpirq = sregs[cpu].mip & sregs[cpu].mie;
+ if (tmpirq & MIP_MSIP)
+ ext_irl[cpu] = 0x13;
+ else if (tmpirq & MIP_MTIP)
+ ext_irl[cpu] = 0x17;
+ if ((ext_irl[cpu]) && sregs[cpu].pwd_mode)
+ {
+ sregs[cpu].pwdtime += sregs[cpu].simtime - sregs[cpu].pwdstart;
+ sregs[cpu].pwd_mode = 0;
+ }
+ }
+}
+
static int
riscv_dispatch_instruction (sregs)
struct pstate *sregs;
@@ -1369,6 +1393,7 @@ riscv_dispatch_instruction (sregs)
sregs->mode = sregs->mpp;
sregs->mstatus |= (sregs->mstatus >> 4) & MSTATUS_MIE;
sregs->mstatus |= MSTATUS_MPIE; // set mstatus.mpie
+ rv32_check_lirq (sregs->cpu);
if (ebase.coven)
cov_jmp (sregs->pc, npc);
break;
@@ -1723,20 +1748,20 @@ riscv_dispatch_instruction (sregs)
case 0: /* FSGNJ */
sregs->fsi[frd + BEH] = sregs->fsi[frs1 + BEH];
sregs->fsi[frd + 1 - BEH] =
- (sregs->
- fsi[frs1 + 1 -
- BEH] & 0x7fffffff) | (sregs->fsi[frs2 + 1 -
- BEH] &
- 0x80000000);
+ (sregs->fsi[frs1 + 1 -
+ BEH] & 0x7fffffff) | (sregs->fsi[frs2 +
+ 1 -
+ BEH] &
+ 0x80000000);
break;
case 1: /* FSGNJN */
sregs->fsi[frd + BEH] = sregs->fsi[frs1 + BEH];
sregs->fsi[frd + 1 - BEH] =
- (sregs->
- fsi[frs1 + 1 -
- BEH] & 0x7fffffff) | (~sregs->fsi[frs2 + 1 -
- BEH] &
- 0x80000000);
+ (sregs->fsi[frs1 + 1 -
+ BEH] & 0x7fffffff) | (~sregs->fsi[frs2 +
+ 1 -
+ BEH] &
+ 0x80000000);
break;
case 2: /* FSGNJX */
sregs->fsi[frd + BEH] = sregs->fsi[frs1 + BEH];
@@ -2055,14 +2080,19 @@ riscv_execute_trap (sregs)
}
if (((sregs->trap >= 16) && (sregs->trap < 32))
-// || ((sregs->trap == 7) || (sregs->trap == 11))
- )
+ || ((sregs->trap == 0x23) || (sregs->trap == 0x27)))
{
sregs->mcause &= 0x1f; // filter trap cause
sregs->mcause |= 0x80000000; // indicate async interrupt
if ((sregs->trap > 16) && (sregs->trap < 32))
sregs->intack (sregs->trap - 16, sregs->cpu);
+ else
+ ext_irl[sregs->cpu] = 0;
}
+ if (sregs->trap == 0x23)
+ sregs->mip &= ~MIP_MSIP;
+ if (sregs->trap == 0x27)
+ sregs->mip &= ~MIP_MTIP;
// save mstatus.mie in mstatus.mpie
sregs->mstatus |= (sregs->mstatus << 4) & MSTATUS_MPIE;
@@ -2091,8 +2121,8 @@ static int
riscv_check_interrupts (sregs)
struct pstate *sregs;
{
- if ((ext_irl[sregs->cpu]) && (sregs->mstatus & MSTATUS_MIE) &&
- (sregs->mie & MIE_MEIE))
+ if ((ext_irl[sregs->cpu]) &&
+ ((sregs->mstatus & MSTATUS_MIE) && (sregs->mie & MIE_MEIE)))
{
if (sregs->pwd_mode)
{
diff --git a/riscv.h b/riscv.h
index 04e99a7..b5c880b 100644
--- a/riscv.h
+++ b/riscv.h
@@ -155,7 +155,8 @@
#define MSTATUS_MPIE 0x80
#define MSTATUS_MPP 0x1800
-#define MIP_MTI 0x080
+#define MIP_MSIP 0x008
+#define MIP_MTIP 0x080
#define MIP_MEIP 0x800
#define MIE_MTIE 0x080
#define MIE_MEIE 0x800
diff --git a/rv32.c b/rv32.c
new file mode 100644
index 0000000..305fd1e
--- /dev/null
+++ b/rv32.c
@@ -0,0 +1,273 @@
+/*
+ * This file is part of SIS.
+ *
+ * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
+ * European Space Agency
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Leon3 emulation, loosely based on erc32.c.
+ */
+
+#define ROM_START 0x20000000
+#define ROM_SIZE 0x01000000
+#define RAM_START 0x80000000
+#define RAM_SIZE 0x04000000
+
+#include <errno.h>
+#include <sys/types.h>
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#ifdef HAVE_TERMIOS_H
+#include <termios.h>
+#endif
+#include <sys/file.h>
+#include <unistd.h>
+#include "riscv.h"
+#include "grlib.h"
+#include "rv32dtb.h"
+
+#define PLIC_START 0x0C000000
+#define PLIC_MASK 0xFFC
+#define NS16550_START 0x10000000
+#define TESTSTART 0x00100000
+
+#define CLINT_START 0x02000000
+
+/* APB registers */
+#define APBSTART 0xC0000000
+
+/* Memory exception waitstates. */
+#define MEM_EX_WS 1
+
+
+/* Forward declarations. */
+static char *get_mem_ptr (uint32 addr, uint32 size);
+
+/* One-time init. */
+
+static void
+init_sim (void)
+{
+ int i;
+
+ for (i = 0; i < ncpu; i++)
+ grlib_ahbm_add (&leon3s, 0);
+
+ grlib_ahbs_add (&s5test, 0, TESTSTART, 0xFFF);
+ grlib_ahbs_add (&clint, 0, CLINT_START, 0xFFF);
+ grlib_ahbs_add (&plic, 0, PLIC_START, PLIC_MASK);
+ grlib_ahbs_add (&ns16550, 0, NS16550_START, 0xFFF);
+ grlib_ahbs_add (&srctrl, 0, ROM_START, ROM_MASKPP);
+ grlib_ahbs_add (&sdctrl, 0, RAM_START, RAM_MASKPP);
+
+ grlib_init ();
+ memcpy (&romb[(ROM_END - 0x10000) & ROM_MASK], rv32_dtb, sizeof (rv32_dtb));
+ ebase.ramstart = RAM_START;
+}
+
+/* Power-on reset init. */
+
+static void
+reset (void)
+{
+ grlib_reset ();
+}
+
+/* IU error mode manager. */
+
+static void
+error_mode (uint32 pc)
+{
+
+}
+
+/* Flush ports when simulator stops. */
+
+static void
+sim_halt (void)
+{
+#ifdef FAST_UART
+ apbuart_flush ();
+#endif
+}
+
+static void
+exit_sim (void)
+{
+ apbuart_close_port ();
+}
+
+/* Memory emulation. */
+
+static int
+memory_read (uint32 addr, uint32 * data, int32 * ws)
+{
+ uint64 tmp;
+ int32 mexc;
+ int reg, cpuid;
+
+ *ws = 0;
+ /* bypass system bus decoding to speed-up RAM/ROM access */
+ if ((addr >= RAM_START) && (addr < RAM_END))
+ {
+ memcpy (data, &ramb[addr & RAM_MASK], 4);
+ return 0;
+ }
+ if ((addr >= ROM_START) && (addr < ROM_END))
+ {
+ memcpy (data, &romb[addr & ROM_MASK], 4);
+ return 0;
+ }
+
+ /* regular system bus access */
+ mexc = grlib_read (addr, data);
+ *ws = 4;
+
+ if (sis_verbose > 1)
+ printf ("BUS read a: %08x, d: %08x\n", addr, *data);
+
+ if (sis_verbose && mexc)
+ {
+ printf ("Memory exception at %x (illegal address)\n", addr);
+ *ws = MEM_EX_WS;
+ }
+ return mexc;
+}
+
+static int
+memory_write (uint32 addr, uint32 * data, int32 sz, int32 * ws)
+{
+ uint32 waddr;
+ int32 mexc;
+ uint64 tmp;
+ int reg, cpuid;
+
+ mexc = 0;
+ *ws = 0;
+ if ((addr >= RAM_START) && (addr < RAM_END))
+ {
+ waddr = addr & RAM_MASK;
+ grlib_store_bytes (ramb, waddr, data, sz);
+ return 0;
+ }
+ else if ((addr >= ROM_START) && (addr < ROM_END))
+ {
+ grlib_store_bytes (romb, addr, data, sz);
+ return 0;
+ }
+ else
+ {
+ mexc = grlib_write (addr, data, sz);
+ *ws = 4;
+ }
+
+ if (sis_verbose > 0)
+ printf ("AHB write a: %08x, d: %08x\n", addr, *data);
+ if (sis_verbose && mexc)
+ {
+ printf ("Memory exception at %x (illegal address)\n", addr);
+ *ws = MEM_EX_WS;
+ }
+ return mexc;
+}
+
+static char *
+get_mem_ptr (uint32 addr, uint32 size)
+{
+ if ((addr >= RAM_START) && ((addr + size) < RAM_END))
+ {
+ return &ramb[addr & RAM_MASK];
+ }
+ else if ((addr >= ROM_START) && ((addr + size) < ROM_END))
+ {
+ return &romb[addr & ROM_MASK];
+ }
+
+ return NULL;
+}
+
+static int
+sis_memory_write (uint32 addr, const char *data, uint32 length)
+{
+ char *mem;
+ int32 ws;
+
+ if ((mem = get_mem_ptr (addr, length)) != NULL)
+ {
+ memcpy (mem, data, length);
+ return length;
+ }
+ else if (length == 4)
+ memory_write (addr, (uint32 *) data, 2, &ws);
+ return 0;
+}
+
+static int
+sis_memory_read (uint32 addr, char *data, uint32 length)
+{
+ char *mem;
+ int ws;
+
+ if (length == 4)
+ {
+ memory_read (addr, (uint32 *) data, &ws);
+ return 4;
+ }
+
+ if ((mem = get_mem_ptr (addr, length)) == NULL)
+ return 0;
+
+ memcpy (data, mem, length);
+ return length;
+}
+
+static void
+boot_init (void)
+{
+
+ int i;
+
+ grlib_boot_init ();
+ for (i = 0; i < ncpu; i++)
+ {
+ sregs[i].wim = 2;
+ sregs[i].psr = 0xF30010e0;
+ sregs[i].r[30] = RAM_END - (i * 0x20000);
+ sregs[i].r[14] = sregs[i].r[30] - 96 * 4;
+ sregs[i].cache_ctrl = 0x81000f;
+ sregs[i].r[2] = sregs[i].r[30]; /* sp on RISCV-V */
+ sregs[i].r[11] = ROM_END - 0x10000; /* dtb on RISCV-V */
+ sregs[i].pwd_mode = 0;
+ }
+}
+
+const struct memsys rv32 = {
+ init_sim,
+ reset,
+ error_mode,
+ sim_halt,
+ exit_sim,
+ apbuart_init_stdio,
+ apbuart_restore_stdio,
+ memory_read,
+ memory_read,
+ memory_write,
+ sis_memory_write,
+ sis_memory_read,
+ boot_init,
+ get_mem_ptr,
+ grlib_set_irq
+};
diff --git a/rv32.dts b/rv32.dts
new file mode 100644
index 0000000..9911d9d
--- /dev/null
+++ b/rv32.dts
@@ -0,0 +1,251 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ compatible = "riscv-virtio";
+ model = "riscv-virtio,qemu";
+
+ chosen {
+ bootargs = [00];
+ stdout-path = "/soc/uart@10000000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ timebase-frequency = <0x2FAF080>;
+
+ cpu@0 {
+ phandle = <0x7>;
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv32imafdcsu";
+ mmu-type = "riscv,sv32";
+
+ interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x8>;
+ };
+ };
+
+ cpu@1 {
+ phandle = <0x5>;
+ device_type = "cpu";
+ reg = <0x1>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv32imafdcsu";
+ mmu-type = "riscv,sv32";
+
+ interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x6>;
+ };
+ };
+
+ cpu@2 {
+ phandle = <0x3>;
+ device_type = "cpu";
+ reg = <0x2>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv32imafdcsu";
+ mmu-type = "riscv,sv32";
+
+ interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x4>;
+ };
+ };
+
+ cpu@3 {
+ phandle = <0x1>;
+ device_type = "cpu";
+ reg = <0x3>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv32imafdcsu";
+ mmu-type = "riscv,sv32";
+
+ interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x2>;
+ };
+ };
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x7>;
+ };
+
+ core1 {
+ cpu = <0x5>;
+ };
+
+ core2 {
+ cpu = <0x3>;
+ };
+
+ core3 {
+ cpu = <0x1>;
+ };
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ compatible = "simple-bus";
+ ranges;
+
+ flash@20000000 {
+ bank-width = <0x4>;
+ reg = <0x0 0x20000000 0x0 0x2000000 0x0 0x22000000 0x0 0x2000000>;
+ compatible = "cfi-flash";
+ };
+
+ rtc@101000 {
+ interrupts = <0xb>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x101000 0x0 0x1000>;
+ compatible = "google,goldfish-rtc";
+ };
+
+ uart@10000000 {
+ interrupts = <0xa>;
+ interrupt-parent = <0x9>;
+ clock-frequency = <0x384000>;
+ reg-shift = <0x2>;
+ reg = <0x0 0x10000000 0x0 0x100>;
+ compatible = "ns16550a";
+ };
+
+ poweroff {
+ value = <0x5555>;
+ offset = <0x0>;
+ regmap = <0xa>;
+ compatible = "syscon-poweroff";
+ };
+
+ reboot {
+ value = <0x7777>;
+ offset = <0x0>;
+ regmap = <0xa>;
+ compatible = "syscon-reboot";
+ };
+
+ test@100000 {
+ phandle = <0xa>;
+ reg = <0x0 0x100000 0x0 0x1000>;
+ compatible = "sifive,test1", "sifive,test0", "syscon";
+ };
+
+ pci@30000000 {
+ interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 0x9 0x20 0x0 0x0 0x0 0x2 0x9 0x21 0x0 0x0 0x0 0x3 0x9 0x22 0x0 0x0 0x0 0x4 0x9 0x23 0x800 0x0 0x0 0x1 0x9 0x21 0x800 0x0 0x0 0x2 0x9 0x22 0x800 0x0 0x0 0x3 0x9 0x23 0x800 0x0 0x0 0x4 0x9 0x20 0x1000 0x0 0x0 0x1 0x9 0x22 0x1000 0x0 0x0 0x2 0x9 0x23 0x1000 0x0 0x0 0x3 0x9 0x20 0x1000 0x0 0x0 0x4 0x9 0x21 0x1800 0x0 0x0 0x1 0x9 0x23 0x1800 0x0 0x0 0x2 0x9 0x20 0x1800 0x0 0x0 0x3 0x9 0x21 0x1800 0x0 0x0 0x4 0x9 0x22>;
+ ranges = <0x1000000 0x0 0x0 0x0 0x3000000 0x0 0x10000 0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+ reg = <0x0 0x30000000 0x0 0x10000000>;
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ linux,pci-domain = <0x0>;
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ #address-cells = <0x3>;
+ };
+
+ virtio_mmio@10008000 {
+ interrupts = <0x8>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10008000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x7>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10007000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10006000 {
+ interrupts = <0x6>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10006000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10005000 {
+ interrupts = <0x5>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10005000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10004000 {
+ interrupts = <0x4>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10004000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10003000 {
+ interrupts = <0x3>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10003000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10002000 {
+ interrupts = <0x2>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10002000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10001000 {
+ interrupts = <0x1>;
+ interrupt-parent = <0x9>;
+ reg = <0x0 0x10001000 0x0 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ plic@c000000 {
+ phandle = <0x9>;
+ riscv,ndev = <0x35>;
+ reg = <0x0 0xc000000 0x0 0x210000>;
+ interrupts-extended = <0x8 0xb 0x8 0x9 0x6 0xb 0x6 0x9 0x4 0xb 0x4 0x9 0x2 0xb 0x2 0x9>;
+ interrupt-controller;
+ compatible = "riscv,plic0";
+ #interrupt-cells = <0x1>;
+ #address-cells = <0x0>;
+ };
+
+ clint@2000000 {
+ interrupts-extended = <0x8 0x3 0x8 0x7 0x6 0x3 0x6 0x7 0x4 0x3 0x4 0x7 0x2 0x3 0x2 0x7>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ compatible = "riscv,clint0";
+ };
+ };
+};
diff --git a/rv32dtb.h b/rv32dtb.h
new file mode 100644
index 0000000..653c9a2
--- /dev/null
+++ b/rv32dtb.h
@@ -0,0 +1,394 @@
+unsigned char rv32_dtb[] = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x12, 0x4c, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x10, 0xd8, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x74,
+ 0x00, 0x00, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x1b,
+ 0x72, 0x69, 0x73, 0x63, 0x76, 0x2d, 0x76, 0x69, 0x72, 0x74, 0x69, 0x6f,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12,
+ 0x00, 0x00, 0x00, 0x26, 0x72, 0x69, 0x73, 0x63, 0x76, 0x2d, 0x76, 0x69,
+ 0x72, 0x74, 0x69, 0x6f, 0x2c, 0x71, 0x65, 0x6d, 0x75, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x01, 0x63, 0x68, 0x6f, 0x73, 0x65, 0x6e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x2c,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13,
+ 0x00, 0x00, 0x00, 0x35, 0x2f, 0x73, 0x6f, 0x63, 0x2f, 0x75, 0x61, 0x72,
+ 0x74, 0x40, 0x31, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x6d, 0x65, 0x6d, 0x6f,
+ 0x72, 0x79, 0x40, 0x38, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x41,
+ 0x6d, 0x65, 0x6d, 0x6f, 0x72, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x73,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x51,
+ 0x02, 0xfa, 0xf0, 0x80, 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x41, 0x63, 0x70, 0x75, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
+ 0x00, 0x00, 0x00, 0x6c, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1b,
+ 0x72, 0x69, 0x73, 0x63, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x73, 0x72, 0x76, 0x33, 0x32,
+ 0x69, 0x6d, 0x61, 0x66, 0x64, 0x63, 0x73, 0x75, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x7d,
+ 0x72, 0x69, 0x73, 0x63, 0x76, 0x2c, 0x73, 0x76, 0x33, 0x32, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x01, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70,
+ 0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x86, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x1b, 0x72, 0x69, 0x73, 0x63,
+ 0x76, 0x2c, 0x63, 0x70, 0x75, 0x2d, 0x69, 0x6e, 0x74, 0x63, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x64,
+ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x01, 0x63, 0x70, 0x75, 0x40, 0x31, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x64,
+ 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x41, 0x63, 0x70, 0x75, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x6c,
+ 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1b, 0x72, 0x69, 0x73, 0x63,
+ 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0d,
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+ 0x64, 0x63, 0x73, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x7d, 0x72, 0x69, 0x73, 0x63,
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+ 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x6d, 0x61, 0x70, 0x2d, 0x6d, 0x61,
+ 0x73, 0x6b, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74,
+ 0x2d, 0x6d, 0x61, 0x70, 0x00, 0x64, 0x6d, 0x61, 0x2d, 0x63, 0x6f, 0x68,
+ 0x65, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x62, 0x75, 0x73, 0x2d, 0x72, 0x61,
+ 0x6e, 0x67, 0x65, 0x00, 0x6c, 0x69, 0x6e, 0x75, 0x78, 0x2c, 0x70, 0x63,
+ 0x69, 0x2d, 0x64, 0x6f, 0x6d, 0x61, 0x69, 0x6e, 0x00, 0x72, 0x69, 0x73,
+ 0x63, 0x76, 0x2c, 0x6e, 0x64, 0x65, 0x76, 0x00, 0x69, 0x6e, 0x74, 0x65,
+ 0x72, 0x72, 0x75, 0x70, 0x74, 0x73, 0x2d, 0x65, 0x78, 0x74, 0x65, 0x6e,
+ 0x64, 0x65, 0x64, 0x00
+};
+unsigned int rv32_dtb_len = 4684;
diff --git a/sis.c b/sis.c
index 837f516..580eb64 100644
--- a/sis.c
+++ b/sis.c
@@ -60,7 +60,6 @@ main (argc, argv)
int run = 0;
char prompt[8];
int gdb = 0;
- int lcputype = 0;
printf
("\n SIS - SPARC/RISCV instruction simulator %s, copyright Jiri Gaisler 2020\n",
@@ -75,9 +74,9 @@ main (argc, argv)
strncpy (uart_dev1, argv[0], 128);
cfile = basename (uart_dev1);
if (strncmp (cfile, "riscv", 5) == 0)
- {
- lcputype = CPU_RISCV;
- }
+ archtype = CPU_RISCV;
+ if (strncmp (cfile, "sparc", 5) == 0)
+ archtype = CPU_SPARC;
cfile = 0;
uart_dev1[0] = 0;
@@ -158,24 +157,37 @@ main (argc, argv)
}
else if (strcmp (argv[stat], "-erc32") == 0)
{
- lcputype = CPU_ERC32;
+ cputype = CPU_ERC32;
+ archtype = CPU_SPARC;
}
else if (strcmp (argv[stat], "-leon2") == 0)
{
- lcputype = CPU_LEON2;
+ cputype = CPU_LEON2;
+ archtype = CPU_SPARC;
}
else if (strcmp (argv[stat], "-leon3") == 0)
{
- lcputype = CPU_LEON3;
+ cputype = CPU_LEON3;
+ archtype = CPU_SPARC;
}
else if (strcmp (argv[stat], "-gr740") == 0)
{
- lcputype = CPU_LEON3;
- ms = &gr740;
+ cputype = CPU_LEON4;
+ archtype = CPU_SPARC;
}
else if (strcmp (argv[stat], "-riscv") == 0)
{
- lcputype = CPU_RISCV;
+ archtype = CPU_RISCV;
+ }
+ else if (strcmp (argv[stat], "-griscv") == 0)
+ {
+ cputype = CPU_LEON3;
+ archtype = CPU_RISCV;
+ }
+ else if (strcmp (argv[stat], "-rv32") == 0)
+ {
+ cputype = CPU_RISCV;
+ archtype = CPU_RISCV;
}
else if (strcmp (argv[stat], "-tlim") == 0)
{
@@ -218,15 +230,44 @@ main (argc, argv)
if (lfile)
{
last_load_addr = elf_load (argv[lfile], 0);
- if (ebase.cpu)
- cputype = ebase.cpu;
}
- if (lcputype)
- cputype = lcputype;
+ if (!archtype)
+ {
+ if (!ebase.arch)
+ {
+ archtype = CPU_SPARC;
+ cputype = CPU_ERC32;
+ }
+ else
+ {
+ archtype = ebase.arch;
+ cputype = ebase.cpu;
+ }
+ if (!cputype)
+ cputype = CPU_LEON3;
+ }
+ else if (!cputype)
+ {
+ cputype = ebase.cpu;
+ if (!cputype)
+ {
+ if (archtype == CPU_SPARC)
+ cputype = CPU_ERC32;
+ else
+ cputype = CPU_LEON3;
+ }
+ }
switch (cputype)
{
+ case CPU_ERC32:
+ printf (" ERC32 emulation enabled\n");
+ cputype = CPU_ERC32;
+ ms = &erc32sys;
+ if (!freq)
+ freq = 14;
+ break;
case CPU_LEON2:
printf (" LEON2 emulation enabled\n");
ms = &leon2;
@@ -234,17 +275,34 @@ main (argc, argv)
freq = 50;
break;
case CPU_LEON3:
- printf (" LEON3 emulation enabled, %d cpus online, delta %d clocks\n",
- ncpu, delta);
- if (!ms)
- ms = &leon3;
+ if (archtype == CPU_SPARC)
+ printf (" LEON3 emulation enabled, %d cpus online, delta %d clocks\n",
+ ncpu, delta);
+ else
+ {
+ printf
+ (" RISCV/GRLIB emulation enabled, %d cpus online, delta %d clocks\n",
+ ncpu, delta);
+ arch = &riscv;
+ }
+ ms = &leon3;
+ if (!freq)
+ freq = 50;
+ break;
+ case CPU_LEON4:
+ printf
+ (" GR740/LEON4 emulation enabled, %d cpus online, delta %d clocks\n",
+ ncpu, delta);
+ ms = &gr740;
if (!freq)
freq = 50;
break;
case CPU_RISCV:
- printf (" RISCV emulation enabled, %d cpus online, delta %d clocks\n",
- ncpu, delta);
- ms = &leon3;
+// if (delta == 50) delta = 25; // 25 clock delta works better with the CLINT
+ printf
+ (" RISCV/CLINT emulation enabled, %d cpus online, delta %d clocks\n",
+ ncpu, delta);
+ ms = &rv32;
arch = &riscv;
if (!freq)
freq = 50;
diff --git a/sis.h b/sis.h
index ea99f6d..a357fb2 100644
--- a/sis.h
+++ b/sis.h
@@ -225,7 +225,8 @@ struct estate
uint32 ramstart; /* start of RAM */
uint32 bpcpu; /* cpu that hit breakpoint */
uint32 bend; /* cpu big endian */
- uint32 cpu; /* cpu typefrom elf file */
+ uint32 cpu; /* cpu type from elf file */
+ uint32 arch; /* cpu arch from elf file */
};
extern const struct cpu_arch *arch;
@@ -251,7 +252,9 @@ extern const struct cpu_arch riscv;
#define CPU_ERC32 1
#define CPU_LEON2 2
#define CPU_LEON3 3
+#define CPU_LEON4 4
#define CPU_RISCV 5
+#define CPU_SPARC 6
/* Prototypes */
@@ -306,6 +309,7 @@ extern int nouartrx;
extern int dumbio;
extern int tty_setup;
extern int cputype;
+extern int archtype;
extern int sis_gdb_break;
extern int cpu; /* active debug cpu */
extern int ncpu; /* number of online cpus */
@@ -376,6 +380,9 @@ extern const struct memsys leon3;
/* gr740.c */
extern const struct memsys gr740;
+/* rv32.c */
+extern const struct memsys rv32;
+
/* remote.c */
extern void gdb_remote (int port);
@@ -397,6 +404,10 @@ extern int sim_clear_watchpoint (uint32 mem, int length, int type);
/* sparc.c */
extern int gdb_sp_read (uint32 mem, char *buf, int length);
+/* riscv.c */
+
+extern int rv32_check_lirq (int cpu);
+
/* greth.c */
extern uint32 greth_read (uint32 address);
extern void greth_write (uint32 address, uint32 data);
diff --git a/sis.info b/sis.info
index 87125da..cc0750e 100644
--- a/sis.info
+++ b/sis.info
@@ -1,6 +1,6 @@
This is sis.info, produced by makeinfo version 6.5 from sis.texi.
-This manual is for SIS (version 2.25, 1 December 2020).
+This manual is for SIS (version 2.26, 15 December 2020).
Copyright (C) 2020 Free Software Foundation, Inc.
@@ -21,7 +21,7 @@ File: sis.info, Node: Top, Next: Introduction, Up: (dir)
SIS
***
-This manual is for SIS (version 2.25, 1 December 2020).
+This manual is for SIS (version 2.26, 15 December 2020).
* Menu:
@@ -48,7 +48,7 @@ consist of three main parts: an event-based simulator core, a cpu
(SPARC/RISCV) emulation module and system-specific memory and peripheral
modules.
- SIS can emulate four specific systems:
+ SIS can emulate six specific systems:
'ERC32'
ERC32 SPARC V7 processor
@@ -59,10 +59,16 @@ modules.
'LEON3'
LEON3 SPARC V8 processor
-'RISC-V'
- RISC-V (RV32IMACFD) processor
+'GR740'
+ LEON4 SPARC V8 processor
+
+'GRISCV'
+ RISC-V (RV32IMACFD) processor with GRLIB peripherals
- The LEON3 and RISC-V emulation also supports SMP with up to four
+'RV32'
+ RISC-V (RV32IMACFD) processor with CLINT and ns16550 UART
+
+ The LEON3/4 and RISC-V emulation supports SMP with up to four
processor cores.

@@ -103,6 +109,12 @@ The simulator is started as follows:
Start a gdb server, listening on port 1234. An alternative port
can be specified with -PORT NN.
+'-gr740'
+ Emulate a (limited) GR740 SOC device
+
+'-griscv'
+ Emulate a GRISCV (RISCV/GRLIB) SOC device
+
'-leon2'
Emulate the SPARC V8 LEON2 processor
@@ -129,8 +141,8 @@ The simulator is started as follows:
the simulator time to the wall (host) time. Useful for interactive
programs. Enabled by default when networking is used.
-'-riscv'
- Emulate a RISC-V RV32IMACFD processor
+'-rv32'
+ Emulate a RISC-V RV32IMACFD processor with CLINT module.
'-tlim DELAY'
Used together with -R to limit the amount of simulated time that
@@ -606,7 +618,7 @@ The following memory areas are valid for LEON3:
Address Type
------------------------------------------------------------------
0x00000000 - 0x01000000 ROM (16 Mbyte)
-0x40000000 - 0x41000000 RAM (16 Mbyte)
+0x40000000 - 0x41000000 RAM (64 Mbyte)
0x80000000 - 0x81000000 APB bus
0xFFFFF000 - 0xFFFFFFFF AHB plug&play
@@ -651,7 +663,7 @@ The following memory areas are valid for GR740:
Address Type
------------------------------------------------------------------
0x00000000 - 0x04000000 RAM (64 Mbyte)
-0xC0000000 - 0xC1000000 RAM (16 Mbyte)
+0xC0000000 - 0xC1000000 ROM (16 Mbyte)
0xFF900000 - 0xFFA00000 APB bus
0xFFFFF000 - 0xFFFFFFFF AHB plug&play
@@ -661,10 +673,23 @@ Address Type
====================
In RISC-V mode, SIS emulates a RV32IMACFD processor as defined in the
-RISC-V specification 1.9. The RISC-V procssor is attached to an
-identical GRLIB sub-system as when LEON3 is emulated.
+RISC-V specification 1.9. Two different SOCs can be emulated, GRISCV
+and a CLINT base system.
+
+ The GRISCV SOC uses the same peripherals and memory maps as a SPARC
+LEON3 processor. A CLINT based system uses a CLINT core for timers and
+UARTs with the following address map:
+
+Address Type
+------------------------------------------------------------------
+0x02000000 - 0x02100000 CLINT
+0x0C000000 - 0x0C200000 PLIC
+0x10000000 - 0x10000100 NS16550 UART
+0x20000000 - 0x21000000 ROM (16 Mbyte)
+0x80000000 - 0x84000000 RAM (64 Mbyte)
- To start sis in RISC-V mode, use the -riscv switch.
+ The DTB (device-tree table) is located at the end of ROM
+(0x20FF0000).
4.5.1 Power-down mode
---------------------
@@ -683,8 +708,7 @@ the C-extension can not be used when code coverage is measured.
-------------------------
The standard RISC-V 64-bit timer is provided and can be read through the
-time and timeh CSR. The timer does not generare any interrupt and the
-timecmp register is not implemented.
+time and timeh CSR.

File: sis.info, Node: Multi-processing, Next: Networking, Prev: Emulated Systems, Up: Top
@@ -1395,17 +1419,17 @@ Index

Tag Table:
-Node: Top700
-Node: Introduction1053
-Node: Invoking sis1677
-Node: Commands4109
-Node: Emulated Systems8213
-Node: Multi-processing22329
-Node: Networking22817
-Node: Interfacing to GDB29127
-Node: Code coverage29531
-Node: Building SIS30536
-Node: GNU Free Documentation License31186
-Node: Index56330
+Node: Top701
+Node: Introduction1055
+Node: Invoking sis1808
+Node: Commands4368
+Node: Emulated Systems8472
+Node: Multi-processing23069
+Node: Networking23557
+Node: Interfacing to GDB29867
+Node: Code coverage30271
+Node: Building SIS31276
+Node: GNU Free Documentation License31926
+Node: Index57070

End Tag Table
diff --git a/sis.texi b/sis.texi
index 019bfaf..4e352c3 100644
--- a/sis.texi
+++ b/sis.texi
@@ -67,7 +67,7 @@ It consist of three main parts: an event-based simulator core,
a cpu (SPARC/RISCV) emulation module and system-specific memory and
peripheral modules.
-SIS can emulate four specific systems:
+SIS can emulate six specific systems:
@table @code
@@ -80,12 +80,18 @@ LEON2 SPARC V8 processor
@item LEON3
LEON3 SPARC V8 processor
-@item RISC-V
-RISC-V (RV32IMACFD) processor
+@item GR740
+LEON4 SPARC V8 processor
+
+@item GRISCV
+RISC-V (RV32IMACFD) processor with GRLIB peripherals
+
+@item RV32
+RISC-V (RV32IMACFD) processor with CLINT and ns16550 UART
@end table
-The LEON3 and RISC-V emulation also supports SMP with up to four processor cores.
+The LEON3/4 and RISC-V emulation supports SMP with up to four processor cores.
@node Invoking sis
@chapter Invoking sis
@@ -129,6 +135,9 @@ be specified with @var{-port nn}.
@item -gr740
Emulate a (limited) GR740 SOC device
+@item -griscv
+Emulate a GRISCV (RISCV/GRLIB) SOC device
+
@item -leon2
Emulate the SPARC V8 LEON2 processor
@@ -152,8 +161,8 @@ for automated testing.
@item -rt
Real-time mode. When enabled, the simulator tries to synchronize the simulator time to the wall (host) time. Useful for interactive programs. Enabled by default when networking is used.
-@item -riscv
-Emulate a RISC-V RV32IMACFD processor
+@item -rv32
+Emulate a RISC-V RV32IMACFD processor with CLINT module.
@item -tlim @var{delay}
Used together with @var{-r} to limit the amount of simulated time that
@@ -611,7 +620,7 @@ The following memory areas are valid for LEON3:
@multitable {Very long text so that we avoid wrapping } {A long long Address}
@headitem Address @tab Type
@item 0x00000000 - 0x01000000 @tab ROM (16 Mbyte)
-@item 0x40000000 - 0x41000000 @tab RAM (16 Mbyte)
+@item 0x40000000 - 0x41000000 @tab RAM (64 Mbyte)
@item 0x80000000 - 0x81000000 @tab APB bus
@item 0xFFFFF000 - 0xFFFFFFFF @tab AHB plug&play
@end multitable
@@ -654,7 +663,7 @@ The following memory areas are valid for GR740:
@multitable {Very long text so that we avoid wrapping } {A long long Address}
@headitem Address @tab Type
@item 0x00000000 - 0x04000000 @tab RAM (64 Mbyte)
-@item 0xC0000000 - 0xC1000000 @tab RAM (16 Mbyte)
+@item 0xC0000000 - 0xC1000000 @tab ROM (16 Mbyte)
@item 0xFF900000 - 0xFFA00000 @tab APB bus
@item 0xFFFFF000 - 0xFFFFFFFF @tab AHB plug&play
@end multitable
@@ -664,10 +673,23 @@ Access to non-existing memory will result in a memory exception trap.
@section RISC-V emulation
In RISC-V mode, SIS emulates a RV32IMACFD processor as defined in the
-RISC-V specification 1.9. The RISC-V procssor is attached to an identical GRLIB
-sub-system as when LEON3 is emulated.
+RISC-V specification 1.9. Two different SOCs can be emulated, GRISCV and
+a CLINT base system.
+
+The GRISCV SOC uses the same peripherals and memory maps as a SPARC
+LEON3 processor. A CLINT based system uses a CLINT core for timers
+and UARTs with the following address map:
+
+@multitable {Very long text so that we avoid wrapping } {A long long Address}
+@headitem Address @tab Type
+@item 0x02000000 - 0x02100000 @tab CLINT
+@item 0x0C000000 - 0x0C200000 @tab PLIC
+@item 0x10000000 - 0x10000100 @tab NS16550 UART
+@item 0x20000000 - 0x21000000 @tab ROM (16 Mbyte)
+@item 0x80000000 - 0x84000000 @tab RAM (64 Mbyte)
+@end multitable
-To start sis in RISC-V mode, use the -riscv switch.
+The DTB (device-tree table) is located at the end of ROM (0x20FF0000).
@subsection Power-down mode
@@ -683,8 +705,7 @@ the C-extension can not be used when code coverage is measured.
@subsection RISC-V 64-bit timer
The standard RISC-V 64-bit timer is provided and can be read through the
-time and timeh CSR. The timer does not generare any interrupt and the
-timecmp register is not implemented.
+time and timeh CSR.
@node Multi-processing
@chapter Multi-processing
diff --git a/sparc.c b/sparc.c
index 9f046ab..3a242fa 100644
--- a/sparc.c
+++ b/sparc.c
@@ -845,7 +845,7 @@ sparc_dispatch_instruction (sregs)
*rdd = sregs->psr;
break;
case RDY:
- if (cputype == CPU_LEON3)
+ if (cputype != CPU_ERC32)
{
rs1 = (sregs->inst >> 14) & 0x1f;
switch (rs1)
@@ -916,7 +916,7 @@ sparc_dispatch_instruction (sregs)
break;
case WRY:
sregs->y = (rs1 ^ operand2);
- if (cputype == CPU_LEON3)
+ if (cputype != CPU_ERC32)
{
if (17 == rd)
{
@@ -1089,7 +1089,7 @@ sparc_dispatch_instruction (sregs)
sregs->trap = TRAP_UNALI;
break;
}
- if ((cputype == CPU_LEON3) && (asi == 2))
+ if ((cputype != CPU_ERC32) && (asi == 2))
{
if (address == 0)
*rdd = sregs->cache_ctrl;
@@ -1321,7 +1321,7 @@ sparc_dispatch_instruction (sregs)
sregs->trap = TRAP_UNALI;
break;
}
- if ((cputype == CPU_LEON3) && (asi == 2))
+ if ((cputype != CPU_ERC32) && (asi == 2))
{
sregs->cache_ctrl = *rdd;
break;
@@ -1802,7 +1802,7 @@ fpexec (op3, rd, rs1, rs2, sregs)
sregs->ftime += T_FMULs;
break;
case FsMULd:
- if (cputype == CPU_LEON3)
+ if (cputype != CPU_ERC32)
{ /* FSMULD only supported for LEON3 */
sregs->fd[rd >> 1] =
(double) sregs->fs[rs1] * (double) sregs->fs[rs2];
diff --git a/version.texi b/version.texi
index 9300ecc..0aad4bb 100644
--- a/version.texi
+++ b/version.texi
@@ -1,4 +1,4 @@
-@set UPDATED 1 December 2020
+@set UPDATED 15 December 2020
@set UPDATED-MONTH December 2020
-@set EDITION 2.25
-@set VERSION 2.25
+@set EDITION 2.26
+@set VERSION 2.26
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 13:55:14 +0000