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authorTian Ye <tianye@sugon.com>2023-10-18 09:21:56 -0500
committerJoel Sherrill <joel@rtems.org>2023-10-18 10:14:42 -0500
commita738d69bcf97d5a6fd88c1665380cfb381f05b1f (patch)
tree33f700e60110b4ce54d254e27ecf0a855220dbdb
parente7cb79c39d8dbc02ded1d6d9c37ee00323508bf3 (diff)
bsps/aarch64: Disable use of TTBR1
Force use of addresses that would be translated by TTBR1 to cause a translation fault. RTEMS on AArch64 does not use TTBR1 and so attempted translation of that address range could cause unexpected behavior in the form of other exception types since TTBR1 is never set.
-rw-r--r--bsps/aarch64/include/bsp/aarch64-mmu.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h b/bsps/aarch64/include/bsp/aarch64-mmu.h
index 2101ef4ae0..8c69705230 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -439,7 +439,8 @@ BSP_START_TEXT_SECTION static inline void aarch64_mmu_setup( void )
_AArch64_Write_tcr_el1(
AARCH64_TCR_EL1_T0SZ( 0x10 ) | AARCH64_TCR_EL1_IRGN0( 0x1 ) |
AARCH64_TCR_EL1_ORGN0( 0x1 ) | AARCH64_TCR_EL1_SH0( 0x3 ) |
- AARCH64_TCR_EL1_TG0( 0x0 ) | AARCH64_TCR_EL1_IPS( 0x5ULL )
+ AARCH64_TCR_EL1_TG0( 0x0 ) | AARCH64_TCR_EL1_IPS( 0x5ULL ) |
+ AARCH64_TCR_EL1_EPD1
);
/* Set MAIR */