| Commit message (Collapse) | Author | Age | Files | Lines |
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Move useful functions to the top of the file.
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The SPARC processors supported by RTEMS have no built-in CPU counter
support. We have to use some hardware counter module for this purpose.
The BSP must provide a 32-bit register which contains the current CPU
counter value and a function for the difference calculation. It can use
for example the GPTIMER instance used for the clock driver.
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Do not use _TLS_Size here since this will lead GCC to assume that this
symbol is not 0 and the later > 0 test will be optimized away.
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Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor()
and all _CPU_SMP_Get_current_processor(). Make inline ASM statements
volatile again. Test smptests/smpmigration01 showed that GCC optimizes
too much otherwise.
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Fix serious race-condition. Read the heir after the per-CPU lock
acquire.
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Rename _Internal_error_Occurred() into _Terminate().
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Inline _SMP_Inter_processor_interrupt_handler() to avoid function call
overhead. Remove debug output.
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Wait for per-CPU changes into PER_CPU_STATE_READY_TO_BEGIN_MULTITASKING
later. There is no need to delay the initialization of the main
processor at this point.
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Rename rtems_smp_process_interrupt() into
_SMP_Inter_processor_interrupt_handler(). Delete unused header file
<rtems/bspsmp.h>.
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Rename rtems_smp_secondary_cpu_initialize() into
_SMP_Start_multitasking_on_secondary_processor(). Move declaration to
<rtems/score/smpimpl.h>.
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Collect SMP implementation specific parts in the
<rtems/score/smpimpl.h> header file.
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Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
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Rename bsp_smp_initialize() into _CPU_SMP_Initialize() since every CPU
port must supply this function.
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Rename RTEMS_BSP_SMP_SHUTDOWN in SMP_MESSAGE_SHUTDOWN since SMP messages
have nothing to do with the BSP. Use UINT32_C() instead of casts.
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Use rtems_fatal() instead of _CPU_Fatal_halt() to shutdown processors in
SMP configurations since this allows intervention of BSP or application
specific fatal extensions.
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Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC
into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to
figure out the code position given a fatal source and code.
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This error case is no longer required since rtems_shutdown_executive()
can be called anytime, anywhere
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Move _SMP_Request_other_cores_to_shutdown() invocation from
rtems_shutdown_executive() to _Internal_error_Occurred() to allow a
proper shutdown on SMP configurations even in the error case.
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Disable interrupts as the first step in _Internal_error_Occurred() to
get a defined execution context for the fatal extensions.
Make _ISR_Disable_without_giant() available for non-SMP configurations.
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Do not return to BSP context in the exit() shutdown path. This makes it
possible to re-use the initialization stack. It can be used for the
interrupt stack for example. On targets with a small RAM this is a
considerable benefit.
This change eliminates also some special cases and simplifies the code.
Delete _Thread_Set_global_exit_status(),
_Thread_Get_global_exit_status() and _Thread_Stop_multitasking().
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Merge systems states SYSTEM_STATE_SHUTDOWN and SYSTEM_STATE_FAILED into
new system state SYSTEM_STATE_TERMINATED. This reflects that all system
termination paths end up in _Internal_error_Occurred().
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Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().
At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
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Move SMP interrupt stack initialization for secondary processors from
_SMP_Handler_initialize() to _ISR_Handler_initialization() to avoid code
duplication. Apply _CPU_Interrupt_stack_setup() to all interrupt
stacks.
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Use a ticket lock implementation based on atomic operations. Delete CPU
port specific SMP lock implementations.
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Use SWAP instruction with one lock for the system in the SMP case.
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Add _LEON3_Get_current_processor().
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The instructions to get the processor current index have no
side-effects.
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Add a CPU counter interface to allow access to a free-running counter.
It is useful to measure short time intervals. This can be used for
example to enable profiling of critical low-level functions.
Add two busy wait functions rtems_counter_delay_ticks() and
rtems_counter_delay_nanoseconds() implemented via the CPU counter.
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Recent LEON4 systems use a cache line size of 32 bytes.
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Rename rtems_internal_error_description() to
rtems_internal_error_text(). Rename rtems_fatal_source_description() to
rtems_fatal_source_text(). Rename rtems_status_code_description() to
rtems_status_text(). Remove previous implementation of
rtems_status_text().
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The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
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Delete _CPU_Context_switch_to_first_task_smp() and use
_CPU_Context_restore() instead.
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Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
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