powerpc: Change interrupt disable implemetation

Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().

At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.

3 files changed, 36 insertions, 19 deletions

diff --git a/cpukit/score/cpu/powerpc/Makefile.am b/cpukit/score/cpu/powerpc/Makefile.am
index b205762674..5934dae6c9 100644
--- a/cpukit/score/cpu/powerpc/Makefile.am
+++ b/cpukit/score/cpu/powerpc/Makefile.am
@@ -16,6 +16,7 @@ noinst_LIBRARIES = libscorecpu.a
 libscorecpu_a_SOURCES = cpu.c
 libscorecpu_a_SOURCES += ppc-context-volatile-clobber.S
 libscorecpu_a_SOURCES += ppc-context-validate.S
+libscorecpu_a_SOURCES += ppc-isr-disable-mask.S
 libscorecpu_a_SOURCES += ppc-isr-vector-install.c
 libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
 
diff --git a/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S b/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S
new file mode 100644
index 0000000000..4784b65b7e
--- /dev/null
+++ b/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+#include <rtems/score/cpu.h>
+
+.global	_PPC_INTERRUPT_DISABLE_MASK
+.weak	_PPC_INTERRUPT_DISABLE_MASK
+.set	_PPC_INTERRUPT_DISABLE_MASK, PPC_INTERRUPT_DISABLE_MASK_DEFAULT
diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
index a64291ed15..6cf713671b 100644
--- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
@@ -581,8 +581,8 @@ lidate */
 /**
  * @brief Default value for the interrupt disable mask.
  *
- * The interrupt disable mask is stored in the SPRG0 (= special purpose
- * register 272).
+ * The interrupt disable mask is stored in the global symbol
+ * _PPC_INTERRUPT_DISABLE_MASK.
  */
 #define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
 
@@ -603,25 +603,16 @@ extern "C" {
 #define _CPU_MSR_SET( _msr_value ) \
 { __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
 
-static inline void ppc_interrupt_set_disable_mask( uint32_t mask )
-{
-  __asm__ volatile (
-    "mtspr 272, %0"
-    :
-    : "r" (mask)
-  );
-}
+/**
+ * @brief A global symbol used to disable interrupts in the MSR.
+ *
+ * A one bit means that this bit should be cleared.
+ */
+extern char _PPC_INTERRUPT_DISABLE_MASK[];
 
 static inline uint32_t ppc_interrupt_get_disable_mask( void )
 {
-  uint32_t mask;
-
-  __asm__ volatile (
-    "mfspr %0, 272"
-    : "=r" (mask)
-  );
-
-  return mask;
+  return (uint32_t) _PPC_INTERRUPT_DISABLE_MASK;
 }
 
 static inline uint32_t ppc_interrupt_disable( void )
@@ -631,7 +622,8 @@ static inline uint32_t ppc_interrupt_disable( void )
 
   __asm__ volatile (
     "mfmsr %0;"
-    "mfspr %1, 272;"
+    "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;"
+    "ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;"
     "andc %1, %0, %1;"
     "mtmsr %1"
     : "=r" (level), "=r" (mask)