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* bsp/x86_64: Minimal bootable BSPAmaan Cheval2018-07-1113-1/+896
| | | | | | | | | | | | | | | | Current state: - Basic context initialization and switching code. - Stubbed console (empty functions). - Mostly functional linker script (may need tweaks if we ever want to move away from the large code model (see: CPU_CFLAGS). - Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for UEFI-awareness. In short, the current state with this commit lets us boot, go through the system initialization functions, and then call user application's Init task too. Updates #2898.
* riscv: Add LADDR assembler defineSebastian Huber2018-07-062-2/+12
| | | | | | | An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
* riscv: Implement CPU counterSebastian Huber2018-07-062-2/+16
| | | | Update #3433.
* riscv: Clear reservationsSebastian Huber2018-07-055-6/+25
| | | | | | | See also RISC-V User-Level ISA V2.3, comment in section 8.2 "Load-Reserved/Store-Conditional Instructions". Update #3433.
* posix: Check for new <pthread.h> prototypesSebastian Huber2018-07-055-9/+40
| | | | | Update #3342. Update #3343.
* riscv: Fix fcsr initializationSebastian Huber2018-07-022-1/+19
| | | | Update #3433.
* score: Increase PER_CPU_CONTROL_SIZE_APPROXSebastian Huber2018-06-291-1/+1
| | | | | | Increase the PER_CPU_CONTROL_SIZE_APPROX on 64-bit targets. Update #3433.
* riscv: Fix SMP context switch supportSebastian Huber2018-06-291-2/+2
| | | | Update #3433.
* riscv: Add SMP context switch supportSebastian Huber2018-06-291-0/+47
| | | | Update #3433.
* riscv: Add floating-point supportSebastian Huber2018-06-298-50/+538
| | | | Update #3433.
* riscv: Fix global constructionSebastian Huber2018-06-293-6/+7
| | | | Update #3433.
* riscv: Add TLS supportSebastian Huber2018-06-292-0/+9
| | | | Update #3433.
* riscv: Remove dead codeSebastian Huber2018-06-291-41/+1
| | | | Update #3433.
* riscv: Optimize context switch and interruptsSebastian Huber2018-06-296-174/+255
| | | | | | | | Save/restore non-volatile registers in _CPU_Context_switch(). Save/restore volatile registers in _ISR_Handler(). Update #3433.
* riscv: Fix _CPU_Context_Initialize() prototypeSebastian Huber2018-06-292-12/+12
| | | | Update #3433.
* riscv: Fix interrupt save/restoreSebastian Huber2018-06-291-1/+1
| | | | Update #3433.
* riscv: Implement _CPU_Context_validate()Sebastian Huber2018-06-292-160/+168
| | | | Update #3433.
* riscv: Make some CPU port defines visible to asmSebastian Huber2018-06-292-37/+49
| | | | | | Move SREG and LREG assembler defines to <rtems/score/asm.h>. Update #3433.
* riscv: Implement _CPU_Context_volatile_clobber()Sebastian Huber2018-06-292-16/+16
| | | | Update #3433.
* riscv: Remove mstatus from thread contextSebastian Huber2018-06-294-27/+14
| | | | | | | | | | The mstatus register contains no thread-specific state which must be saved/restored during a context switch. Machine interrupts (MIE) must be enabled during a context switch. Create separate CPU_Interrupt_frame structure. Update #3433.
* riscv: Remove x8 initializationSebastian Huber2018-06-291-2/+0
| | | | | | | | | | The RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md does not mention that this is a frame pointer. Update #3433.
* riscv: Properly align the thread stackSebastian Huber2018-06-291-3/+7
| | | | Update #3433.
* riscv: Do not clear thread contextSebastian Huber2018-06-291-5/+2
| | | | | | | | Do not clear the complete thread context. Initialize only the necessary members. The Context_Control::is_executing member must be preserved across _CPU_Context_Initialize() calls. Update #3433.
* riscv: Fix CPU_STACK_ALIGNMENTSebastian Huber2018-06-291-1/+2
| | | | | | | | | | According to the RISC-V psABI https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md the stack alignment is 128 bits (16 bytes). Update #3433.
* riscv: Remove RISCV_GCC_RED_ZONE_SIZESebastian Huber2018-06-292-5/+1
| | | | | | | | | | | The current ABI says that there is no stack red zone: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md "Procedures must not rely upon the persistence of stack-allocated data whose addresses lie below the stack pointer." Update #3433.
* riscv: Enable interrupts during dispatch after ISRSebastian Huber2018-06-295-55/+91
| | | | | | | | The code sequence is derived from the ARM code (see _ARMV4_Exception_interrupt). Update #2751. Update #3433.
* riscv: Add _CPU_Get_current_per_CPU_control()Sebastian Huber2018-06-282-0/+23
| | | | Update #3433.
* riscv: Avoid namespace pollutionSebastian Huber2018-06-283-10/+4
| | | | | | | Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h> (which is visible via <rtems.h> for example). Update #3433.
* riscv: Optimize and fix interrupt disable/enableSebastian Huber2018-06-281-15/+16
| | | | | | | | | Use the atomic read and clear operation to disable interrupts. Do not write the complete mstatus. Instead, set only the MIE bit depending on the level parameter. Update #3433.
* riscv: Add dummy SMP supportSebastian Huber2018-06-282-125/+27
| | | | Update #3433.
* build: Enable RISC-V SMP buildSebastian Huber2018-06-281-1/+1
| | | | Update #3433.
* riscv: Implement ISR set/get levelSebastian Huber2018-06-282-9/+18
| | | | | | Fix prototypes. Update #3433.
* bsp/riscv: Load global pointerSebastian Huber2018-06-271-2/+0
| | | | Update #3433.
* riscv: Format assembler filesSebastian Huber2018-06-274-435/+437
| | | | | | Use tabs to match the GCC generated assembler output. Update #3433.
* Rework initialization and interrupt stack supportSebastian Huber2018-06-2741-1275/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
* score: Add CPU_INTERRUPT_STACK_ALIGNMENTSebastian Huber2018-06-2718-0/+45
| | | | | | | Add CPU port define for the interrupt stack alignment. The alignment should take the stack ABI and the cache line size into account. Update #3459.
* console: Add missing return statusSebastian Huber2018-06-271-0/+2
| | | | Update #3320.
* Remove unused CPU_MODES_INTERRUPT_LEVELSebastian Huber2018-06-273-3/+0
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* score: Macros to declare and define global symbolsSebastian Huber2018-06-211-1/+33
| | | | | | Add RTEMS_DEFINE_GLOBAL_SYMBOL() and add RTEMS_DECLARE_GLOBAL_SYMBOL(). Update #3459.
* stackchk: Add SMP supportSebastian Huber2018-06-202-38/+67
| | | | | | | | | | | | Check the interrupt stacks of all processors. Set up the interrupt stack of the current processor for high water testing in the thread begin extension. This must be done after multi-threading started, since the initialization stacks may reuse the interrupt stacks. Disable thread dispatching in SMP configurations to prevent thread migration. Writing to the interrupt stack is only safe if done from the corresponding processor in thread context. Update #3459.
* stackchk: Refactor Stack_check_Dump_threads_usageSebastian Huber2018-06-201-60/+49
| | | | Update #3459.
* stackchk: Remove dead codeSebastian Huber2018-06-202-26/+2
| | | | Update #3459.
* config: SMP only CONFIGURE_MAXIMUM_PROCESSORSSebastian Huber2018-06-201-1/+3
| | | | | | | Do not set the CONFIGURE_MAXIMUM_PROCESSORS in uni-processor default configuration, since this may lead to an oversize workspace. Update #3459.
* arm: Simplify CPU counter supportSebastian Huber2018-06-151-2/+5
| | | | | | | | | | Use the standard ARMv7-M systick module for the ARMv7-M CPU counter instead of DWT counter since the DWT counter is affected by power saving states. Use an inline function for _CPU_Counter_difference() for all ARM BSPs. Update #3456.
* Add _CPU_Counter_frequency()Sebastian Huber2018-06-1536-7/+103
| | | | | | | | | | Add rtems_counter_frequency() API function. Use it to initialize the counter value converter via the new system initialization step (RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation and the counter converter. It avoids an unnecessary pull in of the 64-bit integer division from libgcc. Update #3456.
* Add RTEMS_SYSINIT_CPU_COUNTERSebastian Huber2018-06-151-1/+2
| | | | | | Add initialization step for the CPU counter support. Update #3456.
* Reassign system initilization order numbersSebastian Huber2018-06-151-39/+39
| | | | | Assign each system initialization step a number divisible by 256 to allow more easily future additions. Keep the order as is.
* powerpc: Fix ss555 buildSebastian Huber2018-06-071-6/+0
| | | | | | | The mpc555 define is provided via <bspopts.h>. It must not be used in cpukit header files. Update #3425.
* Add RTEMS_FATAL_SOURCE_INVALID_HEAP_FREESebastian Huber2018-06-053-7/+10
| | | | | | | | An invalid heap usage such as a double free is usually a fatal error since this indicates a use after free. Replace the use of printk() in free() with a fatal error. Update #3437.
* Update rtems_fatal_source_text()Sebastian Huber2018-06-051-2/+3
| | | | | | Add RTEMS_FATAL_SOURCE_PANIC to rtems_fatal_source_text(). Update #3244.
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