diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-06 11:07:20 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-06 13:46:46 +0200 |
| commit | bca36d986b24b0720ce19b618bbe592baed6cb95 (patch) | |
| tree | a1cb260164decf4d98def37505203269920cf985 /cpukit | |
| parent | riscv: Implement CPU counter (diff) | |
| download | rtems-bca36d986b24b0720ce19b618bbe592baed6cb95.tar.bz2 | |
riscv: Add LADDR assembler define
An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.
Update #3433.
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/asm.h | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 2 |
2 files changed, 12 insertions, 2 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/asm.h b/cpukit/score/cpu/riscv/include/rtems/asm.h index c3be827be0..c4abc76a27 100644 --- a/cpukit/score/cpu/riscv/include/rtems/asm.h +++ b/cpukit/score/cpu/riscv/include/rtems/asm.h @@ -131,6 +131,16 @@ #endif /* __riscv_xlen */ +#ifdef __riscv_cmodel_medany + +#define LADDR lla + +#else /* !__riscv_cmodel_medany */ + +#define LADDR la + +#endif /* __riscv_cmodel_medany */ + #if __riscv_flen == 32 #define FLREG flw @@ -167,7 +177,7 @@ #ifdef RTEMS_SMP csrr \REG, mscratch #else - la \REG, _Per_CPU_Information + LADDR \REG, _Per_CPU_Information #endif .endm diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 05bad455ac..875566cb23 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -128,7 +128,7 @@ SYM(ISR_Handler): mv a1, sp /* calculate the offset */ - la t5, bsp_start_vector_table_begin + LADDR t5, bsp_start_vector_table_begin #if __riscv_xlen == 32 slli t6, a0, 2 #else /* xlen = 64 */ |