diff options
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/configure.ac | 1 | ||||
| -rw-r--r-- | cpukit/librpc/src/xdr/xdr_float.c | 3 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/Makefile.am | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/cpu.c | 83 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/headers.am | 16 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/include/machine/elf_machdep.h | 4 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/asm.h | 134 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/cpu.h | 359 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h | 14 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h | 37 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h | 41 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/x86_64-context-initialize.c | 95 | ||||
| -rw-r--r-- | cpukit/score/cpu/x86_64/x86_64-context-switch.S | 98 |
13 files changed, 896 insertions, 1 deletions
diff --git a/cpukit/configure.ac b/cpukit/configure.ac index 0361128e1d..17c47f445e 100644 --- a/cpukit/configure.ac +++ b/cpukit/configure.ac @@ -487,6 +487,7 @@ score/cpu/sh/Makefile score/cpu/sparc/Makefile score/cpu/sparc64/Makefile score/cpu/v850/Makefile +score/cpu/x86_64/Makefile score/cpu/no_cpu/Makefile posix/Makefile libblock/Makefile diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c index 989cbfffad..b2282b376a 100644 --- a/cpukit/librpc/src/xdr/xdr_float.c +++ b/cpukit/librpc/src/xdr/xdr_float.c @@ -76,7 +76,8 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00 defined(__sh__) || \ defined(__BFIN__) || \ defined(__m32c__) || \ - defined(__v850) + defined(__v850) || \ + defined(__x86_64__) #include <rtems/endian.h> #if !defined(IEEEFP) diff --git a/cpukit/score/cpu/x86_64/Makefile.am b/cpukit/score/cpu/x86_64/Makefile.am new file mode 100644 index 0000000000..db4bd15cd5 --- /dev/null +++ b/cpukit/score/cpu/x86_64/Makefile.am @@ -0,0 +1,12 @@ +include $(top_srcdir)/automake/compile.am + +noinst_LIBRARIES = libscorecpu.a +libscorecpu_a_SOURCES = cpu.c +libscorecpu_a_SOURCES += ../no_cpu/cpucounterfrequency.c +libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c +libscorecpu_a_SOURCES += x86_64-context-initialize.c +libscorecpu_a_SOURCES += x86_64-context-switch.S +libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) + +include $(top_srcdir)/automake/local.am +include $(srcdir)/headers.am diff --git a/cpukit/score/cpu/x86_64/cpu.c b/cpukit/score/cpu/x86_64/cpu.c new file mode 100644 index 0000000000..308d231186 --- /dev/null +++ b/cpukit/score/cpu/x86_64/cpu.c @@ -0,0 +1,83 @@ +/** + * @file + * + * @brief x86_64 Dependent Source + */ + +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Copyright (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/system.h> +#include <rtems/score/isr.h> +#include <rtems/score/wkspace.h> +#include <rtems/score/tls.h> + +Context_Control_fp _CPU_Null_fp_context; + +void _CPU_Exception_frame_print(const CPU_Exception_frame *ctx) +{ +} + +void _CPU_Initialize(void) +{ +} + +uint32_t _CPU_ISR_Get_level(void) +{ + return 0; +} + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ +} + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +) +{ +} + +void _CPU_Install_interrupt_stack(void) +{ +} + +void *_CPU_Thread_Idle_body(uintptr_t ignored) +{ + for( ; ; ) { } +} diff --git a/cpukit/score/cpu/x86_64/headers.am b/cpukit/score/cpu/x86_64/headers.am new file mode 100644 index 0000000000..b3792d00b1 --- /dev/null +++ b/cpukit/score/cpu/x86_64/headers.am @@ -0,0 +1,16 @@ +## This file was generated by "./boostrap -H". + +include_machinedir = $(includedir)/machine +include_machine_HEADERS = +include_machine_HEADERS += include/machine/elf_machdep.h + +include_rtemsdir = $(includedir)/rtems +include_rtems_HEADERS = +include_rtems_HEADERS += include/rtems/asm.h + +include_rtems_scoredir = $(includedir)/rtems/score +include_rtems_score_HEADERS = +include_rtems_score_HEADERS += include/rtems/score/cpu.h +include_rtems_score_HEADERS += include/rtems/score/cpuatomic.h +include_rtems_score_HEADERS += include/rtems/score/cpuimpl.h +include_rtems_score_HEADERS += include/rtems/score/x86_64.h diff --git a/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h b/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h new file mode 100644 index 0000000000..5f5cf1d6e0 --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/machine/elf_machdep.h @@ -0,0 +1,4 @@ +/* + * XXX: Needs research as to purpose. Seems like this might do: + * https://github.com/NetBSD/src/blob/trunk/sys/arch/amd64/include/elf_machdep.h + */ diff --git a/cpukit/score/cpu/x86_64/include/rtems/asm.h b/cpukit/score/cpu/x86_64/include/rtems/asm.h new file mode 100644 index 0000000000..36699140b7 --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/rtems/asm.h @@ -0,0 +1,134 @@ +/** + * @file rtems/asm.h + * + * @brief Addresses Incompatible Flavors Problems + * + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. + * + * NOTE: The spacing in the use of these macros + * is critical to them working as advertised. + */ + +/* + * COPYRIGHT: + * + * This file is based on similar code found in newlib available + * from ftp.cygnus.com. The file which was used had no copyright + * notice. This file is freely distributable as long as the source + * of the file is noted. This file is: + * + * COPYRIGHT (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * COPYRIGHT (c) 1994-2006. + * On-Line Applications Research Corporation (OAR). + */ + +#ifndef _RTEMS_ASM_H +#define _RTEMS_ASM_H + +/* + * Indicate we are in an assembly file and get the basic CPU definitions. + */ + +#ifndef ASM +#define ASM +#endif +#include <rtems/score/cpuopts.h> +#include <rtems/score/x86_64.h> + +#ifndef __USER_LABEL_PREFIX__ +/** + * Recent versions of GNU cpp define variables which indicate the + * need for underscores and percents. If not using GNU cpp or + * the version does not support this, then you will obviously + * have to define these as appropriate. + * + * This symbol is prefixed to all C program symbols. + */ +#define __USER_LABEL_PREFIX__ _ +#endif + +#undef __REGISTER_PREFIX__ +#define __REGISTER_PREFIX__ % + +#include <rtems/concat.h> + +/** Use the right prefix for global labels. */ +#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +/** Use the right prefix for registers. */ +#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) + +/* + * define macros for all of the registers on this CPU + */ +#define rax REG (rax) +#define rbx REG (rbx) +#define rcx REG (rcx) +#define rdx REG (rdx) +#define rdi REG (rdi) +#define rsi REG (rsi) +#define rbp REG (rbp) +#define rsp REG (rsp) +#define r8 REG (r8) +#define r9 REG (r9) +#define r10 REG (r10) +#define r11 REG (r11) +#define r12 REG (r12) +#define r13 REG (r13) +#define r14 REG (r14) +#define r15 REG (r15) + +// XXX: eax, ax, etc., segment registers + +/* + * Define macros to handle section beginning and ends. + */ + +/** This macro is used to denote the beginning of a code declaration. */ +#define BEGIN_CODE_DCL .text +/** This macro is used to denote the end of a code declaration. */ +#define END_CODE_DCL +/** This macro is used to denote the beginning of a data declaration section. */ +#define BEGIN_DATA_DCL .data +/** This macro is used to denote the end of a data declaration section. */ +#define END_DATA_DCL +/** This macro is used to denote the beginning of a code section. */ +#define BEGIN_CODE .text +/** This macro is used to denote the end of a code section. */ +#define END_CODE +/** This macro is used to denote the beginning of a data section. */ +#define BEGIN_DATA +/** This macro is used to denote the end of a data section. */ +#define END_DATA +/** This macro is used to denote the beginning of the + * unitialized data section. + */ +#define BEGIN_BSS +/** This macro is used to denote the end of the unitialized data section. */ +#define END_BSS +/** This macro is used to denote the end of the assembly file. */ +#define END + +/** + * This macro is used to declare a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define PUBLIC(sym) .globl SYM (sym) + +/** + * This macro is used to prototype a public global symbol. + * + * @note This must be tailored for a particular flavor of the C compiler. + * They may need to put underscores in front of the symbols. + */ +#define EXTERN(sym) .globl SYM (sym) + +#endif diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h new file mode 100644 index 0000000000..012ef5069b --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h @@ -0,0 +1,359 @@ +/** + * @file rtems/score/cpu.h + * + * @brief x86_64 Dependent Source + * + * This include file contains information pertaining to the x86_64 processor. + */ + +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems/score/basedefs.h> +#include <rtems/score/x86_64.h> + +#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE +#define CPU_ISR_PASSES_FRAME_POINTER FALSE +// XXX: Enable FPU support +#define CPU_HARDWARE_FP FALSE +#define CPU_SOFTWARE_FP FALSE +#define CPU_ALL_TASKS_ARE_FP FALSE +#define CPU_IDLE_TASK_IS_FP FALSE +#define CPU_USE_DEFERRED_FP_SWITCH TRUE +#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE +#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE +#define CPU_STACK_GROWS_UP FALSE + +#define CPU_STRUCTURE_ALIGNMENT __attribute__((aligned ( 64 ))) +#define CPU_CACHE_LINE_BYTES 64 +#define CPU_MODES_INTERRUPT_MASK 0x00000001 +#define CPU_MAXIMUM_PROCESSORS 32 + +#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 +#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 + +#ifndef ASM + +typedef struct { + uint64_t rflags; + + /** + * Callee-saved registers as listed in the SysV ABI document: + * https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI + */ + uint64_t rbx; + void *rsp; + void *rbp; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + + // XXX: FS segment descriptor for TLS + +#ifdef RTEMS_SMP + volatile bool is_executing; +#endif +} Context_Control; + +#define _CPU_Context_Get_SP( _context ) \ + (_context)->rsp + +typedef struct { + /* XXX: MMX, XMM, others? + * + * All x87 registers are caller-saved, so callees that make use of the MMX + * registers may use the faster femms instruction + */ + + /** FPU registers are listed here */ + double some_float_register; +} Context_Control_fp; + +typedef struct { + uint32_t special_interrupt_register; +} CPU_Interrupt_frame; + +#endif /* ASM */ + + +#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE +#define CPU_STACK_MINIMUM_SIZE (1024*4) +#define CPU_SIZEOF_POINTER 8 +#define CPU_ALIGNMENT 8 +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT +#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT +#define CPU_STACK_ALIGNMENT 16 +#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES + +/* + * ISR handler macros + */ + +#ifndef ASM + +#define _CPU_Initialize_vectors() + +// XXX: For RTEMS critical sections +#define _CPU_ISR_Disable( _isr_cookie ) \ + { \ + (_isr_cookie) = 0; /* do something to prevent warnings */ \ + } + +#define _CPU_ISR_Enable( _isr_cookie ) \ + { \ + (void) (_isr_cookie); /* prevent warnings from -Wunused-but-set-variable */ \ + } + +#define _CPU_ISR_Flash( _isr_cookie ) \ + { \ + } + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return false; +} + +#define _CPU_ISR_Set_level( new_level ) \ + { \ + } + +uint32_t _CPU_ISR_Get_level( void ); + +/* end of ISR handler macros */ + +/* Context handler macros */ +#define _CPU_Context_Destroy( _the_thread, _the_context ) \ + { \ + } + +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +#define _CPU_Fatal_halt( _source, _error ) \ + { \ + } + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + { \ + (_output) = 0; /* do something to prevent warnings */ \ + } +#endif + +/* end of Bitfield handler macros */ + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) +#define _CPU_Priority_Mask( _bit_number ) \ + ( 1 << (_bit_number) ) +#endif + +#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) +#define _CPU_Priority_bits_index( _priority ) \ + (_priority) +#endif + +/* end of Priority handler macros */ + +/* functions */ + +void _CPU_Initialize(void); + +void _CPU_ISR_install_raw_handler( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +void _CPU_ISR_install_vector( + uint32_t vector, + proc_ptr new_handler, + proc_ptr *old_handler +); + +void _CPU_Install_interrupt_stack( void ); + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +void _CPU_Context_restore( + Context_Control *new_context +) RTEMS_NO_RETURN; + +void _CPU_Context_save_fp( + Context_Control_fp **fp_context_ptr +); + +void _CPU_Context_restore_fp( + Context_Control_fp **fp_context_ptr +); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +static inline void _CPU_Context_validate( uintptr_t pattern ); + +static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) +{ + /* TODO */ +} + +static inline void _CPU_Context_validate( uintptr_t pattern ) +{ + while (1) { + /* TODO */ + } +} + +typedef struct { + uint32_t processor_state_register; + uint32_t integer_registers [1]; + double float_registers [1]; +} CPU_Exception_frame; + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +typedef uint32_t CPU_Counter_ticks; + +uint32_t _CPU_Counter_frequency( void ); + +CPU_Counter_ticks _CPU_Counter_read( void ); + + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +#ifdef RTEMS_SMP + * + uint32_t _CPU_SMP_Initialize( void ); + + bool _CPU_SMP_Start_processor( uint32_t cpu_index ); + + void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); + + void _CPU_SMP_Prepare_start_multitasking( void ); + + static inline uint32_t _CPU_SMP_Get_current_processor( void ) + { + return 123; + } + + void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); + + static inline void _CPU_SMP_Processor_event_broadcast( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + static inline void _CPU_SMP_Processor_event_receive( void ) + { + __asm__ volatile ( "" : : : "memory" ); + } + + static inline bool _CPU_Context_Get_is_executing( + const Context_Control *context + ) + return context->is_executing; + } + + static inline void _CPU_Context_Set_is_executing( + Context_Control *context, + bool is_executing + ) + { + } + +#endif /* RTEMS_SMP */ + +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..598ee76b20 --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuatomic.h @@ -0,0 +1,14 @@ +/* + * COPYRIGHT (c) 2012-2013 Deng Hengyi. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include <rtems/score/cpustdatomic.h> + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..bac092c320 --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h @@ -0,0 +1,37 @@ +/** + * @file + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Copyright (c) 2013, 2016 embedded brains GmbH + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include <rtems/score/cpu.h> + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h b/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h new file mode 100644 index 0000000000..237d95de98 --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/rtems/score/x86_64.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_X86_64_H +#define _RTEMS_SCORE_X86_64_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CPU_NAME "x86-64" +#define CPU_MODEL_NAME "XXX: x86-64 generic" + +#ifdef __cplusplus +} +#endif + +#endif /* _RTEMS_SCORE_X86_64_H */ diff --git a/cpukit/score/cpu/x86_64/x86_64-context-initialize.c b/cpukit/score/cpu/x86_64/x86_64-context-initialize.c new file mode 100644 index 0000000000..2324d16990 --- /dev/null +++ b/cpukit/score/cpu/x86_64/x86_64-context-initialize.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <rtems/score/cpu.h> +#include <rtems/score/tls.h> + +/* + * Stack alignment note: + * + * Per the x86-64 SysV ABI, the stack frame layout is as follows: + * optional args + * ------ (16-byte alignment boundary) + * RSP-> return_addr (RSP is moved lower as needed for this frame) + * + * Per the ABI: + * + * > The end of the input argument area shall be aligned on a 16 (32 or 64, if + * __m256 or __m512 is passed on stack) byte boundary. + * + * > In other words, the value (%rsp + 8) is always a multiple of 16 (32 or 64) + * when control is transferred to the function entry point. + * + * We want the stack to look to the '_entry_point' routine + * like an ordinary stack frame as if '_entry_point' was + * called from C-code. + * Note that '_entry_point' is jumped-to by the 'ret' + * instruction returning from _CPU_Context_switch() or + * _CPU_Context_restore() thus popping the _entry_point + * from the stack. + * + * Hence we must initialize the stack as follows + * + * [arg0 (aligned)]: n/a + * [ret. addr ]: NULL + * RSP-> [jump-target ]: _entry_point + * + * When Context_switch returns it pops the _entry_point from + * the stack which then finds a standard layout. + */ +void _CPU_Context_Initialize( + Context_Control *the_context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +) +{ + uintptr_t _stack; + + /* avoid warning for being unused */ + (void) is_fp; + + // XXX: Should be used in the future + (void) new_level; + (void) tls_area; + + // XXX: Leaving interrupts off regardless of `new_level` for now + the_context->rflags = CPU_EFLAGS_INTERRUPTS_OFF; + + _stack = ((uintptr_t) stack_area_begin) + stack_area_size; + _stack &= ~(CPU_STACK_ALIGNMENT - 1); + _stack -= sizeof(uintptr_t); /* fake return address for entry_point's frame; + * this allows rsp+8 to be an aligned boundary */ + *((proc_ptr *) _stack) = entry_point; + + the_context->rbp = (void *) 0; + the_context->rsp = (void *) _stack; + + // XXX: Initialize thread-local storage area (TLS / TCB) +} diff --git a/cpukit/score/cpu/x86_64/x86_64-context-switch.S b/cpukit/score/cpu/x86_64/x86_64-context-switch.S new file mode 100644 index 0000000000..cb451e9acb --- /dev/null +++ b/cpukit/score/cpu/x86_64/x86_64-context-switch.S @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/asm.h> +#include <rtems/score/cpu.h> + +#ifndef CPU_STACK_ALIGNMENT +#error "Missing header? CPU_STACK_ALIGNMENT not defined" +#endif + +BEGIN_CODE + +/* + * void _CPU_Context_switch( run_context, heir_context ) + * + * This routine performs a normal non-FP context. + */ + +.p2align 1 +PUBLIC(_CPU_Context_switch) + +.set RUNCONTEXT_ARG, rdi /* save context argument */ +.set HEIRCONTEXT_ARG, rsi /* restore context argument */ + +SYM(_CPU_Context_switch): + movq RUNCONTEXT_ARG, rax /* rax = running threads context */ + + /* Fill up Context_Control struct */ + pushf + popq (0 * CPU_SIZEOF_POINTER)(rax) /* pop rflags into context */ + movq rbx, (1 * CPU_SIZEOF_POINTER)(rax) + movq rsp, (2 * CPU_SIZEOF_POINTER)(rax) + movq rbp, (3 * CPU_SIZEOF_POINTER)(rax) + movq r12, (4 * CPU_SIZEOF_POINTER)(rax) + movq r13, (5 * CPU_SIZEOF_POINTER)(rax) + movq r14, (6 * CPU_SIZEOF_POINTER)(rax) + movq r15, (7 * CPU_SIZEOF_POINTER)(rax) + + movq HEIRCONTEXT_ARG, rax /* rax = heir threads context */ + +restore: + pushq (0 * CPU_SIZEOF_POINTER)(rax) /* push rflags */ + popf /* restore rflags */ + movq (1 * CPU_SIZEOF_POINTER)(rax), rbx + movq (2 * CPU_SIZEOF_POINTER)(rax), rsp + movq (3 * CPU_SIZEOF_POINTER)(rax), rbp + movq (4 * CPU_SIZEOF_POINTER)(rax), r12 + movq (5 * CPU_SIZEOF_POINTER)(rax), r13 + movq (6 * CPU_SIZEOF_POINTER)(rax), r14 + movq (7 * CPU_SIZEOF_POINTER)(rax), r15 + + /* XXX: TLS - load GDT and refresh FS segment selector */ + + ret + +/* + * void _CPU_Context_restore( new_context ) + * + * This routine performs a normal non-FP context restore. + */ + +PUBLIC(_CPU_Context_restore) + +.set NEWCONTEXT_ARG, rdi /* context to restore argument */ + +SYM(_CPU_Context_restore): + movq NEWCONTEXT_ARG, rax /* rax = running threads context */ + jmp restore + +END_CODE +END |