Commit message (Collapse) | Author | Age | Files | Lines | |
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* | score: More robust _SMP_Multicast_action() | Sebastian Huber | 2019-04-12 | 1 | -2/+12 |
| | | | | | | If the caller already disabled interrupts, then do not disable thread dispatching. Calling _SMP_Multicast_action() with interrupts disabled is a questionable use case. | ||||
* | score: Remove _SMP_Before_multitasking_action() | Sebastian Huber | 2019-04-12 | 2 | -96/+0 |
| | | | | Use _SMP_Multicast_action() instead. | ||||
* | score: Improve _SMP_Multicast_action() | Sebastian Huber | 2019-04-12 | 2 | -7/+22 |
| | | | | Let it work during system initialization. | ||||
* | score: Rework SMP multicast action | Sebastian Huber | 2019-04-12 | 2 | -76/+174 |
| | | | | | Use a FIFO list of jobs per processor to carry out the SMP multicast action. Use a done indicator per job to reduce the bus traffic a bit. | ||||
* | score: Use processor mask in _SMP_Multicast_action | Sebastian Huber | 2019-04-12 | 1 | -17/+7 |
| | | | | Processor_mask is the internal data type to deal with processor sets. | ||||
* | score: Use an ISR lock for Per_CPU_Control::Lock | Sebastian Huber | 2019-04-12 | 5 | -22/+23 |
| | | | | | | The use of a hand crafted lock for Per_CPU_Control::Lock was necessary at some point in the SMP support development, but it is no longer justified. | ||||
* | score: Add _ISR_lock_Set_name() | Sebastian Huber | 2019-04-12 | 1 | -2/+3 |
| | | | | | Add _ISR_lock_Set_name() to optimize the initialization of zero-initialized locks. | ||||
* | score: Rename _SMP_Get_processor_count() | Sebastian Huber | 2019-04-11 | 5 | -29/+39 |
| | | | | | | | Rename _SMP_Get_processor_count() in _SMP_Get_processor_maximum() to be in line with the API level rtems_scheduler_get_processor_maximum(). Update #3732. | ||||
* | score: Rename _SMP_Processor_count | Sebastian Huber | 2019-04-11 | 1 | -2/+2 |
| | | | | | | | Rename _SMP_Processor_count in _SMP_Processor_maximum to be in line with the API level rtems_scheduler_get_processor_maximum(). Update #3732. | ||||
* | Remove superfluous run-time check | Sebastian Huber | 2019-04-09 | 1 | -4/+1 |
| | | | | | The _Objects_Information_table[ the_api ] is never NULL for a valid API index. | ||||
* | doxygen: Rename Score* groups in RTEMSScore* | Sebastian Huber | 2019-04-04 | 157 | -157/+157 |
| | | | | Update #3706 | ||||
* | doxygen: Added Management to Example CPU Architecture | Andreas Dachsberger | 2019-04-04 | 1 | -0/+8 |
| | | | | Update #3706. | ||||
* | doxygen: score: Put ARM Co-Processor 15 group in ARM | Andreas Dachsberger | 2019-04-02 | 1 | -3/+3 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add x86-64 CPU architecture group | Andreas Dachsberger | 2019-04-02 | 2 | -0/+24 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add V850 CPU architecture group | Andreas Dachsberger | 2019-04-02 | 3 | -18/+54 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add SPARC64 CPU architecture group | Andreas Dachsberger | 2019-04-02 | 2 | -0/+22 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add SPARC CPU architecture group | Andreas Dachsberger | 2019-04-02 | 3 | -2/+26 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add SuperH CPU architecture group | Andreas Dachsberger | 2019-04-02 | 2 | -0/+20 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add RISC-V CPU architecture group | Andreas Dachsberger | 2019-04-02 | 4 | -1/+26 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add powerpc CPU architecture group | Andreas Dachsberger | 2019-04-02 | 5 | -2/+32 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add or1k CPU architecture group | Andreas Dachsberger | 2019-04-02 | 4 | -1/+27 |
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* | doxygen: score: Add nios2 CPU architecture group | Andreas Dachsberger | 2019-04-01 | 3 | -0/+26 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add Moxie CPU architecture group | Andreas Dachsberger | 2019-04-01 | 3 | -0/+26 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add m68k CPU architecture group | Andreas Dachsberger | 2019-04-01 | 9 | -10/+47 |
| | | | | Update #3706. | ||||
* | doxygen: score: Change no_cpu architecture group | Andreas Dachsberger | 2019-04-01 | 2 | -36/+49 |
| | | | | | | Groups CPUContext and CPUInterrupt are now defined with a unique name for this architecture group. Update #3706. | ||||
* | doxygen: score: Add lm32 CPU architecture group | Andreas Dachsberger | 2019-04-01 | 3 | -14/+53 |
| | | | | Update #3706. | ||||
* | doxygen: score: Add i386 CPU architecture group | Andreas Dachsberger | 2019-04-01 | 8 | -2/+57 |
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* | doxygen: score: Add Epiphany CPU architecture group | Andreas Dachsberger | 2019-04-01 | 4 | -2/+20 |
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* | doxygen: score: Add Blackfin CPU architecture group | Andreas Dachsberger | 2019-04-01 | 2 | -16/+43 |
| | | | | Update #3706. | ||||
* | score: Add ARM CPU architecture group | Sebastian Huber | 2019-03-26 | 10 | -52/+32 |
| | | | | Update #3706. | ||||
* | score: Add example CPU architecture group | Sebastian Huber | 2019-03-26 | 2 | -2/+14 |
| | | | | Update #3706. | ||||
* | score: Rename ScoreCPU Doxygen group | Sebastian Huber | 2019-03-26 | 14 | -16/+15 |
| | | | | Update #3706. | ||||
* | Remove superfluous <rtems/system.h> includes | Sebastian Huber | 2019-03-14 | 43 | -43/+1 |
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* | sparc64: Do not include <rtems/asm.h> in C source | Sebastian Huber | 2019-03-14 | 1 | -1/+0 |
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* | coremsgseize.c: Fix spelling error | Joel Sherrill | 2019-03-12 | 1 | -1/+1 |
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* | cpukit/arm: Correct register definition | Jonathan Brandmeyer | 2019-03-08 | 1 | -2/+2 |
| | | | | | | | | | | | | | | The register definition for the CP15 PMCR (performance monitor control register) has the bits for X (export enable) and D (clock divider enable) backwards. Correct them according to ARMv7-A/R Architecture Reference Manual, Rev C, Section B4.1.117. Consequences: On an implementation that starts off with D set at reset, the clock divider will not be disabled by using RTEMS' definition of the D bit. Tested by using the counter on Xilinx Zynq 7020 to measure some atomic accesses and cache flushing operations. | ||||
* | score: Fix _Scheduler_EDF_Cancel_job() | Sebastian Huber | 2019-03-01 | 1 | -2/+4 |
| | | | | Remove the priority node only in case it is active. | ||||
* | Remove explicit file names from @file | Sebastian Huber | 2019-02-28 | 25 | -25/+25 |
| | | | | | | This makes the @file documentation independent of the actual file name. Update #3707. | ||||
* | bsps/arm: Fix system register for virtual timer | Kinsey Moore | 2019-02-22 | 1 | -1/+1 |
| | | | | | | | | | The system register in use for retrieval of the virtual timer value was mistakenly copied from the physical timer value retrieval function. Virtual timer value retrieval should use the same system register as the virtual timer value setter. Close #3699. | ||||
* | score: Avoid some deadlocks in _Once() | Sebastian Huber | 2019-02-18 | 1 | -43/+74 |
| | | | | | | | | Recursive usage of the same pthread_once_t results now in a deadlock. Previously, an error of EINVAL was returned. This usage scenario is invalid according to the POSIX pthread_once() specification. Close #3334. | ||||
* | libdl: Fix the support for constructors and desctructors. | Chris Johns | 2019-02-09 | 1 | -20/+52 |
| | | | | | | | - Fix the handling of pending objects. - Add a constructor flags in objects to track then being called. Closes #2921 | ||||
* | score: Fix plain priority thread queues (SMP) | Sebastian Huber | 2019-02-07 | 1 | -0/+8 |
| | | | | We must add/remove the priority queue to the FIFO of priority queues. | ||||
* | riscv: Fix misaligned access in context validate | Sebastian Huber | 2019-02-02 | 1 | -1/+1 |
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* | m68k: Avoid _Addresses_Add_offset() | Sebastian Huber | 2019-01-29 | 1 | -4/+2 |
| | | | | | This prevents a cyclic dependency between <rtems/score/cpu.h> and <rtems/score/address.h>. | ||||
* | riscv: add griscv bsp | Jiri Gaisler | 2019-01-22 | 1 | -4/+1 |
| | | | | Update #3678. | ||||
* | grlib: use cpu-independent routines for uncached access | Jiri Gaisler | 2019-01-22 | 3 | -0/+83 |
| | | | | Update #3678. | ||||
* | score: Avoid internal API and use ISR lock | Sebastian Huber | 2019-01-18 | 1 | -9/+9 |
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* | m68k/include/rtems/score/cpu.h: Add include of address.h | Joel Sherrill | 2019-01-14 | 1 | -0/+2 |
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* | riscv: Enable robust thread dispatch | Sebastian Huber | 2019-01-09 | 1 | -0/+3 |
| | | | | | | | It must be enabled, since the context switch code does not save/restore the interrupt status. Update #3433. | ||||
* | Adjust interrupt mode tests for some CPU ports | Sebastian Huber | 2019-01-09 | 2 | -2/+4 |
| | | | | | | | In case the robust thread dispatch is enabled by the CPU port, then the interrupt level must not be changed through the task mode. Update #3000. |