| Commit message (Collapse) | Author | Age | Files | Lines |
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The use of a hand crafted lock for Per_CPU_Control::Lock was necessary
at some point in the SMP support development, but it is no longer
justified.
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Update #3706
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In case the robust thread dispatch is enabled by the CPU port, then the
interrupt level must not be changed through the task mode.
Update #3000.
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Add support to temporarily pin a thread to its current processor. This
may be used to access per-processor data structures in critical sections
with enabled thread dispatching, e.g. a pinned thread is allowed to
block.
Update #3508.
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This function is slighly too complex for inlining with two if
statements. The caller already needs a stack frame due to the potential
call to _Thread_Do_dispatch(). In _Thread_Dispatch_enable() the call to
_Thread_Do_dispatch() can be optimized to a tail call.
A text size comparision
(text size after patch - text size before patch)
/ text size before patch
on sparc/erc32 with SMP enabled showed these results:
Minimum -0.000697892 (fsdosfsname01.exe)
Median -0.00745021 (psxtimes01.exe)
Maximum -0.0233032 (spscheduler01.exe)
A text size comparision
text size after patch - text size before patch
on sparc/erc32 with SMP enabled showed these results:
Minimum -3312 (ada_sp09.exe)
Median -1024 (tm15.exe)
Maximum -592 (spglobalcon01.exe)
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Update #3060.
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This task variable is superfluous since we use thread-local storage now.
Update #2289.
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Move _Thread_Scheduler_ask_for_help(), rename it to
_Thread_Ask_for_help() and make it static.
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The fatal is internal indicator is redundant since the fatal source and
error code uniquely identify a fatal error. Keep the fatal user
extension is internal parameter for backward compatibility and set it to
false always.
Update #2825.
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On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
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Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
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This function is useful for operations which synchronously block, e.g.
self restart, self deletion, yield, sleep. It helps to detect if these
operations are called in the wrong context. Since the thread dispatch
necessary indicator is not used, this is more robust in some SMP
situations.
Update #2751.
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Update #2556.
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This information turned out to be useless in the last couple of months.
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Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable()
into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant().
This is a preparation to remove the Giant lock.
Update #2555.
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Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename
_ISR_Enable_without_giant() into _ISR_Local_enable().
This is a preparation to remove the Giant lock.
Update #2555.
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Update #2556.
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The CPU time used of a thread was previously maintained per-processor
mostly during _Thread_Dispatch(). However, on SMP configurations the
actual processor of a thread is difficult to figure out since thread
dispatching is a highly asynchronous process (e.g. via inter-processor
interrupts). Only the intended processor of a thread is known to the
scheduler easily. Do the CPU usage accounting during thread heir
updates in the context of the scheduler operations. Provide the
function _Thread_Get_CPU_time_used() to get the CPU usage of a thread
using proper locks to get a consistent value.
Close #2627.
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Delete SCORE_INIT. This finally removes the
some.h:
#ifndef SOME_XYZ_EXTERN
#define SOME_XYZ_EXTERN extern
#endif
SOME_XYZ_EXTERN type xyz;
some_xyz.c:
#define SOME_XYZ_EXTERN
#include <some.h>
pattern in favour of
some.h:
extern type xyz;
some_xyz.c
#include <some.h>
type xyz;
Update #2559.
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Update #2408.
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This function is used by Newlib since 2013-07-09 (Git commit
9b51cd8c6b9cdd067d9648a7ab952884019c56a5).
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This was obsolete and broken based upon recent time keeping changes.
Thie build option was previously enabled by adding
USE_TICKS_FOR_STATISTICS=1 to the configure command line.
This propagated into the code as preprocessor conditionals
using the __RTEMS_USE_TICKS_FOR_STATISTICS__ conditional.
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The _Thread_Dispatch() function is quite complex and the time to set up
and tear down the stack frame is significant. Split this function into
two parts. The complex part is now in _Thread_Do_dispatch(). Call
_Thread_Do_dispatch() in _Thread_Enable_dispatch() only if necessary.
This increases the average case performance.
Simplify _Thread_Handler() for SMP configurations.
Update #2273.
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After a context switch we end up in the second part of
_Thread_Dispatch() or in _Thread_Handler() in case of new threads. Use
the same function _Thread_Restore_fp() to restore the floating-point
context. It makes no sense to do this in _Thread_Start_multitasking().
This fixes also a race condition in SMP configurations.
Update #2268.
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The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
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Use "cpu" for an arbitrary Per_CPU_Control variable.
Use "cpu_self" for the Per_CPU_Control of the current processor.
Use "cpu_index" for an arbitrary processor index.
Use "cpu_index_self" for the processor index of the current processor.
Use "cpu_count" for the processor count obtained via
_SMP_Get_processor_count().
Use "cpu_max" for the processor maximum obtained by
rtems_configuration_get_maximum_processors().
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The _Scheduler_SMP_Allocate_processor() and _Thread_Dispatch() exchange
information without locks. Make sure we use the right load/store
ordering.
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Use the Configuration instead.
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Use thread post-switch actions instead.
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Thread actions are the building block for efficient implementation of
- Classic signals delivery,
- POSIX signals delivery,
- thread restart notification,
- thread delete notification,
- forced thread migration on SMP configurations, and
- the Multiprocessor Resource Sharing Protocol (MrsP).
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Add per-CPU profiling stats API. Implement the thread dispatch disable
level profiling. The interrupt profiling must be implemented in CPU
port specific parts (mostly assembler code). Add a support function
_Profiling_Outer_most_interrupt_entry_and_exit() for this purpose.
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It is not necessary to load the executing thread control again after
the context switch since it is an invariant of the executing thread.
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Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
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Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
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Fix _times().
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Use an event triggered unicast to inform remote processors about a
necessary thread dispatch instead.
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If we enter _Thread_Dispatch() then _Thread_Dispatch_disable_level must
be zero. Single processor RTEMS assumes that stores of non-zero values
to _Thread_Dispatch_disable_level are observed by interrupts as non-zero values.
Move the _Thread_Dispatch_set_disable_level( 1 ) out of the first ISR
disabled critical section. In case interrupts happen between the
_Thread_Dispatch_set_disable_level( 1 ) and _ISR_Disable( level ) then
the interrupt will observe a non-zero _Thread_Dispatch_disable_level and
will not issue a _Thread_Dispatch() and we can enter the ISR disabled
section directly after interrupt processing.
This change leads to symmetry between the single processor and SMP
configuration.
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Move implementation specific parts of thread.h and thread.inl into new
header file threadimpl.h. The thread.h contains now only the
application visible API.
Remove superfluous header file includes from various files.
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Delete _Thread_libc_reent and add __getreent() instead according to
__DYNAMIC_REENT__ define.
For SMP configurations __DYNAMIC_REENT__ must be defined.
A Newlib including the following patch is required:
2013-07-09 Sebastian Huber <sebastian.huber@embedded-brains.de>
* libc/include/sys/config.h (__DYNAMIC_REENT__): Define for RTEMS.
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The new Simple SMP Scheduler allocates a processor for the processor
count highest priority ready threads. The thread priority and position
in the ready chain are the only information to determine the scheduling
decision. Threads with an allocated processor are in the scheduled
chain. After initialization the scheduled chain has exactly processor
count nodes. Each processor has exactly one allocated thread after
initialization. All enqueue and extract operations may exchange threads
with the scheduled chain. One thread will be added and another will be
removed. The scheduled and ready chain is ordered according to the
thread priority order. The chain insert operations are O(count of ready
threads), thus this scheduler is unsuitable for most real-time
applications.
The thread preempt mode will be ignored.
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Move thread dispatch declarations and inline functions to new header
<rtems/score/threaddispatch.h> to make it independent of the
Thread_Control structure. This avoids a cyclic dependency in case
thread dispatch functions are used for the object implementation.
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Move post switch hook from API_extensions_Control to new
API_extensions_Post_switch_control. Rename
_API_extensions_Run_postswitch() in _API_extensions_Run_post_switch().
Add _API_extensions_Post_switch_list and
_API_extensions_Add_post_switch().
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This patch is a task from GCI 2012 which improves the Doxygen
comments in the RTEMS source.
http://www.google-melange.com/gci/task/view/google/gci2012/7985215
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The _API_extensions_Run_postswitch() function is only used in
_Thread_Dispatch(). Avoid superfluous load of _Thread_Executing.
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This file contains the parts of <rtems/score/userext.h> that are only
necessary for the RTEMS implementation.
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