summaryrefslogtreecommitdiffstats
path: root/cpukit/score/cpu/sparc (follow)
Commit message (Collapse)AuthorAgeFilesLines
...
* score: Remove CPU_PROVIDES_IDLE_THREAD_BODYSebastian Huber2018-10-052-17/+4
| | | | | | | Remove the CPU_PROVIDES_IDLE_THREAD_BODY option to avoid unnecessary conditional compilation. Close #3539.
* Rename files to make them unique within cpukitSebastian Huber2018-10-042-1/+1
| | | | This allows to build librtemscpu.a in one rush in the future.
* sparc: clang AS does no accept UNIMP without argumentDaniel Hellstrom2018-09-201-1/+1
|
* sparc: Remove sequence that could trigger B2BST errataDaniel Cederman2018-09-201-2/+0
|
* sparc: Return to previous section type when done with .data._SPARC_CounterDaniel Cederman2018-09-201-0/+1
|
* sparc: Restore npc when returning from the syscall_lazy_fp_switch trapDaniel Cederman2018-08-241-1/+1
| | | | | If the floating point trap occurred in a delay slot it is not certain that npc will be equal to pc + 4.
* score: Remove CPU_PARTITION_ALIGNMENTSebastian Huber2018-08-021-13/+0
| | | | | | | | | | | | | | Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment requirement is defined by the use of Chain_Node (consisting of two pointers) to manage the free chain of partitions. It seems that previously the condition CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node) was true on all CPU ports. Now, we need an additional check. Update #3482.
* score: Add _CPU_Instruction_illegal()Sebastian Huber2018-07-231-0/+5
| | | | | | | | On some architectures/simulators it is difficult to provoke an exception with misaligned or illegal data loads. Use an illegal instruction instead. Update #3433.
* score: Add _CPU_Instruction_no_operation()Sebastian Huber2018-07-201-0/+5
| | | | | This helps to reduce the use of architecture-specific defines throughout the code base.
* score: Move context validation declarationsSebastian Huber2018-07-202-4/+4
| | | | | | | The context validation support functions _CPU_Context_validate() and _CPU_Context_volatile_clobber() are used only by one test program (spcontext01). Move the function declarations to the CPU port implementation header file.
* Rework initialization and interrupt stack supportSebastian Huber2018-06-271-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statically initialize the interrupt stack area (_Configuration_Interrupt_stack_area_begin, _Configuration_Interrupt_stack_area_end, and _Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the interrupt stack area in a special section ".rtemsstack.interrupt". Let BSPs define the optimal placement of this section in their linker command files (e.g. in a fast on-chip memory). This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the low level initialization code has all information available via global symbols. This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define superfluous, since the interrupt stacks are allocated by confdefs.h for all architectures. There is no need for BSP-specific linker command file magic (except the section placement), see previous ARM linker command file as a bad example. Remove _CPU_Install_interrupt_stack(). Initialize the hardware interrupt stack in _CPU_Initialize() if necessary (e.g. m68k_install_interrupt_stack()). The optional _CPU_Interrupt_stack_setup() is still useful to customize the registration of the interrupt stack area in the per-CPU information. The initialization stack can reuse the interrupt stack, since * interrupts are disabled during the sequential system initialization, and * the boot_card() function does not return. This stack resuse saves memory. Changes per architecture: arm: * Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases. * Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp. bfin: * Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value. lm32, m32c, mips, nios2, riscv, sh, v850: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. m68k: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. powerpc: * Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack. * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA). sparc: * Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM. Update #3459.
* score: Add CPU_INTERRUPT_STACK_ALIGNMENTSebastian Huber2018-06-271-0/+2
| | | | | | | Add CPU port define for the interrupt stack alignment. The alignment should take the stack ABI and the cache line size into account. Update #3459.
* Add _CPU_Counter_frequency()Sebastian Huber2018-06-151-0/+2
| | | | | | | | | | Add rtems_counter_frequency() API function. Use it to initialize the counter value converter via the new system initialization step (RTEMS_SYSINIT_CPU_COUNTER). This decouples the counter implementation and the counter converter. It avoids an unnecessary pull in of the 64-bit integer division from libgcc. Update #3456.
* sparc: Move irq_asm.SSebastian Huber2018-04-202-0/+904
| | | | | | | | This file is BSP-independent. This patch is a part of the BSP source reorganization. Update #3285.
* sparc: Move _CPU_Trap_slot_templateSebastian Huber2018-04-201-0/+16
| | | | | | | | | The definition of _CPU_Trap_slot_template is BSP-independent. A potential para-virtualization support may use <rtems/score/paravirt.h>. This patch is a part of the BSP source reorganization. Update #3285.
* Remove register keyword from public header filesSebastian Huber2018-04-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following code void f(void) { register int i; } gives a warning with GCC and -std=c++17 test.cc: In function ‘void f()’: test.cc:3:15: warning: ISO C++1z does not allow ‘register’ storage class specifier [-Wregister] register int i; ^ and clang with -std=c++14 test.cc:3:3: warning: 'register' storage class specifier is deprecated and incompatible with C++1z [-Wdeprecated-register] register int i; ^~~~~~~~~ 1 warning generated. Remove the use of the register keyword at least in the public header files for C++ compatibility. Close #3397.
* sparc: Move libcpu content to cpukitSebastian Huber2018-03-138-4/+756
| | | | | | This patch is a part of the BSP source reorganization. Update #3285.
* sparc/include/rtems/score/types.h: Eliminate this fileJoel Sherrill2018-03-124-56/+5
| | | | Updates #3327.
* Remove make preinstallChris Johns2018-01-2511-77/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
* sparc: Move <libcpu/byteorder.h>Sebastian Huber2018-01-023-0/+78
| | | | | Update #3254. Update #3260.
* sparc: Add lazy floating point switchSebastian Huber2017-07-256-219/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPARC ABI is a bit special with respect to the floating point context. The complete floating point context is volatile. Thus, from an ABI point of view nothing needs to be saved and restored during a context switch. Instead the floating point context must be saved and restored during interrupt processing. Historically, the deferred floating point switch was used for SPARC and the complete floating point context is saved and restored during a context switch to the new floating point unit owner. This is a bit dangerous since post-switch actions (e.g. signal handlers) and context switch extensions may silently corrupt the floating point context. The floating point unit is disabled for interrupt handlers. Thus, in case an interrupt handler uses the floating point unit then this will result in a trap (INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT). In uniprocessor configurations, a lazy floating point context switch is used. In case an active floating point thread is interrupted (PSR[EF] == 1) and a thread dispatch is carried out, then this thread is registered as the floating point owner. When a floating point owner is present during a context switch, the floating point unit is disabled for the heir thread (PSR[EF] == 0). The floating point disabled trap checks that the use of the floating point unit is allowed and saves/restores the floating point context on demand. Update #3077.
* sparc: Rename SPARC_USE_SAFE_FP_SUPPORTSebastian Huber2017-07-253-28/+30
| | | | | | | Rename SPARC_USE_SAFE_FP_SUPPORT in SPARC_USE_SYNCHRONOUS_FP_SWITCH. Update comment. Update #3077.
* sparc: Add assembly workaround for LEON3FT B2BST errataDaniel Cederman2017-07-173-0/+33
| | | | | | | | | | | | | | | This patch adds NOP instructions to prevent instruction sequences that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error" for more information. The sequences are only modified if __FIX_LEON3FT_B2BST is defined. The patch works in conjunction with the -mfix-ut700, -mfix-gr712rc, and -mfix-ut699 GCC flags that prevents the sensitive sequences from being generated. Update #3057.
* sparc: Fix volatile clobberSebastian Huber2017-02-031-1/+1
| | | | | | | Do not adjust the stack pointer, since this is already done by the restor instruction. Update #2270.
* score: Delete _CPU_Context_Fp_start()Sebastian Huber2017-01-261-7/+0
| | | | | | | | | | Since the FP area pointer is passed by reference in _CPU_Context_Initialize_fp() the optional FP area adjustment via _CPU_Context_Fp_start() is superfluous. It is also wrong with respect to memory management, e.g. pointer passed to _Workspace_Free() may be not the one returned by _Workspace_Allocate(). Close #1400.
* sparc: Relax CPU_STACK_ALIGNMENTSebastian Huber2017-01-241-12/+3
| | | | Close #2352.
* Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIANSebastian Huber2017-01-241-16/+0
| | | | | | Use de-facto standard BYTE_ORDER instead. Close #2803.
* sparc: Optimize _ISR_Handler()Sebastian Huber2016-11-281-0/+3
| | | | | | Use _Thread_Do_dispatch() instead of _Thread_Dispatch(). Restore the PSR[EF] state of the interrupted context via new system call syscall_irqdis_fp in case floating-point support is enabled.
* score: Robust thread dispatchSebastian Huber2016-11-231-0/+2
| | | | | | | | | | | | On SMP configurations, it is a fatal error to call blocking operating system with interrupts disabled, since this prevents delivery of inter-processor interrupts. This could lead to executing threads which are not allowed to execute resulting in undefined behaviour. The ARM Cortex-M port has a similar problem, since the interrupt state is not a part of the thread context. Update #2811.
* score: Add _ISR_Is_enabled()Sebastian Huber2016-11-181-0/+8
| | | | | | | In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
* sparc: Use Per_CPU_Control::isr_dispatch_disableSebastian Huber2016-11-182-22/+5
| | | | Update #2751.
* score: Add Per_CPU_Control::Interrupt_frameSebastian Huber2016-11-181-5/+0
| | | | Update #2809.
* sparc: Move CPU_Interrupt_frame related definesSebastian Huber2016-11-185-54/+58
| | | | | | Move CPU_Interrupt_frame related defines to <rtems/score/cpuimpl.h>. Update #2809.
* sparc: Rename CPU_Minimum_stack_frameSebastian Huber2016-11-184-26/+26
| | | | | | | | Rename SPARC-specific CPU_Minimum_stack_frame to SPARC_Minimum_stack_frame. Rename SPARC-specific CPU_MINIMUM_STACK_FRAME_SIZE to SPARC_MINIMUM_STACK_FRAME_SIZE. Update #2809.
* rtems: Conditionally define rtems_interrupt_frameSebastian Huber2016-11-181-1/+1
| | | | Update #2808.
* score: Move CPU_PER_CPU_CONTROL_SIZESebastian Huber2016-11-182-42/+43
| | | | | Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to <rtems/score/cpuimpl.h> to hide it from <rtems.h>.
* score: Remove obsolete definesSebastian Huber2016-11-181-10/+0
| | | | The thread dispatch inline option is no longer used.
* score: Move _CPU_Get_current_per_CPU_control()Sebastian Huber2016-11-102-9/+9
| | | | | Move _CPU_Get_current_per_CPU_control() from <rtems/score/cpu.h> to <rtems/score/cpuimpl.h>.
* sparc: Provide _CPU_Get_thread_executing()Sebastian Huber2016-11-071-0/+4
|
* score: Add <rtems/score/cpuimpl.h>Sebastian Huber2016-11-073-0/+35
| | | | | | The aim of this file is to encapsulate CPU port implementation details. This helps to hide implementation details from <rtems.h> which indirectly includes <rtems/score/cpu.h>.
* sparc: Optimize CPU counter supportSebastian Huber2016-06-225-38/+98
|
* sparc: Rework CPU counter supportSebastian Huber2016-06-214-26/+88
| | | | | Rework CPU counter support to enable use of the GR740 up-counter via %asr22 and %asr23.
* score: Simplify priority bit map implementationSebastian Huber2016-06-081-9/+0
| | | | | | | | | | The priority bit map can deal with a maximum of 256 priority values ranging from 0 to 255. Consistently use an unsigned int for computation, due to the usual integer promotion rules. Make Priority_bit_map_Word definition architecture-independent and define it to uint16_t. This was already the case for all architectures except PowerPC. Adjust the PowerPC bitmap support accordingly.
* score: Delete CPU_USE_GENERIC_BITFIELD_DATASebastian Huber2016-06-081-6/+0
| | | | | | Rename __log2table into _Bitfield_Leading_zeros since it acually returns the count of leading zeros of an 8-bit integer. The value for zero is a bit odd. Provide it unconditionally.
* score: Add libatomic supportSebastian Huber2016-05-302-212/+0
| | | | Close #2695.
* score: Rename _ISR_Disable_without_giant()Sebastian Huber2016-05-201-2/+2
| | | | | | | | | Rename _ISR_Disable_without_giant() into _ISR_Local_disable(). Rename _ISR_Enable_without_giant() into _ISR_Local_enable(). This is a preparation to remove the Giant lock. Update #2555.
* score: Add CPU_MAXIMUM_PROCESSORSSebastian Huber2016-03-041-0/+2
| | | | Maximum number of processors of all systems supported by this CPU port.
* sparc: Avoid SCORE_EXTERNSebastian Huber2016-02-172-1/+5
| | | | Update #2559.
* sparc: Adjust CPU_CACHE_LINE_BYTES for LEON3Sebastian Huber2016-01-261-2/+2
| | | | Fix for commit a8865f8b415788c4e9bb7f68e38d41aec0e485db.
* score: Introduce CPU_CACHE_LINE_BYTESSebastian Huber2016-01-261-11/+4
| | | | | Add CPU_CACHE_LINE_BYTES for the maximum cache line size in bytes. The actual processor may use no cache or a smaller cache line size.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 20:38:07 +0000